2 * QEMU Sun4u/Sun4v System Emulator
4 * Copyright (c) 2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
31 #include "qemu-timer.h"
34 #include "firmware_abi.h"
41 #include "exec-memory.h"
48 #define CPUIRQ_DPRINTF(fmt, ...) \
49 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
51 #define CPUIRQ_DPRINTF(fmt, ...)
55 #define EBUS_DPRINTF(fmt, ...) \
56 do { printf("EBUS: " fmt , ## __VA_ARGS__); } while (0)
58 #define EBUS_DPRINTF(fmt, ...)
62 #define TIMER_DPRINTF(fmt, ...) \
63 do { printf("TIMER: " fmt , ## __VA_ARGS__); } while (0)
65 #define TIMER_DPRINTF(fmt, ...)
68 #define KERNEL_LOAD_ADDR 0x00404000
69 #define CMDLINE_ADDR 0x003ff000
70 #define INITRD_LOAD_ADDR 0x00300000
71 #define PROM_SIZE_MAX (4 * 1024 * 1024)
72 #define PROM_VADDR 0x000ffd00000ULL
73 #define APB_SPECIAL_BASE 0x1fe00000000ULL
74 #define APB_MEM_BASE 0x1ff00000000ULL
75 #define APB_PCI_IO_BASE (APB_SPECIAL_BASE + 0x02000000ULL)
76 #define PROM_FILENAME "openbios-sparc64"
77 #define NVRAM_SIZE 0x2000
79 #define BIOS_CFG_IOPORT 0x510
80 #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
81 #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
82 #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
86 #define TICK_MAX 0x7fffffffffffffffULL
89 const char * const default_cpu_model
;
92 uint64_t console_serial_base
;
95 typedef struct EbusState
{
101 int DMA_get_channel_mode (int nchan
)
105 int DMA_read_memory (int nchan
, void *buf
, int pos
, int size
)
109 int DMA_write_memory (int nchan
, void *buf
, int pos
, int size
)
113 void DMA_hold_DREQ (int nchan
) {}
114 void DMA_release_DREQ (int nchan
) {}
115 void DMA_schedule(int nchan
) {}
117 void DMA_init(int high_page_enable
, qemu_irq
*cpu_request_exit
)
121 void DMA_register_channel (int nchan
,
122 DMA_transfer_handler transfer_handler
,
127 static int fw_cfg_boot_set(void *opaque
, const char *boot_device
)
129 fw_cfg_add_i16(opaque
, FW_CFG_BOOT_DEVICE
, boot_device
[0]);
133 static int sun4u_NVRAM_set_params(M48t59State
*nvram
, uint16_t NVRAM_size
,
134 const char *arch
, ram_addr_t RAM_size
,
135 const char *boot_devices
,
136 uint32_t kernel_image
, uint32_t kernel_size
,
138 uint32_t initrd_image
, uint32_t initrd_size
,
139 uint32_t NVRAM_image
,
140 int width
, int height
, int depth
,
141 const uint8_t *macaddr
)
145 uint8_t image
[0x1ff0];
146 struct OpenBIOS_nvpart_v1
*part_header
;
148 memset(image
, '\0', sizeof(image
));
152 // OpenBIOS nvram variables
153 // Variable partition
154 part_header
= (struct OpenBIOS_nvpart_v1
*)&image
[start
];
155 part_header
->signature
= OPENBIOS_PART_SYSTEM
;
156 pstrcpy(part_header
->name
, sizeof(part_header
->name
), "system");
158 end
= start
+ sizeof(struct OpenBIOS_nvpart_v1
);
159 for (i
= 0; i
< nb_prom_envs
; i
++)
160 end
= OpenBIOS_set_var(image
, end
, prom_envs
[i
]);
165 end
= start
+ ((end
- start
+ 15) & ~15);
166 OpenBIOS_finish_partition(part_header
, end
- start
);
170 part_header
= (struct OpenBIOS_nvpart_v1
*)&image
[start
];
171 part_header
->signature
= OPENBIOS_PART_FREE
;
172 pstrcpy(part_header
->name
, sizeof(part_header
->name
), "free");
175 OpenBIOS_finish_partition(part_header
, end
- start
);
177 Sun_init_header((struct Sun_nvram
*)&image
[0x1fd8], macaddr
, 0x80);
179 for (i
= 0; i
< sizeof(image
); i
++)
180 m48t59_write(nvram
, i
, image
[i
]);
184 static unsigned long sun4u_load_kernel(const char *kernel_filename
,
185 const char *initrd_filename
,
186 ram_addr_t RAM_size
, long *initrd_size
)
193 linux_boot
= (kernel_filename
!= NULL
);
204 kernel_size
= load_elf(kernel_filename
, NULL
, NULL
, NULL
,
205 NULL
, NULL
, 1, ELF_MACHINE
, 0);
207 kernel_size
= load_aout(kernel_filename
, KERNEL_LOAD_ADDR
,
208 RAM_size
- KERNEL_LOAD_ADDR
, bswap_needed
,
211 kernel_size
= load_image_targphys(kernel_filename
,
213 RAM_size
- KERNEL_LOAD_ADDR
);
214 if (kernel_size
< 0) {
215 fprintf(stderr
, "qemu: could not load kernel '%s'\n",
222 if (initrd_filename
) {
223 *initrd_size
= load_image_targphys(initrd_filename
,
225 RAM_size
- INITRD_LOAD_ADDR
);
226 if (*initrd_size
< 0) {
227 fprintf(stderr
, "qemu: could not load initial ram disk '%s'\n",
232 if (*initrd_size
> 0) {
233 for (i
= 0; i
< 64 * TARGET_PAGE_SIZE
; i
+= TARGET_PAGE_SIZE
) {
234 ptr
= rom_ptr(KERNEL_LOAD_ADDR
+ i
);
235 if (ldl_p(ptr
+ 8) == 0x48647253) { /* HdrS */
236 stl_p(ptr
+ 24, INITRD_LOAD_ADDR
+ KERNEL_LOAD_ADDR
- 0x4000);
237 stl_p(ptr
+ 28, *initrd_size
);
246 void cpu_check_irqs(CPUSPARCState
*env
)
248 uint32_t pil
= env
->pil_in
|
249 (env
->softint
& ~(SOFTINT_TIMER
| SOFTINT_STIMER
));
251 /* TT_IVEC has a higher priority (16) than TT_EXTINT (31..17) */
252 if (env
->ivec_status
& 0x20) {
255 /* check if TM or SM in SOFTINT are set
256 setting these also causes interrupt 14 */
257 if (env
->softint
& (SOFTINT_TIMER
| SOFTINT_STIMER
)) {
261 /* The bit corresponding to psrpil is (1<< psrpil), the next bit
263 if (pil
< (2 << env
->psrpil
)){
264 if (env
->interrupt_request
& CPU_INTERRUPT_HARD
) {
265 CPUIRQ_DPRINTF("Reset CPU IRQ (current interrupt %x)\n",
266 env
->interrupt_index
);
267 env
->interrupt_index
= 0;
268 cpu_reset_interrupt(env
, CPU_INTERRUPT_HARD
);
273 if (cpu_interrupts_enabled(env
)) {
277 for (i
= 15; i
> env
->psrpil
; i
--) {
278 if (pil
& (1 << i
)) {
279 int old_interrupt
= env
->interrupt_index
;
280 int new_interrupt
= TT_EXTINT
| i
;
282 if (unlikely(env
->tl
> 0 && cpu_tsptr(env
)->tt
> new_interrupt
283 && ((cpu_tsptr(env
)->tt
& 0x1f0) == TT_EXTINT
))) {
284 CPUIRQ_DPRINTF("Not setting CPU IRQ: TL=%d "
285 "current %x >= pending %x\n",
286 env
->tl
, cpu_tsptr(env
)->tt
, new_interrupt
);
287 } else if (old_interrupt
!= new_interrupt
) {
288 env
->interrupt_index
= new_interrupt
;
289 CPUIRQ_DPRINTF("Set CPU IRQ %d old=%x new=%x\n", i
,
290 old_interrupt
, new_interrupt
);
291 cpu_interrupt(env
, CPU_INTERRUPT_HARD
);
296 } else if (env
->interrupt_request
& CPU_INTERRUPT_HARD
) {
297 CPUIRQ_DPRINTF("Interrupts disabled, pil=%08x pil_in=%08x softint=%08x "
298 "current interrupt %x\n",
299 pil
, env
->pil_in
, env
->softint
, env
->interrupt_index
);
300 env
->interrupt_index
= 0;
301 cpu_reset_interrupt(env
, CPU_INTERRUPT_HARD
);
305 static void cpu_kick_irq(CPUSPARCState
*env
)
312 static void cpu_set_ivec_irq(void *opaque
, int irq
, int level
)
314 CPUSPARCState
*env
= opaque
;
317 if (!(env
->ivec_status
& 0x20)) {
318 CPUIRQ_DPRINTF("Raise IVEC IRQ %d\n", irq
);
320 env
->interrupt_index
= TT_IVEC
;
321 env
->ivec_status
|= 0x20;
322 env
->ivec_data
[0] = (0x1f << 6) | irq
;
323 env
->ivec_data
[1] = 0;
324 env
->ivec_data
[2] = 0;
325 cpu_interrupt(env
, CPU_INTERRUPT_HARD
);
328 if (env
->ivec_status
& 0x20) {
329 CPUIRQ_DPRINTF("Lower IVEC IRQ %d\n", irq
);
330 env
->ivec_status
&= ~0x20;
331 cpu_reset_interrupt(env
, CPU_INTERRUPT_HARD
);
336 typedef struct ResetData
{
341 void cpu_put_timer(QEMUFile
*f
, CPUTimer
*s
)
343 qemu_put_be32s(f
, &s
->frequency
);
344 qemu_put_be32s(f
, &s
->disabled
);
345 qemu_put_be64s(f
, &s
->disabled_mask
);
346 qemu_put_sbe64s(f
, &s
->clock_offset
);
348 qemu_put_timer(f
, s
->qtimer
);
351 void cpu_get_timer(QEMUFile
*f
, CPUTimer
*s
)
353 qemu_get_be32s(f
, &s
->frequency
);
354 qemu_get_be32s(f
, &s
->disabled
);
355 qemu_get_be64s(f
, &s
->disabled_mask
);
356 qemu_get_sbe64s(f
, &s
->clock_offset
);
358 qemu_get_timer(f
, s
->qtimer
);
361 static CPUTimer
* cpu_timer_create(const char* name
, CPUSPARCState
*env
,
362 QEMUBHFunc
*cb
, uint32_t frequency
,
363 uint64_t disabled_mask
)
365 CPUTimer
*timer
= g_malloc0(sizeof (CPUTimer
));
368 timer
->frequency
= frequency
;
369 timer
->disabled_mask
= disabled_mask
;
372 timer
->clock_offset
= qemu_get_clock_ns(vm_clock
);
374 timer
->qtimer
= qemu_new_timer_ns(vm_clock
, cb
, env
);
379 static void cpu_timer_reset(CPUTimer
*timer
)
382 timer
->clock_offset
= qemu_get_clock_ns(vm_clock
);
384 qemu_del_timer(timer
->qtimer
);
387 static void main_cpu_reset(void *opaque
)
389 ResetData
*s
= (ResetData
*)opaque
;
390 CPUSPARCState
*env
= s
->env
;
391 static unsigned int nr_resets
;
393 cpu_state_reset(env
);
395 cpu_timer_reset(env
->tick
);
396 cpu_timer_reset(env
->stick
);
397 cpu_timer_reset(env
->hstick
);
399 env
->gregs
[1] = 0; // Memory start
400 env
->gregs
[2] = ram_size
; // Memory size
401 env
->gregs
[3] = 0; // Machine description XXX
402 if (nr_resets
++ == 0) {
404 env
->pc
= s
->prom_addr
+ 0x20ULL
;
406 env
->pc
= s
->prom_addr
+ 0x40ULL
;
408 env
->npc
= env
->pc
+ 4;
411 static void tick_irq(void *opaque
)
413 CPUSPARCState
*env
= opaque
;
415 CPUTimer
* timer
= env
->tick
;
417 if (timer
->disabled
) {
418 CPUIRQ_DPRINTF("tick_irq: softint disabled\n");
421 CPUIRQ_DPRINTF("tick: fire\n");
424 env
->softint
|= SOFTINT_TIMER
;
428 static void stick_irq(void *opaque
)
430 CPUSPARCState
*env
= opaque
;
432 CPUTimer
* timer
= env
->stick
;
434 if (timer
->disabled
) {
435 CPUIRQ_DPRINTF("stick_irq: softint disabled\n");
438 CPUIRQ_DPRINTF("stick: fire\n");
441 env
->softint
|= SOFTINT_STIMER
;
445 static void hstick_irq(void *opaque
)
447 CPUSPARCState
*env
= opaque
;
449 CPUTimer
* timer
= env
->hstick
;
451 if (timer
->disabled
) {
452 CPUIRQ_DPRINTF("hstick_irq: softint disabled\n");
455 CPUIRQ_DPRINTF("hstick: fire\n");
458 env
->softint
|= SOFTINT_STIMER
;
462 static int64_t cpu_to_timer_ticks(int64_t cpu_ticks
, uint32_t frequency
)
464 return muldiv64(cpu_ticks
, get_ticks_per_sec(), frequency
);
467 static uint64_t timer_to_cpu_ticks(int64_t timer_ticks
, uint32_t frequency
)
469 return muldiv64(timer_ticks
, frequency
, get_ticks_per_sec());
472 void cpu_tick_set_count(CPUTimer
*timer
, uint64_t count
)
474 uint64_t real_count
= count
& ~timer
->disabled_mask
;
475 uint64_t disabled_bit
= count
& timer
->disabled_mask
;
477 int64_t vm_clock_offset
= qemu_get_clock_ns(vm_clock
) -
478 cpu_to_timer_ticks(real_count
, timer
->frequency
);
480 TIMER_DPRINTF("%s set_count count=0x%016lx (%s) p=%p\n",
481 timer
->name
, real_count
,
482 timer
->disabled
?"disabled":"enabled", timer
);
484 timer
->disabled
= disabled_bit
? 1 : 0;
485 timer
->clock_offset
= vm_clock_offset
;
488 uint64_t cpu_tick_get_count(CPUTimer
*timer
)
490 uint64_t real_count
= timer_to_cpu_ticks(
491 qemu_get_clock_ns(vm_clock
) - timer
->clock_offset
,
494 TIMER_DPRINTF("%s get_count count=0x%016lx (%s) p=%p\n",
495 timer
->name
, real_count
,
496 timer
->disabled
?"disabled":"enabled", timer
);
499 real_count
|= timer
->disabled_mask
;
504 void cpu_tick_set_limit(CPUTimer
*timer
, uint64_t limit
)
506 int64_t now
= qemu_get_clock_ns(vm_clock
);
508 uint64_t real_limit
= limit
& ~timer
->disabled_mask
;
509 timer
->disabled
= (limit
& timer
->disabled_mask
) ? 1 : 0;
511 int64_t expires
= cpu_to_timer_ticks(real_limit
, timer
->frequency
) +
518 TIMER_DPRINTF("%s set_limit limit=0x%016lx (%s) p=%p "
519 "called with limit=0x%016lx at 0x%016lx (delta=0x%016lx)\n",
520 timer
->name
, real_limit
,
521 timer
->disabled
?"disabled":"enabled",
523 timer_to_cpu_ticks(now
- timer
->clock_offset
,
525 timer_to_cpu_ticks(expires
- now
, timer
->frequency
));
528 TIMER_DPRINTF("%s set_limit limit=ZERO - not starting timer\n",
530 qemu_del_timer(timer
->qtimer
);
531 } else if (timer
->disabled
) {
532 qemu_del_timer(timer
->qtimer
);
534 qemu_mod_timer(timer
->qtimer
, expires
);
538 static void isa_irq_handler(void *opaque
, int n
, int level
)
540 static const int isa_irq_to_ivec
[16] = {
541 [1] = 0x29, /* keyboard */
542 [4] = 0x2b, /* serial */
543 [6] = 0x27, /* floppy */
544 [7] = 0x22, /* parallel */
545 [12] = 0x2a, /* mouse */
547 qemu_irq
*irqs
= opaque
;
551 ivec
= isa_irq_to_ivec
[n
];
552 EBUS_DPRINTF("Set ISA IRQ %d level %d -> ivec 0x%x\n", n
, level
, ivec
);
554 qemu_set_irq(irqs
[ivec
], level
);
558 /* EBUS (Eight bit bus) bridge */
560 pci_ebus_init(PCIBus
*bus
, int devfn
, qemu_irq
*irqs
)
566 pci_dev
= pci_create_simple(bus
, devfn
, "ebus");
567 isa_bus
= DO_UPCAST(ISABus
, qbus
,
568 qdev_get_child_bus(&pci_dev
->qdev
, "isa.0"));
569 isa_irq
= qemu_allocate_irqs(isa_irq_handler
, irqs
, 16);
570 isa_bus_irqs(isa_bus
, isa_irq
);
575 pci_ebus_init1(PCIDevice
*pci_dev
)
577 EbusState
*s
= DO_UPCAST(EbusState
, pci_dev
, pci_dev
);
579 isa_bus_new(&pci_dev
->qdev
, pci_address_space_io(pci_dev
));
581 pci_dev
->config
[0x04] = 0x06; // command = bus master, pci mem
582 pci_dev
->config
[0x05] = 0x00;
583 pci_dev
->config
[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
584 pci_dev
->config
[0x07] = 0x03; // status = medium devsel
585 pci_dev
->config
[0x09] = 0x00; // programming i/f
586 pci_dev
->config
[0x0D] = 0x0a; // latency_timer
588 isa_mmio_setup(&s
->bar0
, 0x1000000);
589 pci_register_bar(pci_dev
, 0, PCI_BASE_ADDRESS_SPACE_MEMORY
, &s
->bar0
);
590 isa_mmio_setup(&s
->bar1
, 0x800000);
591 pci_register_bar(pci_dev
, 1, PCI_BASE_ADDRESS_SPACE_MEMORY
, &s
->bar1
);
595 static void ebus_class_init(ObjectClass
*klass
, void *data
)
597 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
599 k
->init
= pci_ebus_init1
;
600 k
->vendor_id
= PCI_VENDOR_ID_SUN
;
601 k
->device_id
= PCI_DEVICE_ID_SUN_EBUS
;
603 k
->class_id
= PCI_CLASS_BRIDGE_OTHER
;
606 static TypeInfo ebus_info
= {
608 .parent
= TYPE_PCI_DEVICE
,
609 .instance_size
= sizeof(EbusState
),
610 .class_init
= ebus_class_init
,
613 typedef struct PROMState
{
618 static uint64_t translate_prom_address(void *opaque
, uint64_t addr
)
620 target_phys_addr_t
*base_addr
= (target_phys_addr_t
*)opaque
;
621 return addr
+ *base_addr
- PROM_VADDR
;
624 /* Boot PROM (OpenBIOS) */
625 static void prom_init(target_phys_addr_t addr
, const char *bios_name
)
632 dev
= qdev_create(NULL
, "openprom");
633 qdev_init_nofail(dev
);
634 s
= sysbus_from_qdev(dev
);
636 sysbus_mmio_map(s
, 0, addr
);
639 if (bios_name
== NULL
) {
640 bios_name
= PROM_FILENAME
;
642 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
644 ret
= load_elf(filename
, translate_prom_address
, &addr
,
645 NULL
, NULL
, NULL
, 1, ELF_MACHINE
, 0);
646 if (ret
< 0 || ret
> PROM_SIZE_MAX
) {
647 ret
= load_image_targphys(filename
, addr
, PROM_SIZE_MAX
);
653 if (ret
< 0 || ret
> PROM_SIZE_MAX
) {
654 fprintf(stderr
, "qemu: could not load prom '%s'\n", bios_name
);
659 static int prom_init1(SysBusDevice
*dev
)
661 PROMState
*s
= FROM_SYSBUS(PROMState
, dev
);
663 memory_region_init_ram(&s
->prom
, "sun4u.prom", PROM_SIZE_MAX
);
664 vmstate_register_ram_global(&s
->prom
);
665 memory_region_set_readonly(&s
->prom
, true);
666 sysbus_init_mmio(dev
, &s
->prom
);
670 static Property prom_properties
[] = {
671 {/* end of property list */},
674 static void prom_class_init(ObjectClass
*klass
, void *data
)
676 DeviceClass
*dc
= DEVICE_CLASS(klass
);
677 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
679 k
->init
= prom_init1
;
680 dc
->props
= prom_properties
;
683 static TypeInfo prom_info
= {
685 .parent
= TYPE_SYS_BUS_DEVICE
,
686 .instance_size
= sizeof(PROMState
),
687 .class_init
= prom_class_init
,
691 typedef struct RamDevice
699 static int ram_init1(SysBusDevice
*dev
)
701 RamDevice
*d
= FROM_SYSBUS(RamDevice
, dev
);
703 memory_region_init_ram(&d
->ram
, "sun4u.ram", d
->size
);
704 vmstate_register_ram_global(&d
->ram
);
705 sysbus_init_mmio(dev
, &d
->ram
);
709 static void ram_init(target_phys_addr_t addr
, ram_addr_t RAM_size
)
716 dev
= qdev_create(NULL
, "memory");
717 s
= sysbus_from_qdev(dev
);
719 d
= FROM_SYSBUS(RamDevice
, s
);
721 qdev_init_nofail(dev
);
723 sysbus_mmio_map(s
, 0, addr
);
726 static Property ram_properties
[] = {
727 DEFINE_PROP_UINT64("size", RamDevice
, size
, 0),
728 DEFINE_PROP_END_OF_LIST(),
731 static void ram_class_init(ObjectClass
*klass
, void *data
)
733 DeviceClass
*dc
= DEVICE_CLASS(klass
);
734 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
737 dc
->props
= ram_properties
;
740 static TypeInfo ram_info
= {
742 .parent
= TYPE_SYS_BUS_DEVICE
,
743 .instance_size
= sizeof(RamDevice
),
744 .class_init
= ram_class_init
,
747 static CPUSPARCState
*cpu_devinit(const char *cpu_model
, const struct hwdef
*hwdef
)
750 ResetData
*reset_info
;
752 uint32_t tick_frequency
= 100*1000000;
753 uint32_t stick_frequency
= 100*1000000;
754 uint32_t hstick_frequency
= 100*1000000;
757 cpu_model
= hwdef
->default_cpu_model
;
758 env
= cpu_init(cpu_model
);
760 fprintf(stderr
, "Unable to find Sparc CPU definition\n");
764 env
->tick
= cpu_timer_create("tick", env
, tick_irq
,
765 tick_frequency
, TICK_NPT_MASK
);
767 env
->stick
= cpu_timer_create("stick", env
, stick_irq
,
768 stick_frequency
, TICK_INT_DIS
);
770 env
->hstick
= cpu_timer_create("hstick", env
, hstick_irq
,
771 hstick_frequency
, TICK_INT_DIS
);
773 reset_info
= g_malloc0(sizeof(ResetData
));
774 reset_info
->env
= env
;
775 reset_info
->prom_addr
= hwdef
->prom_addr
;
776 qemu_register_reset(main_cpu_reset
, reset_info
);
781 static void sun4uv_init(MemoryRegion
*address_space_mem
,
783 const char *boot_devices
,
784 const char *kernel_filename
, const char *kernel_cmdline
,
785 const char *initrd_filename
, const char *cpu_model
,
786 const struct hwdef
*hwdef
)
791 long initrd_size
, kernel_size
;
792 PCIBus
*pci_bus
, *pci_bus2
, *pci_bus3
;
794 qemu_irq
*ivec_irqs
, *pbm_irqs
;
795 DriveInfo
*hd
[MAX_IDE_BUS
* MAX_IDE_DEVS
];
796 DriveInfo
*fd
[MAX_FD
];
800 env
= cpu_devinit(cpu_model
, hwdef
);
803 ram_init(0, RAM_size
);
805 prom_init(hwdef
->prom_addr
, bios_name
);
807 ivec_irqs
= qemu_allocate_irqs(cpu_set_ivec_irq
, env
, IVEC_MAX
);
808 pci_bus
= pci_apb_init(APB_SPECIAL_BASE
, APB_MEM_BASE
, ivec_irqs
, &pci_bus2
,
809 &pci_bus3
, &pbm_irqs
);
810 pci_vga_init(pci_bus
);
812 // XXX Should be pci_bus3
813 isa_bus
= pci_ebus_init(pci_bus
, -1, pbm_irqs
);
816 if (hwdef
->console_serial_base
) {
817 serial_mm_init(address_space_mem
, hwdef
->console_serial_base
, 0,
818 NULL
, 115200, serial_hds
[i
], DEVICE_BIG_ENDIAN
);
821 for(; i
< MAX_SERIAL_PORTS
; i
++) {
823 serial_isa_init(isa_bus
, i
, serial_hds
[i
]);
827 for(i
= 0; i
< MAX_PARALLEL_PORTS
; i
++) {
828 if (parallel_hds
[i
]) {
829 parallel_init(isa_bus
, i
, parallel_hds
[i
]);
833 for(i
= 0; i
< nb_nics
; i
++)
834 pci_nic_init_nofail(&nd_table
[i
], "ne2k_pci", NULL
);
836 ide_drive_get(hd
, MAX_IDE_BUS
);
838 pci_cmd646_ide_init(pci_bus
, hd
, 1);
840 isa_create_simple(isa_bus
, "i8042");
841 for(i
= 0; i
< MAX_FD
; i
++) {
842 fd
[i
] = drive_get(IF_FLOPPY
, 0, i
);
844 fdctrl_init_isa(isa_bus
, fd
);
845 nvram
= m48t59_init_isa(isa_bus
, 0x0074, NVRAM_SIZE
, 59);
848 kernel_size
= sun4u_load_kernel(kernel_filename
, initrd_filename
,
849 ram_size
, &initrd_size
);
851 sun4u_NVRAM_set_params(nvram
, NVRAM_SIZE
, "Sun4u", RAM_size
, boot_devices
,
852 KERNEL_LOAD_ADDR
, kernel_size
,
854 INITRD_LOAD_ADDR
, initrd_size
,
855 /* XXX: need an option to load a NVRAM image */
857 graphic_width
, graphic_height
, graphic_depth
,
858 (uint8_t *)&nd_table
[0].macaddr
);
860 fw_cfg
= fw_cfg_init(BIOS_CFG_IOPORT
, BIOS_CFG_IOPORT
+ 1, 0, 0);
861 fw_cfg_add_i32(fw_cfg
, FW_CFG_ID
, 1);
862 fw_cfg_add_i64(fw_cfg
, FW_CFG_RAM_SIZE
, (uint64_t)ram_size
);
863 fw_cfg_add_i16(fw_cfg
, FW_CFG_MACHINE_ID
, hwdef
->machine_id
);
864 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_ADDR
, KERNEL_LOAD_ADDR
);
865 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_SIZE
, kernel_size
);
866 if (kernel_cmdline
) {
867 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_SIZE
,
868 strlen(kernel_cmdline
) + 1);
869 fw_cfg_add_bytes(fw_cfg
, FW_CFG_CMDLINE_DATA
,
870 (uint8_t*)strdup(kernel_cmdline
),
871 strlen(kernel_cmdline
) + 1);
873 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_SIZE
, 0);
875 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_ADDR
, INITRD_LOAD_ADDR
);
876 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_SIZE
, initrd_size
);
877 fw_cfg_add_i16(fw_cfg
, FW_CFG_BOOT_DEVICE
, boot_devices
[0]);
879 fw_cfg_add_i16(fw_cfg
, FW_CFG_SPARC64_WIDTH
, graphic_width
);
880 fw_cfg_add_i16(fw_cfg
, FW_CFG_SPARC64_HEIGHT
, graphic_height
);
881 fw_cfg_add_i16(fw_cfg
, FW_CFG_SPARC64_DEPTH
, graphic_depth
);
883 qemu_register_boot_set(fw_cfg_boot_set
, fw_cfg
);
892 static const struct hwdef hwdefs
[] = {
893 /* Sun4u generic PC-like machine */
895 .default_cpu_model
= "TI UltraSparc IIi",
896 .machine_id
= sun4u_id
,
897 .prom_addr
= 0x1fff0000000ULL
,
898 .console_serial_base
= 0,
900 /* Sun4v generic PC-like machine */
902 .default_cpu_model
= "Sun UltraSparc T1",
903 .machine_id
= sun4v_id
,
904 .prom_addr
= 0x1fff0000000ULL
,
905 .console_serial_base
= 0,
907 /* Sun4v generic Niagara machine */
909 .default_cpu_model
= "Sun UltraSparc T1",
910 .machine_id
= niagara_id
,
911 .prom_addr
= 0xfff0000000ULL
,
912 .console_serial_base
= 0xfff0c2c000ULL
,
916 /* Sun4u hardware initialisation */
917 static void sun4u_init(ram_addr_t RAM_size
,
918 const char *boot_devices
,
919 const char *kernel_filename
, const char *kernel_cmdline
,
920 const char *initrd_filename
, const char *cpu_model
)
922 sun4uv_init(get_system_memory(), RAM_size
, boot_devices
, kernel_filename
,
923 kernel_cmdline
, initrd_filename
, cpu_model
, &hwdefs
[0]);
926 /* Sun4v hardware initialisation */
927 static void sun4v_init(ram_addr_t RAM_size
,
928 const char *boot_devices
,
929 const char *kernel_filename
, const char *kernel_cmdline
,
930 const char *initrd_filename
, const char *cpu_model
)
932 sun4uv_init(get_system_memory(), RAM_size
, boot_devices
, kernel_filename
,
933 kernel_cmdline
, initrd_filename
, cpu_model
, &hwdefs
[1]);
936 /* Niagara hardware initialisation */
937 static void niagara_init(ram_addr_t RAM_size
,
938 const char *boot_devices
,
939 const char *kernel_filename
, const char *kernel_cmdline
,
940 const char *initrd_filename
, const char *cpu_model
)
942 sun4uv_init(get_system_memory(), RAM_size
, boot_devices
, kernel_filename
,
943 kernel_cmdline
, initrd_filename
, cpu_model
, &hwdefs
[2]);
946 static QEMUMachine sun4u_machine
= {
948 .desc
= "Sun4u platform",
950 .max_cpus
= 1, // XXX for now
954 static QEMUMachine sun4v_machine
= {
956 .desc
= "Sun4v platform",
958 .max_cpus
= 1, // XXX for now
961 static QEMUMachine niagara_machine
= {
963 .desc
= "Sun4v platform, Niagara",
964 .init
= niagara_init
,
965 .max_cpus
= 1, // XXX for now
968 static void sun4u_register_types(void)
970 type_register_static(&ebus_info
);
971 type_register_static(&prom_info
);
972 type_register_static(&ram_info
);
975 static void sun4u_machine_init(void)
977 qemu_register_machine(&sun4u_machine
);
978 qemu_register_machine(&sun4v_machine
);
979 qemu_register_machine(&niagara_machine
);
982 type_init(sun4u_register_types
)
983 machine_init(sun4u_machine_init
);