4 * Copyright (c) 2005 Samuel Tardieu
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
27 #include "hw/sh_intc.h"
29 #if defined(CONFIG_USER_ONLY)
31 void do_interrupt (CPUState
*env
)
33 env
->exception_index
= -1;
36 int cpu_sh4_handle_mmu_fault(CPUState
* env
, target_ulong address
, int rw
,
40 env
->exception_index
= -1;
43 env
->exception_index
= 0x0a0;
46 env
->exception_index
= 0x0c0;
49 env
->exception_index
= 0x0a0;
55 int cpu_sh4_is_cached(CPUSH4State
* env
, target_ulong addr
)
57 /* For user mode, only U0 area is cachable. */
58 return !(addr
& 0x80000000);
61 #else /* !CONFIG_USER_ONLY */
64 #define MMU_ITLB_MISS (-1)
65 #define MMU_ITLB_MULTIPLE (-2)
66 #define MMU_ITLB_VIOLATION (-3)
67 #define MMU_DTLB_MISS_READ (-4)
68 #define MMU_DTLB_MISS_WRITE (-5)
69 #define MMU_DTLB_INITIAL_WRITE (-6)
70 #define MMU_DTLB_VIOLATION_READ (-7)
71 #define MMU_DTLB_VIOLATION_WRITE (-8)
72 #define MMU_DTLB_MULTIPLE (-9)
73 #define MMU_DTLB_MISS (-10)
74 #define MMU_IADDR_ERROR (-11)
75 #define MMU_DADDR_ERROR_READ (-12)
76 #define MMU_DADDR_ERROR_WRITE (-13)
78 void do_interrupt(CPUState
* env
)
80 int do_irq
= env
->interrupt_request
& CPU_INTERRUPT_HARD
;
81 int do_exp
, irq_vector
= env
->exception_index
;
83 /* prioritize exceptions over interrupts */
85 do_exp
= env
->exception_index
!= -1;
86 do_irq
= do_irq
&& (env
->exception_index
== -1);
88 if (env
->sr
& SR_BL
) {
89 if (do_exp
&& env
->exception_index
!= 0x1e0) {
90 env
->exception_index
= 0x000; /* masked exception -> reset */
92 if (do_irq
&& !env
->in_sleep
) {
99 irq_vector
= sh_intc_get_pending_vector(env
->intc_handle
,
100 (env
->sr
>> 4) & 0xf);
101 if (irq_vector
== -1) {
106 if (qemu_loglevel_mask(CPU_LOG_INT
)) {
108 switch (env
->exception_index
) {
110 expname
= "addr_error";
113 expname
= "tlb_miss";
116 expname
= "tlb_violation";
119 expname
= "illegal_instruction";
122 expname
= "slot_illegal_instruction";
125 expname
= "fpu_disable";
128 expname
= "slot_fpu";
131 expname
= "data_write";
134 expname
= "dtlb_miss_write";
137 expname
= "dtlb_violation_write";
140 expname
= "fpu_exception";
143 expname
= "initial_page_write";
149 expname
= do_irq
? "interrupt" : "???";
152 qemu_log("exception 0x%03x [%s] raised\n",
153 irq_vector
, expname
);
154 log_cpu_state(env
, 0);
159 env
->sgr
= env
->gregs
[15];
160 env
->sr
|= SR_BL
| SR_MD
| SR_RB
;
162 if (env
->flags
& (DELAY_SLOT
| DELAY_SLOT_CONDITIONAL
)) {
163 /* Branch instruction should be executed again before delay slot. */
165 /* Clear flags for exception/interrupt routine. */
166 env
->flags
&= ~(DELAY_SLOT
| DELAY_SLOT_CONDITIONAL
| DELAY_SLOT_TRUE
);
168 if (env
->flags
& DELAY_SLOT_CLEARME
)
172 env
->expevt
= env
->exception_index
;
173 switch (env
->exception_index
) {
178 env
->sr
|= 0xf << 4; /* IMASK */
179 env
->pc
= 0xa0000000;
183 env
->pc
= env
->vbr
+ 0x400;
186 env
->spc
+= 2; /* special case for TRAPA */
189 env
->pc
= env
->vbr
+ 0x100;
196 env
->intevt
= irq_vector
;
197 env
->pc
= env
->vbr
+ 0x600;
202 static void update_itlb_use(CPUState
* env
, int itlbnb
)
204 uint8_t or_mask
= 0, and_mask
= (uint8_t) - 1;
223 env
->mmucr
&= (and_mask
<< 24) | 0x00ffffff;
224 env
->mmucr
|= (or_mask
<< 24);
227 static int itlb_replacement(CPUState
* env
)
229 if ((env
->mmucr
& 0xe0000000) == 0xe0000000)
231 if ((env
->mmucr
& 0x98000000) == 0x18000000)
233 if ((env
->mmucr
& 0x54000000) == 0x04000000)
235 if ((env
->mmucr
& 0x2c000000) == 0x00000000)
237 cpu_abort(env
, "Unhandled itlb_replacement");
240 /* Find the corresponding entry in the right TLB
241 Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE
243 static int find_tlb_entry(CPUState
* env
, target_ulong address
,
244 tlb_t
* entries
, uint8_t nbtlb
, int use_asid
)
246 int match
= MMU_DTLB_MISS
;
251 asid
= env
->pteh
& 0xff;
253 for (i
= 0; i
< nbtlb
; i
++) {
255 continue; /* Invalid entry */
256 if (!entries
[i
].sh
&& use_asid
&& entries
[i
].asid
!= asid
)
257 continue; /* Bad ASID */
258 start
= (entries
[i
].vpn
<< 10) & ~(entries
[i
].size
- 1);
259 end
= start
+ entries
[i
].size
- 1;
260 if (address
>= start
&& address
<= end
) { /* Match */
261 if (match
!= MMU_DTLB_MISS
)
262 return MMU_DTLB_MULTIPLE
; /* Multiple match */
269 static void increment_urc(CPUState
* env
)
274 urb
= ((env
->mmucr
) >> 18) & 0x3f;
275 urc
= ((env
->mmucr
) >> 10) & 0x3f;
277 if ((urb
> 0 && urc
> urb
) || urc
> (UTLB_SIZE
- 1))
279 env
->mmucr
= (env
->mmucr
& 0xffff03ff) | (urc
<< 10);
282 /* Copy and utlb entry into itlb
285 static int copy_utlb_entry_itlb(CPUState
*env
, int utlb
)
290 itlb
= itlb_replacement(env
);
291 ientry
= &env
->itlb
[itlb
];
293 tlb_flush_page(env
, ientry
->vpn
<< 10);
295 *ientry
= env
->utlb
[utlb
];
296 update_itlb_use(env
, itlb
);
301 Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE
303 static int find_itlb_entry(CPUState
* env
, target_ulong address
,
308 e
= find_tlb_entry(env
, address
, env
->itlb
, ITLB_SIZE
, use_asid
);
309 if (e
== MMU_DTLB_MULTIPLE
) {
310 e
= MMU_ITLB_MULTIPLE
;
311 } else if (e
== MMU_DTLB_MISS
) {
314 update_itlb_use(env
, e
);
320 Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */
321 static int find_utlb_entry(CPUState
* env
, target_ulong address
, int use_asid
)
323 /* per utlb access */
327 return find_tlb_entry(env
, address
, env
->utlb
, UTLB_SIZE
, use_asid
);
330 /* Match address against MMU
331 Return MMU_OK, MMU_DTLB_MISS_READ, MMU_DTLB_MISS_WRITE,
332 MMU_DTLB_INITIAL_WRITE, MMU_DTLB_VIOLATION_READ,
333 MMU_DTLB_VIOLATION_WRITE, MMU_ITLB_MISS,
334 MMU_ITLB_MULTIPLE, MMU_ITLB_VIOLATION,
335 MMU_IADDR_ERROR, MMU_DADDR_ERROR_READ, MMU_DADDR_ERROR_WRITE.
337 static int get_mmu_address(CPUState
* env
, target_ulong
* physical
,
338 int *prot
, target_ulong address
,
339 int rw
, int access_type
)
342 tlb_t
*matching
= NULL
;
344 use_asid
= (env
->mmucr
& MMUCR_SV
) == 0 || (env
->sr
& SR_MD
) == 0;
347 n
= find_itlb_entry(env
, address
, use_asid
);
349 matching
= &env
->itlb
[n
];
350 if (!(env
->sr
& SR_MD
) && !(matching
->pr
& 2))
351 n
= MMU_ITLB_VIOLATION
;
355 n
= find_utlb_entry(env
, address
, use_asid
);
357 n
= copy_utlb_entry_itlb(env
, n
);
358 matching
= &env
->itlb
[n
];
359 if (!(env
->sr
& SR_MD
) && !(matching
->pr
& 2)) {
360 n
= MMU_ITLB_VIOLATION
;
362 *prot
= PAGE_READ
| PAGE_EXEC
;
363 if ((matching
->pr
& 1) && matching
->d
) {
367 } else if (n
== MMU_DTLB_MULTIPLE
) {
368 n
= MMU_ITLB_MULTIPLE
;
369 } else if (n
== MMU_DTLB_MISS
) {
374 n
= find_utlb_entry(env
, address
, use_asid
);
376 matching
= &env
->utlb
[n
];
377 if (!(env
->sr
& SR_MD
) && !(matching
->pr
& 2)) {
378 n
= (rw
== 1) ? MMU_DTLB_VIOLATION_WRITE
:
379 MMU_DTLB_VIOLATION_READ
;
380 } else if ((rw
== 1) && !(matching
->pr
& 1)) {
381 n
= MMU_DTLB_VIOLATION_WRITE
;
382 } else if ((rw
== 1) && !matching
->d
) {
383 n
= MMU_DTLB_INITIAL_WRITE
;
386 if ((matching
->pr
& 1) && matching
->d
) {
390 } else if (n
== MMU_DTLB_MISS
) {
391 n
= (rw
== 1) ? MMU_DTLB_MISS_WRITE
:
397 *physical
= ((matching
->ppn
<< 10) & ~(matching
->size
- 1)) |
398 (address
& (matching
->size
- 1));
403 static int get_physical_address(CPUState
* env
, target_ulong
* physical
,
404 int *prot
, target_ulong address
,
405 int rw
, int access_type
)
407 /* P1, P2 and P4 areas do not use translation */
408 if ((address
>= 0x80000000 && address
< 0xc0000000) ||
409 address
>= 0xe0000000) {
410 if (!(env
->sr
& SR_MD
)
411 && (address
< 0xe0000000 || address
>= 0xe4000000)) {
412 /* Unauthorized access in user mode (only store queues are available) */
413 fprintf(stderr
, "Unauthorized access\n");
415 return MMU_DADDR_ERROR_READ
;
417 return MMU_DADDR_ERROR_WRITE
;
419 return MMU_IADDR_ERROR
;
421 if (address
>= 0x80000000 && address
< 0xc0000000) {
422 /* Mask upper 3 bits for P1 and P2 areas */
423 *physical
= address
& 0x1fffffff;
427 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
431 /* If MMU is disabled, return the corresponding physical page */
432 if (!(env
->mmucr
& MMUCR_AT
)) {
433 *physical
= address
& 0x1FFFFFFF;
434 *prot
= PAGE_READ
| PAGE_WRITE
| PAGE_EXEC
;
438 /* We need to resort to the MMU */
439 return get_mmu_address(env
, physical
, prot
, address
, rw
, access_type
);
442 int cpu_sh4_handle_mmu_fault(CPUState
* env
, target_ulong address
, int rw
,
445 target_ulong physical
;
446 int prot
, ret
, access_type
;
448 access_type
= ACCESS_INT
;
450 get_physical_address(env
, &physical
, &prot
, address
, rw
,
455 if (ret
!= MMU_DTLB_MULTIPLE
&& ret
!= MMU_ITLB_MULTIPLE
) {
456 env
->pteh
= (env
->pteh
& PTEH_ASID_MASK
) |
457 (address
& PTEH_VPN_MASK
);
461 case MMU_DTLB_MISS_READ
:
462 env
->exception_index
= 0x040;
464 case MMU_DTLB_MULTIPLE
:
465 case MMU_ITLB_MULTIPLE
:
466 env
->exception_index
= 0x140;
468 case MMU_ITLB_VIOLATION
:
469 env
->exception_index
= 0x0a0;
471 case MMU_DTLB_MISS_WRITE
:
472 env
->exception_index
= 0x060;
474 case MMU_DTLB_INITIAL_WRITE
:
475 env
->exception_index
= 0x080;
477 case MMU_DTLB_VIOLATION_READ
:
478 env
->exception_index
= 0x0a0;
480 case MMU_DTLB_VIOLATION_WRITE
:
481 env
->exception_index
= 0x0c0;
483 case MMU_IADDR_ERROR
:
484 case MMU_DADDR_ERROR_READ
:
485 env
->exception_index
= 0x0e0;
487 case MMU_DADDR_ERROR_WRITE
:
488 env
->exception_index
= 0x100;
491 cpu_abort(env
, "Unhandled MMU fault");
496 address
&= TARGET_PAGE_MASK
;
497 physical
&= TARGET_PAGE_MASK
;
499 tlb_set_page(env
, address
, physical
, prot
, mmu_idx
, TARGET_PAGE_SIZE
);
503 target_phys_addr_t
cpu_get_phys_page_debug(CPUState
* env
, target_ulong addr
)
505 target_ulong physical
;
508 get_physical_address(env
, &physical
, &prot
, addr
, 0, 0);
512 void cpu_load_tlb(CPUSH4State
* env
)
514 int n
= cpu_mmucr_urc(env
->mmucr
);
515 tlb_t
* entry
= &env
->utlb
[n
];
518 /* Overwriting valid entry in utlb. */
519 target_ulong address
= entry
->vpn
<< 10;
520 tlb_flush_page(env
, address
);
523 /* Take values into cpu status from registers. */
524 entry
->asid
= (uint8_t)cpu_pteh_asid(env
->pteh
);
525 entry
->vpn
= cpu_pteh_vpn(env
->pteh
);
526 entry
->v
= (uint8_t)cpu_ptel_v(env
->ptel
);
527 entry
->ppn
= cpu_ptel_ppn(env
->ptel
);
528 entry
->sz
= (uint8_t)cpu_ptel_sz(env
->ptel
);
531 entry
->size
= 1024; /* 1K */
534 entry
->size
= 1024 * 4; /* 4K */
537 entry
->size
= 1024 * 64; /* 64K */
540 entry
->size
= 1024 * 1024; /* 1M */
543 cpu_abort(env
, "Unhandled load_tlb");
546 entry
->sh
= (uint8_t)cpu_ptel_sh(env
->ptel
);
547 entry
->c
= (uint8_t)cpu_ptel_c(env
->ptel
);
548 entry
->pr
= (uint8_t)cpu_ptel_pr(env
->ptel
);
549 entry
->d
= (uint8_t)cpu_ptel_d(env
->ptel
);
550 entry
->wt
= (uint8_t)cpu_ptel_wt(env
->ptel
);
551 entry
->sa
= (uint8_t)cpu_ptea_sa(env
->ptea
);
552 entry
->tc
= (uint8_t)cpu_ptea_tc(env
->ptea
);
555 void cpu_sh4_invalidate_tlb(CPUSH4State
*s
)
560 for (i
= 0; i
< UTLB_SIZE
; i
++) {
561 tlb_t
* entry
= &s
->utlb
[i
];
565 for (i
= 0; i
< ITLB_SIZE
; i
++) {
566 tlb_t
* entry
= &s
->itlb
[i
];
573 uint32_t cpu_sh4_read_mmaped_itlb_addr(CPUSH4State
*s
,
574 target_phys_addr_t addr
)
576 int index
= (addr
& 0x00000300) >> 8;
577 tlb_t
* entry
= &s
->itlb
[index
];
579 return (entry
->vpn
<< 10) |
584 void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State
*s
, target_phys_addr_t addr
,
587 uint32_t vpn
= (mem_value
& 0xfffffc00) >> 10;
588 uint8_t v
= (uint8_t)((mem_value
& 0x00000100) >> 8);
589 uint8_t asid
= (uint8_t)(mem_value
& 0x000000ff);
591 int index
= (addr
& 0x00000300) >> 8;
592 tlb_t
* entry
= &s
->itlb
[index
];
594 /* Overwriting valid entry in itlb. */
595 target_ulong address
= entry
->vpn
<< 10;
596 tlb_flush_page(s
, address
);
603 uint32_t cpu_sh4_read_mmaped_itlb_data(CPUSH4State
*s
,
604 target_phys_addr_t addr
)
606 int array
= (addr
& 0x00800000) >> 23;
607 int index
= (addr
& 0x00000300) >> 8;
608 tlb_t
* entry
= &s
->itlb
[index
];
611 /* ITLB Data Array 1 */
612 return (entry
->ppn
<< 10) |
615 ((entry
->sz
& 1) << 6) |
616 ((entry
->sz
& 2) << 4) |
620 /* ITLB Data Array 2 */
621 return (entry
->tc
<< 1) |
626 void cpu_sh4_write_mmaped_itlb_data(CPUSH4State
*s
, target_phys_addr_t addr
,
629 int array
= (addr
& 0x00800000) >> 23;
630 int index
= (addr
& 0x00000300) >> 8;
631 tlb_t
* entry
= &s
->itlb
[index
];
634 /* ITLB Data Array 1 */
636 /* Overwriting valid entry in utlb. */
637 target_ulong address
= entry
->vpn
<< 10;
638 tlb_flush_page(s
, address
);
640 entry
->ppn
= (mem_value
& 0x1ffffc00) >> 10;
641 entry
->v
= (mem_value
& 0x00000100) >> 8;
642 entry
->sz
= (mem_value
& 0x00000080) >> 6 |
643 (mem_value
& 0x00000010) >> 4;
644 entry
->pr
= (mem_value
& 0x00000040) >> 5;
645 entry
->c
= (mem_value
& 0x00000008) >> 3;
646 entry
->sh
= (mem_value
& 0x00000002) >> 1;
648 /* ITLB Data Array 2 */
649 entry
->tc
= (mem_value
& 0x00000008) >> 3;
650 entry
->sa
= (mem_value
& 0x00000007);
654 uint32_t cpu_sh4_read_mmaped_utlb_addr(CPUSH4State
*s
,
655 target_phys_addr_t addr
)
657 int index
= (addr
& 0x00003f00) >> 8;
658 tlb_t
* entry
= &s
->utlb
[index
];
660 increment_urc(s
); /* per utlb access */
662 return (entry
->vpn
<< 10) |
667 void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State
*s
, target_phys_addr_t addr
,
670 int associate
= addr
& 0x0000080;
671 uint32_t vpn
= (mem_value
& 0xfffffc00) >> 10;
672 uint8_t d
= (uint8_t)((mem_value
& 0x00000200) >> 9);
673 uint8_t v
= (uint8_t)((mem_value
& 0x00000100) >> 8);
674 uint8_t asid
= (uint8_t)(mem_value
& 0x000000ff);
675 int use_asid
= (s
->mmucr
& MMUCR_SV
) == 0 || (s
->sr
& SR_MD
) == 0;
679 tlb_t
* utlb_match_entry
= NULL
;
680 int needs_tlb_flush
= 0;
683 for (i
= 0; i
< UTLB_SIZE
; i
++) {
684 tlb_t
* entry
= &s
->utlb
[i
];
688 if (entry
->vpn
== vpn
689 && (!use_asid
|| entry
->asid
== asid
|| entry
->sh
)) {
690 if (utlb_match_entry
) {
691 /* Multiple TLB Exception */
692 s
->exception_index
= 0x140;
700 utlb_match_entry
= entry
;
702 increment_urc(s
); /* per utlb access */
706 for (i
= 0; i
< ITLB_SIZE
; i
++) {
707 tlb_t
* entry
= &s
->itlb
[i
];
708 if (entry
->vpn
== vpn
709 && (!use_asid
|| entry
->asid
== asid
|| entry
->sh
)) {
712 if (utlb_match_entry
)
713 *entry
= *utlb_match_entry
;
721 tlb_flush_page(s
, vpn
<< 10);
724 int index
= (addr
& 0x00003f00) >> 8;
725 tlb_t
* entry
= &s
->utlb
[index
];
727 /* Overwriting valid entry in utlb. */
728 target_ulong address
= entry
->vpn
<< 10;
729 tlb_flush_page(s
, address
);
739 uint32_t cpu_sh4_read_mmaped_utlb_data(CPUSH4State
*s
,
740 target_phys_addr_t addr
)
742 int array
= (addr
& 0x00800000) >> 23;
743 int index
= (addr
& 0x00003f00) >> 8;
744 tlb_t
* entry
= &s
->utlb
[index
];
746 increment_urc(s
); /* per utlb access */
749 /* ITLB Data Array 1 */
750 return (entry
->ppn
<< 10) |
753 ((entry
->sz
& 1) << 6) |
754 ((entry
->sz
& 2) << 4) |
760 /* ITLB Data Array 2 */
761 return (entry
->tc
<< 1) |
766 void cpu_sh4_write_mmaped_utlb_data(CPUSH4State
*s
, target_phys_addr_t addr
,
769 int array
= (addr
& 0x00800000) >> 23;
770 int index
= (addr
& 0x00003f00) >> 8;
771 tlb_t
* entry
= &s
->utlb
[index
];
773 increment_urc(s
); /* per utlb access */
776 /* UTLB Data Array 1 */
778 /* Overwriting valid entry in utlb. */
779 target_ulong address
= entry
->vpn
<< 10;
780 tlb_flush_page(s
, address
);
782 entry
->ppn
= (mem_value
& 0x1ffffc00) >> 10;
783 entry
->v
= (mem_value
& 0x00000100) >> 8;
784 entry
->sz
= (mem_value
& 0x00000080) >> 6 |
785 (mem_value
& 0x00000010) >> 4;
786 entry
->pr
= (mem_value
& 0x00000060) >> 5;
787 entry
->c
= (mem_value
& 0x00000008) >> 3;
788 entry
->d
= (mem_value
& 0x00000004) >> 2;
789 entry
->sh
= (mem_value
& 0x00000002) >> 1;
790 entry
->wt
= (mem_value
& 0x00000001);
792 /* UTLB Data Array 2 */
793 entry
->tc
= (mem_value
& 0x00000008) >> 3;
794 entry
->sa
= (mem_value
& 0x00000007);
798 int cpu_sh4_is_cached(CPUSH4State
* env
, target_ulong addr
)
801 int use_asid
= (env
->mmucr
& MMUCR_SV
) == 0 || (env
->sr
& SR_MD
) == 0;
804 if (env
->sr
& SR_MD
) {
805 /* For previledged mode, P2 and P4 area is not cachable. */
806 if ((0xA0000000 <= addr
&& addr
< 0xC0000000) || 0xE0000000 <= addr
)
809 /* For user mode, only U0 area is cachable. */
810 if (0x80000000 <= addr
)
815 * TODO : Evaluate CCR and check if the cache is on or off.
816 * Now CCR is not in CPUSH4State, but in SH7750State.
817 * When you move the ccr into CPUSH4State, the code will be
821 /* check if operand cache is enabled or not. */
826 /* if MMU is off, no check for TLB. */
827 if (env
->mmucr
& MMUCR_AT
)
831 n
= find_tlb_entry(env
, addr
, env
->itlb
, ITLB_SIZE
, use_asid
);
833 return env
->itlb
[n
].c
;
835 n
= find_tlb_entry(env
, addr
, env
->utlb
, UTLB_SIZE
, use_asid
);
837 return env
->utlb
[n
].c
;