4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
22 #include "exec/exec-all.h"
24 #include "tcg-op-gvec.h"
27 #include "translate.h"
28 #include "internals.h"
29 #include "qemu/host-utils.h"
31 #include "exec/semihost.h"
32 #include "exec/gen-icount.h"
34 #include "exec/helper-proto.h"
35 #include "exec/helper-gen.h"
38 #include "trace-tcg.h"
39 #include "translate-a64.h"
40 #include "qemu/atomic128.h"
42 static TCGv_i64 cpu_X
[32];
43 static TCGv_i64 cpu_pc
;
45 /* Load/store exclusive handling */
46 static TCGv_i64 cpu_exclusive_high
;
48 static const char *regnames
[] = {
49 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
50 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
51 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
52 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
56 A64_SHIFT_TYPE_LSL
= 0,
57 A64_SHIFT_TYPE_LSR
= 1,
58 A64_SHIFT_TYPE_ASR
= 2,
59 A64_SHIFT_TYPE_ROR
= 3
62 /* Table based decoder typedefs - used when the relevant bits for decode
63 * are too awkwardly scattered across the instruction (eg SIMD).
65 typedef void AArch64DecodeFn(DisasContext
*s
, uint32_t insn
);
67 typedef struct AArch64DecodeTable
{
70 AArch64DecodeFn
*disas_fn
;
73 /* Function prototype for gen_ functions for calling Neon helpers */
74 typedef void NeonGenOneOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
);
75 typedef void NeonGenTwoOpFn(TCGv_i32
, TCGv_i32
, TCGv_i32
);
76 typedef void NeonGenTwoOpEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i32
, TCGv_i32
);
77 typedef void NeonGenTwo64OpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
);
78 typedef void NeonGenTwo64OpEnvFn(TCGv_i64
, TCGv_ptr
, TCGv_i64
, TCGv_i64
);
79 typedef void NeonGenNarrowFn(TCGv_i32
, TCGv_i64
);
80 typedef void NeonGenNarrowEnvFn(TCGv_i32
, TCGv_ptr
, TCGv_i64
);
81 typedef void NeonGenWidenFn(TCGv_i64
, TCGv_i32
);
82 typedef void NeonGenTwoSingleOPFn(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
83 typedef void NeonGenTwoDoubleOPFn(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGv_ptr
);
84 typedef void NeonGenOneOpFn(TCGv_i64
, TCGv_i64
);
85 typedef void CryptoTwoOpFn(TCGv_ptr
, TCGv_ptr
);
86 typedef void CryptoThreeOpIntFn(TCGv_ptr
, TCGv_ptr
, TCGv_i32
);
87 typedef void CryptoThreeOpFn(TCGv_ptr
, TCGv_ptr
, TCGv_ptr
);
88 typedef void AtomicThreeOpFn(TCGv_i64
, TCGv_i64
, TCGv_i64
, TCGArg
, TCGMemOp
);
90 /* initialize TCG globals. */
91 void a64_translate_init(void)
95 cpu_pc
= tcg_global_mem_new_i64(cpu_env
,
96 offsetof(CPUARMState
, pc
),
98 for (i
= 0; i
< 32; i
++) {
99 cpu_X
[i
] = tcg_global_mem_new_i64(cpu_env
,
100 offsetof(CPUARMState
, xregs
[i
]),
104 cpu_exclusive_high
= tcg_global_mem_new_i64(cpu_env
,
105 offsetof(CPUARMState
, exclusive_high
), "exclusive_high");
108 static inline int get_a64_user_mem_index(DisasContext
*s
)
110 /* Return the core mmu_idx to use for A64 "unprivileged load/store" insns:
111 * if EL1, access as if EL0; otherwise access at current EL
115 switch (s
->mmu_idx
) {
116 case ARMMMUIdx_S12NSE1
:
117 useridx
= ARMMMUIdx_S12NSE0
;
119 case ARMMMUIdx_S1SE1
:
120 useridx
= ARMMMUIdx_S1SE0
;
123 g_assert_not_reached();
125 useridx
= s
->mmu_idx
;
128 return arm_to_core_mmu_idx(useridx
);
131 static void reset_btype(DisasContext
*s
)
134 TCGv_i32 zero
= tcg_const_i32(0);
135 tcg_gen_st_i32(zero
, cpu_env
, offsetof(CPUARMState
, btype
));
136 tcg_temp_free_i32(zero
);
141 static void set_btype(DisasContext
*s
, int val
)
145 /* BTYPE is a 2-bit field, and 0 should be done with reset_btype. */
146 tcg_debug_assert(val
>= 1 && val
<= 3);
148 tcg_val
= tcg_const_i32(val
);
149 tcg_gen_st_i32(tcg_val
, cpu_env
, offsetof(CPUARMState
, btype
));
150 tcg_temp_free_i32(tcg_val
);
154 void aarch64_cpu_dump_state(CPUState
*cs
, FILE *f
,
155 fprintf_function cpu_fprintf
, int flags
)
157 ARMCPU
*cpu
= ARM_CPU(cs
);
158 CPUARMState
*env
= &cpu
->env
;
159 uint32_t psr
= pstate_read(env
);
161 int el
= arm_current_el(env
);
162 const char *ns_status
;
164 cpu_fprintf(f
, " PC=%016" PRIx64
" ", env
->pc
);
165 for (i
= 0; i
< 32; i
++) {
167 cpu_fprintf(f
, " SP=%016" PRIx64
"\n", env
->xregs
[i
]);
169 cpu_fprintf(f
, "X%02d=%016" PRIx64
"%s", i
, env
->xregs
[i
],
170 (i
+ 2) % 3 ? " " : "\n");
174 if (arm_feature(env
, ARM_FEATURE_EL3
) && el
!= 3) {
175 ns_status
= env
->cp15
.scr_el3
& SCR_NS
? "NS " : "S ";
179 cpu_fprintf(f
, "PSTATE=%08x %c%c%c%c %sEL%d%c",
181 psr
& PSTATE_N
? 'N' : '-',
182 psr
& PSTATE_Z
? 'Z' : '-',
183 psr
& PSTATE_C
? 'C' : '-',
184 psr
& PSTATE_V
? 'V' : '-',
187 psr
& PSTATE_SP
? 'h' : 't');
189 if (cpu_isar_feature(aa64_bti
, cpu
)) {
190 cpu_fprintf(f
, " BTYPE=%d", (psr
& PSTATE_BTYPE
) >> 10);
192 if (!(flags
& CPU_DUMP_FPU
)) {
193 cpu_fprintf(f
, "\n");
196 if (fp_exception_el(env
, el
) != 0) {
197 cpu_fprintf(f
, " FPU disabled\n");
200 cpu_fprintf(f
, " FPCR=%08x FPSR=%08x\n",
201 vfp_get_fpcr(env
), vfp_get_fpsr(env
));
203 if (cpu_isar_feature(aa64_sve
, cpu
) && sve_exception_el(env
, el
) == 0) {
204 int j
, zcr_len
= sve_zcr_len_for_el(env
, el
);
206 for (i
= 0; i
<= FFR_PRED_NUM
; i
++) {
208 if (i
== FFR_PRED_NUM
) {
209 cpu_fprintf(f
, "FFR=");
210 /* It's last, so end the line. */
213 cpu_fprintf(f
, "P%02d=", i
);
226 /* More than one quadword per predicate. */
231 for (j
= zcr_len
/ 4; j
>= 0; j
--) {
233 if (j
* 4 + 4 <= zcr_len
+ 1) {
236 digits
= (zcr_len
% 4 + 1) * 4;
238 cpu_fprintf(f
, "%0*" PRIx64
"%s", digits
,
239 env
->vfp
.pregs
[i
].p
[j
],
240 j
? ":" : eol
? "\n" : " ");
244 for (i
= 0; i
< 32; i
++) {
246 cpu_fprintf(f
, "Z%02d=%016" PRIx64
":%016" PRIx64
"%s",
247 i
, env
->vfp
.zregs
[i
].d
[1],
248 env
->vfp
.zregs
[i
].d
[0], i
& 1 ? "\n" : " ");
249 } else if (zcr_len
== 1) {
250 cpu_fprintf(f
, "Z%02d=%016" PRIx64
":%016" PRIx64
251 ":%016" PRIx64
":%016" PRIx64
"\n",
252 i
, env
->vfp
.zregs
[i
].d
[3], env
->vfp
.zregs
[i
].d
[2],
253 env
->vfp
.zregs
[i
].d
[1], env
->vfp
.zregs
[i
].d
[0]);
255 for (j
= zcr_len
; j
>= 0; j
--) {
256 bool odd
= (zcr_len
- j
) % 2 != 0;
258 cpu_fprintf(f
, "Z%02d[%x-%x]=", i
, j
, j
- 1);
261 cpu_fprintf(f
, " [%x-%x]=", j
, j
- 1);
263 cpu_fprintf(f
, " [%x]=", j
);
266 cpu_fprintf(f
, "%016" PRIx64
":%016" PRIx64
"%s",
267 env
->vfp
.zregs
[i
].d
[j
* 2 + 1],
268 env
->vfp
.zregs
[i
].d
[j
* 2],
269 odd
|| j
== 0 ? "\n" : ":");
274 for (i
= 0; i
< 32; i
++) {
275 uint64_t *q
= aa64_vfp_qreg(env
, i
);
276 cpu_fprintf(f
, "Q%02d=%016" PRIx64
":%016" PRIx64
"%s",
277 i
, q
[1], q
[0], (i
& 1 ? "\n" : " "));
282 void gen_a64_set_pc_im(uint64_t val
)
284 tcg_gen_movi_i64(cpu_pc
, val
);
288 * Handle Top Byte Ignore (TBI) bits.
290 * If address tagging is enabled via the TCR TBI bits:
291 * + for EL2 and EL3 there is only one TBI bit, and if it is set
292 * then the address is zero-extended, clearing bits [63:56]
293 * + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0
294 * and TBI1 controls addressses with bit 55 == 1.
295 * If the appropriate TBI bit is set for the address then
296 * the address is sign-extended from bit 55 into bits [63:56]
298 * Here We have concatenated TBI{1,0} into tbi.
300 static void gen_top_byte_ignore(DisasContext
*s
, TCGv_i64 dst
,
301 TCGv_i64 src
, int tbi
)
304 /* Load unmodified address */
305 tcg_gen_mov_i64(dst
, src
);
306 } else if (s
->current_el
>= 2) {
307 /* FIXME: ARMv8.1-VHE S2 translation regime. */
308 /* Force tag byte to all zero */
309 tcg_gen_extract_i64(dst
, src
, 0, 56);
311 /* Sign-extend from bit 55. */
312 tcg_gen_sextract_i64(dst
, src
, 0, 56);
315 TCGv_i64 tcg_zero
= tcg_const_i64(0);
318 * The two TBI bits differ.
319 * If tbi0, then !tbi1: only use the extension if positive.
320 * if !tbi0, then tbi1: only use the extension if negative.
322 tcg_gen_movcond_i64(tbi
== 1 ? TCG_COND_GE
: TCG_COND_LT
,
323 dst
, dst
, tcg_zero
, dst
, src
);
324 tcg_temp_free_i64(tcg_zero
);
329 static void gen_a64_set_pc(DisasContext
*s
, TCGv_i64 src
)
332 * If address tagging is enabled for instructions via the TCR TBI bits,
333 * then loading an address into the PC will clear out any tag.
335 gen_top_byte_ignore(s
, cpu_pc
, src
, s
->tbii
);
338 typedef struct DisasCompare64
{
343 static void a64_test_cc(DisasCompare64
*c64
, int cc
)
347 arm_test_cc(&c32
, cc
);
349 /* Sign-extend the 32-bit value so that the GE/LT comparisons work
350 * properly. The NE/EQ comparisons are also fine with this choice. */
351 c64
->cond
= c32
.cond
;
352 c64
->value
= tcg_temp_new_i64();
353 tcg_gen_ext_i32_i64(c64
->value
, c32
.value
);
358 static void a64_free_cc(DisasCompare64
*c64
)
360 tcg_temp_free_i64(c64
->value
);
363 static void gen_exception_internal(int excp
)
365 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
367 assert(excp_is_internal(excp
));
368 gen_helper_exception_internal(cpu_env
, tcg_excp
);
369 tcg_temp_free_i32(tcg_excp
);
372 static void gen_exception(int excp
, uint32_t syndrome
, uint32_t target_el
)
374 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
375 TCGv_i32 tcg_syn
= tcg_const_i32(syndrome
);
376 TCGv_i32 tcg_el
= tcg_const_i32(target_el
);
378 gen_helper_exception_with_syndrome(cpu_env
, tcg_excp
,
380 tcg_temp_free_i32(tcg_el
);
381 tcg_temp_free_i32(tcg_syn
);
382 tcg_temp_free_i32(tcg_excp
);
385 static void gen_exception_internal_insn(DisasContext
*s
, int offset
, int excp
)
387 gen_a64_set_pc_im(s
->pc
- offset
);
388 gen_exception_internal(excp
);
389 s
->base
.is_jmp
= DISAS_NORETURN
;
392 static void gen_exception_insn(DisasContext
*s
, int offset
, int excp
,
393 uint32_t syndrome
, uint32_t target_el
)
395 gen_a64_set_pc_im(s
->pc
- offset
);
396 gen_exception(excp
, syndrome
, target_el
);
397 s
->base
.is_jmp
= DISAS_NORETURN
;
400 static void gen_exception_bkpt_insn(DisasContext
*s
, int offset
,
405 gen_a64_set_pc_im(s
->pc
- offset
);
406 tcg_syn
= tcg_const_i32(syndrome
);
407 gen_helper_exception_bkpt_insn(cpu_env
, tcg_syn
);
408 tcg_temp_free_i32(tcg_syn
);
409 s
->base
.is_jmp
= DISAS_NORETURN
;
412 static void gen_ss_advance(DisasContext
*s
)
414 /* If the singlestep state is Active-not-pending, advance to
419 gen_helper_clear_pstate_ss(cpu_env
);
423 static void gen_step_complete_exception(DisasContext
*s
)
425 /* We just completed step of an insn. Move from Active-not-pending
426 * to Active-pending, and then also take the swstep exception.
427 * This corresponds to making the (IMPDEF) choice to prioritize
428 * swstep exceptions over asynchronous exceptions taken to an exception
429 * level where debug is disabled. This choice has the advantage that
430 * we do not need to maintain internal state corresponding to the
431 * ISV/EX syndrome bits between completion of the step and generation
432 * of the exception, and our syndrome information is always correct.
435 gen_exception(EXCP_UDEF
, syn_swstep(s
->ss_same_el
, 1, s
->is_ldex
),
436 default_exception_el(s
));
437 s
->base
.is_jmp
= DISAS_NORETURN
;
440 static inline bool use_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
442 /* No direct tb linking with singlestep (either QEMU's or the ARM
443 * debug architecture kind) or deterministic io
445 if (s
->base
.singlestep_enabled
|| s
->ss_active
||
446 (tb_cflags(s
->base
.tb
) & CF_LAST_IO
)) {
450 #ifndef CONFIG_USER_ONLY
451 /* Only link tbs from inside the same guest page */
452 if ((s
->base
.tb
->pc
& TARGET_PAGE_MASK
) != (dest
& TARGET_PAGE_MASK
)) {
460 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
462 TranslationBlock
*tb
;
465 if (use_goto_tb(s
, n
, dest
)) {
467 gen_a64_set_pc_im(dest
);
468 tcg_gen_exit_tb(tb
, n
);
469 s
->base
.is_jmp
= DISAS_NORETURN
;
471 gen_a64_set_pc_im(dest
);
473 gen_step_complete_exception(s
);
474 } else if (s
->base
.singlestep_enabled
) {
475 gen_exception_internal(EXCP_DEBUG
);
477 tcg_gen_lookup_and_goto_ptr();
478 s
->base
.is_jmp
= DISAS_NORETURN
;
483 void unallocated_encoding(DisasContext
*s
)
485 /* Unallocated and reserved encodings are uncategorized */
486 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_uncategorized(),
487 default_exception_el(s
));
490 static void init_tmp_a64_array(DisasContext
*s
)
492 #ifdef CONFIG_DEBUG_TCG
493 memset(s
->tmp_a64
, 0, sizeof(s
->tmp_a64
));
495 s
->tmp_a64_count
= 0;
498 static void free_tmp_a64(DisasContext
*s
)
501 for (i
= 0; i
< s
->tmp_a64_count
; i
++) {
502 tcg_temp_free_i64(s
->tmp_a64
[i
]);
504 init_tmp_a64_array(s
);
507 TCGv_i64
new_tmp_a64(DisasContext
*s
)
509 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
510 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_new_i64();
513 TCGv_i64
new_tmp_a64_zero(DisasContext
*s
)
515 TCGv_i64 t
= new_tmp_a64(s
);
516 tcg_gen_movi_i64(t
, 0);
521 * Register access functions
523 * These functions are used for directly accessing a register in where
524 * changes to the final register value are likely to be made. If you
525 * need to use a register for temporary calculation (e.g. index type
526 * operations) use the read_* form.
528 * B1.2.1 Register mappings
530 * In instruction register encoding 31 can refer to ZR (zero register) or
531 * the SP (stack pointer) depending on context. In QEMU's case we map SP
532 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
533 * This is the point of the _sp forms.
535 TCGv_i64
cpu_reg(DisasContext
*s
, int reg
)
538 return new_tmp_a64_zero(s
);
544 /* register access for when 31 == SP */
545 TCGv_i64
cpu_reg_sp(DisasContext
*s
, int reg
)
550 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
551 * representing the register contents. This TCGv is an auto-freed
552 * temporary so it need not be explicitly freed, and may be modified.
554 TCGv_i64
read_cpu_reg(DisasContext
*s
, int reg
, int sf
)
556 TCGv_i64 v
= new_tmp_a64(s
);
559 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
561 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
564 tcg_gen_movi_i64(v
, 0);
569 TCGv_i64
read_cpu_reg_sp(DisasContext
*s
, int reg
, int sf
)
571 TCGv_i64 v
= new_tmp_a64(s
);
573 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
575 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
580 /* Return the offset into CPUARMState of a slice (from
581 * the least significant end) of FP register Qn (ie
583 * (Note that this is not the same mapping as for A32; see cpu.h)
585 static inline int fp_reg_offset(DisasContext
*s
, int regno
, TCGMemOp size
)
587 return vec_reg_offset(s
, regno
, 0, size
);
590 /* Offset of the high half of the 128 bit vector Qn */
591 static inline int fp_reg_hi_offset(DisasContext
*s
, int regno
)
593 return vec_reg_offset(s
, regno
, 1, MO_64
);
596 /* Convenience accessors for reading and writing single and double
597 * FP registers. Writing clears the upper parts of the associated
598 * 128 bit vector register, as required by the architecture.
599 * Note that unlike the GP register accessors, the values returned
600 * by the read functions must be manually freed.
602 static TCGv_i64
read_fp_dreg(DisasContext
*s
, int reg
)
604 TCGv_i64 v
= tcg_temp_new_i64();
606 tcg_gen_ld_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
610 static TCGv_i32
read_fp_sreg(DisasContext
*s
, int reg
)
612 TCGv_i32 v
= tcg_temp_new_i32();
614 tcg_gen_ld_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_32
));
618 static TCGv_i32
read_fp_hreg(DisasContext
*s
, int reg
)
620 TCGv_i32 v
= tcg_temp_new_i32();
622 tcg_gen_ld16u_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_16
));
626 /* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64).
627 * If SVE is not enabled, then there are only 128 bits in the vector.
629 static void clear_vec_high(DisasContext
*s
, bool is_q
, int rd
)
631 unsigned ofs
= fp_reg_offset(s
, rd
, MO_64
);
632 unsigned vsz
= vec_full_reg_size(s
);
635 TCGv_i64 tcg_zero
= tcg_const_i64(0);
636 tcg_gen_st_i64(tcg_zero
, cpu_env
, ofs
+ 8);
637 tcg_temp_free_i64(tcg_zero
);
640 tcg_gen_gvec_dup8i(ofs
+ 16, vsz
- 16, vsz
- 16, 0);
644 void write_fp_dreg(DisasContext
*s
, int reg
, TCGv_i64 v
)
646 unsigned ofs
= fp_reg_offset(s
, reg
, MO_64
);
648 tcg_gen_st_i64(v
, cpu_env
, ofs
);
649 clear_vec_high(s
, false, reg
);
652 static void write_fp_sreg(DisasContext
*s
, int reg
, TCGv_i32 v
)
654 TCGv_i64 tmp
= tcg_temp_new_i64();
656 tcg_gen_extu_i32_i64(tmp
, v
);
657 write_fp_dreg(s
, reg
, tmp
);
658 tcg_temp_free_i64(tmp
);
661 TCGv_ptr
get_fpstatus_ptr(bool is_f16
)
663 TCGv_ptr statusptr
= tcg_temp_new_ptr();
666 /* In A64 all instructions (both FP and Neon) use the FPCR; there
667 * is no equivalent of the A32 Neon "standard FPSCR value".
668 * However half-precision operations operate under a different
669 * FZ16 flag and use vfp.fp_status_f16 instead of vfp.fp_status.
672 offset
= offsetof(CPUARMState
, vfp
.fp_status_f16
);
674 offset
= offsetof(CPUARMState
, vfp
.fp_status
);
676 tcg_gen_addi_ptr(statusptr
, cpu_env
, offset
);
680 /* Expand a 2-operand AdvSIMD vector operation using an expander function. */
681 static void gen_gvec_fn2(DisasContext
*s
, bool is_q
, int rd
, int rn
,
682 GVecGen2Fn
*gvec_fn
, int vece
)
684 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
685 is_q
? 16 : 8, vec_full_reg_size(s
));
688 /* Expand a 2-operand + immediate AdvSIMD vector operation using
689 * an expander function.
691 static void gen_gvec_fn2i(DisasContext
*s
, bool is_q
, int rd
, int rn
,
692 int64_t imm
, GVecGen2iFn
*gvec_fn
, int vece
)
694 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
695 imm
, is_q
? 16 : 8, vec_full_reg_size(s
));
698 /* Expand a 3-operand AdvSIMD vector operation using an expander function. */
699 static void gen_gvec_fn3(DisasContext
*s
, bool is_q
, int rd
, int rn
, int rm
,
700 GVecGen3Fn
*gvec_fn
, int vece
)
702 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
703 vec_full_reg_offset(s
, rm
), is_q
? 16 : 8, vec_full_reg_size(s
));
706 /* Expand a 2-operand + immediate AdvSIMD vector operation using
709 static void gen_gvec_op2i(DisasContext
*s
, bool is_q
, int rd
,
710 int rn
, int64_t imm
, const GVecGen2i
*gvec_op
)
712 tcg_gen_gvec_2i(vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
713 is_q
? 16 : 8, vec_full_reg_size(s
), imm
, gvec_op
);
716 /* Expand a 3-operand AdvSIMD vector operation using an op descriptor. */
717 static void gen_gvec_op3(DisasContext
*s
, bool is_q
, int rd
,
718 int rn
, int rm
, const GVecGen3
*gvec_op
)
720 tcg_gen_gvec_3(vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
721 vec_full_reg_offset(s
, rm
), is_q
? 16 : 8,
722 vec_full_reg_size(s
), gvec_op
);
725 /* Expand a 3-operand operation using an out-of-line helper. */
726 static void gen_gvec_op3_ool(DisasContext
*s
, bool is_q
, int rd
,
727 int rn
, int rm
, int data
, gen_helper_gvec_3
*fn
)
729 tcg_gen_gvec_3_ool(vec_full_reg_offset(s
, rd
),
730 vec_full_reg_offset(s
, rn
),
731 vec_full_reg_offset(s
, rm
),
732 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
735 /* Expand a 3-operand + env pointer operation using
736 * an out-of-line helper.
738 static void gen_gvec_op3_env(DisasContext
*s
, bool is_q
, int rd
,
739 int rn
, int rm
, gen_helper_gvec_3_ptr
*fn
)
741 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
742 vec_full_reg_offset(s
, rn
),
743 vec_full_reg_offset(s
, rm
), cpu_env
,
744 is_q
? 16 : 8, vec_full_reg_size(s
), 0, fn
);
747 /* Expand a 3-operand + fpstatus pointer + simd data value operation using
748 * an out-of-line helper.
750 static void gen_gvec_op3_fpst(DisasContext
*s
, bool is_q
, int rd
, int rn
,
751 int rm
, bool is_fp16
, int data
,
752 gen_helper_gvec_3_ptr
*fn
)
754 TCGv_ptr fpst
= get_fpstatus_ptr(is_fp16
);
755 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
756 vec_full_reg_offset(s
, rn
),
757 vec_full_reg_offset(s
, rm
), fpst
,
758 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
759 tcg_temp_free_ptr(fpst
);
762 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
763 * than the 32 bit equivalent.
765 static inline void gen_set_NZ64(TCGv_i64 result
)
767 tcg_gen_extr_i64_i32(cpu_ZF
, cpu_NF
, result
);
768 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, cpu_NF
);
771 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
772 static inline void gen_logic_CC(int sf
, TCGv_i64 result
)
775 gen_set_NZ64(result
);
777 tcg_gen_extrl_i64_i32(cpu_ZF
, result
);
778 tcg_gen_mov_i32(cpu_NF
, cpu_ZF
);
780 tcg_gen_movi_i32(cpu_CF
, 0);
781 tcg_gen_movi_i32(cpu_VF
, 0);
784 /* dest = T0 + T1; compute C, N, V and Z flags */
785 static void gen_add_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
788 TCGv_i64 result
, flag
, tmp
;
789 result
= tcg_temp_new_i64();
790 flag
= tcg_temp_new_i64();
791 tmp
= tcg_temp_new_i64();
793 tcg_gen_movi_i64(tmp
, 0);
794 tcg_gen_add2_i64(result
, flag
, t0
, tmp
, t1
, tmp
);
796 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
798 gen_set_NZ64(result
);
800 tcg_gen_xor_i64(flag
, result
, t0
);
801 tcg_gen_xor_i64(tmp
, t0
, t1
);
802 tcg_gen_andc_i64(flag
, flag
, tmp
);
803 tcg_temp_free_i64(tmp
);
804 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
806 tcg_gen_mov_i64(dest
, result
);
807 tcg_temp_free_i64(result
);
808 tcg_temp_free_i64(flag
);
810 /* 32 bit arithmetic */
811 TCGv_i32 t0_32
= tcg_temp_new_i32();
812 TCGv_i32 t1_32
= tcg_temp_new_i32();
813 TCGv_i32 tmp
= tcg_temp_new_i32();
815 tcg_gen_movi_i32(tmp
, 0);
816 tcg_gen_extrl_i64_i32(t0_32
, t0
);
817 tcg_gen_extrl_i64_i32(t1_32
, t1
);
818 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, t1_32
, tmp
);
819 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
820 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
821 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
822 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
823 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
825 tcg_temp_free_i32(tmp
);
826 tcg_temp_free_i32(t0_32
);
827 tcg_temp_free_i32(t1_32
);
831 /* dest = T0 - T1; compute C, N, V and Z flags */
832 static void gen_sub_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
835 /* 64 bit arithmetic */
836 TCGv_i64 result
, flag
, tmp
;
838 result
= tcg_temp_new_i64();
839 flag
= tcg_temp_new_i64();
840 tcg_gen_sub_i64(result
, t0
, t1
);
842 gen_set_NZ64(result
);
844 tcg_gen_setcond_i64(TCG_COND_GEU
, flag
, t0
, t1
);
845 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
847 tcg_gen_xor_i64(flag
, result
, t0
);
848 tmp
= tcg_temp_new_i64();
849 tcg_gen_xor_i64(tmp
, t0
, t1
);
850 tcg_gen_and_i64(flag
, flag
, tmp
);
851 tcg_temp_free_i64(tmp
);
852 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
853 tcg_gen_mov_i64(dest
, result
);
854 tcg_temp_free_i64(flag
);
855 tcg_temp_free_i64(result
);
857 /* 32 bit arithmetic */
858 TCGv_i32 t0_32
= tcg_temp_new_i32();
859 TCGv_i32 t1_32
= tcg_temp_new_i32();
862 tcg_gen_extrl_i64_i32(t0_32
, t0
);
863 tcg_gen_extrl_i64_i32(t1_32
, t1
);
864 tcg_gen_sub_i32(cpu_NF
, t0_32
, t1_32
);
865 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
866 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0_32
, t1_32
);
867 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
868 tmp
= tcg_temp_new_i32();
869 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
870 tcg_temp_free_i32(t0_32
);
871 tcg_temp_free_i32(t1_32
);
872 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
873 tcg_temp_free_i32(tmp
);
874 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
878 /* dest = T0 + T1 + CF; do not compute flags. */
879 static void gen_adc(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
881 TCGv_i64 flag
= tcg_temp_new_i64();
882 tcg_gen_extu_i32_i64(flag
, cpu_CF
);
883 tcg_gen_add_i64(dest
, t0
, t1
);
884 tcg_gen_add_i64(dest
, dest
, flag
);
885 tcg_temp_free_i64(flag
);
888 tcg_gen_ext32u_i64(dest
, dest
);
892 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
893 static void gen_adc_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
896 TCGv_i64 result
, cf_64
, vf_64
, tmp
;
897 result
= tcg_temp_new_i64();
898 cf_64
= tcg_temp_new_i64();
899 vf_64
= tcg_temp_new_i64();
900 tmp
= tcg_const_i64(0);
902 tcg_gen_extu_i32_i64(cf_64
, cpu_CF
);
903 tcg_gen_add2_i64(result
, cf_64
, t0
, tmp
, cf_64
, tmp
);
904 tcg_gen_add2_i64(result
, cf_64
, result
, cf_64
, t1
, tmp
);
905 tcg_gen_extrl_i64_i32(cpu_CF
, cf_64
);
906 gen_set_NZ64(result
);
908 tcg_gen_xor_i64(vf_64
, result
, t0
);
909 tcg_gen_xor_i64(tmp
, t0
, t1
);
910 tcg_gen_andc_i64(vf_64
, vf_64
, tmp
);
911 tcg_gen_extrh_i64_i32(cpu_VF
, vf_64
);
913 tcg_gen_mov_i64(dest
, result
);
915 tcg_temp_free_i64(tmp
);
916 tcg_temp_free_i64(vf_64
);
917 tcg_temp_free_i64(cf_64
);
918 tcg_temp_free_i64(result
);
920 TCGv_i32 t0_32
, t1_32
, tmp
;
921 t0_32
= tcg_temp_new_i32();
922 t1_32
= tcg_temp_new_i32();
923 tmp
= tcg_const_i32(0);
925 tcg_gen_extrl_i64_i32(t0_32
, t0
);
926 tcg_gen_extrl_i64_i32(t1_32
, t1
);
927 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, cpu_CF
, tmp
);
928 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1_32
, tmp
);
930 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
931 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
932 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
933 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
934 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
936 tcg_temp_free_i32(tmp
);
937 tcg_temp_free_i32(t1_32
);
938 tcg_temp_free_i32(t0_32
);
943 * Load/Store generators
947 * Store from GPR register to memory.
949 static void do_gpr_st_memidx(DisasContext
*s
, TCGv_i64 source
,
950 TCGv_i64 tcg_addr
, int size
, int memidx
,
952 unsigned int iss_srt
,
953 bool iss_sf
, bool iss_ar
)
956 tcg_gen_qemu_st_i64(source
, tcg_addr
, memidx
, s
->be_data
+ size
);
961 syn
= syn_data_abort_with_iss(0,
967 0, 0, 0, 0, 0, false);
968 disas_set_insn_syndrome(s
, syn
);
972 static void do_gpr_st(DisasContext
*s
, TCGv_i64 source
,
973 TCGv_i64 tcg_addr
, int size
,
975 unsigned int iss_srt
,
976 bool iss_sf
, bool iss_ar
)
978 do_gpr_st_memidx(s
, source
, tcg_addr
, size
, get_mem_index(s
),
979 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
983 * Load from memory to GPR register
985 static void do_gpr_ld_memidx(DisasContext
*s
,
986 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
987 int size
, bool is_signed
,
988 bool extend
, int memidx
,
989 bool iss_valid
, unsigned int iss_srt
,
990 bool iss_sf
, bool iss_ar
)
992 TCGMemOp memop
= s
->be_data
+ size
;
1000 tcg_gen_qemu_ld_i64(dest
, tcg_addr
, memidx
, memop
);
1002 if (extend
&& is_signed
) {
1004 tcg_gen_ext32u_i64(dest
, dest
);
1010 syn
= syn_data_abort_with_iss(0,
1016 0, 0, 0, 0, 0, false);
1017 disas_set_insn_syndrome(s
, syn
);
1021 static void do_gpr_ld(DisasContext
*s
,
1022 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
1023 int size
, bool is_signed
, bool extend
,
1024 bool iss_valid
, unsigned int iss_srt
,
1025 bool iss_sf
, bool iss_ar
)
1027 do_gpr_ld_memidx(s
, dest
, tcg_addr
, size
, is_signed
, extend
,
1029 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
1033 * Store from FP register to memory
1035 static void do_fp_st(DisasContext
*s
, int srcidx
, TCGv_i64 tcg_addr
, int size
)
1037 /* This writes the bottom N bits of a 128 bit wide vector to memory */
1038 TCGv_i64 tmp
= tcg_temp_new_i64();
1039 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_offset(s
, srcidx
, MO_64
));
1041 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
),
1044 bool be
= s
->be_data
== MO_BE
;
1045 TCGv_i64 tcg_hiaddr
= tcg_temp_new_i64();
1047 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
1048 tcg_gen_qemu_st_i64(tmp
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
1050 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, srcidx
));
1051 tcg_gen_qemu_st_i64(tmp
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
1053 tcg_temp_free_i64(tcg_hiaddr
);
1056 tcg_temp_free_i64(tmp
);
1060 * Load from memory to FP register
1062 static void do_fp_ld(DisasContext
*s
, int destidx
, TCGv_i64 tcg_addr
, int size
)
1064 /* This always zero-extends and writes to a full 128 bit wide vector */
1065 TCGv_i64 tmplo
= tcg_temp_new_i64();
1069 TCGMemOp memop
= s
->be_data
+ size
;
1070 tmphi
= tcg_const_i64(0);
1071 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), memop
);
1073 bool be
= s
->be_data
== MO_BE
;
1074 TCGv_i64 tcg_hiaddr
;
1076 tmphi
= tcg_temp_new_i64();
1077 tcg_hiaddr
= tcg_temp_new_i64();
1079 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
1080 tcg_gen_qemu_ld_i64(tmplo
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
1082 tcg_gen_qemu_ld_i64(tmphi
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
1084 tcg_temp_free_i64(tcg_hiaddr
);
1087 tcg_gen_st_i64(tmplo
, cpu_env
, fp_reg_offset(s
, destidx
, MO_64
));
1088 tcg_gen_st_i64(tmphi
, cpu_env
, fp_reg_hi_offset(s
, destidx
));
1090 tcg_temp_free_i64(tmplo
);
1091 tcg_temp_free_i64(tmphi
);
1093 clear_vec_high(s
, true, destidx
);
1097 * Vector load/store helpers.
1099 * The principal difference between this and a FP load is that we don't
1100 * zero extend as we are filling a partial chunk of the vector register.
1101 * These functions don't support 128 bit loads/stores, which would be
1102 * normal load/store operations.
1104 * The _i32 versions are useful when operating on 32 bit quantities
1105 * (eg for floating point single or using Neon helper functions).
1108 /* Get value of an element within a vector register */
1109 static void read_vec_element(DisasContext
*s
, TCGv_i64 tcg_dest
, int srcidx
,
1110 int element
, TCGMemOp memop
)
1112 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
1115 tcg_gen_ld8u_i64(tcg_dest
, cpu_env
, vect_off
);
1118 tcg_gen_ld16u_i64(tcg_dest
, cpu_env
, vect_off
);
1121 tcg_gen_ld32u_i64(tcg_dest
, cpu_env
, vect_off
);
1124 tcg_gen_ld8s_i64(tcg_dest
, cpu_env
, vect_off
);
1127 tcg_gen_ld16s_i64(tcg_dest
, cpu_env
, vect_off
);
1130 tcg_gen_ld32s_i64(tcg_dest
, cpu_env
, vect_off
);
1134 tcg_gen_ld_i64(tcg_dest
, cpu_env
, vect_off
);
1137 g_assert_not_reached();
1141 static void read_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_dest
, int srcidx
,
1142 int element
, TCGMemOp memop
)
1144 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
1147 tcg_gen_ld8u_i32(tcg_dest
, cpu_env
, vect_off
);
1150 tcg_gen_ld16u_i32(tcg_dest
, cpu_env
, vect_off
);
1153 tcg_gen_ld8s_i32(tcg_dest
, cpu_env
, vect_off
);
1156 tcg_gen_ld16s_i32(tcg_dest
, cpu_env
, vect_off
);
1160 tcg_gen_ld_i32(tcg_dest
, cpu_env
, vect_off
);
1163 g_assert_not_reached();
1167 /* Set value of an element within a vector register */
1168 static void write_vec_element(DisasContext
*s
, TCGv_i64 tcg_src
, int destidx
,
1169 int element
, TCGMemOp memop
)
1171 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1174 tcg_gen_st8_i64(tcg_src
, cpu_env
, vect_off
);
1177 tcg_gen_st16_i64(tcg_src
, cpu_env
, vect_off
);
1180 tcg_gen_st32_i64(tcg_src
, cpu_env
, vect_off
);
1183 tcg_gen_st_i64(tcg_src
, cpu_env
, vect_off
);
1186 g_assert_not_reached();
1190 static void write_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_src
,
1191 int destidx
, int element
, TCGMemOp memop
)
1193 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1196 tcg_gen_st8_i32(tcg_src
, cpu_env
, vect_off
);
1199 tcg_gen_st16_i32(tcg_src
, cpu_env
, vect_off
);
1202 tcg_gen_st_i32(tcg_src
, cpu_env
, vect_off
);
1205 g_assert_not_reached();
1209 /* Store from vector register to memory */
1210 static void do_vec_st(DisasContext
*s
, int srcidx
, int element
,
1211 TCGv_i64 tcg_addr
, int size
, TCGMemOp endian
)
1213 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1215 read_vec_element(s
, tcg_tmp
, srcidx
, element
, size
);
1216 tcg_gen_qemu_st_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), endian
| size
);
1218 tcg_temp_free_i64(tcg_tmp
);
1221 /* Load from memory to vector register */
1222 static void do_vec_ld(DisasContext
*s
, int destidx
, int element
,
1223 TCGv_i64 tcg_addr
, int size
, TCGMemOp endian
)
1225 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1227 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), endian
| size
);
1228 write_vec_element(s
, tcg_tmp
, destidx
, element
, size
);
1230 tcg_temp_free_i64(tcg_tmp
);
1233 /* Check that FP/Neon access is enabled. If it is, return
1234 * true. If not, emit code to generate an appropriate exception,
1235 * and return false; the caller should not emit any code for
1236 * the instruction. Note that this check must happen after all
1237 * unallocated-encoding checks (otherwise the syndrome information
1238 * for the resulting exception will be incorrect).
1240 static inline bool fp_access_check(DisasContext
*s
)
1242 assert(!s
->fp_access_checked
);
1243 s
->fp_access_checked
= true;
1245 if (!s
->fp_excp_el
) {
1249 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_fp_access_trap(1, 0xe, false),
1254 /* Check that SVE access is enabled. If it is, return true.
1255 * If not, emit code to generate an appropriate exception and return false.
1257 bool sve_access_check(DisasContext
*s
)
1259 if (s
->sve_excp_el
) {
1260 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_sve_access_trap(),
1264 return fp_access_check(s
);
1268 * This utility function is for doing register extension with an
1269 * optional shift. You will likely want to pass a temporary for the
1270 * destination register. See DecodeRegExtend() in the ARM ARM.
1272 static void ext_and_shift_reg(TCGv_i64 tcg_out
, TCGv_i64 tcg_in
,
1273 int option
, unsigned int shift
)
1275 int extsize
= extract32(option
, 0, 2);
1276 bool is_signed
= extract32(option
, 2, 1);
1281 tcg_gen_ext8s_i64(tcg_out
, tcg_in
);
1284 tcg_gen_ext16s_i64(tcg_out
, tcg_in
);
1287 tcg_gen_ext32s_i64(tcg_out
, tcg_in
);
1290 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1296 tcg_gen_ext8u_i64(tcg_out
, tcg_in
);
1299 tcg_gen_ext16u_i64(tcg_out
, tcg_in
);
1302 tcg_gen_ext32u_i64(tcg_out
, tcg_in
);
1305 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1311 tcg_gen_shli_i64(tcg_out
, tcg_out
, shift
);
1315 static inline void gen_check_sp_alignment(DisasContext
*s
)
1317 /* The AArch64 architecture mandates that (if enabled via PSTATE
1318 * or SCTLR bits) there is a check that SP is 16-aligned on every
1319 * SP-relative load or store (with an exception generated if it is not).
1320 * In line with general QEMU practice regarding misaligned accesses,
1321 * we omit these checks for the sake of guest program performance.
1322 * This function is provided as a hook so we can more easily add these
1323 * checks in future (possibly as a "favour catching guest program bugs
1324 * over speed" user selectable option).
1329 * This provides a simple table based table lookup decoder. It is
1330 * intended to be used when the relevant bits for decode are too
1331 * awkwardly placed and switch/if based logic would be confusing and
1332 * deeply nested. Since it's a linear search through the table, tables
1333 * should be kept small.
1335 * It returns the first handler where insn & mask == pattern, or
1336 * NULL if there is no match.
1337 * The table is terminated by an empty mask (i.e. 0)
1339 static inline AArch64DecodeFn
*lookup_disas_fn(const AArch64DecodeTable
*table
,
1342 const AArch64DecodeTable
*tptr
= table
;
1344 while (tptr
->mask
) {
1345 if ((insn
& tptr
->mask
) == tptr
->pattern
) {
1346 return tptr
->disas_fn
;
1354 * The instruction disassembly implemented here matches
1355 * the instruction encoding classifications in chapter C4
1356 * of the ARM Architecture Reference Manual (DDI0487B_a);
1357 * classification names and decode diagrams here should generally
1358 * match up with those in the manual.
1361 /* Unconditional branch (immediate)
1363 * +----+-----------+-------------------------------------+
1364 * | op | 0 0 1 0 1 | imm26 |
1365 * +----+-----------+-------------------------------------+
1367 static void disas_uncond_b_imm(DisasContext
*s
, uint32_t insn
)
1369 uint64_t addr
= s
->pc
+ sextract32(insn
, 0, 26) * 4 - 4;
1371 if (insn
& (1U << 31)) {
1372 /* BL Branch with link */
1373 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
1376 /* B Branch / BL Branch with link */
1378 gen_goto_tb(s
, 0, addr
);
1381 /* Compare and branch (immediate)
1382 * 31 30 25 24 23 5 4 0
1383 * +----+-------------+----+---------------------+--------+
1384 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
1385 * +----+-------------+----+---------------------+--------+
1387 static void disas_comp_b_imm(DisasContext
*s
, uint32_t insn
)
1389 unsigned int sf
, op
, rt
;
1391 TCGLabel
*label_match
;
1394 sf
= extract32(insn
, 31, 1);
1395 op
= extract32(insn
, 24, 1); /* 0: CBZ; 1: CBNZ */
1396 rt
= extract32(insn
, 0, 5);
1397 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1399 tcg_cmp
= read_cpu_reg(s
, rt
, sf
);
1400 label_match
= gen_new_label();
1403 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1404 tcg_cmp
, 0, label_match
);
1406 gen_goto_tb(s
, 0, s
->pc
);
1407 gen_set_label(label_match
);
1408 gen_goto_tb(s
, 1, addr
);
1411 /* Test and branch (immediate)
1412 * 31 30 25 24 23 19 18 5 4 0
1413 * +----+-------------+----+-------+-------------+------+
1414 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
1415 * +----+-------------+----+-------+-------------+------+
1417 static void disas_test_b_imm(DisasContext
*s
, uint32_t insn
)
1419 unsigned int bit_pos
, op
, rt
;
1421 TCGLabel
*label_match
;
1424 bit_pos
= (extract32(insn
, 31, 1) << 5) | extract32(insn
, 19, 5);
1425 op
= extract32(insn
, 24, 1); /* 0: TBZ; 1: TBNZ */
1426 addr
= s
->pc
+ sextract32(insn
, 5, 14) * 4 - 4;
1427 rt
= extract32(insn
, 0, 5);
1429 tcg_cmp
= tcg_temp_new_i64();
1430 tcg_gen_andi_i64(tcg_cmp
, cpu_reg(s
, rt
), (1ULL << bit_pos
));
1431 label_match
= gen_new_label();
1434 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1435 tcg_cmp
, 0, label_match
);
1436 tcg_temp_free_i64(tcg_cmp
);
1437 gen_goto_tb(s
, 0, s
->pc
);
1438 gen_set_label(label_match
);
1439 gen_goto_tb(s
, 1, addr
);
1442 /* Conditional branch (immediate)
1443 * 31 25 24 23 5 4 3 0
1444 * +---------------+----+---------------------+----+------+
1445 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
1446 * +---------------+----+---------------------+----+------+
1448 static void disas_cond_b_imm(DisasContext
*s
, uint32_t insn
)
1453 if ((insn
& (1 << 4)) || (insn
& (1 << 24))) {
1454 unallocated_encoding(s
);
1457 addr
= s
->pc
+ sextract32(insn
, 5, 19) * 4 - 4;
1458 cond
= extract32(insn
, 0, 4);
1462 /* genuinely conditional branches */
1463 TCGLabel
*label_match
= gen_new_label();
1464 arm_gen_test_cc(cond
, label_match
);
1465 gen_goto_tb(s
, 0, s
->pc
);
1466 gen_set_label(label_match
);
1467 gen_goto_tb(s
, 1, addr
);
1469 /* 0xe and 0xf are both "always" conditions */
1470 gen_goto_tb(s
, 0, addr
);
1474 /* HINT instruction group, including various allocated HINTs */
1475 static void handle_hint(DisasContext
*s
, uint32_t insn
,
1476 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1478 unsigned int selector
= crm
<< 3 | op2
;
1481 unallocated_encoding(s
);
1486 case 0b00000: /* NOP */
1488 case 0b00011: /* WFI */
1489 s
->base
.is_jmp
= DISAS_WFI
;
1491 case 0b00001: /* YIELD */
1492 /* When running in MTTCG we don't generate jumps to the yield and
1493 * WFE helpers as it won't affect the scheduling of other vCPUs.
1494 * If we wanted to more completely model WFE/SEV so we don't busy
1495 * spin unnecessarily we would need to do something more involved.
1497 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1498 s
->base
.is_jmp
= DISAS_YIELD
;
1501 case 0b00010: /* WFE */
1502 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1503 s
->base
.is_jmp
= DISAS_WFE
;
1506 case 0b00100: /* SEV */
1507 case 0b00101: /* SEVL */
1508 /* we treat all as NOP at least for now */
1510 case 0b00111: /* XPACLRI */
1511 if (s
->pauth_active
) {
1512 gen_helper_xpaci(cpu_X
[30], cpu_env
, cpu_X
[30]);
1515 case 0b01000: /* PACIA1716 */
1516 if (s
->pauth_active
) {
1517 gen_helper_pacia(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1520 case 0b01010: /* PACIB1716 */
1521 if (s
->pauth_active
) {
1522 gen_helper_pacib(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1525 case 0b01100: /* AUTIA1716 */
1526 if (s
->pauth_active
) {
1527 gen_helper_autia(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1530 case 0b01110: /* AUTIB1716 */
1531 if (s
->pauth_active
) {
1532 gen_helper_autib(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1535 case 0b11000: /* PACIAZ */
1536 if (s
->pauth_active
) {
1537 gen_helper_pacia(cpu_X
[30], cpu_env
, cpu_X
[30],
1538 new_tmp_a64_zero(s
));
1541 case 0b11001: /* PACIASP */
1542 if (s
->pauth_active
) {
1543 gen_helper_pacia(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1546 case 0b11010: /* PACIBZ */
1547 if (s
->pauth_active
) {
1548 gen_helper_pacib(cpu_X
[30], cpu_env
, cpu_X
[30],
1549 new_tmp_a64_zero(s
));
1552 case 0b11011: /* PACIBSP */
1553 if (s
->pauth_active
) {
1554 gen_helper_pacib(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1557 case 0b11100: /* AUTIAZ */
1558 if (s
->pauth_active
) {
1559 gen_helper_autia(cpu_X
[30], cpu_env
, cpu_X
[30],
1560 new_tmp_a64_zero(s
));
1563 case 0b11101: /* AUTIASP */
1564 if (s
->pauth_active
) {
1565 gen_helper_autia(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1568 case 0b11110: /* AUTIBZ */
1569 if (s
->pauth_active
) {
1570 gen_helper_autib(cpu_X
[30], cpu_env
, cpu_X
[30],
1571 new_tmp_a64_zero(s
));
1574 case 0b11111: /* AUTIBSP */
1575 if (s
->pauth_active
) {
1576 gen_helper_autib(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1580 /* default specified as NOP equivalent */
1585 static void gen_clrex(DisasContext
*s
, uint32_t insn
)
1587 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1590 /* CLREX, DSB, DMB, ISB */
1591 static void handle_sync(DisasContext
*s
, uint32_t insn
,
1592 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1597 unallocated_encoding(s
);
1608 case 1: /* MBReqTypes_Reads */
1609 bar
= TCG_BAR_SC
| TCG_MO_LD_LD
| TCG_MO_LD_ST
;
1611 case 2: /* MBReqTypes_Writes */
1612 bar
= TCG_BAR_SC
| TCG_MO_ST_ST
;
1614 default: /* MBReqTypes_All */
1615 bar
= TCG_BAR_SC
| TCG_MO_ALL
;
1621 /* We need to break the TB after this insn to execute
1622 * a self-modified code correctly and also to take
1623 * any pending interrupts immediately.
1626 gen_goto_tb(s
, 0, s
->pc
);
1629 unallocated_encoding(s
);
1634 /* MSR (immediate) - move immediate to processor state field */
1635 static void handle_msr_i(DisasContext
*s
, uint32_t insn
,
1636 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1638 int op
= op1
<< 3 | op2
;
1640 case 0x05: /* SPSel */
1641 if (s
->current_el
== 0) {
1642 unallocated_encoding(s
);
1646 case 0x1e: /* DAIFSet */
1647 case 0x1f: /* DAIFClear */
1649 TCGv_i32 tcg_imm
= tcg_const_i32(crm
);
1650 TCGv_i32 tcg_op
= tcg_const_i32(op
);
1651 gen_a64_set_pc_im(s
->pc
- 4);
1652 gen_helper_msr_i_pstate(cpu_env
, tcg_op
, tcg_imm
);
1653 tcg_temp_free_i32(tcg_imm
);
1654 tcg_temp_free_i32(tcg_op
);
1655 /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */
1656 gen_a64_set_pc_im(s
->pc
);
1657 s
->base
.is_jmp
= (op
== 0x1f ? DISAS_EXIT
: DISAS_JUMP
);
1661 unallocated_encoding(s
);
1666 static void gen_get_nzcv(TCGv_i64 tcg_rt
)
1668 TCGv_i32 tmp
= tcg_temp_new_i32();
1669 TCGv_i32 nzcv
= tcg_temp_new_i32();
1671 /* build bit 31, N */
1672 tcg_gen_andi_i32(nzcv
, cpu_NF
, (1U << 31));
1673 /* build bit 30, Z */
1674 tcg_gen_setcondi_i32(TCG_COND_EQ
, tmp
, cpu_ZF
, 0);
1675 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 30, 1);
1676 /* build bit 29, C */
1677 tcg_gen_deposit_i32(nzcv
, nzcv
, cpu_CF
, 29, 1);
1678 /* build bit 28, V */
1679 tcg_gen_shri_i32(tmp
, cpu_VF
, 31);
1680 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 28, 1);
1681 /* generate result */
1682 tcg_gen_extu_i32_i64(tcg_rt
, nzcv
);
1684 tcg_temp_free_i32(nzcv
);
1685 tcg_temp_free_i32(tmp
);
1688 static void gen_set_nzcv(TCGv_i64 tcg_rt
)
1691 TCGv_i32 nzcv
= tcg_temp_new_i32();
1693 /* take NZCV from R[t] */
1694 tcg_gen_extrl_i64_i32(nzcv
, tcg_rt
);
1697 tcg_gen_andi_i32(cpu_NF
, nzcv
, (1U << 31));
1699 tcg_gen_andi_i32(cpu_ZF
, nzcv
, (1 << 30));
1700 tcg_gen_setcondi_i32(TCG_COND_EQ
, cpu_ZF
, cpu_ZF
, 0);
1702 tcg_gen_andi_i32(cpu_CF
, nzcv
, (1 << 29));
1703 tcg_gen_shri_i32(cpu_CF
, cpu_CF
, 29);
1705 tcg_gen_andi_i32(cpu_VF
, nzcv
, (1 << 28));
1706 tcg_gen_shli_i32(cpu_VF
, cpu_VF
, 3);
1707 tcg_temp_free_i32(nzcv
);
1710 /* MRS - move from system register
1711 * MSR (register) - move to system register
1714 * These are all essentially the same insn in 'read' and 'write'
1715 * versions, with varying op0 fields.
1717 static void handle_sys(DisasContext
*s
, uint32_t insn
, bool isread
,
1718 unsigned int op0
, unsigned int op1
, unsigned int op2
,
1719 unsigned int crn
, unsigned int crm
, unsigned int rt
)
1721 const ARMCPRegInfo
*ri
;
1724 ri
= get_arm_cp_reginfo(s
->cp_regs
,
1725 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP
,
1726 crn
, crm
, op0
, op1
, op2
));
1729 /* Unknown register; this might be a guest error or a QEMU
1730 * unimplemented feature.
1732 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch64 "
1733 "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
1734 isread
? "read" : "write", op0
, op1
, crn
, crm
, op2
);
1735 unallocated_encoding(s
);
1739 /* Check access permissions */
1740 if (!cp_access_ok(s
->current_el
, ri
, isread
)) {
1741 unallocated_encoding(s
);
1746 /* Emit code to perform further access permissions checks at
1747 * runtime; this may result in an exception.
1750 TCGv_i32 tcg_syn
, tcg_isread
;
1753 gen_a64_set_pc_im(s
->pc
- 4);
1754 tmpptr
= tcg_const_ptr(ri
);
1755 syndrome
= syn_aa64_sysregtrap(op0
, op1
, op2
, crn
, crm
, rt
, isread
);
1756 tcg_syn
= tcg_const_i32(syndrome
);
1757 tcg_isread
= tcg_const_i32(isread
);
1758 gen_helper_access_check_cp_reg(cpu_env
, tmpptr
, tcg_syn
, tcg_isread
);
1759 tcg_temp_free_ptr(tmpptr
);
1760 tcg_temp_free_i32(tcg_syn
);
1761 tcg_temp_free_i32(tcg_isread
);
1764 /* Handle special cases first */
1765 switch (ri
->type
& ~(ARM_CP_FLAG_MASK
& ~ARM_CP_SPECIAL
)) {
1769 tcg_rt
= cpu_reg(s
, rt
);
1771 gen_get_nzcv(tcg_rt
);
1773 gen_set_nzcv(tcg_rt
);
1776 case ARM_CP_CURRENTEL
:
1777 /* Reads as current EL value from pstate, which is
1778 * guaranteed to be constant by the tb flags.
1780 tcg_rt
= cpu_reg(s
, rt
);
1781 tcg_gen_movi_i64(tcg_rt
, s
->current_el
<< 2);
1784 /* Writes clear the aligned block of memory which rt points into. */
1785 tcg_rt
= cpu_reg(s
, rt
);
1786 gen_helper_dc_zva(cpu_env
, tcg_rt
);
1791 if ((ri
->type
& ARM_CP_FPU
) && !fp_access_check(s
)) {
1793 } else if ((ri
->type
& ARM_CP_SVE
) && !sve_access_check(s
)) {
1797 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1801 tcg_rt
= cpu_reg(s
, rt
);
1804 if (ri
->type
& ARM_CP_CONST
) {
1805 tcg_gen_movi_i64(tcg_rt
, ri
->resetvalue
);
1806 } else if (ri
->readfn
) {
1808 tmpptr
= tcg_const_ptr(ri
);
1809 gen_helper_get_cp_reg64(tcg_rt
, cpu_env
, tmpptr
);
1810 tcg_temp_free_ptr(tmpptr
);
1812 tcg_gen_ld_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1815 if (ri
->type
& ARM_CP_CONST
) {
1816 /* If not forbidden by access permissions, treat as WI */
1818 } else if (ri
->writefn
) {
1820 tmpptr
= tcg_const_ptr(ri
);
1821 gen_helper_set_cp_reg64(cpu_env
, tmpptr
, tcg_rt
);
1822 tcg_temp_free_ptr(tmpptr
);
1824 tcg_gen_st_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1828 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1829 /* I/O operations must end the TB here (whether read or write) */
1831 s
->base
.is_jmp
= DISAS_UPDATE
;
1832 } else if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
1833 /* We default to ending the TB on a coprocessor register write,
1834 * but allow this to be suppressed by the register definition
1835 * (usually only necessary to work around guest bugs).
1837 s
->base
.is_jmp
= DISAS_UPDATE
;
1842 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
1843 * +---------------------+---+-----+-----+-------+-------+-----+------+
1844 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
1845 * +---------------------+---+-----+-----+-------+-------+-----+------+
1847 static void disas_system(DisasContext
*s
, uint32_t insn
)
1849 unsigned int l
, op0
, op1
, crn
, crm
, op2
, rt
;
1850 l
= extract32(insn
, 21, 1);
1851 op0
= extract32(insn
, 19, 2);
1852 op1
= extract32(insn
, 16, 3);
1853 crn
= extract32(insn
, 12, 4);
1854 crm
= extract32(insn
, 8, 4);
1855 op2
= extract32(insn
, 5, 3);
1856 rt
= extract32(insn
, 0, 5);
1859 if (l
|| rt
!= 31) {
1860 unallocated_encoding(s
);
1864 case 2: /* HINT (including allocated hints like NOP, YIELD, etc) */
1865 handle_hint(s
, insn
, op1
, op2
, crm
);
1867 case 3: /* CLREX, DSB, DMB, ISB */
1868 handle_sync(s
, insn
, op1
, op2
, crm
);
1870 case 4: /* MSR (immediate) */
1871 handle_msr_i(s
, insn
, op1
, op2
, crm
);
1874 unallocated_encoding(s
);
1879 handle_sys(s
, insn
, l
, op0
, op1
, op2
, crn
, crm
, rt
);
1882 /* Exception generation
1884 * 31 24 23 21 20 5 4 2 1 0
1885 * +-----------------+-----+------------------------+-----+----+
1886 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
1887 * +-----------------------+------------------------+----------+
1889 static void disas_exc(DisasContext
*s
, uint32_t insn
)
1891 int opc
= extract32(insn
, 21, 3);
1892 int op2_ll
= extract32(insn
, 0, 5);
1893 int imm16
= extract32(insn
, 5, 16);
1898 /* For SVC, HVC and SMC we advance the single-step state
1899 * machine before taking the exception. This is architecturally
1900 * mandated, to ensure that single-stepping a system call
1901 * instruction works properly.
1906 gen_exception_insn(s
, 0, EXCP_SWI
, syn_aa64_svc(imm16
),
1907 default_exception_el(s
));
1910 if (s
->current_el
== 0) {
1911 unallocated_encoding(s
);
1914 /* The pre HVC helper handles cases when HVC gets trapped
1915 * as an undefined insn by runtime configuration.
1917 gen_a64_set_pc_im(s
->pc
- 4);
1918 gen_helper_pre_hvc(cpu_env
);
1920 gen_exception_insn(s
, 0, EXCP_HVC
, syn_aa64_hvc(imm16
), 2);
1923 if (s
->current_el
== 0) {
1924 unallocated_encoding(s
);
1927 gen_a64_set_pc_im(s
->pc
- 4);
1928 tmp
= tcg_const_i32(syn_aa64_smc(imm16
));
1929 gen_helper_pre_smc(cpu_env
, tmp
);
1930 tcg_temp_free_i32(tmp
);
1932 gen_exception_insn(s
, 0, EXCP_SMC
, syn_aa64_smc(imm16
), 3);
1935 unallocated_encoding(s
);
1941 unallocated_encoding(s
);
1945 gen_exception_bkpt_insn(s
, 4, syn_aa64_bkpt(imm16
));
1949 unallocated_encoding(s
);
1952 /* HLT. This has two purposes.
1953 * Architecturally, it is an external halting debug instruction.
1954 * Since QEMU doesn't implement external debug, we treat this as
1955 * it is required for halting debug disabled: it will UNDEF.
1956 * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
1958 if (semihosting_enabled() && imm16
== 0xf000) {
1959 #ifndef CONFIG_USER_ONLY
1960 /* In system mode, don't allow userspace access to semihosting,
1961 * to provide some semblance of security (and for consistency
1962 * with our 32-bit semihosting).
1964 if (s
->current_el
== 0) {
1965 unsupported_encoding(s
, insn
);
1969 gen_exception_internal_insn(s
, 0, EXCP_SEMIHOST
);
1971 unsupported_encoding(s
, insn
);
1975 if (op2_ll
< 1 || op2_ll
> 3) {
1976 unallocated_encoding(s
);
1979 /* DCPS1, DCPS2, DCPS3 */
1980 unsupported_encoding(s
, insn
);
1983 unallocated_encoding(s
);
1988 /* Unconditional branch (register)
1989 * 31 25 24 21 20 16 15 10 9 5 4 0
1990 * +---------------+-------+-------+-------+------+-------+
1991 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
1992 * +---------------+-------+-------+-------+------+-------+
1994 static void disas_uncond_b_reg(DisasContext
*s
, uint32_t insn
)
1996 unsigned int opc
, op2
, op3
, rn
, op4
;
1997 unsigned btype_mod
= 2; /* 0: BR, 1: BLR, 2: other */
2001 opc
= extract32(insn
, 21, 4);
2002 op2
= extract32(insn
, 16, 5);
2003 op3
= extract32(insn
, 10, 6);
2004 rn
= extract32(insn
, 5, 5);
2005 op4
= extract32(insn
, 0, 5);
2008 goto do_unallocated
;
2020 goto do_unallocated
;
2022 dst
= cpu_reg(s
, rn
);
2027 if (!dc_isar_feature(aa64_pauth
, s
)) {
2028 goto do_unallocated
;
2032 if (rn
!= 0x1f || op4
!= 0x1f) {
2033 goto do_unallocated
;
2036 modifier
= cpu_X
[31];
2038 /* BRAAZ, BRABZ, BLRAAZ, BLRABZ */
2040 goto do_unallocated
;
2042 modifier
= new_tmp_a64_zero(s
);
2044 if (s
->pauth_active
) {
2045 dst
= new_tmp_a64(s
);
2047 gen_helper_autia(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2049 gen_helper_autib(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2052 dst
= cpu_reg(s
, rn
);
2057 goto do_unallocated
;
2059 gen_a64_set_pc(s
, dst
);
2060 /* BLR also needs to load return address */
2062 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
2068 if (!dc_isar_feature(aa64_pauth
, s
)) {
2069 goto do_unallocated
;
2071 if ((op3
& ~1) != 2) {
2072 goto do_unallocated
;
2074 btype_mod
= opc
& 1;
2075 if (s
->pauth_active
) {
2076 dst
= new_tmp_a64(s
);
2077 modifier
= cpu_reg_sp(s
, op4
);
2079 gen_helper_autia(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2081 gen_helper_autib(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2084 dst
= cpu_reg(s
, rn
);
2086 gen_a64_set_pc(s
, dst
);
2087 /* BLRAA also needs to load return address */
2089 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->pc
);
2094 if (s
->current_el
== 0) {
2095 goto do_unallocated
;
2100 goto do_unallocated
;
2102 dst
= tcg_temp_new_i64();
2103 tcg_gen_ld_i64(dst
, cpu_env
,
2104 offsetof(CPUARMState
, elr_el
[s
->current_el
]));
2107 case 2: /* ERETAA */
2108 case 3: /* ERETAB */
2109 if (!dc_isar_feature(aa64_pauth
, s
)) {
2110 goto do_unallocated
;
2112 if (rn
!= 0x1f || op4
!= 0x1f) {
2113 goto do_unallocated
;
2115 dst
= tcg_temp_new_i64();
2116 tcg_gen_ld_i64(dst
, cpu_env
,
2117 offsetof(CPUARMState
, elr_el
[s
->current_el
]));
2118 if (s
->pauth_active
) {
2119 modifier
= cpu_X
[31];
2121 gen_helper_autia(dst
, cpu_env
, dst
, modifier
);
2123 gen_helper_autib(dst
, cpu_env
, dst
, modifier
);
2129 goto do_unallocated
;
2131 if (tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) {
2135 gen_helper_exception_return(cpu_env
, dst
);
2136 tcg_temp_free_i64(dst
);
2137 if (tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) {
2140 /* Must exit loop to check un-masked IRQs */
2141 s
->base
.is_jmp
= DISAS_EXIT
;
2145 if (op3
!= 0 || op4
!= 0 || rn
!= 0x1f) {
2146 goto do_unallocated
;
2148 unsupported_encoding(s
, insn
);
2154 unallocated_encoding(s
);
2158 switch (btype_mod
) {
2160 if (dc_isar_feature(aa64_bti
, s
)) {
2161 /* BR to {x16,x17} or !guard -> 1, else 3. */
2162 set_btype(s
, rn
== 16 || rn
== 17 || !s
->guarded_page
? 1 : 3);
2167 if (dc_isar_feature(aa64_bti
, s
)) {
2168 /* BLR sets BTYPE to 2, regardless of source guarded page. */
2173 default: /* RET or none of the above. */
2174 /* BTYPE will be set to 0 by normal end-of-insn processing. */
2178 s
->base
.is_jmp
= DISAS_JUMP
;
2181 /* Branches, exception generating and system instructions */
2182 static void disas_b_exc_sys(DisasContext
*s
, uint32_t insn
)
2184 switch (extract32(insn
, 25, 7)) {
2185 case 0x0a: case 0x0b:
2186 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
2187 disas_uncond_b_imm(s
, insn
);
2189 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
2190 disas_comp_b_imm(s
, insn
);
2192 case 0x1b: case 0x5b: /* Test & branch (immediate) */
2193 disas_test_b_imm(s
, insn
);
2195 case 0x2a: /* Conditional branch (immediate) */
2196 disas_cond_b_imm(s
, insn
);
2198 case 0x6a: /* Exception generation / System */
2199 if (insn
& (1 << 24)) {
2200 if (extract32(insn
, 22, 2) == 0) {
2201 disas_system(s
, insn
);
2203 unallocated_encoding(s
);
2209 case 0x6b: /* Unconditional branch (register) */
2210 disas_uncond_b_reg(s
, insn
);
2213 unallocated_encoding(s
);
2219 * Load/Store exclusive instructions are implemented by remembering
2220 * the value/address loaded, and seeing if these are the same
2221 * when the store is performed. This is not actually the architecturally
2222 * mandated semantics, but it works for typical guest code sequences
2223 * and avoids having to monitor regular stores.
2225 * The store exclusive uses the atomic cmpxchg primitives to avoid
2226 * races in multi-threaded linux-user and when MTTCG softmmu is
2229 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
2230 TCGv_i64 addr
, int size
, bool is_pair
)
2232 int idx
= get_mem_index(s
);
2233 TCGMemOp memop
= s
->be_data
;
2235 g_assert(size
<= 3);
2237 g_assert(size
>= 2);
2239 /* The pair must be single-copy atomic for the doubleword. */
2240 memop
|= MO_64
| MO_ALIGN
;
2241 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2242 if (s
->be_data
== MO_LE
) {
2243 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 0, 32);
2244 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 32, 32);
2246 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 32, 32);
2247 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 0, 32);
2250 /* The pair must be single-copy atomic for *each* doubleword, not
2251 the entire quadword, however it must be quadword aligned. */
2253 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
,
2254 memop
| MO_ALIGN_16
);
2256 TCGv_i64 addr2
= tcg_temp_new_i64();
2257 tcg_gen_addi_i64(addr2
, addr
, 8);
2258 tcg_gen_qemu_ld_i64(cpu_exclusive_high
, addr2
, idx
, memop
);
2259 tcg_temp_free_i64(addr2
);
2261 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2262 tcg_gen_mov_i64(cpu_reg(s
, rt2
), cpu_exclusive_high
);
2265 memop
|= size
| MO_ALIGN
;
2266 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2267 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2269 tcg_gen_mov_i64(cpu_exclusive_addr
, addr
);
2272 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
2273 TCGv_i64 addr
, int size
, int is_pair
)
2275 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
2276 * && (!is_pair || env->exclusive_high == [addr + datasize])) {
2279 * [addr + datasize] = {Rt2};
2285 * env->exclusive_addr = -1;
2287 TCGLabel
*fail_label
= gen_new_label();
2288 TCGLabel
*done_label
= gen_new_label();
2291 tcg_gen_brcond_i64(TCG_COND_NE
, addr
, cpu_exclusive_addr
, fail_label
);
2293 tmp
= tcg_temp_new_i64();
2296 if (s
->be_data
== MO_LE
) {
2297 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2299 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt2
), cpu_reg(s
, rt
));
2301 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
,
2302 cpu_exclusive_val
, tmp
,
2304 MO_64
| MO_ALIGN
| s
->be_data
);
2305 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2306 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2307 if (!HAVE_CMPXCHG128
) {
2308 gen_helper_exit_atomic(cpu_env
);
2309 s
->base
.is_jmp
= DISAS_NORETURN
;
2310 } else if (s
->be_data
== MO_LE
) {
2311 gen_helper_paired_cmpxchg64_le_parallel(tmp
, cpu_env
,
2316 gen_helper_paired_cmpxchg64_be_parallel(tmp
, cpu_env
,
2321 } else if (s
->be_data
== MO_LE
) {
2322 gen_helper_paired_cmpxchg64_le(tmp
, cpu_env
, cpu_exclusive_addr
,
2323 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2325 gen_helper_paired_cmpxchg64_be(tmp
, cpu_env
, cpu_exclusive_addr
,
2326 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2329 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
, cpu_exclusive_val
,
2330 cpu_reg(s
, rt
), get_mem_index(s
),
2331 size
| MO_ALIGN
| s
->be_data
);
2332 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2334 tcg_gen_mov_i64(cpu_reg(s
, rd
), tmp
);
2335 tcg_temp_free_i64(tmp
);
2336 tcg_gen_br(done_label
);
2338 gen_set_label(fail_label
);
2339 tcg_gen_movi_i64(cpu_reg(s
, rd
), 1);
2340 gen_set_label(done_label
);
2341 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
2344 static void gen_compare_and_swap(DisasContext
*s
, int rs
, int rt
,
2347 TCGv_i64 tcg_rs
= cpu_reg(s
, rs
);
2348 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2349 int memidx
= get_mem_index(s
);
2350 TCGv_i64 addr
= cpu_reg_sp(s
, rn
);
2353 gen_check_sp_alignment(s
);
2355 tcg_gen_atomic_cmpxchg_i64(tcg_rs
, addr
, tcg_rs
, tcg_rt
, memidx
,
2356 size
| MO_ALIGN
| s
->be_data
);
2359 static void gen_compare_and_swap_pair(DisasContext
*s
, int rs
, int rt
,
2362 TCGv_i64 s1
= cpu_reg(s
, rs
);
2363 TCGv_i64 s2
= cpu_reg(s
, rs
+ 1);
2364 TCGv_i64 t1
= cpu_reg(s
, rt
);
2365 TCGv_i64 t2
= cpu_reg(s
, rt
+ 1);
2366 TCGv_i64 addr
= cpu_reg_sp(s
, rn
);
2367 int memidx
= get_mem_index(s
);
2370 gen_check_sp_alignment(s
);
2374 TCGv_i64 cmp
= tcg_temp_new_i64();
2375 TCGv_i64 val
= tcg_temp_new_i64();
2377 if (s
->be_data
== MO_LE
) {
2378 tcg_gen_concat32_i64(val
, t1
, t2
);
2379 tcg_gen_concat32_i64(cmp
, s1
, s2
);
2381 tcg_gen_concat32_i64(val
, t2
, t1
);
2382 tcg_gen_concat32_i64(cmp
, s2
, s1
);
2385 tcg_gen_atomic_cmpxchg_i64(cmp
, addr
, cmp
, val
, memidx
,
2386 MO_64
| MO_ALIGN
| s
->be_data
);
2387 tcg_temp_free_i64(val
);
2389 if (s
->be_data
== MO_LE
) {
2390 tcg_gen_extr32_i64(s1
, s2
, cmp
);
2392 tcg_gen_extr32_i64(s2
, s1
, cmp
);
2394 tcg_temp_free_i64(cmp
);
2395 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2396 if (HAVE_CMPXCHG128
) {
2397 TCGv_i32 tcg_rs
= tcg_const_i32(rs
);
2398 if (s
->be_data
== MO_LE
) {
2399 gen_helper_casp_le_parallel(cpu_env
, tcg_rs
, addr
, t1
, t2
);
2401 gen_helper_casp_be_parallel(cpu_env
, tcg_rs
, addr
, t1
, t2
);
2403 tcg_temp_free_i32(tcg_rs
);
2405 gen_helper_exit_atomic(cpu_env
);
2406 s
->base
.is_jmp
= DISAS_NORETURN
;
2409 TCGv_i64 d1
= tcg_temp_new_i64();
2410 TCGv_i64 d2
= tcg_temp_new_i64();
2411 TCGv_i64 a2
= tcg_temp_new_i64();
2412 TCGv_i64 c1
= tcg_temp_new_i64();
2413 TCGv_i64 c2
= tcg_temp_new_i64();
2414 TCGv_i64 zero
= tcg_const_i64(0);
2416 /* Load the two words, in memory order. */
2417 tcg_gen_qemu_ld_i64(d1
, addr
, memidx
,
2418 MO_64
| MO_ALIGN_16
| s
->be_data
);
2419 tcg_gen_addi_i64(a2
, addr
, 8);
2420 tcg_gen_qemu_ld_i64(d2
, addr
, memidx
, MO_64
| s
->be_data
);
2422 /* Compare the two words, also in memory order. */
2423 tcg_gen_setcond_i64(TCG_COND_EQ
, c1
, d1
, s1
);
2424 tcg_gen_setcond_i64(TCG_COND_EQ
, c2
, d2
, s2
);
2425 tcg_gen_and_i64(c2
, c2
, c1
);
2427 /* If compare equal, write back new data, else write back old data. */
2428 tcg_gen_movcond_i64(TCG_COND_NE
, c1
, c2
, zero
, t1
, d1
);
2429 tcg_gen_movcond_i64(TCG_COND_NE
, c2
, c2
, zero
, t2
, d2
);
2430 tcg_gen_qemu_st_i64(c1
, addr
, memidx
, MO_64
| s
->be_data
);
2431 tcg_gen_qemu_st_i64(c2
, a2
, memidx
, MO_64
| s
->be_data
);
2432 tcg_temp_free_i64(a2
);
2433 tcg_temp_free_i64(c1
);
2434 tcg_temp_free_i64(c2
);
2435 tcg_temp_free_i64(zero
);
2437 /* Write back the data from memory to Rs. */
2438 tcg_gen_mov_i64(s1
, d1
);
2439 tcg_gen_mov_i64(s2
, d2
);
2440 tcg_temp_free_i64(d1
);
2441 tcg_temp_free_i64(d2
);
2445 /* Update the Sixty-Four bit (SF) registersize. This logic is derived
2446 * from the ARMv8 specs for LDR (Shared decode for all encodings).
2448 static bool disas_ldst_compute_iss_sf(int size
, bool is_signed
, int opc
)
2450 int opc0
= extract32(opc
, 0, 1);
2454 regsize
= opc0
? 32 : 64;
2456 regsize
= size
== 3 ? 64 : 32;
2458 return regsize
== 64;
2461 /* Load/store exclusive
2463 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
2464 * +-----+-------------+----+---+----+------+----+-------+------+------+
2465 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
2466 * +-----+-------------+----+---+----+------+----+-------+------+------+
2468 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
2469 * L: 0 -> store, 1 -> load
2470 * o2: 0 -> exclusive, 1 -> not
2471 * o1: 0 -> single register, 1 -> register pair
2472 * o0: 1 -> load-acquire/store-release, 0 -> not
2474 static void disas_ldst_excl(DisasContext
*s
, uint32_t insn
)
2476 int rt
= extract32(insn
, 0, 5);
2477 int rn
= extract32(insn
, 5, 5);
2478 int rt2
= extract32(insn
, 10, 5);
2479 int rs
= extract32(insn
, 16, 5);
2480 int is_lasr
= extract32(insn
, 15, 1);
2481 int o2_L_o1_o0
= extract32(insn
, 21, 3) * 2 | is_lasr
;
2482 int size
= extract32(insn
, 30, 2);
2485 switch (o2_L_o1_o0
) {
2486 case 0x0: /* STXR */
2487 case 0x1: /* STLXR */
2489 gen_check_sp_alignment(s
);
2492 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2494 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2495 gen_store_exclusive(s
, rs
, rt
, rt2
, tcg_addr
, size
, false);
2498 case 0x4: /* LDXR */
2499 case 0x5: /* LDAXR */
2501 gen_check_sp_alignment(s
);
2503 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2505 gen_load_exclusive(s
, rt
, rt2
, tcg_addr
, size
, false);
2507 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2511 case 0x8: /* STLLR */
2512 if (!dc_isar_feature(aa64_lor
, s
)) {
2515 /* StoreLORelease is the same as Store-Release for QEMU. */
2517 case 0x9: /* STLR */
2518 /* Generate ISS for non-exclusive accesses including LASR. */
2520 gen_check_sp_alignment(s
);
2522 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2523 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2524 do_gpr_st(s
, cpu_reg(s
, rt
), tcg_addr
, size
, true, rt
,
2525 disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2528 case 0xc: /* LDLAR */
2529 if (!dc_isar_feature(aa64_lor
, s
)) {
2532 /* LoadLOAcquire is the same as Load-Acquire for QEMU. */
2534 case 0xd: /* LDAR */
2535 /* Generate ISS for non-exclusive accesses including LASR. */
2537 gen_check_sp_alignment(s
);
2539 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2540 do_gpr_ld(s
, cpu_reg(s
, rt
), tcg_addr
, size
, false, false, true, rt
,
2541 disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2542 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2545 case 0x2: case 0x3: /* CASP / STXP */
2546 if (size
& 2) { /* STXP / STLXP */
2548 gen_check_sp_alignment(s
);
2551 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2553 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2554 gen_store_exclusive(s
, rs
, rt
, rt2
, tcg_addr
, size
, true);
2558 && ((rt
| rs
) & 1) == 0
2559 && dc_isar_feature(aa64_atomics
, s
)) {
2561 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2566 case 0x6: case 0x7: /* CASPA / LDXP */
2567 if (size
& 2) { /* LDXP / LDAXP */
2569 gen_check_sp_alignment(s
);
2571 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2573 gen_load_exclusive(s
, rt
, rt2
, tcg_addr
, size
, true);
2575 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2580 && ((rt
| rs
) & 1) == 0
2581 && dc_isar_feature(aa64_atomics
, s
)) {
2582 /* CASPA / CASPAL */
2583 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2589 case 0xb: /* CASL */
2590 case 0xe: /* CASA */
2591 case 0xf: /* CASAL */
2592 if (rt2
== 31 && dc_isar_feature(aa64_atomics
, s
)) {
2593 gen_compare_and_swap(s
, rs
, rt
, rn
, size
);
2598 unallocated_encoding(s
);
2602 * Load register (literal)
2604 * 31 30 29 27 26 25 24 23 5 4 0
2605 * +-----+-------+---+-----+-------------------+-------+
2606 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
2607 * +-----+-------+---+-----+-------------------+-------+
2609 * V: 1 -> vector (simd/fp)
2610 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
2611 * 10-> 32 bit signed, 11 -> prefetch
2612 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
2614 static void disas_ld_lit(DisasContext
*s
, uint32_t insn
)
2616 int rt
= extract32(insn
, 0, 5);
2617 int64_t imm
= sextract32(insn
, 5, 19) << 2;
2618 bool is_vector
= extract32(insn
, 26, 1);
2619 int opc
= extract32(insn
, 30, 2);
2620 bool is_signed
= false;
2622 TCGv_i64 tcg_rt
, tcg_addr
;
2626 unallocated_encoding(s
);
2630 if (!fp_access_check(s
)) {
2635 /* PRFM (literal) : prefetch */
2638 size
= 2 + extract32(opc
, 0, 1);
2639 is_signed
= extract32(opc
, 1, 1);
2642 tcg_rt
= cpu_reg(s
, rt
);
2644 tcg_addr
= tcg_const_i64((s
->pc
- 4) + imm
);
2646 do_fp_ld(s
, rt
, tcg_addr
, size
);
2648 /* Only unsigned 32bit loads target 32bit registers. */
2649 bool iss_sf
= opc
!= 0;
2651 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, false,
2652 true, rt
, iss_sf
, false);
2654 tcg_temp_free_i64(tcg_addr
);
2658 * LDNP (Load Pair - non-temporal hint)
2659 * LDP (Load Pair - non vector)
2660 * LDPSW (Load Pair Signed Word - non vector)
2661 * STNP (Store Pair - non-temporal hint)
2662 * STP (Store Pair - non vector)
2663 * LDNP (Load Pair of SIMD&FP - non-temporal hint)
2664 * LDP (Load Pair of SIMD&FP)
2665 * STNP (Store Pair of SIMD&FP - non-temporal hint)
2666 * STP (Store Pair of SIMD&FP)
2668 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
2669 * +-----+-------+---+---+-------+---+-----------------------------+
2670 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
2671 * +-----+-------+---+---+-------+---+-------+-------+------+------+
2673 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
2675 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
2676 * V: 0 -> GPR, 1 -> Vector
2677 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
2678 * 10 -> signed offset, 11 -> pre-index
2679 * L: 0 -> Store 1 -> Load
2681 * Rt, Rt2 = GPR or SIMD registers to be stored
2682 * Rn = general purpose register containing address
2683 * imm7 = signed offset (multiple of 4 or 8 depending on size)
2685 static void disas_ldst_pair(DisasContext
*s
, uint32_t insn
)
2687 int rt
= extract32(insn
, 0, 5);
2688 int rn
= extract32(insn
, 5, 5);
2689 int rt2
= extract32(insn
, 10, 5);
2690 uint64_t offset
= sextract64(insn
, 15, 7);
2691 int index
= extract32(insn
, 23, 2);
2692 bool is_vector
= extract32(insn
, 26, 1);
2693 bool is_load
= extract32(insn
, 22, 1);
2694 int opc
= extract32(insn
, 30, 2);
2696 bool is_signed
= false;
2697 bool postindex
= false;
2700 TCGv_i64 tcg_addr
; /* calculated address */
2704 unallocated_encoding(s
);
2711 size
= 2 + extract32(opc
, 1, 1);
2712 is_signed
= extract32(opc
, 0, 1);
2713 if (!is_load
&& is_signed
) {
2714 unallocated_encoding(s
);
2720 case 1: /* post-index */
2725 /* signed offset with "non-temporal" hint. Since we don't emulate
2726 * caches we don't care about hints to the cache system about
2727 * data access patterns, and handle this identically to plain
2731 /* There is no non-temporal-hint version of LDPSW */
2732 unallocated_encoding(s
);
2737 case 2: /* signed offset, rn not updated */
2740 case 3: /* pre-index */
2746 if (is_vector
&& !fp_access_check(s
)) {
2753 gen_check_sp_alignment(s
);
2756 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2759 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
2764 do_fp_ld(s
, rt
, tcg_addr
, size
);
2766 do_fp_st(s
, rt
, tcg_addr
, size
);
2768 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2770 do_fp_ld(s
, rt2
, tcg_addr
, size
);
2772 do_fp_st(s
, rt2
, tcg_addr
, size
);
2775 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2776 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt2
);
2779 TCGv_i64 tmp
= tcg_temp_new_i64();
2781 /* Do not modify tcg_rt before recognizing any exception
2782 * from the second load.
2784 do_gpr_ld(s
, tmp
, tcg_addr
, size
, is_signed
, false,
2785 false, 0, false, false);
2786 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2787 do_gpr_ld(s
, tcg_rt2
, tcg_addr
, size
, is_signed
, false,
2788 false, 0, false, false);
2790 tcg_gen_mov_i64(tcg_rt
, tmp
);
2791 tcg_temp_free_i64(tmp
);
2793 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
,
2794 false, 0, false, false);
2795 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2796 do_gpr_st(s
, tcg_rt2
, tcg_addr
, size
,
2797 false, 0, false, false);
2803 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
- (1 << size
));
2805 tcg_gen_subi_i64(tcg_addr
, tcg_addr
, 1 << size
);
2807 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), tcg_addr
);
2812 * Load/store (immediate post-indexed)
2813 * Load/store (immediate pre-indexed)
2814 * Load/store (unscaled immediate)
2816 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
2817 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2818 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
2819 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2821 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
2823 * V = 0 -> non-vector
2824 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
2825 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2827 static void disas_ldst_reg_imm9(DisasContext
*s
, uint32_t insn
,
2833 int rn
= extract32(insn
, 5, 5);
2834 int imm9
= sextract32(insn
, 12, 9);
2835 int idx
= extract32(insn
, 10, 2);
2836 bool is_signed
= false;
2837 bool is_store
= false;
2838 bool is_extended
= false;
2839 bool is_unpriv
= (idx
== 2);
2840 bool iss_valid
= !is_vector
;
2847 size
|= (opc
& 2) << 1;
2848 if (size
> 4 || is_unpriv
) {
2849 unallocated_encoding(s
);
2852 is_store
= ((opc
& 1) == 0);
2853 if (!fp_access_check(s
)) {
2857 if (size
== 3 && opc
== 2) {
2858 /* PRFM - prefetch */
2860 unallocated_encoding(s
);
2865 if (opc
== 3 && size
> 1) {
2866 unallocated_encoding(s
);
2869 is_store
= (opc
== 0);
2870 is_signed
= extract32(opc
, 1, 1);
2871 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2889 g_assert_not_reached();
2893 gen_check_sp_alignment(s
);
2895 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
2898 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
2903 do_fp_st(s
, rt
, tcg_addr
, size
);
2905 do_fp_ld(s
, rt
, tcg_addr
, size
);
2908 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2909 int memidx
= is_unpriv
? get_a64_user_mem_index(s
) : get_mem_index(s
);
2910 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2913 do_gpr_st_memidx(s
, tcg_rt
, tcg_addr
, size
, memidx
,
2914 iss_valid
, rt
, iss_sf
, false);
2916 do_gpr_ld_memidx(s
, tcg_rt
, tcg_addr
, size
,
2917 is_signed
, is_extended
, memidx
,
2918 iss_valid
, rt
, iss_sf
, false);
2923 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
2925 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, imm9
);
2927 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
2932 * Load/store (register offset)
2934 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2935 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2936 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
2937 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2940 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2941 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2943 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2944 * opc<0>: 0 -> store, 1 -> load
2945 * V: 1 -> vector/simd
2946 * opt: extend encoding (see DecodeRegExtend)
2947 * S: if S=1 then scale (essentially index by sizeof(size))
2948 * Rt: register to transfer into/out of
2949 * Rn: address register or SP for base
2950 * Rm: offset register or ZR for offset
2952 static void disas_ldst_reg_roffset(DisasContext
*s
, uint32_t insn
,
2958 int rn
= extract32(insn
, 5, 5);
2959 int shift
= extract32(insn
, 12, 1);
2960 int rm
= extract32(insn
, 16, 5);
2961 int opt
= extract32(insn
, 13, 3);
2962 bool is_signed
= false;
2963 bool is_store
= false;
2964 bool is_extended
= false;
2969 if (extract32(opt
, 1, 1) == 0) {
2970 unallocated_encoding(s
);
2975 size
|= (opc
& 2) << 1;
2977 unallocated_encoding(s
);
2980 is_store
= !extract32(opc
, 0, 1);
2981 if (!fp_access_check(s
)) {
2985 if (size
== 3 && opc
== 2) {
2986 /* PRFM - prefetch */
2989 if (opc
== 3 && size
> 1) {
2990 unallocated_encoding(s
);
2993 is_store
= (opc
== 0);
2994 is_signed
= extract32(opc
, 1, 1);
2995 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2999 gen_check_sp_alignment(s
);
3001 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
3003 tcg_rm
= read_cpu_reg(s
, rm
, 1);
3004 ext_and_shift_reg(tcg_rm
, tcg_rm
, opt
, shift
? size
: 0);
3006 tcg_gen_add_i64(tcg_addr
, tcg_addr
, tcg_rm
);
3010 do_fp_st(s
, rt
, tcg_addr
, size
);
3012 do_fp_ld(s
, rt
, tcg_addr
, size
);
3015 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3016 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3018 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
,
3019 true, rt
, iss_sf
, false);
3021 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
,
3022 is_signed
, is_extended
,
3023 true, rt
, iss_sf
, false);
3029 * Load/store (unsigned immediate)
3031 * 31 30 29 27 26 25 24 23 22 21 10 9 5
3032 * +----+-------+---+-----+-----+------------+-------+------+
3033 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
3034 * +----+-------+---+-----+-----+------------+-------+------+
3037 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
3038 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
3040 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
3041 * opc<0>: 0 -> store, 1 -> load
3042 * Rn: base address register (inc SP)
3043 * Rt: target register
3045 static void disas_ldst_reg_unsigned_imm(DisasContext
*s
, uint32_t insn
,
3051 int rn
= extract32(insn
, 5, 5);
3052 unsigned int imm12
= extract32(insn
, 10, 12);
3053 unsigned int offset
;
3058 bool is_signed
= false;
3059 bool is_extended
= false;
3062 size
|= (opc
& 2) << 1;
3064 unallocated_encoding(s
);
3067 is_store
= !extract32(opc
, 0, 1);
3068 if (!fp_access_check(s
)) {
3072 if (size
== 3 && opc
== 2) {
3073 /* PRFM - prefetch */
3076 if (opc
== 3 && size
> 1) {
3077 unallocated_encoding(s
);
3080 is_store
= (opc
== 0);
3081 is_signed
= extract32(opc
, 1, 1);
3082 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
3086 gen_check_sp_alignment(s
);
3088 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
3089 offset
= imm12
<< size
;
3090 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
3094 do_fp_st(s
, rt
, tcg_addr
, size
);
3096 do_fp_ld(s
, rt
, tcg_addr
, size
);
3099 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3100 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3102 do_gpr_st(s
, tcg_rt
, tcg_addr
, size
,
3103 true, rt
, iss_sf
, false);
3105 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, is_signed
, is_extended
,
3106 true, rt
, iss_sf
, false);
3111 /* Atomic memory operations
3113 * 31 30 27 26 24 22 21 16 15 12 10 5 0
3114 * +------+-------+---+-----+-----+---+----+----+-----+-----+----+-----+
3115 * | size | 1 1 1 | V | 0 0 | A R | 1 | Rs | o3 | opc | 0 0 | Rn | Rt |
3116 * +------+-------+---+-----+-----+--------+----+-----+-----+----+-----+
3118 * Rt: the result register
3119 * Rn: base address or SP
3120 * Rs: the source register for the operation
3121 * V: vector flag (always 0 as of v8.3)
3125 static void disas_ldst_atomic(DisasContext
*s
, uint32_t insn
,
3126 int size
, int rt
, bool is_vector
)
3128 int rs
= extract32(insn
, 16, 5);
3129 int rn
= extract32(insn
, 5, 5);
3130 int o3_opc
= extract32(insn
, 12, 4);
3131 TCGv_i64 tcg_rn
, tcg_rs
;
3132 AtomicThreeOpFn
*fn
;
3134 if (is_vector
|| !dc_isar_feature(aa64_atomics
, s
)) {
3135 unallocated_encoding(s
);
3139 case 000: /* LDADD */
3140 fn
= tcg_gen_atomic_fetch_add_i64
;
3142 case 001: /* LDCLR */
3143 fn
= tcg_gen_atomic_fetch_and_i64
;
3145 case 002: /* LDEOR */
3146 fn
= tcg_gen_atomic_fetch_xor_i64
;
3148 case 003: /* LDSET */
3149 fn
= tcg_gen_atomic_fetch_or_i64
;
3151 case 004: /* LDSMAX */
3152 fn
= tcg_gen_atomic_fetch_smax_i64
;
3154 case 005: /* LDSMIN */
3155 fn
= tcg_gen_atomic_fetch_smin_i64
;
3157 case 006: /* LDUMAX */
3158 fn
= tcg_gen_atomic_fetch_umax_i64
;
3160 case 007: /* LDUMIN */
3161 fn
= tcg_gen_atomic_fetch_umin_i64
;
3164 fn
= tcg_gen_atomic_xchg_i64
;
3167 unallocated_encoding(s
);
3172 gen_check_sp_alignment(s
);
3174 tcg_rn
= cpu_reg_sp(s
, rn
);
3175 tcg_rs
= read_cpu_reg(s
, rs
, true);
3177 if (o3_opc
== 1) { /* LDCLR */
3178 tcg_gen_not_i64(tcg_rs
, tcg_rs
);
3181 /* The tcg atomic primitives are all full barriers. Therefore we
3182 * can ignore the Acquire and Release bits of this instruction.
3184 fn(cpu_reg(s
, rt
), tcg_rn
, tcg_rs
, get_mem_index(s
),
3185 s
->be_data
| size
| MO_ALIGN
);
3189 * PAC memory operations
3191 * 31 30 27 26 24 22 21 12 11 10 5 0
3192 * +------+-------+---+-----+-----+---+--------+---+---+----+-----+
3193 * | size | 1 1 1 | V | 0 0 | M S | 1 | imm9 | W | 1 | Rn | Rt |
3194 * +------+-------+---+-----+-----+---+--------+---+---+----+-----+
3196 * Rt: the result register
3197 * Rn: base address or SP
3198 * V: vector flag (always 0 as of v8.3)
3199 * M: clear for key DA, set for key DB
3200 * W: pre-indexing flag
3203 static void disas_ldst_pac(DisasContext
*s
, uint32_t insn
,
3204 int size
, int rt
, bool is_vector
)
3206 int rn
= extract32(insn
, 5, 5);
3207 bool is_wback
= extract32(insn
, 11, 1);
3208 bool use_key_a
= !extract32(insn
, 23, 1);
3210 TCGv_i64 tcg_addr
, tcg_rt
;
3212 if (size
!= 3 || is_vector
|| !dc_isar_feature(aa64_pauth
, s
)) {
3213 unallocated_encoding(s
);
3218 gen_check_sp_alignment(s
);
3220 tcg_addr
= read_cpu_reg_sp(s
, rn
, 1);
3222 if (s
->pauth_active
) {
3224 gen_helper_autda(tcg_addr
, cpu_env
, tcg_addr
, cpu_X
[31]);
3226 gen_helper_autdb(tcg_addr
, cpu_env
, tcg_addr
, cpu_X
[31]);
3230 /* Form the 10-bit signed, scaled offset. */
3231 offset
= (extract32(insn
, 22, 1) << 9) | extract32(insn
, 12, 9);
3232 offset
= sextract32(offset
<< size
, 0, 10 + size
);
3233 tcg_gen_addi_i64(tcg_addr
, tcg_addr
, offset
);
3235 tcg_rt
= cpu_reg(s
, rt
);
3237 do_gpr_ld(s
, tcg_rt
, tcg_addr
, size
, /* is_signed */ false,
3238 /* extend */ false, /* iss_valid */ !is_wback
,
3239 /* iss_srt */ rt
, /* iss_sf */ true, /* iss_ar */ false);
3242 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), tcg_addr
);
3246 /* Load/store register (all forms) */
3247 static void disas_ldst_reg(DisasContext
*s
, uint32_t insn
)
3249 int rt
= extract32(insn
, 0, 5);
3250 int opc
= extract32(insn
, 22, 2);
3251 bool is_vector
= extract32(insn
, 26, 1);
3252 int size
= extract32(insn
, 30, 2);
3254 switch (extract32(insn
, 24, 2)) {
3256 if (extract32(insn
, 21, 1) == 0) {
3257 /* Load/store register (unscaled immediate)
3258 * Load/store immediate pre/post-indexed
3259 * Load/store register unprivileged
3261 disas_ldst_reg_imm9(s
, insn
, opc
, size
, rt
, is_vector
);
3264 switch (extract32(insn
, 10, 2)) {
3266 disas_ldst_atomic(s
, insn
, size
, rt
, is_vector
);
3269 disas_ldst_reg_roffset(s
, insn
, opc
, size
, rt
, is_vector
);
3272 disas_ldst_pac(s
, insn
, size
, rt
, is_vector
);
3277 disas_ldst_reg_unsigned_imm(s
, insn
, opc
, size
, rt
, is_vector
);
3280 unallocated_encoding(s
);
3283 /* AdvSIMD load/store multiple structures
3285 * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
3286 * +---+---+---------------+---+-------------+--------+------+------+------+
3287 * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
3288 * +---+---+---------------+---+-------------+--------+------+------+------+
3290 * AdvSIMD load/store multiple structures (post-indexed)
3292 * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
3293 * +---+---+---------------+---+---+---------+--------+------+------+------+
3294 * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
3295 * +---+---+---------------+---+---+---------+--------+------+------+------+
3297 * Rt: first (or only) SIMD&FP register to be transferred
3298 * Rn: base address or SP
3299 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3301 static void disas_ldst_multiple_struct(DisasContext
*s
, uint32_t insn
)
3303 int rt
= extract32(insn
, 0, 5);
3304 int rn
= extract32(insn
, 5, 5);
3305 int rm
= extract32(insn
, 16, 5);
3306 int size
= extract32(insn
, 10, 2);
3307 int opcode
= extract32(insn
, 12, 4);
3308 bool is_store
= !extract32(insn
, 22, 1);
3309 bool is_postidx
= extract32(insn
, 23, 1);
3310 bool is_q
= extract32(insn
, 30, 1);
3311 TCGv_i64 tcg_addr
, tcg_rn
, tcg_ebytes
;
3312 TCGMemOp endian
= s
->be_data
;
3314 int ebytes
; /* bytes per element */
3315 int elements
; /* elements per vector */
3316 int rpt
; /* num iterations */
3317 int selem
; /* structure elements */
3320 if (extract32(insn
, 31, 1) || extract32(insn
, 21, 1)) {
3321 unallocated_encoding(s
);
3325 if (!is_postidx
&& rm
!= 0) {
3326 unallocated_encoding(s
);
3330 /* From the shared decode logic */
3361 unallocated_encoding(s
);
3365 if (size
== 3 && !is_q
&& selem
!= 1) {
3367 unallocated_encoding(s
);
3371 if (!fp_access_check(s
)) {
3376 gen_check_sp_alignment(s
);
3379 /* For our purposes, bytes are always little-endian. */
3384 /* Consecutive little-endian elements from a single register
3385 * can be promoted to a larger little-endian operation.
3387 if (selem
== 1 && endian
== MO_LE
) {
3391 elements
= (is_q
? 16 : 8) / ebytes
;
3393 tcg_rn
= cpu_reg_sp(s
, rn
);
3394 tcg_addr
= tcg_temp_new_i64();
3395 tcg_gen_mov_i64(tcg_addr
, tcg_rn
);
3396 tcg_ebytes
= tcg_const_i64(ebytes
);
3398 for (r
= 0; r
< rpt
; r
++) {
3400 for (e
= 0; e
< elements
; e
++) {
3402 for (xs
= 0; xs
< selem
; xs
++) {
3403 int tt
= (rt
+ r
+ xs
) % 32;
3405 do_vec_st(s
, tt
, e
, tcg_addr
, size
, endian
);
3407 do_vec_ld(s
, tt
, e
, tcg_addr
, size
, endian
);
3409 tcg_gen_add_i64(tcg_addr
, tcg_addr
, tcg_ebytes
);
3415 /* For non-quad operations, setting a slice of the low
3416 * 64 bits of the register clears the high 64 bits (in
3417 * the ARM ARM pseudocode this is implicit in the fact
3418 * that 'rval' is a 64 bit wide variable).
3419 * For quad operations, we might still need to zero the
3422 for (r
= 0; r
< rpt
* selem
; r
++) {
3423 int tt
= (rt
+ r
) % 32;
3424 clear_vec_high(s
, is_q
, tt
);
3430 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
3432 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3435 tcg_temp_free_i64(tcg_ebytes
);
3436 tcg_temp_free_i64(tcg_addr
);
3439 /* AdvSIMD load/store single structure
3441 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3442 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3443 * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
3444 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3446 * AdvSIMD load/store single structure (post-indexed)
3448 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3449 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3450 * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
3451 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3453 * Rt: first (or only) SIMD&FP register to be transferred
3454 * Rn: base address or SP
3455 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3456 * index = encoded in Q:S:size dependent on size
3458 * lane_size = encoded in R, opc
3459 * transfer width = encoded in opc, S, size
3461 static void disas_ldst_single_struct(DisasContext
*s
, uint32_t insn
)
3463 int rt
= extract32(insn
, 0, 5);
3464 int rn
= extract32(insn
, 5, 5);
3465 int rm
= extract32(insn
, 16, 5);
3466 int size
= extract32(insn
, 10, 2);
3467 int S
= extract32(insn
, 12, 1);
3468 int opc
= extract32(insn
, 13, 3);
3469 int R
= extract32(insn
, 21, 1);
3470 int is_load
= extract32(insn
, 22, 1);
3471 int is_postidx
= extract32(insn
, 23, 1);
3472 int is_q
= extract32(insn
, 30, 1);
3474 int scale
= extract32(opc
, 1, 2);
3475 int selem
= (extract32(opc
, 0, 1) << 1 | R
) + 1;
3476 bool replicate
= false;
3477 int index
= is_q
<< 3 | S
<< 2 | size
;
3479 TCGv_i64 tcg_addr
, tcg_rn
, tcg_ebytes
;
3481 if (extract32(insn
, 31, 1)) {
3482 unallocated_encoding(s
);
3485 if (!is_postidx
&& rm
!= 0) {
3486 unallocated_encoding(s
);
3492 if (!is_load
|| S
) {
3493 unallocated_encoding(s
);
3502 if (extract32(size
, 0, 1)) {
3503 unallocated_encoding(s
);
3509 if (extract32(size
, 1, 1)) {
3510 unallocated_encoding(s
);
3513 if (!extract32(size
, 0, 1)) {
3517 unallocated_encoding(s
);
3525 g_assert_not_reached();
3528 if (!fp_access_check(s
)) {
3532 ebytes
= 1 << scale
;
3535 gen_check_sp_alignment(s
);
3538 tcg_rn
= cpu_reg_sp(s
, rn
);
3539 tcg_addr
= tcg_temp_new_i64();
3540 tcg_gen_mov_i64(tcg_addr
, tcg_rn
);
3541 tcg_ebytes
= tcg_const_i64(ebytes
);
3543 for (xs
= 0; xs
< selem
; xs
++) {
3545 /* Load and replicate to all elements */
3546 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
3548 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
,
3549 get_mem_index(s
), s
->be_data
+ scale
);
3550 tcg_gen_gvec_dup_i64(scale
, vec_full_reg_offset(s
, rt
),
3551 (is_q
+ 1) * 8, vec_full_reg_size(s
),
3553 tcg_temp_free_i64(tcg_tmp
);
3555 /* Load/store one element per register */
3557 do_vec_ld(s
, rt
, index
, tcg_addr
, scale
, s
->be_data
);
3559 do_vec_st(s
, rt
, index
, tcg_addr
, scale
, s
->be_data
);
3562 tcg_gen_add_i64(tcg_addr
, tcg_addr
, tcg_ebytes
);
3568 tcg_gen_mov_i64(tcg_rn
, tcg_addr
);
3570 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3573 tcg_temp_free_i64(tcg_ebytes
);
3574 tcg_temp_free_i64(tcg_addr
);
3577 /* Loads and stores */
3578 static void disas_ldst(DisasContext
*s
, uint32_t insn
)
3580 switch (extract32(insn
, 24, 6)) {
3581 case 0x08: /* Load/store exclusive */
3582 disas_ldst_excl(s
, insn
);
3584 case 0x18: case 0x1c: /* Load register (literal) */
3585 disas_ld_lit(s
, insn
);
3587 case 0x28: case 0x29:
3588 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
3589 disas_ldst_pair(s
, insn
);
3591 case 0x38: case 0x39:
3592 case 0x3c: case 0x3d: /* Load/store register (all forms) */
3593 disas_ldst_reg(s
, insn
);
3595 case 0x0c: /* AdvSIMD load/store multiple structures */
3596 disas_ldst_multiple_struct(s
, insn
);
3598 case 0x0d: /* AdvSIMD load/store single structure */
3599 disas_ldst_single_struct(s
, insn
);
3602 unallocated_encoding(s
);
3607 /* PC-rel. addressing
3608 * 31 30 29 28 24 23 5 4 0
3609 * +----+-------+-----------+-------------------+------+
3610 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
3611 * +----+-------+-----------+-------------------+------+
3613 static void disas_pc_rel_adr(DisasContext
*s
, uint32_t insn
)
3615 unsigned int page
, rd
;
3619 page
= extract32(insn
, 31, 1);
3620 /* SignExtend(immhi:immlo) -> offset */
3621 offset
= sextract64(insn
, 5, 19);
3622 offset
= offset
<< 2 | extract32(insn
, 29, 2);
3623 rd
= extract32(insn
, 0, 5);
3627 /* ADRP (page based) */
3632 tcg_gen_movi_i64(cpu_reg(s
, rd
), base
+ offset
);
3636 * Add/subtract (immediate)
3638 * 31 30 29 28 24 23 22 21 10 9 5 4 0
3639 * +--+--+--+-----------+-----+-------------+-----+-----+
3640 * |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd |
3641 * +--+--+--+-----------+-----+-------------+-----+-----+
3643 * sf: 0 -> 32bit, 1 -> 64bit
3644 * op: 0 -> add , 1 -> sub
3646 * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12
3648 static void disas_add_sub_imm(DisasContext
*s
, uint32_t insn
)
3650 int rd
= extract32(insn
, 0, 5);
3651 int rn
= extract32(insn
, 5, 5);
3652 uint64_t imm
= extract32(insn
, 10, 12);
3653 int shift
= extract32(insn
, 22, 2);
3654 bool setflags
= extract32(insn
, 29, 1);
3655 bool sub_op
= extract32(insn
, 30, 1);
3656 bool is_64bit
= extract32(insn
, 31, 1);
3658 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
3659 TCGv_i64 tcg_rd
= setflags
? cpu_reg(s
, rd
) : cpu_reg_sp(s
, rd
);
3660 TCGv_i64 tcg_result
;
3669 unallocated_encoding(s
);
3673 tcg_result
= tcg_temp_new_i64();
3676 tcg_gen_subi_i64(tcg_result
, tcg_rn
, imm
);
3678 tcg_gen_addi_i64(tcg_result
, tcg_rn
, imm
);
3681 TCGv_i64 tcg_imm
= tcg_const_i64(imm
);
3683 gen_sub_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
3685 gen_add_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
3687 tcg_temp_free_i64(tcg_imm
);
3691 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3693 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3696 tcg_temp_free_i64(tcg_result
);
3699 /* The input should be a value in the bottom e bits (with higher
3700 * bits zero); returns that value replicated into every element
3701 * of size e in a 64 bit integer.
3703 static uint64_t bitfield_replicate(uint64_t mask
, unsigned int e
)
3713 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
3714 static inline uint64_t bitmask64(unsigned int length
)
3716 assert(length
> 0 && length
<= 64);
3717 return ~0ULL >> (64 - length
);
3720 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
3721 * only require the wmask. Returns false if the imms/immr/immn are a reserved
3722 * value (ie should cause a guest UNDEF exception), and true if they are
3723 * valid, in which case the decoded bit pattern is written to result.
3725 bool logic_imm_decode_wmask(uint64_t *result
, unsigned int immn
,
3726 unsigned int imms
, unsigned int immr
)
3729 unsigned e
, levels
, s
, r
;
3732 assert(immn
< 2 && imms
< 64 && immr
< 64);
3734 /* The bit patterns we create here are 64 bit patterns which
3735 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
3736 * 64 bits each. Each element contains the same value: a run
3737 * of between 1 and e-1 non-zero bits, rotated within the
3738 * element by between 0 and e-1 bits.
3740 * The element size and run length are encoded into immn (1 bit)
3741 * and imms (6 bits) as follows:
3742 * 64 bit elements: immn = 1, imms = <length of run - 1>
3743 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
3744 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
3745 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
3746 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
3747 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
3748 * Notice that immn = 0, imms = 11111x is the only combination
3749 * not covered by one of the above options; this is reserved.
3750 * Further, <length of run - 1> all-ones is a reserved pattern.
3752 * In all cases the rotation is by immr % e (and immr is 6 bits).
3755 /* First determine the element size */
3756 len
= 31 - clz32((immn
<< 6) | (~imms
& 0x3f));
3758 /* This is the immn == 0, imms == 0x11111x case */
3768 /* <length of run - 1> mustn't be all-ones. */
3772 /* Create the value of one element: s+1 set bits rotated
3773 * by r within the element (which is e bits wide)...
3775 mask
= bitmask64(s
+ 1);
3777 mask
= (mask
>> r
) | (mask
<< (e
- r
));
3778 mask
&= bitmask64(e
);
3780 /* ...then replicate the element over the whole 64 bit value */
3781 mask
= bitfield_replicate(mask
, e
);
3786 /* Logical (immediate)
3787 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
3788 * +----+-----+-------------+---+------+------+------+------+
3789 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
3790 * +----+-----+-------------+---+------+------+------+------+
3792 static void disas_logic_imm(DisasContext
*s
, uint32_t insn
)
3794 unsigned int sf
, opc
, is_n
, immr
, imms
, rn
, rd
;
3795 TCGv_i64 tcg_rd
, tcg_rn
;
3797 bool is_and
= false;
3799 sf
= extract32(insn
, 31, 1);
3800 opc
= extract32(insn
, 29, 2);
3801 is_n
= extract32(insn
, 22, 1);
3802 immr
= extract32(insn
, 16, 6);
3803 imms
= extract32(insn
, 10, 6);
3804 rn
= extract32(insn
, 5, 5);
3805 rd
= extract32(insn
, 0, 5);
3808 unallocated_encoding(s
);
3812 if (opc
== 0x3) { /* ANDS */
3813 tcg_rd
= cpu_reg(s
, rd
);
3815 tcg_rd
= cpu_reg_sp(s
, rd
);
3817 tcg_rn
= cpu_reg(s
, rn
);
3819 if (!logic_imm_decode_wmask(&wmask
, is_n
, imms
, immr
)) {
3820 /* some immediate field values are reserved */
3821 unallocated_encoding(s
);
3826 wmask
&= 0xffffffff;
3830 case 0x3: /* ANDS */
3832 tcg_gen_andi_i64(tcg_rd
, tcg_rn
, wmask
);
3836 tcg_gen_ori_i64(tcg_rd
, tcg_rn
, wmask
);
3839 tcg_gen_xori_i64(tcg_rd
, tcg_rn
, wmask
);
3842 assert(FALSE
); /* must handle all above */
3846 if (!sf
&& !is_and
) {
3847 /* zero extend final result; we know we can skip this for AND
3848 * since the immediate had the high 32 bits clear.
3850 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3853 if (opc
== 3) { /* ANDS */
3854 gen_logic_CC(sf
, tcg_rd
);
3859 * Move wide (immediate)
3861 * 31 30 29 28 23 22 21 20 5 4 0
3862 * +--+-----+-------------+-----+----------------+------+
3863 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
3864 * +--+-----+-------------+-----+----------------+------+
3866 * sf: 0 -> 32 bit, 1 -> 64 bit
3867 * opc: 00 -> N, 10 -> Z, 11 -> K
3868 * hw: shift/16 (0,16, and sf only 32, 48)
3870 static void disas_movw_imm(DisasContext
*s
, uint32_t insn
)
3872 int rd
= extract32(insn
, 0, 5);
3873 uint64_t imm
= extract32(insn
, 5, 16);
3874 int sf
= extract32(insn
, 31, 1);
3875 int opc
= extract32(insn
, 29, 2);
3876 int pos
= extract32(insn
, 21, 2) << 4;
3877 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
3880 if (!sf
&& (pos
>= 32)) {
3881 unallocated_encoding(s
);
3895 tcg_gen_movi_i64(tcg_rd
, imm
);
3898 tcg_imm
= tcg_const_i64(imm
);
3899 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_imm
, pos
, 16);
3900 tcg_temp_free_i64(tcg_imm
);
3902 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3906 unallocated_encoding(s
);
3912 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
3913 * +----+-----+-------------+---+------+------+------+------+
3914 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
3915 * +----+-----+-------------+---+------+------+------+------+
3917 static void disas_bitfield(DisasContext
*s
, uint32_t insn
)
3919 unsigned int sf
, n
, opc
, ri
, si
, rn
, rd
, bitsize
, pos
, len
;
3920 TCGv_i64 tcg_rd
, tcg_tmp
;
3922 sf
= extract32(insn
, 31, 1);
3923 opc
= extract32(insn
, 29, 2);
3924 n
= extract32(insn
, 22, 1);
3925 ri
= extract32(insn
, 16, 6);
3926 si
= extract32(insn
, 10, 6);
3927 rn
= extract32(insn
, 5, 5);
3928 rd
= extract32(insn
, 0, 5);
3929 bitsize
= sf
? 64 : 32;
3931 if (sf
!= n
|| ri
>= bitsize
|| si
>= bitsize
|| opc
> 2) {
3932 unallocated_encoding(s
);
3936 tcg_rd
= cpu_reg(s
, rd
);
3938 /* Suppress the zero-extend for !sf. Since RI and SI are constrained
3939 to be smaller than bitsize, we'll never reference data outside the
3940 low 32-bits anyway. */
3941 tcg_tmp
= read_cpu_reg(s
, rn
, 1);
3943 /* Recognize simple(r) extractions. */
3945 /* Wd<s-r:0> = Wn<s:r> */
3946 len
= (si
- ri
) + 1;
3947 if (opc
== 0) { /* SBFM: ASR, SBFX, SXTB, SXTH, SXTW */
3948 tcg_gen_sextract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
3950 } else if (opc
== 2) { /* UBFM: UBFX, LSR, UXTB, UXTH */
3951 tcg_gen_extract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
3954 /* opc == 1, BXFIL fall through to deposit */
3955 tcg_gen_extract_i64(tcg_tmp
, tcg_tmp
, ri
, len
);
3958 /* Handle the ri > si case with a deposit
3959 * Wd<32+s-r,32-r> = Wn<s:0>
3962 pos
= (bitsize
- ri
) & (bitsize
- 1);
3965 if (opc
== 0 && len
< ri
) {
3966 /* SBFM: sign extend the destination field from len to fill
3967 the balance of the word. Let the deposit below insert all
3968 of those sign bits. */
3969 tcg_gen_sextract_i64(tcg_tmp
, tcg_tmp
, 0, len
);
3973 if (opc
== 1) { /* BFM, BXFIL */
3974 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, pos
, len
);
3976 /* SBFM or UBFM: We start with zero, and we haven't modified
3977 any bits outside bitsize, therefore the zero-extension
3978 below is unneeded. */
3979 tcg_gen_deposit_z_i64(tcg_rd
, tcg_tmp
, pos
, len
);
3984 if (!sf
) { /* zero extend final result */
3985 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
3990 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
3991 * +----+------+-------------+---+----+------+--------+------+------+
3992 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
3993 * +----+------+-------------+---+----+------+--------+------+------+
3995 static void disas_extract(DisasContext
*s
, uint32_t insn
)
3997 unsigned int sf
, n
, rm
, imm
, rn
, rd
, bitsize
, op21
, op0
;
3999 sf
= extract32(insn
, 31, 1);
4000 n
= extract32(insn
, 22, 1);
4001 rm
= extract32(insn
, 16, 5);
4002 imm
= extract32(insn
, 10, 6);
4003 rn
= extract32(insn
, 5, 5);
4004 rd
= extract32(insn
, 0, 5);
4005 op21
= extract32(insn
, 29, 2);
4006 op0
= extract32(insn
, 21, 1);
4007 bitsize
= sf
? 64 : 32;
4009 if (sf
!= n
|| op21
|| op0
|| imm
>= bitsize
) {
4010 unallocated_encoding(s
);
4012 TCGv_i64 tcg_rd
, tcg_rm
, tcg_rn
;
4014 tcg_rd
= cpu_reg(s
, rd
);
4016 if (unlikely(imm
== 0)) {
4017 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
4018 * so an extract from bit 0 is a special case.
4021 tcg_gen_mov_i64(tcg_rd
, cpu_reg(s
, rm
));
4023 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rm
));
4025 } else if (rm
== rn
) { /* ROR */
4026 tcg_rm
= cpu_reg(s
, rm
);
4028 tcg_gen_rotri_i64(tcg_rd
, tcg_rm
, imm
);
4030 TCGv_i32 tmp
= tcg_temp_new_i32();
4031 tcg_gen_extrl_i64_i32(tmp
, tcg_rm
);
4032 tcg_gen_rotri_i32(tmp
, tmp
, imm
);
4033 tcg_gen_extu_i32_i64(tcg_rd
, tmp
);
4034 tcg_temp_free_i32(tmp
);
4037 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4038 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4039 tcg_gen_shri_i64(tcg_rm
, tcg_rm
, imm
);
4040 tcg_gen_shli_i64(tcg_rn
, tcg_rn
, bitsize
- imm
);
4041 tcg_gen_or_i64(tcg_rd
, tcg_rm
, tcg_rn
);
4043 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4049 /* Data processing - immediate */
4050 static void disas_data_proc_imm(DisasContext
*s
, uint32_t insn
)
4052 switch (extract32(insn
, 23, 6)) {
4053 case 0x20: case 0x21: /* PC-rel. addressing */
4054 disas_pc_rel_adr(s
, insn
);
4056 case 0x22: case 0x23: /* Add/subtract (immediate) */
4057 disas_add_sub_imm(s
, insn
);
4059 case 0x24: /* Logical (immediate) */
4060 disas_logic_imm(s
, insn
);
4062 case 0x25: /* Move wide (immediate) */
4063 disas_movw_imm(s
, insn
);
4065 case 0x26: /* Bitfield */
4066 disas_bitfield(s
, insn
);
4068 case 0x27: /* Extract */
4069 disas_extract(s
, insn
);
4072 unallocated_encoding(s
);
4077 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
4078 * Note that it is the caller's responsibility to ensure that the
4079 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
4080 * mandated semantics for out of range shifts.
4082 static void shift_reg(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
4083 enum a64_shift_type shift_type
, TCGv_i64 shift_amount
)
4085 switch (shift_type
) {
4086 case A64_SHIFT_TYPE_LSL
:
4087 tcg_gen_shl_i64(dst
, src
, shift_amount
);
4089 case A64_SHIFT_TYPE_LSR
:
4090 tcg_gen_shr_i64(dst
, src
, shift_amount
);
4092 case A64_SHIFT_TYPE_ASR
:
4094 tcg_gen_ext32s_i64(dst
, src
);
4096 tcg_gen_sar_i64(dst
, sf
? src
: dst
, shift_amount
);
4098 case A64_SHIFT_TYPE_ROR
:
4100 tcg_gen_rotr_i64(dst
, src
, shift_amount
);
4103 t0
= tcg_temp_new_i32();
4104 t1
= tcg_temp_new_i32();
4105 tcg_gen_extrl_i64_i32(t0
, src
);
4106 tcg_gen_extrl_i64_i32(t1
, shift_amount
);
4107 tcg_gen_rotr_i32(t0
, t0
, t1
);
4108 tcg_gen_extu_i32_i64(dst
, t0
);
4109 tcg_temp_free_i32(t0
);
4110 tcg_temp_free_i32(t1
);
4114 assert(FALSE
); /* all shift types should be handled */
4118 if (!sf
) { /* zero extend final result */
4119 tcg_gen_ext32u_i64(dst
, dst
);
4123 /* Shift a TCGv src by immediate, put result in dst.
4124 * The shift amount must be in range (this should always be true as the
4125 * relevant instructions will UNDEF on bad shift immediates).
4127 static void shift_reg_imm(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
4128 enum a64_shift_type shift_type
, unsigned int shift_i
)
4130 assert(shift_i
< (sf
? 64 : 32));
4133 tcg_gen_mov_i64(dst
, src
);
4135 TCGv_i64 shift_const
;
4137 shift_const
= tcg_const_i64(shift_i
);
4138 shift_reg(dst
, src
, sf
, shift_type
, shift_const
);
4139 tcg_temp_free_i64(shift_const
);
4143 /* Logical (shifted register)
4144 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
4145 * +----+-----+-----------+-------+---+------+--------+------+------+
4146 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
4147 * +----+-----+-----------+-------+---+------+--------+------+------+
4149 static void disas_logic_reg(DisasContext
*s
, uint32_t insn
)
4151 TCGv_i64 tcg_rd
, tcg_rn
, tcg_rm
;
4152 unsigned int sf
, opc
, shift_type
, invert
, rm
, shift_amount
, rn
, rd
;
4154 sf
= extract32(insn
, 31, 1);
4155 opc
= extract32(insn
, 29, 2);
4156 shift_type
= extract32(insn
, 22, 2);
4157 invert
= extract32(insn
, 21, 1);
4158 rm
= extract32(insn
, 16, 5);
4159 shift_amount
= extract32(insn
, 10, 6);
4160 rn
= extract32(insn
, 5, 5);
4161 rd
= extract32(insn
, 0, 5);
4163 if (!sf
&& (shift_amount
& (1 << 5))) {
4164 unallocated_encoding(s
);
4168 tcg_rd
= cpu_reg(s
, rd
);
4170 if (opc
== 1 && shift_amount
== 0 && shift_type
== 0 && rn
== 31) {
4171 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
4172 * register-register MOV and MVN, so it is worth special casing.
4174 tcg_rm
= cpu_reg(s
, rm
);
4176 tcg_gen_not_i64(tcg_rd
, tcg_rm
);
4178 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4182 tcg_gen_mov_i64(tcg_rd
, tcg_rm
);
4184 tcg_gen_ext32u_i64(tcg_rd
, tcg_rm
);
4190 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4193 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, shift_amount
);
4196 tcg_rn
= cpu_reg(s
, rn
);
4198 switch (opc
| (invert
<< 2)) {
4201 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4204 tcg_gen_or_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4207 tcg_gen_xor_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4211 tcg_gen_andc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4214 tcg_gen_orc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4217 tcg_gen_eqv_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4225 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4229 gen_logic_CC(sf
, tcg_rd
);
4234 * Add/subtract (extended register)
4236 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
4237 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
4238 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
4239 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
4241 * sf: 0 -> 32bit, 1 -> 64bit
4242 * op: 0 -> add , 1 -> sub
4245 * option: extension type (see DecodeRegExtend)
4246 * imm3: optional shift to Rm
4248 * Rd = Rn + LSL(extend(Rm), amount)
4250 static void disas_add_sub_ext_reg(DisasContext
*s
, uint32_t insn
)
4252 int rd
= extract32(insn
, 0, 5);
4253 int rn
= extract32(insn
, 5, 5);
4254 int imm3
= extract32(insn
, 10, 3);
4255 int option
= extract32(insn
, 13, 3);
4256 int rm
= extract32(insn
, 16, 5);
4257 int opt
= extract32(insn
, 22, 2);
4258 bool setflags
= extract32(insn
, 29, 1);
4259 bool sub_op
= extract32(insn
, 30, 1);
4260 bool sf
= extract32(insn
, 31, 1);
4262 TCGv_i64 tcg_rm
, tcg_rn
; /* temps */
4264 TCGv_i64 tcg_result
;
4266 if (imm3
> 4 || opt
!= 0) {
4267 unallocated_encoding(s
);
4271 /* non-flag setting ops may use SP */
4273 tcg_rd
= cpu_reg_sp(s
, rd
);
4275 tcg_rd
= cpu_reg(s
, rd
);
4277 tcg_rn
= read_cpu_reg_sp(s
, rn
, sf
);
4279 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4280 ext_and_shift_reg(tcg_rm
, tcg_rm
, option
, imm3
);
4282 tcg_result
= tcg_temp_new_i64();
4286 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
4288 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
4292 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4294 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4299 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4301 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4304 tcg_temp_free_i64(tcg_result
);
4308 * Add/subtract (shifted register)
4310 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
4311 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4312 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
4313 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4315 * sf: 0 -> 32bit, 1 -> 64bit
4316 * op: 0 -> add , 1 -> sub
4318 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
4319 * imm6: Shift amount to apply to Rm before the add/sub
4321 static void disas_add_sub_reg(DisasContext
*s
, uint32_t insn
)
4323 int rd
= extract32(insn
, 0, 5);
4324 int rn
= extract32(insn
, 5, 5);
4325 int imm6
= extract32(insn
, 10, 6);
4326 int rm
= extract32(insn
, 16, 5);
4327 int shift_type
= extract32(insn
, 22, 2);
4328 bool setflags
= extract32(insn
, 29, 1);
4329 bool sub_op
= extract32(insn
, 30, 1);
4330 bool sf
= extract32(insn
, 31, 1);
4332 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4333 TCGv_i64 tcg_rn
, tcg_rm
;
4334 TCGv_i64 tcg_result
;
4336 if ((shift_type
== 3) || (!sf
&& (imm6
> 31))) {
4337 unallocated_encoding(s
);
4341 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4342 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4344 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, imm6
);
4346 tcg_result
= tcg_temp_new_i64();
4350 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
4352 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
4356 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4358 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4363 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4365 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4368 tcg_temp_free_i64(tcg_result
);
4371 /* Data-processing (3 source)
4373 * 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
4374 * +--+------+-----------+------+------+----+------+------+------+
4375 * |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
4376 * +--+------+-----------+------+------+----+------+------+------+
4378 static void disas_data_proc_3src(DisasContext
*s
, uint32_t insn
)
4380 int rd
= extract32(insn
, 0, 5);
4381 int rn
= extract32(insn
, 5, 5);
4382 int ra
= extract32(insn
, 10, 5);
4383 int rm
= extract32(insn
, 16, 5);
4384 int op_id
= (extract32(insn
, 29, 3) << 4) |
4385 (extract32(insn
, 21, 3) << 1) |
4386 extract32(insn
, 15, 1);
4387 bool sf
= extract32(insn
, 31, 1);
4388 bool is_sub
= extract32(op_id
, 0, 1);
4389 bool is_high
= extract32(op_id
, 2, 1);
4390 bool is_signed
= false;
4395 /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
4397 case 0x42: /* SMADDL */
4398 case 0x43: /* SMSUBL */
4399 case 0x44: /* SMULH */
4402 case 0x0: /* MADD (32bit) */
4403 case 0x1: /* MSUB (32bit) */
4404 case 0x40: /* MADD (64bit) */
4405 case 0x41: /* MSUB (64bit) */
4406 case 0x4a: /* UMADDL */
4407 case 0x4b: /* UMSUBL */
4408 case 0x4c: /* UMULH */
4411 unallocated_encoding(s
);
4416 TCGv_i64 low_bits
= tcg_temp_new_i64(); /* low bits discarded */
4417 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4418 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
4419 TCGv_i64 tcg_rm
= cpu_reg(s
, rm
);
4422 tcg_gen_muls2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
4424 tcg_gen_mulu2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
4427 tcg_temp_free_i64(low_bits
);
4431 tcg_op1
= tcg_temp_new_i64();
4432 tcg_op2
= tcg_temp_new_i64();
4433 tcg_tmp
= tcg_temp_new_i64();
4436 tcg_gen_mov_i64(tcg_op1
, cpu_reg(s
, rn
));
4437 tcg_gen_mov_i64(tcg_op2
, cpu_reg(s
, rm
));
4440 tcg_gen_ext32s_i64(tcg_op1
, cpu_reg(s
, rn
));
4441 tcg_gen_ext32s_i64(tcg_op2
, cpu_reg(s
, rm
));
4443 tcg_gen_ext32u_i64(tcg_op1
, cpu_reg(s
, rn
));
4444 tcg_gen_ext32u_i64(tcg_op2
, cpu_reg(s
, rm
));
4448 if (ra
== 31 && !is_sub
) {
4449 /* Special-case MADD with rA == XZR; it is the standard MUL alias */
4450 tcg_gen_mul_i64(cpu_reg(s
, rd
), tcg_op1
, tcg_op2
);
4452 tcg_gen_mul_i64(tcg_tmp
, tcg_op1
, tcg_op2
);
4454 tcg_gen_sub_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
4456 tcg_gen_add_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
4461 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), cpu_reg(s
, rd
));
4464 tcg_temp_free_i64(tcg_op1
);
4465 tcg_temp_free_i64(tcg_op2
);
4466 tcg_temp_free_i64(tcg_tmp
);
4469 /* Add/subtract (with carry)
4470 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
4471 * +--+--+--+------------------------+------+---------+------+-----+
4472 * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | opcode2 | Rn | Rd |
4473 * +--+--+--+------------------------+------+---------+------+-----+
4477 static void disas_adc_sbc(DisasContext
*s
, uint32_t insn
)
4479 unsigned int sf
, op
, setflags
, rm
, rn
, rd
;
4480 TCGv_i64 tcg_y
, tcg_rn
, tcg_rd
;
4482 if (extract32(insn
, 10, 6) != 0) {
4483 unallocated_encoding(s
);
4487 sf
= extract32(insn
, 31, 1);
4488 op
= extract32(insn
, 30, 1);
4489 setflags
= extract32(insn
, 29, 1);
4490 rm
= extract32(insn
, 16, 5);
4491 rn
= extract32(insn
, 5, 5);
4492 rd
= extract32(insn
, 0, 5);
4494 tcg_rd
= cpu_reg(s
, rd
);
4495 tcg_rn
= cpu_reg(s
, rn
);
4498 tcg_y
= new_tmp_a64(s
);
4499 tcg_gen_not_i64(tcg_y
, cpu_reg(s
, rm
));
4501 tcg_y
= cpu_reg(s
, rm
);
4505 gen_adc_CC(sf
, tcg_rd
, tcg_rn
, tcg_y
);
4507 gen_adc(sf
, tcg_rd
, tcg_rn
, tcg_y
);
4511 /* Conditional compare (immediate / register)
4512 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
4513 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
4514 * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
4515 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
4518 static void disas_cc(DisasContext
*s
, uint32_t insn
)
4520 unsigned int sf
, op
, y
, cond
, rn
, nzcv
, is_imm
;
4521 TCGv_i32 tcg_t0
, tcg_t1
, tcg_t2
;
4522 TCGv_i64 tcg_tmp
, tcg_y
, tcg_rn
;
4525 if (!extract32(insn
, 29, 1)) {
4526 unallocated_encoding(s
);
4529 if (insn
& (1 << 10 | 1 << 4)) {
4530 unallocated_encoding(s
);
4533 sf
= extract32(insn
, 31, 1);
4534 op
= extract32(insn
, 30, 1);
4535 is_imm
= extract32(insn
, 11, 1);
4536 y
= extract32(insn
, 16, 5); /* y = rm (reg) or imm5 (imm) */
4537 cond
= extract32(insn
, 12, 4);
4538 rn
= extract32(insn
, 5, 5);
4539 nzcv
= extract32(insn
, 0, 4);
4541 /* Set T0 = !COND. */
4542 tcg_t0
= tcg_temp_new_i32();
4543 arm_test_cc(&c
, cond
);
4544 tcg_gen_setcondi_i32(tcg_invert_cond(c
.cond
), tcg_t0
, c
.value
, 0);
4547 /* Load the arguments for the new comparison. */
4549 tcg_y
= new_tmp_a64(s
);
4550 tcg_gen_movi_i64(tcg_y
, y
);
4552 tcg_y
= cpu_reg(s
, y
);
4554 tcg_rn
= cpu_reg(s
, rn
);
4556 /* Set the flags for the new comparison. */
4557 tcg_tmp
= tcg_temp_new_i64();
4559 gen_sub_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
4561 gen_add_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
4563 tcg_temp_free_i64(tcg_tmp
);
4565 /* If COND was false, force the flags to #nzcv. Compute two masks
4566 * to help with this: T1 = (COND ? 0 : -1), T2 = (COND ? -1 : 0).
4567 * For tcg hosts that support ANDC, we can make do with just T1.
4568 * In either case, allow the tcg optimizer to delete any unused mask.
4570 tcg_t1
= tcg_temp_new_i32();
4571 tcg_t2
= tcg_temp_new_i32();
4572 tcg_gen_neg_i32(tcg_t1
, tcg_t0
);
4573 tcg_gen_subi_i32(tcg_t2
, tcg_t0
, 1);
4575 if (nzcv
& 8) { /* N */
4576 tcg_gen_or_i32(cpu_NF
, cpu_NF
, tcg_t1
);
4578 if (TCG_TARGET_HAS_andc_i32
) {
4579 tcg_gen_andc_i32(cpu_NF
, cpu_NF
, tcg_t1
);
4581 tcg_gen_and_i32(cpu_NF
, cpu_NF
, tcg_t2
);
4584 if (nzcv
& 4) { /* Z */
4585 if (TCG_TARGET_HAS_andc_i32
) {
4586 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, tcg_t1
);
4588 tcg_gen_and_i32(cpu_ZF
, cpu_ZF
, tcg_t2
);
4591 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, tcg_t0
);
4593 if (nzcv
& 2) { /* C */
4594 tcg_gen_or_i32(cpu_CF
, cpu_CF
, tcg_t0
);
4596 if (TCG_TARGET_HAS_andc_i32
) {
4597 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, tcg_t1
);
4599 tcg_gen_and_i32(cpu_CF
, cpu_CF
, tcg_t2
);
4602 if (nzcv
& 1) { /* V */
4603 tcg_gen_or_i32(cpu_VF
, cpu_VF
, tcg_t1
);
4605 if (TCG_TARGET_HAS_andc_i32
) {
4606 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tcg_t1
);
4608 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tcg_t2
);
4611 tcg_temp_free_i32(tcg_t0
);
4612 tcg_temp_free_i32(tcg_t1
);
4613 tcg_temp_free_i32(tcg_t2
);
4616 /* Conditional select
4617 * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
4618 * +----+----+---+-----------------+------+------+-----+------+------+
4619 * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
4620 * +----+----+---+-----------------+------+------+-----+------+------+
4622 static void disas_cond_select(DisasContext
*s
, uint32_t insn
)
4624 unsigned int sf
, else_inv
, rm
, cond
, else_inc
, rn
, rd
;
4625 TCGv_i64 tcg_rd
, zero
;
4628 if (extract32(insn
, 29, 1) || extract32(insn
, 11, 1)) {
4629 /* S == 1 or op2<1> == 1 */
4630 unallocated_encoding(s
);
4633 sf
= extract32(insn
, 31, 1);
4634 else_inv
= extract32(insn
, 30, 1);
4635 rm
= extract32(insn
, 16, 5);
4636 cond
= extract32(insn
, 12, 4);
4637 else_inc
= extract32(insn
, 10, 1);
4638 rn
= extract32(insn
, 5, 5);
4639 rd
= extract32(insn
, 0, 5);
4641 tcg_rd
= cpu_reg(s
, rd
);
4643 a64_test_cc(&c
, cond
);
4644 zero
= tcg_const_i64(0);
4646 if (rn
== 31 && rm
== 31 && (else_inc
^ else_inv
)) {
4648 tcg_gen_setcond_i64(tcg_invert_cond(c
.cond
), tcg_rd
, c
.value
, zero
);
4650 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
4653 TCGv_i64 t_true
= cpu_reg(s
, rn
);
4654 TCGv_i64 t_false
= read_cpu_reg(s
, rm
, 1);
4655 if (else_inv
&& else_inc
) {
4656 tcg_gen_neg_i64(t_false
, t_false
);
4657 } else if (else_inv
) {
4658 tcg_gen_not_i64(t_false
, t_false
);
4659 } else if (else_inc
) {
4660 tcg_gen_addi_i64(t_false
, t_false
, 1);
4662 tcg_gen_movcond_i64(c
.cond
, tcg_rd
, c
.value
, zero
, t_true
, t_false
);
4665 tcg_temp_free_i64(zero
);
4669 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4673 static void handle_clz(DisasContext
*s
, unsigned int sf
,
4674 unsigned int rn
, unsigned int rd
)
4676 TCGv_i64 tcg_rd
, tcg_rn
;
4677 tcg_rd
= cpu_reg(s
, rd
);
4678 tcg_rn
= cpu_reg(s
, rn
);
4681 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
4683 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4684 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4685 tcg_gen_clzi_i32(tcg_tmp32
, tcg_tmp32
, 32);
4686 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4687 tcg_temp_free_i32(tcg_tmp32
);
4691 static void handle_cls(DisasContext
*s
, unsigned int sf
,
4692 unsigned int rn
, unsigned int rd
)
4694 TCGv_i64 tcg_rd
, tcg_rn
;
4695 tcg_rd
= cpu_reg(s
, rd
);
4696 tcg_rn
= cpu_reg(s
, rn
);
4699 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
4701 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4702 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4703 tcg_gen_clrsb_i32(tcg_tmp32
, tcg_tmp32
);
4704 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4705 tcg_temp_free_i32(tcg_tmp32
);
4709 static void handle_rbit(DisasContext
*s
, unsigned int sf
,
4710 unsigned int rn
, unsigned int rd
)
4712 TCGv_i64 tcg_rd
, tcg_rn
;
4713 tcg_rd
= cpu_reg(s
, rd
);
4714 tcg_rn
= cpu_reg(s
, rn
);
4717 gen_helper_rbit64(tcg_rd
, tcg_rn
);
4719 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4720 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4721 gen_helper_rbit(tcg_tmp32
, tcg_tmp32
);
4722 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4723 tcg_temp_free_i32(tcg_tmp32
);
4727 /* REV with sf==1, opcode==3 ("REV64") */
4728 static void handle_rev64(DisasContext
*s
, unsigned int sf
,
4729 unsigned int rn
, unsigned int rd
)
4732 unallocated_encoding(s
);
4735 tcg_gen_bswap64_i64(cpu_reg(s
, rd
), cpu_reg(s
, rn
));
4738 /* REV with sf==0, opcode==2
4739 * REV32 (sf==1, opcode==2)
4741 static void handle_rev32(DisasContext
*s
, unsigned int sf
,
4742 unsigned int rn
, unsigned int rd
)
4744 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4747 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4748 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4750 /* bswap32_i64 requires zero high word */
4751 tcg_gen_ext32u_i64(tcg_tmp
, tcg_rn
);
4752 tcg_gen_bswap32_i64(tcg_rd
, tcg_tmp
);
4753 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
4754 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
4755 tcg_gen_concat32_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
4757 tcg_temp_free_i64(tcg_tmp
);
4759 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rn
));
4760 tcg_gen_bswap32_i64(tcg_rd
, tcg_rd
);
4764 /* REV16 (opcode==1) */
4765 static void handle_rev16(DisasContext
*s
, unsigned int sf
,
4766 unsigned int rn
, unsigned int rd
)
4768 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4769 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4770 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4771 TCGv_i64 mask
= tcg_const_i64(sf
? 0x00ff00ff00ff00ffull
: 0x00ff00ff);
4773 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 8);
4774 tcg_gen_and_i64(tcg_rd
, tcg_rn
, mask
);
4775 tcg_gen_and_i64(tcg_tmp
, tcg_tmp
, mask
);
4776 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, 8);
4777 tcg_gen_or_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
4779 tcg_temp_free_i64(mask
);
4780 tcg_temp_free_i64(tcg_tmp
);
4783 /* Data-processing (1 source)
4784 * 31 30 29 28 21 20 16 15 10 9 5 4 0
4785 * +----+---+---+-----------------+---------+--------+------+------+
4786 * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
4787 * +----+---+---+-----------------+---------+--------+------+------+
4789 static void disas_data_proc_1src(DisasContext
*s
, uint32_t insn
)
4791 unsigned int sf
, opcode
, opcode2
, rn
, rd
;
4794 if (extract32(insn
, 29, 1)) {
4795 unallocated_encoding(s
);
4799 sf
= extract32(insn
, 31, 1);
4800 opcode
= extract32(insn
, 10, 6);
4801 opcode2
= extract32(insn
, 16, 5);
4802 rn
= extract32(insn
, 5, 5);
4803 rd
= extract32(insn
, 0, 5);
4805 #define MAP(SF, O2, O1) ((SF) | (O1 << 1) | (O2 << 7))
4807 switch (MAP(sf
, opcode2
, opcode
)) {
4808 case MAP(0, 0x00, 0x00): /* RBIT */
4809 case MAP(1, 0x00, 0x00):
4810 handle_rbit(s
, sf
, rn
, rd
);
4812 case MAP(0, 0x00, 0x01): /* REV16 */
4813 case MAP(1, 0x00, 0x01):
4814 handle_rev16(s
, sf
, rn
, rd
);
4816 case MAP(0, 0x00, 0x02): /* REV/REV32 */
4817 case MAP(1, 0x00, 0x02):
4818 handle_rev32(s
, sf
, rn
, rd
);
4820 case MAP(1, 0x00, 0x03): /* REV64 */
4821 handle_rev64(s
, sf
, rn
, rd
);
4823 case MAP(0, 0x00, 0x04): /* CLZ */
4824 case MAP(1, 0x00, 0x04):
4825 handle_clz(s
, sf
, rn
, rd
);
4827 case MAP(0, 0x00, 0x05): /* CLS */
4828 case MAP(1, 0x00, 0x05):
4829 handle_cls(s
, sf
, rn
, rd
);
4831 case MAP(1, 0x01, 0x00): /* PACIA */
4832 if (s
->pauth_active
) {
4833 tcg_rd
= cpu_reg(s
, rd
);
4834 gen_helper_pacia(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4835 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4836 goto do_unallocated
;
4839 case MAP(1, 0x01, 0x01): /* PACIB */
4840 if (s
->pauth_active
) {
4841 tcg_rd
= cpu_reg(s
, rd
);
4842 gen_helper_pacib(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4843 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4844 goto do_unallocated
;
4847 case MAP(1, 0x01, 0x02): /* PACDA */
4848 if (s
->pauth_active
) {
4849 tcg_rd
= cpu_reg(s
, rd
);
4850 gen_helper_pacda(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4851 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4852 goto do_unallocated
;
4855 case MAP(1, 0x01, 0x03): /* PACDB */
4856 if (s
->pauth_active
) {
4857 tcg_rd
= cpu_reg(s
, rd
);
4858 gen_helper_pacdb(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4859 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4860 goto do_unallocated
;
4863 case MAP(1, 0x01, 0x04): /* AUTIA */
4864 if (s
->pauth_active
) {
4865 tcg_rd
= cpu_reg(s
, rd
);
4866 gen_helper_autia(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4867 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4868 goto do_unallocated
;
4871 case MAP(1, 0x01, 0x05): /* AUTIB */
4872 if (s
->pauth_active
) {
4873 tcg_rd
= cpu_reg(s
, rd
);
4874 gen_helper_autib(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4875 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4876 goto do_unallocated
;
4879 case MAP(1, 0x01, 0x06): /* AUTDA */
4880 if (s
->pauth_active
) {
4881 tcg_rd
= cpu_reg(s
, rd
);
4882 gen_helper_autda(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4883 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4884 goto do_unallocated
;
4887 case MAP(1, 0x01, 0x07): /* AUTDB */
4888 if (s
->pauth_active
) {
4889 tcg_rd
= cpu_reg(s
, rd
);
4890 gen_helper_autdb(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
4891 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
4892 goto do_unallocated
;
4895 case MAP(1, 0x01, 0x08): /* PACIZA */
4896 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4897 goto do_unallocated
;
4898 } else if (s
->pauth_active
) {
4899 tcg_rd
= cpu_reg(s
, rd
);
4900 gen_helper_pacia(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
4903 case MAP(1, 0x01, 0x09): /* PACIZB */
4904 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4905 goto do_unallocated
;
4906 } else if (s
->pauth_active
) {
4907 tcg_rd
= cpu_reg(s
, rd
);
4908 gen_helper_pacib(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
4911 case MAP(1, 0x01, 0x0a): /* PACDZA */
4912 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4913 goto do_unallocated
;
4914 } else if (s
->pauth_active
) {
4915 tcg_rd
= cpu_reg(s
, rd
);
4916 gen_helper_pacda(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
4919 case MAP(1, 0x01, 0x0b): /* PACDZB */
4920 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4921 goto do_unallocated
;
4922 } else if (s
->pauth_active
) {
4923 tcg_rd
= cpu_reg(s
, rd
);
4924 gen_helper_pacdb(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
4927 case MAP(1, 0x01, 0x0c): /* AUTIZA */
4928 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4929 goto do_unallocated
;
4930 } else if (s
->pauth_active
) {
4931 tcg_rd
= cpu_reg(s
, rd
);
4932 gen_helper_autia(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
4935 case MAP(1, 0x01, 0x0d): /* AUTIZB */
4936 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4937 goto do_unallocated
;
4938 } else if (s
->pauth_active
) {
4939 tcg_rd
= cpu_reg(s
, rd
);
4940 gen_helper_autib(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
4943 case MAP(1, 0x01, 0x0e): /* AUTDZA */
4944 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4945 goto do_unallocated
;
4946 } else if (s
->pauth_active
) {
4947 tcg_rd
= cpu_reg(s
, rd
);
4948 gen_helper_autda(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
4951 case MAP(1, 0x01, 0x0f): /* AUTDZB */
4952 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4953 goto do_unallocated
;
4954 } else if (s
->pauth_active
) {
4955 tcg_rd
= cpu_reg(s
, rd
);
4956 gen_helper_autdb(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
4959 case MAP(1, 0x01, 0x10): /* XPACI */
4960 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4961 goto do_unallocated
;
4962 } else if (s
->pauth_active
) {
4963 tcg_rd
= cpu_reg(s
, rd
);
4964 gen_helper_xpaci(tcg_rd
, cpu_env
, tcg_rd
);
4967 case MAP(1, 0x01, 0x11): /* XPACD */
4968 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
4969 goto do_unallocated
;
4970 } else if (s
->pauth_active
) {
4971 tcg_rd
= cpu_reg(s
, rd
);
4972 gen_helper_xpacd(tcg_rd
, cpu_env
, tcg_rd
);
4977 unallocated_encoding(s
);
4984 static void handle_div(DisasContext
*s
, bool is_signed
, unsigned int sf
,
4985 unsigned int rm
, unsigned int rn
, unsigned int rd
)
4987 TCGv_i64 tcg_n
, tcg_m
, tcg_rd
;
4988 tcg_rd
= cpu_reg(s
, rd
);
4990 if (!sf
&& is_signed
) {
4991 tcg_n
= new_tmp_a64(s
);
4992 tcg_m
= new_tmp_a64(s
);
4993 tcg_gen_ext32s_i64(tcg_n
, cpu_reg(s
, rn
));
4994 tcg_gen_ext32s_i64(tcg_m
, cpu_reg(s
, rm
));
4996 tcg_n
= read_cpu_reg(s
, rn
, sf
);
4997 tcg_m
= read_cpu_reg(s
, rm
, sf
);
5001 gen_helper_sdiv64(tcg_rd
, tcg_n
, tcg_m
);
5003 gen_helper_udiv64(tcg_rd
, tcg_n
, tcg_m
);
5006 if (!sf
) { /* zero extend final result */
5007 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
5011 /* LSLV, LSRV, ASRV, RORV */
5012 static void handle_shift_reg(DisasContext
*s
,
5013 enum a64_shift_type shift_type
, unsigned int sf
,
5014 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5016 TCGv_i64 tcg_shift
= tcg_temp_new_i64();
5017 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5018 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
5020 tcg_gen_andi_i64(tcg_shift
, cpu_reg(s
, rm
), sf
? 63 : 31);
5021 shift_reg(tcg_rd
, tcg_rn
, sf
, shift_type
, tcg_shift
);
5022 tcg_temp_free_i64(tcg_shift
);
5025 /* CRC32[BHWX], CRC32C[BHWX] */
5026 static void handle_crc32(DisasContext
*s
,
5027 unsigned int sf
, unsigned int sz
, bool crc32c
,
5028 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5030 TCGv_i64 tcg_acc
, tcg_val
;
5033 if (!dc_isar_feature(aa64_crc32
, s
)
5034 || (sf
== 1 && sz
!= 3)
5035 || (sf
== 0 && sz
== 3)) {
5036 unallocated_encoding(s
);
5041 tcg_val
= cpu_reg(s
, rm
);
5055 g_assert_not_reached();
5057 tcg_val
= new_tmp_a64(s
);
5058 tcg_gen_andi_i64(tcg_val
, cpu_reg(s
, rm
), mask
);
5061 tcg_acc
= cpu_reg(s
, rn
);
5062 tcg_bytes
= tcg_const_i32(1 << sz
);
5065 gen_helper_crc32c_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
5067 gen_helper_crc32_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
5070 tcg_temp_free_i32(tcg_bytes
);
5073 /* Data-processing (2 source)
5074 * 31 30 29 28 21 20 16 15 10 9 5 4 0
5075 * +----+---+---+-----------------+------+--------+------+------+
5076 * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
5077 * +----+---+---+-----------------+------+--------+------+------+
5079 static void disas_data_proc_2src(DisasContext
*s
, uint32_t insn
)
5081 unsigned int sf
, rm
, opcode
, rn
, rd
;
5082 sf
= extract32(insn
, 31, 1);
5083 rm
= extract32(insn
, 16, 5);
5084 opcode
= extract32(insn
, 10, 6);
5085 rn
= extract32(insn
, 5, 5);
5086 rd
= extract32(insn
, 0, 5);
5088 if (extract32(insn
, 29, 1)) {
5089 unallocated_encoding(s
);
5095 handle_div(s
, false, sf
, rm
, rn
, rd
);
5098 handle_div(s
, true, sf
, rm
, rn
, rd
);
5101 handle_shift_reg(s
, A64_SHIFT_TYPE_LSL
, sf
, rm
, rn
, rd
);
5104 handle_shift_reg(s
, A64_SHIFT_TYPE_LSR
, sf
, rm
, rn
, rd
);
5107 handle_shift_reg(s
, A64_SHIFT_TYPE_ASR
, sf
, rm
, rn
, rd
);
5110 handle_shift_reg(s
, A64_SHIFT_TYPE_ROR
, sf
, rm
, rn
, rd
);
5112 case 12: /* PACGA */
5113 if (sf
== 0 || !dc_isar_feature(aa64_pauth
, s
)) {
5114 goto do_unallocated
;
5116 gen_helper_pacga(cpu_reg(s
, rd
), cpu_env
,
5117 cpu_reg(s
, rn
), cpu_reg_sp(s
, rm
));
5126 case 23: /* CRC32 */
5128 int sz
= extract32(opcode
, 0, 2);
5129 bool crc32c
= extract32(opcode
, 2, 1);
5130 handle_crc32(s
, sf
, sz
, crc32c
, rm
, rn
, rd
);
5135 unallocated_encoding(s
);
5140 /* Data processing - register */
5141 static void disas_data_proc_reg(DisasContext
*s
, uint32_t insn
)
5143 switch (extract32(insn
, 24, 5)) {
5144 case 0x0a: /* Logical (shifted register) */
5145 disas_logic_reg(s
, insn
);
5147 case 0x0b: /* Add/subtract */
5148 if (insn
& (1 << 21)) { /* (extended register) */
5149 disas_add_sub_ext_reg(s
, insn
);
5151 disas_add_sub_reg(s
, insn
);
5154 case 0x1b: /* Data-processing (3 source) */
5155 disas_data_proc_3src(s
, insn
);
5158 switch (extract32(insn
, 21, 3)) {
5159 case 0x0: /* Add/subtract (with carry) */
5160 disas_adc_sbc(s
, insn
);
5162 case 0x2: /* Conditional compare */
5163 disas_cc(s
, insn
); /* both imm and reg forms */
5165 case 0x4: /* Conditional select */
5166 disas_cond_select(s
, insn
);
5168 case 0x6: /* Data-processing */
5169 if (insn
& (1 << 30)) { /* (1 source) */
5170 disas_data_proc_1src(s
, insn
);
5171 } else { /* (2 source) */
5172 disas_data_proc_2src(s
, insn
);
5176 unallocated_encoding(s
);
5181 unallocated_encoding(s
);
5186 static void handle_fp_compare(DisasContext
*s
, int size
,
5187 unsigned int rn
, unsigned int rm
,
5188 bool cmp_with_zero
, bool signal_all_nans
)
5190 TCGv_i64 tcg_flags
= tcg_temp_new_i64();
5191 TCGv_ptr fpst
= get_fpstatus_ptr(size
== MO_16
);
5193 if (size
== MO_64
) {
5194 TCGv_i64 tcg_vn
, tcg_vm
;
5196 tcg_vn
= read_fp_dreg(s
, rn
);
5197 if (cmp_with_zero
) {
5198 tcg_vm
= tcg_const_i64(0);
5200 tcg_vm
= read_fp_dreg(s
, rm
);
5202 if (signal_all_nans
) {
5203 gen_helper_vfp_cmped_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5205 gen_helper_vfp_cmpd_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5207 tcg_temp_free_i64(tcg_vn
);
5208 tcg_temp_free_i64(tcg_vm
);
5210 TCGv_i32 tcg_vn
= tcg_temp_new_i32();
5211 TCGv_i32 tcg_vm
= tcg_temp_new_i32();
5213 read_vec_element_i32(s
, tcg_vn
, rn
, 0, size
);
5214 if (cmp_with_zero
) {
5215 tcg_gen_movi_i32(tcg_vm
, 0);
5217 read_vec_element_i32(s
, tcg_vm
, rm
, 0, size
);
5222 if (signal_all_nans
) {
5223 gen_helper_vfp_cmpes_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5225 gen_helper_vfp_cmps_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5229 if (signal_all_nans
) {
5230 gen_helper_vfp_cmpeh_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5232 gen_helper_vfp_cmph_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5236 g_assert_not_reached();
5239 tcg_temp_free_i32(tcg_vn
);
5240 tcg_temp_free_i32(tcg_vm
);
5243 tcg_temp_free_ptr(fpst
);
5245 gen_set_nzcv(tcg_flags
);
5247 tcg_temp_free_i64(tcg_flags
);
5250 /* Floating point compare
5251 * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
5252 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
5253 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
5254 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
5256 static void disas_fp_compare(DisasContext
*s
, uint32_t insn
)
5258 unsigned int mos
, type
, rm
, op
, rn
, opc
, op2r
;
5261 mos
= extract32(insn
, 29, 3);
5262 type
= extract32(insn
, 22, 2);
5263 rm
= extract32(insn
, 16, 5);
5264 op
= extract32(insn
, 14, 2);
5265 rn
= extract32(insn
, 5, 5);
5266 opc
= extract32(insn
, 3, 2);
5267 op2r
= extract32(insn
, 0, 3);
5269 if (mos
|| op
|| op2r
) {
5270 unallocated_encoding(s
);
5283 if (dc_isar_feature(aa64_fp16
, s
)) {
5288 unallocated_encoding(s
);
5292 if (!fp_access_check(s
)) {
5296 handle_fp_compare(s
, size
, rn
, rm
, opc
& 1, opc
& 2);
5299 /* Floating point conditional compare
5300 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
5301 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
5302 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
5303 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
5305 static void disas_fp_ccomp(DisasContext
*s
, uint32_t insn
)
5307 unsigned int mos
, type
, rm
, cond
, rn
, op
, nzcv
;
5309 TCGLabel
*label_continue
= NULL
;
5312 mos
= extract32(insn
, 29, 3);
5313 type
= extract32(insn
, 22, 2);
5314 rm
= extract32(insn
, 16, 5);
5315 cond
= extract32(insn
, 12, 4);
5316 rn
= extract32(insn
, 5, 5);
5317 op
= extract32(insn
, 4, 1);
5318 nzcv
= extract32(insn
, 0, 4);
5321 unallocated_encoding(s
);
5334 if (dc_isar_feature(aa64_fp16
, s
)) {
5339 unallocated_encoding(s
);
5343 if (!fp_access_check(s
)) {
5347 if (cond
< 0x0e) { /* not always */
5348 TCGLabel
*label_match
= gen_new_label();
5349 label_continue
= gen_new_label();
5350 arm_gen_test_cc(cond
, label_match
);
5352 tcg_flags
= tcg_const_i64(nzcv
<< 28);
5353 gen_set_nzcv(tcg_flags
);
5354 tcg_temp_free_i64(tcg_flags
);
5355 tcg_gen_br(label_continue
);
5356 gen_set_label(label_match
);
5359 handle_fp_compare(s
, size
, rn
, rm
, false, op
);
5362 gen_set_label(label_continue
);
5366 /* Floating point conditional select
5367 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
5368 * +---+---+---+-----------+------+---+------+------+-----+------+------+
5369 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
5370 * +---+---+---+-----------+------+---+------+------+-----+------+------+
5372 static void disas_fp_csel(DisasContext
*s
, uint32_t insn
)
5374 unsigned int mos
, type
, rm
, cond
, rn
, rd
;
5375 TCGv_i64 t_true
, t_false
, t_zero
;
5379 mos
= extract32(insn
, 29, 3);
5380 type
= extract32(insn
, 22, 2);
5381 rm
= extract32(insn
, 16, 5);
5382 cond
= extract32(insn
, 12, 4);
5383 rn
= extract32(insn
, 5, 5);
5384 rd
= extract32(insn
, 0, 5);
5387 unallocated_encoding(s
);
5400 if (dc_isar_feature(aa64_fp16
, s
)) {
5405 unallocated_encoding(s
);
5409 if (!fp_access_check(s
)) {
5413 /* Zero extend sreg & hreg inputs to 64 bits now. */
5414 t_true
= tcg_temp_new_i64();
5415 t_false
= tcg_temp_new_i64();
5416 read_vec_element(s
, t_true
, rn
, 0, sz
);
5417 read_vec_element(s
, t_false
, rm
, 0, sz
);
5419 a64_test_cc(&c
, cond
);
5420 t_zero
= tcg_const_i64(0);
5421 tcg_gen_movcond_i64(c
.cond
, t_true
, c
.value
, t_zero
, t_true
, t_false
);
5422 tcg_temp_free_i64(t_zero
);
5423 tcg_temp_free_i64(t_false
);
5426 /* Note that sregs & hregs write back zeros to the high bits,
5427 and we've already done the zero-extension. */
5428 write_fp_dreg(s
, rd
, t_true
);
5429 tcg_temp_free_i64(t_true
);
5432 /* Floating-point data-processing (1 source) - half precision */
5433 static void handle_fp_1src_half(DisasContext
*s
, int opcode
, int rd
, int rn
)
5435 TCGv_ptr fpst
= NULL
;
5436 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
5437 TCGv_i32 tcg_res
= tcg_temp_new_i32();
5440 case 0x0: /* FMOV */
5441 tcg_gen_mov_i32(tcg_res
, tcg_op
);
5443 case 0x1: /* FABS */
5444 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
5446 case 0x2: /* FNEG */
5447 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
5449 case 0x3: /* FSQRT */
5450 fpst
= get_fpstatus_ptr(true);
5451 gen_helper_sqrt_f16(tcg_res
, tcg_op
, fpst
);
5453 case 0x8: /* FRINTN */
5454 case 0x9: /* FRINTP */
5455 case 0xa: /* FRINTM */
5456 case 0xb: /* FRINTZ */
5457 case 0xc: /* FRINTA */
5459 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
5460 fpst
= get_fpstatus_ptr(true);
5462 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5463 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
5465 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5466 tcg_temp_free_i32(tcg_rmode
);
5469 case 0xe: /* FRINTX */
5470 fpst
= get_fpstatus_ptr(true);
5471 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, fpst
);
5473 case 0xf: /* FRINTI */
5474 fpst
= get_fpstatus_ptr(true);
5475 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
5481 write_fp_sreg(s
, rd
, tcg_res
);
5484 tcg_temp_free_ptr(fpst
);
5486 tcg_temp_free_i32(tcg_op
);
5487 tcg_temp_free_i32(tcg_res
);
5490 /* Floating-point data-processing (1 source) - single precision */
5491 static void handle_fp_1src_single(DisasContext
*s
, int opcode
, int rd
, int rn
)
5497 fpst
= get_fpstatus_ptr(false);
5498 tcg_op
= read_fp_sreg(s
, rn
);
5499 tcg_res
= tcg_temp_new_i32();
5502 case 0x0: /* FMOV */
5503 tcg_gen_mov_i32(tcg_res
, tcg_op
);
5505 case 0x1: /* FABS */
5506 gen_helper_vfp_abss(tcg_res
, tcg_op
);
5508 case 0x2: /* FNEG */
5509 gen_helper_vfp_negs(tcg_res
, tcg_op
);
5511 case 0x3: /* FSQRT */
5512 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
5514 case 0x8: /* FRINTN */
5515 case 0x9: /* FRINTP */
5516 case 0xa: /* FRINTM */
5517 case 0xb: /* FRINTZ */
5518 case 0xc: /* FRINTA */
5520 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
5522 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5523 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
5525 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5526 tcg_temp_free_i32(tcg_rmode
);
5529 case 0xe: /* FRINTX */
5530 gen_helper_rints_exact(tcg_res
, tcg_op
, fpst
);
5532 case 0xf: /* FRINTI */
5533 gen_helper_rints(tcg_res
, tcg_op
, fpst
);
5539 write_fp_sreg(s
, rd
, tcg_res
);
5541 tcg_temp_free_ptr(fpst
);
5542 tcg_temp_free_i32(tcg_op
);
5543 tcg_temp_free_i32(tcg_res
);
5546 /* Floating-point data-processing (1 source) - double precision */
5547 static void handle_fp_1src_double(DisasContext
*s
, int opcode
, int rd
, int rn
)
5554 case 0x0: /* FMOV */
5555 gen_gvec_fn2(s
, false, rd
, rn
, tcg_gen_gvec_mov
, 0);
5559 fpst
= get_fpstatus_ptr(false);
5560 tcg_op
= read_fp_dreg(s
, rn
);
5561 tcg_res
= tcg_temp_new_i64();
5564 case 0x1: /* FABS */
5565 gen_helper_vfp_absd(tcg_res
, tcg_op
);
5567 case 0x2: /* FNEG */
5568 gen_helper_vfp_negd(tcg_res
, tcg_op
);
5570 case 0x3: /* FSQRT */
5571 gen_helper_vfp_sqrtd(tcg_res
, tcg_op
, cpu_env
);
5573 case 0x8: /* FRINTN */
5574 case 0x9: /* FRINTP */
5575 case 0xa: /* FRINTM */
5576 case 0xb: /* FRINTZ */
5577 case 0xc: /* FRINTA */
5579 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
5581 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5582 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
5584 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5585 tcg_temp_free_i32(tcg_rmode
);
5588 case 0xe: /* FRINTX */
5589 gen_helper_rintd_exact(tcg_res
, tcg_op
, fpst
);
5591 case 0xf: /* FRINTI */
5592 gen_helper_rintd(tcg_res
, tcg_op
, fpst
);
5598 write_fp_dreg(s
, rd
, tcg_res
);
5600 tcg_temp_free_ptr(fpst
);
5601 tcg_temp_free_i64(tcg_op
);
5602 tcg_temp_free_i64(tcg_res
);
5605 static void handle_fp_fcvt(DisasContext
*s
, int opcode
,
5606 int rd
, int rn
, int dtype
, int ntype
)
5611 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
5613 /* Single to double */
5614 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
5615 gen_helper_vfp_fcvtds(tcg_rd
, tcg_rn
, cpu_env
);
5616 write_fp_dreg(s
, rd
, tcg_rd
);
5617 tcg_temp_free_i64(tcg_rd
);
5619 /* Single to half */
5620 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5621 TCGv_i32 ahp
= get_ahp_flag();
5622 TCGv_ptr fpst
= get_fpstatus_ptr(false);
5624 gen_helper_vfp_fcvt_f32_to_f16(tcg_rd
, tcg_rn
, fpst
, ahp
);
5625 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
5626 write_fp_sreg(s
, rd
, tcg_rd
);
5627 tcg_temp_free_i32(tcg_rd
);
5628 tcg_temp_free_i32(ahp
);
5629 tcg_temp_free_ptr(fpst
);
5631 tcg_temp_free_i32(tcg_rn
);
5636 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
5637 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5639 /* Double to single */
5640 gen_helper_vfp_fcvtsd(tcg_rd
, tcg_rn
, cpu_env
);
5642 TCGv_ptr fpst
= get_fpstatus_ptr(false);
5643 TCGv_i32 ahp
= get_ahp_flag();
5644 /* Double to half */
5645 gen_helper_vfp_fcvt_f64_to_f16(tcg_rd
, tcg_rn
, fpst
, ahp
);
5646 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
5647 tcg_temp_free_ptr(fpst
);
5648 tcg_temp_free_i32(ahp
);
5650 write_fp_sreg(s
, rd
, tcg_rd
);
5651 tcg_temp_free_i32(tcg_rd
);
5652 tcg_temp_free_i64(tcg_rn
);
5657 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
5658 TCGv_ptr tcg_fpst
= get_fpstatus_ptr(false);
5659 TCGv_i32 tcg_ahp
= get_ahp_flag();
5660 tcg_gen_ext16u_i32(tcg_rn
, tcg_rn
);
5662 /* Half to single */
5663 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5664 gen_helper_vfp_fcvt_f16_to_f32(tcg_rd
, tcg_rn
, tcg_fpst
, tcg_ahp
);
5665 write_fp_sreg(s
, rd
, tcg_rd
);
5666 tcg_temp_free_ptr(tcg_fpst
);
5667 tcg_temp_free_i32(tcg_ahp
);
5668 tcg_temp_free_i32(tcg_rd
);
5670 /* Half to double */
5671 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
5672 gen_helper_vfp_fcvt_f16_to_f64(tcg_rd
, tcg_rn
, tcg_fpst
, tcg_ahp
);
5673 write_fp_dreg(s
, rd
, tcg_rd
);
5674 tcg_temp_free_i64(tcg_rd
);
5676 tcg_temp_free_i32(tcg_rn
);
5684 /* Floating point data-processing (1 source)
5685 * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
5686 * +---+---+---+-----------+------+---+--------+-----------+------+------+
5687 * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
5688 * +---+---+---+-----------+------+---+--------+-----------+------+------+
5690 static void disas_fp_1src(DisasContext
*s
, uint32_t insn
)
5692 int mos
= extract32(insn
, 29, 3);
5693 int type
= extract32(insn
, 22, 2);
5694 int opcode
= extract32(insn
, 15, 6);
5695 int rn
= extract32(insn
, 5, 5);
5696 int rd
= extract32(insn
, 0, 5);
5699 unallocated_encoding(s
);
5704 case 0x4: case 0x5: case 0x7:
5706 /* FCVT between half, single and double precision */
5707 int dtype
= extract32(opcode
, 0, 2);
5708 if (type
== 2 || dtype
== type
) {
5709 unallocated_encoding(s
);
5712 if (!fp_access_check(s
)) {
5716 handle_fp_fcvt(s
, opcode
, rd
, rn
, dtype
, type
);
5722 /* 32-to-32 and 64-to-64 ops */
5725 if (!fp_access_check(s
)) {
5729 handle_fp_1src_single(s
, opcode
, rd
, rn
);
5732 if (!fp_access_check(s
)) {
5736 handle_fp_1src_double(s
, opcode
, rd
, rn
);
5739 if (!dc_isar_feature(aa64_fp16
, s
)) {
5740 unallocated_encoding(s
);
5744 if (!fp_access_check(s
)) {
5748 handle_fp_1src_half(s
, opcode
, rd
, rn
);
5751 unallocated_encoding(s
);
5755 unallocated_encoding(s
);
5760 /* Floating-point data-processing (2 source) - single precision */
5761 static void handle_fp_2src_single(DisasContext
*s
, int opcode
,
5762 int rd
, int rn
, int rm
)
5769 tcg_res
= tcg_temp_new_i32();
5770 fpst
= get_fpstatus_ptr(false);
5771 tcg_op1
= read_fp_sreg(s
, rn
);
5772 tcg_op2
= read_fp_sreg(s
, rm
);
5775 case 0x0: /* FMUL */
5776 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5778 case 0x1: /* FDIV */
5779 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5781 case 0x2: /* FADD */
5782 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5784 case 0x3: /* FSUB */
5785 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5787 case 0x4: /* FMAX */
5788 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5790 case 0x5: /* FMIN */
5791 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5793 case 0x6: /* FMAXNM */
5794 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5796 case 0x7: /* FMINNM */
5797 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5799 case 0x8: /* FNMUL */
5800 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5801 gen_helper_vfp_negs(tcg_res
, tcg_res
);
5805 write_fp_sreg(s
, rd
, tcg_res
);
5807 tcg_temp_free_ptr(fpst
);
5808 tcg_temp_free_i32(tcg_op1
);
5809 tcg_temp_free_i32(tcg_op2
);
5810 tcg_temp_free_i32(tcg_res
);
5813 /* Floating-point data-processing (2 source) - double precision */
5814 static void handle_fp_2src_double(DisasContext
*s
, int opcode
,
5815 int rd
, int rn
, int rm
)
5822 tcg_res
= tcg_temp_new_i64();
5823 fpst
= get_fpstatus_ptr(false);
5824 tcg_op1
= read_fp_dreg(s
, rn
);
5825 tcg_op2
= read_fp_dreg(s
, rm
);
5828 case 0x0: /* FMUL */
5829 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5831 case 0x1: /* FDIV */
5832 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5834 case 0x2: /* FADD */
5835 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5837 case 0x3: /* FSUB */
5838 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5840 case 0x4: /* FMAX */
5841 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5843 case 0x5: /* FMIN */
5844 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5846 case 0x6: /* FMAXNM */
5847 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5849 case 0x7: /* FMINNM */
5850 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5852 case 0x8: /* FNMUL */
5853 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5854 gen_helper_vfp_negd(tcg_res
, tcg_res
);
5858 write_fp_dreg(s
, rd
, tcg_res
);
5860 tcg_temp_free_ptr(fpst
);
5861 tcg_temp_free_i64(tcg_op1
);
5862 tcg_temp_free_i64(tcg_op2
);
5863 tcg_temp_free_i64(tcg_res
);
5866 /* Floating-point data-processing (2 source) - half precision */
5867 static void handle_fp_2src_half(DisasContext
*s
, int opcode
,
5868 int rd
, int rn
, int rm
)
5875 tcg_res
= tcg_temp_new_i32();
5876 fpst
= get_fpstatus_ptr(true);
5877 tcg_op1
= read_fp_hreg(s
, rn
);
5878 tcg_op2
= read_fp_hreg(s
, rm
);
5881 case 0x0: /* FMUL */
5882 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5884 case 0x1: /* FDIV */
5885 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5887 case 0x2: /* FADD */
5888 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5890 case 0x3: /* FSUB */
5891 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5893 case 0x4: /* FMAX */
5894 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5896 case 0x5: /* FMIN */
5897 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5899 case 0x6: /* FMAXNM */
5900 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5902 case 0x7: /* FMINNM */
5903 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5905 case 0x8: /* FNMUL */
5906 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
5907 tcg_gen_xori_i32(tcg_res
, tcg_res
, 0x8000);
5910 g_assert_not_reached();
5913 write_fp_sreg(s
, rd
, tcg_res
);
5915 tcg_temp_free_ptr(fpst
);
5916 tcg_temp_free_i32(tcg_op1
);
5917 tcg_temp_free_i32(tcg_op2
);
5918 tcg_temp_free_i32(tcg_res
);
5921 /* Floating point data-processing (2 source)
5922 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
5923 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
5924 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
5925 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
5927 static void disas_fp_2src(DisasContext
*s
, uint32_t insn
)
5929 int mos
= extract32(insn
, 29, 3);
5930 int type
= extract32(insn
, 22, 2);
5931 int rd
= extract32(insn
, 0, 5);
5932 int rn
= extract32(insn
, 5, 5);
5933 int rm
= extract32(insn
, 16, 5);
5934 int opcode
= extract32(insn
, 12, 4);
5936 if (opcode
> 8 || mos
) {
5937 unallocated_encoding(s
);
5943 if (!fp_access_check(s
)) {
5946 handle_fp_2src_single(s
, opcode
, rd
, rn
, rm
);
5949 if (!fp_access_check(s
)) {
5952 handle_fp_2src_double(s
, opcode
, rd
, rn
, rm
);
5955 if (!dc_isar_feature(aa64_fp16
, s
)) {
5956 unallocated_encoding(s
);
5959 if (!fp_access_check(s
)) {
5962 handle_fp_2src_half(s
, opcode
, rd
, rn
, rm
);
5965 unallocated_encoding(s
);
5969 /* Floating-point data-processing (3 source) - single precision */
5970 static void handle_fp_3src_single(DisasContext
*s
, bool o0
, bool o1
,
5971 int rd
, int rn
, int rm
, int ra
)
5973 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
5974 TCGv_i32 tcg_res
= tcg_temp_new_i32();
5975 TCGv_ptr fpst
= get_fpstatus_ptr(false);
5977 tcg_op1
= read_fp_sreg(s
, rn
);
5978 tcg_op2
= read_fp_sreg(s
, rm
);
5979 tcg_op3
= read_fp_sreg(s
, ra
);
5981 /* These are fused multiply-add, and must be done as one
5982 * floating point operation with no rounding between the
5983 * multiplication and addition steps.
5984 * NB that doing the negations here as separate steps is
5985 * correct : an input NaN should come out with its sign bit
5986 * flipped if it is a negated-input.
5989 gen_helper_vfp_negs(tcg_op3
, tcg_op3
);
5993 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
5996 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
5998 write_fp_sreg(s
, rd
, tcg_res
);
6000 tcg_temp_free_ptr(fpst
);
6001 tcg_temp_free_i32(tcg_op1
);
6002 tcg_temp_free_i32(tcg_op2
);
6003 tcg_temp_free_i32(tcg_op3
);
6004 tcg_temp_free_i32(tcg_res
);
6007 /* Floating-point data-processing (3 source) - double precision */
6008 static void handle_fp_3src_double(DisasContext
*s
, bool o0
, bool o1
,
6009 int rd
, int rn
, int rm
, int ra
)
6011 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
;
6012 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6013 TCGv_ptr fpst
= get_fpstatus_ptr(false);
6015 tcg_op1
= read_fp_dreg(s
, rn
);
6016 tcg_op2
= read_fp_dreg(s
, rm
);
6017 tcg_op3
= read_fp_dreg(s
, ra
);
6019 /* These are fused multiply-add, and must be done as one
6020 * floating point operation with no rounding between the
6021 * multiplication and addition steps.
6022 * NB that doing the negations here as separate steps is
6023 * correct : an input NaN should come out with its sign bit
6024 * flipped if it is a negated-input.
6027 gen_helper_vfp_negd(tcg_op3
, tcg_op3
);
6031 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
6034 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6036 write_fp_dreg(s
, rd
, tcg_res
);
6038 tcg_temp_free_ptr(fpst
);
6039 tcg_temp_free_i64(tcg_op1
);
6040 tcg_temp_free_i64(tcg_op2
);
6041 tcg_temp_free_i64(tcg_op3
);
6042 tcg_temp_free_i64(tcg_res
);
6045 /* Floating-point data-processing (3 source) - half precision */
6046 static void handle_fp_3src_half(DisasContext
*s
, bool o0
, bool o1
,
6047 int rd
, int rn
, int rm
, int ra
)
6049 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
6050 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6051 TCGv_ptr fpst
= get_fpstatus_ptr(true);
6053 tcg_op1
= read_fp_hreg(s
, rn
);
6054 tcg_op2
= read_fp_hreg(s
, rm
);
6055 tcg_op3
= read_fp_hreg(s
, ra
);
6057 /* These are fused multiply-add, and must be done as one
6058 * floating point operation with no rounding between the
6059 * multiplication and addition steps.
6060 * NB that doing the negations here as separate steps is
6061 * correct : an input NaN should come out with its sign bit
6062 * flipped if it is a negated-input.
6065 tcg_gen_xori_i32(tcg_op3
, tcg_op3
, 0x8000);
6069 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
6072 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6074 write_fp_sreg(s
, rd
, tcg_res
);
6076 tcg_temp_free_ptr(fpst
);
6077 tcg_temp_free_i32(tcg_op1
);
6078 tcg_temp_free_i32(tcg_op2
);
6079 tcg_temp_free_i32(tcg_op3
);
6080 tcg_temp_free_i32(tcg_res
);
6083 /* Floating point data-processing (3 source)
6084 * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
6085 * +---+---+---+-----------+------+----+------+----+------+------+------+
6086 * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
6087 * +---+---+---+-----------+------+----+------+----+------+------+------+
6089 static void disas_fp_3src(DisasContext
*s
, uint32_t insn
)
6091 int mos
= extract32(insn
, 29, 3);
6092 int type
= extract32(insn
, 22, 2);
6093 int rd
= extract32(insn
, 0, 5);
6094 int rn
= extract32(insn
, 5, 5);
6095 int ra
= extract32(insn
, 10, 5);
6096 int rm
= extract32(insn
, 16, 5);
6097 bool o0
= extract32(insn
, 15, 1);
6098 bool o1
= extract32(insn
, 21, 1);
6101 unallocated_encoding(s
);
6107 if (!fp_access_check(s
)) {
6110 handle_fp_3src_single(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6113 if (!fp_access_check(s
)) {
6116 handle_fp_3src_double(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6119 if (!dc_isar_feature(aa64_fp16
, s
)) {
6120 unallocated_encoding(s
);
6123 if (!fp_access_check(s
)) {
6126 handle_fp_3src_half(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6129 unallocated_encoding(s
);
6133 /* The imm8 encodes the sign bit, enough bits to represent an exponent in
6134 * the range 01....1xx to 10....0xx, and the most significant 4 bits of
6135 * the mantissa; see VFPExpandImm() in the v8 ARM ARM.
6137 uint64_t vfp_expand_imm(int size
, uint8_t imm8
)
6143 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
6144 (extract32(imm8
, 6, 1) ? 0x3fc0 : 0x4000) |
6145 extract32(imm8
, 0, 6);
6149 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
6150 (extract32(imm8
, 6, 1) ? 0x3e00 : 0x4000) |
6151 (extract32(imm8
, 0, 6) << 3);
6155 imm
= (extract32(imm8
, 7, 1) ? 0x8000 : 0) |
6156 (extract32(imm8
, 6, 1) ? 0x3000 : 0x4000) |
6157 (extract32(imm8
, 0, 6) << 6);
6160 g_assert_not_reached();
6165 /* Floating point immediate
6166 * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
6167 * +---+---+---+-----------+------+---+------------+-------+------+------+
6168 * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
6169 * +---+---+---+-----------+------+---+------------+-------+------+------+
6171 static void disas_fp_imm(DisasContext
*s
, uint32_t insn
)
6173 int rd
= extract32(insn
, 0, 5);
6174 int imm5
= extract32(insn
, 5, 5);
6175 int imm8
= extract32(insn
, 13, 8);
6176 int type
= extract32(insn
, 22, 2);
6177 int mos
= extract32(insn
, 29, 3);
6183 unallocated_encoding(s
);
6196 if (dc_isar_feature(aa64_fp16
, s
)) {
6201 unallocated_encoding(s
);
6205 if (!fp_access_check(s
)) {
6209 imm
= vfp_expand_imm(sz
, imm8
);
6211 tcg_res
= tcg_const_i64(imm
);
6212 write_fp_dreg(s
, rd
, tcg_res
);
6213 tcg_temp_free_i64(tcg_res
);
6216 /* Handle floating point <=> fixed point conversions. Note that we can
6217 * also deal with fp <=> integer conversions as a special case (scale == 64)
6218 * OPTME: consider handling that special case specially or at least skipping
6219 * the call to scalbn in the helpers for zero shifts.
6221 static void handle_fpfpcvt(DisasContext
*s
, int rd
, int rn
, int opcode
,
6222 bool itof
, int rmode
, int scale
, int sf
, int type
)
6224 bool is_signed
= !(opcode
& 1);
6225 TCGv_ptr tcg_fpstatus
;
6226 TCGv_i32 tcg_shift
, tcg_single
;
6227 TCGv_i64 tcg_double
;
6229 tcg_fpstatus
= get_fpstatus_ptr(type
== 3);
6231 tcg_shift
= tcg_const_i32(64 - scale
);
6234 TCGv_i64 tcg_int
= cpu_reg(s
, rn
);
6236 TCGv_i64 tcg_extend
= new_tmp_a64(s
);
6239 tcg_gen_ext32s_i64(tcg_extend
, tcg_int
);
6241 tcg_gen_ext32u_i64(tcg_extend
, tcg_int
);
6244 tcg_int
= tcg_extend
;
6248 case 1: /* float64 */
6249 tcg_double
= tcg_temp_new_i64();
6251 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
6252 tcg_shift
, tcg_fpstatus
);
6254 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
6255 tcg_shift
, tcg_fpstatus
);
6257 write_fp_dreg(s
, rd
, tcg_double
);
6258 tcg_temp_free_i64(tcg_double
);
6261 case 0: /* float32 */
6262 tcg_single
= tcg_temp_new_i32();
6264 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
6265 tcg_shift
, tcg_fpstatus
);
6267 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
6268 tcg_shift
, tcg_fpstatus
);
6270 write_fp_sreg(s
, rd
, tcg_single
);
6271 tcg_temp_free_i32(tcg_single
);
6274 case 3: /* float16 */
6275 tcg_single
= tcg_temp_new_i32();
6277 gen_helper_vfp_sqtoh(tcg_single
, tcg_int
,
6278 tcg_shift
, tcg_fpstatus
);
6280 gen_helper_vfp_uqtoh(tcg_single
, tcg_int
,
6281 tcg_shift
, tcg_fpstatus
);
6283 write_fp_sreg(s
, rd
, tcg_single
);
6284 tcg_temp_free_i32(tcg_single
);
6288 g_assert_not_reached();
6291 TCGv_i64 tcg_int
= cpu_reg(s
, rd
);
6294 if (extract32(opcode
, 2, 1)) {
6295 /* There are too many rounding modes to all fit into rmode,
6296 * so FCVTA[US] is a special case.
6298 rmode
= FPROUNDING_TIEAWAY
;
6301 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
6303 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
6306 case 1: /* float64 */
6307 tcg_double
= read_fp_dreg(s
, rn
);
6310 gen_helper_vfp_tosld(tcg_int
, tcg_double
,
6311 tcg_shift
, tcg_fpstatus
);
6313 gen_helper_vfp_tosqd(tcg_int
, tcg_double
,
6314 tcg_shift
, tcg_fpstatus
);
6318 gen_helper_vfp_tould(tcg_int
, tcg_double
,
6319 tcg_shift
, tcg_fpstatus
);
6321 gen_helper_vfp_touqd(tcg_int
, tcg_double
,
6322 tcg_shift
, tcg_fpstatus
);
6326 tcg_gen_ext32u_i64(tcg_int
, tcg_int
);
6328 tcg_temp_free_i64(tcg_double
);
6331 case 0: /* float32 */
6332 tcg_single
= read_fp_sreg(s
, rn
);
6335 gen_helper_vfp_tosqs(tcg_int
, tcg_single
,
6336 tcg_shift
, tcg_fpstatus
);
6338 gen_helper_vfp_touqs(tcg_int
, tcg_single
,
6339 tcg_shift
, tcg_fpstatus
);
6342 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
6344 gen_helper_vfp_tosls(tcg_dest
, tcg_single
,
6345 tcg_shift
, tcg_fpstatus
);
6347 gen_helper_vfp_touls(tcg_dest
, tcg_single
,
6348 tcg_shift
, tcg_fpstatus
);
6350 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
6351 tcg_temp_free_i32(tcg_dest
);
6353 tcg_temp_free_i32(tcg_single
);
6356 case 3: /* float16 */
6357 tcg_single
= read_fp_sreg(s
, rn
);
6360 gen_helper_vfp_tosqh(tcg_int
, tcg_single
,
6361 tcg_shift
, tcg_fpstatus
);
6363 gen_helper_vfp_touqh(tcg_int
, tcg_single
,
6364 tcg_shift
, tcg_fpstatus
);
6367 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
6369 gen_helper_vfp_toslh(tcg_dest
, tcg_single
,
6370 tcg_shift
, tcg_fpstatus
);
6372 gen_helper_vfp_toulh(tcg_dest
, tcg_single
,
6373 tcg_shift
, tcg_fpstatus
);
6375 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
6376 tcg_temp_free_i32(tcg_dest
);
6378 tcg_temp_free_i32(tcg_single
);
6382 g_assert_not_reached();
6385 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
6386 tcg_temp_free_i32(tcg_rmode
);
6389 tcg_temp_free_ptr(tcg_fpstatus
);
6390 tcg_temp_free_i32(tcg_shift
);
6393 /* Floating point <-> fixed point conversions
6394 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
6395 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
6396 * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
6397 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
6399 static void disas_fp_fixed_conv(DisasContext
*s
, uint32_t insn
)
6401 int rd
= extract32(insn
, 0, 5);
6402 int rn
= extract32(insn
, 5, 5);
6403 int scale
= extract32(insn
, 10, 6);
6404 int opcode
= extract32(insn
, 16, 3);
6405 int rmode
= extract32(insn
, 19, 2);
6406 int type
= extract32(insn
, 22, 2);
6407 bool sbit
= extract32(insn
, 29, 1);
6408 bool sf
= extract32(insn
, 31, 1);
6411 if (sbit
|| (!sf
&& scale
< 32)) {
6412 unallocated_encoding(s
);
6417 case 0: /* float32 */
6418 case 1: /* float64 */
6420 case 3: /* float16 */
6421 if (dc_isar_feature(aa64_fp16
, s
)) {
6426 unallocated_encoding(s
);
6430 switch ((rmode
<< 3) | opcode
) {
6431 case 0x2: /* SCVTF */
6432 case 0x3: /* UCVTF */
6435 case 0x18: /* FCVTZS */
6436 case 0x19: /* FCVTZU */
6440 unallocated_encoding(s
);
6444 if (!fp_access_check(s
)) {
6448 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, FPROUNDING_ZERO
, scale
, sf
, type
);
6451 static void handle_fmov(DisasContext
*s
, int rd
, int rn
, int type
, bool itof
)
6453 /* FMOV: gpr to or from float, double, or top half of quad fp reg,
6454 * without conversion.
6458 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
6464 tmp
= tcg_temp_new_i64();
6465 tcg_gen_ext32u_i64(tmp
, tcg_rn
);
6466 write_fp_dreg(s
, rd
, tmp
);
6467 tcg_temp_free_i64(tmp
);
6471 write_fp_dreg(s
, rd
, tcg_rn
);
6474 /* 64 bit to top half. */
6475 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_hi_offset(s
, rd
));
6476 clear_vec_high(s
, true, rd
);
6480 tmp
= tcg_temp_new_i64();
6481 tcg_gen_ext16u_i64(tmp
, tcg_rn
);
6482 write_fp_dreg(s
, rd
, tmp
);
6483 tcg_temp_free_i64(tmp
);
6486 g_assert_not_reached();
6489 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
6494 tcg_gen_ld32u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_32
));
6498 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_64
));
6501 /* 64 bits from top half */
6502 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_hi_offset(s
, rn
));
6506 tcg_gen_ld16u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_16
));
6509 g_assert_not_reached();
6514 /* Floating point <-> integer conversions
6515 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
6516 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
6517 * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
6518 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
6520 static void disas_fp_int_conv(DisasContext
*s
, uint32_t insn
)
6522 int rd
= extract32(insn
, 0, 5);
6523 int rn
= extract32(insn
, 5, 5);
6524 int opcode
= extract32(insn
, 16, 3);
6525 int rmode
= extract32(insn
, 19, 2);
6526 int type
= extract32(insn
, 22, 2);
6527 bool sbit
= extract32(insn
, 29, 1);
6528 bool sf
= extract32(insn
, 31, 1);
6531 unallocated_encoding(s
);
6537 bool itof
= opcode
& 1;
6540 unallocated_encoding(s
);
6544 switch (sf
<< 3 | type
<< 1 | rmode
) {
6545 case 0x0: /* 32 bit */
6546 case 0xa: /* 64 bit */
6547 case 0xd: /* 64 bit to top half of quad */
6549 case 0x6: /* 16-bit float, 32-bit int */
6550 case 0xe: /* 16-bit float, 64-bit int */
6551 if (dc_isar_feature(aa64_fp16
, s
)) {
6556 /* all other sf/type/rmode combinations are invalid */
6557 unallocated_encoding(s
);
6561 if (!fp_access_check(s
)) {
6564 handle_fmov(s
, rd
, rn
, type
, itof
);
6566 /* actual FP conversions */
6567 bool itof
= extract32(opcode
, 1, 1);
6569 if (rmode
!= 0 && opcode
> 1) {
6570 unallocated_encoding(s
);
6574 case 0: /* float32 */
6575 case 1: /* float64 */
6577 case 3: /* float16 */
6578 if (dc_isar_feature(aa64_fp16
, s
)) {
6583 unallocated_encoding(s
);
6587 if (!fp_access_check(s
)) {
6590 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, rmode
, 64, sf
, type
);
6594 /* FP-specific subcases of table C3-6 (SIMD and FP data processing)
6595 * 31 30 29 28 25 24 0
6596 * +---+---+---+---------+-----------------------------+
6597 * | | 0 | | 1 1 1 1 | |
6598 * +---+---+---+---------+-----------------------------+
6600 static void disas_data_proc_fp(DisasContext
*s
, uint32_t insn
)
6602 if (extract32(insn
, 24, 1)) {
6603 /* Floating point data-processing (3 source) */
6604 disas_fp_3src(s
, insn
);
6605 } else if (extract32(insn
, 21, 1) == 0) {
6606 /* Floating point to fixed point conversions */
6607 disas_fp_fixed_conv(s
, insn
);
6609 switch (extract32(insn
, 10, 2)) {
6611 /* Floating point conditional compare */
6612 disas_fp_ccomp(s
, insn
);
6615 /* Floating point data-processing (2 source) */
6616 disas_fp_2src(s
, insn
);
6619 /* Floating point conditional select */
6620 disas_fp_csel(s
, insn
);
6623 switch (ctz32(extract32(insn
, 12, 4))) {
6624 case 0: /* [15:12] == xxx1 */
6625 /* Floating point immediate */
6626 disas_fp_imm(s
, insn
);
6628 case 1: /* [15:12] == xx10 */
6629 /* Floating point compare */
6630 disas_fp_compare(s
, insn
);
6632 case 2: /* [15:12] == x100 */
6633 /* Floating point data-processing (1 source) */
6634 disas_fp_1src(s
, insn
);
6636 case 3: /* [15:12] == 1000 */
6637 unallocated_encoding(s
);
6639 default: /* [15:12] == 0000 */
6640 /* Floating point <-> integer conversions */
6641 disas_fp_int_conv(s
, insn
);
6649 static void do_ext64(DisasContext
*s
, TCGv_i64 tcg_left
, TCGv_i64 tcg_right
,
6652 /* Extract 64 bits from the middle of two concatenated 64 bit
6653 * vector register slices left:right. The extracted bits start
6654 * at 'pos' bits into the right (least significant) side.
6655 * We return the result in tcg_right, and guarantee not to
6658 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
6659 assert(pos
> 0 && pos
< 64);
6661 tcg_gen_shri_i64(tcg_right
, tcg_right
, pos
);
6662 tcg_gen_shli_i64(tcg_tmp
, tcg_left
, 64 - pos
);
6663 tcg_gen_or_i64(tcg_right
, tcg_right
, tcg_tmp
);
6665 tcg_temp_free_i64(tcg_tmp
);
6669 * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
6670 * +---+---+-------------+-----+---+------+---+------+---+------+------+
6671 * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
6672 * +---+---+-------------+-----+---+------+---+------+---+------+------+
6674 static void disas_simd_ext(DisasContext
*s
, uint32_t insn
)
6676 int is_q
= extract32(insn
, 30, 1);
6677 int op2
= extract32(insn
, 22, 2);
6678 int imm4
= extract32(insn
, 11, 4);
6679 int rm
= extract32(insn
, 16, 5);
6680 int rn
= extract32(insn
, 5, 5);
6681 int rd
= extract32(insn
, 0, 5);
6682 int pos
= imm4
<< 3;
6683 TCGv_i64 tcg_resl
, tcg_resh
;
6685 if (op2
!= 0 || (!is_q
&& extract32(imm4
, 3, 1))) {
6686 unallocated_encoding(s
);
6690 if (!fp_access_check(s
)) {
6694 tcg_resh
= tcg_temp_new_i64();
6695 tcg_resl
= tcg_temp_new_i64();
6697 /* Vd gets bits starting at pos bits into Vm:Vn. This is
6698 * either extracting 128 bits from a 128:128 concatenation, or
6699 * extracting 64 bits from a 64:64 concatenation.
6702 read_vec_element(s
, tcg_resl
, rn
, 0, MO_64
);
6704 read_vec_element(s
, tcg_resh
, rm
, 0, MO_64
);
6705 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
6707 tcg_gen_movi_i64(tcg_resh
, 0);
6714 EltPosns eltposns
[] = { {rn
, 0}, {rn
, 1}, {rm
, 0}, {rm
, 1} };
6715 EltPosns
*elt
= eltposns
;
6722 read_vec_element(s
, tcg_resl
, elt
->reg
, elt
->elt
, MO_64
);
6724 read_vec_element(s
, tcg_resh
, elt
->reg
, elt
->elt
, MO_64
);
6727 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
6728 tcg_hh
= tcg_temp_new_i64();
6729 read_vec_element(s
, tcg_hh
, elt
->reg
, elt
->elt
, MO_64
);
6730 do_ext64(s
, tcg_hh
, tcg_resh
, pos
);
6731 tcg_temp_free_i64(tcg_hh
);
6735 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
6736 tcg_temp_free_i64(tcg_resl
);
6737 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
6738 tcg_temp_free_i64(tcg_resh
);
6742 * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
6743 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
6744 * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
6745 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
6747 static void disas_simd_tb(DisasContext
*s
, uint32_t insn
)
6749 int op2
= extract32(insn
, 22, 2);
6750 int is_q
= extract32(insn
, 30, 1);
6751 int rm
= extract32(insn
, 16, 5);
6752 int rn
= extract32(insn
, 5, 5);
6753 int rd
= extract32(insn
, 0, 5);
6754 int is_tblx
= extract32(insn
, 12, 1);
6755 int len
= extract32(insn
, 13, 2);
6756 TCGv_i64 tcg_resl
, tcg_resh
, tcg_idx
;
6757 TCGv_i32 tcg_regno
, tcg_numregs
;
6760 unallocated_encoding(s
);
6764 if (!fp_access_check(s
)) {
6768 /* This does a table lookup: for every byte element in the input
6769 * we index into a table formed from up to four vector registers,
6770 * and then the output is the result of the lookups. Our helper
6771 * function does the lookup operation for a single 64 bit part of
6774 tcg_resl
= tcg_temp_new_i64();
6775 tcg_resh
= tcg_temp_new_i64();
6778 read_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
6780 tcg_gen_movi_i64(tcg_resl
, 0);
6782 if (is_tblx
&& is_q
) {
6783 read_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
6785 tcg_gen_movi_i64(tcg_resh
, 0);
6788 tcg_idx
= tcg_temp_new_i64();
6789 tcg_regno
= tcg_const_i32(rn
);
6790 tcg_numregs
= tcg_const_i32(len
+ 1);
6791 read_vec_element(s
, tcg_idx
, rm
, 0, MO_64
);
6792 gen_helper_simd_tbl(tcg_resl
, cpu_env
, tcg_resl
, tcg_idx
,
6793 tcg_regno
, tcg_numregs
);
6795 read_vec_element(s
, tcg_idx
, rm
, 1, MO_64
);
6796 gen_helper_simd_tbl(tcg_resh
, cpu_env
, tcg_resh
, tcg_idx
,
6797 tcg_regno
, tcg_numregs
);
6799 tcg_temp_free_i64(tcg_idx
);
6800 tcg_temp_free_i32(tcg_regno
);
6801 tcg_temp_free_i32(tcg_numregs
);
6803 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
6804 tcg_temp_free_i64(tcg_resl
);
6805 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
6806 tcg_temp_free_i64(tcg_resh
);
6810 * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
6811 * +---+---+-------------+------+---+------+---+------------------+------+
6812 * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
6813 * +---+---+-------------+------+---+------+---+------------------+------+
6815 static void disas_simd_zip_trn(DisasContext
*s
, uint32_t insn
)
6817 int rd
= extract32(insn
, 0, 5);
6818 int rn
= extract32(insn
, 5, 5);
6819 int rm
= extract32(insn
, 16, 5);
6820 int size
= extract32(insn
, 22, 2);
6821 /* opc field bits [1:0] indicate ZIP/UZP/TRN;
6822 * bit 2 indicates 1 vs 2 variant of the insn.
6824 int opcode
= extract32(insn
, 12, 2);
6825 bool part
= extract32(insn
, 14, 1);
6826 bool is_q
= extract32(insn
, 30, 1);
6827 int esize
= 8 << size
;
6829 int datasize
= is_q
? 128 : 64;
6830 int elements
= datasize
/ esize
;
6831 TCGv_i64 tcg_res
, tcg_resl
, tcg_resh
;
6833 if (opcode
== 0 || (size
== 3 && !is_q
)) {
6834 unallocated_encoding(s
);
6838 if (!fp_access_check(s
)) {
6842 tcg_resl
= tcg_const_i64(0);
6843 tcg_resh
= tcg_const_i64(0);
6844 tcg_res
= tcg_temp_new_i64();
6846 for (i
= 0; i
< elements
; i
++) {
6848 case 1: /* UZP1/2 */
6850 int midpoint
= elements
/ 2;
6852 read_vec_element(s
, tcg_res
, rn
, 2 * i
+ part
, size
);
6854 read_vec_element(s
, tcg_res
, rm
,
6855 2 * (i
- midpoint
) + part
, size
);
6859 case 2: /* TRN1/2 */
6861 read_vec_element(s
, tcg_res
, rm
, (i
& ~1) + part
, size
);
6863 read_vec_element(s
, tcg_res
, rn
, (i
& ~1) + part
, size
);
6866 case 3: /* ZIP1/2 */
6868 int base
= part
* elements
/ 2;
6870 read_vec_element(s
, tcg_res
, rm
, base
+ (i
>> 1), size
);
6872 read_vec_element(s
, tcg_res
, rn
, base
+ (i
>> 1), size
);
6877 g_assert_not_reached();
6882 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
);
6883 tcg_gen_or_i64(tcg_resl
, tcg_resl
, tcg_res
);
6885 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
- 64);
6886 tcg_gen_or_i64(tcg_resh
, tcg_resh
, tcg_res
);
6890 tcg_temp_free_i64(tcg_res
);
6892 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
6893 tcg_temp_free_i64(tcg_resl
);
6894 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
6895 tcg_temp_free_i64(tcg_resh
);
6899 * do_reduction_op helper
6901 * This mirrors the Reduce() pseudocode in the ARM ARM. It is
6902 * important for correct NaN propagation that we do these
6903 * operations in exactly the order specified by the pseudocode.
6905 * This is a recursive function, TCG temps should be freed by the
6906 * calling function once it is done with the values.
6908 static TCGv_i32
do_reduction_op(DisasContext
*s
, int fpopcode
, int rn
,
6909 int esize
, int size
, int vmap
, TCGv_ptr fpst
)
6911 if (esize
== size
) {
6913 TCGMemOp msize
= esize
== 16 ? MO_16
: MO_32
;
6916 /* We should have one register left here */
6917 assert(ctpop8(vmap
) == 1);
6918 element
= ctz32(vmap
);
6919 assert(element
< 8);
6921 tcg_elem
= tcg_temp_new_i32();
6922 read_vec_element_i32(s
, tcg_elem
, rn
, element
, msize
);
6925 int bits
= size
/ 2;
6926 int shift
= ctpop8(vmap
) / 2;
6927 int vmap_lo
= (vmap
>> shift
) & vmap
;
6928 int vmap_hi
= (vmap
& ~vmap_lo
);
6929 TCGv_i32 tcg_hi
, tcg_lo
, tcg_res
;
6931 tcg_hi
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_hi
, fpst
);
6932 tcg_lo
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_lo
, fpst
);
6933 tcg_res
= tcg_temp_new_i32();
6936 case 0x0c: /* fmaxnmv half-precision */
6937 gen_helper_advsimd_maxnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6939 case 0x0f: /* fmaxv half-precision */
6940 gen_helper_advsimd_maxh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6942 case 0x1c: /* fminnmv half-precision */
6943 gen_helper_advsimd_minnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6945 case 0x1f: /* fminv half-precision */
6946 gen_helper_advsimd_minh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6948 case 0x2c: /* fmaxnmv */
6949 gen_helper_vfp_maxnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6951 case 0x2f: /* fmaxv */
6952 gen_helper_vfp_maxs(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6954 case 0x3c: /* fminnmv */
6955 gen_helper_vfp_minnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6957 case 0x3f: /* fminv */
6958 gen_helper_vfp_mins(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
6961 g_assert_not_reached();
6964 tcg_temp_free_i32(tcg_hi
);
6965 tcg_temp_free_i32(tcg_lo
);
6970 /* AdvSIMD across lanes
6971 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
6972 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
6973 * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
6974 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
6976 static void disas_simd_across_lanes(DisasContext
*s
, uint32_t insn
)
6978 int rd
= extract32(insn
, 0, 5);
6979 int rn
= extract32(insn
, 5, 5);
6980 int size
= extract32(insn
, 22, 2);
6981 int opcode
= extract32(insn
, 12, 5);
6982 bool is_q
= extract32(insn
, 30, 1);
6983 bool is_u
= extract32(insn
, 29, 1);
6985 bool is_min
= false;
6989 TCGv_i64 tcg_res
, tcg_elt
;
6992 case 0x1b: /* ADDV */
6994 unallocated_encoding(s
);
6998 case 0x3: /* SADDLV, UADDLV */
6999 case 0xa: /* SMAXV, UMAXV */
7000 case 0x1a: /* SMINV, UMINV */
7001 if (size
== 3 || (size
== 2 && !is_q
)) {
7002 unallocated_encoding(s
);
7006 case 0xc: /* FMAXNMV, FMINNMV */
7007 case 0xf: /* FMAXV, FMINV */
7008 /* Bit 1 of size field encodes min vs max and the actual size
7009 * depends on the encoding of the U bit. If not set (and FP16
7010 * enabled) then we do half-precision float instead of single
7013 is_min
= extract32(size
, 1, 1);
7015 if (!is_u
&& dc_isar_feature(aa64_fp16
, s
)) {
7017 } else if (!is_u
|| !is_q
|| extract32(size
, 0, 1)) {
7018 unallocated_encoding(s
);
7025 unallocated_encoding(s
);
7029 if (!fp_access_check(s
)) {
7034 elements
= (is_q
? 128 : 64) / esize
;
7036 tcg_res
= tcg_temp_new_i64();
7037 tcg_elt
= tcg_temp_new_i64();
7039 /* These instructions operate across all lanes of a vector
7040 * to produce a single result. We can guarantee that a 64
7041 * bit intermediate is sufficient:
7042 * + for [US]ADDLV the maximum element size is 32 bits, and
7043 * the result type is 64 bits
7044 * + for FMAX*V, FMIN*V, ADDV the intermediate type is the
7045 * same as the element size, which is 32 bits at most
7046 * For the integer operations we can choose to work at 64
7047 * or 32 bits and truncate at the end; for simplicity
7048 * we use 64 bits always. The floating point
7049 * ops do require 32 bit intermediates, though.
7052 read_vec_element(s
, tcg_res
, rn
, 0, size
| (is_u
? 0 : MO_SIGN
));
7054 for (i
= 1; i
< elements
; i
++) {
7055 read_vec_element(s
, tcg_elt
, rn
, i
, size
| (is_u
? 0 : MO_SIGN
));
7058 case 0x03: /* SADDLV / UADDLV */
7059 case 0x1b: /* ADDV */
7060 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_elt
);
7062 case 0x0a: /* SMAXV / UMAXV */
7064 tcg_gen_umax_i64(tcg_res
, tcg_res
, tcg_elt
);
7066 tcg_gen_smax_i64(tcg_res
, tcg_res
, tcg_elt
);
7069 case 0x1a: /* SMINV / UMINV */
7071 tcg_gen_umin_i64(tcg_res
, tcg_res
, tcg_elt
);
7073 tcg_gen_smin_i64(tcg_res
, tcg_res
, tcg_elt
);
7077 g_assert_not_reached();
7082 /* Floating point vector reduction ops which work across 32
7083 * bit (single) or 16 bit (half-precision) intermediates.
7084 * Note that correct NaN propagation requires that we do these
7085 * operations in exactly the order specified by the pseudocode.
7087 TCGv_ptr fpst
= get_fpstatus_ptr(size
== MO_16
);
7088 int fpopcode
= opcode
| is_min
<< 4 | is_u
<< 5;
7089 int vmap
= (1 << elements
) - 1;
7090 TCGv_i32 tcg_res32
= do_reduction_op(s
, fpopcode
, rn
, esize
,
7091 (is_q
? 128 : 64), vmap
, fpst
);
7092 tcg_gen_extu_i32_i64(tcg_res
, tcg_res32
);
7093 tcg_temp_free_i32(tcg_res32
);
7094 tcg_temp_free_ptr(fpst
);
7097 tcg_temp_free_i64(tcg_elt
);
7099 /* Now truncate the result to the width required for the final output */
7100 if (opcode
== 0x03) {
7101 /* SADDLV, UADDLV: result is 2*esize */
7107 tcg_gen_ext8u_i64(tcg_res
, tcg_res
);
7110 tcg_gen_ext16u_i64(tcg_res
, tcg_res
);
7113 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
7118 g_assert_not_reached();
7121 write_fp_dreg(s
, rd
, tcg_res
);
7122 tcg_temp_free_i64(tcg_res
);
7125 /* DUP (Element, Vector)
7127 * 31 30 29 21 20 16 15 10 9 5 4 0
7128 * +---+---+-------------------+--------+-------------+------+------+
7129 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
7130 * +---+---+-------------------+--------+-------------+------+------+
7132 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7134 static void handle_simd_dupe(DisasContext
*s
, int is_q
, int rd
, int rn
,
7137 int size
= ctz32(imm5
);
7138 int index
= imm5
>> (size
+ 1);
7140 if (size
> 3 || (size
== 3 && !is_q
)) {
7141 unallocated_encoding(s
);
7145 if (!fp_access_check(s
)) {
7149 tcg_gen_gvec_dup_mem(size
, vec_full_reg_offset(s
, rd
),
7150 vec_reg_offset(s
, rn
, index
, size
),
7151 is_q
? 16 : 8, vec_full_reg_size(s
));
7154 /* DUP (element, scalar)
7155 * 31 21 20 16 15 10 9 5 4 0
7156 * +-----------------------+--------+-------------+------+------+
7157 * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
7158 * +-----------------------+--------+-------------+------+------+
7160 static void handle_simd_dupes(DisasContext
*s
, int rd
, int rn
,
7163 int size
= ctz32(imm5
);
7168 unallocated_encoding(s
);
7172 if (!fp_access_check(s
)) {
7176 index
= imm5
>> (size
+ 1);
7178 /* This instruction just extracts the specified element and
7179 * zero-extends it into the bottom of the destination register.
7181 tmp
= tcg_temp_new_i64();
7182 read_vec_element(s
, tmp
, rn
, index
, size
);
7183 write_fp_dreg(s
, rd
, tmp
);
7184 tcg_temp_free_i64(tmp
);
7189 * 31 30 29 21 20 16 15 10 9 5 4 0
7190 * +---+---+-------------------+--------+-------------+------+------+
7191 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd |
7192 * +---+---+-------------------+--------+-------------+------+------+
7194 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7196 static void handle_simd_dupg(DisasContext
*s
, int is_q
, int rd
, int rn
,
7199 int size
= ctz32(imm5
);
7200 uint32_t dofs
, oprsz
, maxsz
;
7202 if (size
> 3 || ((size
== 3) && !is_q
)) {
7203 unallocated_encoding(s
);
7207 if (!fp_access_check(s
)) {
7211 dofs
= vec_full_reg_offset(s
, rd
);
7212 oprsz
= is_q
? 16 : 8;
7213 maxsz
= vec_full_reg_size(s
);
7215 tcg_gen_gvec_dup_i64(size
, dofs
, oprsz
, maxsz
, cpu_reg(s
, rn
));
7220 * 31 21 20 16 15 14 11 10 9 5 4 0
7221 * +-----------------------+--------+------------+---+------+------+
7222 * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7223 * +-----------------------+--------+------------+---+------+------+
7225 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7226 * index: encoded in imm5<4:size+1>
7228 static void handle_simd_inse(DisasContext
*s
, int rd
, int rn
,
7231 int size
= ctz32(imm5
);
7232 int src_index
, dst_index
;
7236 unallocated_encoding(s
);
7240 if (!fp_access_check(s
)) {
7244 dst_index
= extract32(imm5
, 1+size
, 5);
7245 src_index
= extract32(imm4
, size
, 4);
7247 tmp
= tcg_temp_new_i64();
7249 read_vec_element(s
, tmp
, rn
, src_index
, size
);
7250 write_vec_element(s
, tmp
, rd
, dst_index
, size
);
7252 tcg_temp_free_i64(tmp
);
7258 * 31 21 20 16 15 10 9 5 4 0
7259 * +-----------------------+--------+-------------+------+------+
7260 * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd |
7261 * +-----------------------+--------+-------------+------+------+
7263 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7264 * index: encoded in imm5<4:size+1>
7266 static void handle_simd_insg(DisasContext
*s
, int rd
, int rn
, int imm5
)
7268 int size
= ctz32(imm5
);
7272 unallocated_encoding(s
);
7276 if (!fp_access_check(s
)) {
7280 idx
= extract32(imm5
, 1 + size
, 4 - size
);
7281 write_vec_element(s
, cpu_reg(s
, rn
), rd
, idx
, size
);
7288 * 31 30 29 21 20 16 15 12 10 9 5 4 0
7289 * +---+---+-------------------+--------+-------------+------+------+
7290 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd |
7291 * +---+---+-------------------+--------+-------------+------+------+
7293 * U: unsigned when set
7294 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7296 static void handle_simd_umov_smov(DisasContext
*s
, int is_q
, int is_signed
,
7297 int rn
, int rd
, int imm5
)
7299 int size
= ctz32(imm5
);
7303 /* Check for UnallocatedEncodings */
7305 if (size
> 2 || (size
== 2 && !is_q
)) {
7306 unallocated_encoding(s
);
7311 || (size
< 3 && is_q
)
7312 || (size
== 3 && !is_q
)) {
7313 unallocated_encoding(s
);
7318 if (!fp_access_check(s
)) {
7322 element
= extract32(imm5
, 1+size
, 4);
7324 tcg_rd
= cpu_reg(s
, rd
);
7325 read_vec_element(s
, tcg_rd
, rn
, element
, size
| (is_signed
? MO_SIGN
: 0));
7326 if (is_signed
&& !is_q
) {
7327 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
7332 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
7333 * +---+---+----+-----------------+------+---+------+---+------+------+
7334 * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7335 * +---+---+----+-----------------+------+---+------+---+------+------+
7337 static void disas_simd_copy(DisasContext
*s
, uint32_t insn
)
7339 int rd
= extract32(insn
, 0, 5);
7340 int rn
= extract32(insn
, 5, 5);
7341 int imm4
= extract32(insn
, 11, 4);
7342 int op
= extract32(insn
, 29, 1);
7343 int is_q
= extract32(insn
, 30, 1);
7344 int imm5
= extract32(insn
, 16, 5);
7349 handle_simd_inse(s
, rd
, rn
, imm4
, imm5
);
7351 unallocated_encoding(s
);
7356 /* DUP (element - vector) */
7357 handle_simd_dupe(s
, is_q
, rd
, rn
, imm5
);
7361 handle_simd_dupg(s
, is_q
, rd
, rn
, imm5
);
7366 handle_simd_insg(s
, rd
, rn
, imm5
);
7368 unallocated_encoding(s
);
7373 /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */
7374 handle_simd_umov_smov(s
, is_q
, (imm4
== 5), rn
, rd
, imm5
);
7377 unallocated_encoding(s
);
7383 /* AdvSIMD modified immediate
7384 * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
7385 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
7386 * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
7387 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
7389 * There are a number of operations that can be carried out here:
7390 * MOVI - move (shifted) imm into register
7391 * MVNI - move inverted (shifted) imm into register
7392 * ORR - bitwise OR of (shifted) imm with register
7393 * BIC - bitwise clear of (shifted) imm with register
7394 * With ARMv8.2 we also have:
7395 * FMOV half-precision
7397 static void disas_simd_mod_imm(DisasContext
*s
, uint32_t insn
)
7399 int rd
= extract32(insn
, 0, 5);
7400 int cmode
= extract32(insn
, 12, 4);
7401 int cmode_3_1
= extract32(cmode
, 1, 3);
7402 int cmode_0
= extract32(cmode
, 0, 1);
7403 int o2
= extract32(insn
, 11, 1);
7404 uint64_t abcdefgh
= extract32(insn
, 5, 5) | (extract32(insn
, 16, 3) << 5);
7405 bool is_neg
= extract32(insn
, 29, 1);
7406 bool is_q
= extract32(insn
, 30, 1);
7409 if (o2
!= 0 || ((cmode
== 0xf) && is_neg
&& !is_q
)) {
7410 /* Check for FMOV (vector, immediate) - half-precision */
7411 if (!(dc_isar_feature(aa64_fp16
, s
) && o2
&& cmode
== 0xf)) {
7412 unallocated_encoding(s
);
7417 if (!fp_access_check(s
)) {
7421 /* See AdvSIMDExpandImm() in ARM ARM */
7422 switch (cmode_3_1
) {
7423 case 0: /* Replicate(Zeros(24):imm8, 2) */
7424 case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
7425 case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
7426 case 3: /* Replicate(imm8:Zeros(24), 2) */
7428 int shift
= cmode_3_1
* 8;
7429 imm
= bitfield_replicate(abcdefgh
<< shift
, 32);
7432 case 4: /* Replicate(Zeros(8):imm8, 4) */
7433 case 5: /* Replicate(imm8:Zeros(8), 4) */
7435 int shift
= (cmode_3_1
& 0x1) * 8;
7436 imm
= bitfield_replicate(abcdefgh
<< shift
, 16);
7441 /* Replicate(Zeros(8):imm8:Ones(16), 2) */
7442 imm
= (abcdefgh
<< 16) | 0xffff;
7444 /* Replicate(Zeros(16):imm8:Ones(8), 2) */
7445 imm
= (abcdefgh
<< 8) | 0xff;
7447 imm
= bitfield_replicate(imm
, 32);
7450 if (!cmode_0
&& !is_neg
) {
7451 imm
= bitfield_replicate(abcdefgh
, 8);
7452 } else if (!cmode_0
&& is_neg
) {
7455 for (i
= 0; i
< 8; i
++) {
7456 if ((abcdefgh
) & (1 << i
)) {
7457 imm
|= 0xffULL
<< (i
* 8);
7460 } else if (cmode_0
) {
7462 imm
= (abcdefgh
& 0x3f) << 48;
7463 if (abcdefgh
& 0x80) {
7464 imm
|= 0x8000000000000000ULL
;
7466 if (abcdefgh
& 0x40) {
7467 imm
|= 0x3fc0000000000000ULL
;
7469 imm
|= 0x4000000000000000ULL
;
7473 /* FMOV (vector, immediate) - half-precision */
7474 imm
= vfp_expand_imm(MO_16
, abcdefgh
);
7475 /* now duplicate across the lanes */
7476 imm
= bitfield_replicate(imm
, 16);
7478 imm
= (abcdefgh
& 0x3f) << 19;
7479 if (abcdefgh
& 0x80) {
7482 if (abcdefgh
& 0x40) {
7493 fprintf(stderr
, "%s: cmode_3_1: %x\n", __func__
, cmode_3_1
);
7494 g_assert_not_reached();
7497 if (cmode_3_1
!= 7 && is_neg
) {
7501 if (!((cmode
& 0x9) == 0x1 || (cmode
& 0xd) == 0x9)) {
7502 /* MOVI or MVNI, with MVNI negation handled above. */
7503 tcg_gen_gvec_dup64i(vec_full_reg_offset(s
, rd
), is_q
? 16 : 8,
7504 vec_full_reg_size(s
), imm
);
7506 /* ORR or BIC, with BIC negation to AND handled above. */
7508 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_andi
, MO_64
);
7510 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_ori
, MO_64
);
7515 /* AdvSIMD scalar copy
7516 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
7517 * +-----+----+-----------------+------+---+------+---+------+------+
7518 * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7519 * +-----+----+-----------------+------+---+------+---+------+------+
7521 static void disas_simd_scalar_copy(DisasContext
*s
, uint32_t insn
)
7523 int rd
= extract32(insn
, 0, 5);
7524 int rn
= extract32(insn
, 5, 5);
7525 int imm4
= extract32(insn
, 11, 4);
7526 int imm5
= extract32(insn
, 16, 5);
7527 int op
= extract32(insn
, 29, 1);
7529 if (op
!= 0 || imm4
!= 0) {
7530 unallocated_encoding(s
);
7534 /* DUP (element, scalar) */
7535 handle_simd_dupes(s
, rd
, rn
, imm5
);
7538 /* AdvSIMD scalar pairwise
7539 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
7540 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7541 * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
7542 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7544 static void disas_simd_scalar_pairwise(DisasContext
*s
, uint32_t insn
)
7546 int u
= extract32(insn
, 29, 1);
7547 int size
= extract32(insn
, 22, 2);
7548 int opcode
= extract32(insn
, 12, 5);
7549 int rn
= extract32(insn
, 5, 5);
7550 int rd
= extract32(insn
, 0, 5);
7553 /* For some ops (the FP ones), size[1] is part of the encoding.
7554 * For ADDP strictly it is not but size[1] is always 1 for valid
7557 opcode
|= (extract32(size
, 1, 1) << 5);
7560 case 0x3b: /* ADDP */
7561 if (u
|| size
!= 3) {
7562 unallocated_encoding(s
);
7565 if (!fp_access_check(s
)) {
7571 case 0xc: /* FMAXNMP */
7572 case 0xd: /* FADDP */
7573 case 0xf: /* FMAXP */
7574 case 0x2c: /* FMINNMP */
7575 case 0x2f: /* FMINP */
7576 /* FP op, size[0] is 32 or 64 bit*/
7578 if (!dc_isar_feature(aa64_fp16
, s
)) {
7579 unallocated_encoding(s
);
7585 size
= extract32(size
, 0, 1) ? MO_64
: MO_32
;
7588 if (!fp_access_check(s
)) {
7592 fpst
= get_fpstatus_ptr(size
== MO_16
);
7595 unallocated_encoding(s
);
7599 if (size
== MO_64
) {
7600 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7601 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
7602 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7604 read_vec_element(s
, tcg_op1
, rn
, 0, MO_64
);
7605 read_vec_element(s
, tcg_op2
, rn
, 1, MO_64
);
7608 case 0x3b: /* ADDP */
7609 tcg_gen_add_i64(tcg_res
, tcg_op1
, tcg_op2
);
7611 case 0xc: /* FMAXNMP */
7612 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7614 case 0xd: /* FADDP */
7615 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7617 case 0xf: /* FMAXP */
7618 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7620 case 0x2c: /* FMINNMP */
7621 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7623 case 0x2f: /* FMINP */
7624 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7627 g_assert_not_reached();
7630 write_fp_dreg(s
, rd
, tcg_res
);
7632 tcg_temp_free_i64(tcg_op1
);
7633 tcg_temp_free_i64(tcg_op2
);
7634 tcg_temp_free_i64(tcg_res
);
7636 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
7637 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
7638 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7640 read_vec_element_i32(s
, tcg_op1
, rn
, 0, size
);
7641 read_vec_element_i32(s
, tcg_op2
, rn
, 1, size
);
7643 if (size
== MO_16
) {
7645 case 0xc: /* FMAXNMP */
7646 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7648 case 0xd: /* FADDP */
7649 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7651 case 0xf: /* FMAXP */
7652 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7654 case 0x2c: /* FMINNMP */
7655 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7657 case 0x2f: /* FMINP */
7658 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7661 g_assert_not_reached();
7665 case 0xc: /* FMAXNMP */
7666 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7668 case 0xd: /* FADDP */
7669 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7671 case 0xf: /* FMAXP */
7672 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7674 case 0x2c: /* FMINNMP */
7675 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7677 case 0x2f: /* FMINP */
7678 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7681 g_assert_not_reached();
7685 write_fp_sreg(s
, rd
, tcg_res
);
7687 tcg_temp_free_i32(tcg_op1
);
7688 tcg_temp_free_i32(tcg_op2
);
7689 tcg_temp_free_i32(tcg_res
);
7693 tcg_temp_free_ptr(fpst
);
7698 * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate)
7700 * This code is handles the common shifting code and is used by both
7701 * the vector and scalar code.
7703 static void handle_shri_with_rndacc(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
7704 TCGv_i64 tcg_rnd
, bool accumulate
,
7705 bool is_u
, int size
, int shift
)
7707 bool extended_result
= false;
7708 bool round
= tcg_rnd
!= NULL
;
7710 TCGv_i64 tcg_src_hi
;
7712 if (round
&& size
== 3) {
7713 extended_result
= true;
7714 ext_lshift
= 64 - shift
;
7715 tcg_src_hi
= tcg_temp_new_i64();
7716 } else if (shift
== 64) {
7717 if (!accumulate
&& is_u
) {
7718 /* result is zero */
7719 tcg_gen_movi_i64(tcg_res
, 0);
7724 /* Deal with the rounding step */
7726 if (extended_result
) {
7727 TCGv_i64 tcg_zero
= tcg_const_i64(0);
7729 /* take care of sign extending tcg_res */
7730 tcg_gen_sari_i64(tcg_src_hi
, tcg_src
, 63);
7731 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
7732 tcg_src
, tcg_src_hi
,
7735 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
7739 tcg_temp_free_i64(tcg_zero
);
7741 tcg_gen_add_i64(tcg_src
, tcg_src
, tcg_rnd
);
7745 /* Now do the shift right */
7746 if (round
&& extended_result
) {
7747 /* extended case, >64 bit precision required */
7748 if (ext_lshift
== 0) {
7749 /* special case, only high bits matter */
7750 tcg_gen_mov_i64(tcg_src
, tcg_src_hi
);
7752 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
7753 tcg_gen_shli_i64(tcg_src_hi
, tcg_src_hi
, ext_lshift
);
7754 tcg_gen_or_i64(tcg_src
, tcg_src
, tcg_src_hi
);
7759 /* essentially shifting in 64 zeros */
7760 tcg_gen_movi_i64(tcg_src
, 0);
7762 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
7766 /* effectively extending the sign-bit */
7767 tcg_gen_sari_i64(tcg_src
, tcg_src
, 63);
7769 tcg_gen_sari_i64(tcg_src
, tcg_src
, shift
);
7775 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_src
);
7777 tcg_gen_mov_i64(tcg_res
, tcg_src
);
7780 if (extended_result
) {
7781 tcg_temp_free_i64(tcg_src_hi
);
7785 /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */
7786 static void handle_scalar_simd_shri(DisasContext
*s
,
7787 bool is_u
, int immh
, int immb
,
7788 int opcode
, int rn
, int rd
)
7791 int immhb
= immh
<< 3 | immb
;
7792 int shift
= 2 * (8 << size
) - immhb
;
7793 bool accumulate
= false;
7795 bool insert
= false;
7800 if (!extract32(immh
, 3, 1)) {
7801 unallocated_encoding(s
);
7805 if (!fp_access_check(s
)) {
7810 case 0x02: /* SSRA / USRA (accumulate) */
7813 case 0x04: /* SRSHR / URSHR (rounding) */
7816 case 0x06: /* SRSRA / URSRA (accum + rounding) */
7817 accumulate
= round
= true;
7819 case 0x08: /* SRI */
7825 uint64_t round_const
= 1ULL << (shift
- 1);
7826 tcg_round
= tcg_const_i64(round_const
);
7831 tcg_rn
= read_fp_dreg(s
, rn
);
7832 tcg_rd
= (accumulate
|| insert
) ? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
7835 /* shift count same as element size is valid but does nothing;
7836 * special case to avoid potential shift by 64.
7838 int esize
= 8 << size
;
7839 if (shift
!= esize
) {
7840 tcg_gen_shri_i64(tcg_rn
, tcg_rn
, shift
);
7841 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, 0, esize
- shift
);
7844 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
7845 accumulate
, is_u
, size
, shift
);
7848 write_fp_dreg(s
, rd
, tcg_rd
);
7850 tcg_temp_free_i64(tcg_rn
);
7851 tcg_temp_free_i64(tcg_rd
);
7853 tcg_temp_free_i64(tcg_round
);
7857 /* SHL/SLI - Scalar shift left */
7858 static void handle_scalar_simd_shli(DisasContext
*s
, bool insert
,
7859 int immh
, int immb
, int opcode
,
7862 int size
= 32 - clz32(immh
) - 1;
7863 int immhb
= immh
<< 3 | immb
;
7864 int shift
= immhb
- (8 << size
);
7865 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
7866 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
7868 if (!extract32(immh
, 3, 1)) {
7869 unallocated_encoding(s
);
7873 if (!fp_access_check(s
)) {
7877 tcg_rn
= read_fp_dreg(s
, rn
);
7878 tcg_rd
= insert
? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
7881 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, shift
, 64 - shift
);
7883 tcg_gen_shli_i64(tcg_rd
, tcg_rn
, shift
);
7886 write_fp_dreg(s
, rd
, tcg_rd
);
7888 tcg_temp_free_i64(tcg_rn
);
7889 tcg_temp_free_i64(tcg_rd
);
7892 /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with
7893 * (signed/unsigned) narrowing */
7894 static void handle_vec_simd_sqshrn(DisasContext
*s
, bool is_scalar
, bool is_q
,
7895 bool is_u_shift
, bool is_u_narrow
,
7896 int immh
, int immb
, int opcode
,
7899 int immhb
= immh
<< 3 | immb
;
7900 int size
= 32 - clz32(immh
) - 1;
7901 int esize
= 8 << size
;
7902 int shift
= (2 * esize
) - immhb
;
7903 int elements
= is_scalar
? 1 : (64 / esize
);
7904 bool round
= extract32(opcode
, 0, 1);
7905 TCGMemOp ldop
= (size
+ 1) | (is_u_shift
? 0 : MO_SIGN
);
7906 TCGv_i64 tcg_rn
, tcg_rd
, tcg_round
;
7907 TCGv_i32 tcg_rd_narrowed
;
7910 static NeonGenNarrowEnvFn
* const signed_narrow_fns
[4][2] = {
7911 { gen_helper_neon_narrow_sat_s8
,
7912 gen_helper_neon_unarrow_sat8
},
7913 { gen_helper_neon_narrow_sat_s16
,
7914 gen_helper_neon_unarrow_sat16
},
7915 { gen_helper_neon_narrow_sat_s32
,
7916 gen_helper_neon_unarrow_sat32
},
7919 static NeonGenNarrowEnvFn
* const unsigned_narrow_fns
[4] = {
7920 gen_helper_neon_narrow_sat_u8
,
7921 gen_helper_neon_narrow_sat_u16
,
7922 gen_helper_neon_narrow_sat_u32
,
7925 NeonGenNarrowEnvFn
*narrowfn
;
7931 if (extract32(immh
, 3, 1)) {
7932 unallocated_encoding(s
);
7936 if (!fp_access_check(s
)) {
7941 narrowfn
= unsigned_narrow_fns
[size
];
7943 narrowfn
= signed_narrow_fns
[size
][is_u_narrow
? 1 : 0];
7946 tcg_rn
= tcg_temp_new_i64();
7947 tcg_rd
= tcg_temp_new_i64();
7948 tcg_rd_narrowed
= tcg_temp_new_i32();
7949 tcg_final
= tcg_const_i64(0);
7952 uint64_t round_const
= 1ULL << (shift
- 1);
7953 tcg_round
= tcg_const_i64(round_const
);
7958 for (i
= 0; i
< elements
; i
++) {
7959 read_vec_element(s
, tcg_rn
, rn
, i
, ldop
);
7960 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
7961 false, is_u_shift
, size
+1, shift
);
7962 narrowfn(tcg_rd_narrowed
, cpu_env
, tcg_rd
);
7963 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd_narrowed
);
7964 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
7968 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
7970 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
7974 tcg_temp_free_i64(tcg_round
);
7976 tcg_temp_free_i64(tcg_rn
);
7977 tcg_temp_free_i64(tcg_rd
);
7978 tcg_temp_free_i32(tcg_rd_narrowed
);
7979 tcg_temp_free_i64(tcg_final
);
7981 clear_vec_high(s
, is_q
, rd
);
7984 /* SQSHLU, UQSHL, SQSHL: saturating left shifts */
7985 static void handle_simd_qshl(DisasContext
*s
, bool scalar
, bool is_q
,
7986 bool src_unsigned
, bool dst_unsigned
,
7987 int immh
, int immb
, int rn
, int rd
)
7989 int immhb
= immh
<< 3 | immb
;
7990 int size
= 32 - clz32(immh
) - 1;
7991 int shift
= immhb
- (8 << size
);
7995 assert(!(scalar
&& is_q
));
7998 if (!is_q
&& extract32(immh
, 3, 1)) {
7999 unallocated_encoding(s
);
8003 /* Since we use the variable-shift helpers we must
8004 * replicate the shift count into each element of
8005 * the tcg_shift value.
8009 shift
|= shift
<< 8;
8012 shift
|= shift
<< 16;
8018 g_assert_not_reached();
8022 if (!fp_access_check(s
)) {
8027 TCGv_i64 tcg_shift
= tcg_const_i64(shift
);
8028 static NeonGenTwo64OpEnvFn
* const fns
[2][2] = {
8029 { gen_helper_neon_qshl_s64
, gen_helper_neon_qshlu_s64
},
8030 { NULL
, gen_helper_neon_qshl_u64
},
8032 NeonGenTwo64OpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
];
8033 int maxpass
= is_q
? 2 : 1;
8035 for (pass
= 0; pass
< maxpass
; pass
++) {
8036 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8038 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
8039 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
8040 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
8042 tcg_temp_free_i64(tcg_op
);
8044 tcg_temp_free_i64(tcg_shift
);
8045 clear_vec_high(s
, is_q
, rd
);
8047 TCGv_i32 tcg_shift
= tcg_const_i32(shift
);
8048 static NeonGenTwoOpEnvFn
* const fns
[2][2][3] = {
8050 { gen_helper_neon_qshl_s8
,
8051 gen_helper_neon_qshl_s16
,
8052 gen_helper_neon_qshl_s32
},
8053 { gen_helper_neon_qshlu_s8
,
8054 gen_helper_neon_qshlu_s16
,
8055 gen_helper_neon_qshlu_s32
}
8057 { NULL
, NULL
, NULL
},
8058 { gen_helper_neon_qshl_u8
,
8059 gen_helper_neon_qshl_u16
,
8060 gen_helper_neon_qshl_u32
}
8063 NeonGenTwoOpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
][size
];
8064 TCGMemOp memop
= scalar
? size
: MO_32
;
8065 int maxpass
= scalar
? 1 : is_q
? 4 : 2;
8067 for (pass
= 0; pass
< maxpass
; pass
++) {
8068 TCGv_i32 tcg_op
= tcg_temp_new_i32();
8070 read_vec_element_i32(s
, tcg_op
, rn
, pass
, memop
);
8071 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
8075 tcg_gen_ext8u_i32(tcg_op
, tcg_op
);
8078 tcg_gen_ext16u_i32(tcg_op
, tcg_op
);
8083 g_assert_not_reached();
8085 write_fp_sreg(s
, rd
, tcg_op
);
8087 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
8090 tcg_temp_free_i32(tcg_op
);
8092 tcg_temp_free_i32(tcg_shift
);
8095 clear_vec_high(s
, is_q
, rd
);
8100 /* Common vector code for handling integer to FP conversion */
8101 static void handle_simd_intfp_conv(DisasContext
*s
, int rd
, int rn
,
8102 int elements
, int is_signed
,
8103 int fracbits
, int size
)
8105 TCGv_ptr tcg_fpst
= get_fpstatus_ptr(size
== MO_16
);
8106 TCGv_i32 tcg_shift
= NULL
;
8108 TCGMemOp mop
= size
| (is_signed
? MO_SIGN
: 0);
8111 if (fracbits
|| size
== MO_64
) {
8112 tcg_shift
= tcg_const_i32(fracbits
);
8115 if (size
== MO_64
) {
8116 TCGv_i64 tcg_int64
= tcg_temp_new_i64();
8117 TCGv_i64 tcg_double
= tcg_temp_new_i64();
8119 for (pass
= 0; pass
< elements
; pass
++) {
8120 read_vec_element(s
, tcg_int64
, rn
, pass
, mop
);
8123 gen_helper_vfp_sqtod(tcg_double
, tcg_int64
,
8124 tcg_shift
, tcg_fpst
);
8126 gen_helper_vfp_uqtod(tcg_double
, tcg_int64
,
8127 tcg_shift
, tcg_fpst
);
8129 if (elements
== 1) {
8130 write_fp_dreg(s
, rd
, tcg_double
);
8132 write_vec_element(s
, tcg_double
, rd
, pass
, MO_64
);
8136 tcg_temp_free_i64(tcg_int64
);
8137 tcg_temp_free_i64(tcg_double
);
8140 TCGv_i32 tcg_int32
= tcg_temp_new_i32();
8141 TCGv_i32 tcg_float
= tcg_temp_new_i32();
8143 for (pass
= 0; pass
< elements
; pass
++) {
8144 read_vec_element_i32(s
, tcg_int32
, rn
, pass
, mop
);
8150 gen_helper_vfp_sltos(tcg_float
, tcg_int32
,
8151 tcg_shift
, tcg_fpst
);
8153 gen_helper_vfp_ultos(tcg_float
, tcg_int32
,
8154 tcg_shift
, tcg_fpst
);
8158 gen_helper_vfp_sitos(tcg_float
, tcg_int32
, tcg_fpst
);
8160 gen_helper_vfp_uitos(tcg_float
, tcg_int32
, tcg_fpst
);
8167 gen_helper_vfp_sltoh(tcg_float
, tcg_int32
,
8168 tcg_shift
, tcg_fpst
);
8170 gen_helper_vfp_ultoh(tcg_float
, tcg_int32
,
8171 tcg_shift
, tcg_fpst
);
8175 gen_helper_vfp_sitoh(tcg_float
, tcg_int32
, tcg_fpst
);
8177 gen_helper_vfp_uitoh(tcg_float
, tcg_int32
, tcg_fpst
);
8182 g_assert_not_reached();
8185 if (elements
== 1) {
8186 write_fp_sreg(s
, rd
, tcg_float
);
8188 write_vec_element_i32(s
, tcg_float
, rd
, pass
, size
);
8192 tcg_temp_free_i32(tcg_int32
);
8193 tcg_temp_free_i32(tcg_float
);
8196 tcg_temp_free_ptr(tcg_fpst
);
8198 tcg_temp_free_i32(tcg_shift
);
8201 clear_vec_high(s
, elements
<< size
== 16, rd
);
8204 /* UCVTF/SCVTF - Integer to FP conversion */
8205 static void handle_simd_shift_intfp_conv(DisasContext
*s
, bool is_scalar
,
8206 bool is_q
, bool is_u
,
8207 int immh
, int immb
, int opcode
,
8210 int size
, elements
, fracbits
;
8211 int immhb
= immh
<< 3 | immb
;
8215 if (!is_scalar
&& !is_q
) {
8216 unallocated_encoding(s
);
8219 } else if (immh
& 4) {
8221 } else if (immh
& 2) {
8223 if (!dc_isar_feature(aa64_fp16
, s
)) {
8224 unallocated_encoding(s
);
8228 /* immh == 0 would be a failure of the decode logic */
8229 g_assert(immh
== 1);
8230 unallocated_encoding(s
);
8237 elements
= (8 << is_q
) >> size
;
8239 fracbits
= (16 << size
) - immhb
;
8241 if (!fp_access_check(s
)) {
8245 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !is_u
, fracbits
, size
);
8248 /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */
8249 static void handle_simd_shift_fpint_conv(DisasContext
*s
, bool is_scalar
,
8250 bool is_q
, bool is_u
,
8251 int immh
, int immb
, int rn
, int rd
)
8253 int immhb
= immh
<< 3 | immb
;
8254 int pass
, size
, fracbits
;
8255 TCGv_ptr tcg_fpstatus
;
8256 TCGv_i32 tcg_rmode
, tcg_shift
;
8260 if (!is_scalar
&& !is_q
) {
8261 unallocated_encoding(s
);
8264 } else if (immh
& 0x4) {
8266 } else if (immh
& 0x2) {
8268 if (!dc_isar_feature(aa64_fp16
, s
)) {
8269 unallocated_encoding(s
);
8273 /* Should have split out AdvSIMD modified immediate earlier. */
8275 unallocated_encoding(s
);
8279 if (!fp_access_check(s
)) {
8283 assert(!(is_scalar
&& is_q
));
8285 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO
));
8286 tcg_fpstatus
= get_fpstatus_ptr(size
== MO_16
);
8287 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
8288 fracbits
= (16 << size
) - immhb
;
8289 tcg_shift
= tcg_const_i32(fracbits
);
8291 if (size
== MO_64
) {
8292 int maxpass
= is_scalar
? 1 : 2;
8294 for (pass
= 0; pass
< maxpass
; pass
++) {
8295 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8297 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
8299 gen_helper_vfp_touqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
8301 gen_helper_vfp_tosqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
8303 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
8304 tcg_temp_free_i64(tcg_op
);
8306 clear_vec_high(s
, is_q
, rd
);
8308 void (*fn
)(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
8309 int maxpass
= is_scalar
? 1 : ((8 << is_q
) >> size
);
8314 fn
= gen_helper_vfp_touhh
;
8316 fn
= gen_helper_vfp_toshh
;
8321 fn
= gen_helper_vfp_touls
;
8323 fn
= gen_helper_vfp_tosls
;
8327 g_assert_not_reached();
8330 for (pass
= 0; pass
< maxpass
; pass
++) {
8331 TCGv_i32 tcg_op
= tcg_temp_new_i32();
8333 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
8334 fn(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
8336 write_fp_sreg(s
, rd
, tcg_op
);
8338 write_vec_element_i32(s
, tcg_op
, rd
, pass
, size
);
8340 tcg_temp_free_i32(tcg_op
);
8343 clear_vec_high(s
, is_q
, rd
);
8347 tcg_temp_free_ptr(tcg_fpstatus
);
8348 tcg_temp_free_i32(tcg_shift
);
8349 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
8350 tcg_temp_free_i32(tcg_rmode
);
8353 /* AdvSIMD scalar shift by immediate
8354 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
8355 * +-----+---+-------------+------+------+--------+---+------+------+
8356 * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
8357 * +-----+---+-------------+------+------+--------+---+------+------+
8359 * This is the scalar version so it works on a fixed sized registers
8361 static void disas_simd_scalar_shift_imm(DisasContext
*s
, uint32_t insn
)
8363 int rd
= extract32(insn
, 0, 5);
8364 int rn
= extract32(insn
, 5, 5);
8365 int opcode
= extract32(insn
, 11, 5);
8366 int immb
= extract32(insn
, 16, 3);
8367 int immh
= extract32(insn
, 19, 4);
8368 bool is_u
= extract32(insn
, 29, 1);
8371 unallocated_encoding(s
);
8376 case 0x08: /* SRI */
8378 unallocated_encoding(s
);
8382 case 0x00: /* SSHR / USHR */
8383 case 0x02: /* SSRA / USRA */
8384 case 0x04: /* SRSHR / URSHR */
8385 case 0x06: /* SRSRA / URSRA */
8386 handle_scalar_simd_shri(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8388 case 0x0a: /* SHL / SLI */
8389 handle_scalar_simd_shli(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8391 case 0x1c: /* SCVTF, UCVTF */
8392 handle_simd_shift_intfp_conv(s
, true, false, is_u
, immh
, immb
,
8395 case 0x10: /* SQSHRUN, SQSHRUN2 */
8396 case 0x11: /* SQRSHRUN, SQRSHRUN2 */
8398 unallocated_encoding(s
);
8401 handle_vec_simd_sqshrn(s
, true, false, false, true,
8402 immh
, immb
, opcode
, rn
, rd
);
8404 case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */
8405 case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */
8406 handle_vec_simd_sqshrn(s
, true, false, is_u
, is_u
,
8407 immh
, immb
, opcode
, rn
, rd
);
8409 case 0xc: /* SQSHLU */
8411 unallocated_encoding(s
);
8414 handle_simd_qshl(s
, true, false, false, true, immh
, immb
, rn
, rd
);
8416 case 0xe: /* SQSHL, UQSHL */
8417 handle_simd_qshl(s
, true, false, is_u
, is_u
, immh
, immb
, rn
, rd
);
8419 case 0x1f: /* FCVTZS, FCVTZU */
8420 handle_simd_shift_fpint_conv(s
, true, false, is_u
, immh
, immb
, rn
, rd
);
8423 unallocated_encoding(s
);
8428 /* AdvSIMD scalar three different
8429 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
8430 * +-----+---+-----------+------+---+------+--------+-----+------+------+
8431 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
8432 * +-----+---+-----------+------+---+------+--------+-----+------+------+
8434 static void disas_simd_scalar_three_reg_diff(DisasContext
*s
, uint32_t insn
)
8436 bool is_u
= extract32(insn
, 29, 1);
8437 int size
= extract32(insn
, 22, 2);
8438 int opcode
= extract32(insn
, 12, 4);
8439 int rm
= extract32(insn
, 16, 5);
8440 int rn
= extract32(insn
, 5, 5);
8441 int rd
= extract32(insn
, 0, 5);
8444 unallocated_encoding(s
);
8449 case 0x9: /* SQDMLAL, SQDMLAL2 */
8450 case 0xb: /* SQDMLSL, SQDMLSL2 */
8451 case 0xd: /* SQDMULL, SQDMULL2 */
8452 if (size
== 0 || size
== 3) {
8453 unallocated_encoding(s
);
8458 unallocated_encoding(s
);
8462 if (!fp_access_check(s
)) {
8467 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8468 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8469 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8471 read_vec_element(s
, tcg_op1
, rn
, 0, MO_32
| MO_SIGN
);
8472 read_vec_element(s
, tcg_op2
, rm
, 0, MO_32
| MO_SIGN
);
8474 tcg_gen_mul_i64(tcg_res
, tcg_op1
, tcg_op2
);
8475 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
8478 case 0xd: /* SQDMULL, SQDMULL2 */
8480 case 0xb: /* SQDMLSL, SQDMLSL2 */
8481 tcg_gen_neg_i64(tcg_res
, tcg_res
);
8483 case 0x9: /* SQDMLAL, SQDMLAL2 */
8484 read_vec_element(s
, tcg_op1
, rd
, 0, MO_64
);
8485 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
,
8489 g_assert_not_reached();
8492 write_fp_dreg(s
, rd
, tcg_res
);
8494 tcg_temp_free_i64(tcg_op1
);
8495 tcg_temp_free_i64(tcg_op2
);
8496 tcg_temp_free_i64(tcg_res
);
8498 TCGv_i32 tcg_op1
= read_fp_hreg(s
, rn
);
8499 TCGv_i32 tcg_op2
= read_fp_hreg(s
, rm
);
8500 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8502 gen_helper_neon_mull_s16(tcg_res
, tcg_op1
, tcg_op2
);
8503 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
8506 case 0xd: /* SQDMULL, SQDMULL2 */
8508 case 0xb: /* SQDMLSL, SQDMLSL2 */
8509 gen_helper_neon_negl_u32(tcg_res
, tcg_res
);
8511 case 0x9: /* SQDMLAL, SQDMLAL2 */
8513 TCGv_i64 tcg_op3
= tcg_temp_new_i64();
8514 read_vec_element(s
, tcg_op3
, rd
, 0, MO_32
);
8515 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
,
8517 tcg_temp_free_i64(tcg_op3
);
8521 g_assert_not_reached();
8524 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
8525 write_fp_dreg(s
, rd
, tcg_res
);
8527 tcg_temp_free_i32(tcg_op1
);
8528 tcg_temp_free_i32(tcg_op2
);
8529 tcg_temp_free_i64(tcg_res
);
8533 static void handle_3same_64(DisasContext
*s
, int opcode
, bool u
,
8534 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
, TCGv_i64 tcg_rm
)
8536 /* Handle 64x64->64 opcodes which are shared between the scalar
8537 * and vector 3-same groups. We cover every opcode where size == 3
8538 * is valid in either the three-reg-same (integer, not pairwise)
8539 * or scalar-three-reg-same groups.
8544 case 0x1: /* SQADD */
8546 gen_helper_neon_qadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8548 gen_helper_neon_qadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8551 case 0x5: /* SQSUB */
8553 gen_helper_neon_qsub_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8555 gen_helper_neon_qsub_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8558 case 0x6: /* CMGT, CMHI */
8559 /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0.
8560 * We implement this using setcond (test) and then negating.
8562 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
8564 tcg_gen_setcond_i64(cond
, tcg_rd
, tcg_rn
, tcg_rm
);
8565 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
8567 case 0x7: /* CMGE, CMHS */
8568 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
8570 case 0x11: /* CMTST, CMEQ */
8575 gen_cmtst_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8577 case 0x8: /* SSHL, USHL */
8579 gen_helper_neon_shl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
8581 gen_helper_neon_shl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
8584 case 0x9: /* SQSHL, UQSHL */
8586 gen_helper_neon_qshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8588 gen_helper_neon_qshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8591 case 0xa: /* SRSHL, URSHL */
8593 gen_helper_neon_rshl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
8595 gen_helper_neon_rshl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
8598 case 0xb: /* SQRSHL, UQRSHL */
8600 gen_helper_neon_qrshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8602 gen_helper_neon_qrshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8605 case 0x10: /* ADD, SUB */
8607 tcg_gen_sub_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8609 tcg_gen_add_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8613 g_assert_not_reached();
8617 /* Handle the 3-same-operands float operations; shared by the scalar
8618 * and vector encodings. The caller must filter out any encodings
8619 * not allocated for the encoding it is dealing with.
8621 static void handle_3same_float(DisasContext
*s
, int size
, int elements
,
8622 int fpopcode
, int rd
, int rn
, int rm
)
8625 TCGv_ptr fpst
= get_fpstatus_ptr(false);
8627 for (pass
= 0; pass
< elements
; pass
++) {
8630 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8631 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8632 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8634 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8635 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
8638 case 0x39: /* FMLS */
8639 /* As usual for ARM, separate negation for fused multiply-add */
8640 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
8642 case 0x19: /* FMLA */
8643 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
8644 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
,
8647 case 0x18: /* FMAXNM */
8648 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8650 case 0x1a: /* FADD */
8651 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8653 case 0x1b: /* FMULX */
8654 gen_helper_vfp_mulxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8656 case 0x1c: /* FCMEQ */
8657 gen_helper_neon_ceq_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8659 case 0x1e: /* FMAX */
8660 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8662 case 0x1f: /* FRECPS */
8663 gen_helper_recpsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8665 case 0x38: /* FMINNM */
8666 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8668 case 0x3a: /* FSUB */
8669 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8671 case 0x3e: /* FMIN */
8672 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8674 case 0x3f: /* FRSQRTS */
8675 gen_helper_rsqrtsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8677 case 0x5b: /* FMUL */
8678 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8680 case 0x5c: /* FCMGE */
8681 gen_helper_neon_cge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8683 case 0x5d: /* FACGE */
8684 gen_helper_neon_acge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8686 case 0x5f: /* FDIV */
8687 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8689 case 0x7a: /* FABD */
8690 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8691 gen_helper_vfp_absd(tcg_res
, tcg_res
);
8693 case 0x7c: /* FCMGT */
8694 gen_helper_neon_cgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8696 case 0x7d: /* FACGT */
8697 gen_helper_neon_acgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8700 g_assert_not_reached();
8703 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
8705 tcg_temp_free_i64(tcg_res
);
8706 tcg_temp_free_i64(tcg_op1
);
8707 tcg_temp_free_i64(tcg_op2
);
8710 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
8711 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8712 TCGv_i32 tcg_res
= tcg_temp_new_i32();
8714 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
8715 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
8718 case 0x39: /* FMLS */
8719 /* As usual for ARM, separate negation for fused multiply-add */
8720 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
8722 case 0x19: /* FMLA */
8723 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
8724 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
,
8727 case 0x1a: /* FADD */
8728 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8730 case 0x1b: /* FMULX */
8731 gen_helper_vfp_mulxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8733 case 0x1c: /* FCMEQ */
8734 gen_helper_neon_ceq_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8736 case 0x1e: /* FMAX */
8737 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8739 case 0x1f: /* FRECPS */
8740 gen_helper_recpsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8742 case 0x18: /* FMAXNM */
8743 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8745 case 0x38: /* FMINNM */
8746 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8748 case 0x3a: /* FSUB */
8749 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8751 case 0x3e: /* FMIN */
8752 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8754 case 0x3f: /* FRSQRTS */
8755 gen_helper_rsqrtsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8757 case 0x5b: /* FMUL */
8758 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8760 case 0x5c: /* FCMGE */
8761 gen_helper_neon_cge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8763 case 0x5d: /* FACGE */
8764 gen_helper_neon_acge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8766 case 0x5f: /* FDIV */
8767 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8769 case 0x7a: /* FABD */
8770 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8771 gen_helper_vfp_abss(tcg_res
, tcg_res
);
8773 case 0x7c: /* FCMGT */
8774 gen_helper_neon_cgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8776 case 0x7d: /* FACGT */
8777 gen_helper_neon_acgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8780 g_assert_not_reached();
8783 if (elements
== 1) {
8784 /* scalar single so clear high part */
8785 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
8787 tcg_gen_extu_i32_i64(tcg_tmp
, tcg_res
);
8788 write_vec_element(s
, tcg_tmp
, rd
, pass
, MO_64
);
8789 tcg_temp_free_i64(tcg_tmp
);
8791 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
8794 tcg_temp_free_i32(tcg_res
);
8795 tcg_temp_free_i32(tcg_op1
);
8796 tcg_temp_free_i32(tcg_op2
);
8800 tcg_temp_free_ptr(fpst
);
8802 clear_vec_high(s
, elements
* (size
? 8 : 4) > 8, rd
);
8805 /* AdvSIMD scalar three same
8806 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
8807 * +-----+---+-----------+------+---+------+--------+---+------+------+
8808 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
8809 * +-----+---+-----------+------+---+------+--------+---+------+------+
8811 static void disas_simd_scalar_three_reg_same(DisasContext
*s
, uint32_t insn
)
8813 int rd
= extract32(insn
, 0, 5);
8814 int rn
= extract32(insn
, 5, 5);
8815 int opcode
= extract32(insn
, 11, 5);
8816 int rm
= extract32(insn
, 16, 5);
8817 int size
= extract32(insn
, 22, 2);
8818 bool u
= extract32(insn
, 29, 1);
8821 if (opcode
>= 0x18) {
8822 /* Floating point: U, size[1] and opcode indicate operation */
8823 int fpopcode
= opcode
| (extract32(size
, 1, 1) << 5) | (u
<< 6);
8825 case 0x1b: /* FMULX */
8826 case 0x1f: /* FRECPS */
8827 case 0x3f: /* FRSQRTS */
8828 case 0x5d: /* FACGE */
8829 case 0x7d: /* FACGT */
8830 case 0x1c: /* FCMEQ */
8831 case 0x5c: /* FCMGE */
8832 case 0x7c: /* FCMGT */
8833 case 0x7a: /* FABD */
8836 unallocated_encoding(s
);
8840 if (!fp_access_check(s
)) {
8844 handle_3same_float(s
, extract32(size
, 0, 1), 1, fpopcode
, rd
, rn
, rm
);
8849 case 0x1: /* SQADD, UQADD */
8850 case 0x5: /* SQSUB, UQSUB */
8851 case 0x9: /* SQSHL, UQSHL */
8852 case 0xb: /* SQRSHL, UQRSHL */
8854 case 0x8: /* SSHL, USHL */
8855 case 0xa: /* SRSHL, URSHL */
8856 case 0x6: /* CMGT, CMHI */
8857 case 0x7: /* CMGE, CMHS */
8858 case 0x11: /* CMTST, CMEQ */
8859 case 0x10: /* ADD, SUB (vector) */
8861 unallocated_encoding(s
);
8865 case 0x16: /* SQDMULH, SQRDMULH (vector) */
8866 if (size
!= 1 && size
!= 2) {
8867 unallocated_encoding(s
);
8872 unallocated_encoding(s
);
8876 if (!fp_access_check(s
)) {
8880 tcg_rd
= tcg_temp_new_i64();
8883 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
8884 TCGv_i64 tcg_rm
= read_fp_dreg(s
, rm
);
8886 handle_3same_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rm
);
8887 tcg_temp_free_i64(tcg_rn
);
8888 tcg_temp_free_i64(tcg_rm
);
8890 /* Do a single operation on the lowest element in the vector.
8891 * We use the standard Neon helpers and rely on 0 OP 0 == 0 with
8892 * no side effects for all these operations.
8893 * OPTME: special-purpose helpers would avoid doing some
8894 * unnecessary work in the helper for the 8 and 16 bit cases.
8896 NeonGenTwoOpEnvFn
*genenvfn
;
8897 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
8898 TCGv_i32 tcg_rm
= tcg_temp_new_i32();
8899 TCGv_i32 tcg_rd32
= tcg_temp_new_i32();
8901 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
8902 read_vec_element_i32(s
, tcg_rm
, rm
, 0, size
);
8905 case 0x1: /* SQADD, UQADD */
8907 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
8908 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
8909 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
8910 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
8912 genenvfn
= fns
[size
][u
];
8915 case 0x5: /* SQSUB, UQSUB */
8917 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
8918 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
8919 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
8920 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
8922 genenvfn
= fns
[size
][u
];
8925 case 0x9: /* SQSHL, UQSHL */
8927 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
8928 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
8929 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
8930 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
8932 genenvfn
= fns
[size
][u
];
8935 case 0xb: /* SQRSHL, UQRSHL */
8937 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
8938 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
8939 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
8940 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
8942 genenvfn
= fns
[size
][u
];
8945 case 0x16: /* SQDMULH, SQRDMULH */
8947 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
8948 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
8949 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
8951 assert(size
== 1 || size
== 2);
8952 genenvfn
= fns
[size
- 1][u
];
8956 g_assert_not_reached();
8959 genenvfn(tcg_rd32
, cpu_env
, tcg_rn
, tcg_rm
);
8960 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd32
);
8961 tcg_temp_free_i32(tcg_rd32
);
8962 tcg_temp_free_i32(tcg_rn
);
8963 tcg_temp_free_i32(tcg_rm
);
8966 write_fp_dreg(s
, rd
, tcg_rd
);
8968 tcg_temp_free_i64(tcg_rd
);
8971 /* AdvSIMD scalar three same FP16
8972 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
8973 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
8974 * | 0 1 | U | 1 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
8975 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
8976 * v: 0101 1110 0100 0000 0000 0100 0000 0000 => 5e400400
8977 * m: 1101 1111 0110 0000 1100 0100 0000 0000 => df60c400
8979 static void disas_simd_scalar_three_reg_same_fp16(DisasContext
*s
,
8982 int rd
= extract32(insn
, 0, 5);
8983 int rn
= extract32(insn
, 5, 5);
8984 int opcode
= extract32(insn
, 11, 3);
8985 int rm
= extract32(insn
, 16, 5);
8986 bool u
= extract32(insn
, 29, 1);
8987 bool a
= extract32(insn
, 23, 1);
8988 int fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
8995 case 0x03: /* FMULX */
8996 case 0x04: /* FCMEQ (reg) */
8997 case 0x07: /* FRECPS */
8998 case 0x0f: /* FRSQRTS */
8999 case 0x14: /* FCMGE (reg) */
9000 case 0x15: /* FACGE */
9001 case 0x1a: /* FABD */
9002 case 0x1c: /* FCMGT (reg) */
9003 case 0x1d: /* FACGT */
9006 unallocated_encoding(s
);
9010 if (!dc_isar_feature(aa64_fp16
, s
)) {
9011 unallocated_encoding(s
);
9014 if (!fp_access_check(s
)) {
9018 fpst
= get_fpstatus_ptr(true);
9020 tcg_op1
= read_fp_hreg(s
, rn
);
9021 tcg_op2
= read_fp_hreg(s
, rm
);
9022 tcg_res
= tcg_temp_new_i32();
9025 case 0x03: /* FMULX */
9026 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9028 case 0x04: /* FCMEQ (reg) */
9029 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9031 case 0x07: /* FRECPS */
9032 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9034 case 0x0f: /* FRSQRTS */
9035 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9037 case 0x14: /* FCMGE (reg) */
9038 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9040 case 0x15: /* FACGE */
9041 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9043 case 0x1a: /* FABD */
9044 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9045 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
9047 case 0x1c: /* FCMGT (reg) */
9048 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9050 case 0x1d: /* FACGT */
9051 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9054 g_assert_not_reached();
9057 write_fp_sreg(s
, rd
, tcg_res
);
9060 tcg_temp_free_i32(tcg_res
);
9061 tcg_temp_free_i32(tcg_op1
);
9062 tcg_temp_free_i32(tcg_op2
);
9063 tcg_temp_free_ptr(fpst
);
9066 /* AdvSIMD scalar three same extra
9067 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
9068 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
9069 * | 0 1 | U | 1 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
9070 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
9072 static void disas_simd_scalar_three_reg_same_extra(DisasContext
*s
,
9075 int rd
= extract32(insn
, 0, 5);
9076 int rn
= extract32(insn
, 5, 5);
9077 int opcode
= extract32(insn
, 11, 4);
9078 int rm
= extract32(insn
, 16, 5);
9079 int size
= extract32(insn
, 22, 2);
9080 bool u
= extract32(insn
, 29, 1);
9081 TCGv_i32 ele1
, ele2
, ele3
;
9085 switch (u
* 16 + opcode
) {
9086 case 0x10: /* SQRDMLAH (vector) */
9087 case 0x11: /* SQRDMLSH (vector) */
9088 if (size
!= 1 && size
!= 2) {
9089 unallocated_encoding(s
);
9092 feature
= dc_isar_feature(aa64_rdm
, s
);
9095 unallocated_encoding(s
);
9099 unallocated_encoding(s
);
9102 if (!fp_access_check(s
)) {
9106 /* Do a single operation on the lowest element in the vector.
9107 * We use the standard Neon helpers and rely on 0 OP 0 == 0
9108 * with no side effects for all these operations.
9109 * OPTME: special-purpose helpers would avoid doing some
9110 * unnecessary work in the helper for the 16 bit cases.
9112 ele1
= tcg_temp_new_i32();
9113 ele2
= tcg_temp_new_i32();
9114 ele3
= tcg_temp_new_i32();
9116 read_vec_element_i32(s
, ele1
, rn
, 0, size
);
9117 read_vec_element_i32(s
, ele2
, rm
, 0, size
);
9118 read_vec_element_i32(s
, ele3
, rd
, 0, size
);
9121 case 0x0: /* SQRDMLAH */
9123 gen_helper_neon_qrdmlah_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9125 gen_helper_neon_qrdmlah_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9128 case 0x1: /* SQRDMLSH */
9130 gen_helper_neon_qrdmlsh_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9132 gen_helper_neon_qrdmlsh_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9136 g_assert_not_reached();
9138 tcg_temp_free_i32(ele1
);
9139 tcg_temp_free_i32(ele2
);
9141 res
= tcg_temp_new_i64();
9142 tcg_gen_extu_i32_i64(res
, ele3
);
9143 tcg_temp_free_i32(ele3
);
9145 write_fp_dreg(s
, rd
, res
);
9146 tcg_temp_free_i64(res
);
9149 static void handle_2misc_64(DisasContext
*s
, int opcode
, bool u
,
9150 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
,
9151 TCGv_i32 tcg_rmode
, TCGv_ptr tcg_fpstatus
)
9153 /* Handle 64->64 opcodes which are shared between the scalar and
9154 * vector 2-reg-misc groups. We cover every integer opcode where size == 3
9155 * is valid in either group and also the double-precision fp ops.
9156 * The caller only need provide tcg_rmode and tcg_fpstatus if the op
9162 case 0x4: /* CLS, CLZ */
9164 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
9166 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
9170 /* This opcode is shared with CNT and RBIT but we have earlier
9171 * enforced that size == 3 if and only if this is the NOT insn.
9173 tcg_gen_not_i64(tcg_rd
, tcg_rn
);
9175 case 0x7: /* SQABS, SQNEG */
9177 gen_helper_neon_qneg_s64(tcg_rd
, cpu_env
, tcg_rn
);
9179 gen_helper_neon_qabs_s64(tcg_rd
, cpu_env
, tcg_rn
);
9182 case 0xa: /* CMLT */
9183 /* 64 bit integer comparison against zero, result is
9184 * test ? (2^64 - 1) : 0. We implement via setcond(!test) and
9189 tcg_gen_setcondi_i64(cond
, tcg_rd
, tcg_rn
, 0);
9190 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
9192 case 0x8: /* CMGT, CMGE */
9193 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
9195 case 0x9: /* CMEQ, CMLE */
9196 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
9198 case 0xb: /* ABS, NEG */
9200 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
9202 TCGv_i64 tcg_zero
= tcg_const_i64(0);
9203 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
9204 tcg_gen_movcond_i64(TCG_COND_GT
, tcg_rd
, tcg_rn
, tcg_zero
,
9206 tcg_temp_free_i64(tcg_zero
);
9209 case 0x2f: /* FABS */
9210 gen_helper_vfp_absd(tcg_rd
, tcg_rn
);
9212 case 0x6f: /* FNEG */
9213 gen_helper_vfp_negd(tcg_rd
, tcg_rn
);
9215 case 0x7f: /* FSQRT */
9216 gen_helper_vfp_sqrtd(tcg_rd
, tcg_rn
, cpu_env
);
9218 case 0x1a: /* FCVTNS */
9219 case 0x1b: /* FCVTMS */
9220 case 0x1c: /* FCVTAS */
9221 case 0x3a: /* FCVTPS */
9222 case 0x3b: /* FCVTZS */
9224 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9225 gen_helper_vfp_tosqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9226 tcg_temp_free_i32(tcg_shift
);
9229 case 0x5a: /* FCVTNU */
9230 case 0x5b: /* FCVTMU */
9231 case 0x5c: /* FCVTAU */
9232 case 0x7a: /* FCVTPU */
9233 case 0x7b: /* FCVTZU */
9235 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9236 gen_helper_vfp_touqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9237 tcg_temp_free_i32(tcg_shift
);
9240 case 0x18: /* FRINTN */
9241 case 0x19: /* FRINTM */
9242 case 0x38: /* FRINTP */
9243 case 0x39: /* FRINTZ */
9244 case 0x58: /* FRINTA */
9245 case 0x79: /* FRINTI */
9246 gen_helper_rintd(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9248 case 0x59: /* FRINTX */
9249 gen_helper_rintd_exact(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9252 g_assert_not_reached();
9256 static void handle_2misc_fcmp_zero(DisasContext
*s
, int opcode
,
9257 bool is_scalar
, bool is_u
, bool is_q
,
9258 int size
, int rn
, int rd
)
9260 bool is_double
= (size
== MO_64
);
9263 if (!fp_access_check(s
)) {
9267 fpst
= get_fpstatus_ptr(size
== MO_16
);
9270 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9271 TCGv_i64 tcg_zero
= tcg_const_i64(0);
9272 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9273 NeonGenTwoDoubleOPFn
*genfn
;
9278 case 0x2e: /* FCMLT (zero) */
9281 case 0x2c: /* FCMGT (zero) */
9282 genfn
= gen_helper_neon_cgt_f64
;
9284 case 0x2d: /* FCMEQ (zero) */
9285 genfn
= gen_helper_neon_ceq_f64
;
9287 case 0x6d: /* FCMLE (zero) */
9290 case 0x6c: /* FCMGE (zero) */
9291 genfn
= gen_helper_neon_cge_f64
;
9294 g_assert_not_reached();
9297 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9298 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9300 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
9302 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
9304 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9306 tcg_temp_free_i64(tcg_res
);
9307 tcg_temp_free_i64(tcg_zero
);
9308 tcg_temp_free_i64(tcg_op
);
9310 clear_vec_high(s
, !is_scalar
, rd
);
9312 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9313 TCGv_i32 tcg_zero
= tcg_const_i32(0);
9314 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9315 NeonGenTwoSingleOPFn
*genfn
;
9317 int pass
, maxpasses
;
9319 if (size
== MO_16
) {
9321 case 0x2e: /* FCMLT (zero) */
9324 case 0x2c: /* FCMGT (zero) */
9325 genfn
= gen_helper_advsimd_cgt_f16
;
9327 case 0x2d: /* FCMEQ (zero) */
9328 genfn
= gen_helper_advsimd_ceq_f16
;
9330 case 0x6d: /* FCMLE (zero) */
9333 case 0x6c: /* FCMGE (zero) */
9334 genfn
= gen_helper_advsimd_cge_f16
;
9337 g_assert_not_reached();
9341 case 0x2e: /* FCMLT (zero) */
9344 case 0x2c: /* FCMGT (zero) */
9345 genfn
= gen_helper_neon_cgt_f32
;
9347 case 0x2d: /* FCMEQ (zero) */
9348 genfn
= gen_helper_neon_ceq_f32
;
9350 case 0x6d: /* FCMLE (zero) */
9353 case 0x6c: /* FCMGE (zero) */
9354 genfn
= gen_helper_neon_cge_f32
;
9357 g_assert_not_reached();
9364 int vector_size
= 8 << is_q
;
9365 maxpasses
= vector_size
>> size
;
9368 for (pass
= 0; pass
< maxpasses
; pass
++) {
9369 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
9371 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
9373 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
9376 write_fp_sreg(s
, rd
, tcg_res
);
9378 write_vec_element_i32(s
, tcg_res
, rd
, pass
, size
);
9381 tcg_temp_free_i32(tcg_res
);
9382 tcg_temp_free_i32(tcg_zero
);
9383 tcg_temp_free_i32(tcg_op
);
9385 clear_vec_high(s
, is_q
, rd
);
9389 tcg_temp_free_ptr(fpst
);
9392 static void handle_2misc_reciprocal(DisasContext
*s
, int opcode
,
9393 bool is_scalar
, bool is_u
, bool is_q
,
9394 int size
, int rn
, int rd
)
9396 bool is_double
= (size
== 3);
9397 TCGv_ptr fpst
= get_fpstatus_ptr(false);
9400 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9401 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9404 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9405 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9407 case 0x3d: /* FRECPE */
9408 gen_helper_recpe_f64(tcg_res
, tcg_op
, fpst
);
9410 case 0x3f: /* FRECPX */
9411 gen_helper_frecpx_f64(tcg_res
, tcg_op
, fpst
);
9413 case 0x7d: /* FRSQRTE */
9414 gen_helper_rsqrte_f64(tcg_res
, tcg_op
, fpst
);
9417 g_assert_not_reached();
9419 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9421 tcg_temp_free_i64(tcg_res
);
9422 tcg_temp_free_i64(tcg_op
);
9423 clear_vec_high(s
, !is_scalar
, rd
);
9425 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9426 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9427 int pass
, maxpasses
;
9432 maxpasses
= is_q
? 4 : 2;
9435 for (pass
= 0; pass
< maxpasses
; pass
++) {
9436 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
9439 case 0x3c: /* URECPE */
9440 gen_helper_recpe_u32(tcg_res
, tcg_op
, fpst
);
9442 case 0x3d: /* FRECPE */
9443 gen_helper_recpe_f32(tcg_res
, tcg_op
, fpst
);
9445 case 0x3f: /* FRECPX */
9446 gen_helper_frecpx_f32(tcg_res
, tcg_op
, fpst
);
9448 case 0x7d: /* FRSQRTE */
9449 gen_helper_rsqrte_f32(tcg_res
, tcg_op
, fpst
);
9452 g_assert_not_reached();
9456 write_fp_sreg(s
, rd
, tcg_res
);
9458 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9461 tcg_temp_free_i32(tcg_res
);
9462 tcg_temp_free_i32(tcg_op
);
9464 clear_vec_high(s
, is_q
, rd
);
9467 tcg_temp_free_ptr(fpst
);
9470 static void handle_2misc_narrow(DisasContext
*s
, bool scalar
,
9471 int opcode
, bool u
, bool is_q
,
9472 int size
, int rn
, int rd
)
9474 /* Handle 2-reg-misc ops which are narrowing (so each 2*size element
9475 * in the source becomes a size element in the destination).
9478 TCGv_i32 tcg_res
[2];
9479 int destelt
= is_q
? 2 : 0;
9480 int passes
= scalar
? 1 : 2;
9483 tcg_res
[1] = tcg_const_i32(0);
9486 for (pass
= 0; pass
< passes
; pass
++) {
9487 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9488 NeonGenNarrowFn
*genfn
= NULL
;
9489 NeonGenNarrowEnvFn
*genenvfn
= NULL
;
9492 read_vec_element(s
, tcg_op
, rn
, pass
, size
+ 1);
9494 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9496 tcg_res
[pass
] = tcg_temp_new_i32();
9499 case 0x12: /* XTN, SQXTUN */
9501 static NeonGenNarrowFn
* const xtnfns
[3] = {
9502 gen_helper_neon_narrow_u8
,
9503 gen_helper_neon_narrow_u16
,
9504 tcg_gen_extrl_i64_i32
,
9506 static NeonGenNarrowEnvFn
* const sqxtunfns
[3] = {
9507 gen_helper_neon_unarrow_sat8
,
9508 gen_helper_neon_unarrow_sat16
,
9509 gen_helper_neon_unarrow_sat32
,
9512 genenvfn
= sqxtunfns
[size
];
9514 genfn
= xtnfns
[size
];
9518 case 0x14: /* SQXTN, UQXTN */
9520 static NeonGenNarrowEnvFn
* const fns
[3][2] = {
9521 { gen_helper_neon_narrow_sat_s8
,
9522 gen_helper_neon_narrow_sat_u8
},
9523 { gen_helper_neon_narrow_sat_s16
,
9524 gen_helper_neon_narrow_sat_u16
},
9525 { gen_helper_neon_narrow_sat_s32
,
9526 gen_helper_neon_narrow_sat_u32
},
9528 genenvfn
= fns
[size
][u
];
9531 case 0x16: /* FCVTN, FCVTN2 */
9532 /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
9534 gen_helper_vfp_fcvtsd(tcg_res
[pass
], tcg_op
, cpu_env
);
9536 TCGv_i32 tcg_lo
= tcg_temp_new_i32();
9537 TCGv_i32 tcg_hi
= tcg_temp_new_i32();
9538 TCGv_ptr fpst
= get_fpstatus_ptr(false);
9539 TCGv_i32 ahp
= get_ahp_flag();
9541 tcg_gen_extr_i64_i32(tcg_lo
, tcg_hi
, tcg_op
);
9542 gen_helper_vfp_fcvt_f32_to_f16(tcg_lo
, tcg_lo
, fpst
, ahp
);
9543 gen_helper_vfp_fcvt_f32_to_f16(tcg_hi
, tcg_hi
, fpst
, ahp
);
9544 tcg_gen_deposit_i32(tcg_res
[pass
], tcg_lo
, tcg_hi
, 16, 16);
9545 tcg_temp_free_i32(tcg_lo
);
9546 tcg_temp_free_i32(tcg_hi
);
9547 tcg_temp_free_ptr(fpst
);
9548 tcg_temp_free_i32(ahp
);
9551 case 0x56: /* FCVTXN, FCVTXN2 */
9552 /* 64 bit to 32 bit float conversion
9553 * with von Neumann rounding (round to odd)
9556 gen_helper_fcvtx_f64_to_f32(tcg_res
[pass
], tcg_op
, cpu_env
);
9559 g_assert_not_reached();
9563 genfn(tcg_res
[pass
], tcg_op
);
9564 } else if (genenvfn
) {
9565 genenvfn(tcg_res
[pass
], cpu_env
, tcg_op
);
9568 tcg_temp_free_i64(tcg_op
);
9571 for (pass
= 0; pass
< 2; pass
++) {
9572 write_vec_element_i32(s
, tcg_res
[pass
], rd
, destelt
+ pass
, MO_32
);
9573 tcg_temp_free_i32(tcg_res
[pass
]);
9575 clear_vec_high(s
, is_q
, rd
);
9578 /* Remaining saturating accumulating ops */
9579 static void handle_2misc_satacc(DisasContext
*s
, bool is_scalar
, bool is_u
,
9580 bool is_q
, int size
, int rn
, int rd
)
9582 bool is_double
= (size
== 3);
9585 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
9586 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
9589 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9590 read_vec_element(s
, tcg_rn
, rn
, pass
, MO_64
);
9591 read_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
9593 if (is_u
) { /* USQADD */
9594 gen_helper_neon_uqadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9595 } else { /* SUQADD */
9596 gen_helper_neon_sqadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9598 write_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
9600 tcg_temp_free_i64(tcg_rd
);
9601 tcg_temp_free_i64(tcg_rn
);
9602 clear_vec_high(s
, !is_scalar
, rd
);
9604 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
9605 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
9606 int pass
, maxpasses
;
9611 maxpasses
= is_q
? 4 : 2;
9614 for (pass
= 0; pass
< maxpasses
; pass
++) {
9616 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, size
);
9617 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, size
);
9619 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, MO_32
);
9620 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
9623 if (is_u
) { /* USQADD */
9626 gen_helper_neon_uqadd_s8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9629 gen_helper_neon_uqadd_s16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9632 gen_helper_neon_uqadd_s32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9635 g_assert_not_reached();
9637 } else { /* SUQADD */
9640 gen_helper_neon_sqadd_u8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9643 gen_helper_neon_sqadd_u16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9646 gen_helper_neon_sqadd_u32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9649 g_assert_not_reached();
9654 TCGv_i64 tcg_zero
= tcg_const_i64(0);
9655 write_vec_element(s
, tcg_zero
, rd
, 0, MO_64
);
9656 tcg_temp_free_i64(tcg_zero
);
9658 write_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
9660 tcg_temp_free_i32(tcg_rd
);
9661 tcg_temp_free_i32(tcg_rn
);
9662 clear_vec_high(s
, is_q
, rd
);
9666 /* AdvSIMD scalar two reg misc
9667 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
9668 * +-----+---+-----------+------+-----------+--------+-----+------+------+
9669 * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
9670 * +-----+---+-----------+------+-----------+--------+-----+------+------+
9672 static void disas_simd_scalar_two_reg_misc(DisasContext
*s
, uint32_t insn
)
9674 int rd
= extract32(insn
, 0, 5);
9675 int rn
= extract32(insn
, 5, 5);
9676 int opcode
= extract32(insn
, 12, 5);
9677 int size
= extract32(insn
, 22, 2);
9678 bool u
= extract32(insn
, 29, 1);
9679 bool is_fcvt
= false;
9682 TCGv_ptr tcg_fpstatus
;
9685 case 0x3: /* USQADD / SUQADD*/
9686 if (!fp_access_check(s
)) {
9689 handle_2misc_satacc(s
, true, u
, false, size
, rn
, rd
);
9691 case 0x7: /* SQABS / SQNEG */
9693 case 0xa: /* CMLT */
9695 unallocated_encoding(s
);
9699 case 0x8: /* CMGT, CMGE */
9700 case 0x9: /* CMEQ, CMLE */
9701 case 0xb: /* ABS, NEG */
9703 unallocated_encoding(s
);
9707 case 0x12: /* SQXTUN */
9709 unallocated_encoding(s
);
9713 case 0x14: /* SQXTN, UQXTN */
9715 unallocated_encoding(s
);
9718 if (!fp_access_check(s
)) {
9721 handle_2misc_narrow(s
, true, opcode
, u
, false, size
, rn
, rd
);
9726 /* Floating point: U, size[1] and opcode indicate operation;
9727 * size[0] indicates single or double precision.
9729 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
9730 size
= extract32(size
, 0, 1) ? 3 : 2;
9732 case 0x2c: /* FCMGT (zero) */
9733 case 0x2d: /* FCMEQ (zero) */
9734 case 0x2e: /* FCMLT (zero) */
9735 case 0x6c: /* FCMGE (zero) */
9736 case 0x6d: /* FCMLE (zero) */
9737 handle_2misc_fcmp_zero(s
, opcode
, true, u
, true, size
, rn
, rd
);
9739 case 0x1d: /* SCVTF */
9740 case 0x5d: /* UCVTF */
9742 bool is_signed
= (opcode
== 0x1d);
9743 if (!fp_access_check(s
)) {
9746 handle_simd_intfp_conv(s
, rd
, rn
, 1, is_signed
, 0, size
);
9749 case 0x3d: /* FRECPE */
9750 case 0x3f: /* FRECPX */
9751 case 0x7d: /* FRSQRTE */
9752 if (!fp_access_check(s
)) {
9755 handle_2misc_reciprocal(s
, opcode
, true, u
, true, size
, rn
, rd
);
9757 case 0x1a: /* FCVTNS */
9758 case 0x1b: /* FCVTMS */
9759 case 0x3a: /* FCVTPS */
9760 case 0x3b: /* FCVTZS */
9761 case 0x5a: /* FCVTNU */
9762 case 0x5b: /* FCVTMU */
9763 case 0x7a: /* FCVTPU */
9764 case 0x7b: /* FCVTZU */
9766 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
9768 case 0x1c: /* FCVTAS */
9769 case 0x5c: /* FCVTAU */
9770 /* TIEAWAY doesn't fit in the usual rounding mode encoding */
9772 rmode
= FPROUNDING_TIEAWAY
;
9774 case 0x56: /* FCVTXN, FCVTXN2 */
9776 unallocated_encoding(s
);
9779 if (!fp_access_check(s
)) {
9782 handle_2misc_narrow(s
, true, opcode
, u
, false, size
- 1, rn
, rd
);
9785 unallocated_encoding(s
);
9790 unallocated_encoding(s
);
9794 if (!fp_access_check(s
)) {
9799 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
9800 tcg_fpstatus
= get_fpstatus_ptr(false);
9801 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
9804 tcg_fpstatus
= NULL
;
9808 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
9809 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
9811 handle_2misc_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rmode
, tcg_fpstatus
);
9812 write_fp_dreg(s
, rd
, tcg_rd
);
9813 tcg_temp_free_i64(tcg_rd
);
9814 tcg_temp_free_i64(tcg_rn
);
9816 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
9817 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
9819 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
9822 case 0x7: /* SQABS, SQNEG */
9824 NeonGenOneOpEnvFn
*genfn
;
9825 static NeonGenOneOpEnvFn
* const fns
[3][2] = {
9826 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
9827 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
9828 { gen_helper_neon_qabs_s32
, gen_helper_neon_qneg_s32
},
9830 genfn
= fns
[size
][u
];
9831 genfn(tcg_rd
, cpu_env
, tcg_rn
);
9834 case 0x1a: /* FCVTNS */
9835 case 0x1b: /* FCVTMS */
9836 case 0x1c: /* FCVTAS */
9837 case 0x3a: /* FCVTPS */
9838 case 0x3b: /* FCVTZS */
9840 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9841 gen_helper_vfp_tosls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9842 tcg_temp_free_i32(tcg_shift
);
9845 case 0x5a: /* FCVTNU */
9846 case 0x5b: /* FCVTMU */
9847 case 0x5c: /* FCVTAU */
9848 case 0x7a: /* FCVTPU */
9849 case 0x7b: /* FCVTZU */
9851 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9852 gen_helper_vfp_touls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9853 tcg_temp_free_i32(tcg_shift
);
9857 g_assert_not_reached();
9860 write_fp_sreg(s
, rd
, tcg_rd
);
9861 tcg_temp_free_i32(tcg_rd
);
9862 tcg_temp_free_i32(tcg_rn
);
9866 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
9867 tcg_temp_free_i32(tcg_rmode
);
9868 tcg_temp_free_ptr(tcg_fpstatus
);
9872 /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
9873 static void handle_vec_simd_shri(DisasContext
*s
, bool is_q
, bool is_u
,
9874 int immh
, int immb
, int opcode
, int rn
, int rd
)
9876 int size
= 32 - clz32(immh
) - 1;
9877 int immhb
= immh
<< 3 | immb
;
9878 int shift
= 2 * (8 << size
) - immhb
;
9879 bool accumulate
= false;
9880 int dsize
= is_q
? 128 : 64;
9881 int esize
= 8 << size
;
9882 int elements
= dsize
/esize
;
9883 TCGMemOp memop
= size
| (is_u
? 0 : MO_SIGN
);
9884 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
9885 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
9887 uint64_t round_const
;
9890 if (extract32(immh
, 3, 1) && !is_q
) {
9891 unallocated_encoding(s
);
9894 tcg_debug_assert(size
<= 3);
9896 if (!fp_access_check(s
)) {
9901 case 0x02: /* SSRA / USRA (accumulate) */
9903 /* Shift count same as element size produces zero to add. */
9904 if (shift
== 8 << size
) {
9907 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &usra_op
[size
]);
9909 /* Shift count same as element size produces all sign to add. */
9910 if (shift
== 8 << size
) {
9913 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &ssra_op
[size
]);
9916 case 0x08: /* SRI */
9917 /* Shift count same as element size is valid but does nothing. */
9918 if (shift
== 8 << size
) {
9921 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &sri_op
[size
]);
9924 case 0x00: /* SSHR / USHR */
9926 if (shift
== 8 << size
) {
9927 /* Shift count the same size as element size produces zero. */
9928 tcg_gen_gvec_dup8i(vec_full_reg_offset(s
, rd
),
9929 is_q
? 16 : 8, vec_full_reg_size(s
), 0);
9931 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_shri
, size
);
9934 /* Shift count the same size as element size produces all sign. */
9935 if (shift
== 8 << size
) {
9938 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_sari
, size
);
9942 case 0x04: /* SRSHR / URSHR (rounding) */
9944 case 0x06: /* SRSRA / URSRA (accum + rounding) */
9948 g_assert_not_reached();
9951 round_const
= 1ULL << (shift
- 1);
9952 tcg_round
= tcg_const_i64(round_const
);
9954 for (i
= 0; i
< elements
; i
++) {
9955 read_vec_element(s
, tcg_rn
, rn
, i
, memop
);
9957 read_vec_element(s
, tcg_rd
, rd
, i
, memop
);
9960 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
9961 accumulate
, is_u
, size
, shift
);
9963 write_vec_element(s
, tcg_rd
, rd
, i
, size
);
9965 tcg_temp_free_i64(tcg_round
);
9968 clear_vec_high(s
, is_q
, rd
);
9971 /* SHL/SLI - Vector shift left */
9972 static void handle_vec_simd_shli(DisasContext
*s
, bool is_q
, bool insert
,
9973 int immh
, int immb
, int opcode
, int rn
, int rd
)
9975 int size
= 32 - clz32(immh
) - 1;
9976 int immhb
= immh
<< 3 | immb
;
9977 int shift
= immhb
- (8 << size
);
9979 /* Range of size is limited by decode: immh is a non-zero 4 bit field */
9980 assert(size
>= 0 && size
<= 3);
9982 if (extract32(immh
, 3, 1) && !is_q
) {
9983 unallocated_encoding(s
);
9987 if (!fp_access_check(s
)) {
9992 gen_gvec_op2i(s
, is_q
, rd
, rn
, shift
, &sli_op
[size
]);
9994 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_shli
, size
);
9998 /* USHLL/SHLL - Vector shift left with widening */
9999 static void handle_vec_simd_wshli(DisasContext
*s
, bool is_q
, bool is_u
,
10000 int immh
, int immb
, int opcode
, int rn
, int rd
)
10002 int size
= 32 - clz32(immh
) - 1;
10003 int immhb
= immh
<< 3 | immb
;
10004 int shift
= immhb
- (8 << size
);
10006 int esize
= 8 << size
;
10007 int elements
= dsize
/esize
;
10008 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
10009 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
10013 unallocated_encoding(s
);
10017 if (!fp_access_check(s
)) {
10021 /* For the LL variants the store is larger than the load,
10022 * so if rd == rn we would overwrite parts of our input.
10023 * So load everything right now and use shifts in the main loop.
10025 read_vec_element(s
, tcg_rn
, rn
, is_q
? 1 : 0, MO_64
);
10027 for (i
= 0; i
< elements
; i
++) {
10028 tcg_gen_shri_i64(tcg_rd
, tcg_rn
, i
* esize
);
10029 ext_and_shift_reg(tcg_rd
, tcg_rd
, size
| (!is_u
<< 2), 0);
10030 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, shift
);
10031 write_vec_element(s
, tcg_rd
, rd
, i
, size
+ 1);
10035 /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */
10036 static void handle_vec_simd_shrn(DisasContext
*s
, bool is_q
,
10037 int immh
, int immb
, int opcode
, int rn
, int rd
)
10039 int immhb
= immh
<< 3 | immb
;
10040 int size
= 32 - clz32(immh
) - 1;
10042 int esize
= 8 << size
;
10043 int elements
= dsize
/esize
;
10044 int shift
= (2 * esize
) - immhb
;
10045 bool round
= extract32(opcode
, 0, 1);
10046 TCGv_i64 tcg_rn
, tcg_rd
, tcg_final
;
10047 TCGv_i64 tcg_round
;
10050 if (extract32(immh
, 3, 1)) {
10051 unallocated_encoding(s
);
10055 if (!fp_access_check(s
)) {
10059 tcg_rn
= tcg_temp_new_i64();
10060 tcg_rd
= tcg_temp_new_i64();
10061 tcg_final
= tcg_temp_new_i64();
10062 read_vec_element(s
, tcg_final
, rd
, is_q
? 1 : 0, MO_64
);
10065 uint64_t round_const
= 1ULL << (shift
- 1);
10066 tcg_round
= tcg_const_i64(round_const
);
10071 for (i
= 0; i
< elements
; i
++) {
10072 read_vec_element(s
, tcg_rn
, rn
, i
, size
+1);
10073 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
10074 false, true, size
+1, shift
);
10076 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
10080 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
10082 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
10085 tcg_temp_free_i64(tcg_round
);
10087 tcg_temp_free_i64(tcg_rn
);
10088 tcg_temp_free_i64(tcg_rd
);
10089 tcg_temp_free_i64(tcg_final
);
10091 clear_vec_high(s
, is_q
, rd
);
10095 /* AdvSIMD shift by immediate
10096 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
10097 * +---+---+---+-------------+------+------+--------+---+------+------+
10098 * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
10099 * +---+---+---+-------------+------+------+--------+---+------+------+
10101 static void disas_simd_shift_imm(DisasContext
*s
, uint32_t insn
)
10103 int rd
= extract32(insn
, 0, 5);
10104 int rn
= extract32(insn
, 5, 5);
10105 int opcode
= extract32(insn
, 11, 5);
10106 int immb
= extract32(insn
, 16, 3);
10107 int immh
= extract32(insn
, 19, 4);
10108 bool is_u
= extract32(insn
, 29, 1);
10109 bool is_q
= extract32(insn
, 30, 1);
10112 case 0x08: /* SRI */
10114 unallocated_encoding(s
);
10118 case 0x00: /* SSHR / USHR */
10119 case 0x02: /* SSRA / USRA (accumulate) */
10120 case 0x04: /* SRSHR / URSHR (rounding) */
10121 case 0x06: /* SRSRA / URSRA (accum + rounding) */
10122 handle_vec_simd_shri(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10124 case 0x0a: /* SHL / SLI */
10125 handle_vec_simd_shli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10127 case 0x10: /* SHRN */
10128 case 0x11: /* RSHRN / SQRSHRUN */
10130 handle_vec_simd_sqshrn(s
, false, is_q
, false, true, immh
, immb
,
10133 handle_vec_simd_shrn(s
, is_q
, immh
, immb
, opcode
, rn
, rd
);
10136 case 0x12: /* SQSHRN / UQSHRN */
10137 case 0x13: /* SQRSHRN / UQRSHRN */
10138 handle_vec_simd_sqshrn(s
, false, is_q
, is_u
, is_u
, immh
, immb
,
10141 case 0x14: /* SSHLL / USHLL */
10142 handle_vec_simd_wshli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10144 case 0x1c: /* SCVTF / UCVTF */
10145 handle_simd_shift_intfp_conv(s
, false, is_q
, is_u
, immh
, immb
,
10148 case 0xc: /* SQSHLU */
10150 unallocated_encoding(s
);
10153 handle_simd_qshl(s
, false, is_q
, false, true, immh
, immb
, rn
, rd
);
10155 case 0xe: /* SQSHL, UQSHL */
10156 handle_simd_qshl(s
, false, is_q
, is_u
, is_u
, immh
, immb
, rn
, rd
);
10158 case 0x1f: /* FCVTZS/ FCVTZU */
10159 handle_simd_shift_fpint_conv(s
, false, is_q
, is_u
, immh
, immb
, rn
, rd
);
10162 unallocated_encoding(s
);
10167 /* Generate code to do a "long" addition or subtraction, ie one done in
10168 * TCGv_i64 on vector lanes twice the width specified by size.
10170 static void gen_neon_addl(int size
, bool is_sub
, TCGv_i64 tcg_res
,
10171 TCGv_i64 tcg_op1
, TCGv_i64 tcg_op2
)
10173 static NeonGenTwo64OpFn
* const fns
[3][2] = {
10174 { gen_helper_neon_addl_u16
, gen_helper_neon_subl_u16
},
10175 { gen_helper_neon_addl_u32
, gen_helper_neon_subl_u32
},
10176 { tcg_gen_add_i64
, tcg_gen_sub_i64
},
10178 NeonGenTwo64OpFn
*genfn
;
10181 genfn
= fns
[size
][is_sub
];
10182 genfn(tcg_res
, tcg_op1
, tcg_op2
);
10185 static void handle_3rd_widening(DisasContext
*s
, int is_q
, int is_u
, int size
,
10186 int opcode
, int rd
, int rn
, int rm
)
10188 /* 3-reg-different widening insns: 64 x 64 -> 128 */
10189 TCGv_i64 tcg_res
[2];
10192 tcg_res
[0] = tcg_temp_new_i64();
10193 tcg_res
[1] = tcg_temp_new_i64();
10195 /* Does this op do an adding accumulate, a subtracting accumulate,
10196 * or no accumulate at all?
10214 read_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
10215 read_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
10218 /* size == 2 means two 32x32->64 operations; this is worth special
10219 * casing because we can generally handle it inline.
10222 for (pass
= 0; pass
< 2; pass
++) {
10223 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10224 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10225 TCGv_i64 tcg_passres
;
10226 TCGMemOp memop
= MO_32
| (is_u
? 0 : MO_SIGN
);
10228 int elt
= pass
+ is_q
* 2;
10230 read_vec_element(s
, tcg_op1
, rn
, elt
, memop
);
10231 read_vec_element(s
, tcg_op2
, rm
, elt
, memop
);
10234 tcg_passres
= tcg_res
[pass
];
10236 tcg_passres
= tcg_temp_new_i64();
10240 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10241 tcg_gen_add_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10243 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10244 tcg_gen_sub_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10246 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10247 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10249 TCGv_i64 tcg_tmp1
= tcg_temp_new_i64();
10250 TCGv_i64 tcg_tmp2
= tcg_temp_new_i64();
10252 tcg_gen_sub_i64(tcg_tmp1
, tcg_op1
, tcg_op2
);
10253 tcg_gen_sub_i64(tcg_tmp2
, tcg_op2
, tcg_op1
);
10254 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
10256 tcg_op1
, tcg_op2
, tcg_tmp1
, tcg_tmp2
);
10257 tcg_temp_free_i64(tcg_tmp1
);
10258 tcg_temp_free_i64(tcg_tmp2
);
10261 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10262 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10263 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
10264 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10266 case 9: /* SQDMLAL, SQDMLAL2 */
10267 case 11: /* SQDMLSL, SQDMLSL2 */
10268 case 13: /* SQDMULL, SQDMULL2 */
10269 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10270 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
10271 tcg_passres
, tcg_passres
);
10274 g_assert_not_reached();
10277 if (opcode
== 9 || opcode
== 11) {
10278 /* saturating accumulate ops */
10280 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
10282 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
10283 tcg_res
[pass
], tcg_passres
);
10284 } else if (accop
> 0) {
10285 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10286 } else if (accop
< 0) {
10287 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10291 tcg_temp_free_i64(tcg_passres
);
10294 tcg_temp_free_i64(tcg_op1
);
10295 tcg_temp_free_i64(tcg_op2
);
10298 /* size 0 or 1, generally helper functions */
10299 for (pass
= 0; pass
< 2; pass
++) {
10300 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
10301 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10302 TCGv_i64 tcg_passres
;
10303 int elt
= pass
+ is_q
* 2;
10305 read_vec_element_i32(s
, tcg_op1
, rn
, elt
, MO_32
);
10306 read_vec_element_i32(s
, tcg_op2
, rm
, elt
, MO_32
);
10309 tcg_passres
= tcg_res
[pass
];
10311 tcg_passres
= tcg_temp_new_i64();
10315 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10316 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10318 TCGv_i64 tcg_op2_64
= tcg_temp_new_i64();
10319 static NeonGenWidenFn
* const widenfns
[2][2] = {
10320 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
10321 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
10323 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
10325 widenfn(tcg_op2_64
, tcg_op2
);
10326 widenfn(tcg_passres
, tcg_op1
);
10327 gen_neon_addl(size
, (opcode
== 2), tcg_passres
,
10328 tcg_passres
, tcg_op2_64
);
10329 tcg_temp_free_i64(tcg_op2_64
);
10332 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10333 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10336 gen_helper_neon_abdl_u16(tcg_passres
, tcg_op1
, tcg_op2
);
10338 gen_helper_neon_abdl_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10342 gen_helper_neon_abdl_u32(tcg_passres
, tcg_op1
, tcg_op2
);
10344 gen_helper_neon_abdl_s32(tcg_passres
, tcg_op1
, tcg_op2
);
10348 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10349 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10350 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
10353 gen_helper_neon_mull_u8(tcg_passres
, tcg_op1
, tcg_op2
);
10355 gen_helper_neon_mull_s8(tcg_passres
, tcg_op1
, tcg_op2
);
10359 gen_helper_neon_mull_u16(tcg_passres
, tcg_op1
, tcg_op2
);
10361 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10365 case 9: /* SQDMLAL, SQDMLAL2 */
10366 case 11: /* SQDMLSL, SQDMLSL2 */
10367 case 13: /* SQDMULL, SQDMULL2 */
10369 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10370 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
10371 tcg_passres
, tcg_passres
);
10373 case 14: /* PMULL */
10375 gen_helper_neon_mull_p8(tcg_passres
, tcg_op1
, tcg_op2
);
10378 g_assert_not_reached();
10380 tcg_temp_free_i32(tcg_op1
);
10381 tcg_temp_free_i32(tcg_op2
);
10384 if (opcode
== 9 || opcode
== 11) {
10385 /* saturating accumulate ops */
10387 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
10389 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
10393 gen_neon_addl(size
, (accop
< 0), tcg_res
[pass
],
10394 tcg_res
[pass
], tcg_passres
);
10396 tcg_temp_free_i64(tcg_passres
);
10401 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
10402 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
10403 tcg_temp_free_i64(tcg_res
[0]);
10404 tcg_temp_free_i64(tcg_res
[1]);
10407 static void handle_3rd_wide(DisasContext
*s
, int is_q
, int is_u
, int size
,
10408 int opcode
, int rd
, int rn
, int rm
)
10410 TCGv_i64 tcg_res
[2];
10411 int part
= is_q
? 2 : 0;
10414 for (pass
= 0; pass
< 2; pass
++) {
10415 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10416 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10417 TCGv_i64 tcg_op2_wide
= tcg_temp_new_i64();
10418 static NeonGenWidenFn
* const widenfns
[3][2] = {
10419 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
10420 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
10421 { tcg_gen_ext_i32_i64
, tcg_gen_extu_i32_i64
},
10423 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
10425 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
10426 read_vec_element_i32(s
, tcg_op2
, rm
, part
+ pass
, MO_32
);
10427 widenfn(tcg_op2_wide
, tcg_op2
);
10428 tcg_temp_free_i32(tcg_op2
);
10429 tcg_res
[pass
] = tcg_temp_new_i64();
10430 gen_neon_addl(size
, (opcode
== 3),
10431 tcg_res
[pass
], tcg_op1
, tcg_op2_wide
);
10432 tcg_temp_free_i64(tcg_op1
);
10433 tcg_temp_free_i64(tcg_op2_wide
);
10436 for (pass
= 0; pass
< 2; pass
++) {
10437 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10438 tcg_temp_free_i64(tcg_res
[pass
]);
10442 static void do_narrow_round_high_u32(TCGv_i32 res
, TCGv_i64 in
)
10444 tcg_gen_addi_i64(in
, in
, 1U << 31);
10445 tcg_gen_extrh_i64_i32(res
, in
);
10448 static void handle_3rd_narrowing(DisasContext
*s
, int is_q
, int is_u
, int size
,
10449 int opcode
, int rd
, int rn
, int rm
)
10451 TCGv_i32 tcg_res
[2];
10452 int part
= is_q
? 2 : 0;
10455 for (pass
= 0; pass
< 2; pass
++) {
10456 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10457 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10458 TCGv_i64 tcg_wideres
= tcg_temp_new_i64();
10459 static NeonGenNarrowFn
* const narrowfns
[3][2] = {
10460 { gen_helper_neon_narrow_high_u8
,
10461 gen_helper_neon_narrow_round_high_u8
},
10462 { gen_helper_neon_narrow_high_u16
,
10463 gen_helper_neon_narrow_round_high_u16
},
10464 { tcg_gen_extrh_i64_i32
, do_narrow_round_high_u32
},
10466 NeonGenNarrowFn
*gennarrow
= narrowfns
[size
][is_u
];
10468 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
10469 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
10471 gen_neon_addl(size
, (opcode
== 6), tcg_wideres
, tcg_op1
, tcg_op2
);
10473 tcg_temp_free_i64(tcg_op1
);
10474 tcg_temp_free_i64(tcg_op2
);
10476 tcg_res
[pass
] = tcg_temp_new_i32();
10477 gennarrow(tcg_res
[pass
], tcg_wideres
);
10478 tcg_temp_free_i64(tcg_wideres
);
10481 for (pass
= 0; pass
< 2; pass
++) {
10482 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
+ part
, MO_32
);
10483 tcg_temp_free_i32(tcg_res
[pass
]);
10485 clear_vec_high(s
, is_q
, rd
);
10488 static void handle_pmull_64(DisasContext
*s
, int is_q
, int rd
, int rn
, int rm
)
10490 /* PMULL of 64 x 64 -> 128 is an odd special case because it
10491 * is the only three-reg-diff instruction which produces a
10492 * 128-bit wide result from a single operation. However since
10493 * it's possible to calculate the two halves more or less
10494 * separately we just use two helper calls.
10496 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10497 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10498 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10500 read_vec_element(s
, tcg_op1
, rn
, is_q
, MO_64
);
10501 read_vec_element(s
, tcg_op2
, rm
, is_q
, MO_64
);
10502 gen_helper_neon_pmull_64_lo(tcg_res
, tcg_op1
, tcg_op2
);
10503 write_vec_element(s
, tcg_res
, rd
, 0, MO_64
);
10504 gen_helper_neon_pmull_64_hi(tcg_res
, tcg_op1
, tcg_op2
);
10505 write_vec_element(s
, tcg_res
, rd
, 1, MO_64
);
10507 tcg_temp_free_i64(tcg_op1
);
10508 tcg_temp_free_i64(tcg_op2
);
10509 tcg_temp_free_i64(tcg_res
);
10512 /* AdvSIMD three different
10513 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
10514 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
10515 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
10516 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
10518 static void disas_simd_three_reg_diff(DisasContext
*s
, uint32_t insn
)
10520 /* Instructions in this group fall into three basic classes
10521 * (in each case with the operation working on each element in
10522 * the input vectors):
10523 * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
10525 * (2) wide 64 x 128 -> 128
10526 * (3) narrowing 128 x 128 -> 64
10527 * Here we do initial decode, catch unallocated cases and
10528 * dispatch to separate functions for each class.
10530 int is_q
= extract32(insn
, 30, 1);
10531 int is_u
= extract32(insn
, 29, 1);
10532 int size
= extract32(insn
, 22, 2);
10533 int opcode
= extract32(insn
, 12, 4);
10534 int rm
= extract32(insn
, 16, 5);
10535 int rn
= extract32(insn
, 5, 5);
10536 int rd
= extract32(insn
, 0, 5);
10539 case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
10540 case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
10541 /* 64 x 128 -> 128 */
10543 unallocated_encoding(s
);
10546 if (!fp_access_check(s
)) {
10549 handle_3rd_wide(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10551 case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
10552 case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
10553 /* 128 x 128 -> 64 */
10555 unallocated_encoding(s
);
10558 if (!fp_access_check(s
)) {
10561 handle_3rd_narrowing(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10563 case 14: /* PMULL, PMULL2 */
10564 if (is_u
|| size
== 1 || size
== 2) {
10565 unallocated_encoding(s
);
10569 if (!dc_isar_feature(aa64_pmull
, s
)) {
10570 unallocated_encoding(s
);
10573 if (!fp_access_check(s
)) {
10576 handle_pmull_64(s
, is_q
, rd
, rn
, rm
);
10580 case 9: /* SQDMLAL, SQDMLAL2 */
10581 case 11: /* SQDMLSL, SQDMLSL2 */
10582 case 13: /* SQDMULL, SQDMULL2 */
10583 if (is_u
|| size
== 0) {
10584 unallocated_encoding(s
);
10588 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10589 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10590 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10591 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10592 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10593 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10594 case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
10595 /* 64 x 64 -> 128 */
10597 unallocated_encoding(s
);
10601 if (!fp_access_check(s
)) {
10605 handle_3rd_widening(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10608 /* opcode 15 not allocated */
10609 unallocated_encoding(s
);
10614 /* Logic op (opcode == 3) subgroup of C3.6.16. */
10615 static void disas_simd_3same_logic(DisasContext
*s
, uint32_t insn
)
10617 int rd
= extract32(insn
, 0, 5);
10618 int rn
= extract32(insn
, 5, 5);
10619 int rm
= extract32(insn
, 16, 5);
10620 int size
= extract32(insn
, 22, 2);
10621 bool is_u
= extract32(insn
, 29, 1);
10622 bool is_q
= extract32(insn
, 30, 1);
10624 if (!fp_access_check(s
)) {
10628 switch (size
+ 4 * is_u
) {
10630 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_and
, 0);
10633 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_andc
, 0);
10636 if (rn
== rm
) { /* MOV */
10637 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_mov
, 0);
10639 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_or
, 0);
10643 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_orc
, 0);
10646 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_xor
, 0);
10649 case 5: /* BSL bitwise select */
10650 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &bsl_op
);
10652 case 6: /* BIT, bitwise insert if true */
10653 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &bit_op
);
10655 case 7: /* BIF, bitwise insert if false */
10656 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &bif_op
);
10660 g_assert_not_reached();
10664 /* Pairwise op subgroup of C3.6.16.
10666 * This is called directly or via the handle_3same_float for float pairwise
10667 * operations where the opcode and size are calculated differently.
10669 static void handle_simd_3same_pair(DisasContext
*s
, int is_q
, int u
, int opcode
,
10670 int size
, int rn
, int rm
, int rd
)
10675 /* Floating point operations need fpst */
10676 if (opcode
>= 0x58) {
10677 fpst
= get_fpstatus_ptr(false);
10682 if (!fp_access_check(s
)) {
10686 /* These operations work on the concatenated rm:rn, with each pair of
10687 * adjacent elements being operated on to produce an element in the result.
10690 TCGv_i64 tcg_res
[2];
10692 for (pass
= 0; pass
< 2; pass
++) {
10693 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10694 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10695 int passreg
= (pass
== 0) ? rn
: rm
;
10697 read_vec_element(s
, tcg_op1
, passreg
, 0, MO_64
);
10698 read_vec_element(s
, tcg_op2
, passreg
, 1, MO_64
);
10699 tcg_res
[pass
] = tcg_temp_new_i64();
10702 case 0x17: /* ADDP */
10703 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
10705 case 0x58: /* FMAXNMP */
10706 gen_helper_vfp_maxnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10708 case 0x5a: /* FADDP */
10709 gen_helper_vfp_addd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10711 case 0x5e: /* FMAXP */
10712 gen_helper_vfp_maxd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10714 case 0x78: /* FMINNMP */
10715 gen_helper_vfp_minnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10717 case 0x7e: /* FMINP */
10718 gen_helper_vfp_mind(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10721 g_assert_not_reached();
10724 tcg_temp_free_i64(tcg_op1
);
10725 tcg_temp_free_i64(tcg_op2
);
10728 for (pass
= 0; pass
< 2; pass
++) {
10729 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10730 tcg_temp_free_i64(tcg_res
[pass
]);
10733 int maxpass
= is_q
? 4 : 2;
10734 TCGv_i32 tcg_res
[4];
10736 for (pass
= 0; pass
< maxpass
; pass
++) {
10737 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
10738 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10739 NeonGenTwoOpFn
*genfn
= NULL
;
10740 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
10741 int passelt
= (is_q
&& (pass
& 1)) ? 2 : 0;
10743 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_32
);
10744 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_32
);
10745 tcg_res
[pass
] = tcg_temp_new_i32();
10748 case 0x17: /* ADDP */
10750 static NeonGenTwoOpFn
* const fns
[3] = {
10751 gen_helper_neon_padd_u8
,
10752 gen_helper_neon_padd_u16
,
10758 case 0x14: /* SMAXP, UMAXP */
10760 static NeonGenTwoOpFn
* const fns
[3][2] = {
10761 { gen_helper_neon_pmax_s8
, gen_helper_neon_pmax_u8
},
10762 { gen_helper_neon_pmax_s16
, gen_helper_neon_pmax_u16
},
10763 { tcg_gen_smax_i32
, tcg_gen_umax_i32
},
10765 genfn
= fns
[size
][u
];
10768 case 0x15: /* SMINP, UMINP */
10770 static NeonGenTwoOpFn
* const fns
[3][2] = {
10771 { gen_helper_neon_pmin_s8
, gen_helper_neon_pmin_u8
},
10772 { gen_helper_neon_pmin_s16
, gen_helper_neon_pmin_u16
},
10773 { tcg_gen_smin_i32
, tcg_gen_umin_i32
},
10775 genfn
= fns
[size
][u
];
10778 /* The FP operations are all on single floats (32 bit) */
10779 case 0x58: /* FMAXNMP */
10780 gen_helper_vfp_maxnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10782 case 0x5a: /* FADDP */
10783 gen_helper_vfp_adds(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10785 case 0x5e: /* FMAXP */
10786 gen_helper_vfp_maxs(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10788 case 0x78: /* FMINNMP */
10789 gen_helper_vfp_minnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10791 case 0x7e: /* FMINP */
10792 gen_helper_vfp_mins(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
10795 g_assert_not_reached();
10798 /* FP ops called directly, otherwise call now */
10800 genfn(tcg_res
[pass
], tcg_op1
, tcg_op2
);
10803 tcg_temp_free_i32(tcg_op1
);
10804 tcg_temp_free_i32(tcg_op2
);
10807 for (pass
= 0; pass
< maxpass
; pass
++) {
10808 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
10809 tcg_temp_free_i32(tcg_res
[pass
]);
10811 clear_vec_high(s
, is_q
, rd
);
10815 tcg_temp_free_ptr(fpst
);
10819 /* Floating point op subgroup of C3.6.16. */
10820 static void disas_simd_3same_float(DisasContext
*s
, uint32_t insn
)
10822 /* For floating point ops, the U, size[1] and opcode bits
10823 * together indicate the operation. size[0] indicates single
10826 int fpopcode
= extract32(insn
, 11, 5)
10827 | (extract32(insn
, 23, 1) << 5)
10828 | (extract32(insn
, 29, 1) << 6);
10829 int is_q
= extract32(insn
, 30, 1);
10830 int size
= extract32(insn
, 22, 1);
10831 int rm
= extract32(insn
, 16, 5);
10832 int rn
= extract32(insn
, 5, 5);
10833 int rd
= extract32(insn
, 0, 5);
10835 int datasize
= is_q
? 128 : 64;
10836 int esize
= 32 << size
;
10837 int elements
= datasize
/ esize
;
10839 if (size
== 1 && !is_q
) {
10840 unallocated_encoding(s
);
10844 switch (fpopcode
) {
10845 case 0x58: /* FMAXNMP */
10846 case 0x5a: /* FADDP */
10847 case 0x5e: /* FMAXP */
10848 case 0x78: /* FMINNMP */
10849 case 0x7e: /* FMINP */
10850 if (size
&& !is_q
) {
10851 unallocated_encoding(s
);
10854 handle_simd_3same_pair(s
, is_q
, 0, fpopcode
, size
? MO_64
: MO_32
,
10857 case 0x1b: /* FMULX */
10858 case 0x1f: /* FRECPS */
10859 case 0x3f: /* FRSQRTS */
10860 case 0x5d: /* FACGE */
10861 case 0x7d: /* FACGT */
10862 case 0x19: /* FMLA */
10863 case 0x39: /* FMLS */
10864 case 0x18: /* FMAXNM */
10865 case 0x1a: /* FADD */
10866 case 0x1c: /* FCMEQ */
10867 case 0x1e: /* FMAX */
10868 case 0x38: /* FMINNM */
10869 case 0x3a: /* FSUB */
10870 case 0x3e: /* FMIN */
10871 case 0x5b: /* FMUL */
10872 case 0x5c: /* FCMGE */
10873 case 0x5f: /* FDIV */
10874 case 0x7a: /* FABD */
10875 case 0x7c: /* FCMGT */
10876 if (!fp_access_check(s
)) {
10880 handle_3same_float(s
, size
, elements
, fpopcode
, rd
, rn
, rm
);
10883 unallocated_encoding(s
);
10888 /* Integer op subgroup of C3.6.16. */
10889 static void disas_simd_3same_int(DisasContext
*s
, uint32_t insn
)
10891 int is_q
= extract32(insn
, 30, 1);
10892 int u
= extract32(insn
, 29, 1);
10893 int size
= extract32(insn
, 22, 2);
10894 int opcode
= extract32(insn
, 11, 5);
10895 int rm
= extract32(insn
, 16, 5);
10896 int rn
= extract32(insn
, 5, 5);
10897 int rd
= extract32(insn
, 0, 5);
10902 case 0x13: /* MUL, PMUL */
10903 if (u
&& size
!= 0) {
10904 unallocated_encoding(s
);
10908 case 0x0: /* SHADD, UHADD */
10909 case 0x2: /* SRHADD, URHADD */
10910 case 0x4: /* SHSUB, UHSUB */
10911 case 0xc: /* SMAX, UMAX */
10912 case 0xd: /* SMIN, UMIN */
10913 case 0xe: /* SABD, UABD */
10914 case 0xf: /* SABA, UABA */
10915 case 0x12: /* MLA, MLS */
10917 unallocated_encoding(s
);
10921 case 0x16: /* SQDMULH, SQRDMULH */
10922 if (size
== 0 || size
== 3) {
10923 unallocated_encoding(s
);
10928 if (size
== 3 && !is_q
) {
10929 unallocated_encoding(s
);
10935 if (!fp_access_check(s
)) {
10940 case 0x10: /* ADD, SUB */
10942 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_sub
, size
);
10944 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_add
, size
);
10947 case 0x13: /* MUL, PMUL */
10948 if (!u
) { /* MUL */
10949 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_mul
, size
);
10953 case 0x12: /* MLA, MLS */
10955 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &mls_op
[size
]);
10957 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &mla_op
[size
]);
10961 if (!u
) { /* CMTST */
10962 gen_gvec_op3(s
, is_q
, rd
, rn
, rm
, &cmtst_op
[size
]);
10966 cond
= TCG_COND_EQ
;
10968 case 0x06: /* CMGT, CMHI */
10969 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
10971 case 0x07: /* CMGE, CMHS */
10972 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
10974 tcg_gen_gvec_cmp(cond
, size
, vec_full_reg_offset(s
, rd
),
10975 vec_full_reg_offset(s
, rn
),
10976 vec_full_reg_offset(s
, rm
),
10977 is_q
? 16 : 8, vec_full_reg_size(s
));
10983 for (pass
= 0; pass
< 2; pass
++) {
10984 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10985 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10986 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10988 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
10989 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
10991 handle_3same_64(s
, opcode
, u
, tcg_res
, tcg_op1
, tcg_op2
);
10993 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10995 tcg_temp_free_i64(tcg_res
);
10996 tcg_temp_free_i64(tcg_op1
);
10997 tcg_temp_free_i64(tcg_op2
);
11000 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
11001 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11002 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11003 TCGv_i32 tcg_res
= tcg_temp_new_i32();
11004 NeonGenTwoOpFn
*genfn
= NULL
;
11005 NeonGenTwoOpEnvFn
*genenvfn
= NULL
;
11007 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
11008 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
11011 case 0x0: /* SHADD, UHADD */
11013 static NeonGenTwoOpFn
* const fns
[3][2] = {
11014 { gen_helper_neon_hadd_s8
, gen_helper_neon_hadd_u8
},
11015 { gen_helper_neon_hadd_s16
, gen_helper_neon_hadd_u16
},
11016 { gen_helper_neon_hadd_s32
, gen_helper_neon_hadd_u32
},
11018 genfn
= fns
[size
][u
];
11021 case 0x1: /* SQADD, UQADD */
11023 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11024 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
11025 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
11026 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
11028 genenvfn
= fns
[size
][u
];
11031 case 0x2: /* SRHADD, URHADD */
11033 static NeonGenTwoOpFn
* const fns
[3][2] = {
11034 { gen_helper_neon_rhadd_s8
, gen_helper_neon_rhadd_u8
},
11035 { gen_helper_neon_rhadd_s16
, gen_helper_neon_rhadd_u16
},
11036 { gen_helper_neon_rhadd_s32
, gen_helper_neon_rhadd_u32
},
11038 genfn
= fns
[size
][u
];
11041 case 0x4: /* SHSUB, UHSUB */
11043 static NeonGenTwoOpFn
* const fns
[3][2] = {
11044 { gen_helper_neon_hsub_s8
, gen_helper_neon_hsub_u8
},
11045 { gen_helper_neon_hsub_s16
, gen_helper_neon_hsub_u16
},
11046 { gen_helper_neon_hsub_s32
, gen_helper_neon_hsub_u32
},
11048 genfn
= fns
[size
][u
];
11051 case 0x5: /* SQSUB, UQSUB */
11053 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11054 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
11055 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
11056 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
11058 genenvfn
= fns
[size
][u
];
11061 case 0x8: /* SSHL, USHL */
11063 static NeonGenTwoOpFn
* const fns
[3][2] = {
11064 { gen_helper_neon_shl_s8
, gen_helper_neon_shl_u8
},
11065 { gen_helper_neon_shl_s16
, gen_helper_neon_shl_u16
},
11066 { gen_helper_neon_shl_s32
, gen_helper_neon_shl_u32
},
11068 genfn
= fns
[size
][u
];
11071 case 0x9: /* SQSHL, UQSHL */
11073 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11074 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
11075 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
11076 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
11078 genenvfn
= fns
[size
][u
];
11081 case 0xa: /* SRSHL, URSHL */
11083 static NeonGenTwoOpFn
* const fns
[3][2] = {
11084 { gen_helper_neon_rshl_s8
, gen_helper_neon_rshl_u8
},
11085 { gen_helper_neon_rshl_s16
, gen_helper_neon_rshl_u16
},
11086 { gen_helper_neon_rshl_s32
, gen_helper_neon_rshl_u32
},
11088 genfn
= fns
[size
][u
];
11091 case 0xb: /* SQRSHL, UQRSHL */
11093 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11094 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
11095 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
11096 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
11098 genenvfn
= fns
[size
][u
];
11101 case 0xc: /* SMAX, UMAX */
11103 static NeonGenTwoOpFn
* const fns
[3][2] = {
11104 { gen_helper_neon_max_s8
, gen_helper_neon_max_u8
},
11105 { gen_helper_neon_max_s16
, gen_helper_neon_max_u16
},
11106 { tcg_gen_smax_i32
, tcg_gen_umax_i32
},
11108 genfn
= fns
[size
][u
];
11112 case 0xd: /* SMIN, UMIN */
11114 static NeonGenTwoOpFn
* const fns
[3][2] = {
11115 { gen_helper_neon_min_s8
, gen_helper_neon_min_u8
},
11116 { gen_helper_neon_min_s16
, gen_helper_neon_min_u16
},
11117 { tcg_gen_smin_i32
, tcg_gen_umin_i32
},
11119 genfn
= fns
[size
][u
];
11122 case 0xe: /* SABD, UABD */
11123 case 0xf: /* SABA, UABA */
11125 static NeonGenTwoOpFn
* const fns
[3][2] = {
11126 { gen_helper_neon_abd_s8
, gen_helper_neon_abd_u8
},
11127 { gen_helper_neon_abd_s16
, gen_helper_neon_abd_u16
},
11128 { gen_helper_neon_abd_s32
, gen_helper_neon_abd_u32
},
11130 genfn
= fns
[size
][u
];
11133 case 0x13: /* MUL, PMUL */
11134 assert(u
); /* PMUL */
11136 genfn
= gen_helper_neon_mul_p8
;
11138 case 0x16: /* SQDMULH, SQRDMULH */
11140 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
11141 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
11142 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
11144 assert(size
== 1 || size
== 2);
11145 genenvfn
= fns
[size
- 1][u
];
11149 g_assert_not_reached();
11153 genenvfn(tcg_res
, cpu_env
, tcg_op1
, tcg_op2
);
11155 genfn(tcg_res
, tcg_op1
, tcg_op2
);
11158 if (opcode
== 0xf) {
11159 /* SABA, UABA: accumulating ops */
11160 static NeonGenTwoOpFn
* const fns
[3] = {
11161 gen_helper_neon_add_u8
,
11162 gen_helper_neon_add_u16
,
11166 read_vec_element_i32(s
, tcg_op1
, rd
, pass
, MO_32
);
11167 fns
[size
](tcg_res
, tcg_op1
, tcg_res
);
11170 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
11172 tcg_temp_free_i32(tcg_res
);
11173 tcg_temp_free_i32(tcg_op1
);
11174 tcg_temp_free_i32(tcg_op2
);
11177 clear_vec_high(s
, is_q
, rd
);
11180 /* AdvSIMD three same
11181 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
11182 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11183 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
11184 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11186 static void disas_simd_three_reg_same(DisasContext
*s
, uint32_t insn
)
11188 int opcode
= extract32(insn
, 11, 5);
11191 case 0x3: /* logic ops */
11192 disas_simd_3same_logic(s
, insn
);
11194 case 0x17: /* ADDP */
11195 case 0x14: /* SMAXP, UMAXP */
11196 case 0x15: /* SMINP, UMINP */
11198 /* Pairwise operations */
11199 int is_q
= extract32(insn
, 30, 1);
11200 int u
= extract32(insn
, 29, 1);
11201 int size
= extract32(insn
, 22, 2);
11202 int rm
= extract32(insn
, 16, 5);
11203 int rn
= extract32(insn
, 5, 5);
11204 int rd
= extract32(insn
, 0, 5);
11205 if (opcode
== 0x17) {
11206 if (u
|| (size
== 3 && !is_q
)) {
11207 unallocated_encoding(s
);
11212 unallocated_encoding(s
);
11216 handle_simd_3same_pair(s
, is_q
, u
, opcode
, size
, rn
, rm
, rd
);
11219 case 0x18 ... 0x31:
11220 /* floating point ops, sz[1] and U are part of opcode */
11221 disas_simd_3same_float(s
, insn
);
11224 disas_simd_3same_int(s
, insn
);
11230 * Advanced SIMD three same (ARMv8.2 FP16 variants)
11232 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
11233 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11234 * | 0 | Q | U | 0 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
11235 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11237 * This includes FMULX, FCMEQ (register), FRECPS, FRSQRTS, FCMGE
11238 * (register), FACGE, FABD, FCMGT (register) and FACGT.
11241 static void disas_simd_three_reg_same_fp16(DisasContext
*s
, uint32_t insn
)
11243 int opcode
, fpopcode
;
11244 int is_q
, u
, a
, rm
, rn
, rd
;
11245 int datasize
, elements
;
11248 bool pairwise
= false;
11250 if (!dc_isar_feature(aa64_fp16
, s
)) {
11251 unallocated_encoding(s
);
11255 if (!fp_access_check(s
)) {
11259 /* For these floating point ops, the U, a and opcode bits
11260 * together indicate the operation.
11262 opcode
= extract32(insn
, 11, 3);
11263 u
= extract32(insn
, 29, 1);
11264 a
= extract32(insn
, 23, 1);
11265 is_q
= extract32(insn
, 30, 1);
11266 rm
= extract32(insn
, 16, 5);
11267 rn
= extract32(insn
, 5, 5);
11268 rd
= extract32(insn
, 0, 5);
11270 fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
11271 datasize
= is_q
? 128 : 64;
11272 elements
= datasize
/ 16;
11274 switch (fpopcode
) {
11275 case 0x10: /* FMAXNMP */
11276 case 0x12: /* FADDP */
11277 case 0x16: /* FMAXP */
11278 case 0x18: /* FMINNMP */
11279 case 0x1e: /* FMINP */
11284 fpst
= get_fpstatus_ptr(true);
11287 int maxpass
= is_q
? 8 : 4;
11288 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11289 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11290 TCGv_i32 tcg_res
[8];
11292 for (pass
= 0; pass
< maxpass
; pass
++) {
11293 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
11294 int passelt
= (pass
<< 1) & (maxpass
- 1);
11296 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_16
);
11297 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_16
);
11298 tcg_res
[pass
] = tcg_temp_new_i32();
11300 switch (fpopcode
) {
11301 case 0x10: /* FMAXNMP */
11302 gen_helper_advsimd_maxnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
11305 case 0x12: /* FADDP */
11306 gen_helper_advsimd_addh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11308 case 0x16: /* FMAXP */
11309 gen_helper_advsimd_maxh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11311 case 0x18: /* FMINNMP */
11312 gen_helper_advsimd_minnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
11315 case 0x1e: /* FMINP */
11316 gen_helper_advsimd_minh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11319 g_assert_not_reached();
11323 for (pass
= 0; pass
< maxpass
; pass
++) {
11324 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_16
);
11325 tcg_temp_free_i32(tcg_res
[pass
]);
11328 tcg_temp_free_i32(tcg_op1
);
11329 tcg_temp_free_i32(tcg_op2
);
11332 for (pass
= 0; pass
< elements
; pass
++) {
11333 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11334 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11335 TCGv_i32 tcg_res
= tcg_temp_new_i32();
11337 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_16
);
11338 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_16
);
11340 switch (fpopcode
) {
11341 case 0x0: /* FMAXNM */
11342 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11344 case 0x1: /* FMLA */
11345 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11346 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
11349 case 0x2: /* FADD */
11350 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11352 case 0x3: /* FMULX */
11353 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11355 case 0x4: /* FCMEQ */
11356 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11358 case 0x6: /* FMAX */
11359 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11361 case 0x7: /* FRECPS */
11362 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11364 case 0x8: /* FMINNM */
11365 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11367 case 0x9: /* FMLS */
11368 /* As usual for ARM, separate negation for fused multiply-add */
11369 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
11370 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11371 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
11374 case 0xa: /* FSUB */
11375 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11377 case 0xe: /* FMIN */
11378 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11380 case 0xf: /* FRSQRTS */
11381 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11383 case 0x13: /* FMUL */
11384 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11386 case 0x14: /* FCMGE */
11387 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11389 case 0x15: /* FACGE */
11390 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11392 case 0x17: /* FDIV */
11393 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11395 case 0x1a: /* FABD */
11396 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11397 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
11399 case 0x1c: /* FCMGT */
11400 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11402 case 0x1d: /* FACGT */
11403 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11406 fprintf(stderr
, "%s: insn %#04x, fpop %#2x @ %#" PRIx64
"\n",
11407 __func__
, insn
, fpopcode
, s
->pc
);
11408 g_assert_not_reached();
11411 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11412 tcg_temp_free_i32(tcg_res
);
11413 tcg_temp_free_i32(tcg_op1
);
11414 tcg_temp_free_i32(tcg_op2
);
11418 tcg_temp_free_ptr(fpst
);
11420 clear_vec_high(s
, is_q
, rd
);
11423 /* AdvSIMD three same extra
11424 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
11425 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
11426 * | 0 | Q | U | 0 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
11427 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
11429 static void disas_simd_three_reg_same_extra(DisasContext
*s
, uint32_t insn
)
11431 int rd
= extract32(insn
, 0, 5);
11432 int rn
= extract32(insn
, 5, 5);
11433 int opcode
= extract32(insn
, 11, 4);
11434 int rm
= extract32(insn
, 16, 5);
11435 int size
= extract32(insn
, 22, 2);
11436 bool u
= extract32(insn
, 29, 1);
11437 bool is_q
= extract32(insn
, 30, 1);
11441 switch (u
* 16 + opcode
) {
11442 case 0x10: /* SQRDMLAH (vector) */
11443 case 0x11: /* SQRDMLSH (vector) */
11444 if (size
!= 1 && size
!= 2) {
11445 unallocated_encoding(s
);
11448 feature
= dc_isar_feature(aa64_rdm
, s
);
11450 case 0x02: /* SDOT (vector) */
11451 case 0x12: /* UDOT (vector) */
11452 if (size
!= MO_32
) {
11453 unallocated_encoding(s
);
11456 feature
= dc_isar_feature(aa64_dp
, s
);
11458 case 0x18: /* FCMLA, #0 */
11459 case 0x19: /* FCMLA, #90 */
11460 case 0x1a: /* FCMLA, #180 */
11461 case 0x1b: /* FCMLA, #270 */
11462 case 0x1c: /* FCADD, #90 */
11463 case 0x1e: /* FCADD, #270 */
11465 || (size
== 1 && !dc_isar_feature(aa64_fp16
, s
))
11466 || (size
== 3 && !is_q
)) {
11467 unallocated_encoding(s
);
11470 feature
= dc_isar_feature(aa64_fcma
, s
);
11473 unallocated_encoding(s
);
11477 unallocated_encoding(s
);
11480 if (!fp_access_check(s
)) {
11485 case 0x0: /* SQRDMLAH (vector) */
11488 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlah_s16
);
11491 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlah_s32
);
11494 g_assert_not_reached();
11498 case 0x1: /* SQRDMLSH (vector) */
11501 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlsh_s16
);
11504 gen_gvec_op3_env(s
, is_q
, rd
, rn
, rm
, gen_helper_gvec_qrdmlsh_s32
);
11507 g_assert_not_reached();
11511 case 0x2: /* SDOT / UDOT */
11512 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, 0,
11513 u
? gen_helper_gvec_udot_b
: gen_helper_gvec_sdot_b
);
11516 case 0x8: /* FCMLA, #0 */
11517 case 0x9: /* FCMLA, #90 */
11518 case 0xa: /* FCMLA, #180 */
11519 case 0xb: /* FCMLA, #270 */
11520 rot
= extract32(opcode
, 0, 2);
11523 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, true, rot
,
11524 gen_helper_gvec_fcmlah
);
11527 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, false, rot
,
11528 gen_helper_gvec_fcmlas
);
11531 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, false, rot
,
11532 gen_helper_gvec_fcmlad
);
11535 g_assert_not_reached();
11539 case 0xc: /* FCADD, #90 */
11540 case 0xe: /* FCADD, #270 */
11541 rot
= extract32(opcode
, 1, 1);
11544 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11545 gen_helper_gvec_fcaddh
);
11548 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11549 gen_helper_gvec_fcadds
);
11552 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11553 gen_helper_gvec_fcaddd
);
11556 g_assert_not_reached();
11561 g_assert_not_reached();
11565 static void handle_2misc_widening(DisasContext
*s
, int opcode
, bool is_q
,
11566 int size
, int rn
, int rd
)
11568 /* Handle 2-reg-misc ops which are widening (so each size element
11569 * in the source becomes a 2*size element in the destination.
11570 * The only instruction like this is FCVTL.
11575 /* 32 -> 64 bit fp conversion */
11576 TCGv_i64 tcg_res
[2];
11577 int srcelt
= is_q
? 2 : 0;
11579 for (pass
= 0; pass
< 2; pass
++) {
11580 TCGv_i32 tcg_op
= tcg_temp_new_i32();
11581 tcg_res
[pass
] = tcg_temp_new_i64();
11583 read_vec_element_i32(s
, tcg_op
, rn
, srcelt
+ pass
, MO_32
);
11584 gen_helper_vfp_fcvtds(tcg_res
[pass
], tcg_op
, cpu_env
);
11585 tcg_temp_free_i32(tcg_op
);
11587 for (pass
= 0; pass
< 2; pass
++) {
11588 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11589 tcg_temp_free_i64(tcg_res
[pass
]);
11592 /* 16 -> 32 bit fp conversion */
11593 int srcelt
= is_q
? 4 : 0;
11594 TCGv_i32 tcg_res
[4];
11595 TCGv_ptr fpst
= get_fpstatus_ptr(false);
11596 TCGv_i32 ahp
= get_ahp_flag();
11598 for (pass
= 0; pass
< 4; pass
++) {
11599 tcg_res
[pass
] = tcg_temp_new_i32();
11601 read_vec_element_i32(s
, tcg_res
[pass
], rn
, srcelt
+ pass
, MO_16
);
11602 gen_helper_vfp_fcvt_f16_to_f32(tcg_res
[pass
], tcg_res
[pass
],
11605 for (pass
= 0; pass
< 4; pass
++) {
11606 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
11607 tcg_temp_free_i32(tcg_res
[pass
]);
11610 tcg_temp_free_ptr(fpst
);
11611 tcg_temp_free_i32(ahp
);
11615 static void handle_rev(DisasContext
*s
, int opcode
, bool u
,
11616 bool is_q
, int size
, int rn
, int rd
)
11618 int op
= (opcode
<< 1) | u
;
11619 int opsz
= op
+ size
;
11620 int grp_size
= 3 - opsz
;
11621 int dsize
= is_q
? 128 : 64;
11625 unallocated_encoding(s
);
11629 if (!fp_access_check(s
)) {
11634 /* Special case bytes, use bswap op on each group of elements */
11635 int groups
= dsize
/ (8 << grp_size
);
11637 for (i
= 0; i
< groups
; i
++) {
11638 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
11640 read_vec_element(s
, tcg_tmp
, rn
, i
, grp_size
);
11641 switch (grp_size
) {
11643 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
11646 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
11649 tcg_gen_bswap64_i64(tcg_tmp
, tcg_tmp
);
11652 g_assert_not_reached();
11654 write_vec_element(s
, tcg_tmp
, rd
, i
, grp_size
);
11655 tcg_temp_free_i64(tcg_tmp
);
11657 clear_vec_high(s
, is_q
, rd
);
11659 int revmask
= (1 << grp_size
) - 1;
11660 int esize
= 8 << size
;
11661 int elements
= dsize
/ esize
;
11662 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
11663 TCGv_i64 tcg_rd
= tcg_const_i64(0);
11664 TCGv_i64 tcg_rd_hi
= tcg_const_i64(0);
11666 for (i
= 0; i
< elements
; i
++) {
11667 int e_rev
= (i
& 0xf) ^ revmask
;
11668 int off
= e_rev
* esize
;
11669 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
11671 tcg_gen_deposit_i64(tcg_rd_hi
, tcg_rd_hi
,
11672 tcg_rn
, off
- 64, esize
);
11674 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, off
, esize
);
11677 write_vec_element(s
, tcg_rd
, rd
, 0, MO_64
);
11678 write_vec_element(s
, tcg_rd_hi
, rd
, 1, MO_64
);
11680 tcg_temp_free_i64(tcg_rd_hi
);
11681 tcg_temp_free_i64(tcg_rd
);
11682 tcg_temp_free_i64(tcg_rn
);
11686 static void handle_2misc_pairwise(DisasContext
*s
, int opcode
, bool u
,
11687 bool is_q
, int size
, int rn
, int rd
)
11689 /* Implement the pairwise operations from 2-misc:
11690 * SADDLP, UADDLP, SADALP, UADALP.
11691 * These all add pairs of elements in the input to produce a
11692 * double-width result element in the output (possibly accumulating).
11694 bool accum
= (opcode
== 0x6);
11695 int maxpass
= is_q
? 2 : 1;
11697 TCGv_i64 tcg_res
[2];
11700 /* 32 + 32 -> 64 op */
11701 TCGMemOp memop
= size
+ (u
? 0 : MO_SIGN
);
11703 for (pass
= 0; pass
< maxpass
; pass
++) {
11704 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11705 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11707 tcg_res
[pass
] = tcg_temp_new_i64();
11709 read_vec_element(s
, tcg_op1
, rn
, pass
* 2, memop
);
11710 read_vec_element(s
, tcg_op2
, rn
, pass
* 2 + 1, memop
);
11711 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
11713 read_vec_element(s
, tcg_op1
, rd
, pass
, MO_64
);
11714 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
11717 tcg_temp_free_i64(tcg_op1
);
11718 tcg_temp_free_i64(tcg_op2
);
11721 for (pass
= 0; pass
< maxpass
; pass
++) {
11722 TCGv_i64 tcg_op
= tcg_temp_new_i64();
11723 NeonGenOneOpFn
*genfn
;
11724 static NeonGenOneOpFn
* const fns
[2][2] = {
11725 { gen_helper_neon_addlp_s8
, gen_helper_neon_addlp_u8
},
11726 { gen_helper_neon_addlp_s16
, gen_helper_neon_addlp_u16
},
11729 genfn
= fns
[size
][u
];
11731 tcg_res
[pass
] = tcg_temp_new_i64();
11733 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
11734 genfn(tcg_res
[pass
], tcg_op
);
11737 read_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
11739 gen_helper_neon_addl_u16(tcg_res
[pass
],
11740 tcg_res
[pass
], tcg_op
);
11742 gen_helper_neon_addl_u32(tcg_res
[pass
],
11743 tcg_res
[pass
], tcg_op
);
11746 tcg_temp_free_i64(tcg_op
);
11750 tcg_res
[1] = tcg_const_i64(0);
11752 for (pass
= 0; pass
< 2; pass
++) {
11753 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11754 tcg_temp_free_i64(tcg_res
[pass
]);
11758 static void handle_shll(DisasContext
*s
, bool is_q
, int size
, int rn
, int rd
)
11760 /* Implement SHLL and SHLL2 */
11762 int part
= is_q
? 2 : 0;
11763 TCGv_i64 tcg_res
[2];
11765 for (pass
= 0; pass
< 2; pass
++) {
11766 static NeonGenWidenFn
* const widenfns
[3] = {
11767 gen_helper_neon_widen_u8
,
11768 gen_helper_neon_widen_u16
,
11769 tcg_gen_extu_i32_i64
,
11771 NeonGenWidenFn
*widenfn
= widenfns
[size
];
11772 TCGv_i32 tcg_op
= tcg_temp_new_i32();
11774 read_vec_element_i32(s
, tcg_op
, rn
, part
+ pass
, MO_32
);
11775 tcg_res
[pass
] = tcg_temp_new_i64();
11776 widenfn(tcg_res
[pass
], tcg_op
);
11777 tcg_gen_shli_i64(tcg_res
[pass
], tcg_res
[pass
], 8 << size
);
11779 tcg_temp_free_i32(tcg_op
);
11782 for (pass
= 0; pass
< 2; pass
++) {
11783 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11784 tcg_temp_free_i64(tcg_res
[pass
]);
11788 /* AdvSIMD two reg misc
11789 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
11790 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
11791 * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
11792 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
11794 static void disas_simd_two_reg_misc(DisasContext
*s
, uint32_t insn
)
11796 int size
= extract32(insn
, 22, 2);
11797 int opcode
= extract32(insn
, 12, 5);
11798 bool u
= extract32(insn
, 29, 1);
11799 bool is_q
= extract32(insn
, 30, 1);
11800 int rn
= extract32(insn
, 5, 5);
11801 int rd
= extract32(insn
, 0, 5);
11802 bool need_fpstatus
= false;
11803 bool need_rmode
= false;
11805 TCGv_i32 tcg_rmode
;
11806 TCGv_ptr tcg_fpstatus
;
11809 case 0x0: /* REV64, REV32 */
11810 case 0x1: /* REV16 */
11811 handle_rev(s
, opcode
, u
, is_q
, size
, rn
, rd
);
11813 case 0x5: /* CNT, NOT, RBIT */
11814 if (u
&& size
== 0) {
11817 } else if (u
&& size
== 1) {
11820 } else if (!u
&& size
== 0) {
11824 unallocated_encoding(s
);
11826 case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
11827 case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
11829 unallocated_encoding(s
);
11832 if (!fp_access_check(s
)) {
11836 handle_2misc_narrow(s
, false, opcode
, u
, is_q
, size
, rn
, rd
);
11838 case 0x4: /* CLS, CLZ */
11840 unallocated_encoding(s
);
11844 case 0x2: /* SADDLP, UADDLP */
11845 case 0x6: /* SADALP, UADALP */
11847 unallocated_encoding(s
);
11850 if (!fp_access_check(s
)) {
11853 handle_2misc_pairwise(s
, opcode
, u
, is_q
, size
, rn
, rd
);
11855 case 0x13: /* SHLL, SHLL2 */
11856 if (u
== 0 || size
== 3) {
11857 unallocated_encoding(s
);
11860 if (!fp_access_check(s
)) {
11863 handle_shll(s
, is_q
, size
, rn
, rd
);
11865 case 0xa: /* CMLT */
11867 unallocated_encoding(s
);
11871 case 0x8: /* CMGT, CMGE */
11872 case 0x9: /* CMEQ, CMLE */
11873 case 0xb: /* ABS, NEG */
11874 if (size
== 3 && !is_q
) {
11875 unallocated_encoding(s
);
11879 case 0x3: /* SUQADD, USQADD */
11880 if (size
== 3 && !is_q
) {
11881 unallocated_encoding(s
);
11884 if (!fp_access_check(s
)) {
11887 handle_2misc_satacc(s
, false, u
, is_q
, size
, rn
, rd
);
11889 case 0x7: /* SQABS, SQNEG */
11890 if (size
== 3 && !is_q
) {
11891 unallocated_encoding(s
);
11896 case 0x16 ... 0x1d:
11899 /* Floating point: U, size[1] and opcode indicate operation;
11900 * size[0] indicates single or double precision.
11902 int is_double
= extract32(size
, 0, 1);
11903 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
11904 size
= is_double
? 3 : 2;
11906 case 0x2f: /* FABS */
11907 case 0x6f: /* FNEG */
11908 if (size
== 3 && !is_q
) {
11909 unallocated_encoding(s
);
11913 case 0x1d: /* SCVTF */
11914 case 0x5d: /* UCVTF */
11916 bool is_signed
= (opcode
== 0x1d) ? true : false;
11917 int elements
= is_double
? 2 : is_q
? 4 : 2;
11918 if (is_double
&& !is_q
) {
11919 unallocated_encoding(s
);
11922 if (!fp_access_check(s
)) {
11925 handle_simd_intfp_conv(s
, rd
, rn
, elements
, is_signed
, 0, size
);
11928 case 0x2c: /* FCMGT (zero) */
11929 case 0x2d: /* FCMEQ (zero) */
11930 case 0x2e: /* FCMLT (zero) */
11931 case 0x6c: /* FCMGE (zero) */
11932 case 0x6d: /* FCMLE (zero) */
11933 if (size
== 3 && !is_q
) {
11934 unallocated_encoding(s
);
11937 handle_2misc_fcmp_zero(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
11939 case 0x7f: /* FSQRT */
11940 if (size
== 3 && !is_q
) {
11941 unallocated_encoding(s
);
11945 case 0x1a: /* FCVTNS */
11946 case 0x1b: /* FCVTMS */
11947 case 0x3a: /* FCVTPS */
11948 case 0x3b: /* FCVTZS */
11949 case 0x5a: /* FCVTNU */
11950 case 0x5b: /* FCVTMU */
11951 case 0x7a: /* FCVTPU */
11952 case 0x7b: /* FCVTZU */
11953 need_fpstatus
= true;
11955 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
11956 if (size
== 3 && !is_q
) {
11957 unallocated_encoding(s
);
11961 case 0x5c: /* FCVTAU */
11962 case 0x1c: /* FCVTAS */
11963 need_fpstatus
= true;
11965 rmode
= FPROUNDING_TIEAWAY
;
11966 if (size
== 3 && !is_q
) {
11967 unallocated_encoding(s
);
11971 case 0x3c: /* URECPE */
11973 unallocated_encoding(s
);
11977 case 0x3d: /* FRECPE */
11978 case 0x7d: /* FRSQRTE */
11979 if (size
== 3 && !is_q
) {
11980 unallocated_encoding(s
);
11983 if (!fp_access_check(s
)) {
11986 handle_2misc_reciprocal(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
11988 case 0x56: /* FCVTXN, FCVTXN2 */
11990 unallocated_encoding(s
);
11994 case 0x16: /* FCVTN, FCVTN2 */
11995 /* handle_2misc_narrow does a 2*size -> size operation, but these
11996 * instructions encode the source size rather than dest size.
11998 if (!fp_access_check(s
)) {
12001 handle_2misc_narrow(s
, false, opcode
, 0, is_q
, size
- 1, rn
, rd
);
12003 case 0x17: /* FCVTL, FCVTL2 */
12004 if (!fp_access_check(s
)) {
12007 handle_2misc_widening(s
, opcode
, is_q
, size
, rn
, rd
);
12009 case 0x18: /* FRINTN */
12010 case 0x19: /* FRINTM */
12011 case 0x38: /* FRINTP */
12012 case 0x39: /* FRINTZ */
12014 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
12016 case 0x59: /* FRINTX */
12017 case 0x79: /* FRINTI */
12018 need_fpstatus
= true;
12019 if (size
== 3 && !is_q
) {
12020 unallocated_encoding(s
);
12024 case 0x58: /* FRINTA */
12026 rmode
= FPROUNDING_TIEAWAY
;
12027 need_fpstatus
= true;
12028 if (size
== 3 && !is_q
) {
12029 unallocated_encoding(s
);
12033 case 0x7c: /* URSQRTE */
12035 unallocated_encoding(s
);
12038 need_fpstatus
= true;
12041 unallocated_encoding(s
);
12047 unallocated_encoding(s
);
12051 if (!fp_access_check(s
)) {
12055 if (need_fpstatus
|| need_rmode
) {
12056 tcg_fpstatus
= get_fpstatus_ptr(false);
12058 tcg_fpstatus
= NULL
;
12061 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
12062 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12069 if (u
&& size
== 0) { /* NOT */
12070 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_not
, 0);
12076 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_neg
, size
);
12083 /* All 64-bit element operations can be shared with scalar 2misc */
12086 /* Coverity claims (size == 3 && !is_q) has been eliminated
12087 * from all paths leading to here.
12089 tcg_debug_assert(is_q
);
12090 for (pass
= 0; pass
< 2; pass
++) {
12091 TCGv_i64 tcg_op
= tcg_temp_new_i64();
12092 TCGv_i64 tcg_res
= tcg_temp_new_i64();
12094 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
12096 handle_2misc_64(s
, opcode
, u
, tcg_res
, tcg_op
,
12097 tcg_rmode
, tcg_fpstatus
);
12099 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
12101 tcg_temp_free_i64(tcg_res
);
12102 tcg_temp_free_i64(tcg_op
);
12107 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
12108 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12109 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12112 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
12115 /* Special cases for 32 bit elements */
12117 case 0xa: /* CMLT */
12118 /* 32 bit integer comparison against zero, result is
12119 * test ? (2^32 - 1) : 0. We implement via setcond(test)
12122 cond
= TCG_COND_LT
;
12124 tcg_gen_setcondi_i32(cond
, tcg_res
, tcg_op
, 0);
12125 tcg_gen_neg_i32(tcg_res
, tcg_res
);
12127 case 0x8: /* CMGT, CMGE */
12128 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
12130 case 0x9: /* CMEQ, CMLE */
12131 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
12133 case 0x4: /* CLS */
12135 tcg_gen_clzi_i32(tcg_res
, tcg_op
, 32);
12137 tcg_gen_clrsb_i32(tcg_res
, tcg_op
);
12140 case 0x7: /* SQABS, SQNEG */
12142 gen_helper_neon_qneg_s32(tcg_res
, cpu_env
, tcg_op
);
12144 gen_helper_neon_qabs_s32(tcg_res
, cpu_env
, tcg_op
);
12147 case 0xb: /* ABS, NEG */
12149 tcg_gen_neg_i32(tcg_res
, tcg_op
);
12151 TCGv_i32 tcg_zero
= tcg_const_i32(0);
12152 tcg_gen_neg_i32(tcg_res
, tcg_op
);
12153 tcg_gen_movcond_i32(TCG_COND_GT
, tcg_res
, tcg_op
,
12154 tcg_zero
, tcg_op
, tcg_res
);
12155 tcg_temp_free_i32(tcg_zero
);
12158 case 0x2f: /* FABS */
12159 gen_helper_vfp_abss(tcg_res
, tcg_op
);
12161 case 0x6f: /* FNEG */
12162 gen_helper_vfp_negs(tcg_res
, tcg_op
);
12164 case 0x7f: /* FSQRT */
12165 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
12167 case 0x1a: /* FCVTNS */
12168 case 0x1b: /* FCVTMS */
12169 case 0x1c: /* FCVTAS */
12170 case 0x3a: /* FCVTPS */
12171 case 0x3b: /* FCVTZS */
12173 TCGv_i32 tcg_shift
= tcg_const_i32(0);
12174 gen_helper_vfp_tosls(tcg_res
, tcg_op
,
12175 tcg_shift
, tcg_fpstatus
);
12176 tcg_temp_free_i32(tcg_shift
);
12179 case 0x5a: /* FCVTNU */
12180 case 0x5b: /* FCVTMU */
12181 case 0x5c: /* FCVTAU */
12182 case 0x7a: /* FCVTPU */
12183 case 0x7b: /* FCVTZU */
12185 TCGv_i32 tcg_shift
= tcg_const_i32(0);
12186 gen_helper_vfp_touls(tcg_res
, tcg_op
,
12187 tcg_shift
, tcg_fpstatus
);
12188 tcg_temp_free_i32(tcg_shift
);
12191 case 0x18: /* FRINTN */
12192 case 0x19: /* FRINTM */
12193 case 0x38: /* FRINTP */
12194 case 0x39: /* FRINTZ */
12195 case 0x58: /* FRINTA */
12196 case 0x79: /* FRINTI */
12197 gen_helper_rints(tcg_res
, tcg_op
, tcg_fpstatus
);
12199 case 0x59: /* FRINTX */
12200 gen_helper_rints_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
12202 case 0x7c: /* URSQRTE */
12203 gen_helper_rsqrte_u32(tcg_res
, tcg_op
, tcg_fpstatus
);
12206 g_assert_not_reached();
12209 /* Use helpers for 8 and 16 bit elements */
12211 case 0x5: /* CNT, RBIT */
12212 /* For these two insns size is part of the opcode specifier
12213 * (handled earlier); they always operate on byte elements.
12216 gen_helper_neon_rbit_u8(tcg_res
, tcg_op
);
12218 gen_helper_neon_cnt_u8(tcg_res
, tcg_op
);
12221 case 0x7: /* SQABS, SQNEG */
12223 NeonGenOneOpEnvFn
*genfn
;
12224 static NeonGenOneOpEnvFn
* const fns
[2][2] = {
12225 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
12226 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
12228 genfn
= fns
[size
][u
];
12229 genfn(tcg_res
, cpu_env
, tcg_op
);
12232 case 0x8: /* CMGT, CMGE */
12233 case 0x9: /* CMEQ, CMLE */
12234 case 0xa: /* CMLT */
12236 static NeonGenTwoOpFn
* const fns
[3][2] = {
12237 { gen_helper_neon_cgt_s8
, gen_helper_neon_cgt_s16
},
12238 { gen_helper_neon_cge_s8
, gen_helper_neon_cge_s16
},
12239 { gen_helper_neon_ceq_u8
, gen_helper_neon_ceq_u16
},
12241 NeonGenTwoOpFn
*genfn
;
12244 TCGv_i32 tcg_zero
= tcg_const_i32(0);
12246 /* comp = index into [CMGT, CMGE, CMEQ, CMLE, CMLT] */
12247 comp
= (opcode
- 0x8) * 2 + u
;
12248 /* ...but LE, LT are implemented as reverse GE, GT */
12249 reverse
= (comp
> 2);
12253 genfn
= fns
[comp
][size
];
12255 genfn(tcg_res
, tcg_zero
, tcg_op
);
12257 genfn(tcg_res
, tcg_op
, tcg_zero
);
12259 tcg_temp_free_i32(tcg_zero
);
12262 case 0xb: /* ABS, NEG */
12264 TCGv_i32 tcg_zero
= tcg_const_i32(0);
12266 gen_helper_neon_sub_u16(tcg_res
, tcg_zero
, tcg_op
);
12268 gen_helper_neon_sub_u8(tcg_res
, tcg_zero
, tcg_op
);
12270 tcg_temp_free_i32(tcg_zero
);
12273 gen_helper_neon_abs_s16(tcg_res
, tcg_op
);
12275 gen_helper_neon_abs_s8(tcg_res
, tcg_op
);
12279 case 0x4: /* CLS, CLZ */
12282 gen_helper_neon_clz_u8(tcg_res
, tcg_op
);
12284 gen_helper_neon_clz_u16(tcg_res
, tcg_op
);
12288 gen_helper_neon_cls_s8(tcg_res
, tcg_op
);
12290 gen_helper_neon_cls_s16(tcg_res
, tcg_op
);
12295 g_assert_not_reached();
12299 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
12301 tcg_temp_free_i32(tcg_res
);
12302 tcg_temp_free_i32(tcg_op
);
12305 clear_vec_high(s
, is_q
, rd
);
12308 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12309 tcg_temp_free_i32(tcg_rmode
);
12311 if (need_fpstatus
) {
12312 tcg_temp_free_ptr(tcg_fpstatus
);
12316 /* AdvSIMD [scalar] two register miscellaneous (FP16)
12318 * 31 30 29 28 27 24 23 22 21 17 16 12 11 10 9 5 4 0
12319 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
12320 * | 0 | Q | U | S | 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 | Rn | Rd |
12321 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
12322 * mask: 1000 1111 0111 1110 0000 1100 0000 0000 0x8f7e 0c00
12323 * val: 0000 1110 0111 1000 0000 1000 0000 0000 0x0e78 0800
12325 * This actually covers two groups where scalar access is governed by
12326 * bit 28. A bunch of the instructions (float to integral) only exist
12327 * in the vector form and are un-allocated for the scalar decode. Also
12328 * in the scalar decode Q is always 1.
12330 static void disas_simd_two_reg_misc_fp16(DisasContext
*s
, uint32_t insn
)
12332 int fpop
, opcode
, a
, u
;
12336 bool only_in_vector
= false;
12339 TCGv_i32 tcg_rmode
= NULL
;
12340 TCGv_ptr tcg_fpstatus
= NULL
;
12341 bool need_rmode
= false;
12342 bool need_fpst
= true;
12345 if (!dc_isar_feature(aa64_fp16
, s
)) {
12346 unallocated_encoding(s
);
12350 rd
= extract32(insn
, 0, 5);
12351 rn
= extract32(insn
, 5, 5);
12353 a
= extract32(insn
, 23, 1);
12354 u
= extract32(insn
, 29, 1);
12355 is_scalar
= extract32(insn
, 28, 1);
12356 is_q
= extract32(insn
, 30, 1);
12358 opcode
= extract32(insn
, 12, 5);
12359 fpop
= deposit32(opcode
, 5, 1, a
);
12360 fpop
= deposit32(fpop
, 6, 1, u
);
12362 rd
= extract32(insn
, 0, 5);
12363 rn
= extract32(insn
, 5, 5);
12366 case 0x1d: /* SCVTF */
12367 case 0x5d: /* UCVTF */
12374 elements
= (is_q
? 8 : 4);
12377 if (!fp_access_check(s
)) {
12380 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !u
, 0, MO_16
);
12384 case 0x2c: /* FCMGT (zero) */
12385 case 0x2d: /* FCMEQ (zero) */
12386 case 0x2e: /* FCMLT (zero) */
12387 case 0x6c: /* FCMGE (zero) */
12388 case 0x6d: /* FCMLE (zero) */
12389 handle_2misc_fcmp_zero(s
, fpop
, is_scalar
, 0, is_q
, MO_16
, rn
, rd
);
12391 case 0x3d: /* FRECPE */
12392 case 0x3f: /* FRECPX */
12394 case 0x18: /* FRINTN */
12396 only_in_vector
= true;
12397 rmode
= FPROUNDING_TIEEVEN
;
12399 case 0x19: /* FRINTM */
12401 only_in_vector
= true;
12402 rmode
= FPROUNDING_NEGINF
;
12404 case 0x38: /* FRINTP */
12406 only_in_vector
= true;
12407 rmode
= FPROUNDING_POSINF
;
12409 case 0x39: /* FRINTZ */
12411 only_in_vector
= true;
12412 rmode
= FPROUNDING_ZERO
;
12414 case 0x58: /* FRINTA */
12416 only_in_vector
= true;
12417 rmode
= FPROUNDING_TIEAWAY
;
12419 case 0x59: /* FRINTX */
12420 case 0x79: /* FRINTI */
12421 only_in_vector
= true;
12422 /* current rounding mode */
12424 case 0x1a: /* FCVTNS */
12426 rmode
= FPROUNDING_TIEEVEN
;
12428 case 0x1b: /* FCVTMS */
12430 rmode
= FPROUNDING_NEGINF
;
12432 case 0x1c: /* FCVTAS */
12434 rmode
= FPROUNDING_TIEAWAY
;
12436 case 0x3a: /* FCVTPS */
12438 rmode
= FPROUNDING_POSINF
;
12440 case 0x3b: /* FCVTZS */
12442 rmode
= FPROUNDING_ZERO
;
12444 case 0x5a: /* FCVTNU */
12446 rmode
= FPROUNDING_TIEEVEN
;
12448 case 0x5b: /* FCVTMU */
12450 rmode
= FPROUNDING_NEGINF
;
12452 case 0x5c: /* FCVTAU */
12454 rmode
= FPROUNDING_TIEAWAY
;
12456 case 0x7a: /* FCVTPU */
12458 rmode
= FPROUNDING_POSINF
;
12460 case 0x7b: /* FCVTZU */
12462 rmode
= FPROUNDING_ZERO
;
12464 case 0x2f: /* FABS */
12465 case 0x6f: /* FNEG */
12468 case 0x7d: /* FRSQRTE */
12469 case 0x7f: /* FSQRT (vector) */
12472 fprintf(stderr
, "%s: insn %#04x fpop %#2x\n", __func__
, insn
, fpop
);
12473 g_assert_not_reached();
12477 /* Check additional constraints for the scalar encoding */
12480 unallocated_encoding(s
);
12483 /* FRINTxx is only in the vector form */
12484 if (only_in_vector
) {
12485 unallocated_encoding(s
);
12490 if (!fp_access_check(s
)) {
12494 if (need_rmode
|| need_fpst
) {
12495 tcg_fpstatus
= get_fpstatus_ptr(true);
12499 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
12500 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12504 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
12505 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12508 case 0x1a: /* FCVTNS */
12509 case 0x1b: /* FCVTMS */
12510 case 0x1c: /* FCVTAS */
12511 case 0x3a: /* FCVTPS */
12512 case 0x3b: /* FCVTZS */
12513 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12515 case 0x3d: /* FRECPE */
12516 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12518 case 0x3f: /* FRECPX */
12519 gen_helper_frecpx_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12521 case 0x5a: /* FCVTNU */
12522 case 0x5b: /* FCVTMU */
12523 case 0x5c: /* FCVTAU */
12524 case 0x7a: /* FCVTPU */
12525 case 0x7b: /* FCVTZU */
12526 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12528 case 0x6f: /* FNEG */
12529 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
12531 case 0x7d: /* FRSQRTE */
12532 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12535 g_assert_not_reached();
12538 /* limit any sign extension going on */
12539 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0xffff);
12540 write_fp_sreg(s
, rd
, tcg_res
);
12542 tcg_temp_free_i32(tcg_res
);
12543 tcg_temp_free_i32(tcg_op
);
12545 for (pass
= 0; pass
< (is_q
? 8 : 4); pass
++) {
12546 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12547 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12549 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_16
);
12552 case 0x1a: /* FCVTNS */
12553 case 0x1b: /* FCVTMS */
12554 case 0x1c: /* FCVTAS */
12555 case 0x3a: /* FCVTPS */
12556 case 0x3b: /* FCVTZS */
12557 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12559 case 0x3d: /* FRECPE */
12560 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12562 case 0x5a: /* FCVTNU */
12563 case 0x5b: /* FCVTMU */
12564 case 0x5c: /* FCVTAU */
12565 case 0x7a: /* FCVTPU */
12566 case 0x7b: /* FCVTZU */
12567 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12569 case 0x18: /* FRINTN */
12570 case 0x19: /* FRINTM */
12571 case 0x38: /* FRINTP */
12572 case 0x39: /* FRINTZ */
12573 case 0x58: /* FRINTA */
12574 case 0x79: /* FRINTI */
12575 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12577 case 0x59: /* FRINTX */
12578 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
12580 case 0x2f: /* FABS */
12581 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
12583 case 0x6f: /* FNEG */
12584 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
12586 case 0x7d: /* FRSQRTE */
12587 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12589 case 0x7f: /* FSQRT */
12590 gen_helper_sqrt_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12593 g_assert_not_reached();
12596 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
12598 tcg_temp_free_i32(tcg_res
);
12599 tcg_temp_free_i32(tcg_op
);
12602 clear_vec_high(s
, is_q
, rd
);
12606 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12607 tcg_temp_free_i32(tcg_rmode
);
12610 if (tcg_fpstatus
) {
12611 tcg_temp_free_ptr(tcg_fpstatus
);
12615 /* AdvSIMD scalar x indexed element
12616 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
12617 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
12618 * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
12619 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
12620 * AdvSIMD vector x indexed element
12621 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
12622 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
12623 * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
12624 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
12626 static void disas_simd_indexed(DisasContext
*s
, uint32_t insn
)
12628 /* This encoding has two kinds of instruction:
12629 * normal, where we perform elt x idxelt => elt for each
12630 * element in the vector
12631 * long, where we perform elt x idxelt and generate a result of
12632 * double the width of the input element
12633 * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
12635 bool is_scalar
= extract32(insn
, 28, 1);
12636 bool is_q
= extract32(insn
, 30, 1);
12637 bool u
= extract32(insn
, 29, 1);
12638 int size
= extract32(insn
, 22, 2);
12639 int l
= extract32(insn
, 21, 1);
12640 int m
= extract32(insn
, 20, 1);
12641 /* Note that the Rm field here is only 4 bits, not 5 as it usually is */
12642 int rm
= extract32(insn
, 16, 4);
12643 int opcode
= extract32(insn
, 12, 4);
12644 int h
= extract32(insn
, 11, 1);
12645 int rn
= extract32(insn
, 5, 5);
12646 int rd
= extract32(insn
, 0, 5);
12647 bool is_long
= false;
12649 bool is_fp16
= false;
12653 switch (16 * u
+ opcode
) {
12654 case 0x08: /* MUL */
12655 case 0x10: /* MLA */
12656 case 0x14: /* MLS */
12658 unallocated_encoding(s
);
12662 case 0x02: /* SMLAL, SMLAL2 */
12663 case 0x12: /* UMLAL, UMLAL2 */
12664 case 0x06: /* SMLSL, SMLSL2 */
12665 case 0x16: /* UMLSL, UMLSL2 */
12666 case 0x0a: /* SMULL, SMULL2 */
12667 case 0x1a: /* UMULL, UMULL2 */
12669 unallocated_encoding(s
);
12674 case 0x03: /* SQDMLAL, SQDMLAL2 */
12675 case 0x07: /* SQDMLSL, SQDMLSL2 */
12676 case 0x0b: /* SQDMULL, SQDMULL2 */
12679 case 0x0c: /* SQDMULH */
12680 case 0x0d: /* SQRDMULH */
12682 case 0x01: /* FMLA */
12683 case 0x05: /* FMLS */
12684 case 0x09: /* FMUL */
12685 case 0x19: /* FMULX */
12688 case 0x1d: /* SQRDMLAH */
12689 case 0x1f: /* SQRDMLSH */
12690 if (!dc_isar_feature(aa64_rdm
, s
)) {
12691 unallocated_encoding(s
);
12695 case 0x0e: /* SDOT */
12696 case 0x1e: /* UDOT */
12697 if (is_scalar
|| size
!= MO_32
|| !dc_isar_feature(aa64_dp
, s
)) {
12698 unallocated_encoding(s
);
12702 case 0x11: /* FCMLA #0 */
12703 case 0x13: /* FCMLA #90 */
12704 case 0x15: /* FCMLA #180 */
12705 case 0x17: /* FCMLA #270 */
12706 if (is_scalar
|| !dc_isar_feature(aa64_fcma
, s
)) {
12707 unallocated_encoding(s
);
12713 unallocated_encoding(s
);
12718 case 1: /* normal fp */
12719 /* convert insn encoded size to TCGMemOp size */
12721 case 0: /* half-precision */
12725 case MO_32
: /* single precision */
12726 case MO_64
: /* double precision */
12729 unallocated_encoding(s
);
12734 case 2: /* complex fp */
12735 /* Each indexable element is a complex pair. */
12740 unallocated_encoding(s
);
12748 unallocated_encoding(s
);
12753 default: /* integer */
12757 unallocated_encoding(s
);
12762 if (is_fp16
&& !dc_isar_feature(aa64_fp16
, s
)) {
12763 unallocated_encoding(s
);
12767 /* Given TCGMemOp size, adjust register and indexing. */
12770 index
= h
<< 2 | l
<< 1 | m
;
12773 index
= h
<< 1 | l
;
12778 unallocated_encoding(s
);
12785 g_assert_not_reached();
12788 if (!fp_access_check(s
)) {
12793 fpst
= get_fpstatus_ptr(is_fp16
);
12798 switch (16 * u
+ opcode
) {
12799 case 0x0e: /* SDOT */
12800 case 0x1e: /* UDOT */
12801 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, index
,
12802 u
? gen_helper_gvec_udot_idx_b
12803 : gen_helper_gvec_sdot_idx_b
);
12805 case 0x11: /* FCMLA #0 */
12806 case 0x13: /* FCMLA #90 */
12807 case 0x15: /* FCMLA #180 */
12808 case 0x17: /* FCMLA #270 */
12810 int rot
= extract32(insn
, 13, 2);
12811 int data
= (index
<< 2) | rot
;
12812 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
12813 vec_full_reg_offset(s
, rn
),
12814 vec_full_reg_offset(s
, rm
), fpst
,
12815 is_q
? 16 : 8, vec_full_reg_size(s
), data
,
12817 ? gen_helper_gvec_fcmlas_idx
12818 : gen_helper_gvec_fcmlah_idx
);
12819 tcg_temp_free_ptr(fpst
);
12825 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
12828 assert(is_fp
&& is_q
&& !is_long
);
12830 read_vec_element(s
, tcg_idx
, rm
, index
, MO_64
);
12832 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
12833 TCGv_i64 tcg_op
= tcg_temp_new_i64();
12834 TCGv_i64 tcg_res
= tcg_temp_new_i64();
12836 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
12838 switch (16 * u
+ opcode
) {
12839 case 0x05: /* FMLS */
12840 /* As usual for ARM, separate negation for fused multiply-add */
12841 gen_helper_vfp_negd(tcg_op
, tcg_op
);
12843 case 0x01: /* FMLA */
12844 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
12845 gen_helper_vfp_muladdd(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
12847 case 0x09: /* FMUL */
12848 gen_helper_vfp_muld(tcg_res
, tcg_op
, tcg_idx
, fpst
);
12850 case 0x19: /* FMULX */
12851 gen_helper_vfp_mulxd(tcg_res
, tcg_op
, tcg_idx
, fpst
);
12854 g_assert_not_reached();
12857 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
12858 tcg_temp_free_i64(tcg_op
);
12859 tcg_temp_free_i64(tcg_res
);
12862 tcg_temp_free_i64(tcg_idx
);
12863 clear_vec_high(s
, !is_scalar
, rd
);
12864 } else if (!is_long
) {
12865 /* 32 bit floating point, or 16 or 32 bit integer.
12866 * For the 16 bit scalar case we use the usual Neon helpers and
12867 * rely on the fact that 0 op 0 == 0 with no side effects.
12869 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
12870 int pass
, maxpasses
;
12875 maxpasses
= is_q
? 4 : 2;
12878 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
12880 if (size
== 1 && !is_scalar
) {
12881 /* The simplest way to handle the 16x16 indexed ops is to duplicate
12882 * the index into both halves of the 32 bit tcg_idx and then use
12883 * the usual Neon helpers.
12885 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
12888 for (pass
= 0; pass
< maxpasses
; pass
++) {
12889 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12890 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12892 read_vec_element_i32(s
, tcg_op
, rn
, pass
, is_scalar
? size
: MO_32
);
12894 switch (16 * u
+ opcode
) {
12895 case 0x08: /* MUL */
12896 case 0x10: /* MLA */
12897 case 0x14: /* MLS */
12899 static NeonGenTwoOpFn
* const fns
[2][2] = {
12900 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
12901 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
12903 NeonGenTwoOpFn
*genfn
;
12904 bool is_sub
= opcode
== 0x4;
12907 gen_helper_neon_mul_u16(tcg_res
, tcg_op
, tcg_idx
);
12909 tcg_gen_mul_i32(tcg_res
, tcg_op
, tcg_idx
);
12911 if (opcode
== 0x8) {
12914 read_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
12915 genfn
= fns
[size
- 1][is_sub
];
12916 genfn(tcg_res
, tcg_op
, tcg_res
);
12919 case 0x05: /* FMLS */
12920 case 0x01: /* FMLA */
12921 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
12922 is_scalar
? size
: MO_32
);
12925 if (opcode
== 0x5) {
12926 /* As usual for ARM, separate negation for fused
12928 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80008000);
12931 gen_helper_advsimd_muladdh(tcg_res
, tcg_op
, tcg_idx
,
12934 gen_helper_advsimd_muladd2h(tcg_res
, tcg_op
, tcg_idx
,
12939 if (opcode
== 0x5) {
12940 /* As usual for ARM, separate negation for
12941 * fused multiply-add */
12942 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80000000);
12944 gen_helper_vfp_muladds(tcg_res
, tcg_op
, tcg_idx
,
12948 g_assert_not_reached();
12951 case 0x09: /* FMUL */
12955 gen_helper_advsimd_mulh(tcg_res
, tcg_op
,
12958 gen_helper_advsimd_mul2h(tcg_res
, tcg_op
,
12963 gen_helper_vfp_muls(tcg_res
, tcg_op
, tcg_idx
, fpst
);
12966 g_assert_not_reached();
12969 case 0x19: /* FMULX */
12973 gen_helper_advsimd_mulxh(tcg_res
, tcg_op
,
12976 gen_helper_advsimd_mulx2h(tcg_res
, tcg_op
,
12981 gen_helper_vfp_mulxs(tcg_res
, tcg_op
, tcg_idx
, fpst
);
12984 g_assert_not_reached();
12987 case 0x0c: /* SQDMULH */
12989 gen_helper_neon_qdmulh_s16(tcg_res
, cpu_env
,
12992 gen_helper_neon_qdmulh_s32(tcg_res
, cpu_env
,
12996 case 0x0d: /* SQRDMULH */
12998 gen_helper_neon_qrdmulh_s16(tcg_res
, cpu_env
,
13001 gen_helper_neon_qrdmulh_s32(tcg_res
, cpu_env
,
13005 case 0x1d: /* SQRDMLAH */
13006 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13007 is_scalar
? size
: MO_32
);
13009 gen_helper_neon_qrdmlah_s16(tcg_res
, cpu_env
,
13010 tcg_op
, tcg_idx
, tcg_res
);
13012 gen_helper_neon_qrdmlah_s32(tcg_res
, cpu_env
,
13013 tcg_op
, tcg_idx
, tcg_res
);
13016 case 0x1f: /* SQRDMLSH */
13017 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13018 is_scalar
? size
: MO_32
);
13020 gen_helper_neon_qrdmlsh_s16(tcg_res
, cpu_env
,
13021 tcg_op
, tcg_idx
, tcg_res
);
13023 gen_helper_neon_qrdmlsh_s32(tcg_res
, cpu_env
,
13024 tcg_op
, tcg_idx
, tcg_res
);
13028 g_assert_not_reached();
13032 write_fp_sreg(s
, rd
, tcg_res
);
13034 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
13037 tcg_temp_free_i32(tcg_op
);
13038 tcg_temp_free_i32(tcg_res
);
13041 tcg_temp_free_i32(tcg_idx
);
13042 clear_vec_high(s
, is_q
, rd
);
13044 /* long ops: 16x16->32 or 32x32->64 */
13045 TCGv_i64 tcg_res
[2];
13047 bool satop
= extract32(opcode
, 0, 1);
13048 TCGMemOp memop
= MO_32
;
13055 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
13057 read_vec_element(s
, tcg_idx
, rm
, index
, memop
);
13059 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13060 TCGv_i64 tcg_op
= tcg_temp_new_i64();
13061 TCGv_i64 tcg_passres
;
13067 passelt
= pass
+ (is_q
* 2);
13070 read_vec_element(s
, tcg_op
, rn
, passelt
, memop
);
13072 tcg_res
[pass
] = tcg_temp_new_i64();
13074 if (opcode
== 0xa || opcode
== 0xb) {
13075 /* Non-accumulating ops */
13076 tcg_passres
= tcg_res
[pass
];
13078 tcg_passres
= tcg_temp_new_i64();
13081 tcg_gen_mul_i64(tcg_passres
, tcg_op
, tcg_idx
);
13082 tcg_temp_free_i64(tcg_op
);
13085 /* saturating, doubling */
13086 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
13087 tcg_passres
, tcg_passres
);
13090 if (opcode
== 0xa || opcode
== 0xb) {
13094 /* Accumulating op: handle accumulate step */
13095 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13098 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13099 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
13101 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13102 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
13104 case 0x7: /* SQDMLSL, SQDMLSL2 */
13105 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
13107 case 0x3: /* SQDMLAL, SQDMLAL2 */
13108 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
13113 g_assert_not_reached();
13115 tcg_temp_free_i64(tcg_passres
);
13117 tcg_temp_free_i64(tcg_idx
);
13119 clear_vec_high(s
, !is_scalar
, rd
);
13121 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
13124 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
13127 /* The simplest way to handle the 16x16 indexed ops is to
13128 * duplicate the index into both halves of the 32 bit tcg_idx
13129 * and then use the usual Neon helpers.
13131 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
13134 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13135 TCGv_i32 tcg_op
= tcg_temp_new_i32();
13136 TCGv_i64 tcg_passres
;
13139 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
13141 read_vec_element_i32(s
, tcg_op
, rn
,
13142 pass
+ (is_q
* 2), MO_32
);
13145 tcg_res
[pass
] = tcg_temp_new_i64();
13147 if (opcode
== 0xa || opcode
== 0xb) {
13148 /* Non-accumulating ops */
13149 tcg_passres
= tcg_res
[pass
];
13151 tcg_passres
= tcg_temp_new_i64();
13154 if (memop
& MO_SIGN
) {
13155 gen_helper_neon_mull_s16(tcg_passres
, tcg_op
, tcg_idx
);
13157 gen_helper_neon_mull_u16(tcg_passres
, tcg_op
, tcg_idx
);
13160 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
13161 tcg_passres
, tcg_passres
);
13163 tcg_temp_free_i32(tcg_op
);
13165 if (opcode
== 0xa || opcode
== 0xb) {
13169 /* Accumulating op: handle accumulate step */
13170 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13173 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13174 gen_helper_neon_addl_u32(tcg_res
[pass
], tcg_res
[pass
],
13177 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13178 gen_helper_neon_subl_u32(tcg_res
[pass
], tcg_res
[pass
],
13181 case 0x7: /* SQDMLSL, SQDMLSL2 */
13182 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
13184 case 0x3: /* SQDMLAL, SQDMLAL2 */
13185 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
13190 g_assert_not_reached();
13192 tcg_temp_free_i64(tcg_passres
);
13194 tcg_temp_free_i32(tcg_idx
);
13197 tcg_gen_ext32u_i64(tcg_res
[0], tcg_res
[0]);
13202 tcg_res
[1] = tcg_const_i64(0);
13205 for (pass
= 0; pass
< 2; pass
++) {
13206 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13207 tcg_temp_free_i64(tcg_res
[pass
]);
13212 tcg_temp_free_ptr(fpst
);
13217 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
13218 * +-----------------+------+-----------+--------+-----+------+------+
13219 * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
13220 * +-----------------+------+-----------+--------+-----+------+------+
13222 static void disas_crypto_aes(DisasContext
*s
, uint32_t insn
)
13224 int size
= extract32(insn
, 22, 2);
13225 int opcode
= extract32(insn
, 12, 5);
13226 int rn
= extract32(insn
, 5, 5);
13227 int rd
= extract32(insn
, 0, 5);
13229 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
;
13230 TCGv_i32 tcg_decrypt
;
13231 CryptoThreeOpIntFn
*genfn
;
13233 if (!dc_isar_feature(aa64_aes
, s
) || size
!= 0) {
13234 unallocated_encoding(s
);
13239 case 0x4: /* AESE */
13241 genfn
= gen_helper_crypto_aese
;
13243 case 0x6: /* AESMC */
13245 genfn
= gen_helper_crypto_aesmc
;
13247 case 0x5: /* AESD */
13249 genfn
= gen_helper_crypto_aese
;
13251 case 0x7: /* AESIMC */
13253 genfn
= gen_helper_crypto_aesmc
;
13256 unallocated_encoding(s
);
13260 if (!fp_access_check(s
)) {
13264 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13265 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13266 tcg_decrypt
= tcg_const_i32(decrypt
);
13268 genfn(tcg_rd_ptr
, tcg_rn_ptr
, tcg_decrypt
);
13270 tcg_temp_free_ptr(tcg_rd_ptr
);
13271 tcg_temp_free_ptr(tcg_rn_ptr
);
13272 tcg_temp_free_i32(tcg_decrypt
);
13275 /* Crypto three-reg SHA
13276 * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
13277 * +-----------------+------+---+------+---+--------+-----+------+------+
13278 * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
13279 * +-----------------+------+---+------+---+--------+-----+------+------+
13281 static void disas_crypto_three_reg_sha(DisasContext
*s
, uint32_t insn
)
13283 int size
= extract32(insn
, 22, 2);
13284 int opcode
= extract32(insn
, 12, 3);
13285 int rm
= extract32(insn
, 16, 5);
13286 int rn
= extract32(insn
, 5, 5);
13287 int rd
= extract32(insn
, 0, 5);
13288 CryptoThreeOpFn
*genfn
;
13289 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
;
13293 unallocated_encoding(s
);
13298 case 0: /* SHA1C */
13299 case 1: /* SHA1P */
13300 case 2: /* SHA1M */
13301 case 3: /* SHA1SU0 */
13303 feature
= dc_isar_feature(aa64_sha1
, s
);
13305 case 4: /* SHA256H */
13306 genfn
= gen_helper_crypto_sha256h
;
13307 feature
= dc_isar_feature(aa64_sha256
, s
);
13309 case 5: /* SHA256H2 */
13310 genfn
= gen_helper_crypto_sha256h2
;
13311 feature
= dc_isar_feature(aa64_sha256
, s
);
13313 case 6: /* SHA256SU1 */
13314 genfn
= gen_helper_crypto_sha256su1
;
13315 feature
= dc_isar_feature(aa64_sha256
, s
);
13318 unallocated_encoding(s
);
13323 unallocated_encoding(s
);
13327 if (!fp_access_check(s
)) {
13331 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13332 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13333 tcg_rm_ptr
= vec_full_reg_ptr(s
, rm
);
13336 genfn(tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
);
13338 TCGv_i32 tcg_opcode
= tcg_const_i32(opcode
);
13340 gen_helper_crypto_sha1_3reg(tcg_rd_ptr
, tcg_rn_ptr
,
13341 tcg_rm_ptr
, tcg_opcode
);
13342 tcg_temp_free_i32(tcg_opcode
);
13345 tcg_temp_free_ptr(tcg_rd_ptr
);
13346 tcg_temp_free_ptr(tcg_rn_ptr
);
13347 tcg_temp_free_ptr(tcg_rm_ptr
);
13350 /* Crypto two-reg SHA
13351 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
13352 * +-----------------+------+-----------+--------+-----+------+------+
13353 * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
13354 * +-----------------+------+-----------+--------+-----+------+------+
13356 static void disas_crypto_two_reg_sha(DisasContext
*s
, uint32_t insn
)
13358 int size
= extract32(insn
, 22, 2);
13359 int opcode
= extract32(insn
, 12, 5);
13360 int rn
= extract32(insn
, 5, 5);
13361 int rd
= extract32(insn
, 0, 5);
13362 CryptoTwoOpFn
*genfn
;
13364 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
;
13367 unallocated_encoding(s
);
13372 case 0: /* SHA1H */
13373 feature
= dc_isar_feature(aa64_sha1
, s
);
13374 genfn
= gen_helper_crypto_sha1h
;
13376 case 1: /* SHA1SU1 */
13377 feature
= dc_isar_feature(aa64_sha1
, s
);
13378 genfn
= gen_helper_crypto_sha1su1
;
13380 case 2: /* SHA256SU0 */
13381 feature
= dc_isar_feature(aa64_sha256
, s
);
13382 genfn
= gen_helper_crypto_sha256su0
;
13385 unallocated_encoding(s
);
13390 unallocated_encoding(s
);
13394 if (!fp_access_check(s
)) {
13398 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13399 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13401 genfn(tcg_rd_ptr
, tcg_rn_ptr
);
13403 tcg_temp_free_ptr(tcg_rd_ptr
);
13404 tcg_temp_free_ptr(tcg_rn_ptr
);
13407 /* Crypto three-reg SHA512
13408 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
13409 * +-----------------------+------+---+---+-----+--------+------+------+
13410 * | 1 1 0 0 1 1 1 0 0 1 1 | Rm | 1 | O | 0 0 | opcode | Rn | Rd |
13411 * +-----------------------+------+---+---+-----+--------+------+------+
13413 static void disas_crypto_three_reg_sha512(DisasContext
*s
, uint32_t insn
)
13415 int opcode
= extract32(insn
, 10, 2);
13416 int o
= extract32(insn
, 14, 1);
13417 int rm
= extract32(insn
, 16, 5);
13418 int rn
= extract32(insn
, 5, 5);
13419 int rd
= extract32(insn
, 0, 5);
13421 CryptoThreeOpFn
*genfn
;
13425 case 0: /* SHA512H */
13426 feature
= dc_isar_feature(aa64_sha512
, s
);
13427 genfn
= gen_helper_crypto_sha512h
;
13429 case 1: /* SHA512H2 */
13430 feature
= dc_isar_feature(aa64_sha512
, s
);
13431 genfn
= gen_helper_crypto_sha512h2
;
13433 case 2: /* SHA512SU1 */
13434 feature
= dc_isar_feature(aa64_sha512
, s
);
13435 genfn
= gen_helper_crypto_sha512su1
;
13438 feature
= dc_isar_feature(aa64_sha3
, s
);
13444 case 0: /* SM3PARTW1 */
13445 feature
= dc_isar_feature(aa64_sm3
, s
);
13446 genfn
= gen_helper_crypto_sm3partw1
;
13448 case 1: /* SM3PARTW2 */
13449 feature
= dc_isar_feature(aa64_sm3
, s
);
13450 genfn
= gen_helper_crypto_sm3partw2
;
13452 case 2: /* SM4EKEY */
13453 feature
= dc_isar_feature(aa64_sm4
, s
);
13454 genfn
= gen_helper_crypto_sm4ekey
;
13457 unallocated_encoding(s
);
13463 unallocated_encoding(s
);
13467 if (!fp_access_check(s
)) {
13472 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
;
13474 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13475 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13476 tcg_rm_ptr
= vec_full_reg_ptr(s
, rm
);
13478 genfn(tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
);
13480 tcg_temp_free_ptr(tcg_rd_ptr
);
13481 tcg_temp_free_ptr(tcg_rn_ptr
);
13482 tcg_temp_free_ptr(tcg_rm_ptr
);
13484 TCGv_i64 tcg_op1
, tcg_op2
, tcg_res
[2];
13487 tcg_op1
= tcg_temp_new_i64();
13488 tcg_op2
= tcg_temp_new_i64();
13489 tcg_res
[0] = tcg_temp_new_i64();
13490 tcg_res
[1] = tcg_temp_new_i64();
13492 for (pass
= 0; pass
< 2; pass
++) {
13493 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
13494 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
13496 tcg_gen_rotli_i64(tcg_res
[pass
], tcg_op2
, 1);
13497 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
13499 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
13500 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
13502 tcg_temp_free_i64(tcg_op1
);
13503 tcg_temp_free_i64(tcg_op2
);
13504 tcg_temp_free_i64(tcg_res
[0]);
13505 tcg_temp_free_i64(tcg_res
[1]);
13509 /* Crypto two-reg SHA512
13510 * 31 12 11 10 9 5 4 0
13511 * +-----------------------------------------+--------+------+------+
13512 * | 1 1 0 0 1 1 1 0 1 1 0 0 0 0 0 0 1 0 0 0 | opcode | Rn | Rd |
13513 * +-----------------------------------------+--------+------+------+
13515 static void disas_crypto_two_reg_sha512(DisasContext
*s
, uint32_t insn
)
13517 int opcode
= extract32(insn
, 10, 2);
13518 int rn
= extract32(insn
, 5, 5);
13519 int rd
= extract32(insn
, 0, 5);
13520 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
;
13522 CryptoTwoOpFn
*genfn
;
13525 case 0: /* SHA512SU0 */
13526 feature
= dc_isar_feature(aa64_sha512
, s
);
13527 genfn
= gen_helper_crypto_sha512su0
;
13530 feature
= dc_isar_feature(aa64_sm4
, s
);
13531 genfn
= gen_helper_crypto_sm4e
;
13534 unallocated_encoding(s
);
13539 unallocated_encoding(s
);
13543 if (!fp_access_check(s
)) {
13547 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13548 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13550 genfn(tcg_rd_ptr
, tcg_rn_ptr
);
13552 tcg_temp_free_ptr(tcg_rd_ptr
);
13553 tcg_temp_free_ptr(tcg_rn_ptr
);
13556 /* Crypto four-register
13557 * 31 23 22 21 20 16 15 14 10 9 5 4 0
13558 * +-------------------+-----+------+---+------+------+------+
13559 * | 1 1 0 0 1 1 1 0 0 | Op0 | Rm | 0 | Ra | Rn | Rd |
13560 * +-------------------+-----+------+---+------+------+------+
13562 static void disas_crypto_four_reg(DisasContext
*s
, uint32_t insn
)
13564 int op0
= extract32(insn
, 21, 2);
13565 int rm
= extract32(insn
, 16, 5);
13566 int ra
= extract32(insn
, 10, 5);
13567 int rn
= extract32(insn
, 5, 5);
13568 int rd
= extract32(insn
, 0, 5);
13574 feature
= dc_isar_feature(aa64_sha3
, s
);
13576 case 2: /* SM3SS1 */
13577 feature
= dc_isar_feature(aa64_sm3
, s
);
13580 unallocated_encoding(s
);
13585 unallocated_encoding(s
);
13589 if (!fp_access_check(s
)) {
13594 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
[2];
13597 tcg_op1
= tcg_temp_new_i64();
13598 tcg_op2
= tcg_temp_new_i64();
13599 tcg_op3
= tcg_temp_new_i64();
13600 tcg_res
[0] = tcg_temp_new_i64();
13601 tcg_res
[1] = tcg_temp_new_i64();
13603 for (pass
= 0; pass
< 2; pass
++) {
13604 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
13605 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
13606 read_vec_element(s
, tcg_op3
, ra
, pass
, MO_64
);
13610 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
13613 tcg_gen_andc_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
13615 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
13617 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
13618 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
13620 tcg_temp_free_i64(tcg_op1
);
13621 tcg_temp_free_i64(tcg_op2
);
13622 tcg_temp_free_i64(tcg_op3
);
13623 tcg_temp_free_i64(tcg_res
[0]);
13624 tcg_temp_free_i64(tcg_res
[1]);
13626 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
, tcg_zero
;
13628 tcg_op1
= tcg_temp_new_i32();
13629 tcg_op2
= tcg_temp_new_i32();
13630 tcg_op3
= tcg_temp_new_i32();
13631 tcg_res
= tcg_temp_new_i32();
13632 tcg_zero
= tcg_const_i32(0);
13634 read_vec_element_i32(s
, tcg_op1
, rn
, 3, MO_32
);
13635 read_vec_element_i32(s
, tcg_op2
, rm
, 3, MO_32
);
13636 read_vec_element_i32(s
, tcg_op3
, ra
, 3, MO_32
);
13638 tcg_gen_rotri_i32(tcg_res
, tcg_op1
, 20);
13639 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op2
);
13640 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op3
);
13641 tcg_gen_rotri_i32(tcg_res
, tcg_res
, 25);
13643 write_vec_element_i32(s
, tcg_zero
, rd
, 0, MO_32
);
13644 write_vec_element_i32(s
, tcg_zero
, rd
, 1, MO_32
);
13645 write_vec_element_i32(s
, tcg_zero
, rd
, 2, MO_32
);
13646 write_vec_element_i32(s
, tcg_res
, rd
, 3, MO_32
);
13648 tcg_temp_free_i32(tcg_op1
);
13649 tcg_temp_free_i32(tcg_op2
);
13650 tcg_temp_free_i32(tcg_op3
);
13651 tcg_temp_free_i32(tcg_res
);
13652 tcg_temp_free_i32(tcg_zero
);
13657 * 31 21 20 16 15 10 9 5 4 0
13658 * +-----------------------+------+--------+------+------+
13659 * | 1 1 0 0 1 1 1 0 1 0 0 | Rm | imm6 | Rn | Rd |
13660 * +-----------------------+------+--------+------+------+
13662 static void disas_crypto_xar(DisasContext
*s
, uint32_t insn
)
13664 int rm
= extract32(insn
, 16, 5);
13665 int imm6
= extract32(insn
, 10, 6);
13666 int rn
= extract32(insn
, 5, 5);
13667 int rd
= extract32(insn
, 0, 5);
13668 TCGv_i64 tcg_op1
, tcg_op2
, tcg_res
[2];
13671 if (!dc_isar_feature(aa64_sha3
, s
)) {
13672 unallocated_encoding(s
);
13676 if (!fp_access_check(s
)) {
13680 tcg_op1
= tcg_temp_new_i64();
13681 tcg_op2
= tcg_temp_new_i64();
13682 tcg_res
[0] = tcg_temp_new_i64();
13683 tcg_res
[1] = tcg_temp_new_i64();
13685 for (pass
= 0; pass
< 2; pass
++) {
13686 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
13687 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
13689 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
13690 tcg_gen_rotri_i64(tcg_res
[pass
], tcg_res
[pass
], imm6
);
13692 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
13693 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
13695 tcg_temp_free_i64(tcg_op1
);
13696 tcg_temp_free_i64(tcg_op2
);
13697 tcg_temp_free_i64(tcg_res
[0]);
13698 tcg_temp_free_i64(tcg_res
[1]);
13701 /* Crypto three-reg imm2
13702 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
13703 * +-----------------------+------+-----+------+--------+------+------+
13704 * | 1 1 0 0 1 1 1 0 0 1 0 | Rm | 1 0 | imm2 | opcode | Rn | Rd |
13705 * +-----------------------+------+-----+------+--------+------+------+
13707 static void disas_crypto_three_reg_imm2(DisasContext
*s
, uint32_t insn
)
13709 int opcode
= extract32(insn
, 10, 2);
13710 int imm2
= extract32(insn
, 12, 2);
13711 int rm
= extract32(insn
, 16, 5);
13712 int rn
= extract32(insn
, 5, 5);
13713 int rd
= extract32(insn
, 0, 5);
13714 TCGv_ptr tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
;
13715 TCGv_i32 tcg_imm2
, tcg_opcode
;
13717 if (!dc_isar_feature(aa64_sm3
, s
)) {
13718 unallocated_encoding(s
);
13722 if (!fp_access_check(s
)) {
13726 tcg_rd_ptr
= vec_full_reg_ptr(s
, rd
);
13727 tcg_rn_ptr
= vec_full_reg_ptr(s
, rn
);
13728 tcg_rm_ptr
= vec_full_reg_ptr(s
, rm
);
13729 tcg_imm2
= tcg_const_i32(imm2
);
13730 tcg_opcode
= tcg_const_i32(opcode
);
13732 gen_helper_crypto_sm3tt(tcg_rd_ptr
, tcg_rn_ptr
, tcg_rm_ptr
, tcg_imm2
,
13735 tcg_temp_free_ptr(tcg_rd_ptr
);
13736 tcg_temp_free_ptr(tcg_rn_ptr
);
13737 tcg_temp_free_ptr(tcg_rm_ptr
);
13738 tcg_temp_free_i32(tcg_imm2
);
13739 tcg_temp_free_i32(tcg_opcode
);
13742 /* C3.6 Data processing - SIMD, inc Crypto
13744 * As the decode gets a little complex we are using a table based
13745 * approach for this part of the decode.
13747 static const AArch64DecodeTable data_proc_simd
[] = {
13748 /* pattern , mask , fn */
13749 { 0x0e200400, 0x9f200400, disas_simd_three_reg_same
},
13750 { 0x0e008400, 0x9f208400, disas_simd_three_reg_same_extra
},
13751 { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff
},
13752 { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc
},
13753 { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes
},
13754 { 0x0e000400, 0x9fe08400, disas_simd_copy
},
13755 { 0x0f000000, 0x9f000400, disas_simd_indexed
}, /* vector indexed */
13756 /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
13757 { 0x0f000400, 0x9ff80400, disas_simd_mod_imm
},
13758 { 0x0f000400, 0x9f800400, disas_simd_shift_imm
},
13759 { 0x0e000000, 0xbf208c00, disas_simd_tb
},
13760 { 0x0e000800, 0xbf208c00, disas_simd_zip_trn
},
13761 { 0x2e000000, 0xbf208400, disas_simd_ext
},
13762 { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same
},
13763 { 0x5e008400, 0xdf208400, disas_simd_scalar_three_reg_same_extra
},
13764 { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff
},
13765 { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc
},
13766 { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise
},
13767 { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy
},
13768 { 0x5f000000, 0xdf000400, disas_simd_indexed
}, /* scalar indexed */
13769 { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm
},
13770 { 0x4e280800, 0xff3e0c00, disas_crypto_aes
},
13771 { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha
},
13772 { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha
},
13773 { 0xce608000, 0xffe0b000, disas_crypto_three_reg_sha512
},
13774 { 0xcec08000, 0xfffff000, disas_crypto_two_reg_sha512
},
13775 { 0xce000000, 0xff808000, disas_crypto_four_reg
},
13776 { 0xce800000, 0xffe00000, disas_crypto_xar
},
13777 { 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2
},
13778 { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16
},
13779 { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16
},
13780 { 0x5e400400, 0xdf60c400, disas_simd_scalar_three_reg_same_fp16
},
13781 { 0x00000000, 0x00000000, NULL
}
13784 static void disas_data_proc_simd(DisasContext
*s
, uint32_t insn
)
13786 /* Note that this is called with all non-FP cases from
13787 * table C3-6 so it must UNDEF for entries not specifically
13788 * allocated to instructions in that table.
13790 AArch64DecodeFn
*fn
= lookup_disas_fn(&data_proc_simd
[0], insn
);
13794 unallocated_encoding(s
);
13798 /* C3.6 Data processing - SIMD and floating point */
13799 static void disas_data_proc_simd_fp(DisasContext
*s
, uint32_t insn
)
13801 if (extract32(insn
, 28, 1) == 1 && extract32(insn
, 30, 1) == 0) {
13802 disas_data_proc_fp(s
, insn
);
13804 /* SIMD, including crypto */
13805 disas_data_proc_simd(s
, insn
);
13811 * @env: The cpu environment
13812 * @s: The DisasContext
13814 * Return true if the page is guarded.
13816 static bool is_guarded_page(CPUARMState
*env
, DisasContext
*s
)
13818 #ifdef CONFIG_USER_ONLY
13819 return false; /* FIXME */
13821 uint64_t addr
= s
->base
.pc_first
;
13822 int mmu_idx
= arm_to_core_mmu_idx(s
->mmu_idx
);
13823 unsigned int index
= tlb_index(env
, mmu_idx
, addr
);
13824 CPUTLBEntry
*entry
= tlb_entry(env
, mmu_idx
, addr
);
13827 * We test this immediately after reading an insn, which means
13828 * that any normal page must be in the TLB. The only exception
13829 * would be for executing from flash or device memory, which
13830 * does not retain the TLB entry.
13832 * FIXME: Assume false for those, for now. We could use
13833 * arm_cpu_get_phys_page_attrs_debug to re-read the page
13834 * table entry even for that case.
13836 return (tlb_hit(entry
->addr_code
, addr
) &&
13837 env
->iotlb
[mmu_idx
][index
].attrs
.target_tlb_bit0
);
13842 * btype_destination_ok:
13843 * @insn: The instruction at the branch destination
13844 * @bt: SCTLR_ELx.BT
13845 * @btype: PSTATE.BTYPE, and is non-zero
13847 * On a guarded page, there are a limited number of insns
13848 * that may be present at the branch target:
13849 * - branch target identifiers,
13850 * - paciasp, pacibsp,
13853 * Anything else causes a Branch Target Exception.
13855 * Return true if the branch is compatible, false to raise BTITRAP.
13857 static bool btype_destination_ok(uint32_t insn
, bool bt
, int btype
)
13859 if ((insn
& 0xfffff01fu
) == 0xd503201fu
) {
13861 switch (extract32(insn
, 5, 7)) {
13862 case 0b011001: /* PACIASP */
13863 case 0b011011: /* PACIBSP */
13865 * If SCTLR_ELx.BT, then PACI*SP are not compatible
13866 * with btype == 3. Otherwise all btype are ok.
13868 return !bt
|| btype
!= 3;
13869 case 0b100000: /* BTI */
13870 /* Not compatible with any btype. */
13872 case 0b100010: /* BTI c */
13873 /* Not compatible with btype == 3 */
13875 case 0b100100: /* BTI j */
13876 /* Not compatible with btype == 2 */
13878 case 0b100110: /* BTI jc */
13879 /* Compatible with any btype. */
13883 switch (insn
& 0xffe0001fu
) {
13884 case 0xd4200000u
: /* BRK */
13885 case 0xd4400000u
: /* HLT */
13886 /* Give priority to the breakpoint exception. */
13893 /* C3.1 A64 instruction index by encoding */
13894 static void disas_a64_insn(CPUARMState
*env
, DisasContext
*s
)
13898 insn
= arm_ldl_code(env
, s
->pc
, s
->sctlr_b
);
13902 s
->fp_access_checked
= false;
13904 if (dc_isar_feature(aa64_bti
, s
)) {
13905 if (s
->base
.num_insns
== 1) {
13907 * At the first insn of the TB, compute s->guarded_page.
13908 * We delayed computing this until successfully reading
13909 * the first insn of the TB, above. This (mostly) ensures
13910 * that the softmmu tlb entry has been populated, and the
13911 * page table GP bit is available.
13913 * Note that we need to compute this even if btype == 0,
13914 * because this value is used for BR instructions later
13915 * where ENV is not available.
13917 s
->guarded_page
= is_guarded_page(env
, s
);
13919 /* First insn can have btype set to non-zero. */
13920 tcg_debug_assert(s
->btype
>= 0);
13923 * Note that the Branch Target Exception has fairly high
13924 * priority -- below debugging exceptions but above most
13925 * everything else. This allows us to handle this now
13926 * instead of waiting until the insn is otherwise decoded.
13930 && !btype_destination_ok(insn
, s
->bt
, s
->btype
)) {
13931 gen_exception_insn(s
, 4, EXCP_UDEF
, syn_btitrap(s
->btype
),
13932 default_exception_el(s
));
13936 /* Not the first insn: btype must be 0. */
13937 tcg_debug_assert(s
->btype
== 0);
13941 switch (extract32(insn
, 25, 4)) {
13942 case 0x0: case 0x1: case 0x3: /* UNALLOCATED */
13943 unallocated_encoding(s
);
13946 if (!dc_isar_feature(aa64_sve
, s
) || !disas_sve(s
, insn
)) {
13947 unallocated_encoding(s
);
13950 case 0x8: case 0x9: /* Data processing - immediate */
13951 disas_data_proc_imm(s
, insn
);
13953 case 0xa: case 0xb: /* Branch, exception generation and system insns */
13954 disas_b_exc_sys(s
, insn
);
13959 case 0xe: /* Loads and stores */
13960 disas_ldst(s
, insn
);
13963 case 0xd: /* Data processing - register */
13964 disas_data_proc_reg(s
, insn
);
13967 case 0xf: /* Data processing - SIMD and floating point */
13968 disas_data_proc_simd_fp(s
, insn
);
13971 assert(FALSE
); /* all 15 cases should be handled above */
13975 /* if we allocated any temporaries, free them here */
13979 * After execution of most insns, btype is reset to 0.
13980 * Note that we set btype == -1 when the insn sets btype.
13982 if (s
->btype
> 0 && s
->base
.is_jmp
!= DISAS_NORETURN
) {
13987 static void aarch64_tr_init_disas_context(DisasContextBase
*dcbase
,
13990 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
13991 CPUARMState
*env
= cpu
->env_ptr
;
13992 ARMCPU
*arm_cpu
= arm_env_get_cpu(env
);
13993 uint32_t tb_flags
= dc
->base
.tb
->flags
;
13994 int bound
, core_mmu_idx
;
13996 dc
->isar
= &arm_cpu
->isar
;
13997 dc
->pc
= dc
->base
.pc_first
;
14001 /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
14002 * there is no secure EL1, so we route exceptions to EL3.
14004 dc
->secure_routed_to_el3
= arm_feature(env
, ARM_FEATURE_EL3
) &&
14005 !arm_el_is_aa64(env
, 3);
14008 dc
->be_data
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, BE_DATA
) ? MO_BE
: MO_LE
;
14009 dc
->condexec_mask
= 0;
14010 dc
->condexec_cond
= 0;
14011 core_mmu_idx
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, MMUIDX
);
14012 dc
->mmu_idx
= core_to_arm_mmu_idx(env
, core_mmu_idx
);
14013 dc
->tbii
= FIELD_EX32(tb_flags
, TBFLAG_A64
, TBII
);
14014 dc
->tbid
= FIELD_EX32(tb_flags
, TBFLAG_A64
, TBID
);
14015 dc
->current_el
= arm_mmu_idx_to_el(dc
->mmu_idx
);
14016 #if !defined(CONFIG_USER_ONLY)
14017 dc
->user
= (dc
->current_el
== 0);
14019 dc
->fp_excp_el
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, FPEXC_EL
);
14020 dc
->sve_excp_el
= FIELD_EX32(tb_flags
, TBFLAG_A64
, SVEEXC_EL
);
14021 dc
->sve_len
= (FIELD_EX32(tb_flags
, TBFLAG_A64
, ZCR_LEN
) + 1) * 16;
14022 dc
->pauth_active
= FIELD_EX32(tb_flags
, TBFLAG_A64
, PAUTH_ACTIVE
);
14023 dc
->bt
= FIELD_EX32(tb_flags
, TBFLAG_A64
, BT
);
14024 dc
->btype
= FIELD_EX32(tb_flags
, TBFLAG_A64
, BTYPE
);
14026 dc
->vec_stride
= 0;
14027 dc
->cp_regs
= arm_cpu
->cp_regs
;
14028 dc
->features
= env
->features
;
14030 /* Single step state. The code-generation logic here is:
14032 * generate code with no special handling for single-stepping (except
14033 * that anything that can make us go to SS_ACTIVE == 1 must end the TB;
14034 * this happens anyway because those changes are all system register or
14036 * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending)
14037 * emit code for one insn
14038 * emit code to clear PSTATE.SS
14039 * emit code to generate software step exception for completed step
14040 * end TB (as usual for having generated an exception)
14041 * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending)
14042 * emit code to generate a software step exception
14045 dc
->ss_active
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, SS_ACTIVE
);
14046 dc
->pstate_ss
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, PSTATE_SS
);
14047 dc
->is_ldex
= false;
14048 dc
->ss_same_el
= (arm_debug_target_el(env
) == dc
->current_el
);
14050 /* Bound the number of insns to execute to those left on the page. */
14051 bound
= -(dc
->base
.pc_first
| TARGET_PAGE_MASK
) / 4;
14053 /* If architectural single step active, limit to 1. */
14054 if (dc
->ss_active
) {
14057 dc
->base
.max_insns
= MIN(dc
->base
.max_insns
, bound
);
14059 init_tmp_a64_array(dc
);
14062 static void aarch64_tr_tb_start(DisasContextBase
*db
, CPUState
*cpu
)
14066 static void aarch64_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
14068 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14070 tcg_gen_insn_start(dc
->pc
, 0, 0);
14071 dc
->insn_start
= tcg_last_op();
14074 static bool aarch64_tr_breakpoint_check(DisasContextBase
*dcbase
, CPUState
*cpu
,
14075 const CPUBreakpoint
*bp
)
14077 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14079 if (bp
->flags
& BP_CPU
) {
14080 gen_a64_set_pc_im(dc
->pc
);
14081 gen_helper_check_breakpoints(cpu_env
);
14082 /* End the TB early; it likely won't be executed */
14083 dc
->base
.is_jmp
= DISAS_TOO_MANY
;
14085 gen_exception_internal_insn(dc
, 0, EXCP_DEBUG
);
14086 /* The address covered by the breakpoint must be
14087 included in [tb->pc, tb->pc + tb->size) in order
14088 to for it to be properly cleared -- thus we
14089 increment the PC here so that the logic setting
14090 tb->size below does the right thing. */
14092 dc
->base
.is_jmp
= DISAS_NORETURN
;
14098 static void aarch64_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
14100 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14101 CPUARMState
*env
= cpu
->env_ptr
;
14103 if (dc
->ss_active
&& !dc
->pstate_ss
) {
14104 /* Singlestep state is Active-pending.
14105 * If we're in this state at the start of a TB then either
14106 * a) we just took an exception to an EL which is being debugged
14107 * and this is the first insn in the exception handler
14108 * b) debug exceptions were masked and we just unmasked them
14109 * without changing EL (eg by clearing PSTATE.D)
14110 * In either case we're going to take a swstep exception in the
14111 * "did not step an insn" case, and so the syndrome ISV and EX
14112 * bits should be zero.
14114 assert(dc
->base
.num_insns
== 1);
14115 gen_exception(EXCP_UDEF
, syn_swstep(dc
->ss_same_el
, 0, 0),
14116 default_exception_el(dc
));
14117 dc
->base
.is_jmp
= DISAS_NORETURN
;
14119 disas_a64_insn(env
, dc
);
14122 dc
->base
.pc_next
= dc
->pc
;
14123 translator_loop_temp_check(&dc
->base
);
14126 static void aarch64_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
14128 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14130 if (unlikely(dc
->base
.singlestep_enabled
|| dc
->ss_active
)) {
14131 /* Note that this means single stepping WFI doesn't halt the CPU.
14132 * For conditional branch insns this is harmless unreachable code as
14133 * gen_goto_tb() has already handled emitting the debug exception
14134 * (and thus a tb-jump is not possible when singlestepping).
14136 switch (dc
->base
.is_jmp
) {
14138 gen_a64_set_pc_im(dc
->pc
);
14142 if (dc
->base
.singlestep_enabled
) {
14143 gen_exception_internal(EXCP_DEBUG
);
14145 gen_step_complete_exception(dc
);
14148 case DISAS_NORETURN
:
14152 switch (dc
->base
.is_jmp
) {
14154 case DISAS_TOO_MANY
:
14155 gen_goto_tb(dc
, 1, dc
->pc
);
14159 gen_a64_set_pc_im(dc
->pc
);
14162 tcg_gen_exit_tb(NULL
, 0);
14165 tcg_gen_lookup_and_goto_ptr();
14167 case DISAS_NORETURN
:
14171 gen_a64_set_pc_im(dc
->pc
);
14172 gen_helper_wfe(cpu_env
);
14175 gen_a64_set_pc_im(dc
->pc
);
14176 gen_helper_yield(cpu_env
);
14180 /* This is a special case because we don't want to just halt the CPU
14181 * if trying to debug across a WFI.
14183 TCGv_i32 tmp
= tcg_const_i32(4);
14185 gen_a64_set_pc_im(dc
->pc
);
14186 gen_helper_wfi(cpu_env
, tmp
);
14187 tcg_temp_free_i32(tmp
);
14188 /* The helper doesn't necessarily throw an exception, but we
14189 * must go back to the main loop to check for interrupts anyway.
14191 tcg_gen_exit_tb(NULL
, 0);
14197 /* Functions above can change dc->pc, so re-align db->pc_next */
14198 dc
->base
.pc_next
= dc
->pc
;
14201 static void aarch64_tr_disas_log(const DisasContextBase
*dcbase
,
14204 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14206 qemu_log("IN: %s\n", lookup_symbol(dc
->base
.pc_first
));
14207 log_target_disas(cpu
, dc
->base
.pc_first
, dc
->base
.tb
->size
);
14210 const TranslatorOps aarch64_translator_ops
= {
14211 .init_disas_context
= aarch64_tr_init_disas_context
,
14212 .tb_start
= aarch64_tr_tb_start
,
14213 .insn_start
= aarch64_tr_insn_start
,
14214 .breakpoint_check
= aarch64_tr_breakpoint_check
,
14215 .translate_insn
= aarch64_tr_translate_insn
,
14216 .tb_stop
= aarch64_tr_tb_stop
,
14217 .disas_log
= aarch64_tr_disas_log
,