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pci: untangle pci/msi dependency
[qemu.git] / hw / pci.c
blob254647bc34ad1ec5bde09d9c63458593f0baeceb
1 /*
2 * QEMU PCI bus manager
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "pci.h"
26 #include "pci_bridge.h"
27 #include "pci_internals.h"
28 #include "monitor.h"
29 #include "net.h"
30 #include "sysemu.h"
31 #include "loader.h"
32 #include "qemu-objects.h"
33 #include "range.h"
34
35 //#define DEBUG_PCI
36 #ifdef DEBUG_PCI
37 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
38 #else
39 # define PCI_DPRINTF(format, ...) do { } while (0)
40 #endif
41
42 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
43 static char *pcibus_get_dev_path(DeviceState *dev);
44 static int pcibus_reset(BusState *qbus);
45
46 struct BusInfo pci_bus_info = {
47 .name = "PCI",
48 .size = sizeof(PCIBus),
49 .print_dev = pcibus_dev_print,
50 .get_dev_path = pcibus_get_dev_path,
51 .reset = pcibus_reset,
52 .props = (Property[]) {
53 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
54 DEFINE_PROP_STRING("romfile", PCIDevice, romfile),
55 DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1),
56 DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present,
57 QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false),
58 DEFINE_PROP_BIT("command_serr_enable", PCIDevice, cap_present,
59 QEMU_PCI_CAP_SERR_BITNR, true),
60 DEFINE_PROP_END_OF_LIST()
61 }
62 };
63
64 static void pci_update_mappings(PCIDevice *d);
65 static void pci_set_irq(void *opaque, int irq_num, int level);
66 static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom);
67 static void pci_del_option_rom(PCIDevice *pdev);
68
69 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
70 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
71
72 struct PCIHostBus {
73 int domain;
74 struct PCIBus *bus;
75 QLIST_ENTRY(PCIHostBus) next;
76 };
77 static QLIST_HEAD(, PCIHostBus) host_buses;
78
79 static const VMStateDescription vmstate_pcibus = {
80 .name = "PCIBUS",
81 .version_id = 1,
82 .minimum_version_id = 1,
83 .minimum_version_id_old = 1,
84 .fields = (VMStateField []) {
85 VMSTATE_INT32_EQUAL(nirq, PCIBus),
86 VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t),
87 VMSTATE_END_OF_LIST()
88 }
89 };
90
91 static int pci_bar(PCIDevice *d, int reg)
92 {
93 uint8_t type;
94
95 if (reg != PCI_ROM_SLOT)
96 return PCI_BASE_ADDRESS_0 + reg * 4;
97
98 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
99 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
100 }
101
102 static inline int pci_irq_state(PCIDevice *d, int irq_num)
103 {
104 return (d->irq_state >> irq_num) & 0x1;
105 }
106
107 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level)
108 {
109 d->irq_state &= ~(0x1 << irq_num);
110 d->irq_state |= level << irq_num;
111 }
112
113 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
114 {
115 PCIBus *bus;
116 for (;;) {
117 bus = pci_dev->bus;
118 irq_num = bus->map_irq(pci_dev, irq_num);
119 if (bus->set_irq)
120 break;
121 pci_dev = bus->parent_dev;
122 }
123 bus->irq_count[irq_num] += change;
124 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
125 }
126
127 /* Update interrupt status bit in config space on interrupt
128 * state change. */
129 static void pci_update_irq_status(PCIDevice *dev)
130 {
131 if (dev->irq_state) {
132 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT;
133 } else {
134 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
135 }
136 }
137
138 static void pci_device_reset(PCIDevice *dev)
139 {
140 int r;
141 /* TODO: call the below unconditionally once all pci devices
142 * are qdevified */
143 if (dev->qdev.info) {
144 qdev_reset_all(&dev->qdev);
145 }
146
147 dev->irq_state = 0;
148 pci_update_irq_status(dev);
149 /* Clear all writeable bits */
150 pci_word_test_and_clear_mask(dev->config + PCI_COMMAND,
151 pci_get_word(dev->wmask + PCI_COMMAND) |
152 pci_get_word(dev->w1cmask + PCI_COMMAND));
153 pci_word_test_and_clear_mask(dev->config + PCI_STATUS,
154 pci_get_word(dev->wmask + PCI_STATUS) |
155 pci_get_word(dev->w1cmask + PCI_STATUS));
156 dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
157 dev->config[PCI_INTERRUPT_LINE] = 0x0;
158 for (r = 0; r < PCI_NUM_REGIONS; ++r) {
159 PCIIORegion *region = &dev->io_regions[r];
160 if (!region->size) {
161 continue;
162 }
163
164 if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) &&
165 region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
166 pci_set_quad(dev->config + pci_bar(dev, r), region->type);
167 } else {
168 pci_set_long(dev->config + pci_bar(dev, r), region->type);
169 }
170 }
171 pci_update_mappings(dev);
172 }
173
174 /*
175 * Trigger pci bus reset under a given bus.
176 * To be called on RST# assert.
177 */
178 void pci_bus_reset(PCIBus *bus)
179 {
180 int i;
181
182 for (i = 0; i < bus->nirq; i++) {
183 bus->irq_count[i] = 0;
184 }
185 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
186 if (bus->devices[i]) {
187 pci_device_reset(bus->devices[i]);
188 }
189 }
190 }
191
192 static int pcibus_reset(BusState *qbus)
193 {
194 pci_bus_reset(DO_UPCAST(PCIBus, qbus, qbus));
195
196 /* topology traverse is done by pci_bus_reset().
197 Tell qbus/qdev walker not to traverse the tree */
198 return 1;
199 }
200
201 static void pci_host_bus_register(int domain, PCIBus *bus)
202 {
203 struct PCIHostBus *host;
204 host = qemu_mallocz(sizeof(*host));
205 host->domain = domain;
206 host->bus = bus;
207 QLIST_INSERT_HEAD(&host_buses, host, next);
208 }
209
210 PCIBus *pci_find_root_bus(int domain)
211 {
212 struct PCIHostBus *host;
213
214 QLIST_FOREACH(host, &host_buses, next) {
215 if (host->domain == domain) {
216 return host->bus;
217 }
218 }
219
220 return NULL;
221 }
222
223 int pci_find_domain(const PCIBus *bus)
224 {
225 PCIDevice *d;
226 struct PCIHostBus *host;
227
228 /* obtain root bus */
229 while ((d = bus->parent_dev) != NULL) {
230 bus = d->bus;
231 }
232
233 QLIST_FOREACH(host, &host_buses, next) {
234 if (host->bus == bus) {
235 return host->domain;
236 }
237 }
238
239 abort(); /* should not be reached */
240 return -1;
241 }
242
243 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
244 const char *name, int devfn_min)
245 {
246 qbus_create_inplace(&bus->qbus, &pci_bus_info, parent, name);
247 assert(PCI_FUNC(devfn_min) == 0);
248 bus->devfn_min = devfn_min;
249
250 /* host bridge */
251 QLIST_INIT(&bus->child);
252 pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported */
253
254 vmstate_register(NULL, -1, &vmstate_pcibus, bus);
255 }
256
257 PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min)
258 {
259 PCIBus *bus;
260
261 bus = qemu_mallocz(sizeof(*bus));
262 bus->qbus.qdev_allocated = 1;
263 pci_bus_new_inplace(bus, parent, name, devfn_min);
264 return bus;
265 }
266
267 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
268 void *irq_opaque, int nirq)
269 {
270 bus->set_irq = set_irq;
271 bus->map_irq = map_irq;
272 bus->irq_opaque = irq_opaque;
273 bus->nirq = nirq;
274 bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0]));
275 }
276
277 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *qdev)
278 {
279 bus->qbus.allow_hotplug = 1;
280 bus->hotplug = hotplug;
281 bus->hotplug_qdev = qdev;
282 }
283
284 void pci_bus_set_mem_base(PCIBus *bus, target_phys_addr_t base)
285 {
286 bus->mem_base = base;
287 }
288
289 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
290 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
291 void *irq_opaque, int devfn_min, int nirq)
292 {
293 PCIBus *bus;
294
295 bus = pci_bus_new(parent, name, devfn_min);
296 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
297 return bus;
298 }
299
300 int pci_bus_num(PCIBus *s)
301 {
302 if (!s->parent_dev)
303 return 0; /* pci host bridge */
304 return s->parent_dev->config[PCI_SECONDARY_BUS];
305 }
306
307 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)
308 {
309 PCIDevice *s = container_of(pv, PCIDevice, config);
310 uint8_t *config;
311 int i;
312
313 assert(size == pci_config_size(s));
314 config = qemu_malloc(size);
315
316 qemu_get_buffer(f, config, size);
317 for (i = 0; i < size; ++i) {
318 if ((config[i] ^ s->config[i]) &
319 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) {
320 qemu_free(config);
321 return -EINVAL;
322 }
323 }
324 memcpy(s->config, config, size);
325
326 pci_update_mappings(s);
327
328 qemu_free(config);
329 return 0;
330 }
331
332 /* just put buffer */
333 static void put_pci_config_device(QEMUFile *f, void *pv, size_t size)
334 {
335 const uint8_t **v = pv;
336 assert(size == pci_config_size(container_of(pv, PCIDevice, config)));
337 qemu_put_buffer(f, *v, size);
338 }
339
340 static VMStateInfo vmstate_info_pci_config = {
341 .name = "pci config",
342 .get = get_pci_config_device,
343 .put = put_pci_config_device,
344 };
345
346 static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size)
347 {
348 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
349 uint32_t irq_state[PCI_NUM_PINS];
350 int i;
351 for (i = 0; i < PCI_NUM_PINS; ++i) {
352 irq_state[i] = qemu_get_be32(f);
353 if (irq_state[i] != 0x1 && irq_state[i] != 0) {
354 fprintf(stderr, "irq state %d: must be 0 or 1.\n",
355 irq_state[i]);
356 return -EINVAL;
357 }
358 }
359
360 for (i = 0; i < PCI_NUM_PINS; ++i) {
361 pci_set_irq_state(s, i, irq_state[i]);
362 }
363
364 return 0;
365 }
366
367 static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size)
368 {
369 int i;
370 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
371
372 for (i = 0; i < PCI_NUM_PINS; ++i) {
373 qemu_put_be32(f, pci_irq_state(s, i));
374 }
375 }
376
377 static VMStateInfo vmstate_info_pci_irq_state = {
378 .name = "pci irq state",
379 .get = get_pci_irq_state,
380 .put = put_pci_irq_state,
381 };
382
383 const VMStateDescription vmstate_pci_device = {
384 .name = "PCIDevice",
385 .version_id = 2,
386 .minimum_version_id = 1,
387 .minimum_version_id_old = 1,
388 .fields = (VMStateField []) {
389 VMSTATE_INT32_LE(version_id, PCIDevice),
390 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
391 vmstate_info_pci_config,
392 PCI_CONFIG_SPACE_SIZE),
393 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
394 vmstate_info_pci_irq_state,
395 PCI_NUM_PINS * sizeof(int32_t)),
396 VMSTATE_END_OF_LIST()
397 }
398 };
399
400 const VMStateDescription vmstate_pcie_device = {
401 .name = "PCIDevice",
402 .version_id = 2,
403 .minimum_version_id = 1,
404 .minimum_version_id_old = 1,
405 .fields = (VMStateField []) {
406 VMSTATE_INT32_LE(version_id, PCIDevice),
407 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
408 vmstate_info_pci_config,
409 PCIE_CONFIG_SPACE_SIZE),
410 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
411 vmstate_info_pci_irq_state,
412 PCI_NUM_PINS * sizeof(int32_t)),
413 VMSTATE_END_OF_LIST()
414 }
415 };
416
417 static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s)
418 {
419 return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device;
420 }
421
422 void pci_device_save(PCIDevice *s, QEMUFile *f)
423 {
424 /* Clear interrupt status bit: it is implicit
425 * in irq_state which we are saving.
426 * This makes us compatible with old devices
427 * which never set or clear this bit. */
428 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
429 vmstate_save_state(f, pci_get_vmstate(s), s);
430 /* Restore the interrupt status bit. */
431 pci_update_irq_status(s);
432 }
433
434 int pci_device_load(PCIDevice *s, QEMUFile *f)
435 {
436 int ret;
437 ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id);
438 /* Restore the interrupt status bit. */
439 pci_update_irq_status(s);
440 return ret;
441 }
442
443 static void pci_set_default_subsystem_id(PCIDevice *pci_dev)
444 {
445 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
446 pci_default_sub_vendor_id);
447 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
448 pci_default_sub_device_id);
449 }
450
451 /*
452 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
453 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
454 */
455 int pci_parse_devaddr(const char *addr, int *domp, int *busp,
456 unsigned int *slotp, unsigned int *funcp)
457 {
458 const char *p;
459 char *e;
460 unsigned long val;
461 unsigned long dom = 0, bus = 0;
462 unsigned int slot = 0;
463 unsigned int func = 0;
464
465 p = addr;
466 val = strtoul(p, &e, 16);
467 if (e == p)
468 return -1;
469 if (*e == ':') {
470 bus = val;
471 p = e + 1;
472 val = strtoul(p, &e, 16);
473 if (e == p)
474 return -1;
475 if (*e == ':') {
476 dom = bus;
477 bus = val;
478 p = e + 1;
479 val = strtoul(p, &e, 16);
480 if (e == p)
481 return -1;
482 }
483 }
484
485 slot = val;
486
487 if (funcp != NULL) {
488 if (*e != '.')
489 return -1;
490
491 p = e + 1;
492 val = strtoul(p, &e, 16);
493 if (e == p)
494 return -1;
495
496 func = val;
497 }
498
499 /* if funcp == NULL func is 0 */
500 if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7)
501 return -1;
502
503 if (*e)
504 return -1;
505
506 /* Note: QEMU doesn't implement domains other than 0 */
507 if (!pci_find_bus(pci_find_root_bus(dom), bus))
508 return -1;
509
510 *domp = dom;
511 *busp = bus;
512 *slotp = slot;
513 if (funcp != NULL)
514 *funcp = func;
515 return 0;
516 }
517
518 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
519 unsigned *slotp)
520 {
521 /* strip legacy tag */
522 if (!strncmp(addr, "pci_addr=", 9)) {
523 addr += 9;
524 }
525 if (pci_parse_devaddr(addr, domp, busp, slotp, NULL)) {
526 monitor_printf(mon, "Invalid pci address\n");
527 return -1;
528 }
529 return 0;
530 }
531
532 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
533 {
534 int dom, bus;
535 unsigned slot;
536
537 if (!devaddr) {
538 *devfnp = -1;
539 return pci_find_bus(pci_find_root_bus(0), 0);
540 }
541
542 if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) {
543 return NULL;
544 }
545
546 *devfnp = slot << 3;
547 return pci_find_bus(pci_find_root_bus(dom), bus);
548 }
549
550 static void pci_init_cmask(PCIDevice *dev)
551 {
552 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
553 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
554 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
555 dev->cmask[PCI_REVISION_ID] = 0xff;
556 dev->cmask[PCI_CLASS_PROG] = 0xff;
557 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
558 dev->cmask[PCI_HEADER_TYPE] = 0xff;
559 dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
560 }
561
562 static void pci_init_wmask(PCIDevice *dev)
563 {
564 int config_size = pci_config_size(dev);
565
566 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
567 dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
568 pci_set_word(dev->wmask + PCI_COMMAND,
569 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
570 PCI_COMMAND_INTX_DISABLE);
571 if (dev->cap_present & QEMU_PCI_CAP_SERR) {
572 pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR);
573 }
574
575 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
576 config_size - PCI_CONFIG_HEADER_SIZE);
577 }
578
579 static void pci_init_w1cmask(PCIDevice *dev)
580 {
581 /*
582 * Note: It's okay to set w1cmask even for readonly bits as
583 * long as their value is hardwired to 0.
584 */
585 pci_set_word(dev->w1cmask + PCI_STATUS,
586 PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT |
587 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT |
588 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY);
589 }
590
591 static void pci_init_wmask_bridge(PCIDevice *d)
592 {
593 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
594 PCI_SEC_LETENCY_TIMER */
595 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);
596
597 /* base and limit */
598 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
599 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
600 pci_set_word(d->wmask + PCI_MEMORY_BASE,
601 PCI_MEMORY_RANGE_MASK & 0xffff);
602 pci_set_word(d->wmask + PCI_MEMORY_LIMIT,
603 PCI_MEMORY_RANGE_MASK & 0xffff);
604 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,
605 PCI_PREF_RANGE_MASK & 0xffff);
606 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,
607 PCI_PREF_RANGE_MASK & 0xffff);
608
609 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
610 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
611
612 /* TODO: add this define to pci_regs.h in linux and then in qemu. */
613 #define PCI_BRIDGE_CTL_VGA_16BIT 0x10 /* VGA 16-bit decode */
614 #define PCI_BRIDGE_CTL_DISCARD 0x100 /* Primary discard timer */
615 #define PCI_BRIDGE_CTL_SEC_DISCARD 0x200 /* Secondary discard timer */
616 #define PCI_BRIDGE_CTL_DISCARD_STATUS 0x400 /* Discard timer status */
617 #define PCI_BRIDGE_CTL_DISCARD_SERR 0x800 /* Discard timer SERR# enable */
618 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL,
619 PCI_BRIDGE_CTL_PARITY |
620 PCI_BRIDGE_CTL_SERR |
621 PCI_BRIDGE_CTL_ISA |
622 PCI_BRIDGE_CTL_VGA |
623 PCI_BRIDGE_CTL_VGA_16BIT |
624 PCI_BRIDGE_CTL_MASTER_ABORT |
625 PCI_BRIDGE_CTL_BUS_RESET |
626 PCI_BRIDGE_CTL_FAST_BACK |
627 PCI_BRIDGE_CTL_DISCARD |
628 PCI_BRIDGE_CTL_SEC_DISCARD |
629 PCI_BRIDGE_CTL_DISCARD_STATUS |
630 PCI_BRIDGE_CTL_DISCARD_SERR);
631 /* Below does not do anything as we never set this bit, put here for
632 * completeness. */
633 pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL,
634 PCI_BRIDGE_CTL_DISCARD_STATUS);
635 }
636
637 static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev)
638 {
639 uint8_t slot = PCI_SLOT(dev->devfn);
640 uint8_t func;
641
642 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
643 dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION;
644 }
645
646 /*
647 * multifunction bit is interpreted in two ways as follows.
648 * - all functions must set the bit to 1.
649 * Example: Intel X53
650 * - function 0 must set the bit, but the rest function (> 0)
651 * is allowed to leave the bit to 0.
652 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
653 *
654 * So OS (at least Linux) checks the bit of only function 0,
655 * and doesn't see the bit of function > 0.
656 *
657 * The below check allows both interpretation.
658 */
659 if (PCI_FUNC(dev->devfn)) {
660 PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)];
661 if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) {
662 /* function 0 should set multifunction bit */
663 error_report("PCI: single function device can't be populated "
664 "in function %x.%x", slot, PCI_FUNC(dev->devfn));
665 return -1;
666 }
667 return 0;
668 }
669
670 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
671 return 0;
672 }
673 /* function 0 indicates single function, so function > 0 must be NULL */
674 for (func = 1; func < PCI_FUNC_MAX; ++func) {
675 if (bus->devices[PCI_DEVFN(slot, func)]) {
676 error_report("PCI: %x.0 indicates single function, "
677 "but %x.%x is already populated.",
678 slot, slot, func);
679 return -1;
680 }
681 }
682 return 0;
683 }
684
685 static void pci_config_alloc(PCIDevice *pci_dev)
686 {
687 int config_size = pci_config_size(pci_dev);
688
689 pci_dev->config = qemu_mallocz(config_size);
690 pci_dev->cmask = qemu_mallocz(config_size);
691 pci_dev->wmask = qemu_mallocz(config_size);
692 pci_dev->w1cmask = qemu_mallocz(config_size);
693 pci_dev->used = qemu_mallocz(config_size);
694 }
695
696 static void pci_config_free(PCIDevice *pci_dev)
697 {
698 qemu_free(pci_dev->config);
699 qemu_free(pci_dev->cmask);
700 qemu_free(pci_dev->wmask);
701 qemu_free(pci_dev->w1cmask);
702 qemu_free(pci_dev->used);
703 }
704
705 /* -1 for devfn means auto assign */
706 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
707 const char *name, int devfn,
708 PCIConfigReadFunc *config_read,
709 PCIConfigWriteFunc *config_write,
710 bool is_bridge)
711 {
712 if (devfn < 0) {
713 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
714 devfn += PCI_FUNC_MAX) {
715 if (!bus->devices[devfn])
716 goto found;
717 }
718 error_report("PCI: no slot/function available for %s, all in use", name);
719 return NULL;
720 found: ;
721 } else if (bus->devices[devfn]) {
722 error_report("PCI: slot %d function %d not available for %s, in use by %s",
723 PCI_SLOT(devfn), PCI_FUNC(devfn), name, bus->devices[devfn]->name);
724 return NULL;
725 }
726 pci_dev->bus = bus;
727 pci_dev->devfn = devfn;
728 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
729 pci_dev->irq_state = 0;
730 pci_config_alloc(pci_dev);
731
732 if (!is_bridge) {
733 pci_set_default_subsystem_id(pci_dev);
734 }
735 pci_init_cmask(pci_dev);
736 pci_init_wmask(pci_dev);
737 pci_init_w1cmask(pci_dev);
738 if (is_bridge) {
739 pci_init_wmask_bridge(pci_dev);
740 }
741 if (pci_init_multifunction(bus, pci_dev)) {
742 pci_config_free(pci_dev);
743 return NULL;
744 }
745
746 if (!config_read)
747 config_read = pci_default_read_config;
748 if (!config_write)
749 config_write = pci_default_write_config;
750 pci_dev->config_read = config_read;
751 pci_dev->config_write = config_write;
752 bus->devices[devfn] = pci_dev;
753 pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS);
754 pci_dev->version_id = 2; /* Current pci device vmstate version */
755 return pci_dev;
756 }
757
758 static void do_pci_unregister_device(PCIDevice *pci_dev)
759 {
760 qemu_free_irqs(pci_dev->irq);
761 pci_dev->bus->devices[pci_dev->devfn] = NULL;
762 pci_config_free(pci_dev);
763 }
764
765 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
766 int instance_size, int devfn,
767 PCIConfigReadFunc *config_read,
768 PCIConfigWriteFunc *config_write)
769 {
770 PCIDevice *pci_dev;
771
772 pci_dev = qemu_mallocz(instance_size);
773 pci_dev = do_pci_register_device(pci_dev, bus, name, devfn,
774 config_read, config_write,
775 PCI_HEADER_TYPE_NORMAL);
776 if (pci_dev == NULL) {
777 hw_error("PCI: can't register device\n");
778 }
779 return pci_dev;
780 }
781
782 static target_phys_addr_t pci_to_cpu_addr(PCIBus *bus,
783 target_phys_addr_t addr)
784 {
785 return addr + bus->mem_base;
786 }
787
788 static void pci_unregister_io_regions(PCIDevice *pci_dev)
789 {
790 PCIIORegion *r;
791 int i;
792
793 for(i = 0; i < PCI_NUM_REGIONS; i++) {
794 r = &pci_dev->io_regions[i];
795 if (!r->size || r->addr == PCI_BAR_UNMAPPED)
796 continue;
797 if (r->type == PCI_BASE_ADDRESS_SPACE_IO) {
798 isa_unassign_ioport(r->addr, r->filtered_size);
799 } else {
800 cpu_register_physical_memory(pci_to_cpu_addr(pci_dev->bus,
801 r->addr),
802 r->filtered_size,
803 IO_MEM_UNASSIGNED);
804 }
805 }
806 }
807
808 static int pci_unregister_device(DeviceState *dev)
809 {
810 PCIDevice *pci_dev = DO_UPCAST(PCIDevice, qdev, dev);
811 PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, dev->info);
812 int ret = 0;
813
814 if (info->exit)
815 ret = info->exit(pci_dev);
816 if (ret)
817 return ret;
818
819 pci_unregister_io_regions(pci_dev);
820 pci_del_option_rom(pci_dev);
821 do_pci_unregister_device(pci_dev);
822 return 0;
823 }
824
825 void pci_register_bar(PCIDevice *pci_dev, int region_num,
826 pcibus_t size, uint8_t type,
827 PCIMapIORegionFunc *map_func)
828 {
829 PCIIORegion *r;
830 uint32_t addr;
831 uint64_t wmask;
832
833 assert(region_num >= 0);
834 assert(region_num < PCI_NUM_REGIONS);
835 if (size & (size-1)) {
836 fprintf(stderr, "ERROR: PCI region size must be pow2 "
837 "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);
838 exit(1);
839 }
840
841 r = &pci_dev->io_regions[region_num];
842 r->addr = PCI_BAR_UNMAPPED;
843 r->size = size;
844 r->filtered_size = size;
845 r->type = type;
846 r->map_func = map_func;
847
848 wmask = ~(size - 1);
849 addr = pci_bar(pci_dev, region_num);
850 if (region_num == PCI_ROM_SLOT) {
851 /* ROM enable bit is writeable */
852 wmask |= PCI_ROM_ADDRESS_ENABLE;
853 }
854 pci_set_long(pci_dev->config + addr, type);
855 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
856 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
857 pci_set_quad(pci_dev->wmask + addr, wmask);
858 pci_set_quad(pci_dev->cmask + addr, ~0ULL);
859 } else {
860 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
861 pci_set_long(pci_dev->cmask + addr, 0xffffffff);
862 }
863 }
864
865 static void pci_bridge_filter(PCIDevice *d, pcibus_t *addr, pcibus_t *size,
866 uint8_t type)
867 {
868 pcibus_t base = *addr;
869 pcibus_t limit = *addr + *size - 1;
870 PCIDevice *br;
871
872 for (br = d->bus->parent_dev; br; br = br->bus->parent_dev) {
873 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
874
875 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
876 if (!(cmd & PCI_COMMAND_IO)) {
877 goto no_map;
878 }
879 } else {
880 if (!(cmd & PCI_COMMAND_MEMORY)) {
881 goto no_map;
882 }
883 }
884
885 base = MAX(base, pci_bridge_get_base(br, type));
886 limit = MIN(limit, pci_bridge_get_limit(br, type));
887 }
888
889 if (base > limit) {
890 goto no_map;
891 }
892 *addr = base;
893 *size = limit - base + 1;
894 return;
895 no_map:
896 *addr = PCI_BAR_UNMAPPED;
897 *size = 0;
898 }
899
900 static pcibus_t pci_bar_address(PCIDevice *d,
901 int reg, uint8_t type, pcibus_t size)
902 {
903 pcibus_t new_addr, last_addr;
904 int bar = pci_bar(d, reg);
905 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
906
907 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
908 if (!(cmd & PCI_COMMAND_IO)) {
909 return PCI_BAR_UNMAPPED;
910 }
911 new_addr = pci_get_long(d->config + bar) & ~(size - 1);
912 last_addr = new_addr + size - 1;
913 /* NOTE: we have only 64K ioports on PC */
914 if (last_addr <= new_addr || new_addr == 0 || last_addr > UINT16_MAX) {
915 return PCI_BAR_UNMAPPED;
916 }
917 return new_addr;
918 }
919
920 if (!(cmd & PCI_COMMAND_MEMORY)) {
921 return PCI_BAR_UNMAPPED;
922 }
923 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
924 new_addr = pci_get_quad(d->config + bar);
925 } else {
926 new_addr = pci_get_long(d->config + bar);
927 }
928 /* the ROM slot has a specific enable bit */
929 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
930 return PCI_BAR_UNMAPPED;
931 }
932 new_addr &= ~(size - 1);
933 last_addr = new_addr + size - 1;
934 /* NOTE: we do not support wrapping */
935 /* XXX: as we cannot support really dynamic
936 mappings, we handle specific values as invalid
937 mappings. */
938 if (last_addr <= new_addr || new_addr == 0 ||
939 last_addr == PCI_BAR_UNMAPPED) {
940 return PCI_BAR_UNMAPPED;
941 }
942
943 /* Now pcibus_t is 64bit.
944 * Check if 32 bit BAR wraps around explicitly.
945 * Without this, PC ide doesn't work well.
946 * TODO: remove this work around.
947 */
948 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) {
949 return PCI_BAR_UNMAPPED;
950 }
951
952 /*
953 * OS is allowed to set BAR beyond its addressable
954 * bits. For example, 32 bit OS can set 64bit bar
955 * to >4G. Check it. TODO: we might need to support
956 * it in the future for e.g. PAE.
957 */
958 if (last_addr >= TARGET_PHYS_ADDR_MAX) {
959 return PCI_BAR_UNMAPPED;
960 }
961
962 return new_addr;
963 }
964
965 static void pci_update_mappings(PCIDevice *d)
966 {
967 PCIIORegion *r;
968 int i;
969 pcibus_t new_addr, filtered_size;
970
971 for(i = 0; i < PCI_NUM_REGIONS; i++) {
972 r = &d->io_regions[i];
973
974 /* this region isn't registered */
975 if (!r->size)
976 continue;
977
978 new_addr = pci_bar_address(d, i, r->type, r->size);
979
980 /* bridge filtering */
981 filtered_size = r->size;
982 if (new_addr != PCI_BAR_UNMAPPED) {
983 pci_bridge_filter(d, &new_addr, &filtered_size, r->type);
984 }
985
986 /* This bar isn't changed */
987 if (new_addr == r->addr && filtered_size == r->filtered_size)
988 continue;
989
990 /* now do the real mapping */
991 if (r->addr != PCI_BAR_UNMAPPED) {
992 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
993 int class;
994 /* NOTE: specific hack for IDE in PC case:
995 only one byte must be mapped. */
996 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
997 if (class == 0x0101 && r->size == 4) {
998 isa_unassign_ioport(r->addr + 2, 1);
999 } else {
1000 isa_unassign_ioport(r->addr, r->filtered_size);
1001 }
1002 } else {
1003 cpu_register_physical_memory(pci_to_cpu_addr(d->bus, r->addr),
1004 r->filtered_size,
1005 IO_MEM_UNASSIGNED);
1006 qemu_unregister_coalesced_mmio(r->addr, r->filtered_size);
1007 }
1008 }
1009 r->addr = new_addr;
1010 r->filtered_size = filtered_size;
1011 if (r->addr != PCI_BAR_UNMAPPED) {
1012 /*
1013 * TODO: currently almost all the map funcions assumes
1014 * filtered_size == size and addr & ~(size - 1) == addr.
1015 * However with bridge filtering, they aren't always true.
1016 * Teach them such cases, such that filtered_size < size and
1017 * addr & (size - 1) != 0.
1018 */
1019 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1020 r->map_func(d, i, r->addr, r->filtered_size, r->type);
1021 } else {
1022 r->map_func(d, i, pci_to_cpu_addr(d->bus, r->addr),
1023 r->filtered_size, r->type);
1024 }
1025 }
1026 }
1027 }
1028
1029 static inline int pci_irq_disabled(PCIDevice *d)
1030 {
1031 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE;
1032 }
1033
1034 /* Called after interrupt disabled field update in config space,
1035 * assert/deassert interrupts if necessary.
1036 * Gets original interrupt disable bit value (before update). */
1037 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled)
1038 {
1039 int i, disabled = pci_irq_disabled(d);
1040 if (disabled == was_irq_disabled)
1041 return;
1042 for (i = 0; i < PCI_NUM_PINS; ++i) {
1043 int state = pci_irq_state(d, i);
1044 pci_change_irq_level(d, i, disabled ? -state : state);
1045 }
1046 }
1047
1048 uint32_t pci_default_read_config(PCIDevice *d,
1049 uint32_t address, int len)
1050 {
1051 uint32_t val = 0;
1052 assert(len == 1 || len == 2 || len == 4);
1053 len = MIN(len, pci_config_size(d) - address);
1054 memcpy(&val, d->config + address, len);
1055 return le32_to_cpu(val);
1056 }
1057
1058 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
1059 {
1060 int i, was_irq_disabled = pci_irq_disabled(d);
1061 uint32_t config_size = pci_config_size(d);
1062
1063 for (i = 0; i < l && addr + i < config_size; val >>= 8, ++i) {
1064 uint8_t wmask = d->wmask[addr + i];
1065 uint8_t w1cmask = d->w1cmask[addr + i];
1066 assert(!(wmask & w1cmask));
1067 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
1068 d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */
1069 }
1070 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
1071 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
1072 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
1073 range_covers_byte(addr, l, PCI_COMMAND))
1074 pci_update_mappings(d);
1075
1076 if (range_covers_byte(addr, l, PCI_COMMAND))
1077 pci_update_irq_disabled(d, was_irq_disabled);
1078 }
1079
1080 /***********************************************************/
1081 /* generic PCI irq support */
1082
1083 /* 0 <= irq_num <= 3. level must be 0 or 1 */
1084 static void pci_set_irq(void *opaque, int irq_num, int level)
1085 {
1086 PCIDevice *pci_dev = opaque;
1087 int change;
1088
1089 change = level - pci_irq_state(pci_dev, irq_num);
1090 if (!change)
1091 return;
1092
1093 pci_set_irq_state(pci_dev, irq_num, level);
1094 pci_update_irq_status(pci_dev);
1095 if (pci_irq_disabled(pci_dev))
1096 return;
1097 pci_change_irq_level(pci_dev, irq_num, change);
1098 }
1099
1100 /***********************************************************/
1101 /* monitor info on PCI */
1102
1103 typedef struct {
1104 uint16_t class;
1105 const char *desc;
1106 } pci_class_desc;
1107
1108 static const pci_class_desc pci_class_descriptions[] =
1109 {
1110 { 0x0100, "SCSI controller"},
1111 { 0x0101, "IDE controller"},
1112 { 0x0102, "Floppy controller"},
1113 { 0x0103, "IPI controller"},
1114 { 0x0104, "RAID controller"},
1115 { 0x0106, "SATA controller"},
1116 { 0x0107, "SAS controller"},
1117 { 0x0180, "Storage controller"},
1118 { 0x0200, "Ethernet controller"},
1119 { 0x0201, "Token Ring controller"},
1120 { 0x0202, "FDDI controller"},
1121 { 0x0203, "ATM controller"},
1122 { 0x0280, "Network controller"},
1123 { 0x0300, "VGA controller"},
1124 { 0x0301, "XGA controller"},
1125 { 0x0302, "3D controller"},
1126 { 0x0380, "Display controller"},
1127 { 0x0400, "Video controller"},
1128 { 0x0401, "Audio controller"},
1129 { 0x0402, "Phone"},
1130 { 0x0480, "Multimedia controller"},
1131 { 0x0500, "RAM controller"},
1132 { 0x0501, "Flash controller"},
1133 { 0x0580, "Memory controller"},
1134 { 0x0600, "Host bridge"},
1135 { 0x0601, "ISA bridge"},
1136 { 0x0602, "EISA bridge"},
1137 { 0x0603, "MC bridge"},
1138 { 0x0604, "PCI bridge"},
1139 { 0x0605, "PCMCIA bridge"},
1140 { 0x0606, "NUBUS bridge"},
1141 { 0x0607, "CARDBUS bridge"},
1142 { 0x0608, "RACEWAY bridge"},
1143 { 0x0680, "Bridge"},
1144 { 0x0c03, "USB controller"},
1145 { 0, NULL}
1146 };
1147
1148 static void pci_for_each_device_under_bus(PCIBus *bus,
1149 void (*fn)(PCIBus *b, PCIDevice *d))
1150 {
1151 PCIDevice *d;
1152 int devfn;
1153
1154 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1155 d = bus->devices[devfn];
1156 if (d) {
1157 fn(bus, d);
1158 }
1159 }
1160 }
1161
1162 void pci_for_each_device(PCIBus *bus, int bus_num,
1163 void (*fn)(PCIBus *b, PCIDevice *d))
1164 {
1165 bus = pci_find_bus(bus, bus_num);
1166
1167 if (bus) {
1168 pci_for_each_device_under_bus(bus, fn);
1169 }
1170 }
1171
1172 static void pci_device_print(Monitor *mon, QDict *device)
1173 {
1174 QDict *qdict;
1175 QListEntry *entry;
1176 uint64_t addr, size;
1177
1178 monitor_printf(mon, " Bus %2" PRId64 ", ", qdict_get_int(device, "bus"));
1179 monitor_printf(mon, "device %3" PRId64 ", function %" PRId64 ":\n",
1180 qdict_get_int(device, "slot"),
1181 qdict_get_int(device, "function"));
1182 monitor_printf(mon, " ");
1183
1184 qdict = qdict_get_qdict(device, "class_info");
1185 if (qdict_haskey(qdict, "desc")) {
1186 monitor_printf(mon, "%s", qdict_get_str(qdict, "desc"));
1187 } else {
1188 monitor_printf(mon, "Class %04" PRId64, qdict_get_int(qdict, "class"));
1189 }
1190
1191 qdict = qdict_get_qdict(device, "id");
1192 monitor_printf(mon, ": PCI device %04" PRIx64 ":%04" PRIx64 "\n",
1193 qdict_get_int(qdict, "device"),
1194 qdict_get_int(qdict, "vendor"));
1195
1196 if (qdict_haskey(device, "irq")) {
1197 monitor_printf(mon, " IRQ %" PRId64 ".\n",
1198 qdict_get_int(device, "irq"));
1199 }
1200
1201 if (qdict_haskey(device, "pci_bridge")) {
1202 QDict *info;
1203
1204 qdict = qdict_get_qdict(device, "pci_bridge");
1205
1206 info = qdict_get_qdict(qdict, "bus");
1207 monitor_printf(mon, " BUS %" PRId64 ".\n",
1208 qdict_get_int(info, "number"));
1209 monitor_printf(mon, " secondary bus %" PRId64 ".\n",
1210 qdict_get_int(info, "secondary"));
1211 monitor_printf(mon, " subordinate bus %" PRId64 ".\n",
1212 qdict_get_int(info, "subordinate"));
1213
1214 info = qdict_get_qdict(qdict, "io_range");
1215 monitor_printf(mon, " IO range [0x%04"PRIx64", 0x%04"PRIx64"]\n",
1216 qdict_get_int(info, "base"),
1217 qdict_get_int(info, "limit"));
1218
1219 info = qdict_get_qdict(qdict, "memory_range");
1220 monitor_printf(mon,
1221 " memory range [0x%08"PRIx64", 0x%08"PRIx64"]\n",
1222 qdict_get_int(info, "base"),
1223 qdict_get_int(info, "limit"));
1224
1225 info = qdict_get_qdict(qdict, "prefetchable_range");
1226 monitor_printf(mon, " prefetchable memory range "
1227 "[0x%08"PRIx64", 0x%08"PRIx64"]\n",
1228 qdict_get_int(info, "base"),
1229 qdict_get_int(info, "limit"));
1230 }
1231
1232 QLIST_FOREACH_ENTRY(qdict_get_qlist(device, "regions"), entry) {
1233 qdict = qobject_to_qdict(qlist_entry_obj(entry));
1234 monitor_printf(mon, " BAR%d: ", (int) qdict_get_int(qdict, "bar"));
1235
1236 addr = qdict_get_int(qdict, "address");
1237 size = qdict_get_int(qdict, "size");
1238
1239 if (!strcmp(qdict_get_str(qdict, "type"), "io")) {
1240 monitor_printf(mon, "I/O at 0x%04"FMT_PCIBUS
1241 " [0x%04"FMT_PCIBUS"].\n",
1242 addr, addr + size - 1);
1243 } else {
1244 monitor_printf(mon, "%d bit%s memory at 0x%08"FMT_PCIBUS
1245 " [0x%08"FMT_PCIBUS"].\n",
1246 qdict_get_bool(qdict, "mem_type_64") ? 64 : 32,
1247 qdict_get_bool(qdict, "prefetch") ?
1248 " prefetchable" : "", addr, addr + size - 1);
1249 }
1250 }
1251
1252 monitor_printf(mon, " id \"%s\"\n", qdict_get_str(device, "qdev_id"));
1253
1254 if (qdict_haskey(device, "pci_bridge")) {
1255 qdict = qdict_get_qdict(device, "pci_bridge");
1256 if (qdict_haskey(qdict, "devices")) {
1257 QListEntry *dev;
1258 QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) {
1259 pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev)));
1260 }
1261 }
1262 }
1263 }
1264
1265 void do_pci_info_print(Monitor *mon, const QObject *data)
1266 {
1267 QListEntry *bus, *dev;
1268
1269 QLIST_FOREACH_ENTRY(qobject_to_qlist(data), bus) {
1270 QDict *qdict = qobject_to_qdict(qlist_entry_obj(bus));
1271 QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) {
1272 pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev)));
1273 }
1274 }
1275 }
1276
1277 static QObject *pci_get_dev_class(const PCIDevice *dev)
1278 {
1279 int class;
1280 const pci_class_desc *desc;
1281
1282 class = pci_get_word(dev->config + PCI_CLASS_DEVICE);
1283 desc = pci_class_descriptions;
1284 while (desc->desc && class != desc->class)
1285 desc++;
1286
1287 if (desc->desc) {
1288 return qobject_from_jsonf("{ 'desc': %s, 'class': %d }",
1289 desc->desc, class);
1290 } else {
1291 return qobject_from_jsonf("{ 'class': %d }", class);
1292 }
1293 }
1294
1295 static QObject *pci_get_dev_id(const PCIDevice *dev)
1296 {
1297 return qobject_from_jsonf("{ 'device': %d, 'vendor': %d }",
1298 pci_get_word(dev->config + PCI_VENDOR_ID),
1299 pci_get_word(dev->config + PCI_DEVICE_ID));
1300 }
1301
1302 static QObject *pci_get_regions_list(const PCIDevice *dev)
1303 {
1304 int i;
1305 QList *regions_list;
1306
1307 regions_list = qlist_new();
1308
1309 for (i = 0; i < PCI_NUM_REGIONS; i++) {
1310 QObject *obj;
1311 const PCIIORegion *r = &dev->io_regions[i];
1312
1313 if (!r->size) {
1314 continue;
1315 }
1316
1317 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1318 obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'io', "
1319 "'address': %" PRId64 ", "
1320 "'size': %" PRId64 " }",
1321 i, r->addr, r->size);
1322 } else {
1323 int mem_type_64 = r->type & PCI_BASE_ADDRESS_MEM_TYPE_64;
1324
1325 obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'memory', "
1326 "'mem_type_64': %i, 'prefetch': %i, "
1327 "'address': %" PRId64 ", "
1328 "'size': %" PRId64 " }",
1329 i, mem_type_64,
1330 r->type & PCI_BASE_ADDRESS_MEM_PREFETCH,
1331 r->addr, r->size);
1332 }
1333
1334 qlist_append_obj(regions_list, obj);
1335 }
1336
1337 return QOBJECT(regions_list);
1338 }
1339
1340 static QObject *pci_get_devices_list(PCIBus *bus, int bus_num);
1341
1342 static QObject *pci_get_dev_dict(PCIDevice *dev, PCIBus *bus, int bus_num)
1343 {
1344 uint8_t type;
1345 QObject *obj;
1346
1347 obj = qobject_from_jsonf("{ 'bus': %d, 'slot': %d, 'function': %d," "'class_info': %p, 'id': %p, 'regions': %p,"
1348 " 'qdev_id': %s }",
1349 bus_num,
1350 PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
1351 pci_get_dev_class(dev), pci_get_dev_id(dev),
1352 pci_get_regions_list(dev),
1353 dev->qdev.id ? dev->qdev.id : "");
1354
1355 if (dev->config[PCI_INTERRUPT_PIN] != 0) {
1356 QDict *qdict = qobject_to_qdict(obj);
1357 qdict_put(qdict, "irq", qint_from_int(dev->config[PCI_INTERRUPT_LINE]));
1358 }
1359
1360 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
1361 if (type == PCI_HEADER_TYPE_BRIDGE) {
1362 QDict *qdict;
1363 QObject *pci_bridge;
1364
1365 pci_bridge = qobject_from_jsonf("{ 'bus': "
1366 "{ 'number': %d, 'secondary': %d, 'subordinate': %d }, "
1367 "'io_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, "
1368 "'memory_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, "
1369 "'prefetchable_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "} }",
1370 dev->config[PCI_PRIMARY_BUS], dev->config[PCI_SECONDARY_BUS],
1371 dev->config[PCI_SUBORDINATE_BUS],
1372 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO),
1373 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO),
1374 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY),
1375 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY),
1376 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY |
1377 PCI_BASE_ADDRESS_MEM_PREFETCH),
1378 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY |
1379 PCI_BASE_ADDRESS_MEM_PREFETCH));
1380
1381 if (dev->config[PCI_SECONDARY_BUS] != 0) {
1382 PCIBus *child_bus = pci_find_bus(bus, dev->config[PCI_SECONDARY_BUS]);
1383
1384 if (child_bus) {
1385 qdict = qobject_to_qdict(pci_bridge);
1386 qdict_put_obj(qdict, "devices",
1387 pci_get_devices_list(child_bus,
1388 dev->config[PCI_SECONDARY_BUS]));
1389 }
1390 }
1391 qdict = qobject_to_qdict(obj);
1392 qdict_put_obj(qdict, "pci_bridge", pci_bridge);
1393 }
1394
1395 return obj;
1396 }
1397
1398 static QObject *pci_get_devices_list(PCIBus *bus, int bus_num)
1399 {
1400 int devfn;
1401 PCIDevice *dev;
1402 QList *dev_list;
1403
1404 dev_list = qlist_new();
1405
1406 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1407 dev = bus->devices[devfn];
1408 if (dev) {
1409 qlist_append_obj(dev_list, pci_get_dev_dict(dev, bus, bus_num));
1410 }
1411 }
1412
1413 return QOBJECT(dev_list);
1414 }
1415
1416 static QObject *pci_get_bus_dict(PCIBus *bus, int bus_num)
1417 {
1418 bus = pci_find_bus(bus, bus_num);
1419 if (bus) {
1420 return qobject_from_jsonf("{ 'bus': %d, 'devices': %p }",
1421 bus_num, pci_get_devices_list(bus, bus_num));
1422 }
1423
1424 return NULL;
1425 }
1426
1427 void do_pci_info(Monitor *mon, QObject **ret_data)
1428 {
1429 QList *bus_list;
1430 struct PCIHostBus *host;
1431
1432 bus_list = qlist_new();
1433
1434 QLIST_FOREACH(host, &host_buses, next) {
1435 QObject *obj = pci_get_bus_dict(host->bus, 0);
1436 if (obj) {
1437 qlist_append_obj(bus_list, obj);
1438 }
1439 }
1440
1441 *ret_data = QOBJECT(bus_list);
1442 }
1443
1444 static const char * const pci_nic_models[] = {
1445 "ne2k_pci",
1446 "i82551",
1447 "i82557b",
1448 "i82559er",
1449 "rtl8139",
1450 "e1000",
1451 "pcnet",
1452 "virtio",
1453 NULL
1454 };
1455
1456 static const char * const pci_nic_names[] = {
1457 "ne2k_pci",
1458 "i82551",
1459 "i82557b",
1460 "i82559er",
1461 "rtl8139",
1462 "e1000",
1463 "pcnet",
1464 "virtio-net-pci",
1465 NULL
1466 };
1467
1468 /* Initialize a PCI NIC. */
1469 /* FIXME callers should check for failure, but don't */
1470 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
1471 const char *default_devaddr)
1472 {
1473 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
1474 PCIBus *bus;
1475 int devfn;
1476 PCIDevice *pci_dev;
1477 DeviceState *dev;
1478 int i;
1479
1480 i = qemu_find_nic_model(nd, pci_nic_models, default_model);
1481 if (i < 0)
1482 return NULL;
1483
1484 bus = pci_get_bus_devfn(&devfn, devaddr);
1485 if (!bus) {
1486 error_report("Invalid PCI device address %s for device %s",
1487 devaddr, pci_nic_names[i]);
1488 return NULL;
1489 }
1490
1491 pci_dev = pci_create(bus, devfn, pci_nic_names[i]);
1492 dev = &pci_dev->qdev;
1493 qdev_set_nic_properties(dev, nd);
1494 if (qdev_init(dev) < 0)
1495 return NULL;
1496 return pci_dev;
1497 }
1498
1499 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
1500 const char *default_devaddr)
1501 {
1502 PCIDevice *res;
1503
1504 if (qemu_show_nic_models(nd->model, pci_nic_models))
1505 exit(0);
1506
1507 res = pci_nic_init(nd, default_model, default_devaddr);
1508 if (!res)
1509 exit(1);
1510 return res;
1511 }
1512
1513 static void pci_bridge_update_mappings_fn(PCIBus *b, PCIDevice *d)
1514 {
1515 pci_update_mappings(d);
1516 }
1517
1518 void pci_bridge_update_mappings(PCIBus *b)
1519 {
1520 PCIBus *child;
1521
1522 pci_for_each_device_under_bus(b, pci_bridge_update_mappings_fn);
1523
1524 QLIST_FOREACH(child, &b->child, sibling) {
1525 pci_bridge_update_mappings(child);
1526 }
1527 }
1528
1529 /* Whether a given bus number is in range of the secondary
1530 * bus of the given bridge device. */
1531 static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num)
1532 {
1533 return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) &
1534 PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ &&
1535 dev->config[PCI_SECONDARY_BUS] < bus_num &&
1536 bus_num <= dev->config[PCI_SUBORDINATE_BUS];
1537 }
1538
1539 PCIBus *pci_find_bus(PCIBus *bus, int bus_num)
1540 {
1541 PCIBus *sec;
1542
1543 if (!bus) {
1544 return NULL;
1545 }
1546
1547 if (pci_bus_num(bus) == bus_num) {
1548 return bus;
1549 }
1550
1551 /* Consider all bus numbers in range for the host pci bridge. */
1552 if (bus->parent_dev &&
1553 !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) {
1554 return NULL;
1555 }
1556
1557 /* try child bus */
1558 for (; bus; bus = sec) {
1559 QLIST_FOREACH(sec, &bus->child, sibling) {
1560 assert(sec->parent_dev);
1561 if (sec->parent_dev->config[PCI_SECONDARY_BUS] == bus_num) {
1562 return sec;
1563 }
1564 if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) {
1565 break;
1566 }
1567 }
1568 }
1569
1570 return NULL;
1571 }
1572
1573 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, int slot, int function)
1574 {
1575 bus = pci_find_bus(bus, bus_num);
1576
1577 if (!bus)
1578 return NULL;
1579
1580 return bus->devices[PCI_DEVFN(slot, function)];
1581 }
1582
1583 static int pci_qdev_init(DeviceState *qdev, DeviceInfo *base)
1584 {
1585 PCIDevice *pci_dev = (PCIDevice *)qdev;
1586 PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev);
1587 PCIBus *bus;
1588 int devfn, rc;
1589 bool is_default_rom;
1590
1591 /* initialize cap_present for pci_is_express() and pci_config_size() */
1592 if (info->is_express) {
1593 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
1594 }
1595
1596 bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
1597 devfn = pci_dev->devfn;
1598 pci_dev = do_pci_register_device(pci_dev, bus, base->name, devfn,
1599 info->config_read, info->config_write,
1600 info->is_bridge);
1601 if (pci_dev == NULL)
1602 return -1;
1603 rc = info->init(pci_dev);
1604 if (rc != 0) {
1605 do_pci_unregister_device(pci_dev);
1606 return rc;
1607 }
1608
1609 /* rom loading */
1610 is_default_rom = false;
1611 if (pci_dev->romfile == NULL && info->romfile != NULL) {
1612 pci_dev->romfile = qemu_strdup(info->romfile);
1613 is_default_rom = true;
1614 }
1615 pci_add_option_rom(pci_dev, is_default_rom);
1616
1617 if (bus->hotplug) {
1618 /* Let buses differentiate between hotplug and when device is
1619 * enabled during qemu machine creation. */
1620 rc = bus->hotplug(bus->hotplug_qdev, pci_dev,
1621 qdev->hotplugged ? PCI_HOTPLUG_ENABLED:
1622 PCI_COLDPLUG_ENABLED);
1623 if (rc != 0) {
1624 int r = pci_unregister_device(&pci_dev->qdev);
1625 assert(!r);
1626 return rc;
1627 }
1628 }
1629 return 0;
1630 }
1631
1632 static int pci_unplug_device(DeviceState *qdev)
1633 {
1634 PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev);
1635
1636 return dev->bus->hotplug(dev->bus->hotplug_qdev, dev,
1637 PCI_HOTPLUG_DISABLED);
1638 }
1639
1640 void pci_qdev_register(PCIDeviceInfo *info)
1641 {
1642 info->qdev.init = pci_qdev_init;
1643 info->qdev.unplug = pci_unplug_device;
1644 info->qdev.exit = pci_unregister_device;
1645 info->qdev.bus_info = &pci_bus_info;
1646 qdev_register(&info->qdev);
1647 }
1648
1649 void pci_qdev_register_many(PCIDeviceInfo *info)
1650 {
1651 while (info->qdev.name) {
1652 pci_qdev_register(info);
1653 info++;
1654 }
1655 }
1656
1657 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
1658 const char *name)
1659 {
1660 DeviceState *dev;
1661
1662 dev = qdev_create(&bus->qbus, name);
1663 qdev_prop_set_uint32(dev, "addr", devfn);
1664 qdev_prop_set_bit(dev, "multifunction", multifunction);
1665 return DO_UPCAST(PCIDevice, qdev, dev);
1666 }
1667
1668 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
1669 bool multifunction,
1670 const char *name)
1671 {
1672 PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name);
1673 qdev_init_nofail(&dev->qdev);
1674 return dev;
1675 }
1676
1677 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
1678 {
1679 return pci_create_multifunction(bus, devfn, false, name);
1680 }
1681
1682 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
1683 {
1684 return pci_create_simple_multifunction(bus, devfn, false, name);
1685 }
1686
1687 static int pci_find_space(PCIDevice *pdev, uint8_t size)
1688 {
1689 int config_size = pci_config_size(pdev);
1690 int offset = PCI_CONFIG_HEADER_SIZE;
1691 int i;
1692 for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; ++i)
1693 if (pdev->used[i])
1694 offset = i + 1;
1695 else if (i - offset + 1 == size)
1696 return offset;
1697 return 0;
1698 }
1699
1700 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
1701 uint8_t *prev_p)
1702 {
1703 uint8_t next, prev;
1704
1705 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
1706 return 0;
1707
1708 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1709 prev = next + PCI_CAP_LIST_NEXT)
1710 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
1711 break;
1712
1713 if (prev_p)
1714 *prev_p = prev;
1715 return next;
1716 }
1717
1718 static void pci_map_option_rom(PCIDevice *pdev, int region_num, pcibus_t addr, pcibus_t size, int type)
1719 {
1720 cpu_register_physical_memory(addr, size, pdev->rom_offset);
1721 }
1722
1723 /* Patch the PCI vendor and device ids in a PCI rom image if necessary.
1724 This is needed for an option rom which is used for more than one device. */
1725 static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size)
1726 {
1727 uint16_t vendor_id;
1728 uint16_t device_id;
1729 uint16_t rom_vendor_id;
1730 uint16_t rom_device_id;
1731 uint16_t rom_magic;
1732 uint16_t pcir_offset;
1733 uint8_t checksum;
1734
1735 /* Words in rom data are little endian (like in PCI configuration),
1736 so they can be read / written with pci_get_word / pci_set_word. */
1737
1738 /* Only a valid rom will be patched. */
1739 rom_magic = pci_get_word(ptr);
1740 if (rom_magic != 0xaa55) {
1741 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic);
1742 return;
1743 }
1744 pcir_offset = pci_get_word(ptr + 0x18);
1745 if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) {
1746 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset);
1747 return;
1748 }
1749
1750 vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID);
1751 device_id = pci_get_word(pdev->config + PCI_DEVICE_ID);
1752 rom_vendor_id = pci_get_word(ptr + pcir_offset + 4);
1753 rom_device_id = pci_get_word(ptr + pcir_offset + 6);
1754
1755 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile,
1756 vendor_id, device_id, rom_vendor_id, rom_device_id);
1757
1758 checksum = ptr[6];
1759
1760 if (vendor_id != rom_vendor_id) {
1761 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */
1762 checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8);
1763 checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8);
1764 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
1765 ptr[6] = checksum;
1766 pci_set_word(ptr + pcir_offset + 4, vendor_id);
1767 }
1768
1769 if (device_id != rom_device_id) {
1770 /* Patch device id and checksum (at offset 6 for etherboot roms). */
1771 checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8);
1772 checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8);
1773 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
1774 ptr[6] = checksum;
1775 pci_set_word(ptr + pcir_offset + 6, device_id);
1776 }
1777 }
1778
1779 /* Add an option rom for the device */
1780 static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom)
1781 {
1782 int size;
1783 char *path;
1784 void *ptr;
1785 char name[32];
1786
1787 if (!pdev->romfile)
1788 return 0;
1789 if (strlen(pdev->romfile) == 0)
1790 return 0;
1791
1792 if (!pdev->rom_bar) {
1793 /*
1794 * Load rom via fw_cfg instead of creating a rom bar,
1795 * for 0.11 compatibility.
1796 */
1797 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE);
1798 if (class == 0x0300) {
1799 rom_add_vga(pdev->romfile);
1800 } else {
1801 rom_add_option(pdev->romfile);
1802 }
1803 return 0;
1804 }
1805
1806 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile);
1807 if (path == NULL) {
1808 path = qemu_strdup(pdev->romfile);
1809 }
1810
1811 size = get_image_size(path);
1812 if (size < 0) {
1813 error_report("%s: failed to find romfile \"%s\"",
1814 __FUNCTION__, pdev->romfile);
1815 return -1;
1816 }
1817 if (size & (size - 1)) {
1818 size = 1 << qemu_fls(size);
1819 }
1820
1821 if (pdev->qdev.info->vmsd)
1822 snprintf(name, sizeof(name), "%s.rom", pdev->qdev.info->vmsd->name);
1823 else
1824 snprintf(name, sizeof(name), "%s.rom", pdev->qdev.info->name);
1825 pdev->rom_offset = qemu_ram_alloc(&pdev->qdev, name, size);
1826
1827 ptr = qemu_get_ram_ptr(pdev->rom_offset);
1828 load_image(path, ptr);
1829 qemu_free(path);
1830
1831 if (is_default_rom) {
1832 /* Only the default rom images will be patched (if needed). */
1833 pci_patch_ids(pdev, ptr, size);
1834 }
1835
1836 pci_register_bar(pdev, PCI_ROM_SLOT, size,
1837 0, pci_map_option_rom);
1838
1839 return 0;
1840 }
1841
1842 static void pci_del_option_rom(PCIDevice *pdev)
1843 {
1844 if (!pdev->rom_offset)
1845 return;
1846
1847 qemu_ram_free(pdev->rom_offset);
1848 pdev->rom_offset = 0;
1849 }
1850
1851 /*
1852 * if !offset
1853 * Reserve space and add capability to the linked list in pci config space
1854 *
1855 * if offset = 0,
1856 * Find and reserve space and add capability to the linked list
1857 * in pci config space */
1858 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
1859 uint8_t offset, uint8_t size)
1860 {
1861 uint8_t *config;
1862 if (!offset) {
1863 offset = pci_find_space(pdev, size);
1864 if (!offset) {
1865 return -ENOSPC;
1866 }
1867 }
1868
1869 config = pdev->config + offset;
1870 config[PCI_CAP_LIST_ID] = cap_id;
1871 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
1872 pdev->config[PCI_CAPABILITY_LIST] = offset;
1873 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
1874 memset(pdev->used + offset, 0xFF, size);
1875 /* Make capability read-only by default */
1876 memset(pdev->wmask + offset, 0, size);
1877 /* Check capability by default */
1878 memset(pdev->cmask + offset, 0xFF, size);
1879 return offset;
1880 }
1881
1882 /* Unlink capability from the pci config space. */
1883 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1884 {
1885 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
1886 if (!offset)
1887 return;
1888 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
1889 /* Make capability writeable again */
1890 memset(pdev->wmask + offset, 0xff, size);
1891 memset(pdev->w1cmask + offset, 0, size);
1892 /* Clear cmask as device-specific registers can't be checked */
1893 memset(pdev->cmask + offset, 0, size);
1894 memset(pdev->used + offset, 0, size);
1895
1896 if (!pdev->config[PCI_CAPABILITY_LIST])
1897 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
1898 }
1899
1900 /* Reserve space for capability at a known offset (to call after load). */
1901 void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size)
1902 {
1903 memset(pdev->used + offset, 0xff, size);
1904 }
1905
1906 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
1907 {
1908 return pci_find_capability_list(pdev, cap_id, NULL);
1909 }
1910
1911 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
1912 {
1913 PCIDevice *d = (PCIDevice *)dev;
1914 const pci_class_desc *desc;
1915 char ctxt[64];
1916 PCIIORegion *r;
1917 int i, class;
1918
1919 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
1920 desc = pci_class_descriptions;
1921 while (desc->desc && class != desc->class)
1922 desc++;
1923 if (desc->desc) {
1924 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
1925 } else {
1926 snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
1927 }
1928
1929 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
1930 "pci id %04x:%04x (sub %04x:%04x)\n",
1931 indent, "", ctxt, pci_bus_num(d->bus),
1932 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
1933 pci_get_word(d->config + PCI_VENDOR_ID),
1934 pci_get_word(d->config + PCI_DEVICE_ID),
1935 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
1936 pci_get_word(d->config + PCI_SUBSYSTEM_ID));
1937 for (i = 0; i < PCI_NUM_REGIONS; i++) {
1938 r = &d->io_regions[i];
1939 if (!r->size)
1940 continue;
1941 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
1942 " [0x%"FMT_PCIBUS"]\n",
1943 indent, "",
1944 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
1945 r->addr, r->addr + r->size - 1);
1946 }
1947 }
1948
1949 static char *pcibus_get_dev_path(DeviceState *dev)
1950 {
1951 PCIDevice *d = (PCIDevice *)dev;
1952 char path[16];
1953
1954 snprintf(path, sizeof(path), "%04x:%02x:%02x.%x",
1955 pci_find_domain(d->bus), d->config[PCI_SECONDARY_BUS],
1956 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn));
1957
1958 return strdup(path);
1959 }
1960
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