target-i386/kvm.c

   1 /*
   2  * QEMU KVM support
   3  *
   4  * Copyright (C) 2006-2008 Qumranet Technologies
   5  * Copyright IBM, Corp. 2008
   6  *
   7  * Authors:
   8  *  Anthony Liguori   <aliguori@us.ibm.com>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  11  * See the COPYING file in the top-level directory.
  12  *
  13  */
  14
  15 #include <sys/types.h>
  16 #include <sys/ioctl.h>
  17 #include <sys/mman.h>
  18
  19 #include <linux/kvm.h>
  20
  21 #include "qemu-common.h"
  22 #include "sysemu.h"
  23 #include "kvm.h"
  24 #include "cpu.h"
  25 #include "gdbstub.h"
  26 #include "host-utils.h"
  27 #include "hw/pc.h"
  28 #include "ioport.h"
  29
  30 #ifdef CONFIG_KVM_PARA
  31 #include <linux/kvm_para.h>
  32 #endif
  33 //
  34 //#define DEBUG_KVM
  35
  36 #ifdef DEBUG_KVM
  37 #define DPRINTF(fmt, ...) \
  38     do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
  39 #else
  40 #define DPRINTF(fmt, ...) \
  41     do { } while (0)
  42 #endif
  43
  44 #define MSR_KVM_WALL_CLOCK  0x11
  45 #define MSR_KVM_SYSTEM_TIME 0x12
  46
  47 #ifdef KVM_CAP_EXT_CPUID
  48
  49 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
  50 {
  51     struct kvm_cpuid2 *cpuid;
  52     int r, size;
  53
  54     size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
  55     cpuid = (struct kvm_cpuid2 *)qemu_mallocz(size);
  56     cpuid->nent = max;
  57     r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
  58     if (r == 0 && cpuid->nent >= max) {
  59         r = -E2BIG;
  60     }
  61     if (r < 0) {
  62         if (r == -E2BIG) {
  63             qemu_free(cpuid);
  64             return NULL;
  65         } else {
  66             fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
  67                     strerror(-r));
  68             exit(1);
  69         }
  70     }
  71     return cpuid;
  72 }
  73
  74 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function, int reg)
  75 {
  76     struct kvm_cpuid2 *cpuid;
  77     int i, max;
  78     uint32_t ret = 0;
  79     uint32_t cpuid_1_edx;
  80
  81     if (!kvm_check_extension(env->kvm_state, KVM_CAP_EXT_CPUID)) {
  82         return -1U;
  83     }
  84
  85     max = 1;
  86     while ((cpuid = try_get_cpuid(env->kvm_state, max)) == NULL) {
  87         max *= 2;
  88     }
  89
  90     for (i = 0; i < cpuid->nent; ++i) {
  91         if (cpuid->entries[i].function == function) {
  92             switch (reg) {
  93             case R_EAX:
  94                 ret = cpuid->entries[i].eax;
  95                 break;
  96             case R_EBX:
  97                 ret = cpuid->entries[i].ebx;
  98                 break;
  99             case R_ECX:
 100                 ret = cpuid->entries[i].ecx;
 101                 break;
 102             case R_EDX:
 103                 ret = cpuid->entries[i].edx;
 104                 switch (function) {
 105                 case 1:
 106                     /* KVM before 2.6.30 misreports the following features */
 107                     ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
 108                     break;
 109                 case 0x80000001:
 110                     /* On Intel, kvm returns cpuid according to the Intel spec,
 111                      * so add missing bits according to the AMD spec:
 112                      */
 113                     cpuid_1_edx = kvm_arch_get_supported_cpuid(env, 1, R_EDX);
 114                     ret |= cpuid_1_edx & 0x183f7ff;
 115                     break;
 116                 }
 117                 break;
 118             }
 119         }
 120     }
 121
 122     qemu_free(cpuid);
 123
 124     return ret;
 125 }
 126
 127 #else
 128
 129 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function, int reg)
 130 {
 131     return -1U;
 132 }
 133
 134 #endif
 135
 136 #ifdef CONFIG_KVM_PARA
 137 struct kvm_para_features {
 138         int cap;
 139         int feature;
 140 } para_features[] = {
 141 #ifdef KVM_CAP_CLOCKSOURCE
 142         { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
 143 #endif
 144 #ifdef KVM_CAP_NOP_IO_DELAY
 145         { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
 146 #endif
 147 #ifdef KVM_CAP_PV_MMU
 148         { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
 149 #endif
 150         { -1, -1 }
 151 };
 152
 153 static int get_para_features(CPUState *env)
 154 {
 155         int i, features = 0;
 156
 157         for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) {
 158                 if (kvm_check_extension(env->kvm_state, para_features[i].cap))
 159                         features |= (1 << para_features[i].feature);
 160         }
 161
 162         return features;
 163 }
 164 #endif
 165
 166 int kvm_arch_init_vcpu(CPUState *env)
 167 {
 168     struct {
 169         struct kvm_cpuid2 cpuid;
 170         struct kvm_cpuid_entry2 entries[100];
 171     } __attribute__((packed)) cpuid_data;
 172     uint32_t limit, i, j, cpuid_i;
 173     uint32_t unused;
 174     struct kvm_cpuid_entry2 *c;
 175 #ifdef KVM_CPUID_SIGNATURE
 176     uint32_t signature[3];
 177 #endif
 178
 179     env->mp_state = KVM_MP_STATE_RUNNABLE;
 180
 181     env->cpuid_features &= kvm_arch_get_supported_cpuid(env, 1, R_EDX);
 182
 183     i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR;
 184     env->cpuid_ext_features &= kvm_arch_get_supported_cpuid(env, 1, R_ECX);
 185     env->cpuid_ext_features |= i;
 186
 187     env->cpuid_ext2_features &= kvm_arch_get_supported_cpuid(env, 0x80000001,
 188                                                              R_EDX);
 189     env->cpuid_ext3_features &= kvm_arch_get_supported_cpuid(env, 0x80000001,
 190                                                              R_ECX);
 191
 192     cpuid_i = 0;
 193
 194 #ifdef CONFIG_KVM_PARA
 195     /* Paravirtualization CPUIDs */
 196     memcpy(signature, "KVMKVMKVM\0\0\0", 12);
 197     c = &cpuid_data.entries[cpuid_i++];
 198     memset(c, 0, sizeof(*c));
 199     c->function = KVM_CPUID_SIGNATURE;
 200     c->eax = 0;
 201     c->ebx = signature[0];
 202     c->ecx = signature[1];
 203     c->edx = signature[2];
 204
 205     c = &cpuid_data.entries[cpuid_i++];
 206     memset(c, 0, sizeof(*c));
 207     c->function = KVM_CPUID_FEATURES;
 208     c->eax = env->cpuid_kvm_features & get_para_features(env);
 209 #endif
 210
 211     cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
 212
 213     for (i = 0; i <= limit; i++) {
 214         c = &cpuid_data.entries[cpuid_i++];
 215
 216         switch (i) {
 217         case 2: {
 218             /* Keep reading function 2 till all the input is received */
 219             int times;
 220
 221             c->function = i;
 222             c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
 223                        KVM_CPUID_FLAG_STATE_READ_NEXT;
 224             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 225             times = c->eax & 0xff;
 226
 227             for (j = 1; j < times; ++j) {
 228                 c = &cpuid_data.entries[cpuid_i++];
 229                 c->function = i;
 230                 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
 231                 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 232             }
 233             break;
 234         }
 235         case 4:
 236         case 0xb:
 237         case 0xd:
 238             for (j = 0; ; j++) {
 239                 c->function = i;
 240                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
 241                 c->index = j;
 242                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
 243
 244                 if (i == 4 && c->eax == 0)
 245                     break;
 246                 if (i == 0xb && !(c->ecx & 0xff00))
 247                     break;
 248                 if (i == 0xd && c->eax == 0)
 249                     break;
 250
 251                 c = &cpuid_data.entries[cpuid_i++];
 252             }
 253             break;
 254         default:
 255             c->function = i;
 256             c->flags = 0;
 257             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 258             break;
 259         }
 260     }
 261     cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
 262
 263     for (i = 0x80000000; i <= limit; i++) {
 264         c = &cpuid_data.entries[cpuid_i++];
 265
 266         c->function = i;
 267         c->flags = 0;
 268         cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 269     }
 270
 271     cpuid_data.cpuid.nent = cpuid_i;
 272
 273     return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
 274 }
 275
 276 void kvm_arch_reset_vcpu(CPUState *env)
 277 {
 278     env->exception_injected = -1;
 279     env->interrupt_injected = -1;
 280     env->nmi_injected = 0;
 281     env->nmi_pending = 0;
 282 }
 283
 284 static int kvm_has_msr_star(CPUState *env)
 285 {
 286     static int has_msr_star;
 287     int ret;
 288
 289     /* first time */
 290     if (has_msr_star == 0) {
 291         struct kvm_msr_list msr_list, *kvm_msr_list;
 292
 293         has_msr_star = -1;
 294
 295         /* Obtain MSR list from KVM.  These are the MSRs that we must
 296          * save/restore */
 297         msr_list.nmsrs = 0;
 298         ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, &msr_list);
 299         if (ret < 0 && ret != -E2BIG) {
 300             return 0;
 301         }
 302         /* Old kernel modules had a bug and could write beyond the provided
 303            memory. Allocate at least a safe amount of 1K. */
 304         kvm_msr_list = qemu_mallocz(MAX(1024, sizeof(msr_list) +
 305                                               msr_list.nmsrs *
 306                                               sizeof(msr_list.indices[0])));
 307
 308         kvm_msr_list->nmsrs = msr_list.nmsrs;
 309         ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
 310         if (ret >= 0) {
 311             int i;
 312
 313             for (i = 0; i < kvm_msr_list->nmsrs; i++) {
 314                 if (kvm_msr_list->indices[i] == MSR_STAR) {
 315                     has_msr_star = 1;
 316                     break;
 317                 }
 318             }
 319         }
 320
 321         free(kvm_msr_list);
 322     }
 323
 324     if (has_msr_star == 1)
 325         return 1;
 326     return 0;
 327 }
 328
 329 static int kvm_init_identity_map_page(KVMState *s)
 330 {
 331 #ifdef KVM_CAP_SET_IDENTITY_MAP_ADDR
 332     int ret;
 333     uint64_t addr = 0xfffbc000;
 334
 335     if (!kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
 336         return 0;
 337     }
 338
 339     ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &addr);
 340     if (ret < 0) {
 341         fprintf(stderr, "kvm_set_identity_map_addr: %s\n", strerror(ret));
 342         return ret;
 343     }
 344 #endif
 345     return 0;
 346 }
 347
 348 int kvm_arch_init(KVMState *s, int smp_cpus)
 349 {
 350     int ret;
 351
 352     /* create vm86 tss.  KVM uses vm86 mode to emulate 16-bit code
 353      * directly.  In order to use vm86 mode, a TSS is needed.  Since this
 354      * must be part of guest physical memory, we need to allocate it.  Older
 355      * versions of KVM just assumed that it would be at the end of physical
 356      * memory but that doesn't work with more than 4GB of memory.  We simply
 357      * refuse to work with those older versions of KVM. */
 358     ret = kvm_ioctl(s, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR);
 359     if (ret <= 0) {
 360         fprintf(stderr, "kvm does not support KVM_CAP_SET_TSS_ADDR\n");
 361         return ret;
 362     }
 363
 364     /* this address is 3 pages before the bios, and the bios should present
 365      * as unavaible memory.  FIXME, need to ensure the e820 map deals with
 366      * this?
 367      */
 368     /*
 369      * Tell fw_cfg to notify the BIOS to reserve the range.
 370      */
 371     if (e820_add_entry(0xfffbc000, 0x4000, E820_RESERVED) < 0) {
 372         perror("e820_add_entry() table is full");
 373         exit(1);
 374     }
 375     ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, 0xfffbd000);
 376     if (ret < 0) {
 377         return ret;
 378     }
 379
 380     return kvm_init_identity_map_page(s);
 381 }
 382
 383 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 384 {
 385     lhs->selector = rhs->selector;
 386     lhs->base = rhs->base;
 387     lhs->limit = rhs->limit;
 388     lhs->type = 3;
 389     lhs->present = 1;
 390     lhs->dpl = 3;
 391     lhs->db = 0;
 392     lhs->s = 1;
 393     lhs->l = 0;
 394     lhs->g = 0;
 395     lhs->avl = 0;
 396     lhs->unusable = 0;
 397 }
 398
 399 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 400 {
 401     unsigned flags = rhs->flags;
 402     lhs->selector = rhs->selector;
 403     lhs->base = rhs->base;
 404     lhs->limit = rhs->limit;
 405     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
 406     lhs->present = (flags & DESC_P_MASK) != 0;
 407     lhs->dpl = rhs->selector & 3;
 408     lhs->db = (flags >> DESC_B_SHIFT) & 1;
 409     lhs->s = (flags & DESC_S_MASK) != 0;
 410     lhs->l = (flags >> DESC_L_SHIFT) & 1;
 411     lhs->g = (flags & DESC_G_MASK) != 0;
 412     lhs->avl = (flags & DESC_AVL_MASK) != 0;
 413     lhs->unusable = 0;
 414 }
 415
 416 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
 417 {
 418     lhs->selector = rhs->selector;
 419     lhs->base = rhs->base;
 420     lhs->limit = rhs->limit;
 421     lhs->flags =
 422         (rhs->type << DESC_TYPE_SHIFT)
 423         | (rhs->present * DESC_P_MASK)
 424         | (rhs->dpl << DESC_DPL_SHIFT)
 425         | (rhs->db << DESC_B_SHIFT)
 426         | (rhs->s * DESC_S_MASK)
 427         | (rhs->l << DESC_L_SHIFT)
 428         | (rhs->g * DESC_G_MASK)
 429         | (rhs->avl * DESC_AVL_MASK);
 430 }
 431
 432 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
 433 {
 434     if (set)
 435         *kvm_reg = *qemu_reg;
 436     else
 437         *qemu_reg = *kvm_reg;
 438 }
 439
 440 static int kvm_getput_regs(CPUState *env, int set)
 441 {
 442     struct kvm_regs regs;
 443     int ret = 0;
 444
 445     if (!set) {
 446         ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
 447         if (ret < 0)
 448             return ret;
 449     }
 450
 451     kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
 452     kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
 453     kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
 454     kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
 455     kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
 456     kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
 457     kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
 458     kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
 459 #ifdef TARGET_X86_64
 460     kvm_getput_reg(&regs.r8, &env->regs[8], set);
 461     kvm_getput_reg(&regs.r9, &env->regs[9], set);
 462     kvm_getput_reg(&regs.r10, &env->regs[10], set);
 463     kvm_getput_reg(&regs.r11, &env->regs[11], set);
 464     kvm_getput_reg(&regs.r12, &env->regs[12], set);
 465     kvm_getput_reg(&regs.r13, &env->regs[13], set);
 466     kvm_getput_reg(&regs.r14, &env->regs[14], set);
 467     kvm_getput_reg(&regs.r15, &env->regs[15], set);
 468 #endif
 469
 470     kvm_getput_reg(&regs.rflags, &env->eflags, set);
 471     kvm_getput_reg(&regs.rip, &env->eip, set);
 472
 473     if (set)
 474         ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
 475
 476     return ret;
 477 }
 478
 479 static int kvm_put_fpu(CPUState *env)
 480 {
 481     struct kvm_fpu fpu;
 482     int i;
 483
 484     memset(&fpu, 0, sizeof fpu);
 485     fpu.fsw = env->fpus & ~(7 << 11);
 486     fpu.fsw |= (env->fpstt & 7) << 11;
 487     fpu.fcw = env->fpuc;
 488     for (i = 0; i < 8; ++i)
 489         fpu.ftwx |= (!env->fptags[i]) << i;
 490     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
 491     memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
 492     fpu.mxcsr = env->mxcsr;
 493
 494     return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
 495 }
 496
 497 static int kvm_put_sregs(CPUState *env)
 498 {
 499     struct kvm_sregs sregs;
 500
 501     memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
 502     if (env->interrupt_injected >= 0) {
 503         sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
 504                 (uint64_t)1 << (env->interrupt_injected % 64);
 505     }
 506
 507     if ((env->eflags & VM_MASK)) {
 508             set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
 509             set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
 510             set_v8086_seg(&sregs.es, &env->segs[R_ES]);
 511             set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
 512             set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
 513             set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
 514     } else {
 515             set_seg(&sregs.cs, &env->segs[R_CS]);
 516             set_seg(&sregs.ds, &env->segs[R_DS]);
 517             set_seg(&sregs.es, &env->segs[R_ES]);
 518             set_seg(&sregs.fs, &env->segs[R_FS]);
 519             set_seg(&sregs.gs, &env->segs[R_GS]);
 520             set_seg(&sregs.ss, &env->segs[R_SS]);
 521
 522             if (env->cr[0] & CR0_PE_MASK) {
 523                 /* force ss cpl to cs cpl */
 524                 sregs.ss.selector = (sregs.ss.selector & ~3) |
 525                         (sregs.cs.selector & 3);
 526                 sregs.ss.dpl = sregs.ss.selector & 3;
 527             }
 528     }
 529
 530     set_seg(&sregs.tr, &env->tr);
 531     set_seg(&sregs.ldt, &env->ldt);
 532
 533     sregs.idt.limit = env->idt.limit;
 534     sregs.idt.base = env->idt.base;
 535     sregs.gdt.limit = env->gdt.limit;
 536     sregs.gdt.base = env->gdt.base;
 537
 538     sregs.cr0 = env->cr[0];
 539     sregs.cr2 = env->cr[2];
 540     sregs.cr3 = env->cr[3];
 541     sregs.cr4 = env->cr[4];
 542
 543     sregs.cr8 = cpu_get_apic_tpr(env->apic_state);
 544     sregs.apic_base = cpu_get_apic_base(env->apic_state);
 545
 546     sregs.efer = env->efer;
 547
 548     return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
 549 }
 550
 551 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
 552                               uint32_t index, uint64_t value)
 553 {
 554     entry->index = index;
 555     entry->data = value;
 556 }
 557
 558 static int kvm_put_msrs(CPUState *env, int level)
 559 {
 560     struct {
 561         struct kvm_msrs info;
 562         struct kvm_msr_entry entries[100];
 563     } msr_data;
 564     struct kvm_msr_entry *msrs = msr_data.entries;
 565     int n = 0;
 566
 567     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
 568     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
 569     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
 570     if (kvm_has_msr_star(env))
 571         kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
 572 #ifdef TARGET_X86_64
 573     /* FIXME if lm capable */
 574     kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
 575     kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
 576     kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
 577     kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
 578 #endif
 579     if (level == KVM_PUT_FULL_STATE) {
 580         kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
 581         kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
 582                           env->system_time_msr);
 583         kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
 584     }
 585
 586     msr_data.info.nmsrs = n;
 587
 588     return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
 589
 590 }
 591
 592
 593 static int kvm_get_fpu(CPUState *env)
 594 {
 595     struct kvm_fpu fpu;
 596     int i, ret;
 597
 598     ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
 599     if (ret < 0)
 600         return ret;
 601
 602     env->fpstt = (fpu.fsw >> 11) & 7;
 603     env->fpus = fpu.fsw;
 604     env->fpuc = fpu.fcw;
 605     for (i = 0; i < 8; ++i)
 606         env->fptags[i] = !((fpu.ftwx >> i) & 1);
 607     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
 608     memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
 609     env->mxcsr = fpu.mxcsr;
 610
 611     return 0;
 612 }
 613
 614 static int kvm_get_sregs(CPUState *env)
 615 {
 616     struct kvm_sregs sregs;
 617     uint32_t hflags;
 618     int bit, i, ret;
 619
 620     ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
 621     if (ret < 0)
 622         return ret;
 623
 624     /* There can only be one pending IRQ set in the bitmap at a time, so try
 625        to find it and save its number instead (-1 for none). */
 626     env->interrupt_injected = -1;
 627     for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
 628         if (sregs.interrupt_bitmap[i]) {
 629             bit = ctz64(sregs.interrupt_bitmap[i]);
 630             env->interrupt_injected = i * 64 + bit;
 631             break;
 632         }
 633     }
 634
 635     get_seg(&env->segs[R_CS], &sregs.cs);
 636     get_seg(&env->segs[R_DS], &sregs.ds);
 637     get_seg(&env->segs[R_ES], &sregs.es);
 638     get_seg(&env->segs[R_FS], &sregs.fs);
 639     get_seg(&env->segs[R_GS], &sregs.gs);
 640     get_seg(&env->segs[R_SS], &sregs.ss);
 641
 642     get_seg(&env->tr, &sregs.tr);
 643     get_seg(&env->ldt, &sregs.ldt);
 644
 645     env->idt.limit = sregs.idt.limit;
 646     env->idt.base = sregs.idt.base;
 647     env->gdt.limit = sregs.gdt.limit;
 648     env->gdt.base = sregs.gdt.base;
 649
 650     env->cr[0] = sregs.cr0;
 651     env->cr[2] = sregs.cr2;
 652     env->cr[3] = sregs.cr3;
 653     env->cr[4] = sregs.cr4;
 654
 655     cpu_set_apic_base(env->apic_state, sregs.apic_base);
 656
 657     env->efer = sregs.efer;
 658     //cpu_set_apic_tpr(env->apic_state, sregs.cr8);
 659
 660 #define HFLAG_COPY_MASK ~( \
 661                         HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
 662                         HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
 663                         HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
 664                         HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
 665
 666
 667
 668     hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
 669     hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
 670     hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
 671             (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
 672     hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
 673     hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
 674             (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
 675
 676     if (env->efer & MSR_EFER_LMA) {
 677         hflags |= HF_LMA_MASK;
 678     }
 679
 680     if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
 681         hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
 682     } else {
 683         hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
 684                 (DESC_B_SHIFT - HF_CS32_SHIFT);
 685         hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
 686                 (DESC_B_SHIFT - HF_SS32_SHIFT);
 687         if (!(env->cr[0] & CR0_PE_MASK) ||
 688                    (env->eflags & VM_MASK) ||
 689                    !(hflags & HF_CS32_MASK)) {
 690                 hflags |= HF_ADDSEG_MASK;
 691             } else {
 692                 hflags |= ((env->segs[R_DS].base |
 693                                 env->segs[R_ES].base |
 694                                 env->segs[R_SS].base) != 0) <<
 695                     HF_ADDSEG_SHIFT;
 696             }
 697     }
 698     env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
 699
 700     return 0;
 701 }
 702
 703 static int kvm_get_msrs(CPUState *env)
 704 {
 705     struct {
 706         struct kvm_msrs info;
 707         struct kvm_msr_entry entries[100];
 708     } msr_data;
 709     struct kvm_msr_entry *msrs = msr_data.entries;
 710     int ret, i, n;
 711
 712     n = 0;
 713     msrs[n++].index = MSR_IA32_SYSENTER_CS;
 714     msrs[n++].index = MSR_IA32_SYSENTER_ESP;
 715     msrs[n++].index = MSR_IA32_SYSENTER_EIP;
 716     if (kvm_has_msr_star(env))
 717         msrs[n++].index = MSR_STAR;
 718     msrs[n++].index = MSR_IA32_TSC;
 719 #ifdef TARGET_X86_64
 720     /* FIXME lm_capable_kernel */
 721     msrs[n++].index = MSR_CSTAR;
 722     msrs[n++].index = MSR_KERNELGSBASE;
 723     msrs[n++].index = MSR_FMASK;
 724     msrs[n++].index = MSR_LSTAR;
 725 #endif
 726     msrs[n++].index = MSR_KVM_SYSTEM_TIME;
 727     msrs[n++].index = MSR_KVM_WALL_CLOCK;
 728
 729     msr_data.info.nmsrs = n;
 730     ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
 731     if (ret < 0)
 732         return ret;
 733
 734     for (i = 0; i < ret; i++) {
 735         switch (msrs[i].index) {
 736         case MSR_IA32_SYSENTER_CS:
 737             env->sysenter_cs = msrs[i].data;
 738             break;
 739         case MSR_IA32_SYSENTER_ESP:
 740             env->sysenter_esp = msrs[i].data;
 741             break;
 742         case MSR_IA32_SYSENTER_EIP:
 743             env->sysenter_eip = msrs[i].data;
 744             break;
 745         case MSR_STAR:
 746             env->star = msrs[i].data;
 747             break;
 748 #ifdef TARGET_X86_64
 749         case MSR_CSTAR:
 750             env->cstar = msrs[i].data;
 751             break;
 752         case MSR_KERNELGSBASE:
 753             env->kernelgsbase = msrs[i].data;
 754             break;
 755         case MSR_FMASK:
 756             env->fmask = msrs[i].data;
 757             break;
 758         case MSR_LSTAR:
 759             env->lstar = msrs[i].data;
 760             break;
 761 #endif
 762         case MSR_IA32_TSC:
 763             env->tsc = msrs[i].data;
 764             break;
 765         case MSR_KVM_SYSTEM_TIME:
 766             env->system_time_msr = msrs[i].data;
 767             break;
 768         case MSR_KVM_WALL_CLOCK:
 769             env->wall_clock_msr = msrs[i].data;
 770             break;
 771         }
 772     }
 773
 774     return 0;
 775 }
 776
 777 static int kvm_put_mp_state(CPUState *env)
 778 {
 779     struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
 780
 781     return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state);
 782 }
 783
 784 static int kvm_get_mp_state(CPUState *env)
 785 {
 786     struct kvm_mp_state mp_state;
 787     int ret;
 788
 789     ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE, &mp_state);
 790     if (ret < 0) {
 791         return ret;
 792     }
 793     env->mp_state = mp_state.mp_state;
 794     return 0;
 795 }
 796
 797 static int kvm_put_vcpu_events(CPUState *env, int level)
 798 {
 799 #ifdef KVM_CAP_VCPU_EVENTS
 800     struct kvm_vcpu_events events;
 801
 802     if (!kvm_has_vcpu_events()) {
 803         return 0;
 804     }
 805
 806     events.exception.injected = (env->exception_injected >= 0);
 807     events.exception.nr = env->exception_injected;
 808     events.exception.has_error_code = env->has_error_code;
 809     events.exception.error_code = env->error_code;
 810
 811     events.interrupt.injected = (env->interrupt_injected >= 0);
 812     events.interrupt.nr = env->interrupt_injected;
 813     events.interrupt.soft = env->soft_interrupt;
 814
 815     events.nmi.injected = env->nmi_injected;
 816     events.nmi.pending = env->nmi_pending;
 817     events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
 818
 819     events.sipi_vector = env->sipi_vector;
 820
 821     events.flags = 0;
 822     if (level >= KVM_PUT_RESET_STATE) {
 823         events.flags |=
 824             KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
 825     }
 826
 827     return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events);
 828 #else
 829     return 0;
 830 #endif
 831 }
 832
 833 static int kvm_get_vcpu_events(CPUState *env)
 834 {
 835 #ifdef KVM_CAP_VCPU_EVENTS
 836     struct kvm_vcpu_events events;
 837     int ret;
 838
 839     if (!kvm_has_vcpu_events()) {
 840         return 0;
 841     }
 842
 843     ret = kvm_vcpu_ioctl(env, KVM_GET_VCPU_EVENTS, &events);
 844     if (ret < 0) {
 845        return ret;
 846     }
 847     env->exception_injected =
 848        events.exception.injected ? events.exception.nr : -1;
 849     env->has_error_code = events.exception.has_error_code;
 850     env->error_code = events.exception.error_code;
 851
 852     env->interrupt_injected =
 853         events.interrupt.injected ? events.interrupt.nr : -1;
 854     env->soft_interrupt = events.interrupt.soft;
 855
 856     env->nmi_injected = events.nmi.injected;
 857     env->nmi_pending = events.nmi.pending;
 858     if (events.nmi.masked) {
 859         env->hflags2 |= HF2_NMI_MASK;
 860     } else {
 861         env->hflags2 &= ~HF2_NMI_MASK;
 862     }
 863
 864     env->sipi_vector = events.sipi_vector;
 865 #endif
 866
 867     return 0;
 868 }
 869
 870 static int kvm_guest_debug_workarounds(CPUState *env)
 871 {
 872     int ret = 0;
 873 #ifdef KVM_CAP_SET_GUEST_DEBUG
 874     unsigned long reinject_trap = 0;
 875
 876     if (!kvm_has_vcpu_events()) {
 877         if (env->exception_injected == 1) {
 878             reinject_trap = KVM_GUESTDBG_INJECT_DB;
 879         } else if (env->exception_injected == 3) {
 880             reinject_trap = KVM_GUESTDBG_INJECT_BP;
 881         }
 882         env->exception_injected = -1;
 883     }
 884
 885     /*
 886      * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
 887      * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
 888      * by updating the debug state once again if single-stepping is on.
 889      * Another reason to call kvm_update_guest_debug here is a pending debug
 890      * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
 891      * reinject them via SET_GUEST_DEBUG.
 892      */
 893     if (reinject_trap ||
 894         (!kvm_has_robust_singlestep() && env->singlestep_enabled)) {
 895         ret = kvm_update_guest_debug(env, reinject_trap);
 896     }
 897 #endif /* KVM_CAP_SET_GUEST_DEBUG */
 898     return ret;
 899 }
 900
 901 static int kvm_put_debugregs(CPUState *env)
 902 {
 903 #ifdef KVM_CAP_DEBUGREGS
 904     struct kvm_debugregs dbgregs;
 905     int i;
 906
 907     if (!kvm_has_debugregs()) {
 908         return 0;
 909     }
 910
 911     for (i = 0; i < 4; i++) {
 912         dbgregs.db[i] = env->dr[i];
 913     }
 914     dbgregs.dr6 = env->dr[6];
 915     dbgregs.dr7 = env->dr[7];
 916     dbgregs.flags = 0;
 917
 918     return kvm_vcpu_ioctl(env, KVM_SET_DEBUGREGS, &dbgregs);
 919 #else
 920     return 0;
 921 #endif
 922 }
 923
 924 static int kvm_get_debugregs(CPUState *env)
 925 {
 926 #ifdef KVM_CAP_DEBUGREGS
 927     struct kvm_debugregs dbgregs;
 928     int i, ret;
 929
 930     if (!kvm_has_debugregs()) {
 931         return 0;
 932     }
 933
 934     ret = kvm_vcpu_ioctl(env, KVM_GET_DEBUGREGS, &dbgregs);
 935     if (ret < 0) {
 936        return ret;
 937     }
 938     for (i = 0; i < 4; i++) {
 939         env->dr[i] = dbgregs.db[i];
 940     }
 941     env->dr[4] = env->dr[6] = dbgregs.dr6;
 942     env->dr[5] = env->dr[7] = dbgregs.dr7;
 943 #endif
 944
 945     return 0;
 946 }
 947
 948 int kvm_arch_put_registers(CPUState *env, int level)
 949 {
 950     int ret;
 951
 952     assert(cpu_is_stopped(env) || qemu_cpu_self(env));
 953
 954     ret = kvm_getput_regs(env, 1);
 955     if (ret < 0)
 956         return ret;
 957
 958     ret = kvm_put_fpu(env);
 959     if (ret < 0)
 960         return ret;
 961
 962     ret = kvm_put_sregs(env);
 963     if (ret < 0)
 964         return ret;
 965
 966     ret = kvm_put_msrs(env, level);
 967     if (ret < 0)
 968         return ret;
 969
 970     if (level >= KVM_PUT_RESET_STATE) {
 971         ret = kvm_put_mp_state(env);
 972         if (ret < 0)
 973             return ret;
 974     }
 975
 976     ret = kvm_put_vcpu_events(env, level);
 977     if (ret < 0)
 978         return ret;
 979
 980     /* must be last */
 981     ret = kvm_guest_debug_workarounds(env);
 982     if (ret < 0)
 983         return ret;
 984
 985     ret = kvm_put_debugregs(env);
 986     if (ret < 0)
 987         return ret;
 988
 989     return 0;
 990 }
 991
 992 int kvm_arch_get_registers(CPUState *env)
 993 {
 994     int ret;
 995
 996     assert(cpu_is_stopped(env) || qemu_cpu_self(env));
 997
 998     ret = kvm_getput_regs(env, 0);
 999     if (ret < 0)
1000         return ret;
1001
1002     ret = kvm_get_fpu(env);
1003     if (ret < 0)
1004         return ret;
1005
1006     ret = kvm_get_sregs(env);
1007     if (ret < 0)
1008         return ret;
1009
1010     ret = kvm_get_msrs(env);
1011     if (ret < 0)
1012         return ret;
1013
1014     ret = kvm_get_mp_state(env);
1015     if (ret < 0)
1016         return ret;
1017
1018     ret = kvm_get_vcpu_events(env);
1019     if (ret < 0)
1020         return ret;
1021
1022     ret = kvm_get_debugregs(env);
1023     if (ret < 0)
1024         return ret;
1025
1026     return 0;
1027 }
1028
1029 int kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
1030 {
1031     /* Try to inject an interrupt if the guest can accept it */
1032     if (run->ready_for_interrupt_injection &&
1033         (env->interrupt_request & CPU_INTERRUPT_HARD) &&
1034         (env->eflags & IF_MASK)) {
1035         int irq;
1036
1037         env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1038         irq = cpu_get_pic_interrupt(env);
1039         if (irq >= 0) {
1040             struct kvm_interrupt intr;
1041             intr.irq = irq;
1042             /* FIXME: errors */
1043             DPRINTF("injected interrupt %d\n", irq);
1044             kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
1045         }
1046     }
1047
1048     /* If we have an interrupt but the guest is not ready to receive an
1049      * interrupt, request an interrupt window exit.  This will
1050      * cause a return to userspace as soon as the guest is ready to
1051      * receive interrupts. */
1052     if ((env->interrupt_request & CPU_INTERRUPT_HARD))
1053         run->request_interrupt_window = 1;
1054     else
1055         run->request_interrupt_window = 0;
1056
1057     DPRINTF("setting tpr\n");
1058     run->cr8 = cpu_get_apic_tpr(env->apic_state);
1059
1060     return 0;
1061 }
1062
1063 int kvm_arch_post_run(CPUState *env, struct kvm_run *run)
1064 {
1065     if (run->if_flag)
1066         env->eflags |= IF_MASK;
1067     else
1068         env->eflags &= ~IF_MASK;
1069
1070     cpu_set_apic_tpr(env->apic_state, run->cr8);
1071     cpu_set_apic_base(env->apic_state, run->apic_base);
1072
1073     return 0;
1074 }
1075
1076 int kvm_arch_process_irqchip_events(CPUState *env)
1077 {
1078     if (env->interrupt_request & CPU_INTERRUPT_INIT) {
1079         kvm_cpu_synchronize_state(env);
1080         do_cpu_init(env);
1081         env->exception_index = EXCP_HALTED;
1082     }
1083
1084     if (env->interrupt_request & CPU_INTERRUPT_SIPI) {
1085         kvm_cpu_synchronize_state(env);
1086         do_cpu_sipi(env);
1087     }
1088
1089     return env->halted;
1090 }
1091
1092 static int kvm_handle_halt(CPUState *env)
1093 {
1094     if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1095           (env->eflags & IF_MASK)) &&
1096         !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
1097         env->halted = 1;
1098         env->exception_index = EXCP_HLT;
1099         return 0;
1100     }
1101
1102     return 1;
1103 }
1104
1105 int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
1106 {
1107     int ret = 0;
1108
1109     switch (run->exit_reason) {
1110     case KVM_EXIT_HLT:
1111         DPRINTF("handle_hlt\n");
1112         ret = kvm_handle_halt(env);
1113         break;
1114     }
1115
1116     return ret;
1117 }
1118
1119 #ifdef KVM_CAP_SET_GUEST_DEBUG
1120 int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1121 {
1122     static const uint8_t int3 = 0xcc;
1123
1124     if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
1125         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1))
1126         return -EINVAL;
1127     return 0;
1128 }
1129
1130 int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1131 {
1132     uint8_t int3;
1133
1134     if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
1135         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1))
1136         return -EINVAL;
1137     return 0;
1138 }
1139
1140 static struct {
1141     target_ulong addr;
1142     int len;
1143     int type;
1144 } hw_breakpoint[4];
1145
1146 static int nb_hw_breakpoint;
1147
1148 static int find_hw_breakpoint(target_ulong addr, int len, int type)
1149 {
1150     int n;
1151
1152     for (n = 0; n < nb_hw_breakpoint; n++)
1153         if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
1154             (hw_breakpoint[n].len == len || len == -1))
1155             return n;
1156     return -1;
1157 }
1158
1159 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1160                                   target_ulong len, int type)
1161 {
1162     switch (type) {
1163     case GDB_BREAKPOINT_HW:
1164         len = 1;
1165         break;
1166     case GDB_WATCHPOINT_WRITE:
1167     case GDB_WATCHPOINT_ACCESS:
1168         switch (len) {
1169         case 1:
1170             break;
1171         case 2:
1172         case 4:
1173         case 8:
1174             if (addr & (len - 1))
1175                 return -EINVAL;
1176             break;
1177         default:
1178             return -EINVAL;
1179         }
1180         break;
1181     default:
1182         return -ENOSYS;
1183     }
1184
1185     if (nb_hw_breakpoint == 4)
1186         return -ENOBUFS;
1187
1188     if (find_hw_breakpoint(addr, len, type) >= 0)
1189         return -EEXIST;
1190
1191     hw_breakpoint[nb_hw_breakpoint].addr = addr;
1192     hw_breakpoint[nb_hw_breakpoint].len = len;
1193     hw_breakpoint[nb_hw_breakpoint].type = type;
1194     nb_hw_breakpoint++;
1195
1196     return 0;
1197 }
1198
1199 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1200                                   target_ulong len, int type)
1201 {
1202     int n;
1203
1204     n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
1205     if (n < 0)
1206         return -ENOENT;
1207
1208     nb_hw_breakpoint--;
1209     hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
1210
1211     return 0;
1212 }
1213
1214 void kvm_arch_remove_all_hw_breakpoints(void)
1215 {
1216     nb_hw_breakpoint = 0;
1217 }
1218
1219 static CPUWatchpoint hw_watchpoint;
1220
1221 int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info)
1222 {
1223     int handle = 0;
1224     int n;
1225
1226     if (arch_info->exception == 1) {
1227         if (arch_info->dr6 & (1 << 14)) {
1228             if (cpu_single_env->singlestep_enabled)
1229                 handle = 1;
1230         } else {
1231             for (n = 0; n < 4; n++)
1232                 if (arch_info->dr6 & (1 << n))
1233                     switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
1234                     case 0x0:
1235                         handle = 1;
1236                         break;
1237                     case 0x1:
1238                         handle = 1;
1239                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1240                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1241                         hw_watchpoint.flags = BP_MEM_WRITE;
1242                         break;
1243                     case 0x3:
1244                         handle = 1;
1245                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1246                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1247                         hw_watchpoint.flags = BP_MEM_ACCESS;
1248                         break;
1249                     }
1250         }
1251     } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc))
1252         handle = 1;
1253
1254     if (!handle) {
1255         cpu_synchronize_state(cpu_single_env);
1256         assert(cpu_single_env->exception_injected == -1);
1257
1258         cpu_single_env->exception_injected = arch_info->exception;
1259         cpu_single_env->has_error_code = 0;
1260     }
1261
1262     return handle;
1263 }
1264
1265 void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg)
1266 {
1267     const uint8_t type_code[] = {
1268         [GDB_BREAKPOINT_HW] = 0x0,
1269         [GDB_WATCHPOINT_WRITE] = 0x1,
1270         [GDB_WATCHPOINT_ACCESS] = 0x3
1271     };
1272     const uint8_t len_code[] = {
1273         [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
1274     };
1275     int n;
1276
1277     if (kvm_sw_breakpoints_active(env))
1278         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1279
1280     if (nb_hw_breakpoint > 0) {
1281         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1282         dbg->arch.debugreg[7] = 0x0600;
1283         for (n = 0; n < nb_hw_breakpoint; n++) {
1284             dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
1285             dbg->arch.debugreg[7] |= (2 << (n * 2)) |
1286                 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
1287                 (len_code[hw_breakpoint[n].len] << (18 + n*4));
1288         }
1289     }
1290 }
1291 #endif /* KVM_CAP_SET_GUEST_DEBUG */
1292
1293 bool kvm_arch_stop_on_emulation_error(CPUState *env)
1294 {
1295       return !(env->cr[0] & CR0_PE_MASK) ||
1296               ((env->segs[R_CS].selector  & 3) != 3);
1297 }
1298