hw/sun4u.c

   1 /*
   2  * QEMU Sun4u/Sun4v System Emulator
   3  *
   4  * Copyright (c) 2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pci.h"
  26 #include "apb_pci.h"
  27 #include "pc.h"
  28 #include "nvram.h"
  29 #include "fdc.h"
  30 #include "net.h"
  31 #include "qemu-timer.h"
  32 #include "sysemu.h"
  33 #include "boards.h"
  34 #include "firmware_abi.h"
  35 #include "fw_cfg.h"
  36 #include "sysbus.h"
  37 #include "ide.h"
  38 #include "loader.h"
  39 #include "elf.h"
  40 #include "blockdev.h"
  41 #include "exec-memory.h"
  42
  43 //#define DEBUG_IRQ
  44 //#define DEBUG_EBUS
  45 //#define DEBUG_TIMER
  46
  47 #ifdef DEBUG_IRQ
  48 #define CPUIRQ_DPRINTF(fmt, ...)                                \
  49     do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
  50 #else
  51 #define CPUIRQ_DPRINTF(fmt, ...)
  52 #endif
  53
  54 #ifdef DEBUG_EBUS
  55 #define EBUS_DPRINTF(fmt, ...)                                  \
  56     do { printf("EBUS: " fmt , ## __VA_ARGS__); } while (0)
  57 #else
  58 #define EBUS_DPRINTF(fmt, ...)
  59 #endif
  60
  61 #ifdef DEBUG_TIMER
  62 #define TIMER_DPRINTF(fmt, ...)                                  \
  63     do { printf("TIMER: " fmt , ## __VA_ARGS__); } while (0)
  64 #else
  65 #define TIMER_DPRINTF(fmt, ...)
  66 #endif
  67
  68 #define KERNEL_LOAD_ADDR     0x00404000
  69 #define CMDLINE_ADDR         0x003ff000
  70 #define INITRD_LOAD_ADDR     0x00300000
  71 #define PROM_SIZE_MAX        (4 * 1024 * 1024)
  72 #define PROM_VADDR           0x000ffd00000ULL
  73 #define APB_SPECIAL_BASE     0x1fe00000000ULL
  74 #define APB_MEM_BASE         0x1ff00000000ULL
  75 #define APB_PCI_IO_BASE      (APB_SPECIAL_BASE + 0x02000000ULL)
  76 #define PROM_FILENAME        "openbios-sparc64"
  77 #define NVRAM_SIZE           0x2000
  78 #define MAX_IDE_BUS          2
  79 #define BIOS_CFG_IOPORT      0x510
  80 #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
  81 #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
  82 #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
  83
  84 #define IVEC_MAX             0x30
  85
  86 #define TICK_MAX             0x7fffffffffffffffULL
  87
  88 struct hwdef {
  89     const char * const default_cpu_model;
  90     uint16_t machine_id;
  91     uint64_t prom_addr;
  92     uint64_t console_serial_base;
  93 };
  94
  95 typedef struct EbusState {
  96     PCIDevice pci_dev;
  97     MemoryRegion bar0;
  98     MemoryRegion bar1;
  99 } EbusState;
 100
 101 int DMA_get_channel_mode (int nchan)
 102 {
 103     return 0;
 104 }
 105 int DMA_read_memory (int nchan, void *buf, int pos, int size)
 106 {
 107     return 0;
 108 }
 109 int DMA_write_memory (int nchan, void *buf, int pos, int size)
 110 {
 111     return 0;
 112 }
 113 void DMA_hold_DREQ (int nchan) {}
 114 void DMA_release_DREQ (int nchan) {}
 115 void DMA_schedule(int nchan) {}
 116
 117 void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit)
 118 {
 119 }
 120
 121 void DMA_register_channel (int nchan,
 122                            DMA_transfer_handler transfer_handler,
 123                            void *opaque)
 124 {
 125 }
 126
 127 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
 128 {
 129     fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
 130     return 0;
 131 }
 132
 133 static int sun4u_NVRAM_set_params(M48t59State *nvram, uint16_t NVRAM_size,
 134                                   const char *arch, ram_addr_t RAM_size,
 135                                   const char *boot_devices,
 136                                   uint32_t kernel_image, uint32_t kernel_size,
 137                                   const char *cmdline,
 138                                   uint32_t initrd_image, uint32_t initrd_size,
 139                                   uint32_t NVRAM_image,
 140                                   int width, int height, int depth,
 141                                   const uint8_t *macaddr)
 142 {
 143     unsigned int i;
 144     uint32_t start, end;
 145     uint8_t image[0x1ff0];
 146     struct OpenBIOS_nvpart_v1 *part_header;
 147
 148     memset(image, '\0', sizeof(image));
 149
 150     start = 0;
 151
 152     // OpenBIOS nvram variables
 153     // Variable partition
 154     part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
 155     part_header->signature = OPENBIOS_PART_SYSTEM;
 156     pstrcpy(part_header->name, sizeof(part_header->name), "system");
 157
 158     end = start + sizeof(struct OpenBIOS_nvpart_v1);
 159     for (i = 0; i < nb_prom_envs; i++)
 160         end = OpenBIOS_set_var(image, end, prom_envs[i]);
 161
 162     // End marker
 163     image[end++] = '\0';
 164
 165     end = start + ((end - start + 15) & ~15);
 166     OpenBIOS_finish_partition(part_header, end - start);
 167
 168     // free partition
 169     start = end;
 170     part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
 171     part_header->signature = OPENBIOS_PART_FREE;
 172     pstrcpy(part_header->name, sizeof(part_header->name), "free");
 173
 174     end = 0x1fd0;
 175     OpenBIOS_finish_partition(part_header, end - start);
 176
 177     Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80);
 178
 179     for (i = 0; i < sizeof(image); i++)
 180         m48t59_write(nvram, i, image[i]);
 181
 182     return 0;
 183 }
 184 static unsigned long sun4u_load_kernel(const char *kernel_filename,
 185                                        const char *initrd_filename,
 186                                        ram_addr_t RAM_size, long *initrd_size)
 187 {
 188     int linux_boot;
 189     unsigned int i;
 190     long kernel_size;
 191     uint8_t *ptr;
 192
 193     linux_boot = (kernel_filename != NULL);
 194
 195     kernel_size = 0;
 196     if (linux_boot) {
 197         int bswap_needed;
 198
 199 #ifdef BSWAP_NEEDED
 200         bswap_needed = 1;
 201 #else
 202         bswap_needed = 0;
 203 #endif
 204         kernel_size = load_elf(kernel_filename, NULL, NULL, NULL,
 205                                NULL, NULL, 1, ELF_MACHINE, 0);
 206         if (kernel_size < 0)
 207             kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
 208                                     RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
 209                                     TARGET_PAGE_SIZE);
 210         if (kernel_size < 0)
 211             kernel_size = load_image_targphys(kernel_filename,
 212                                               KERNEL_LOAD_ADDR,
 213                                               RAM_size - KERNEL_LOAD_ADDR);
 214         if (kernel_size < 0) {
 215             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 216                     kernel_filename);
 217             exit(1);
 218         }
 219
 220         /* load initrd */
 221         *initrd_size = 0;
 222         if (initrd_filename) {
 223             *initrd_size = load_image_targphys(initrd_filename,
 224                                                INITRD_LOAD_ADDR,
 225                                                RAM_size - INITRD_LOAD_ADDR);
 226             if (*initrd_size < 0) {
 227                 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 228                         initrd_filename);
 229                 exit(1);
 230             }
 231         }
 232         if (*initrd_size > 0) {
 233             for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
 234                 ptr = rom_ptr(KERNEL_LOAD_ADDR + i);
 235                 if (ldl_p(ptr + 8) == 0x48647253) { /* HdrS */
 236                     stl_p(ptr + 24, INITRD_LOAD_ADDR + KERNEL_LOAD_ADDR - 0x4000);
 237                     stl_p(ptr + 28, *initrd_size);
 238                     break;
 239                 }
 240             }
 241         }
 242     }
 243     return kernel_size;
 244 }
 245
 246 void cpu_check_irqs(CPUSPARCState *env)
 247 {
 248     uint32_t pil = env->pil_in |
 249                   (env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER));
 250
 251     /* check if TM or SM in SOFTINT are set
 252        setting these also causes interrupt 14 */
 253     if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) {
 254         pil |= 1 << 14;
 255     }
 256
 257     /* The bit corresponding to psrpil is (1<< psrpil), the next bit
 258        is (2 << psrpil). */
 259     if (pil < (2 << env->psrpil)){
 260         if (env->interrupt_request & CPU_INTERRUPT_HARD) {
 261             CPUIRQ_DPRINTF("Reset CPU IRQ (current interrupt %x)\n",
 262                            env->interrupt_index);
 263             env->interrupt_index = 0;
 264             cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 265         }
 266         return;
 267     }
 268
 269     if (cpu_interrupts_enabled(env)) {
 270
 271         unsigned int i;
 272
 273         for (i = 15; i > env->psrpil; i--) {
 274             if (pil & (1 << i)) {
 275                 int old_interrupt = env->interrupt_index;
 276                 int new_interrupt = TT_EXTINT | i;
 277
 278                 if (env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt) {
 279                     CPUIRQ_DPRINTF("Not setting CPU IRQ: TL=%d "
 280                                    "current %x >= pending %x\n",
 281                                    env->tl, cpu_tsptr(env)->tt, new_interrupt);
 282                 } else if (old_interrupt != new_interrupt) {
 283                     env->interrupt_index = new_interrupt;
 284                     CPUIRQ_DPRINTF("Set CPU IRQ %d old=%x new=%x\n", i,
 285                                    old_interrupt, new_interrupt);
 286                     cpu_interrupt(env, CPU_INTERRUPT_HARD);
 287                 }
 288                 break;
 289             }
 290         }
 291     } else if (env->interrupt_request & CPU_INTERRUPT_HARD) {
 292         CPUIRQ_DPRINTF("Interrupts disabled, pil=%08x pil_in=%08x softint=%08x "
 293                        "current interrupt %x\n",
 294                        pil, env->pil_in, env->softint, env->interrupt_index);
 295         env->interrupt_index = 0;
 296         cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 297     }
 298 }
 299
 300 static void cpu_kick_irq(CPUSPARCState *env)
 301 {
 302     env->halted = 0;
 303     cpu_check_irqs(env);
 304     qemu_cpu_kick(env);
 305 }
 306
 307 static void cpu_set_ivec_irq(void *opaque, int irq, int level)
 308 {
 309     CPUSPARCState *env = opaque;
 310
 311     if (level) {
 312         CPUIRQ_DPRINTF("Raise IVEC IRQ %d\n", irq);
 313         env->interrupt_index = TT_IVEC;
 314         env->pil_in |= 1 << 5;
 315         env->ivec_status |= 0x20;
 316         env->ivec_data[0] = (0x1f << 6) | irq;
 317         env->ivec_data[1] = 0;
 318         env->ivec_data[2] = 0;
 319         cpu_interrupt(env, CPU_INTERRUPT_HARD);
 320       } else {
 321         CPUIRQ_DPRINTF("Lower IVEC IRQ %d\n", irq);
 322         env->pil_in &= ~(1 << 5);
 323         env->ivec_status &= ~0x20;
 324         cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 325     }
 326 }
 327
 328 typedef struct ResetData {
 329     CPUSPARCState *env;
 330     uint64_t prom_addr;
 331 } ResetData;
 332
 333 void cpu_put_timer(QEMUFile *f, CPUTimer *s)
 334 {
 335     qemu_put_be32s(f, &s->frequency);
 336     qemu_put_be32s(f, &s->disabled);
 337     qemu_put_be64s(f, &s->disabled_mask);
 338     qemu_put_sbe64s(f, &s->clock_offset);
 339
 340     qemu_put_timer(f, s->qtimer);
 341 }
 342
 343 void cpu_get_timer(QEMUFile *f, CPUTimer *s)
 344 {
 345     qemu_get_be32s(f, &s->frequency);
 346     qemu_get_be32s(f, &s->disabled);
 347     qemu_get_be64s(f, &s->disabled_mask);
 348     qemu_get_sbe64s(f, &s->clock_offset);
 349
 350     qemu_get_timer(f, s->qtimer);
 351 }
 352
 353 static CPUTimer* cpu_timer_create(const char* name, CPUSPARCState *env,
 354                                   QEMUBHFunc *cb, uint32_t frequency,
 355                                   uint64_t disabled_mask)
 356 {
 357     CPUTimer *timer = g_malloc0(sizeof (CPUTimer));
 358
 359     timer->name = name;
 360     timer->frequency = frequency;
 361     timer->disabled_mask = disabled_mask;
 362
 363     timer->disabled = 1;
 364     timer->clock_offset = qemu_get_clock_ns(vm_clock);
 365
 366     timer->qtimer = qemu_new_timer_ns(vm_clock, cb, env);
 367
 368     return timer;
 369 }
 370
 371 static void cpu_timer_reset(CPUTimer *timer)
 372 {
 373     timer->disabled = 1;
 374     timer->clock_offset = qemu_get_clock_ns(vm_clock);
 375
 376     qemu_del_timer(timer->qtimer);
 377 }
 378
 379 static void main_cpu_reset(void *opaque)
 380 {
 381     ResetData *s = (ResetData *)opaque;
 382     CPUSPARCState *env = s->env;
 383     static unsigned int nr_resets;
 384
 385     cpu_state_reset(env);
 386
 387     cpu_timer_reset(env->tick);
 388     cpu_timer_reset(env->stick);
 389     cpu_timer_reset(env->hstick);
 390
 391     env->gregs[1] = 0; // Memory start
 392     env->gregs[2] = ram_size; // Memory size
 393     env->gregs[3] = 0; // Machine description XXX
 394     if (nr_resets++ == 0) {
 395         /* Power on reset */
 396         env->pc = s->prom_addr + 0x20ULL;
 397     } else {
 398         env->pc = s->prom_addr + 0x40ULL;
 399     }
 400     env->npc = env->pc + 4;
 401 }
 402
 403 static void tick_irq(void *opaque)
 404 {
 405     CPUSPARCState *env = opaque;
 406
 407     CPUTimer* timer = env->tick;
 408
 409     if (timer->disabled) {
 410         CPUIRQ_DPRINTF("tick_irq: softint disabled\n");
 411         return;
 412     } else {
 413         CPUIRQ_DPRINTF("tick: fire\n");
 414     }
 415
 416     env->softint |= SOFTINT_TIMER;
 417     cpu_kick_irq(env);
 418 }
 419
 420 static void stick_irq(void *opaque)
 421 {
 422     CPUSPARCState *env = opaque;
 423
 424     CPUTimer* timer = env->stick;
 425
 426     if (timer->disabled) {
 427         CPUIRQ_DPRINTF("stick_irq: softint disabled\n");
 428         return;
 429     } else {
 430         CPUIRQ_DPRINTF("stick: fire\n");
 431     }
 432
 433     env->softint |= SOFTINT_STIMER;
 434     cpu_kick_irq(env);
 435 }
 436
 437 static void hstick_irq(void *opaque)
 438 {
 439     CPUSPARCState *env = opaque;
 440
 441     CPUTimer* timer = env->hstick;
 442
 443     if (timer->disabled) {
 444         CPUIRQ_DPRINTF("hstick_irq: softint disabled\n");
 445         return;
 446     } else {
 447         CPUIRQ_DPRINTF("hstick: fire\n");
 448     }
 449
 450     env->softint |= SOFTINT_STIMER;
 451     cpu_kick_irq(env);
 452 }
 453
 454 static int64_t cpu_to_timer_ticks(int64_t cpu_ticks, uint32_t frequency)
 455 {
 456     return muldiv64(cpu_ticks, get_ticks_per_sec(), frequency);
 457 }
 458
 459 static uint64_t timer_to_cpu_ticks(int64_t timer_ticks, uint32_t frequency)
 460 {
 461     return muldiv64(timer_ticks, frequency, get_ticks_per_sec());
 462 }
 463
 464 void cpu_tick_set_count(CPUTimer *timer, uint64_t count)
 465 {
 466     uint64_t real_count = count & ~timer->disabled_mask;
 467     uint64_t disabled_bit = count & timer->disabled_mask;
 468
 469     int64_t vm_clock_offset = qemu_get_clock_ns(vm_clock) -
 470                     cpu_to_timer_ticks(real_count, timer->frequency);
 471
 472     TIMER_DPRINTF("%s set_count count=0x%016lx (%s) p=%p\n",
 473                   timer->name, real_count,
 474                   timer->disabled?"disabled":"enabled", timer);
 475
 476     timer->disabled = disabled_bit ? 1 : 0;
 477     timer->clock_offset = vm_clock_offset;
 478 }
 479
 480 uint64_t cpu_tick_get_count(CPUTimer *timer)
 481 {
 482     uint64_t real_count = timer_to_cpu_ticks(
 483                     qemu_get_clock_ns(vm_clock) - timer->clock_offset,
 484                     timer->frequency);
 485
 486     TIMER_DPRINTF("%s get_count count=0x%016lx (%s) p=%p\n",
 487            timer->name, real_count,
 488            timer->disabled?"disabled":"enabled", timer);
 489
 490     if (timer->disabled)
 491         real_count |= timer->disabled_mask;
 492
 493     return real_count;
 494 }
 495
 496 void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit)
 497 {
 498     int64_t now = qemu_get_clock_ns(vm_clock);
 499
 500     uint64_t real_limit = limit & ~timer->disabled_mask;
 501     timer->disabled = (limit & timer->disabled_mask) ? 1 : 0;
 502
 503     int64_t expires = cpu_to_timer_ticks(real_limit, timer->frequency) +
 504                     timer->clock_offset;
 505
 506     if (expires < now) {
 507         expires = now + 1;
 508     }
 509
 510     TIMER_DPRINTF("%s set_limit limit=0x%016lx (%s) p=%p "
 511                   "called with limit=0x%016lx at 0x%016lx (delta=0x%016lx)\n",
 512                   timer->name, real_limit,
 513                   timer->disabled?"disabled":"enabled",
 514                   timer, limit,
 515                   timer_to_cpu_ticks(now - timer->clock_offset,
 516                                      timer->frequency),
 517                   timer_to_cpu_ticks(expires - now, timer->frequency));
 518
 519     if (!real_limit) {
 520         TIMER_DPRINTF("%s set_limit limit=ZERO - not starting timer\n",
 521                 timer->name);
 522         qemu_del_timer(timer->qtimer);
 523     } else if (timer->disabled) {
 524         qemu_del_timer(timer->qtimer);
 525     } else {
 526         qemu_mod_timer(timer->qtimer, expires);
 527     }
 528 }
 529
 530 static void isa_irq_handler(void *opaque, int n, int level)
 531 {
 532     static const int isa_irq_to_ivec[16] = {
 533         [1] = 0x29, /* keyboard */
 534         [4] = 0x2b, /* serial */
 535         [6] = 0x27, /* floppy */
 536         [7] = 0x22, /* parallel */
 537         [12] = 0x2a, /* mouse */
 538     };
 539     qemu_irq *irqs = opaque;
 540     int ivec;
 541
 542     assert(n < 16);
 543     ivec = isa_irq_to_ivec[n];
 544     EBUS_DPRINTF("Set ISA IRQ %d level %d -> ivec 0x%x\n", n, level, ivec);
 545     if (ivec) {
 546         qemu_set_irq(irqs[ivec], level);
 547     }
 548 }
 549
 550 /* EBUS (Eight bit bus) bridge */
 551 static ISABus *
 552 pci_ebus_init(PCIBus *bus, int devfn, qemu_irq *irqs)
 553 {
 554     qemu_irq *isa_irq;
 555     PCIDevice *pci_dev;
 556     ISABus *isa_bus;
 557
 558     pci_dev = pci_create_simple(bus, devfn, "ebus");
 559     isa_bus = DO_UPCAST(ISABus, qbus,
 560                         qdev_get_child_bus(&pci_dev->qdev, "isa.0"));
 561     isa_irq = qemu_allocate_irqs(isa_irq_handler, irqs, 16);
 562     isa_bus_irqs(isa_bus, isa_irq);
 563     return isa_bus;
 564 }
 565
 566 static int
 567 pci_ebus_init1(PCIDevice *pci_dev)
 568 {
 569     EbusState *s = DO_UPCAST(EbusState, pci_dev, pci_dev);
 570
 571     isa_bus_new(&pci_dev->qdev, pci_address_space_io(pci_dev));
 572
 573     pci_dev->config[0x04] = 0x06; // command = bus master, pci mem
 574     pci_dev->config[0x05] = 0x00;
 575     pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
 576     pci_dev->config[0x07] = 0x03; // status = medium devsel
 577     pci_dev->config[0x09] = 0x00; // programming i/f
 578     pci_dev->config[0x0D] = 0x0a; // latency_timer
 579
 580     isa_mmio_setup(&s->bar0, 0x1000000);
 581     pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0);
 582     isa_mmio_setup(&s->bar1, 0x800000);
 583     pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar1);
 584     return 0;
 585 }
 586
 587 static void ebus_class_init(ObjectClass *klass, void *data)
 588 {
 589     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 590
 591     k->init = pci_ebus_init1;
 592     k->vendor_id = PCI_VENDOR_ID_SUN;
 593     k->device_id = PCI_DEVICE_ID_SUN_EBUS;
 594     k->revision = 0x01;
 595     k->class_id = PCI_CLASS_BRIDGE_OTHER;
 596 }
 597
 598 static TypeInfo ebus_info = {
 599     .name          = "ebus",
 600     .parent        = TYPE_PCI_DEVICE,
 601     .instance_size = sizeof(EbusState),
 602     .class_init    = ebus_class_init,
 603 };
 604
 605 typedef struct PROMState {
 606     SysBusDevice busdev;
 607     MemoryRegion prom;
 608 } PROMState;
 609
 610 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
 611 {
 612     target_phys_addr_t *base_addr = (target_phys_addr_t *)opaque;
 613     return addr + *base_addr - PROM_VADDR;
 614 }
 615
 616 /* Boot PROM (OpenBIOS) */
 617 static void prom_init(target_phys_addr_t addr, const char *bios_name)
 618 {
 619     DeviceState *dev;
 620     SysBusDevice *s;
 621     char *filename;
 622     int ret;
 623
 624     dev = qdev_create(NULL, "openprom");
 625     qdev_init_nofail(dev);
 626     s = sysbus_from_qdev(dev);
 627
 628     sysbus_mmio_map(s, 0, addr);
 629
 630     /* load boot prom */
 631     if (bios_name == NULL) {
 632         bios_name = PROM_FILENAME;
 633     }
 634     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 635     if (filename) {
 636         ret = load_elf(filename, translate_prom_address, &addr,
 637                        NULL, NULL, NULL, 1, ELF_MACHINE, 0);
 638         if (ret < 0 || ret > PROM_SIZE_MAX) {
 639             ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
 640         }
 641         g_free(filename);
 642     } else {
 643         ret = -1;
 644     }
 645     if (ret < 0 || ret > PROM_SIZE_MAX) {
 646         fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
 647         exit(1);
 648     }
 649 }
 650
 651 static int prom_init1(SysBusDevice *dev)
 652 {
 653     PROMState *s = FROM_SYSBUS(PROMState, dev);
 654
 655     memory_region_init_ram(&s->prom, "sun4u.prom", PROM_SIZE_MAX);
 656     vmstate_register_ram_global(&s->prom);
 657     memory_region_set_readonly(&s->prom, true);
 658     sysbus_init_mmio(dev, &s->prom);
 659     return 0;
 660 }
 661
 662 static Property prom_properties[] = {
 663     {/* end of property list */},
 664 };
 665
 666 static void prom_class_init(ObjectClass *klass, void *data)
 667 {
 668     DeviceClass *dc = DEVICE_CLASS(klass);
 669     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 670
 671     k->init = prom_init1;
 672     dc->props = prom_properties;
 673 }
 674
 675 static TypeInfo prom_info = {
 676     .name          = "openprom",
 677     .parent        = TYPE_SYS_BUS_DEVICE,
 678     .instance_size = sizeof(PROMState),
 679     .class_init    = prom_class_init,
 680 };
 681
 682
 683 typedef struct RamDevice
 684 {
 685     SysBusDevice busdev;
 686     MemoryRegion ram;
 687     uint64_t size;
 688 } RamDevice;
 689
 690 /* System RAM */
 691 static int ram_init1(SysBusDevice *dev)
 692 {
 693     RamDevice *d = FROM_SYSBUS(RamDevice, dev);
 694
 695     memory_region_init_ram(&d->ram, "sun4u.ram", d->size);
 696     vmstate_register_ram_global(&d->ram);
 697     sysbus_init_mmio(dev, &d->ram);
 698     return 0;
 699 }
 700
 701 static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size)
 702 {
 703     DeviceState *dev;
 704     SysBusDevice *s;
 705     RamDevice *d;
 706
 707     /* allocate RAM */
 708     dev = qdev_create(NULL, "memory");
 709     s = sysbus_from_qdev(dev);
 710
 711     d = FROM_SYSBUS(RamDevice, s);
 712     d->size = RAM_size;
 713     qdev_init_nofail(dev);
 714
 715     sysbus_mmio_map(s, 0, addr);
 716 }
 717
 718 static Property ram_properties[] = {
 719     DEFINE_PROP_UINT64("size", RamDevice, size, 0),
 720     DEFINE_PROP_END_OF_LIST(),
 721 };
 722
 723 static void ram_class_init(ObjectClass *klass, void *data)
 724 {
 725     DeviceClass *dc = DEVICE_CLASS(klass);
 726     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 727
 728     k->init = ram_init1;
 729     dc->props = ram_properties;
 730 }
 731
 732 static TypeInfo ram_info = {
 733     .name          = "memory",
 734     .parent        = TYPE_SYS_BUS_DEVICE,
 735     .instance_size = sizeof(RamDevice),
 736     .class_init    = ram_class_init,
 737 };
 738
 739 static CPUSPARCState *cpu_devinit(const char *cpu_model, const struct hwdef *hwdef)
 740 {
 741     CPUSPARCState *env;
 742     ResetData *reset_info;
 743
 744     uint32_t   tick_frequency = 100*1000000;
 745     uint32_t  stick_frequency = 100*1000000;
 746     uint32_t hstick_frequency = 100*1000000;
 747
 748     if (!cpu_model)
 749         cpu_model = hwdef->default_cpu_model;
 750     env = cpu_init(cpu_model);
 751     if (!env) {
 752         fprintf(stderr, "Unable to find Sparc CPU definition\n");
 753         exit(1);
 754     }
 755
 756     env->tick = cpu_timer_create("tick", env, tick_irq,
 757                                   tick_frequency, TICK_NPT_MASK);
 758
 759     env->stick = cpu_timer_create("stick", env, stick_irq,
 760                                    stick_frequency, TICK_INT_DIS);
 761
 762     env->hstick = cpu_timer_create("hstick", env, hstick_irq,
 763                                     hstick_frequency, TICK_INT_DIS);
 764
 765     reset_info = g_malloc0(sizeof(ResetData));
 766     reset_info->env = env;
 767     reset_info->prom_addr = hwdef->prom_addr;
 768     qemu_register_reset(main_cpu_reset, reset_info);
 769
 770     return env;
 771 }
 772
 773 static void sun4uv_init(MemoryRegion *address_space_mem,
 774                         ram_addr_t RAM_size,
 775                         const char *boot_devices,
 776                         const char *kernel_filename, const char *kernel_cmdline,
 777                         const char *initrd_filename, const char *cpu_model,
 778                         const struct hwdef *hwdef)
 779 {
 780     CPUSPARCState *env;
 781     M48t59State *nvram;
 782     unsigned int i;
 783     long initrd_size, kernel_size;
 784     PCIBus *pci_bus, *pci_bus2, *pci_bus3;
 785     ISABus *isa_bus;
 786     qemu_irq *ivec_irqs, *pbm_irqs;
 787     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 788     DriveInfo *fd[MAX_FD];
 789     void *fw_cfg;
 790
 791     /* init CPUs */
 792     env = cpu_devinit(cpu_model, hwdef);
 793
 794     /* set up devices */
 795     ram_init(0, RAM_size);
 796
 797     prom_init(hwdef->prom_addr, bios_name);
 798
 799     ivec_irqs = qemu_allocate_irqs(cpu_set_ivec_irq, env, IVEC_MAX);
 800     pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, ivec_irqs, &pci_bus2,
 801                            &pci_bus3, &pbm_irqs);
 802     pci_vga_init(pci_bus);
 803
 804     // XXX Should be pci_bus3
 805     isa_bus = pci_ebus_init(pci_bus, -1, pbm_irqs);
 806
 807     i = 0;
 808     if (hwdef->console_serial_base) {
 809         serial_mm_init(address_space_mem, hwdef->console_serial_base, 0,
 810                        NULL, 115200, serial_hds[i], DEVICE_BIG_ENDIAN);
 811         i++;
 812     }
 813     for(; i < MAX_SERIAL_PORTS; i++) {
 814         if (serial_hds[i]) {
 815             serial_isa_init(isa_bus, i, serial_hds[i]);
 816         }
 817     }
 818
 819     for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
 820         if (parallel_hds[i]) {
 821             parallel_init(isa_bus, i, parallel_hds[i]);
 822         }
 823     }
 824
 825     for(i = 0; i < nb_nics; i++)
 826         pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL);
 827
 828     ide_drive_get(hd, MAX_IDE_BUS);
 829
 830     pci_cmd646_ide_init(pci_bus, hd, 1);
 831
 832     isa_create_simple(isa_bus, "i8042");
 833     for(i = 0; i < MAX_FD; i++) {
 834         fd[i] = drive_get(IF_FLOPPY, 0, i);
 835     }
 836     fdctrl_init_isa(isa_bus, fd);
 837     nvram = m48t59_init_isa(isa_bus, 0x0074, NVRAM_SIZE, 59);
 838
 839     initrd_size = 0;
 840     kernel_size = sun4u_load_kernel(kernel_filename, initrd_filename,
 841                                     ram_size, &initrd_size);
 842
 843     sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", RAM_size, boot_devices,
 844                            KERNEL_LOAD_ADDR, kernel_size,
 845                            kernel_cmdline,
 846                            INITRD_LOAD_ADDR, initrd_size,
 847                            /* XXX: need an option to load a NVRAM image */
 848                            0,
 849                            graphic_width, graphic_height, graphic_depth,
 850                            (uint8_t *)&nd_table[0].macaddr);
 851
 852     fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
 853     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 854     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 855     fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
 856     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
 857     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 858     if (kernel_cmdline) {
 859         fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
 860                        strlen(kernel_cmdline) + 1);
 861         fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
 862                          (uint8_t*)strdup(kernel_cmdline),
 863                          strlen(kernel_cmdline) + 1);
 864     } else {
 865         fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
 866     }
 867     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
 868     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 869     fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_devices[0]);
 870
 871     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width);
 872     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height);
 873     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth);
 874
 875     qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
 876 }
 877
 878 enum {
 879     sun4u_id = 0,
 880     sun4v_id = 64,
 881     niagara_id,
 882 };
 883
 884 static const struct hwdef hwdefs[] = {
 885     /* Sun4u generic PC-like machine */
 886     {
 887         .default_cpu_model = "TI UltraSparc IIi",
 888         .machine_id = sun4u_id,
 889         .prom_addr = 0x1fff0000000ULL,
 890         .console_serial_base = 0,
 891     },
 892     /* Sun4v generic PC-like machine */
 893     {
 894         .default_cpu_model = "Sun UltraSparc T1",
 895         .machine_id = sun4v_id,
 896         .prom_addr = 0x1fff0000000ULL,
 897         .console_serial_base = 0,
 898     },
 899     /* Sun4v generic Niagara machine */
 900     {
 901         .default_cpu_model = "Sun UltraSparc T1",
 902         .machine_id = niagara_id,
 903         .prom_addr = 0xfff0000000ULL,
 904         .console_serial_base = 0xfff0c2c000ULL,
 905     },
 906 };
 907
 908 /* Sun4u hardware initialisation */
 909 static void sun4u_init(ram_addr_t RAM_size,
 910                        const char *boot_devices,
 911                        const char *kernel_filename, const char *kernel_cmdline,
 912                        const char *initrd_filename, const char *cpu_model)
 913 {
 914     sun4uv_init(get_system_memory(), RAM_size, boot_devices, kernel_filename,
 915                 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[0]);
 916 }
 917
 918 /* Sun4v hardware initialisation */
 919 static void sun4v_init(ram_addr_t RAM_size,
 920                        const char *boot_devices,
 921                        const char *kernel_filename, const char *kernel_cmdline,
 922                        const char *initrd_filename, const char *cpu_model)
 923 {
 924     sun4uv_init(get_system_memory(), RAM_size, boot_devices, kernel_filename,
 925                 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[1]);
 926 }
 927
 928 /* Niagara hardware initialisation */
 929 static void niagara_init(ram_addr_t RAM_size,
 930                          const char *boot_devices,
 931                          const char *kernel_filename, const char *kernel_cmdline,
 932                          const char *initrd_filename, const char *cpu_model)
 933 {
 934     sun4uv_init(get_system_memory(), RAM_size, boot_devices, kernel_filename,
 935                 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[2]);
 936 }
 937
 938 static QEMUMachine sun4u_machine = {
 939     .name = "sun4u",
 940     .desc = "Sun4u platform",
 941     .init = sun4u_init,
 942     .max_cpus = 1, // XXX for now
 943     .is_default = 1,
 944 };
 945
 946 static QEMUMachine sun4v_machine = {
 947     .name = "sun4v",
 948     .desc = "Sun4v platform",
 949     .init = sun4v_init,
 950     .max_cpus = 1, // XXX for now
 951 };
 952
 953 static QEMUMachine niagara_machine = {
 954     .name = "Niagara",
 955     .desc = "Sun4v platform, Niagara",
 956     .init = niagara_init,
 957     .max_cpus = 1, // XXX for now
 958 };
 959
 960 static void sun4u_register_types(void)
 961 {
 962     type_register_static(&ebus_info);
 963     type_register_static(&prom_info);
 964     type_register_static(&ram_info);
 965 }
 966
 967 static void sun4u_machine_init(void)
 968 {
 969     qemu_register_machine(&sun4u_machine);
 970     qemu_register_machine(&sun4v_machine);
 971     qemu_register_machine(&niagara_machine);
 972 }
 973
 974 type_init(sun4u_register_types)
 975 machine_init(sun4u_machine_init);