hw/usb-musb.c

   1 /*
   2  * "Inventra" High-speed Dual-Role Controller (MUSB-HDRC), Mentor Graphics,
   3  * USB2.0 OTG compliant core used in various chips.
   4  *
   5  * Copyright (C) 2008 Nokia Corporation
   6  * Written by Andrzej Zaborowski <andrew@openedhand.com>
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 or
  11  * (at your option) version 3 of the License.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License along
  19  * with this program; if not, write to the Free Software Foundation, Inc.,
  20  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  21  *
  22  * Only host-mode and non-DMA accesses are currently supported.
  23  */
  24 #include "qemu-common.h"
  25 #include "qemu-timer.h"
  26 #include "usb.h"
  27 #include "irq.h"
  28
  29 /* Common USB registers */
  30 #define MUSB_HDRC_FADDR         0x00    /* 8-bit */
  31 #define MUSB_HDRC_POWER         0x01    /* 8-bit */
  32
  33 #define MUSB_HDRC_INTRTX        0x02    /* 16-bit */
  34 #define MUSB_HDRC_INTRRX        0x04
  35 #define MUSB_HDRC_INTRTXE       0x06
  36 #define MUSB_HDRC_INTRRXE       0x08
  37 #define MUSB_HDRC_INTRUSB       0x0a    /* 8 bit */
  38 #define MUSB_HDRC_INTRUSBE      0x0b    /* 8 bit */
  39 #define MUSB_HDRC_FRAME         0x0c    /* 16-bit */
  40 #define MUSB_HDRC_INDEX         0x0e    /* 8 bit */
  41 #define MUSB_HDRC_TESTMODE      0x0f    /* 8 bit */
  42
  43 /* Per-EP registers in indexed mode */
  44 #define MUSB_HDRC_EP_IDX        0x10    /* 8-bit */
  45
  46 /* EP FIFOs */
  47 #define MUSB_HDRC_FIFO          0x20
  48
  49 /* Additional Control Registers */
  50 #define MUSB_HDRC_DEVCTL        0x60    /* 8 bit */
  51
  52 /* These are indexed */
  53 #define MUSB_HDRC_TXFIFOSZ      0x62    /* 8 bit (see masks) */
  54 #define MUSB_HDRC_RXFIFOSZ      0x63    /* 8 bit (see masks) */
  55 #define MUSB_HDRC_TXFIFOADDR    0x64    /* 16 bit offset shifted right 3 */
  56 #define MUSB_HDRC_RXFIFOADDR    0x66    /* 16 bit offset shifted right 3 */
  57
  58 /* Some more registers */
  59 #define MUSB_HDRC_VCTRL         0x68    /* 8 bit */
  60 #define MUSB_HDRC_HWVERS        0x6c    /* 8 bit */
  61
  62 /* Added in HDRC 1.9(?) & MHDRC 1.4 */
  63 /* ULPI pass-through */
  64 #define MUSB_HDRC_ULPI_VBUSCTL  0x70
  65 #define MUSB_HDRC_ULPI_REGDATA  0x74
  66 #define MUSB_HDRC_ULPI_REGADDR  0x75
  67 #define MUSB_HDRC_ULPI_REGCTL   0x76
  68
  69 /* Extended config & PHY control */
  70 #define MUSB_HDRC_ENDCOUNT      0x78    /* 8 bit */
  71 #define MUSB_HDRC_DMARAMCFG     0x79    /* 8 bit */
  72 #define MUSB_HDRC_PHYWAIT       0x7a    /* 8 bit */
  73 #define MUSB_HDRC_PHYVPLEN      0x7b    /* 8 bit */
  74 #define MUSB_HDRC_HS_EOF1       0x7c    /* 8 bit, units of 546.1 us */
  75 #define MUSB_HDRC_FS_EOF1       0x7d    /* 8 bit, units of 533.3 ns */
  76 #define MUSB_HDRC_LS_EOF1       0x7e    /* 8 bit, units of 1.067 us */
  77
  78 /* Per-EP BUSCTL registers */
  79 #define MUSB_HDRC_BUSCTL        0x80
  80
  81 /* Per-EP registers in flat mode */
  82 #define MUSB_HDRC_EP            0x100
  83
  84 /* offsets to registers in flat model */
  85 #define MUSB_HDRC_TXMAXP        0x00    /* 16 bit apparently */
  86 #define MUSB_HDRC_TXCSR         0x02    /* 16 bit apparently */
  87 #define MUSB_HDRC_CSR0          MUSB_HDRC_TXCSR         /* re-used for EP0 */
  88 #define MUSB_HDRC_RXMAXP        0x04    /* 16 bit apparently */
  89 #define MUSB_HDRC_RXCSR         0x06    /* 16 bit apparently */
  90 #define MUSB_HDRC_RXCOUNT       0x08    /* 16 bit apparently */
  91 #define MUSB_HDRC_COUNT0        MUSB_HDRC_RXCOUNT       /* re-used for EP0 */
  92 #define MUSB_HDRC_TXTYPE        0x0a    /* 8 bit apparently */
  93 #define MUSB_HDRC_TYPE0         MUSB_HDRC_TXTYPE        /* re-used for EP0 */
  94 #define MUSB_HDRC_TXINTERVAL    0x0b    /* 8 bit apparently */
  95 #define MUSB_HDRC_NAKLIMIT0     MUSB_HDRC_TXINTERVAL    /* re-used for EP0 */
  96 #define MUSB_HDRC_RXTYPE        0x0c    /* 8 bit apparently */
  97 #define MUSB_HDRC_RXINTERVAL    0x0d    /* 8 bit apparently */
  98 #define MUSB_HDRC_FIFOSIZE      0x0f    /* 8 bit apparently */
  99 #define MUSB_HDRC_CONFIGDATA    MGC_O_HDRC_FIFOSIZE     /* re-used for EP0 */
 100
 101 /* "Bus control" registers */
 102 #define MUSB_HDRC_TXFUNCADDR    0x00
 103 #define MUSB_HDRC_TXHUBADDR     0x02
 104 #define MUSB_HDRC_TXHUBPORT     0x03
 105
 106 #define MUSB_HDRC_RXFUNCADDR    0x04
 107 #define MUSB_HDRC_RXHUBADDR     0x06
 108 #define MUSB_HDRC_RXHUBPORT     0x07
 109
 110 /*
 111  * MUSBHDRC Register bit masks
 112  */
 113
 114 /* POWER */
 115 #define MGC_M_POWER_ISOUPDATE           0x80
 116 #define MGC_M_POWER_SOFTCONN            0x40
 117 #define MGC_M_POWER_HSENAB              0x20
 118 #define MGC_M_POWER_HSMODE              0x10
 119 #define MGC_M_POWER_RESET               0x08
 120 #define MGC_M_POWER_RESUME              0x04
 121 #define MGC_M_POWER_SUSPENDM            0x02
 122 #define MGC_M_POWER_ENSUSPEND           0x01
 123
 124 /* INTRUSB */
 125 #define MGC_M_INTR_SUSPEND              0x01
 126 #define MGC_M_INTR_RESUME               0x02
 127 #define MGC_M_INTR_RESET                0x04
 128 #define MGC_M_INTR_BABBLE               0x04
 129 #define MGC_M_INTR_SOF                  0x08
 130 #define MGC_M_INTR_CONNECT              0x10
 131 #define MGC_M_INTR_DISCONNECT           0x20
 132 #define MGC_M_INTR_SESSREQ              0x40
 133 #define MGC_M_INTR_VBUSERROR            0x80    /* FOR SESSION END */
 134 #define MGC_M_INTR_EP0                  0x01    /* FOR EP0 INTERRUPT */
 135
 136 /* DEVCTL */
 137 #define MGC_M_DEVCTL_BDEVICE            0x80
 138 #define MGC_M_DEVCTL_FSDEV              0x40
 139 #define MGC_M_DEVCTL_LSDEV              0x20
 140 #define MGC_M_DEVCTL_VBUS               0x18
 141 #define MGC_S_DEVCTL_VBUS               3
 142 #define MGC_M_DEVCTL_HM                 0x04
 143 #define MGC_M_DEVCTL_HR                 0x02
 144 #define MGC_M_DEVCTL_SESSION            0x01
 145
 146 /* TESTMODE */
 147 #define MGC_M_TEST_FORCE_HOST           0x80
 148 #define MGC_M_TEST_FIFO_ACCESS          0x40
 149 #define MGC_M_TEST_FORCE_FS             0x20
 150 #define MGC_M_TEST_FORCE_HS             0x10
 151 #define MGC_M_TEST_PACKET               0x08
 152 #define MGC_M_TEST_K                    0x04
 153 #define MGC_M_TEST_J                    0x02
 154 #define MGC_M_TEST_SE0_NAK              0x01
 155
 156 /* CSR0 */
 157 #define MGC_M_CSR0_FLUSHFIFO            0x0100
 158 #define MGC_M_CSR0_TXPKTRDY             0x0002
 159 #define MGC_M_CSR0_RXPKTRDY             0x0001
 160
 161 /* CSR0 in Peripheral mode */
 162 #define MGC_M_CSR0_P_SVDSETUPEND        0x0080
 163 #define MGC_M_CSR0_P_SVDRXPKTRDY        0x0040
 164 #define MGC_M_CSR0_P_SENDSTALL          0x0020
 165 #define MGC_M_CSR0_P_SETUPEND           0x0010
 166 #define MGC_M_CSR0_P_DATAEND            0x0008
 167 #define MGC_M_CSR0_P_SENTSTALL          0x0004
 168
 169 /* CSR0 in Host mode */
 170 #define MGC_M_CSR0_H_NO_PING            0x0800
 171 #define MGC_M_CSR0_H_WR_DATATOGGLE      0x0400  /* set to allow setting: */
 172 #define MGC_M_CSR0_H_DATATOGGLE         0x0200  /* data toggle control */
 173 #define MGC_M_CSR0_H_NAKTIMEOUT         0x0080
 174 #define MGC_M_CSR0_H_STATUSPKT          0x0040
 175 #define MGC_M_CSR0_H_REQPKT             0x0020
 176 #define MGC_M_CSR0_H_ERROR              0x0010
 177 #define MGC_M_CSR0_H_SETUPPKT           0x0008
 178 #define MGC_M_CSR0_H_RXSTALL            0x0004
 179
 180 /* CONFIGDATA */
 181 #define MGC_M_CONFIGDATA_MPRXE          0x80    /* auto bulk pkt combining */
 182 #define MGC_M_CONFIGDATA_MPTXE          0x40    /* auto bulk pkt splitting */
 183 #define MGC_M_CONFIGDATA_BIGENDIAN      0x20
 184 #define MGC_M_CONFIGDATA_HBRXE          0x10    /* HB-ISO for RX */
 185 #define MGC_M_CONFIGDATA_HBTXE          0x08    /* HB-ISO for TX */
 186 #define MGC_M_CONFIGDATA_DYNFIFO        0x04    /* dynamic FIFO sizing */
 187 #define MGC_M_CONFIGDATA_SOFTCONE       0x02    /* SoftConnect */
 188 #define MGC_M_CONFIGDATA_UTMIDW         0x01    /* Width, 0 => 8b, 1 => 16b */
 189
 190 /* TXCSR in Peripheral and Host mode */
 191 #define MGC_M_TXCSR_AUTOSET             0x8000
 192 #define MGC_M_TXCSR_ISO                 0x4000
 193 #define MGC_M_TXCSR_MODE                0x2000
 194 #define MGC_M_TXCSR_DMAENAB             0x1000
 195 #define MGC_M_TXCSR_FRCDATATOG          0x0800
 196 #define MGC_M_TXCSR_DMAMODE             0x0400
 197 #define MGC_M_TXCSR_CLRDATATOG          0x0040
 198 #define MGC_M_TXCSR_FLUSHFIFO           0x0008
 199 #define MGC_M_TXCSR_FIFONOTEMPTY        0x0002
 200 #define MGC_M_TXCSR_TXPKTRDY            0x0001
 201
 202 /* TXCSR in Peripheral mode */
 203 #define MGC_M_TXCSR_P_INCOMPTX          0x0080
 204 #define MGC_M_TXCSR_P_SENTSTALL         0x0020
 205 #define MGC_M_TXCSR_P_SENDSTALL         0x0010
 206 #define MGC_M_TXCSR_P_UNDERRUN          0x0004
 207
 208 /* TXCSR in Host mode */
 209 #define MGC_M_TXCSR_H_WR_DATATOGGLE     0x0200
 210 #define MGC_M_TXCSR_H_DATATOGGLE        0x0100
 211 #define MGC_M_TXCSR_H_NAKTIMEOUT        0x0080
 212 #define MGC_M_TXCSR_H_RXSTALL           0x0020
 213 #define MGC_M_TXCSR_H_ERROR             0x0004
 214
 215 /* RXCSR in Peripheral and Host mode */
 216 #define MGC_M_RXCSR_AUTOCLEAR           0x8000
 217 #define MGC_M_RXCSR_DMAENAB             0x2000
 218 #define MGC_M_RXCSR_DISNYET             0x1000
 219 #define MGC_M_RXCSR_DMAMODE             0x0800
 220 #define MGC_M_RXCSR_INCOMPRX            0x0100
 221 #define MGC_M_RXCSR_CLRDATATOG          0x0080
 222 #define MGC_M_RXCSR_FLUSHFIFO           0x0010
 223 #define MGC_M_RXCSR_DATAERROR           0x0008
 224 #define MGC_M_RXCSR_FIFOFULL            0x0002
 225 #define MGC_M_RXCSR_RXPKTRDY            0x0001
 226
 227 /* RXCSR in Peripheral mode */
 228 #define MGC_M_RXCSR_P_ISO               0x4000
 229 #define MGC_M_RXCSR_P_SENTSTALL         0x0040
 230 #define MGC_M_RXCSR_P_SENDSTALL         0x0020
 231 #define MGC_M_RXCSR_P_OVERRUN           0x0004
 232
 233 /* RXCSR in Host mode */
 234 #define MGC_M_RXCSR_H_AUTOREQ           0x4000
 235 #define MGC_M_RXCSR_H_WR_DATATOGGLE     0x0400
 236 #define MGC_M_RXCSR_H_DATATOGGLE        0x0200
 237 #define MGC_M_RXCSR_H_RXSTALL           0x0040
 238 #define MGC_M_RXCSR_H_REQPKT            0x0020
 239 #define MGC_M_RXCSR_H_ERROR             0x0004
 240
 241 /* HUBADDR */
 242 #define MGC_M_HUBADDR_MULTI_TT          0x80
 243
 244 /* ULPI: Added in HDRC 1.9(?) & MHDRC 1.4 */
 245 #define MGC_M_ULPI_VBCTL_USEEXTVBUSIND  0x02
 246 #define MGC_M_ULPI_VBCTL_USEEXTVBUS     0x01
 247 #define MGC_M_ULPI_REGCTL_INT_ENABLE    0x08
 248 #define MGC_M_ULPI_REGCTL_READNOTWRITE  0x04
 249 #define MGC_M_ULPI_REGCTL_COMPLETE      0x02
 250 #define MGC_M_ULPI_REGCTL_REG           0x01
 251
 252 static void musb_attach(USBPort *port, USBDevice *dev);
 253
 254 typedef struct {
 255     uint16_t faddr[2];
 256     uint8_t haddr[2];
 257     uint8_t hport[2];
 258     uint16_t csr[2];
 259     uint16_t maxp[2];
 260     uint16_t rxcount;
 261     uint8_t type[2];
 262     uint8_t interval[2];
 263     uint8_t config;
 264     uint8_t fifosize;
 265     int timeout[2];     /* Always in microframes */
 266
 267     uint32_t *buf[2];
 268     int fifolen[2];
 269     int fifostart[2];
 270     int fifoaddr[2];
 271     USBPacket packey[2];
 272     int status[2];
 273     int ext_size[2];
 274
 275     /* For callbacks' use */
 276     int epnum;
 277     int interrupt[2];
 278     MUSBState *musb;
 279     USBCallback *delayed_cb[2];
 280     QEMUTimer *intv_timer[2];
 281 } MUSBEndPoint;
 282
 283 struct MUSBState {
 284     qemu_irq *irqs;
 285     USBPort port;
 286
 287     int idx;
 288     uint8_t devctl;
 289     uint8_t power;
 290     uint8_t faddr;
 291
 292     uint8_t intr;
 293     uint8_t mask;
 294     uint16_t tx_intr;
 295     uint16_t tx_mask;
 296     uint16_t rx_intr;
 297     uint16_t rx_mask;
 298
 299     int setup_len;
 300     int session;
 301
 302     uint32_t buf[0x2000];
 303
 304         /* Duplicating the world since 2008!...  probably we should have 32
 305          * logical, single endpoints instead.  */
 306     MUSBEndPoint ep[16];
 307 } *musb_init(qemu_irq *irqs)
 308 {
 309     MUSBState *s = qemu_mallocz(sizeof(*s));
 310     int i;
 311
 312     s->irqs = irqs;
 313
 314     s->faddr = 0x00;
 315     s->power = MGC_M_POWER_HSENAB;
 316     s->tx_intr = 0x0000;
 317     s->rx_intr = 0x0000;
 318     s->tx_mask = 0xffff;
 319     s->rx_mask = 0xffff;
 320     s->intr = 0x00;
 321     s->mask = 0x06;
 322     s->idx = 0;
 323
 324     /* TODO: _DW */
 325     s->ep[0].config = MGC_M_CONFIGDATA_SOFTCONE | MGC_M_CONFIGDATA_DYNFIFO;
 326     for (i = 0; i < 16; i ++) {
 327         s->ep[i].fifosize = 64;
 328         s->ep[i].maxp[0] = 0x40;
 329         s->ep[i].maxp[1] = 0x40;
 330         s->ep[i].musb = s;
 331         s->ep[i].epnum = i;
 332     }
 333
 334     qemu_register_usb_port(&s->port, s, 0, musb_attach);
 335
 336     return s;
 337 }
 338
 339 static void musb_vbus_set(MUSBState *s, int level)
 340 {
 341     if (level)
 342         s->devctl |= 3 << MGC_S_DEVCTL_VBUS;
 343     else
 344         s->devctl &= ~MGC_M_DEVCTL_VBUS;
 345
 346     qemu_set_irq(s->irqs[musb_set_vbus], level);
 347 }
 348
 349 static void musb_intr_set(MUSBState *s, int line, int level)
 350 {
 351     if (!level) {
 352         s->intr &= ~(1 << line);
 353         qemu_irq_lower(s->irqs[line]);
 354     } else if (s->mask & (1 << line)) {
 355         s->intr |= 1 << line;
 356         qemu_irq_raise(s->irqs[line]);
 357     }
 358 }
 359
 360 static void musb_tx_intr_set(MUSBState *s, int line, int level)
 361 {
 362     if (!level) {
 363         s->tx_intr &= ~(1 << line);
 364         if (!s->tx_intr)
 365             qemu_irq_lower(s->irqs[musb_irq_tx]);
 366     } else if (s->tx_mask & (1 << line)) {
 367         s->tx_intr |= 1 << line;
 368         qemu_irq_raise(s->irqs[musb_irq_tx]);
 369     }
 370 }
 371
 372 static void musb_rx_intr_set(MUSBState *s, int line, int level)
 373 {
 374     if (line) {
 375         if (!level) {
 376             s->rx_intr &= ~(1 << line);
 377             if (!s->rx_intr)
 378                 qemu_irq_lower(s->irqs[musb_irq_rx]);
 379         } else if (s->rx_mask & (1 << line)) {
 380             s->rx_intr |= 1 << line;
 381             qemu_irq_raise(s->irqs[musb_irq_rx]);
 382         }
 383     } else
 384         musb_tx_intr_set(s, line, level);
 385 }
 386
 387 uint32_t musb_core_intr_get(MUSBState *s)
 388 {
 389     return (s->rx_intr << 15) | s->tx_intr;
 390 }
 391
 392 void musb_core_intr_clear(MUSBState *s, uint32_t mask)
 393 {
 394     if (s->rx_intr) {
 395         s->rx_intr &= mask >> 15;
 396         if (!s->rx_intr)
 397             qemu_irq_lower(s->irqs[musb_irq_rx]);
 398     }
 399
 400     if (s->tx_intr) {
 401         s->tx_intr &= mask & 0xffff;
 402         if (!s->tx_intr)
 403             qemu_irq_lower(s->irqs[musb_irq_tx]);
 404     }
 405 }
 406
 407 void musb_set_size(MUSBState *s, int epnum, int size, int is_tx)
 408 {
 409     s->ep[epnum].ext_size[!is_tx] = size;
 410     s->ep[epnum].fifostart[0] = 0;
 411     s->ep[epnum].fifostart[1] = 0;
 412     s->ep[epnum].fifolen[0] = 0;
 413     s->ep[epnum].fifolen[1] = 0;
 414 }
 415
 416 static void musb_session_update(MUSBState *s, int prev_dev, int prev_sess)
 417 {
 418     int detect_prev = prev_dev && prev_sess;
 419     int detect = !!s->port.dev && s->session;
 420
 421     if (detect && !detect_prev) {
 422         /* Let's skip the ID pin sense and VBUS sense formalities and
 423          * and signal a successful SRP directly.  This should work at least
 424          * for the Linux driver stack.  */
 425         musb_intr_set(s, musb_irq_connect, 1);
 426
 427         if (s->port.dev->speed == USB_SPEED_LOW) {
 428             s->devctl &= ~MGC_M_DEVCTL_FSDEV;
 429             s->devctl |= MGC_M_DEVCTL_LSDEV;
 430         } else {
 431             s->devctl |= MGC_M_DEVCTL_FSDEV;
 432             s->devctl &= ~MGC_M_DEVCTL_LSDEV;
 433         }
 434
 435         /* A-mode?  */
 436         s->devctl &= ~MGC_M_DEVCTL_BDEVICE;
 437
 438         /* Host-mode bit?  */
 439         s->devctl |= MGC_M_DEVCTL_HM;
 440 #if 1
 441         musb_vbus_set(s, 1);
 442 #endif
 443     } else if (!detect && detect_prev) {
 444 #if 1
 445         musb_vbus_set(s, 0);
 446 #endif
 447     }
 448 }
 449
 450 /* Attach or detach a device on our only port.  */
 451 static void musb_attach(USBPort *port, USBDevice *dev)
 452 {
 453     MUSBState *s = (MUSBState *) port->opaque;
 454     USBDevice *curr;
 455
 456     port = &s->port;
 457     curr = port->dev;
 458
 459     if (dev) {
 460         if (curr) {
 461             usb_attach(port, NULL);
 462             /* TODO: signal some interrupts */
 463         }
 464
 465         musb_intr_set(s, musb_irq_vbus_request, 1);
 466
 467         /* Send the attach message to device */
 468         usb_send_msg(dev, USB_MSG_ATTACH);
 469     } else if (curr) {
 470         /* Send the detach message */
 471         usb_send_msg(curr, USB_MSG_DETACH);
 472
 473         musb_intr_set(s, musb_irq_disconnect, 1);
 474     }
 475
 476     port->dev = dev;
 477
 478     musb_session_update(s, !!curr, s->session);
 479 }
 480
 481 static inline void musb_cb_tick0(void *opaque)
 482 {
 483     MUSBEndPoint *ep = (MUSBEndPoint *) opaque;
 484
 485     ep->delayed_cb[0](&ep->packey[0], opaque);
 486 }
 487
 488 static inline void musb_cb_tick1(void *opaque)
 489 {
 490     MUSBEndPoint *ep = (MUSBEndPoint *) opaque;
 491
 492     ep->delayed_cb[1](&ep->packey[1], opaque);
 493 }
 494
 495 #define musb_cb_tick    (dir ? musb_cb_tick1 : musb_cb_tick0)
 496
 497 static inline void musb_schedule_cb(USBPacket *packey, void *opaque, int dir)
 498 {
 499     MUSBEndPoint *ep = (MUSBEndPoint *) opaque;
 500     int timeout = 0;
 501
 502     if (ep->status[dir] == USB_RET_NAK)
 503         timeout = ep->timeout[dir];
 504     else if (ep->interrupt[dir])
 505         timeout = 8;
 506     else
 507         return musb_cb_tick(opaque);
 508
 509     if (!ep->intv_timer[dir])
 510         ep->intv_timer[dir] = qemu_new_timer(vm_clock, musb_cb_tick, opaque);
 511
 512     qemu_mod_timer(ep->intv_timer[dir], qemu_get_clock(vm_clock) +
 513                     muldiv64(timeout, ticks_per_sec, 8000));
 514 }
 515
 516 static void musb_schedule0_cb(USBPacket *packey, void *opaque)
 517 {
 518     return musb_schedule_cb(packey, opaque, 0);
 519 }
 520
 521 static void musb_schedule1_cb(USBPacket *packey, void *opaque)
 522 {
 523     return musb_schedule_cb(packey, opaque, 1);
 524 }
 525
 526 static int musb_timeout(int ttype, int speed, int val)
 527 {
 528 #if 1
 529     return val << 3;
 530 #endif
 531
 532     switch (ttype) {
 533     case USB_ENDPOINT_XFER_CONTROL:
 534         if (val < 2)
 535             return 0;
 536         else if (speed == USB_SPEED_HIGH)
 537             return 1 << (val - 1);
 538         else
 539             return 8 << (val - 1);
 540
 541     case USB_ENDPOINT_XFER_INT:
 542         if (speed == USB_SPEED_HIGH)
 543             if (val < 2)
 544                 return 0;
 545             else
 546                 return 1 << (val - 1);
 547         else
 548             return val << 3;
 549
 550     case USB_ENDPOINT_XFER_BULK:
 551     case USB_ENDPOINT_XFER_ISOC:
 552         if (val < 2)
 553             return 0;
 554         else if (speed == USB_SPEED_HIGH)
 555             return 1 << (val - 1);
 556         else
 557             return 8 << (val - 1);
 558         /* TODO: what with low-speed Bulk and Isochronous?  */
 559     }
 560
 561     hw_error("bad interval\n");
 562 }
 563
 564 static inline void musb_packet(MUSBState *s, MUSBEndPoint *ep,
 565                 int epnum, int pid, int len, USBCallback cb, int dir)
 566 {
 567     int ret;
 568     int idx = epnum && dir;
 569     int ttype;
 570
 571     /* ep->type[0,1] contains:
 572      * in bits 7:6 the speed (0 - invalid, 1 - high, 2 - full, 3 - slow)
 573      * in bits 5:4 the transfer type (BULK / INT)
 574      * in bits 3:0 the EP num
 575      */
 576     ttype = epnum ? (ep->type[idx] >> 4) & 3 : 0;
 577
 578     ep->timeout[dir] = musb_timeout(ttype,
 579                     ep->type[idx] >> 6, ep->interval[idx]);
 580     ep->interrupt[dir] = ttype == USB_ENDPOINT_XFER_INT;
 581     ep->delayed_cb[dir] = cb;
 582     cb = dir ? musb_schedule1_cb : musb_schedule0_cb;
 583
 584     ep->packey[dir].pid = pid;
 585     /* A wild guess on the FADDR semantics... */
 586     ep->packey[dir].devaddr = ep->faddr[idx];
 587     ep->packey[dir].devep = ep->type[idx] & 0xf;
 588     ep->packey[dir].data = (void *) ep->buf[idx];
 589     ep->packey[dir].len = len;
 590     ep->packey[dir].complete_cb = cb;
 591     ep->packey[dir].complete_opaque = ep;
 592
 593     if (s->port.dev)
 594         ret = s->port.dev->handle_packet(s->port.dev, &ep->packey[dir]);
 595     else
 596         ret = USB_RET_NODEV;
 597
 598     if (ret == USB_RET_ASYNC) {
 599         ep->status[dir] = len;
 600         return;
 601     }
 602
 603     ep->status[dir] = ret;
 604     usb_packet_complete(&ep->packey[dir]);
 605 }
 606
 607 static void musb_tx_packet_complete(USBPacket *packey, void *opaque)
 608 {
 609     /* Unfortunately we can't use packey->devep because that's the remote
 610      * endpoint number and may be different than our local.  */
 611     MUSBEndPoint *ep = (MUSBEndPoint *) opaque;
 612     int epnum = ep->epnum;
 613     MUSBState *s = ep->musb;
 614
 615     ep->fifostart[0] = 0;
 616     ep->fifolen[0] = 0;
 617 #ifdef CLEAR_NAK
 618     if (ep->status[0] != USB_RET_NAK) {
 619 #endif
 620         if (epnum)
 621             ep->csr[0] &= ~(MGC_M_TXCSR_FIFONOTEMPTY | MGC_M_TXCSR_TXPKTRDY);
 622         else
 623             ep->csr[0] &= ~MGC_M_CSR0_TXPKTRDY;
 624 #ifdef CLEAR_NAK
 625     }
 626 #endif
 627
 628     /* Clear all of the error bits first */
 629     if (epnum)
 630         ep->csr[0] &= ~(MGC_M_TXCSR_H_ERROR | MGC_M_TXCSR_H_RXSTALL |
 631                         MGC_M_TXCSR_H_NAKTIMEOUT);
 632     else
 633         ep->csr[0] &= ~(MGC_M_CSR0_H_ERROR | MGC_M_CSR0_H_RXSTALL |
 634                         MGC_M_CSR0_H_NAKTIMEOUT | MGC_M_CSR0_H_NO_PING);
 635
 636     if (ep->status[0] == USB_RET_STALL) {
 637         /* Command not supported by target! */
 638         ep->status[0] = 0;
 639
 640         if (epnum)
 641             ep->csr[0] |= MGC_M_TXCSR_H_RXSTALL;
 642         else
 643             ep->csr[0] |= MGC_M_CSR0_H_RXSTALL;
 644     }
 645
 646     if (ep->status[0] == USB_RET_NAK) {
 647         ep->status[0] = 0;
 648
 649         /* NAK timeouts are only generated in Bulk transfers and
 650          * Data-errors in Isochronous.  */
 651         if (ep->interrupt[0]) {
 652             return;
 653         }
 654
 655         if (epnum)
 656             ep->csr[0] |= MGC_M_TXCSR_H_NAKTIMEOUT;
 657         else
 658             ep->csr[0] |= MGC_M_CSR0_H_NAKTIMEOUT;
 659     }
 660
 661     if (ep->status[0] < 0) {
 662         if (ep->status[0] == USB_RET_BABBLE)
 663             musb_intr_set(s, musb_irq_rst_babble, 1);
 664
 665         /* Pretend we've tried three times already and failed (in
 666          * case of USB_TOKEN_SETUP).  */
 667         if (epnum)
 668             ep->csr[0] |= MGC_M_TXCSR_H_ERROR;
 669         else
 670             ep->csr[0] |= MGC_M_CSR0_H_ERROR;
 671
 672         musb_tx_intr_set(s, epnum, 1);
 673         return;
 674     }
 675     /* TODO: check len for over/underruns of an OUT packet?  */
 676
 677 #ifdef SETUPLEN_HACK
 678     if (!epnum && ep->packey[0].pid == USB_TOKEN_SETUP)
 679         s->setup_len = ep->packey[0].data[6];
 680 #endif
 681
 682     /* In DMA mode: if no error, assert DMA request for this EP,
 683      * and skip the interrupt.  */
 684     musb_tx_intr_set(s, epnum, 1);
 685 }
 686
 687 static void musb_rx_packet_complete(USBPacket *packey, void *opaque)
 688 {
 689     /* Unfortunately we can't use packey->devep because that's the remote
 690      * endpoint number and may be different than our local.  */
 691     MUSBEndPoint *ep = (MUSBEndPoint *) opaque;
 692     int epnum = ep->epnum;
 693     MUSBState *s = ep->musb;
 694
 695     ep->fifostart[1] = 0;
 696     ep->fifolen[1] = 0;
 697
 698 #ifdef CLEAR_NAK
 699     if (ep->status[1] != USB_RET_NAK) {
 700 #endif
 701         ep->csr[1] &= ~MGC_M_RXCSR_H_REQPKT;
 702         if (!epnum)
 703             ep->csr[0] &= ~MGC_M_CSR0_H_REQPKT;
 704 #ifdef CLEAR_NAK
 705     }
 706 #endif
 707
 708     /* Clear all of the imaginable error bits first */
 709     ep->csr[1] &= ~(MGC_M_RXCSR_H_ERROR | MGC_M_RXCSR_H_RXSTALL |
 710                     MGC_M_RXCSR_DATAERROR);
 711     if (!epnum)
 712         ep->csr[0] &= ~(MGC_M_CSR0_H_ERROR | MGC_M_CSR0_H_RXSTALL |
 713                         MGC_M_CSR0_H_NAKTIMEOUT | MGC_M_CSR0_H_NO_PING);
 714
 715     if (ep->status[1] == USB_RET_STALL) {
 716         ep->status[1] = 0;
 717         packey->len = 0;
 718
 719         ep->csr[1] |= MGC_M_RXCSR_H_RXSTALL;
 720         if (!epnum)
 721             ep->csr[0] |= MGC_M_CSR0_H_RXSTALL;
 722     }
 723
 724     if (ep->status[1] == USB_RET_NAK) {
 725         ep->status[1] = 0;
 726
 727         /* NAK timeouts are only generated in Bulk transfers and
 728          * Data-errors in Isochronous.  */
 729         if (ep->interrupt[1])
 730             return musb_packet(s, ep, epnum, USB_TOKEN_IN,
 731                             packey->len, musb_rx_packet_complete, 1);
 732
 733         ep->csr[1] |= MGC_M_RXCSR_DATAERROR;
 734         if (!epnum)
 735             ep->csr[0] |= MGC_M_CSR0_H_NAKTIMEOUT;
 736     }
 737
 738     if (ep->status[1] < 0) {
 739         if (ep->status[1] == USB_RET_BABBLE) {
 740             musb_intr_set(s, musb_irq_rst_babble, 1);
 741             return;
 742         }
 743
 744         /* Pretend we've tried three times already and failed (in
 745          * case of a control transfer).  */
 746         ep->csr[1] |= MGC_M_RXCSR_H_ERROR;
 747         if (!epnum)
 748             ep->csr[0] |= MGC_M_CSR0_H_ERROR;
 749
 750         musb_rx_intr_set(s, epnum, 1);
 751         return;
 752     }
 753     /* TODO: check len for over/underruns of an OUT packet?  */
 754     /* TODO: perhaps make use of e->ext_size[1] here.  */
 755
 756     packey->len = ep->status[1];
 757
 758     if (!(ep->csr[1] & (MGC_M_RXCSR_H_RXSTALL | MGC_M_RXCSR_DATAERROR))) {
 759         ep->csr[1] |= MGC_M_RXCSR_FIFOFULL | MGC_M_RXCSR_RXPKTRDY;
 760         if (!epnum)
 761             ep->csr[0] |= MGC_M_CSR0_RXPKTRDY;
 762
 763         ep->rxcount = packey->len; /* XXX: MIN(packey->len, ep->maxp[1]); */
 764         /* In DMA mode: assert DMA request for this EP */
 765     }
 766
 767     /* Only if DMA has not been asserted */
 768     musb_rx_intr_set(s, epnum, 1);
 769 }
 770
 771 static void musb_tx_rdy(MUSBState *s, int epnum)
 772 {
 773     MUSBEndPoint *ep = s->ep + epnum;
 774     int pid;
 775     int total, valid = 0;
 776
 777     ep->fifostart[0] += ep->fifolen[0];
 778     ep->fifolen[0] = 0;
 779
 780     /* XXX: how's the total size of the packet retrieved exactly in
 781      * the generic case?  */
 782     total = ep->maxp[0] & 0x3ff;
 783
 784     if (ep->ext_size[0]) {
 785         total = ep->ext_size[0];
 786         ep->ext_size[0] = 0;
 787         valid = 1;
 788     }
 789
 790     /* If the packet is not fully ready yet, wait for a next segment.  */
 791     if (epnum && (ep->fifostart[0] << 2) < total)
 792         return;
 793
 794     if (!valid)
 795         total = ep->fifostart[0] << 2;
 796
 797     pid = USB_TOKEN_OUT;
 798     if (!epnum && (ep->csr[0] & MGC_M_CSR0_H_SETUPPKT)) {
 799         pid = USB_TOKEN_SETUP;
 800         if (total != 8)
 801             printf("%s: illegal SETUPPKT length of %i bytes\n",
 802                             __FUNCTION__, total);
 803         /* Controller should retry SETUP packets three times on errors
 804          * but it doesn't make sense for us to do that.  */
 805     }
 806
 807     return musb_packet(s, ep, epnum, pid,
 808                     total, musb_tx_packet_complete, 0);
 809 }
 810
 811 static void musb_rx_req(MUSBState *s, int epnum)
 812 {
 813     MUSBEndPoint *ep = s->ep + epnum;
 814     int total;
 815
 816     /* If we already have a packet, which didn't fit into the
 817      * 64 bytes of the FIFO, only move the FIFO start and return. (Obsolete) */
 818     if (ep->packey[1].pid == USB_TOKEN_IN && ep->status[1] >= 0 &&
 819                     (ep->fifostart[1] << 2) + ep->rxcount <
 820                     ep->packey[1].len) {
 821         ep->fifostart[1] += ep->rxcount >> 2;
 822         ep->fifolen[1] = 0;
 823
 824         ep->rxcount = MIN(ep->packey[0].len - (ep->fifostart[1] << 2),
 825                         ep->maxp[1]);
 826
 827         ep->csr[1] &= ~MGC_M_RXCSR_H_REQPKT;
 828         if (!epnum)
 829             ep->csr[0] &= ~MGC_M_CSR0_H_REQPKT;
 830
 831         /* Clear all of the error bits first */
 832         ep->csr[1] &= ~(MGC_M_RXCSR_H_ERROR | MGC_M_RXCSR_H_RXSTALL |
 833                         MGC_M_RXCSR_DATAERROR);
 834         if (!epnum)
 835             ep->csr[0] &= ~(MGC_M_CSR0_H_ERROR | MGC_M_CSR0_H_RXSTALL |
 836                             MGC_M_CSR0_H_NAKTIMEOUT | MGC_M_CSR0_H_NO_PING);
 837
 838         ep->csr[1] |= MGC_M_RXCSR_FIFOFULL | MGC_M_RXCSR_RXPKTRDY;
 839         if (!epnum)
 840             ep->csr[0] |= MGC_M_CSR0_RXPKTRDY;
 841         musb_rx_intr_set(s, epnum, 1);
 842         return;
 843     }
 844
 845     /* The driver sets maxp[1] to 64 or less because it knows the hardware
 846      * FIFO is this deep.  Bigger packets get split in
 847      * usb_generic_handle_packet but we can also do the splitting locally
 848      * for performance.  It turns out we can also have a bigger FIFO and
 849      * ignore the limit set in ep->maxp[1].  The Linux MUSB driver deals
 850      * OK with single packets of even 32KB and we avoid splitting, however
 851      * usb_msd.c sometimes sends a packet bigger than what Linux expects
 852      * (e.g. 8192 bytes instead of 4096) and we get an OVERRUN.  Splitting
 853      * hides this overrun from Linux.  Up to 4096 everything is fine
 854      * though.  Currently this is disabled.
 855      *
 856      * XXX: mind ep->fifosize.  */
 857     total = MIN(ep->maxp[1] & 0x3ff, sizeof(s->buf));
 858
 859 #ifdef SETUPLEN_HACK
 860     /* Why should *we* do that instead of Linux?  */
 861     if (!epnum) {
 862         if (ep->packey[0].devaddr == 2)
 863             total = MIN(s->setup_len, 8);
 864         else
 865             total = MIN(s->setup_len, 64);
 866         s->setup_len -= total;
 867     }
 868 #endif
 869
 870     return musb_packet(s, ep, epnum, USB_TOKEN_IN,
 871                     total, musb_rx_packet_complete, 1);
 872 }
 873
 874 static void musb_ep_frame_cancel(MUSBEndPoint *ep, int dir)
 875 {
 876     if (ep->intv_timer[dir])
 877         qemu_del_timer(ep->intv_timer[dir]);
 878 }
 879
 880 /* Bus control */
 881 static uint8_t musb_busctl_readb(void *opaque, int ep, int addr)
 882 {
 883     MUSBState *s = (MUSBState *) opaque;
 884
 885     switch (addr) {
 886     /* For USB2.0 HS hubs only */
 887     case MUSB_HDRC_TXHUBADDR:
 888         return s->ep[ep].haddr[0];
 889     case MUSB_HDRC_TXHUBPORT:
 890         return s->ep[ep].hport[0];
 891     case MUSB_HDRC_RXHUBADDR:
 892         return s->ep[ep].haddr[1];
 893     case MUSB_HDRC_RXHUBPORT:
 894         return s->ep[ep].hport[1];
 895
 896     default:
 897         printf("%s: unknown register at %02x\n", __FUNCTION__, addr);
 898         return 0x00;
 899     };
 900 }
 901
 902 static void musb_busctl_writeb(void *opaque, int ep, int addr, uint8_t value)
 903 {
 904     MUSBState *s = (MUSBState *) opaque;
 905
 906     switch (addr) {
 907     case MUSB_HDRC_TXHUBADDR:
 908         s->ep[ep].haddr[0] = value;
 909         break;
 910     case MUSB_HDRC_TXHUBPORT:
 911         s->ep[ep].hport[0] = value;
 912         break;
 913     case MUSB_HDRC_RXHUBADDR:
 914         s->ep[ep].haddr[1] = value;
 915         break;
 916     case MUSB_HDRC_RXHUBPORT:
 917         s->ep[ep].hport[1] = value;
 918         break;
 919
 920     default:
 921         printf("%s: unknown register at %02x\n", __FUNCTION__, addr);
 922     };
 923 }
 924
 925 static uint16_t musb_busctl_readh(void *opaque, int ep, int addr)
 926 {
 927     MUSBState *s = (MUSBState *) opaque;
 928
 929     switch (addr) {
 930     case MUSB_HDRC_TXFUNCADDR:
 931         return s->ep[ep].faddr[0];
 932     case MUSB_HDRC_RXFUNCADDR:
 933         return s->ep[ep].faddr[1];
 934
 935     default:
 936         return musb_busctl_readb(s, ep, addr) |
 937                 (musb_busctl_readb(s, ep, addr | 1) << 8);
 938     };
 939 }
 940
 941 static void musb_busctl_writeh(void *opaque, int ep, int addr, uint16_t value)
 942 {
 943     MUSBState *s = (MUSBState *) opaque;
 944
 945     switch (addr) {
 946     case MUSB_HDRC_TXFUNCADDR:
 947         s->ep[ep].faddr[0] = value;
 948         break;
 949     case MUSB_HDRC_RXFUNCADDR:
 950         s->ep[ep].faddr[1] = value;
 951         break;
 952
 953     default:
 954         musb_busctl_writeb(s, ep, addr, value & 0xff);
 955         musb_busctl_writeb(s, ep, addr | 1, value >> 8);
 956     };
 957 }
 958
 959 /* Endpoint control */
 960 static uint8_t musb_ep_readb(void *opaque, int ep, int addr)
 961 {
 962     MUSBState *s = (MUSBState *) opaque;
 963
 964     switch (addr) {
 965     case MUSB_HDRC_TXTYPE:
 966         return s->ep[ep].type[0];
 967     case MUSB_HDRC_TXINTERVAL:
 968         return s->ep[ep].interval[0];
 969     case MUSB_HDRC_RXTYPE:
 970         return s->ep[ep].type[1];
 971     case MUSB_HDRC_RXINTERVAL:
 972         return s->ep[ep].interval[1];
 973     case (MUSB_HDRC_FIFOSIZE & ~1):
 974         return 0x00;
 975     case MUSB_HDRC_FIFOSIZE:
 976         return ep ? s->ep[ep].fifosize : s->ep[ep].config;
 977
 978     default:
 979         printf("%s: unknown register at %02x\n", __FUNCTION__, addr);
 980         return 0x00;
 981     };
 982 }
 983
 984 static void musb_ep_writeb(void *opaque, int ep, int addr, uint8_t value)
 985 {
 986     MUSBState *s = (MUSBState *) opaque;
 987
 988     switch (addr) {
 989     case MUSB_HDRC_TXTYPE:
 990         s->ep[ep].type[0] = value;
 991         break;
 992     case MUSB_HDRC_TXINTERVAL:
 993         s->ep[ep].interval[0] = value;
 994         musb_ep_frame_cancel(&s->ep[ep], 0);
 995         break;
 996     case MUSB_HDRC_RXTYPE:
 997         s->ep[ep].type[1] = value;
 998         break;
 999     case MUSB_HDRC_RXINTERVAL:
1000         s->ep[ep].interval[1] = value;
1001         musb_ep_frame_cancel(&s->ep[ep], 1);
1002         break;
1003     case (MUSB_HDRC_FIFOSIZE & ~1):
1004         break;
1005     case MUSB_HDRC_FIFOSIZE:
1006         printf("%s: somebody messes with fifosize (now %i bytes)\n",
1007                         __FUNCTION__, value);
1008         s->ep[ep].fifosize = value;
1009         break;
1010
1011     default:
1012         printf("%s: unknown register at %02x\n", __FUNCTION__, addr);
1013     };
1014 }
1015
1016 static uint16_t musb_ep_readh(void *opaque, int ep, int addr)
1017 {
1018     MUSBState *s = (MUSBState *) opaque;
1019     uint16_t ret;
1020
1021     switch (addr) {
1022     case MUSB_HDRC_TXMAXP:
1023         return s->ep[ep].maxp[0];
1024     case MUSB_HDRC_TXCSR:
1025         return s->ep[ep].csr[0];
1026     case MUSB_HDRC_RXMAXP:
1027         return s->ep[ep].maxp[1];
1028     case MUSB_HDRC_RXCSR:
1029         ret = s->ep[ep].csr[1];
1030
1031         /* TODO: This and other bits probably depend on
1032          * ep->csr[1] & MGC_M_RXCSR_AUTOCLEAR.  */
1033         if (s->ep[ep].csr[1] & MGC_M_RXCSR_AUTOCLEAR)
1034             s->ep[ep].csr[1] &= ~MGC_M_RXCSR_RXPKTRDY;
1035
1036         return ret;
1037     case MUSB_HDRC_RXCOUNT:
1038         return s->ep[ep].rxcount;
1039
1040     default:
1041         return musb_ep_readb(s, ep, addr) |
1042                 (musb_ep_readb(s, ep, addr | 1) << 8);
1043     };
1044 }
1045
1046 static void musb_ep_writeh(void *opaque, int ep, int addr, uint16_t value)
1047 {
1048     MUSBState *s = (MUSBState *) opaque;
1049
1050     switch (addr) {
1051     case MUSB_HDRC_TXMAXP:
1052         s->ep[ep].maxp[0] = value;
1053         break;
1054     case MUSB_HDRC_TXCSR:
1055         if (ep) {
1056             s->ep[ep].csr[0] &= value & 0xa6;
1057             s->ep[ep].csr[0] |= value & 0xff59;
1058         } else {
1059             s->ep[ep].csr[0] &= value & 0x85;
1060             s->ep[ep].csr[0] |= value & 0xf7a;
1061         }
1062
1063         musb_ep_frame_cancel(&s->ep[ep], 0);
1064
1065         if ((ep && (value & MGC_M_TXCSR_FLUSHFIFO)) ||
1066                         (!ep && (value & MGC_M_CSR0_FLUSHFIFO))) {
1067             s->ep[ep].fifolen[0] = 0;
1068             s->ep[ep].fifostart[0] = 0;
1069             if (ep)
1070                 s->ep[ep].csr[0] &=
1071                         ~(MGC_M_TXCSR_FIFONOTEMPTY | MGC_M_TXCSR_TXPKTRDY);
1072             else
1073                 s->ep[ep].csr[0] &=
1074                         ~(MGC_M_CSR0_TXPKTRDY | MGC_M_CSR0_RXPKTRDY);
1075         }
1076         if (
1077                         (ep &&
1078 #ifdef CLEAR_NAK
1079                          (value & MGC_M_TXCSR_TXPKTRDY) &&
1080                          !(value & MGC_M_TXCSR_H_NAKTIMEOUT)) ||
1081 #else
1082                          (value & MGC_M_TXCSR_TXPKTRDY)) ||
1083 #endif
1084                         (!ep &&
1085 #ifdef CLEAR_NAK
1086                          (value & MGC_M_CSR0_TXPKTRDY) &&
1087                          !(value & MGC_M_CSR0_H_NAKTIMEOUT)))
1088 #else
1089                          (value & MGC_M_CSR0_TXPKTRDY)))
1090 #endif
1091             musb_tx_rdy(s, ep);
1092         if (!ep &&
1093                         (value & MGC_M_CSR0_H_REQPKT) &&
1094 #ifdef CLEAR_NAK
1095                         !(value & (MGC_M_CSR0_H_NAKTIMEOUT |
1096                                         MGC_M_CSR0_RXPKTRDY)))
1097 #else
1098                         !(value & MGC_M_CSR0_RXPKTRDY))
1099 #endif
1100             musb_rx_req(s, ep);
1101         break;
1102
1103     case MUSB_HDRC_RXMAXP:
1104         s->ep[ep].maxp[1] = value;
1105         break;
1106     case MUSB_HDRC_RXCSR:
1107         /* (DMA mode only) */
1108         if (
1109                 (value & MGC_M_RXCSR_H_AUTOREQ) &&
1110                 !(value & MGC_M_RXCSR_RXPKTRDY) &&
1111                 (s->ep[ep].csr[1] & MGC_M_RXCSR_RXPKTRDY))
1112             value |= MGC_M_RXCSR_H_REQPKT;
1113
1114         s->ep[ep].csr[1] &= 0x102 | (value & 0x4d);
1115         s->ep[ep].csr[1] |= value & 0xfeb0;
1116
1117         musb_ep_frame_cancel(&s->ep[ep], 1);
1118
1119         if (value & MGC_M_RXCSR_FLUSHFIFO) {
1120             s->ep[ep].fifolen[1] = 0;
1121             s->ep[ep].fifostart[1] = 0;
1122             s->ep[ep].csr[1] &= ~(MGC_M_RXCSR_FIFOFULL | MGC_M_RXCSR_RXPKTRDY);
1123             /* If double buffering and we have two packets ready, flush
1124              * only the first one and set up the fifo at the second packet.  */
1125         }
1126 #ifdef CLEAR_NAK
1127         if ((value & MGC_M_RXCSR_H_REQPKT) && !(value & MGC_M_RXCSR_DATAERROR))
1128 #else
1129         if (value & MGC_M_RXCSR_H_REQPKT)
1130 #endif
1131             musb_rx_req(s, ep);
1132         break;
1133     case MUSB_HDRC_RXCOUNT:
1134         s->ep[ep].rxcount = value;
1135         break;
1136
1137     default:
1138         musb_ep_writeb(s, ep, addr, value & 0xff);
1139         musb_ep_writeb(s, ep, addr | 1, value >> 8);
1140     };
1141 }
1142
1143 /* Generic control */
1144 static uint32_t musb_readb(void *opaque, target_phys_addr_t addr)
1145 {
1146     MUSBState *s = (MUSBState *) opaque;
1147     int ep, i;
1148     uint8_t ret;
1149
1150     switch (addr) {
1151     case MUSB_HDRC_FADDR:
1152         return s->faddr;
1153     case MUSB_HDRC_POWER:
1154         return s->power;
1155     case MUSB_HDRC_INTRUSB:
1156         ret = s->intr;
1157         for (i = 0; i < sizeof(ret) * 8; i ++)
1158             if (ret & (1 << i))
1159                 musb_intr_set(s, i, 0);
1160         return ret;
1161     case MUSB_HDRC_INTRUSBE:
1162         return s->mask;
1163     case MUSB_HDRC_INDEX:
1164         return s->idx;
1165     case MUSB_HDRC_TESTMODE:
1166         return 0x00;
1167
1168     case MUSB_HDRC_EP_IDX ... (MUSB_HDRC_EP_IDX + 0xf):
1169         return musb_ep_readb(s, s->idx, addr & 0xf);
1170
1171     case MUSB_HDRC_DEVCTL:
1172         return s->devctl;
1173
1174     case MUSB_HDRC_TXFIFOSZ:
1175     case MUSB_HDRC_RXFIFOSZ:
1176     case MUSB_HDRC_VCTRL:
1177         /* TODO */
1178         return 0x00;
1179
1180     case MUSB_HDRC_HWVERS:
1181         return (1 << 10) | 400;
1182
1183     case (MUSB_HDRC_VCTRL | 1):
1184     case (MUSB_HDRC_HWVERS | 1):
1185     case (MUSB_HDRC_DEVCTL | 1):
1186         return 0x00;
1187
1188     case MUSB_HDRC_BUSCTL ... (MUSB_HDRC_BUSCTL + 0x7f):
1189         ep = (addr >> 3) & 0xf;
1190         return musb_busctl_readb(s, ep, addr & 0x7);
1191
1192     case MUSB_HDRC_EP ... (MUSB_HDRC_EP + 0xff):
1193         ep = (addr >> 4) & 0xf;
1194         return musb_ep_readb(s, ep, addr & 0xf);
1195
1196     default:
1197         printf("%s: unknown register at %02x\n", __FUNCTION__, (int) addr);
1198         return 0x00;
1199     };
1200 }
1201
1202 static void musb_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
1203 {
1204     MUSBState *s = (MUSBState *) opaque;
1205     int ep;
1206
1207     switch (addr) {
1208     case MUSB_HDRC_FADDR:
1209         s->faddr = value & 0x7f;
1210         break;
1211     case MUSB_HDRC_POWER:
1212         s->power = (value & 0xef) | (s->power & 0x10);
1213         /* MGC_M_POWER_RESET is also read-only in Peripheral Mode */
1214         if ((value & MGC_M_POWER_RESET) && s->port.dev) {
1215             usb_send_msg(s->port.dev, USB_MSG_RESET);
1216             /* Negotiate high-speed operation if MGC_M_POWER_HSENAB is set.  */
1217             if ((value & MGC_M_POWER_HSENAB) &&
1218                             s->port.dev->speed == USB_SPEED_HIGH)
1219                 s->power |= MGC_M_POWER_HSMODE; /* Success */
1220             /* Restart frame counting.  */
1221         }
1222         if (value & MGC_M_POWER_SUSPENDM) {
1223             /* When all transfers finish, suspend and if MGC_M_POWER_ENSUSPEND
1224              * is set, also go into low power mode.  Frame counting stops.  */
1225             /* XXX: Cleared when the interrupt register is read */
1226         }
1227         if (value & MGC_M_POWER_RESUME) {
1228             /* Wait 20ms and signal resuming on the bus.  Frame counting
1229              * restarts.  */
1230         }
1231         break;
1232     case MUSB_HDRC_INTRUSB:
1233         break;
1234     case MUSB_HDRC_INTRUSBE:
1235         s->mask = value & 0xff;
1236         break;
1237     case MUSB_HDRC_INDEX:
1238         s->idx = value & 0xf;
1239         break;
1240     case MUSB_HDRC_TESTMODE:
1241         break;
1242
1243     case MUSB_HDRC_EP_IDX ... (MUSB_HDRC_EP_IDX + 0xf):
1244         musb_ep_writeb(s, s->idx, addr & 0xf, value);
1245         break;
1246
1247     case MUSB_HDRC_DEVCTL:
1248         s->session = !!(value & MGC_M_DEVCTL_SESSION);
1249         musb_session_update(s,
1250                         !!s->port.dev,
1251                         !!(s->devctl & MGC_M_DEVCTL_SESSION));
1252
1253         /* It seems this is the only R/W bit in this register?  */
1254         s->devctl &= ~MGC_M_DEVCTL_SESSION;
1255         s->devctl |= value & MGC_M_DEVCTL_SESSION;
1256         break;
1257
1258     case MUSB_HDRC_TXFIFOSZ:
1259     case MUSB_HDRC_RXFIFOSZ:
1260     case MUSB_HDRC_VCTRL:
1261         /* TODO */
1262         break;
1263
1264     case (MUSB_HDRC_VCTRL | 1):
1265     case (MUSB_HDRC_DEVCTL | 1):
1266         break;
1267
1268     case MUSB_HDRC_BUSCTL ... (MUSB_HDRC_BUSCTL + 0x7f):
1269         ep = (addr >> 3) & 0xf;
1270         musb_busctl_writeb(s, ep, addr & 0x7, value);
1271         break;
1272
1273     case MUSB_HDRC_EP ... (MUSB_HDRC_EP + 0xff):
1274         ep = (addr >> 4) & 0xf;
1275         musb_ep_writeb(s, ep, addr & 0xf, value);
1276         break;
1277
1278     default:
1279         printf("%s: unknown register at %02x\n", __FUNCTION__, (int) addr);
1280     };
1281 }
1282
1283 static uint32_t musb_readh(void *opaque, target_phys_addr_t addr)
1284 {
1285     MUSBState *s = (MUSBState *) opaque;
1286     int ep, i;
1287     uint16_t ret;
1288
1289     switch (addr) {
1290     case MUSB_HDRC_INTRTX:
1291         ret = s->tx_intr;
1292         /* Auto clear */
1293         for (i = 0; i < sizeof(ret) * 8; i ++)
1294             if (ret & (1 << i))
1295                 musb_tx_intr_set(s, i, 0);
1296         return ret;
1297     case MUSB_HDRC_INTRRX:
1298         ret = s->rx_intr;
1299         /* Auto clear */
1300         for (i = 0; i < sizeof(ret) * 8; i ++)
1301             if (ret & (1 << i))
1302                 musb_rx_intr_set(s, i, 0);
1303         return ret;
1304     case MUSB_HDRC_INTRTXE:
1305         return s->tx_mask;
1306     case MUSB_HDRC_INTRRXE:
1307         return s->rx_mask;
1308
1309     case MUSB_HDRC_FRAME:
1310         /* TODO */
1311         return 0x0000;
1312     case MUSB_HDRC_TXFIFOADDR:
1313         return s->ep[s->idx].fifoaddr[0];
1314     case MUSB_HDRC_RXFIFOADDR:
1315         return s->ep[s->idx].fifoaddr[1];
1316
1317     case MUSB_HDRC_EP_IDX ... (MUSB_HDRC_EP_IDX + 0xf):
1318         return musb_ep_readh(s, s->idx, addr & 0xf);
1319
1320     case MUSB_HDRC_BUSCTL ... (MUSB_HDRC_BUSCTL + 0x7f):
1321         ep = (addr >> 3) & 0xf;
1322         return musb_busctl_readh(s, ep, addr & 0x7);
1323
1324     case MUSB_HDRC_EP ... (MUSB_HDRC_EP + 0xff):
1325         ep = (addr >> 4) & 0xf;
1326         return musb_ep_readh(s, ep, addr & 0xf);
1327
1328     default:
1329         return musb_readb(s, addr) | (musb_readb(s, addr | 1) << 8);
1330     };
1331 }
1332
1333 static void musb_writeh(void *opaque, target_phys_addr_t addr, uint32_t value)
1334 {
1335     MUSBState *s = (MUSBState *) opaque;
1336     int ep;
1337
1338     switch (addr) {
1339     case MUSB_HDRC_INTRTXE:
1340         s->tx_mask = value;
1341         /* XXX: the masks seem to apply on the raising edge like with
1342          * edge-triggered interrupts, thus no need to update.  I may be
1343          * wrong though.  */
1344         break;
1345     case MUSB_HDRC_INTRRXE:
1346         s->rx_mask = value;
1347         break;
1348
1349     case MUSB_HDRC_FRAME:
1350         /* TODO */
1351         break;
1352     case MUSB_HDRC_TXFIFOADDR:
1353         s->ep[s->idx].fifoaddr[0] = value;
1354         s->ep[s->idx].buf[0] =
1355                 s->buf + ((value << 1) & (sizeof(s->buf) / 4 - 1));
1356         break;
1357     case MUSB_HDRC_RXFIFOADDR:
1358         s->ep[s->idx].fifoaddr[1] = value;
1359         s->ep[s->idx].buf[1] =
1360                 s->buf + ((value << 1) & (sizeof(s->buf) / 4 - 1));
1361         break;
1362
1363     case MUSB_HDRC_EP_IDX ... (MUSB_HDRC_EP_IDX + 0xf):
1364         musb_ep_writeh(s, s->idx, addr & 0xf, value);
1365         break;
1366
1367     case MUSB_HDRC_BUSCTL ... (MUSB_HDRC_BUSCTL + 0x7f):
1368         ep = (addr >> 3) & 0xf;
1369         musb_busctl_writeh(s, ep, addr & 0x7, value);
1370         break;
1371
1372     case MUSB_HDRC_EP ... (MUSB_HDRC_EP + 0xff):
1373         ep = (addr >> 4) & 0xf;
1374         musb_ep_writeh(s, ep, addr & 0xf, value);
1375         break;
1376
1377     default:
1378         musb_writeb(s, addr, value & 0xff);
1379         musb_writeb(s, addr | 1, value >> 8);
1380     };
1381 }
1382
1383 static uint32_t musb_readw(void *opaque, target_phys_addr_t addr)
1384 {
1385     MUSBState *s = (MUSBState *) opaque;
1386     MUSBEndPoint *ep;
1387     int epnum;
1388
1389     switch (addr) {
1390     case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
1391         epnum = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1392         ep = s->ep + epnum;
1393
1394         if (ep->fifolen[1] >= 16) {
1395             /* We have a FIFO underrun */
1396             printf("%s: EP%i FIFO is now empty, stop reading\n",
1397                             __FUNCTION__, epnum);
1398             return 0x00000000;
1399         }
1400         /* In DMA mode clear RXPKTRDY and set REQPKT automatically
1401          * (if AUTOREQ is set) */
1402
1403         ep->csr[1] &= ~MGC_M_RXCSR_FIFOFULL;
1404         return ep->buf[1][ep->fifostart[1] + ep->fifolen[1] ++];
1405
1406     default:
1407         printf("%s: unknown register at %02x\n", __FUNCTION__, (int) addr);
1408         return 0x00000000;
1409     };
1410 }
1411
1412 static void musb_writew(void *opaque, target_phys_addr_t addr, uint32_t value)
1413 {
1414     MUSBState *s = (MUSBState *) opaque;
1415     MUSBEndPoint *ep;
1416     int epnum;
1417
1418     switch (addr) {
1419     case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
1420         epnum = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1421         ep = s->ep + epnum;
1422
1423         if (ep->fifolen[0] >= 16) {
1424             /* We have a FIFO overrun */
1425             printf("%s: EP%i FIFO exceeded 64 bytes, stop feeding data\n",
1426                             __FUNCTION__, epnum);
1427             break;
1428         }
1429
1430         ep->buf[0][ep->fifostart[0] + ep->fifolen[0] ++] = value;
1431         if (epnum)
1432             ep->csr[0] |= MGC_M_TXCSR_FIFONOTEMPTY;
1433         break;
1434
1435     default:
1436         printf("%s: unknown register at %02x\n", __FUNCTION__, (int) addr);
1437     };
1438 }
1439
1440 CPUReadMemoryFunc *musb_read[] = {
1441     musb_readb,
1442     musb_readh,
1443     musb_readw,
1444 };
1445
1446 CPUWriteMemoryFunc *musb_write[] = {
1447     musb_writeb,
1448     musb_writeh,
1449     musb_writew,
1450 };