hw/mips_jazz.c

   1 /*
   2  * QEMU MIPS Jazz support
   3  *
   4  * Copyright (c) 2007-2008 Hervé Poussineau
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw.h"
  26 #include "mips.h"
  27 #include "pc.h"
  28 #include "isa.h"
  29 #include "fdc.h"
  30 #include "sysemu.h"
  31 #include "audio/audio.h"
  32 #include "boards.h"
  33 #include "net.h"
  34 #include "scsi.h"
  35 #include "mips-bios.h"
  36
  37 enum jazz_model_e
  38 {
  39     JAZZ_MAGNUM,
  40     JAZZ_PICA61,
  41 };
  42
  43 static void main_cpu_reset(void *opaque)
  44 {
  45     CPUState *env = opaque;
  46     cpu_reset(env);
  47 }
  48
  49 static uint32_t rtc_readb(void *opaque, target_phys_addr_t addr)
  50 {
  51     CPUState *env = opaque;
  52     return cpu_inw(env, 0x71);
  53 }
  54
  55 static void rtc_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
  56 {
  57     CPUState *env = opaque;
  58     cpu_outw(env, 0x71, val & 0xff);
  59 }
  60
  61 static CPUReadMemoryFunc *rtc_read[3] = {
  62     rtc_readb,
  63     rtc_readb,
  64     rtc_readb,
  65 };
  66
  67 static CPUWriteMemoryFunc *rtc_write[3] = {
  68     rtc_writeb,
  69     rtc_writeb,
  70     rtc_writeb,
  71 };
  72
  73 static void dma_dummy_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
  74 {
  75     /* Nothing to do. That is only to ensure that
  76      * the current DMA acknowledge cycle is completed. */
  77 }
  78
  79 static CPUReadMemoryFunc *dma_dummy_read[3] = {
  80     NULL,
  81     NULL,
  82     NULL,
  83 };
  84
  85 static CPUWriteMemoryFunc *dma_dummy_write[3] = {
  86     dma_dummy_writeb,
  87     dma_dummy_writeb,
  88     dma_dummy_writeb,
  89 };
  90
  91 #ifdef HAS_AUDIO
  92 static void audio_init(qemu_irq *pic)
  93 {
  94     struct soundhw *c;
  95     int audio_enabled = 0;
  96
  97     for (c = soundhw; !audio_enabled && c->name; ++c) {
  98         audio_enabled = c->enabled;
  99     }
 100
 101     if (audio_enabled) {
 102         for (c = soundhw; c->name; ++c) {
 103             if (c->enabled) {
 104                 if (c->isa) {
 105                     c->init.init_isa(pic);
 106                 }
 107             }
 108         }
 109     }
 110 }
 111 #endif
 112
 113 #define MAGNUM_BIOS_SIZE_MAX 0x7e000
 114 #define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
 115
 116 static
 117 void mips_jazz_init (ram_addr_t ram_size,
 118                      const char *cpu_model,
 119                      enum jazz_model_e jazz_model)
 120 {
 121     char *filename;
 122     int bios_size, n;
 123     CPUState *env;
 124     qemu_irq *rc4030, *i8259;
 125     rc4030_dma *dmas;
 126     void* rc4030_opaque;
 127     int s_rtc, s_dma_dummy;
 128     NICInfo *nd;
 129     PITState *pit;
 130     BlockDriverState *fds[MAX_FD];
 131     qemu_irq esp_reset;
 132     ram_addr_t ram_offset;
 133     ram_addr_t bios_offset;
 134
 135     /* init CPUs */
 136     if (cpu_model == NULL) {
 137 #ifdef TARGET_MIPS64
 138         cpu_model = "R4000";
 139 #else
 140         /* FIXME: All wrong, this maybe should be R3000 for the older JAZZs. */
 141         cpu_model = "24Kf";
 142 #endif
 143     }
 144     env = cpu_init(cpu_model);
 145     if (!env) {
 146         fprintf(stderr, "Unable to find CPU definition\n");
 147         exit(1);
 148     }
 149     qemu_register_reset(main_cpu_reset, env);
 150
 151     /* allocate RAM */
 152     ram_offset = qemu_ram_alloc(ram_size);
 153     cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
 154
 155     bios_offset = qemu_ram_alloc(MAGNUM_BIOS_SIZE);
 156     cpu_register_physical_memory(0x1fc00000LL,
 157                                  MAGNUM_BIOS_SIZE, bios_offset | IO_MEM_ROM);
 158     cpu_register_physical_memory(0xfff00000LL,
 159                                  MAGNUM_BIOS_SIZE, bios_offset | IO_MEM_ROM);
 160
 161     /* load the BIOS image. */
 162     if (bios_name == NULL)
 163         bios_name = BIOS_FILENAME;
 164     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 165     if (filename) {
 166         bios_size = load_image_targphys(filename, 0xfff00000LL,
 167                                         MAGNUM_BIOS_SIZE);
 168         qemu_free(filename);
 169     } else {
 170         bios_size = -1;
 171     }
 172     if (bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) {
 173         fprintf(stderr, "qemu: Could not load MIPS bios '%s'\n",
 174                 bios_name);
 175         exit(1);
 176     }
 177
 178     /* Init CPU internal devices */
 179     cpu_mips_irq_init_cpu(env);
 180     cpu_mips_clock_init(env);
 181
 182     /* Chipset */
 183     rc4030_opaque = rc4030_init(env->irq[6], env->irq[3], &rc4030, &dmas);
 184     s_dma_dummy = cpu_register_io_memory(dma_dummy_read, dma_dummy_write, NULL);
 185     cpu_register_physical_memory(0x8000d000, 0x00001000, s_dma_dummy);
 186
 187     /* ISA devices */
 188     i8259 = i8259_init(env->irq[4]);
 189     DMA_init(0);
 190     pit = pit_init(0x40, i8259[0]);
 191     pcspk_init(pit);
 192
 193     /* ISA IO space at 0x90000000 */
 194     isa_mmio_init(0x90000000, 0x01000000);
 195     isa_mem_base = 0x11000000;
 196
 197     /* Video card */
 198     switch (jazz_model) {
 199     case JAZZ_MAGNUM:
 200         g364fb_mm_init(0x40000000, 0x60000000, 0, rc4030[3]);
 201         break;
 202     case JAZZ_PICA61:
 203         isa_vga_mm_init(0x40000000, 0x60000000, 0);
 204         break;
 205     default:
 206         break;
 207     }
 208
 209     /* Network controller */
 210     for (n = 0; n < nb_nics; n++) {
 211         nd = &nd_table[n];
 212         if (!nd->model)
 213             nd->model = "dp83932";
 214         if (strcmp(nd->model, "dp83932") == 0) {
 215             dp83932_init(nd, 0x80001000, 2, rc4030[4],
 216                          rc4030_opaque, rc4030_dma_memory_rw);
 217             break;
 218         } else if (strcmp(nd->model, "?") == 0) {
 219             fprintf(stderr, "qemu: Supported NICs: dp83932\n");
 220             exit(1);
 221         } else {
 222             fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model);
 223             exit(1);
 224         }
 225     }
 226
 227     /* SCSI adapter */
 228     esp_init(0x80002000, 0,
 229              rc4030_dma_read, rc4030_dma_write, dmas[0],
 230              rc4030[5], &esp_reset);
 231
 232     /* Floppy */
 233     if (drive_get_max_bus(IF_FLOPPY) >= MAX_FD) {
 234         fprintf(stderr, "qemu: too many floppy drives\n");
 235         exit(1);
 236     }
 237     for (n = 0; n < MAX_FD; n++) {
 238         int fd = drive_get_index(IF_FLOPPY, 0, n);
 239         if (fd != -1)
 240             fds[n] = drives_table[fd].bdrv;
 241         else
 242             fds[n] = NULL;
 243     }
 244     fdctrl_init(rc4030[1], 0, 1, 0x80003000, fds);
 245
 246     /* Real time clock */
 247     rtc_init(0x70, i8259[8], 1980);
 248     s_rtc = cpu_register_io_memory(rtc_read, rtc_write, env);
 249     cpu_register_physical_memory(0x80004000, 0x00001000, s_rtc);
 250
 251     /* Keyboard (i8042) */
 252     i8042_mm_init(rc4030[6], rc4030[7], 0x80005000, 0x1000, 0x1);
 253
 254     /* Serial ports */
 255     if (serial_hds[0])
 256         serial_mm_init(0x80006000, 0, rc4030[8], 8000000/16, serial_hds[0], 1);
 257     if (serial_hds[1])
 258         serial_mm_init(0x80007000, 0, rc4030[9], 8000000/16, serial_hds[1], 1);
 259
 260     /* Parallel port */
 261     if (parallel_hds[0])
 262         parallel_mm_init(0x80008000, 0, rc4030[0], parallel_hds[0]);
 263
 264     /* Sound card */
 265     /* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */
 266 #ifdef HAS_AUDIO
 267     audio_init(i8259);
 268 #endif
 269
 270     /* NVRAM: Unprotected at 0x9000, Protected at 0xa000, Read only at 0xb000 */
 271     ds1225y_init(0x80009000, "nvram");
 272
 273     /* LED indicator */
 274     jazz_led_init(0x8000f000);
 275 }
 276
 277 static
 278 void mips_magnum_init (ram_addr_t ram_size,
 279                        const char *boot_device,
 280                        const char *kernel_filename, const char *kernel_cmdline,
 281                        const char *initrd_filename, const char *cpu_model)
 282 {
 283     mips_jazz_init(ram_size, cpu_model, JAZZ_MAGNUM);
 284 }
 285
 286 static
 287 void mips_pica61_init (ram_addr_t ram_size,
 288                        const char *boot_device,
 289                        const char *kernel_filename, const char *kernel_cmdline,
 290                        const char *initrd_filename, const char *cpu_model)
 291 {
 292     mips_jazz_init(ram_size, cpu_model, JAZZ_PICA61);
 293 }
 294
 295 static QEMUMachine mips_magnum_machine = {
 296     .name = "magnum",
 297     .desc = "MIPS Magnum",
 298     .init = mips_magnum_init,
 299     .use_scsi = 1,
 300 };
 301
 302 static QEMUMachine mips_pica61_machine = {
 303     .name = "pica61",
 304     .desc = "Acer Pica 61",
 305     .init = mips_pica61_init,
 306     .use_scsi = 1,
 307 };
 308
 309 static void mips_jazz_machine_init(void)
 310 {
 311     qemu_register_machine(&mips_magnum_machine);
 312     qemu_register_machine(&mips_pica61_machine);
 313 }
 314
 315 machine_init(mips_jazz_machine_init);