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migration: fix incorrect memory_global_dirty_log_start outside BQL
[qemu.git] / tcg / ppc / tcg-target.c
blobc593344db1e6ac9e7c56398cec869457cdfbc23a
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "tcg-be-ldst.h"
27
28 #if defined _CALL_DARWIN || defined __APPLE__
29 #define TCG_TARGET_CALL_DARWIN
30 #endif
31 #ifdef _CALL_SYSV
32 # define TCG_TARGET_CALL_ALIGN_ARGS 1
33 #endif
34
35 /* For some memory operations, we need a scratch that isn't R0. For the AIX
36 calling convention, we can re-use the TOC register since we'll be reloading
37 it at every call. Otherwise R12 will do nicely as neither a call-saved
38 register nor a parameter register. */
39 #ifdef _CALL_AIX
40 # define TCG_REG_TMP1 TCG_REG_R2
41 #else
42 # define TCG_REG_TMP1 TCG_REG_R12
43 #endif
44
45 /* For the 64-bit target, we don't like the 5 insn sequence needed to build
46 full 64-bit addresses. Better to have a base register to which we can
47 apply a 32-bit displacement.
48
49 There are generally three items of interest:
50 (1) helper functions in the main executable,
51 (2) TranslationBlock data structures,
52 (3) the return address in the epilogue.
53
54 For user-only, we USE_STATIC_CODE_GEN_BUFFER, so the code_gen_buffer
55 will be inside the main executable, and thus near enough to make a
56 pointer to the epilogue be within 2GB of all helper functions.
57
58 For softmmu, we'll let the kernel choose the address of code_gen_buffer,
59 and odds are it'll be somewhere close to the main malloc arena, and so
60 a pointer to the epilogue will be within 2GB of the TranslationBlocks.
61
62 For --enable-pie, everything will be kinda near everything else,
63 somewhere in high memory.
64
65 Thus we choose to keep the return address in a call-saved register. */
66 #define TCG_REG_RA TCG_REG_R31
67 #define USE_REG_RA (TCG_TARGET_REG_BITS == 64)
68
69 /* Shorthand for size of a pointer. Avoid promotion to unsigned. */
70 #define SZP ((int)sizeof(void *))
71
72 /* Shorthand for size of a register. */
73 #define SZR (TCG_TARGET_REG_BITS / 8)
74
75 #define TCG_CT_CONST_S16 0x100
76 #define TCG_CT_CONST_U16 0x200
77 #define TCG_CT_CONST_S32 0x400
78 #define TCG_CT_CONST_U32 0x800
79 #define TCG_CT_CONST_ZERO 0x1000
80 #define TCG_CT_CONST_MONE 0x2000
81
82 static tcg_insn_unit *tb_ret_addr;
83
84 #include "elf.h"
85 static bool have_isa_2_06;
86 #define HAVE_ISA_2_06 have_isa_2_06
87 #define HAVE_ISEL have_isa_2_06
88
89 #ifndef CONFIG_SOFTMMU
90 #define TCG_GUEST_BASE_REG 30
91 #endif
92
93 #ifndef NDEBUG
94 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
95 "r0",
96 "r1",
97 "r2",
98 "r3",
99 "r4",
100 "r5",
101 "r6",
102 "r7",
103 "r8",
104 "r9",
105 "r10",
106 "r11",
107 "r12",
108 "r13",
109 "r14",
110 "r15",
111 "r16",
112 "r17",
113 "r18",
114 "r19",
115 "r20",
116 "r21",
117 "r22",
118 "r23",
119 "r24",
120 "r25",
121 "r26",
122 "r27",
123 "r28",
124 "r29",
125 "r30",
126 "r31"
127 };
128 #endif
129
130 static const int tcg_target_reg_alloc_order[] = {
131 TCG_REG_R14, /* call saved registers */
132 TCG_REG_R15,
133 TCG_REG_R16,
134 TCG_REG_R17,
135 TCG_REG_R18,
136 TCG_REG_R19,
137 TCG_REG_R20,
138 TCG_REG_R21,
139 TCG_REG_R22,
140 TCG_REG_R23,
141 TCG_REG_R24,
142 TCG_REG_R25,
143 TCG_REG_R26,
144 TCG_REG_R27,
145 TCG_REG_R28,
146 TCG_REG_R29,
147 TCG_REG_R30,
148 TCG_REG_R31,
149 TCG_REG_R12, /* call clobbered, non-arguments */
150 TCG_REG_R11,
151 TCG_REG_R2,
152 TCG_REG_R13,
153 TCG_REG_R10, /* call clobbered, arguments */
154 TCG_REG_R9,
155 TCG_REG_R8,
156 TCG_REG_R7,
157 TCG_REG_R6,
158 TCG_REG_R5,
159 TCG_REG_R4,
160 TCG_REG_R3,
161 };
162
163 static const int tcg_target_call_iarg_regs[] = {
164 TCG_REG_R3,
165 TCG_REG_R4,
166 TCG_REG_R5,
167 TCG_REG_R6,
168 TCG_REG_R7,
169 TCG_REG_R8,
170 TCG_REG_R9,
171 TCG_REG_R10
172 };
173
174 static const int tcg_target_call_oarg_regs[] = {
175 TCG_REG_R3,
176 TCG_REG_R4
177 };
178
179 static const int tcg_target_callee_save_regs[] = {
180 #ifdef TCG_TARGET_CALL_DARWIN
181 TCG_REG_R11,
182 #endif
183 TCG_REG_R14,
184 TCG_REG_R15,
185 TCG_REG_R16,
186 TCG_REG_R17,
187 TCG_REG_R18,
188 TCG_REG_R19,
189 TCG_REG_R20,
190 TCG_REG_R21,
191 TCG_REG_R22,
192 TCG_REG_R23,
193 TCG_REG_R24,
194 TCG_REG_R25,
195 TCG_REG_R26,
196 TCG_REG_R27, /* currently used for the global env */
197 TCG_REG_R28,
198 TCG_REG_R29,
199 TCG_REG_R30,
200 TCG_REG_R31
201 };
202
203 static inline bool in_range_b(tcg_target_long target)
204 {
205 return target == sextract64(target, 0, 26);
206 }
207
208 static uint32_t reloc_pc24_val(tcg_insn_unit *pc, tcg_insn_unit *target)
209 {
210 ptrdiff_t disp = tcg_ptr_byte_diff(target, pc);
211 assert(in_range_b(disp));
212 return disp & 0x3fffffc;
213 }
214
215 static void reloc_pc24(tcg_insn_unit *pc, tcg_insn_unit *target)
216 {
217 *pc = (*pc & ~0x3fffffc) | reloc_pc24_val(pc, target);
218 }
219
220 static uint16_t reloc_pc14_val(tcg_insn_unit *pc, tcg_insn_unit *target)
221 {
222 ptrdiff_t disp = tcg_ptr_byte_diff(target, pc);
223 assert(disp == (int16_t) disp);
224 return disp & 0xfffc;
225 }
226
227 static void reloc_pc14(tcg_insn_unit *pc, tcg_insn_unit *target)
228 {
229 *pc = (*pc & ~0xfffc) | reloc_pc14_val(pc, target);
230 }
231
232 static inline void tcg_out_b_noaddr(TCGContext *s, int insn)
233 {
234 unsigned retrans = *s->code_ptr & 0x3fffffc;
235 tcg_out32(s, insn | retrans);
236 }
237
238 static inline void tcg_out_bc_noaddr(TCGContext *s, int insn)
239 {
240 unsigned retrans = *s->code_ptr & 0xfffc;
241 tcg_out32(s, insn | retrans);
242 }
243
244 static void patch_reloc(tcg_insn_unit *code_ptr, int type,
245 intptr_t value, intptr_t addend)
246 {
247 tcg_insn_unit *target = (tcg_insn_unit *)value;
248
249 assert(addend == 0);
250 switch (type) {
251 case R_PPC_REL14:
252 reloc_pc14(code_ptr, target);
253 break;
254 case R_PPC_REL24:
255 reloc_pc24(code_ptr, target);
256 break;
257 default:
258 tcg_abort();
259 }
260 }
261
262 /* parse target specific constraints */
263 static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
264 {
265 const char *ct_str;
266
267 ct_str = *pct_str;
268 switch (ct_str[0]) {
269 case 'A': case 'B': case 'C': case 'D':
270 ct->ct |= TCG_CT_REG;
271 tcg_regset_set_reg(ct->u.regs, 3 + ct_str[0] - 'A');
272 break;
273 case 'r':
274 ct->ct |= TCG_CT_REG;
275 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
276 break;
277 case 'L': /* qemu_ld constraint */
278 ct->ct |= TCG_CT_REG;
279 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
280 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
281 #ifdef CONFIG_SOFTMMU
282 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
283 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
284 #endif
285 break;
286 case 'S': /* qemu_st constraint */
287 ct->ct |= TCG_CT_REG;
288 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
289 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
290 #ifdef CONFIG_SOFTMMU
291 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
292 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
293 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
294 #endif
295 break;
296 case 'I':
297 ct->ct |= TCG_CT_CONST_S16;
298 break;
299 case 'J':
300 ct->ct |= TCG_CT_CONST_U16;
301 break;
302 case 'M':
303 ct->ct |= TCG_CT_CONST_MONE;
304 break;
305 case 'T':
306 ct->ct |= TCG_CT_CONST_S32;
307 break;
308 case 'U':
309 ct->ct |= TCG_CT_CONST_U32;
310 break;
311 case 'Z':
312 ct->ct |= TCG_CT_CONST_ZERO;
313 break;
314 default:
315 return -1;
316 }
317 ct_str++;
318 *pct_str = ct_str;
319 return 0;
320 }
321
322 /* test if a constant matches the constraint */
323 static int tcg_target_const_match(tcg_target_long val, TCGType type,
324 const TCGArgConstraint *arg_ct)
325 {
326 int ct = arg_ct->ct;
327 if (ct & TCG_CT_CONST) {
328 return 1;
329 }
330
331 /* The only 32-bit constraint we use aside from
332 TCG_CT_CONST is TCG_CT_CONST_S16. */
333 if (type == TCG_TYPE_I32) {
334 val = (int32_t)val;
335 }
336
337 if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) {
338 return 1;
339 } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) {
340 return 1;
341 } else if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) {
342 return 1;
343 } else if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) {
344 return 1;
345 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
346 return 1;
347 } else if ((ct & TCG_CT_CONST_MONE) && val == -1) {
348 return 1;
349 }
350 return 0;
351 }
352
353 #define OPCD(opc) ((opc)<<26)
354 #define XO19(opc) (OPCD(19)|((opc)<<1))
355 #define MD30(opc) (OPCD(30)|((opc)<<2))
356 #define MDS30(opc) (OPCD(30)|((opc)<<1))
357 #define XO31(opc) (OPCD(31)|((opc)<<1))
358 #define XO58(opc) (OPCD(58)|(opc))
359 #define XO62(opc) (OPCD(62)|(opc))
360
361 #define B OPCD( 18)
362 #define BC OPCD( 16)
363 #define LBZ OPCD( 34)
364 #define LHZ OPCD( 40)
365 #define LHA OPCD( 42)
366 #define LWZ OPCD( 32)
367 #define STB OPCD( 38)
368 #define STH OPCD( 44)
369 #define STW OPCD( 36)
370
371 #define STD XO62( 0)
372 #define STDU XO62( 1)
373 #define STDX XO31(149)
374
375 #define LD XO58( 0)
376 #define LDX XO31( 21)
377 #define LDU XO58( 1)
378 #define LWA XO58( 2)
379 #define LWAX XO31(341)
380
381 #define ADDIC OPCD( 12)
382 #define ADDI OPCD( 14)
383 #define ADDIS OPCD( 15)
384 #define ORI OPCD( 24)
385 #define ORIS OPCD( 25)
386 #define XORI OPCD( 26)
387 #define XORIS OPCD( 27)
388 #define ANDI OPCD( 28)
389 #define ANDIS OPCD( 29)
390 #define MULLI OPCD( 7)
391 #define CMPLI OPCD( 10)
392 #define CMPI OPCD( 11)
393 #define SUBFIC OPCD( 8)
394
395 #define LWZU OPCD( 33)
396 #define STWU OPCD( 37)
397
398 #define RLWIMI OPCD( 20)
399 #define RLWINM OPCD( 21)
400 #define RLWNM OPCD( 23)
401
402 #define RLDICL MD30( 0)
403 #define RLDICR MD30( 1)
404 #define RLDIMI MD30( 3)
405 #define RLDCL MDS30( 8)
406
407 #define BCLR XO19( 16)
408 #define BCCTR XO19(528)
409 #define CRAND XO19(257)
410 #define CRANDC XO19(129)
411 #define CRNAND XO19(225)
412 #define CROR XO19(449)
413 #define CRNOR XO19( 33)
414
415 #define EXTSB XO31(954)
416 #define EXTSH XO31(922)
417 #define EXTSW XO31(986)
418 #define ADD XO31(266)
419 #define ADDE XO31(138)
420 #define ADDME XO31(234)
421 #define ADDZE XO31(202)
422 #define ADDC XO31( 10)
423 #define AND XO31( 28)
424 #define SUBF XO31( 40)
425 #define SUBFC XO31( 8)
426 #define SUBFE XO31(136)
427 #define SUBFME XO31(232)
428 #define SUBFZE XO31(200)
429 #define OR XO31(444)
430 #define XOR XO31(316)
431 #define MULLW XO31(235)
432 #define MULHW XO31( 75)
433 #define MULHWU XO31( 11)
434 #define DIVW XO31(491)
435 #define DIVWU XO31(459)
436 #define CMP XO31( 0)
437 #define CMPL XO31( 32)
438 #define LHBRX XO31(790)
439 #define LWBRX XO31(534)
440 #define LDBRX XO31(532)
441 #define STHBRX XO31(918)
442 #define STWBRX XO31(662)
443 #define STDBRX XO31(660)
444 #define MFSPR XO31(339)
445 #define MTSPR XO31(467)
446 #define SRAWI XO31(824)
447 #define NEG XO31(104)
448 #define MFCR XO31( 19)
449 #define MFOCRF (MFCR | (1u << 20))
450 #define NOR XO31(124)
451 #define CNTLZW XO31( 26)
452 #define CNTLZD XO31( 58)
453 #define ANDC XO31( 60)
454 #define ORC XO31(412)
455 #define EQV XO31(284)
456 #define NAND XO31(476)
457 #define ISEL XO31( 15)
458
459 #define MULLD XO31(233)
460 #define MULHD XO31( 73)
461 #define MULHDU XO31( 9)
462 #define DIVD XO31(489)
463 #define DIVDU XO31(457)
464
465 #define LBZX XO31( 87)
466 #define LHZX XO31(279)
467 #define LHAX XO31(343)
468 #define LWZX XO31( 23)
469 #define STBX XO31(215)
470 #define STHX XO31(407)
471 #define STWX XO31(151)
472
473 #define SPR(a, b) ((((a)<<5)|(b))<<11)
474 #define LR SPR(8, 0)
475 #define CTR SPR(9, 0)
476
477 #define SLW XO31( 24)
478 #define SRW XO31(536)
479 #define SRAW XO31(792)
480
481 #define SLD XO31( 27)
482 #define SRD XO31(539)
483 #define SRAD XO31(794)
484 #define SRADI XO31(413<<1)
485
486 #define TW XO31( 4)
487 #define TRAP (TW | TO(31))
488
489 #define NOP ORI /* ori 0,0,0 */
490
491 #define RT(r) ((r)<<21)
492 #define RS(r) ((r)<<21)
493 #define RA(r) ((r)<<16)
494 #define RB(r) ((r)<<11)
495 #define TO(t) ((t)<<21)
496 #define SH(s) ((s)<<11)
497 #define MB(b) ((b)<<6)
498 #define ME(e) ((e)<<1)
499 #define BO(o) ((o)<<21)
500 #define MB64(b) ((b)<<5)
501 #define FXM(b) (1 << (19 - (b)))
502
503 #define LK 1
504
505 #define TAB(t, a, b) (RT(t) | RA(a) | RB(b))
506 #define SAB(s, a, b) (RS(s) | RA(a) | RB(b))
507 #define TAI(s, a, i) (RT(s) | RA(a) | ((i) & 0xffff))
508 #define SAI(s, a, i) (RS(s) | RA(a) | ((i) & 0xffff))
509
510 #define BF(n) ((n)<<23)
511 #define BI(n, c) (((c)+((n)*4))<<16)
512 #define BT(n, c) (((c)+((n)*4))<<21)
513 #define BA(n, c) (((c)+((n)*4))<<16)
514 #define BB(n, c) (((c)+((n)*4))<<11)
515 #define BC_(n, c) (((c)+((n)*4))<<6)
516
517 #define BO_COND_TRUE BO(12)
518 #define BO_COND_FALSE BO( 4)
519 #define BO_ALWAYS BO(20)
520
521 enum {
522 CR_LT,
523 CR_GT,
524 CR_EQ,
525 CR_SO
526 };
527
528 static const uint32_t tcg_to_bc[] = {
529 [TCG_COND_EQ] = BC | BI(7, CR_EQ) | BO_COND_TRUE,
530 [TCG_COND_NE] = BC | BI(7, CR_EQ) | BO_COND_FALSE,
531 [TCG_COND_LT] = BC | BI(7, CR_LT) | BO_COND_TRUE,
532 [TCG_COND_GE] = BC | BI(7, CR_LT) | BO_COND_FALSE,
533 [TCG_COND_LE] = BC | BI(7, CR_GT) | BO_COND_FALSE,
534 [TCG_COND_GT] = BC | BI(7, CR_GT) | BO_COND_TRUE,
535 [TCG_COND_LTU] = BC | BI(7, CR_LT) | BO_COND_TRUE,
536 [TCG_COND_GEU] = BC | BI(7, CR_LT) | BO_COND_FALSE,
537 [TCG_COND_LEU] = BC | BI(7, CR_GT) | BO_COND_FALSE,
538 [TCG_COND_GTU] = BC | BI(7, CR_GT) | BO_COND_TRUE,
539 };
540
541 /* The low bit here is set if the RA and RB fields must be inverted. */
542 static const uint32_t tcg_to_isel[] = {
543 [TCG_COND_EQ] = ISEL | BC_(7, CR_EQ),
544 [TCG_COND_NE] = ISEL | BC_(7, CR_EQ) | 1,
545 [TCG_COND_LT] = ISEL | BC_(7, CR_LT),
546 [TCG_COND_GE] = ISEL | BC_(7, CR_LT) | 1,
547 [TCG_COND_LE] = ISEL | BC_(7, CR_GT) | 1,
548 [TCG_COND_GT] = ISEL | BC_(7, CR_GT),
549 [TCG_COND_LTU] = ISEL | BC_(7, CR_LT),
550 [TCG_COND_GEU] = ISEL | BC_(7, CR_LT) | 1,
551 [TCG_COND_LEU] = ISEL | BC_(7, CR_GT) | 1,
552 [TCG_COND_GTU] = ISEL | BC_(7, CR_GT),
553 };
554
555 static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt,
556 TCGReg base, tcg_target_long offset);
557
558 static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
559 {
560 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
561 if (ret != arg) {
562 tcg_out32(s, OR | SAB(arg, ret, arg));
563 }
564 }
565
566 static inline void tcg_out_rld(TCGContext *s, int op, TCGReg ra, TCGReg rs,
567 int sh, int mb)
568 {
569 assert(TCG_TARGET_REG_BITS == 64);
570 sh = SH(sh & 0x1f) | (((sh >> 5) & 1) << 1);
571 mb = MB64((mb >> 5) | ((mb << 1) & 0x3f));
572 tcg_out32(s, op | RA(ra) | RS(rs) | sh | mb);
573 }
574
575 static inline void tcg_out_rlw(TCGContext *s, int op, TCGReg ra, TCGReg rs,
576 int sh, int mb, int me)
577 {
578 tcg_out32(s, op | RA(ra) | RS(rs) | SH(sh) | MB(mb) | ME(me));
579 }
580
581 static inline void tcg_out_ext32u(TCGContext *s, TCGReg dst, TCGReg src)
582 {
583 tcg_out_rld(s, RLDICL, dst, src, 0, 32);
584 }
585
586 static inline void tcg_out_shli32(TCGContext *s, TCGReg dst, TCGReg src, int c)
587 {
588 tcg_out_rlw(s, RLWINM, dst, src, c, 0, 31 - c);
589 }
590
591 static inline void tcg_out_shli64(TCGContext *s, TCGReg dst, TCGReg src, int c)
592 {
593 tcg_out_rld(s, RLDICR, dst, src, c, 63 - c);
594 }
595
596 static inline void tcg_out_shri32(TCGContext *s, TCGReg dst, TCGReg src, int c)
597 {
598 tcg_out_rlw(s, RLWINM, dst, src, 32 - c, c, 31);
599 }
600
601 static inline void tcg_out_shri64(TCGContext *s, TCGReg dst, TCGReg src, int c)
602 {
603 tcg_out_rld(s, RLDICL, dst, src, 64 - c, c);
604 }
605
606 static void tcg_out_movi32(TCGContext *s, TCGReg ret, int32_t arg)
607 {
608 if (arg == (int16_t) arg) {
609 tcg_out32(s, ADDI | TAI(ret, 0, arg));
610 } else {
611 tcg_out32(s, ADDIS | TAI(ret, 0, arg >> 16));
612 if (arg & 0xffff) {
613 tcg_out32(s, ORI | SAI(ret, ret, arg));
614 }
615 }
616 }
617
618 static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret,
619 tcg_target_long arg)
620 {
621 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
622 if (type == TCG_TYPE_I32 || arg == (int32_t)arg) {
623 tcg_out_movi32(s, ret, arg);
624 } else if (arg == (uint32_t)arg && !(arg & 0x8000)) {
625 tcg_out32(s, ADDI | TAI(ret, 0, arg));
626 tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16));
627 } else {
628 int32_t high;
629
630 if (USE_REG_RA) {
631 intptr_t diff = arg - (intptr_t)tb_ret_addr;
632 if (diff == (int32_t)diff) {
633 tcg_out_mem_long(s, ADDI, ADD, ret, TCG_REG_RA, diff);
634 return;
635 }
636 }
637
638 high = arg >> 31 >> 1;
639 tcg_out_movi32(s, ret, high);
640 if (high) {
641 tcg_out_shli64(s, ret, ret, 32);
642 }
643 if (arg & 0xffff0000) {
644 tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16));
645 }
646 if (arg & 0xffff) {
647 tcg_out32(s, ORI | SAI(ret, ret, arg));
648 }
649 }
650 }
651
652 static bool mask_operand(uint32_t c, int *mb, int *me)
653 {
654 uint32_t lsb, test;
655
656 /* Accept a bit pattern like:
657 0....01....1
658 1....10....0
659 0..01..10..0
660 Keep track of the transitions. */
661 if (c == 0 || c == -1) {
662 return false;
663 }
664 test = c;
665 lsb = test & -test;
666 test += lsb;
667 if (test & (test - 1)) {
668 return false;
669 }
670
671 *me = clz32(lsb);
672 *mb = test ? clz32(test & -test) + 1 : 0;
673 return true;
674 }
675
676 static bool mask64_operand(uint64_t c, int *mb, int *me)
677 {
678 uint64_t lsb;
679
680 if (c == 0) {
681 return false;
682 }
683
684 lsb = c & -c;
685 /* Accept 1..10..0. */
686 if (c == -lsb) {
687 *mb = 0;
688 *me = clz64(lsb);
689 return true;
690 }
691 /* Accept 0..01..1. */
692 if (lsb == 1 && (c & (c + 1)) == 0) {
693 *mb = clz64(c + 1) + 1;
694 *me = 63;
695 return true;
696 }
697 return false;
698 }
699
700 static void tcg_out_andi32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
701 {
702 int mb, me;
703
704 if (mask_operand(c, &mb, &me)) {
705 tcg_out_rlw(s, RLWINM, dst, src, 0, mb, me);
706 } else if ((c & 0xffff) == c) {
707 tcg_out32(s, ANDI | SAI(src, dst, c));
708 return;
709 } else if ((c & 0xffff0000) == c) {
710 tcg_out32(s, ANDIS | SAI(src, dst, c >> 16));
711 return;
712 } else {
713 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R0, c);
714 tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0));
715 }
716 }
717
718 static void tcg_out_andi64(TCGContext *s, TCGReg dst, TCGReg src, uint64_t c)
719 {
720 int mb, me;
721
722 assert(TCG_TARGET_REG_BITS == 64);
723 if (mask64_operand(c, &mb, &me)) {
724 if (mb == 0) {
725 tcg_out_rld(s, RLDICR, dst, src, 0, me);
726 } else {
727 tcg_out_rld(s, RLDICL, dst, src, 0, mb);
728 }
729 } else if ((c & 0xffff) == c) {
730 tcg_out32(s, ANDI | SAI(src, dst, c));
731 return;
732 } else if ((c & 0xffff0000) == c) {
733 tcg_out32(s, ANDIS | SAI(src, dst, c >> 16));
734 return;
735 } else {
736 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, c);
737 tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0));
738 }
739 }
740
741 static void tcg_out_zori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c,
742 int op_lo, int op_hi)
743 {
744 if (c >> 16) {
745 tcg_out32(s, op_hi | SAI(src, dst, c >> 16));
746 src = dst;
747 }
748 if (c & 0xffff) {
749 tcg_out32(s, op_lo | SAI(src, dst, c));
750 src = dst;
751 }
752 }
753
754 static void tcg_out_ori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
755 {
756 tcg_out_zori32(s, dst, src, c, ORI, ORIS);
757 }
758
759 static void tcg_out_xori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
760 {
761 tcg_out_zori32(s, dst, src, c, XORI, XORIS);
762 }
763
764 static void tcg_out_b(TCGContext *s, int mask, tcg_insn_unit *target)
765 {
766 ptrdiff_t disp = tcg_pcrel_diff(s, target);
767 if (in_range_b(disp)) {
768 tcg_out32(s, B | (disp & 0x3fffffc) | mask);
769 } else {
770 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, (uintptr_t)target);
771 tcg_out32(s, MTSPR | RS(TCG_REG_R0) | CTR);
772 tcg_out32(s, BCCTR | BO_ALWAYS | mask);
773 }
774 }
775
776 static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt,
777 TCGReg base, tcg_target_long offset)
778 {
779 tcg_target_long orig = offset, l0, l1, extra = 0, align = 0;
780 bool is_store = false;
781 TCGReg rs = TCG_REG_TMP1;
782
783 switch (opi) {
784 case LD: case LWA:
785 align = 3;
786 /* FALLTHRU */
787 default:
788 if (rt != TCG_REG_R0) {
789 rs = rt;
790 break;
791 }
792 break;
793 case STD:
794 align = 3;
795 /* FALLTHRU */
796 case STB: case STH: case STW:
797 is_store = true;
798 break;
799 }
800
801 /* For unaligned, or very large offsets, use the indexed form. */
802 if (offset & align || offset != (int32_t)offset) {
803 if (rs == base) {
804 rs = TCG_REG_R0;
805 }
806 tcg_debug_assert(!is_store || rs != rt);
807 tcg_out_movi(s, TCG_TYPE_PTR, rs, orig);
808 tcg_out32(s, opx | TAB(rt, base, rs));
809 return;
810 }
811
812 l0 = (int16_t)offset;
813 offset = (offset - l0) >> 16;
814 l1 = (int16_t)offset;
815
816 if (l1 < 0 && orig >= 0) {
817 extra = 0x4000;
818 l1 = (int16_t)(offset - 0x4000);
819 }
820 if (l1) {
821 tcg_out32(s, ADDIS | TAI(rs, base, l1));
822 base = rs;
823 }
824 if (extra) {
825 tcg_out32(s, ADDIS | TAI(rs, base, extra));
826 base = rs;
827 }
828 if (opi != ADDI || base != rt || l0 != 0) {
829 tcg_out32(s, opi | TAI(rt, base, l0));
830 }
831 }
832
833 static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret,
834 TCGReg arg1, intptr_t arg2)
835 {
836 int opi, opx;
837
838 assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
839 if (type == TCG_TYPE_I32) {
840 opi = LWZ, opx = LWZX;
841 } else {
842 opi = LD, opx = LDX;
843 }
844 tcg_out_mem_long(s, opi, opx, ret, arg1, arg2);
845 }
846
847 static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
848 TCGReg arg1, intptr_t arg2)
849 {
850 int opi, opx;
851
852 assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
853 if (type == TCG_TYPE_I32) {
854 opi = STW, opx = STWX;
855 } else {
856 opi = STD, opx = STDX;
857 }
858 tcg_out_mem_long(s, opi, opx, arg, arg1, arg2);
859 }
860
861 static void tcg_out_cmp(TCGContext *s, int cond, TCGArg arg1, TCGArg arg2,
862 int const_arg2, int cr, TCGType type)
863 {
864 int imm;
865 uint32_t op;
866
867 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
868
869 /* Simplify the comparisons below wrt CMPI. */
870 if (type == TCG_TYPE_I32) {
871 arg2 = (int32_t)arg2;
872 }
873
874 switch (cond) {
875 case TCG_COND_EQ:
876 case TCG_COND_NE:
877 if (const_arg2) {
878 if ((int16_t) arg2 == arg2) {
879 op = CMPI;
880 imm = 1;
881 break;
882 } else if ((uint16_t) arg2 == arg2) {
883 op = CMPLI;
884 imm = 1;
885 break;
886 }
887 }
888 op = CMPL;
889 imm = 0;
890 break;
891
892 case TCG_COND_LT:
893 case TCG_COND_GE:
894 case TCG_COND_LE:
895 case TCG_COND_GT:
896 if (const_arg2) {
897 if ((int16_t) arg2 == arg2) {
898 op = CMPI;
899 imm = 1;
900 break;
901 }
902 }
903 op = CMP;
904 imm = 0;
905 break;
906
907 case TCG_COND_LTU:
908 case TCG_COND_GEU:
909 case TCG_COND_LEU:
910 case TCG_COND_GTU:
911 if (const_arg2) {
912 if ((uint16_t) arg2 == arg2) {
913 op = CMPLI;
914 imm = 1;
915 break;
916 }
917 }
918 op = CMPL;
919 imm = 0;
920 break;
921
922 default:
923 tcg_abort();
924 }
925 op |= BF(cr) | ((type == TCG_TYPE_I64) << 21);
926
927 if (imm) {
928 tcg_out32(s, op | RA(arg1) | (arg2 & 0xffff));
929 } else {
930 if (const_arg2) {
931 tcg_out_movi(s, type, TCG_REG_R0, arg2);
932 arg2 = TCG_REG_R0;
933 }
934 tcg_out32(s, op | RA(arg1) | RB(arg2));
935 }
936 }
937
938 static void tcg_out_setcond_eq0(TCGContext *s, TCGType type,
939 TCGReg dst, TCGReg src)
940 {
941 if (type == TCG_TYPE_I32) {
942 tcg_out32(s, CNTLZW | RS(src) | RA(dst));
943 tcg_out_shri32(s, dst, dst, 5);
944 } else {
945 tcg_out32(s, CNTLZD | RS(src) | RA(dst));
946 tcg_out_shri64(s, dst, dst, 6);
947 }
948 }
949
950 static void tcg_out_setcond_ne0(TCGContext *s, TCGReg dst, TCGReg src)
951 {
952 /* X != 0 implies X + -1 generates a carry. Extra addition
953 trickery means: R = X-1 + ~X + C = X-1 + (-X+1) + C = C. */
954 if (dst != src) {
955 tcg_out32(s, ADDIC | TAI(dst, src, -1));
956 tcg_out32(s, SUBFE | TAB(dst, dst, src));
957 } else {
958 tcg_out32(s, ADDIC | TAI(TCG_REG_R0, src, -1));
959 tcg_out32(s, SUBFE | TAB(dst, TCG_REG_R0, src));
960 }
961 }
962
963 static TCGReg tcg_gen_setcond_xor(TCGContext *s, TCGReg arg1, TCGArg arg2,
964 bool const_arg2)
965 {
966 if (const_arg2) {
967 if ((uint32_t)arg2 == arg2) {
968 tcg_out_xori32(s, TCG_REG_R0, arg1, arg2);
969 } else {
970 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, arg2);
971 tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, TCG_REG_R0));
972 }
973 } else {
974 tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, arg2));
975 }
976 return TCG_REG_R0;
977 }
978
979 static void tcg_out_setcond(TCGContext *s, TCGType type, TCGCond cond,
980 TCGArg arg0, TCGArg arg1, TCGArg arg2,
981 int const_arg2)
982 {
983 int crop, sh;
984
985 assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32);
986
987 /* Ignore high bits of a potential constant arg2. */
988 if (type == TCG_TYPE_I32) {
989 arg2 = (uint32_t)arg2;
990 }
991
992 /* Handle common and trivial cases before handling anything else. */
993 if (arg2 == 0) {
994 switch (cond) {
995 case TCG_COND_EQ:
996 tcg_out_setcond_eq0(s, type, arg0, arg1);
997 return;
998 case TCG_COND_NE:
999 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
1000 tcg_out_ext32u(s, TCG_REG_R0, arg1);
1001 arg1 = TCG_REG_R0;
1002 }
1003 tcg_out_setcond_ne0(s, arg0, arg1);
1004 return;
1005 case TCG_COND_GE:
1006 tcg_out32(s, NOR | SAB(arg1, arg0, arg1));
1007 arg1 = arg0;
1008 /* FALLTHRU */
1009 case TCG_COND_LT:
1010 /* Extract the sign bit. */
1011 if (type == TCG_TYPE_I32) {
1012 tcg_out_shri32(s, arg0, arg1, 31);
1013 } else {
1014 tcg_out_shri64(s, arg0, arg1, 63);
1015 }
1016 return;
1017 default:
1018 break;
1019 }
1020 }
1021
1022 /* If we have ISEL, we can implement everything with 3 or 4 insns.
1023 All other cases below are also at least 3 insns, so speed up the
1024 code generator by not considering them and always using ISEL. */
1025 if (HAVE_ISEL) {
1026 int isel, tab;
1027
1028 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
1029
1030 isel = tcg_to_isel[cond];
1031
1032 tcg_out_movi(s, type, arg0, 1);
1033 if (isel & 1) {
1034 /* arg0 = (bc ? 0 : 1) */
1035 tab = TAB(arg0, 0, arg0);
1036 isel &= ~1;
1037 } else {
1038 /* arg0 = (bc ? 1 : 0) */
1039 tcg_out_movi(s, type, TCG_REG_R0, 0);
1040 tab = TAB(arg0, arg0, TCG_REG_R0);
1041 }
1042 tcg_out32(s, isel | tab);
1043 return;
1044 }
1045
1046 switch (cond) {
1047 case TCG_COND_EQ:
1048 arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2);
1049 tcg_out_setcond_eq0(s, type, arg0, arg1);
1050 return;
1051
1052 case TCG_COND_NE:
1053 arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2);
1054 /* Discard the high bits only once, rather than both inputs. */
1055 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
1056 tcg_out_ext32u(s, TCG_REG_R0, arg1);
1057 arg1 = TCG_REG_R0;
1058 }
1059 tcg_out_setcond_ne0(s, arg0, arg1);
1060 return;
1061
1062 case TCG_COND_GT:
1063 case TCG_COND_GTU:
1064 sh = 30;
1065 crop = 0;
1066 goto crtest;
1067
1068 case TCG_COND_LT:
1069 case TCG_COND_LTU:
1070 sh = 29;
1071 crop = 0;
1072 goto crtest;
1073
1074 case TCG_COND_GE:
1075 case TCG_COND_GEU:
1076 sh = 31;
1077 crop = CRNOR | BT(7, CR_EQ) | BA(7, CR_LT) | BB(7, CR_LT);
1078 goto crtest;
1079
1080 case TCG_COND_LE:
1081 case TCG_COND_LEU:
1082 sh = 31;
1083 crop = CRNOR | BT(7, CR_EQ) | BA(7, CR_GT) | BB(7, CR_GT);
1084 crtest:
1085 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
1086 if (crop) {
1087 tcg_out32(s, crop);
1088 }
1089 tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7));
1090 tcg_out_rlw(s, RLWINM, arg0, TCG_REG_R0, sh, 31, 31);
1091 break;
1092
1093 default:
1094 tcg_abort();
1095 }
1096 }
1097
1098 static void tcg_out_bc(TCGContext *s, int bc, TCGLabel *l)
1099 {
1100 if (l->has_value) {
1101 tcg_out32(s, bc | reloc_pc14_val(s->code_ptr, l->u.value_ptr));
1102 } else {
1103 tcg_out_reloc(s, s->code_ptr, R_PPC_REL14, l, 0);
1104 tcg_out_bc_noaddr(s, bc);
1105 }
1106 }
1107
1108 static void tcg_out_brcond(TCGContext *s, TCGCond cond,
1109 TCGArg arg1, TCGArg arg2, int const_arg2,
1110 TCGLabel *l, TCGType type)
1111 {
1112 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
1113 tcg_out_bc(s, tcg_to_bc[cond], l);
1114 }
1115
1116 static void tcg_out_movcond(TCGContext *s, TCGType type, TCGCond cond,
1117 TCGArg dest, TCGArg c1, TCGArg c2, TCGArg v1,
1118 TCGArg v2, bool const_c2)
1119 {
1120 /* If for some reason both inputs are zero, don't produce bad code. */
1121 if (v1 == 0 && v2 == 0) {
1122 tcg_out_movi(s, type, dest, 0);
1123 return;
1124 }
1125
1126 tcg_out_cmp(s, cond, c1, c2, const_c2, 7, type);
1127
1128 if (HAVE_ISEL) {
1129 int isel = tcg_to_isel[cond];
1130
1131 /* Swap the V operands if the operation indicates inversion. */
1132 if (isel & 1) {
1133 int t = v1;
1134 v1 = v2;
1135 v2 = t;
1136 isel &= ~1;
1137 }
1138 /* V1 == 0 is handled by isel; V2 == 0 must be handled by hand. */
1139 if (v2 == 0) {
1140 tcg_out_movi(s, type, TCG_REG_R0, 0);
1141 }
1142 tcg_out32(s, isel | TAB(dest, v1, v2));
1143 } else {
1144 if (dest == v2) {
1145 cond = tcg_invert_cond(cond);
1146 v2 = v1;
1147 } else if (dest != v1) {
1148 if (v1 == 0) {
1149 tcg_out_movi(s, type, dest, 0);
1150 } else {
1151 tcg_out_mov(s, type, dest, v1);
1152 }
1153 }
1154 /* Branch forward over one insn */
1155 tcg_out32(s, tcg_to_bc[cond] | 8);
1156 if (v2 == 0) {
1157 tcg_out_movi(s, type, dest, 0);
1158 } else {
1159 tcg_out_mov(s, type, dest, v2);
1160 }
1161 }
1162 }
1163
1164 static void tcg_out_cmp2(TCGContext *s, const TCGArg *args,
1165 const int *const_args)
1166 {
1167 static const struct { uint8_t bit1, bit2; } bits[] = {
1168 [TCG_COND_LT ] = { CR_LT, CR_LT },
1169 [TCG_COND_LE ] = { CR_LT, CR_GT },
1170 [TCG_COND_GT ] = { CR_GT, CR_GT },
1171 [TCG_COND_GE ] = { CR_GT, CR_LT },
1172 [TCG_COND_LTU] = { CR_LT, CR_LT },
1173 [TCG_COND_LEU] = { CR_LT, CR_GT },
1174 [TCG_COND_GTU] = { CR_GT, CR_GT },
1175 [TCG_COND_GEU] = { CR_GT, CR_LT },
1176 };
1177
1178 TCGCond cond = args[4], cond2;
1179 TCGArg al, ah, bl, bh;
1180 int blconst, bhconst;
1181 int op, bit1, bit2;
1182
1183 al = args[0];
1184 ah = args[1];
1185 bl = args[2];
1186 bh = args[3];
1187 blconst = const_args[2];
1188 bhconst = const_args[3];
1189
1190 switch (cond) {
1191 case TCG_COND_EQ:
1192 op = CRAND;
1193 goto do_equality;
1194 case TCG_COND_NE:
1195 op = CRNAND;
1196 do_equality:
1197 tcg_out_cmp(s, cond, al, bl, blconst, 6, TCG_TYPE_I32);
1198 tcg_out_cmp(s, cond, ah, bh, bhconst, 7, TCG_TYPE_I32);
1199 tcg_out32(s, op | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ));
1200 break;
1201
1202 case TCG_COND_LT:
1203 case TCG_COND_LE:
1204 case TCG_COND_GT:
1205 case TCG_COND_GE:
1206 case TCG_COND_LTU:
1207 case TCG_COND_LEU:
1208 case TCG_COND_GTU:
1209 case TCG_COND_GEU:
1210 bit1 = bits[cond].bit1;
1211 bit2 = bits[cond].bit2;
1212 op = (bit1 != bit2 ? CRANDC : CRAND);
1213 cond2 = tcg_unsigned_cond(cond);
1214
1215 tcg_out_cmp(s, cond, ah, bh, bhconst, 6, TCG_TYPE_I32);
1216 tcg_out_cmp(s, cond2, al, bl, blconst, 7, TCG_TYPE_I32);
1217 tcg_out32(s, op | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, bit2));
1218 tcg_out32(s, CROR | BT(7, CR_EQ) | BA(6, bit1) | BB(7, CR_EQ));
1219 break;
1220
1221 default:
1222 tcg_abort();
1223 }
1224 }
1225
1226 static void tcg_out_setcond2(TCGContext *s, const TCGArg *args,
1227 const int *const_args)
1228 {
1229 tcg_out_cmp2(s, args + 1, const_args + 1);
1230 tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7));
1231 tcg_out_rlw(s, RLWINM, args[0], TCG_REG_R0, 31, 31, 31);
1232 }
1233
1234 static void tcg_out_brcond2 (TCGContext *s, const TCGArg *args,
1235 const int *const_args)
1236 {
1237 tcg_out_cmp2(s, args, const_args);
1238 tcg_out_bc(s, BC | BI(7, CR_EQ) | BO_COND_TRUE, arg_label(args[5]));
1239 }
1240
1241 void ppc_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr)
1242 {
1243 tcg_insn_unit i1, i2;
1244 uint64_t pair;
1245 intptr_t diff = addr - jmp_addr;
1246
1247 if (in_range_b(diff)) {
1248 i1 = B | (diff & 0x3fffffc);
1249 i2 = NOP;
1250 } else if (USE_REG_RA) {
1251 intptr_t lo, hi;
1252 diff = addr - (uintptr_t)tb_ret_addr;
1253 lo = (int16_t)diff;
1254 hi = (int32_t)(diff - lo);
1255 assert(diff == hi + lo);
1256 i1 = ADDIS | TAI(TCG_REG_TMP1, TCG_REG_RA, hi >> 16);
1257 i2 = ADDI | TAI(TCG_REG_TMP1, TCG_REG_TMP1, lo);
1258 } else {
1259 assert(TCG_TARGET_REG_BITS == 32 || addr == (int32_t)addr);
1260 i1 = ADDIS | TAI(TCG_REG_TMP1, 0, addr >> 16);
1261 i2 = ORI | SAI(TCG_REG_TMP1, TCG_REG_TMP1, addr);
1262 }
1263 #ifdef HOST_WORDS_BIGENDIAN
1264 pair = (uint64_t)i1 << 32 | i2;
1265 #else
1266 pair = (uint64_t)i2 << 32 | i1;
1267 #endif
1268
1269 /* ??? __atomic_store_8, presuming there's some way to do that
1270 for 32-bit, otherwise this is good enough for 64-bit. */
1271 *(uint64_t *)jmp_addr = pair;
1272 flush_icache_range(jmp_addr, jmp_addr + 8);
1273 }
1274
1275 static void tcg_out_call(TCGContext *s, tcg_insn_unit *target)
1276 {
1277 #ifdef _CALL_AIX
1278 /* Look through the descriptor. If the branch is in range, and we
1279 don't have to spend too much effort on building the toc. */
1280 void *tgt = ((void **)target)[0];
1281 uintptr_t toc = ((uintptr_t *)target)[1];
1282 intptr_t diff = tcg_pcrel_diff(s, tgt);
1283
1284 if (in_range_b(diff) && toc == (uint32_t)toc) {
1285 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, toc);
1286 tcg_out_b(s, LK, tgt);
1287 } else {
1288 /* Fold the low bits of the constant into the addresses below. */
1289 intptr_t arg = (intptr_t)target;
1290 int ofs = (int16_t)arg;
1291
1292 if (ofs + 8 < 0x8000) {
1293 arg -= ofs;
1294 } else {
1295 ofs = 0;
1296 }
1297 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, arg);
1298 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_TMP1, ofs);
1299 tcg_out32(s, MTSPR | RA(TCG_REG_R0) | CTR);
1300 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_REG_TMP1, ofs + SZP);
1301 tcg_out32(s, BCCTR | BO_ALWAYS | LK);
1302 }
1303 #elif defined(_CALL_ELF) && _CALL_ELF == 2
1304 intptr_t diff;
1305
1306 /* In the ELFv2 ABI, we have to set up r12 to contain the destination
1307 address, which the callee uses to compute its TOC address. */
1308 /* FIXME: when the branch is in range, we could avoid r12 load if we
1309 knew that the destination uses the same TOC, and what its local
1310 entry point offset is. */
1311 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R12, (intptr_t)target);
1312
1313 diff = tcg_pcrel_diff(s, target);
1314 if (in_range_b(diff)) {
1315 tcg_out_b(s, LK, target);
1316 } else {
1317 tcg_out32(s, MTSPR | RS(TCG_REG_R12) | CTR);
1318 tcg_out32(s, BCCTR | BO_ALWAYS | LK);
1319 }
1320 #else
1321 tcg_out_b(s, LK, target);
1322 #endif
1323 }
1324
1325 static const uint32_t qemu_ldx_opc[16] = {
1326 [MO_UB] = LBZX,
1327 [MO_UW] = LHZX,
1328 [MO_UL] = LWZX,
1329 [MO_Q] = LDX,
1330 [MO_SW] = LHAX,
1331 [MO_SL] = LWAX,
1332 [MO_BSWAP | MO_UB] = LBZX,
1333 [MO_BSWAP | MO_UW] = LHBRX,
1334 [MO_BSWAP | MO_UL] = LWBRX,
1335 [MO_BSWAP | MO_Q] = LDBRX,
1336 };
1337
1338 static const uint32_t qemu_stx_opc[16] = {
1339 [MO_UB] = STBX,
1340 [MO_UW] = STHX,
1341 [MO_UL] = STWX,
1342 [MO_Q] = STDX,
1343 [MO_BSWAP | MO_UB] = STBX,
1344 [MO_BSWAP | MO_UW] = STHBRX,
1345 [MO_BSWAP | MO_UL] = STWBRX,
1346 [MO_BSWAP | MO_Q] = STDBRX,
1347 };
1348
1349 static const uint32_t qemu_exts_opc[4] = {
1350 EXTSB, EXTSH, EXTSW, 0
1351 };
1352
1353 #if defined (CONFIG_SOFTMMU)
1354 /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
1355 * int mmu_idx, uintptr_t ra)
1356 */
1357 static void * const qemu_ld_helpers[16] = {
1358 [MO_UB] = helper_ret_ldub_mmu,
1359 [MO_LEUW] = helper_le_lduw_mmu,
1360 [MO_LEUL] = helper_le_ldul_mmu,
1361 [MO_LEQ] = helper_le_ldq_mmu,
1362 [MO_BEUW] = helper_be_lduw_mmu,
1363 [MO_BEUL] = helper_be_ldul_mmu,
1364 [MO_BEQ] = helper_be_ldq_mmu,
1365 };
1366
1367 /* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
1368 * uintxx_t val, int mmu_idx, uintptr_t ra)
1369 */
1370 static void * const qemu_st_helpers[16] = {
1371 [MO_UB] = helper_ret_stb_mmu,
1372 [MO_LEUW] = helper_le_stw_mmu,
1373 [MO_LEUL] = helper_le_stl_mmu,
1374 [MO_LEQ] = helper_le_stq_mmu,
1375 [MO_BEUW] = helper_be_stw_mmu,
1376 [MO_BEUL] = helper_be_stl_mmu,
1377 [MO_BEQ] = helper_be_stq_mmu,
1378 };
1379
1380 /* Perform the TLB load and compare. Places the result of the comparison
1381 in CR7, loads the addend of the TLB into R3, and returns the register
1382 containing the guest address (zero-extended into R4). Clobbers R0 and R2. */
1383
1384 static TCGReg tcg_out_tlb_read(TCGContext *s, TCGMemOp opc,
1385 TCGReg addrlo, TCGReg addrhi,
1386 int mem_index, bool is_read)
1387 {
1388 int cmp_off
1389 = (is_read
1390 ? offsetof(CPUArchState, tlb_table[mem_index][0].addr_read)
1391 : offsetof(CPUArchState, tlb_table[mem_index][0].addr_write));
1392 int add_off = offsetof(CPUArchState, tlb_table[mem_index][0].addend);
1393 TCGReg base = TCG_AREG0;
1394 TCGMemOp s_bits = opc & MO_SIZE;
1395
1396 /* Extract the page index, shifted into place for tlb index. */
1397 if (TCG_TARGET_REG_BITS == 64) {
1398 if (TARGET_LONG_BITS == 32) {
1399 /* Zero-extend the address into a place helpful for further use. */
1400 tcg_out_ext32u(s, TCG_REG_R4, addrlo);
1401 addrlo = TCG_REG_R4;
1402 } else {
1403 tcg_out_rld(s, RLDICL, TCG_REG_R3, addrlo,
1404 64 - TARGET_PAGE_BITS, 64 - CPU_TLB_BITS);
1405 }
1406 }
1407
1408 /* Compensate for very large offsets. */
1409 if (add_off >= 0x8000) {
1410 /* Most target env are smaller than 32k; none are larger than 64k.
1411 Simplify the logic here merely to offset by 0x7ff0, giving us a
1412 range just shy of 64k. Check this assumption. */
1413 QEMU_BUILD_BUG_ON(offsetof(CPUArchState,
1414 tlb_table[NB_MMU_MODES - 1][1])
1415 > 0x7ff0 + 0x7fff);
1416 tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, base, 0x7ff0));
1417 base = TCG_REG_TMP1;
1418 cmp_off -= 0x7ff0;
1419 add_off -= 0x7ff0;
1420 }
1421
1422 /* Extraction and shifting, part 2. */
1423 if (TCG_TARGET_REG_BITS == 32 || TARGET_LONG_BITS == 32) {
1424 tcg_out_rlw(s, RLWINM, TCG_REG_R3, addrlo,
1425 32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
1426 32 - (CPU_TLB_BITS + CPU_TLB_ENTRY_BITS),
1427 31 - CPU_TLB_ENTRY_BITS);
1428 } else {
1429 tcg_out_shli64(s, TCG_REG_R3, TCG_REG_R3, CPU_TLB_ENTRY_BITS);
1430 }
1431
1432 tcg_out32(s, ADD | TAB(TCG_REG_R3, TCG_REG_R3, base));
1433
1434 /* Load the tlb comparator. */
1435 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1436 tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R4, TCG_REG_R3, cmp_off);
1437 tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP1, TCG_REG_R3, cmp_off + 4);
1438 } else {
1439 tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP1, TCG_REG_R3, cmp_off);
1440 }
1441
1442 /* Load the TLB addend for use on the fast path. Do this asap
1443 to minimize any load use delay. */
1444 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_REG_R3, add_off);
1445
1446 /* Clear the non-page, non-alignment bits from the address */
1447 if (TCG_TARGET_REG_BITS == 32 || TARGET_LONG_BITS == 32) {
1448 /* We don't support unaligned accesses on 32-bits, preserve
1449 * the bottom bits and thus trigger a comparison failure on
1450 * unaligned accesses
1451 */
1452 tcg_out_rlw(s, RLWINM, TCG_REG_R0, addrlo, 0,
1453 (32 - s_bits) & 31, 31 - TARGET_PAGE_BITS);
1454 } else if (s_bits) {
1455 /* > byte access, we need to handle alignment */
1456 if ((opc & MO_AMASK) == MO_ALIGN) {
1457 /* Alignment required by the front-end, same as 32-bits */
1458 tcg_out_rld(s, RLDICL, TCG_REG_R0, addrlo,
1459 64 - TARGET_PAGE_BITS, TARGET_PAGE_BITS - s_bits);
1460 tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, TARGET_PAGE_BITS, 0);
1461 } else {
1462 /* We support unaligned accesses, we need to make sure we fail
1463 * if we cross a page boundary. The trick is to add the
1464 * access_size-1 to the address before masking the low bits.
1465 * That will make the address overflow to the next page if we
1466 * cross a page boundary which will then force a mismatch of
1467 * the TLB compare since the next page cannot possibly be in
1468 * the same TLB index.
1469 */
1470 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, (1 << s_bits) - 1));
1471 tcg_out_rld(s, RLDICR, TCG_REG_R0, TCG_REG_R0,
1472 0, 63 - TARGET_PAGE_BITS);
1473 }
1474 } else {
1475 /* Byte access, just chop off the bits below the page index */
1476 tcg_out_rld(s, RLDICR, TCG_REG_R0, addrlo, 0, 63 - TARGET_PAGE_BITS);
1477 }
1478
1479 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1480 tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1,
1481 0, 7, TCG_TYPE_I32);
1482 tcg_out_cmp(s, TCG_COND_EQ, addrhi, TCG_REG_R4, 0, 6, TCG_TYPE_I32);
1483 tcg_out32(s, CRAND | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ));
1484 } else {
1485 tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1,
1486 0, 7, TCG_TYPE_TL);
1487 }
1488
1489 return addrlo;
1490 }
1491
1492 /* Record the context of a call to the out of line helper code for the slow
1493 path for a load or store, so that we can later generate the correct
1494 helper code. */
1495 static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
1496 TCGReg datalo_reg, TCGReg datahi_reg,
1497 TCGReg addrlo_reg, TCGReg addrhi_reg,
1498 tcg_insn_unit *raddr, tcg_insn_unit *lptr)
1499 {
1500 TCGLabelQemuLdst *label = new_ldst_label(s);
1501
1502 label->is_ld = is_ld;
1503 label->oi = oi;
1504 label->datalo_reg = datalo_reg;
1505 label->datahi_reg = datahi_reg;
1506 label->addrlo_reg = addrlo_reg;
1507 label->addrhi_reg = addrhi_reg;
1508 label->raddr = raddr;
1509 label->label_ptr[0] = lptr;
1510 }
1511
1512 static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
1513 {
1514 TCGMemOpIdx oi = lb->oi;
1515 TCGMemOp opc = get_memop(oi);
1516 TCGReg hi, lo, arg = TCG_REG_R3;
1517
1518 reloc_pc14(lb->label_ptr[0], s->code_ptr);
1519
1520 tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0);
1521
1522 lo = lb->addrlo_reg;
1523 hi = lb->addrhi_reg;
1524 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1525 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
1526 arg |= 1;
1527 #endif
1528 tcg_out_mov(s, TCG_TYPE_I32, arg++, hi);
1529 tcg_out_mov(s, TCG_TYPE_I32, arg++, lo);
1530 } else {
1531 /* If the address needed to be zero-extended, we'll have already
1532 placed it in R4. The only remaining case is 64-bit guest. */
1533 tcg_out_mov(s, TCG_TYPE_TL, arg++, lo);
1534 }
1535
1536 tcg_out_movi(s, TCG_TYPE_I32, arg++, oi);
1537 tcg_out32(s, MFSPR | RT(arg) | LR);
1538
1539 tcg_out_call(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]);
1540
1541 lo = lb->datalo_reg;
1542 hi = lb->datahi_reg;
1543 if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) {
1544 tcg_out_mov(s, TCG_TYPE_I32, lo, TCG_REG_R4);
1545 tcg_out_mov(s, TCG_TYPE_I32, hi, TCG_REG_R3);
1546 } else if (opc & MO_SIGN) {
1547 uint32_t insn = qemu_exts_opc[opc & MO_SIZE];
1548 tcg_out32(s, insn | RA(lo) | RS(TCG_REG_R3));
1549 } else {
1550 tcg_out_mov(s, TCG_TYPE_REG, lo, TCG_REG_R3);
1551 }
1552
1553 tcg_out_b(s, 0, lb->raddr);
1554 }
1555
1556 static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
1557 {
1558 TCGMemOpIdx oi = lb->oi;
1559 TCGMemOp opc = get_memop(oi);
1560 TCGMemOp s_bits = opc & MO_SIZE;
1561 TCGReg hi, lo, arg = TCG_REG_R3;
1562
1563 reloc_pc14(lb->label_ptr[0], s->code_ptr);
1564
1565 tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0);
1566
1567 lo = lb->addrlo_reg;
1568 hi = lb->addrhi_reg;
1569 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
1570 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
1571 arg |= 1;
1572 #endif
1573 tcg_out_mov(s, TCG_TYPE_I32, arg++, hi);
1574 tcg_out_mov(s, TCG_TYPE_I32, arg++, lo);
1575 } else {
1576 /* If the address needed to be zero-extended, we'll have already
1577 placed it in R4. The only remaining case is 64-bit guest. */
1578 tcg_out_mov(s, TCG_TYPE_TL, arg++, lo);
1579 }
1580
1581 lo = lb->datalo_reg;
1582 hi = lb->datahi_reg;
1583 if (TCG_TARGET_REG_BITS == 32) {
1584 switch (s_bits) {
1585 case MO_64:
1586 #ifdef TCG_TARGET_CALL_ALIGN_ARGS
1587 arg |= 1;
1588 #endif
1589 tcg_out_mov(s, TCG_TYPE_I32, arg++, hi);
1590 /* FALLTHRU */
1591 case MO_32:
1592 tcg_out_mov(s, TCG_TYPE_I32, arg++, lo);
1593 break;
1594 default:
1595 tcg_out_rlw(s, RLWINM, arg++, lo, 0, 32 - (8 << s_bits), 31);
1596 break;
1597 }
1598 } else {
1599 if (s_bits == MO_64) {
1600 tcg_out_mov(s, TCG_TYPE_I64, arg++, lo);
1601 } else {
1602 tcg_out_rld(s, RLDICL, arg++, lo, 0, 64 - (8 << s_bits));
1603 }
1604 }
1605
1606 tcg_out_movi(s, TCG_TYPE_I32, arg++, oi);
1607 tcg_out32(s, MFSPR | RT(arg) | LR);
1608
1609 tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]);
1610
1611 tcg_out_b(s, 0, lb->raddr);
1612 }
1613 #endif /* SOFTMMU */
1614
1615 static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
1616 {
1617 TCGReg datalo, datahi, addrlo, rbase;
1618 TCGReg addrhi __attribute__((unused));
1619 TCGMemOpIdx oi;
1620 TCGMemOp opc, s_bits;
1621 #ifdef CONFIG_SOFTMMU
1622 int mem_index;
1623 tcg_insn_unit *label_ptr;
1624 #endif
1625
1626 datalo = *args++;
1627 datahi = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
1628 addrlo = *args++;
1629 addrhi = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
1630 oi = *args++;
1631 opc = get_memop(oi);
1632 s_bits = opc & MO_SIZE;
1633
1634 #ifdef CONFIG_SOFTMMU
1635 mem_index = get_mmuidx(oi);
1636 addrlo = tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, true);
1637
1638 /* Load a pointer into the current opcode w/conditional branch-link. */
1639 label_ptr = s->code_ptr;
1640 tcg_out_bc_noaddr(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK);
1641
1642 rbase = TCG_REG_R3;
1643 #else /* !CONFIG_SOFTMMU */
1644 rbase = guest_base ? TCG_GUEST_BASE_REG : 0;
1645 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
1646 tcg_out_ext32u(s, TCG_REG_TMP1, addrlo);
1647 addrlo = TCG_REG_TMP1;
1648 }
1649 #endif
1650
1651 if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) {
1652 if (opc & MO_BSWAP) {
1653 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
1654 tcg_out32(s, LWBRX | TAB(datalo, rbase, addrlo));
1655 tcg_out32(s, LWBRX | TAB(datahi, rbase, TCG_REG_R0));
1656 } else if (rbase != 0) {
1657 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
1658 tcg_out32(s, LWZX | TAB(datahi, rbase, addrlo));
1659 tcg_out32(s, LWZX | TAB(datalo, rbase, TCG_REG_R0));
1660 } else if (addrlo == datahi) {
1661 tcg_out32(s, LWZ | TAI(datalo, addrlo, 4));
1662 tcg_out32(s, LWZ | TAI(datahi, addrlo, 0));
1663 } else {
1664 tcg_out32(s, LWZ | TAI(datahi, addrlo, 0));
1665 tcg_out32(s, LWZ | TAI(datalo, addrlo, 4));
1666 }
1667 } else {
1668 uint32_t insn = qemu_ldx_opc[opc & (MO_BSWAP | MO_SSIZE)];
1669 if (!HAVE_ISA_2_06 && insn == LDBRX) {
1670 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
1671 tcg_out32(s, LWBRX | TAB(datalo, rbase, addrlo));
1672 tcg_out32(s, LWBRX | TAB(TCG_REG_R0, rbase, TCG_REG_R0));
1673 tcg_out_rld(s, RLDIMI, datalo, TCG_REG_R0, 32, 0);
1674 } else if (insn) {
1675 tcg_out32(s, insn | TAB(datalo, rbase, addrlo));
1676 } else {
1677 insn = qemu_ldx_opc[opc & (MO_SIZE | MO_BSWAP)];
1678 tcg_out32(s, insn | TAB(datalo, rbase, addrlo));
1679 insn = qemu_exts_opc[s_bits];
1680 tcg_out32(s, insn | RA(datalo) | RS(datalo));
1681 }
1682 }
1683
1684 #ifdef CONFIG_SOFTMMU
1685 add_qemu_ldst_label(s, true, oi, datalo, datahi, addrlo, addrhi,
1686 s->code_ptr, label_ptr);
1687 #endif
1688 }
1689
1690 static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
1691 {
1692 TCGReg datalo, datahi, addrlo, rbase;
1693 TCGReg addrhi __attribute__((unused));
1694 TCGMemOpIdx oi;
1695 TCGMemOp opc, s_bits;
1696 #ifdef CONFIG_SOFTMMU
1697 int mem_index;
1698 tcg_insn_unit *label_ptr;
1699 #endif
1700
1701 datalo = *args++;
1702 datahi = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
1703 addrlo = *args++;
1704 addrhi = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
1705 oi = *args++;
1706 opc = get_memop(oi);
1707 s_bits = opc & MO_SIZE;
1708
1709 #ifdef CONFIG_SOFTMMU
1710 mem_index = get_mmuidx(oi);
1711 addrlo = tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, false);
1712
1713 /* Load a pointer into the current opcode w/conditional branch-link. */
1714 label_ptr = s->code_ptr;
1715 tcg_out_bc_noaddr(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK);
1716
1717 rbase = TCG_REG_R3;
1718 #else /* !CONFIG_SOFTMMU */
1719 rbase = guest_base ? TCG_GUEST_BASE_REG : 0;
1720 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
1721 tcg_out_ext32u(s, TCG_REG_TMP1, addrlo);
1722 addrlo = TCG_REG_TMP1;
1723 }
1724 #endif
1725
1726 if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) {
1727 if (opc & MO_BSWAP) {
1728 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
1729 tcg_out32(s, STWBRX | SAB(datalo, rbase, addrlo));
1730 tcg_out32(s, STWBRX | SAB(datahi, rbase, TCG_REG_R0));
1731 } else if (rbase != 0) {
1732 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4));
1733 tcg_out32(s, STWX | SAB(datahi, rbase, addrlo));
1734 tcg_out32(s, STWX | SAB(datalo, rbase, TCG_REG_R0));
1735 } else {
1736 tcg_out32(s, STW | TAI(datahi, addrlo, 0));
1737 tcg_out32(s, STW | TAI(datalo, addrlo, 4));
1738 }
1739 } else {
1740 uint32_t insn = qemu_stx_opc[opc & (MO_BSWAP | MO_SIZE)];
1741 if (!HAVE_ISA_2_06 && insn == STDBRX) {
1742 tcg_out32(s, STWBRX | SAB(datalo, rbase, addrlo));
1743 tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, addrlo, 4));
1744 tcg_out_shri64(s, TCG_REG_R0, datalo, 32);
1745 tcg_out32(s, STWBRX | SAB(TCG_REG_R0, rbase, TCG_REG_TMP1));
1746 } else {
1747 tcg_out32(s, insn | SAB(datalo, rbase, addrlo));
1748 }
1749 }
1750
1751 #ifdef CONFIG_SOFTMMU
1752 add_qemu_ldst_label(s, false, oi, datalo, datahi, addrlo, addrhi,
1753 s->code_ptr, label_ptr);
1754 #endif
1755 }
1756
1757 /* Parameters for function call generation, used in tcg.c. */
1758 #define TCG_TARGET_STACK_ALIGN 16
1759 #define TCG_TARGET_EXTEND_ARGS 1
1760
1761 #ifdef _CALL_AIX
1762 # define LINK_AREA_SIZE (6 * SZR)
1763 # define LR_OFFSET (1 * SZR)
1764 # define TCG_TARGET_CALL_STACK_OFFSET (LINK_AREA_SIZE + 8 * SZR)
1765 #elif defined(TCG_TARGET_CALL_DARWIN)
1766 # define LINK_AREA_SIZE (6 * SZR)
1767 # define LR_OFFSET (2 * SZR)
1768 #elif TCG_TARGET_REG_BITS == 64
1769 # if defined(_CALL_ELF) && _CALL_ELF == 2
1770 # define LINK_AREA_SIZE (4 * SZR)
1771 # define LR_OFFSET (1 * SZR)
1772 # endif
1773 #else /* TCG_TARGET_REG_BITS == 32 */
1774 # if defined(_CALL_SYSV)
1775 # define LINK_AREA_SIZE (2 * SZR)
1776 # define LR_OFFSET (1 * SZR)
1777 # endif
1778 #endif
1779 #ifndef LR_OFFSET
1780 # error "Unhandled abi"
1781 #endif
1782 #ifndef TCG_TARGET_CALL_STACK_OFFSET
1783 # define TCG_TARGET_CALL_STACK_OFFSET LINK_AREA_SIZE
1784 #endif
1785
1786 #define CPU_TEMP_BUF_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long))
1787 #define REG_SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * SZR)
1788
1789 #define FRAME_SIZE ((TCG_TARGET_CALL_STACK_OFFSET \
1790 + TCG_STATIC_CALL_ARGS_SIZE \
1791 + CPU_TEMP_BUF_SIZE \
1792 + REG_SAVE_SIZE \
1793 + TCG_TARGET_STACK_ALIGN - 1) \
1794 & -TCG_TARGET_STACK_ALIGN)
1795
1796 #define REG_SAVE_BOT (FRAME_SIZE - REG_SAVE_SIZE)
1797
1798 static void tcg_target_qemu_prologue(TCGContext *s)
1799 {
1800 int i;
1801
1802 #ifdef _CALL_AIX
1803 void **desc = (void **)s->code_ptr;
1804 desc[0] = desc + 2; /* entry point */
1805 desc[1] = 0; /* environment pointer */
1806 s->code_ptr = (void *)(desc + 2); /* skip over descriptor */
1807 #endif
1808
1809 tcg_set_frame(s, TCG_REG_CALL_STACK, REG_SAVE_BOT - CPU_TEMP_BUF_SIZE,
1810 CPU_TEMP_BUF_SIZE);
1811
1812 /* Prologue */
1813 tcg_out32(s, MFSPR | RT(TCG_REG_R0) | LR);
1814 tcg_out32(s, (SZR == 8 ? STDU : STWU)
1815 | SAI(TCG_REG_R1, TCG_REG_R1, -FRAME_SIZE));
1816
1817 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) {
1818 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
1819 TCG_REG_R1, REG_SAVE_BOT + i * SZR);
1820 }
1821 tcg_out_st(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET);
1822
1823 #ifndef CONFIG_SOFTMMU
1824 if (guest_base) {
1825 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base);
1826 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
1827 }
1828 #endif
1829
1830 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
1831 tcg_out32(s, MTSPR | RS(tcg_target_call_iarg_regs[1]) | CTR);
1832
1833 if (USE_REG_RA) {
1834 #ifdef _CALL_AIX
1835 /* Make the caller load the value as the TOC into R2. */
1836 tb_ret_addr = s->code_ptr + 2;
1837 desc[1] = tb_ret_addr;
1838 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_RA, TCG_REG_R2);
1839 tcg_out32(s, BCCTR | BO_ALWAYS);
1840 #elif defined(_CALL_ELF) && _CALL_ELF == 2
1841 /* Compute from the incoming R12 value. */
1842 tb_ret_addr = s->code_ptr + 2;
1843 tcg_out32(s, ADDI | TAI(TCG_REG_RA, TCG_REG_R12,
1844 tcg_ptr_byte_diff(tb_ret_addr, s->code_buf)));
1845 tcg_out32(s, BCCTR | BO_ALWAYS);
1846 #else
1847 /* Reserve max 5 insns for the constant load. */
1848 tb_ret_addr = s->code_ptr + 6;
1849 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RA, (intptr_t)tb_ret_addr);
1850 tcg_out32(s, BCCTR | BO_ALWAYS);
1851 while (s->code_ptr < tb_ret_addr) {
1852 tcg_out32(s, NOP);
1853 }
1854 #endif
1855 } else {
1856 tcg_out32(s, BCCTR | BO_ALWAYS);
1857 tb_ret_addr = s->code_ptr;
1858 }
1859
1860 /* Epilogue */
1861 assert(tb_ret_addr == s->code_ptr);
1862
1863 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET);
1864 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) {
1865 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
1866 TCG_REG_R1, REG_SAVE_BOT + i * SZR);
1867 }
1868 tcg_out32(s, MTSPR | RS(TCG_REG_R0) | LR);
1869 tcg_out32(s, ADDI | TAI(TCG_REG_R1, TCG_REG_R1, FRAME_SIZE));
1870 tcg_out32(s, BCLR | BO_ALWAYS);
1871 }
1872
1873 static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
1874 const int *const_args)
1875 {
1876 TCGArg a0, a1, a2;
1877 int c;
1878
1879 switch (opc) {
1880 case INDEX_op_exit_tb:
1881 if (USE_REG_RA) {
1882 ptrdiff_t disp = tcg_pcrel_diff(s, tb_ret_addr);
1883
1884 /* Use a direct branch if we can, otherwise use the value in RA.
1885 Note that the direct branch is always backward, thus we need
1886 to account for the possibility of 5 insns from the movi. */
1887 if (!in_range_b(disp - 20)) {
1888 tcg_out32(s, MTSPR | RS(TCG_REG_RA) | CTR);
1889 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R3, args[0]);
1890 tcg_out32(s, BCCTR | BO_ALWAYS);
1891 break;
1892 }
1893 }
1894 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R3, args[0]);
1895 tcg_out_b(s, 0, tb_ret_addr);
1896 break;
1897 case INDEX_op_goto_tb:
1898 tcg_debug_assert(s->tb_jmp_offset);
1899 /* Direct jump. Ensure the next insns are 8-byte aligned. */
1900 if ((uintptr_t)s->code_ptr & 7) {
1901 tcg_out32(s, NOP);
1902 }
1903 s->tb_jmp_offset[args[0]] = tcg_current_code_size(s);
1904 /* To be replaced by either a branch+nop or a load into TMP1. */
1905 s->code_ptr += 2;
1906 tcg_out32(s, MTSPR | RS(TCG_REG_TMP1) | CTR);
1907 tcg_out32(s, BCCTR | BO_ALWAYS);
1908 s->tb_next_offset[args[0]] = tcg_current_code_size(s);
1909 break;
1910 case INDEX_op_br:
1911 {
1912 TCGLabel *l = arg_label(args[0]);
1913
1914 if (l->has_value) {
1915 tcg_out_b(s, 0, l->u.value_ptr);
1916 } else {
1917 tcg_out_reloc(s, s->code_ptr, R_PPC_REL24, l, 0);
1918 tcg_out_b_noaddr(s, B);
1919 }
1920 }
1921 break;
1922 case INDEX_op_ld8u_i32:
1923 case INDEX_op_ld8u_i64:
1924 tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]);
1925 break;
1926 case INDEX_op_ld8s_i32:
1927 case INDEX_op_ld8s_i64:
1928 tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]);
1929 tcg_out32(s, EXTSB | RS(args[0]) | RA(args[0]));
1930 break;
1931 case INDEX_op_ld16u_i32:
1932 case INDEX_op_ld16u_i64:
1933 tcg_out_mem_long(s, LHZ, LHZX, args[0], args[1], args[2]);
1934 break;
1935 case INDEX_op_ld16s_i32:
1936 case INDEX_op_ld16s_i64:
1937 tcg_out_mem_long(s, LHA, LHAX, args[0], args[1], args[2]);
1938 break;
1939 case INDEX_op_ld_i32:
1940 case INDEX_op_ld32u_i64:
1941 tcg_out_mem_long(s, LWZ, LWZX, args[0], args[1], args[2]);
1942 break;
1943 case INDEX_op_ld32s_i64:
1944 tcg_out_mem_long(s, LWA, LWAX, args[0], args[1], args[2]);
1945 break;
1946 case INDEX_op_ld_i64:
1947 tcg_out_mem_long(s, LD, LDX, args[0], args[1], args[2]);
1948 break;
1949 case INDEX_op_st8_i32:
1950 case INDEX_op_st8_i64:
1951 tcg_out_mem_long(s, STB, STBX, args[0], args[1], args[2]);
1952 break;
1953 case INDEX_op_st16_i32:
1954 case INDEX_op_st16_i64:
1955 tcg_out_mem_long(s, STH, STHX, args[0], args[1], args[2]);
1956 break;
1957 case INDEX_op_st_i32:
1958 case INDEX_op_st32_i64:
1959 tcg_out_mem_long(s, STW, STWX, args[0], args[1], args[2]);
1960 break;
1961 case INDEX_op_st_i64:
1962 tcg_out_mem_long(s, STD, STDX, args[0], args[1], args[2]);
1963 break;
1964
1965 case INDEX_op_add_i32:
1966 a0 = args[0], a1 = args[1], a2 = args[2];
1967 if (const_args[2]) {
1968 do_addi_32:
1969 tcg_out_mem_long(s, ADDI, ADD, a0, a1, (int32_t)a2);
1970 } else {
1971 tcg_out32(s, ADD | TAB(a0, a1, a2));
1972 }
1973 break;
1974 case INDEX_op_sub_i32:
1975 a0 = args[0], a1 = args[1], a2 = args[2];
1976 if (const_args[1]) {
1977 if (const_args[2]) {
1978 tcg_out_movi(s, TCG_TYPE_I32, a0, a1 - a2);
1979 } else {
1980 tcg_out32(s, SUBFIC | TAI(a0, a2, a1));
1981 }
1982 } else if (const_args[2]) {
1983 a2 = -a2;
1984 goto do_addi_32;
1985 } else {
1986 tcg_out32(s, SUBF | TAB(a0, a2, a1));
1987 }
1988 break;
1989
1990 case INDEX_op_and_i32:
1991 a0 = args[0], a1 = args[1], a2 = args[2];
1992 if (const_args[2]) {
1993 tcg_out_andi32(s, a0, a1, a2);
1994 } else {
1995 tcg_out32(s, AND | SAB(a1, a0, a2));
1996 }
1997 break;
1998 case INDEX_op_and_i64:
1999 a0 = args[0], a1 = args[1], a2 = args[2];
2000 if (const_args[2]) {
2001 tcg_out_andi64(s, a0, a1, a2);
2002 } else {
2003 tcg_out32(s, AND | SAB(a1, a0, a2));
2004 }
2005 break;
2006 case INDEX_op_or_i64:
2007 case INDEX_op_or_i32:
2008 a0 = args[0], a1 = args[1], a2 = args[2];
2009 if (const_args[2]) {
2010 tcg_out_ori32(s, a0, a1, a2);
2011 } else {
2012 tcg_out32(s, OR | SAB(a1, a0, a2));
2013 }
2014 break;
2015 case INDEX_op_xor_i64:
2016 case INDEX_op_xor_i32:
2017 a0 = args[0], a1 = args[1], a2 = args[2];
2018 if (const_args[2]) {
2019 tcg_out_xori32(s, a0, a1, a2);
2020 } else {
2021 tcg_out32(s, XOR | SAB(a1, a0, a2));
2022 }
2023 break;
2024 case INDEX_op_andc_i32:
2025 a0 = args[0], a1 = args[1], a2 = args[2];
2026 if (const_args[2]) {
2027 tcg_out_andi32(s, a0, a1, ~a2);
2028 } else {
2029 tcg_out32(s, ANDC | SAB(a1, a0, a2));
2030 }
2031 break;
2032 case INDEX_op_andc_i64:
2033 a0 = args[0], a1 = args[1], a2 = args[2];
2034 if (const_args[2]) {
2035 tcg_out_andi64(s, a0, a1, ~a2);
2036 } else {
2037 tcg_out32(s, ANDC | SAB(a1, a0, a2));
2038 }
2039 break;
2040 case INDEX_op_orc_i32:
2041 if (const_args[2]) {
2042 tcg_out_ori32(s, args[0], args[1], ~args[2]);
2043 break;
2044 }
2045 /* FALLTHRU */
2046 case INDEX_op_orc_i64:
2047 tcg_out32(s, ORC | SAB(args[1], args[0], args[2]));
2048 break;
2049 case INDEX_op_eqv_i32:
2050 if (const_args[2]) {
2051 tcg_out_xori32(s, args[0], args[1], ~args[2]);
2052 break;
2053 }
2054 /* FALLTHRU */
2055 case INDEX_op_eqv_i64:
2056 tcg_out32(s, EQV | SAB(args[1], args[0], args[2]));
2057 break;
2058 case INDEX_op_nand_i32:
2059 case INDEX_op_nand_i64:
2060 tcg_out32(s, NAND | SAB(args[1], args[0], args[2]));
2061 break;
2062 case INDEX_op_nor_i32:
2063 case INDEX_op_nor_i64:
2064 tcg_out32(s, NOR | SAB(args[1], args[0], args[2]));
2065 break;
2066
2067 case INDEX_op_mul_i32:
2068 a0 = args[0], a1 = args[1], a2 = args[2];
2069 if (const_args[2]) {
2070 tcg_out32(s, MULLI | TAI(a0, a1, a2));
2071 } else {
2072 tcg_out32(s, MULLW | TAB(a0, a1, a2));
2073 }
2074 break;
2075
2076 case INDEX_op_div_i32:
2077 tcg_out32(s, DIVW | TAB(args[0], args[1], args[2]));
2078 break;
2079
2080 case INDEX_op_divu_i32:
2081 tcg_out32(s, DIVWU | TAB(args[0], args[1], args[2]));
2082 break;
2083
2084 case INDEX_op_shl_i32:
2085 if (const_args[2]) {
2086 tcg_out_shli32(s, args[0], args[1], args[2]);
2087 } else {
2088 tcg_out32(s, SLW | SAB(args[1], args[0], args[2]));
2089 }
2090 break;
2091 case INDEX_op_shr_i32:
2092 if (const_args[2]) {
2093 tcg_out_shri32(s, args[0], args[1], args[2]);
2094 } else {
2095 tcg_out32(s, SRW | SAB(args[1], args[0], args[2]));
2096 }
2097 break;
2098 case INDEX_op_sar_i32:
2099 if (const_args[2]) {
2100 tcg_out32(s, SRAWI | RS(args[1]) | RA(args[0]) | SH(args[2]));
2101 } else {
2102 tcg_out32(s, SRAW | SAB(args[1], args[0], args[2]));
2103 }
2104 break;
2105 case INDEX_op_rotl_i32:
2106 if (const_args[2]) {
2107 tcg_out_rlw(s, RLWINM, args[0], args[1], args[2], 0, 31);
2108 } else {
2109 tcg_out32(s, RLWNM | SAB(args[1], args[0], args[2])
2110 | MB(0) | ME(31));
2111 }
2112 break;
2113 case INDEX_op_rotr_i32:
2114 if (const_args[2]) {
2115 tcg_out_rlw(s, RLWINM, args[0], args[1], 32 - args[2], 0, 31);
2116 } else {
2117 tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 32));
2118 tcg_out32(s, RLWNM | SAB(args[1], args[0], TCG_REG_R0)
2119 | MB(0) | ME(31));
2120 }
2121 break;
2122
2123 case INDEX_op_brcond_i32:
2124 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
2125 arg_label(args[3]), TCG_TYPE_I32);
2126 break;
2127 case INDEX_op_brcond_i64:
2128 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
2129 arg_label(args[3]), TCG_TYPE_I64);
2130 break;
2131 case INDEX_op_brcond2_i32:
2132 tcg_out_brcond2(s, args, const_args);
2133 break;
2134
2135 case INDEX_op_neg_i32:
2136 case INDEX_op_neg_i64:
2137 tcg_out32(s, NEG | RT(args[0]) | RA(args[1]));
2138 break;
2139
2140 case INDEX_op_not_i32:
2141 case INDEX_op_not_i64:
2142 tcg_out32(s, NOR | SAB(args[1], args[0], args[1]));
2143 break;
2144
2145 case INDEX_op_add_i64:
2146 a0 = args[0], a1 = args[1], a2 = args[2];
2147 if (const_args[2]) {
2148 do_addi_64:
2149 tcg_out_mem_long(s, ADDI, ADD, a0, a1, a2);
2150 } else {
2151 tcg_out32(s, ADD | TAB(a0, a1, a2));
2152 }
2153 break;
2154 case INDEX_op_sub_i64:
2155 a0 = args[0], a1 = args[1], a2 = args[2];
2156 if (const_args[1]) {
2157 if (const_args[2]) {
2158 tcg_out_movi(s, TCG_TYPE_I64, a0, a1 - a2);
2159 } else {
2160 tcg_out32(s, SUBFIC | TAI(a0, a2, a1));
2161 }
2162 } else if (const_args[2]) {
2163 a2 = -a2;
2164 goto do_addi_64;
2165 } else {
2166 tcg_out32(s, SUBF | TAB(a0, a2, a1));
2167 }
2168 break;
2169
2170 case INDEX_op_shl_i64:
2171 if (const_args[2]) {
2172 tcg_out_shli64(s, args[0], args[1], args[2]);
2173 } else {
2174 tcg_out32(s, SLD | SAB(args[1], args[0], args[2]));
2175 }
2176 break;
2177 case INDEX_op_shr_i64:
2178 if (const_args[2]) {
2179 tcg_out_shri64(s, args[0], args[1], args[2]);
2180 } else {
2181 tcg_out32(s, SRD | SAB(args[1], args[0], args[2]));
2182 }
2183 break;
2184 case INDEX_op_sar_i64:
2185 if (const_args[2]) {
2186 int sh = SH(args[2] & 0x1f) | (((args[2] >> 5) & 1) << 1);
2187 tcg_out32(s, SRADI | RA(args[0]) | RS(args[1]) | sh);
2188 } else {
2189 tcg_out32(s, SRAD | SAB(args[1], args[0], args[2]));
2190 }
2191 break;
2192 case INDEX_op_rotl_i64:
2193 if (const_args[2]) {
2194 tcg_out_rld(s, RLDICL, args[0], args[1], args[2], 0);
2195 } else {
2196 tcg_out32(s, RLDCL | SAB(args[1], args[0], args[2]) | MB64(0));
2197 }
2198 break;
2199 case INDEX_op_rotr_i64:
2200 if (const_args[2]) {
2201 tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 0);
2202 } else {
2203 tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 64));
2204 tcg_out32(s, RLDCL | SAB(args[1], args[0], TCG_REG_R0) | MB64(0));
2205 }
2206 break;
2207
2208 case INDEX_op_mul_i64:
2209 a0 = args[0], a1 = args[1], a2 = args[2];
2210 if (const_args[2]) {
2211 tcg_out32(s, MULLI | TAI(a0, a1, a2));
2212 } else {
2213 tcg_out32(s, MULLD | TAB(a0, a1, a2));
2214 }
2215 break;
2216 case INDEX_op_div_i64:
2217 tcg_out32(s, DIVD | TAB(args[0], args[1], args[2]));
2218 break;
2219 case INDEX_op_divu_i64:
2220 tcg_out32(s, DIVDU | TAB(args[0], args[1], args[2]));
2221 break;
2222
2223 case INDEX_op_qemu_ld_i32:
2224 tcg_out_qemu_ld(s, args, false);
2225 break;
2226 case INDEX_op_qemu_ld_i64:
2227 tcg_out_qemu_ld(s, args, true);
2228 break;
2229 case INDEX_op_qemu_st_i32:
2230 tcg_out_qemu_st(s, args, false);
2231 break;
2232 case INDEX_op_qemu_st_i64:
2233 tcg_out_qemu_st(s, args, true);
2234 break;
2235
2236 case INDEX_op_ext8s_i32:
2237 case INDEX_op_ext8s_i64:
2238 c = EXTSB;
2239 goto gen_ext;
2240 case INDEX_op_ext16s_i32:
2241 case INDEX_op_ext16s_i64:
2242 c = EXTSH;
2243 goto gen_ext;
2244 case INDEX_op_ext_i32_i64:
2245 case INDEX_op_ext32s_i64:
2246 c = EXTSW;
2247 goto gen_ext;
2248 gen_ext:
2249 tcg_out32(s, c | RS(args[1]) | RA(args[0]));
2250 break;
2251 case INDEX_op_extu_i32_i64:
2252 tcg_out_ext32u(s, args[0], args[1]);
2253 break;
2254
2255 case INDEX_op_setcond_i32:
2256 tcg_out_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], args[2],
2257 const_args[2]);
2258 break;
2259 case INDEX_op_setcond_i64:
2260 tcg_out_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1], args[2],
2261 const_args[2]);
2262 break;
2263 case INDEX_op_setcond2_i32:
2264 tcg_out_setcond2(s, args, const_args);
2265 break;
2266
2267 case INDEX_op_bswap16_i32:
2268 case INDEX_op_bswap16_i64:
2269 a0 = args[0], a1 = args[1];
2270 /* a1 = abcd */
2271 if (a0 != a1) {
2272 /* a0 = (a1 r<< 24) & 0xff # 000c */
2273 tcg_out_rlw(s, RLWINM, a0, a1, 24, 24, 31);
2274 /* a0 = (a0 & ~0xff00) | (a1 r<< 8) & 0xff00 # 00dc */
2275 tcg_out_rlw(s, RLWIMI, a0, a1, 8, 16, 23);
2276 } else {
2277 /* r0 = (a1 r<< 8) & 0xff00 # 00d0 */
2278 tcg_out_rlw(s, RLWINM, TCG_REG_R0, a1, 8, 16, 23);
2279 /* a0 = (a1 r<< 24) & 0xff # 000c */
2280 tcg_out_rlw(s, RLWINM, a0, a1, 24, 24, 31);
2281 /* a0 = a0 | r0 # 00dc */
2282 tcg_out32(s, OR | SAB(TCG_REG_R0, a0, a0));
2283 }
2284 break;
2285
2286 case INDEX_op_bswap32_i32:
2287 case INDEX_op_bswap32_i64:
2288 /* Stolen from gcc's builtin_bswap32 */
2289 a1 = args[1];
2290 a0 = args[0] == a1 ? TCG_REG_R0 : args[0];
2291
2292 /* a1 = args[1] # abcd */
2293 /* a0 = rotate_left (a1, 8) # bcda */
2294 tcg_out_rlw(s, RLWINM, a0, a1, 8, 0, 31);
2295 /* a0 = (a0 & ~0xff000000) | ((a1 r<< 24) & 0xff000000) # dcda */
2296 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 0, 7);
2297 /* a0 = (a0 & ~0x0000ff00) | ((a1 r<< 24) & 0x0000ff00) # dcba */
2298 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 16, 23);
2299
2300 if (a0 == TCG_REG_R0) {
2301 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
2302 }
2303 break;
2304
2305 case INDEX_op_bswap64_i64:
2306 a0 = args[0], a1 = args[1], a2 = TCG_REG_R0;
2307 if (a0 == a1) {
2308 a0 = TCG_REG_R0;
2309 a2 = a1;
2310 }
2311
2312 /* a1 = # abcd efgh */
2313 /* a0 = rl32(a1, 8) # 0000 fghe */
2314 tcg_out_rlw(s, RLWINM, a0, a1, 8, 0, 31);
2315 /* a0 = dep(a0, rl32(a1, 24), 0xff000000) # 0000 hghe */
2316 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 0, 7);
2317 /* a0 = dep(a0, rl32(a1, 24), 0x0000ff00) # 0000 hgfe */
2318 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 16, 23);
2319
2320 /* a0 = rl64(a0, 32) # hgfe 0000 */
2321 /* a2 = rl64(a1, 32) # efgh abcd */
2322 tcg_out_rld(s, RLDICL, a0, a0, 32, 0);
2323 tcg_out_rld(s, RLDICL, a2, a1, 32, 0);
2324
2325 /* a0 = dep(a0, rl32(a2, 8), 0xffffffff) # hgfe bcda */
2326 tcg_out_rlw(s, RLWIMI, a0, a2, 8, 0, 31);
2327 /* a0 = dep(a0, rl32(a2, 24), 0xff000000) # hgfe dcda */
2328 tcg_out_rlw(s, RLWIMI, a0, a2, 24, 0, 7);
2329 /* a0 = dep(a0, rl32(a2, 24), 0x0000ff00) # hgfe dcba */
2330 tcg_out_rlw(s, RLWIMI, a0, a2, 24, 16, 23);
2331
2332 if (a0 == 0) {
2333 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
2334 }
2335 break;
2336
2337 case INDEX_op_deposit_i32:
2338 if (const_args[2]) {
2339 uint32_t mask = ((2u << (args[4] - 1)) - 1) << args[3];
2340 tcg_out_andi32(s, args[0], args[0], ~mask);
2341 } else {
2342 tcg_out_rlw(s, RLWIMI, args[0], args[2], args[3],
2343 32 - args[3] - args[4], 31 - args[3]);
2344 }
2345 break;
2346 case INDEX_op_deposit_i64:
2347 if (const_args[2]) {
2348 uint64_t mask = ((2ull << (args[4] - 1)) - 1) << args[3];
2349 tcg_out_andi64(s, args[0], args[0], ~mask);
2350 } else {
2351 tcg_out_rld(s, RLDIMI, args[0], args[2], args[3],
2352 64 - args[3] - args[4]);
2353 }
2354 break;
2355
2356 case INDEX_op_movcond_i32:
2357 tcg_out_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1], args[2],
2358 args[3], args[4], const_args[2]);
2359 break;
2360 case INDEX_op_movcond_i64:
2361 tcg_out_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1], args[2],
2362 args[3], args[4], const_args[2]);
2363 break;
2364
2365 #if TCG_TARGET_REG_BITS == 64
2366 case INDEX_op_add2_i64:
2367 #else
2368 case INDEX_op_add2_i32:
2369 #endif
2370 /* Note that the CA bit is defined based on the word size of the
2371 environment. So in 64-bit mode it's always carry-out of bit 63.
2372 The fallback code using deposit works just as well for 32-bit. */
2373 a0 = args[0], a1 = args[1];
2374 if (a0 == args[3] || (!const_args[5] && a0 == args[5])) {
2375 a0 = TCG_REG_R0;
2376 }
2377 if (const_args[4]) {
2378 tcg_out32(s, ADDIC | TAI(a0, args[2], args[4]));
2379 } else {
2380 tcg_out32(s, ADDC | TAB(a0, args[2], args[4]));
2381 }
2382 if (const_args[5]) {
2383 tcg_out32(s, (args[5] ? ADDME : ADDZE) | RT(a1) | RA(args[3]));
2384 } else {
2385 tcg_out32(s, ADDE | TAB(a1, args[3], args[5]));
2386 }
2387 if (a0 != args[0]) {
2388 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
2389 }
2390 break;
2391
2392 #if TCG_TARGET_REG_BITS == 64
2393 case INDEX_op_sub2_i64:
2394 #else
2395 case INDEX_op_sub2_i32:
2396 #endif
2397 a0 = args[0], a1 = args[1];
2398 if (a0 == args[5] || (!const_args[3] && a0 == args[3])) {
2399 a0 = TCG_REG_R0;
2400 }
2401 if (const_args[2]) {
2402 tcg_out32(s, SUBFIC | TAI(a0, args[4], args[2]));
2403 } else {
2404 tcg_out32(s, SUBFC | TAB(a0, args[4], args[2]));
2405 }
2406 if (const_args[3]) {
2407 tcg_out32(s, (args[3] ? SUBFME : SUBFZE) | RT(a1) | RA(args[5]));
2408 } else {
2409 tcg_out32(s, SUBFE | TAB(a1, args[5], args[3]));
2410 }
2411 if (a0 != args[0]) {
2412 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
2413 }
2414 break;
2415
2416 case INDEX_op_muluh_i32:
2417 tcg_out32(s, MULHWU | TAB(args[0], args[1], args[2]));
2418 break;
2419 case INDEX_op_mulsh_i32:
2420 tcg_out32(s, MULHW | TAB(args[0], args[1], args[2]));
2421 break;
2422 case INDEX_op_muluh_i64:
2423 tcg_out32(s, MULHDU | TAB(args[0], args[1], args[2]));
2424 break;
2425 case INDEX_op_mulsh_i64:
2426 tcg_out32(s, MULHD | TAB(args[0], args[1], args[2]));
2427 break;
2428
2429 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
2430 case INDEX_op_mov_i64:
2431 case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
2432 case INDEX_op_movi_i64:
2433 case INDEX_op_call: /* Always emitted via tcg_out_call. */
2434 default:
2435 tcg_abort();
2436 }
2437 }
2438
2439 static const TCGTargetOpDef ppc_op_defs[] = {
2440 { INDEX_op_exit_tb, { } },
2441 { INDEX_op_goto_tb, { } },
2442 { INDEX_op_br, { } },
2443
2444 { INDEX_op_ld8u_i32, { "r", "r" } },
2445 { INDEX_op_ld8s_i32, { "r", "r" } },
2446 { INDEX_op_ld16u_i32, { "r", "r" } },
2447 { INDEX_op_ld16s_i32, { "r", "r" } },
2448 { INDEX_op_ld_i32, { "r", "r" } },
2449
2450 { INDEX_op_st8_i32, { "r", "r" } },
2451 { INDEX_op_st16_i32, { "r", "r" } },
2452 { INDEX_op_st_i32, { "r", "r" } },
2453
2454 { INDEX_op_add_i32, { "r", "r", "ri" } },
2455 { INDEX_op_mul_i32, { "r", "r", "rI" } },
2456 { INDEX_op_div_i32, { "r", "r", "r" } },
2457 { INDEX_op_divu_i32, { "r", "r", "r" } },
2458 { INDEX_op_sub_i32, { "r", "rI", "ri" } },
2459 { INDEX_op_and_i32, { "r", "r", "ri" } },
2460 { INDEX_op_or_i32, { "r", "r", "ri" } },
2461 { INDEX_op_xor_i32, { "r", "r", "ri" } },
2462 { INDEX_op_andc_i32, { "r", "r", "ri" } },
2463 { INDEX_op_orc_i32, { "r", "r", "ri" } },
2464 { INDEX_op_eqv_i32, { "r", "r", "ri" } },
2465 { INDEX_op_nand_i32, { "r", "r", "r" } },
2466 { INDEX_op_nor_i32, { "r", "r", "r" } },
2467
2468 { INDEX_op_shl_i32, { "r", "r", "ri" } },
2469 { INDEX_op_shr_i32, { "r", "r", "ri" } },
2470 { INDEX_op_sar_i32, { "r", "r", "ri" } },
2471 { INDEX_op_rotl_i32, { "r", "r", "ri" } },
2472 { INDEX_op_rotr_i32, { "r", "r", "ri" } },
2473
2474 { INDEX_op_neg_i32, { "r", "r" } },
2475 { INDEX_op_not_i32, { "r", "r" } },
2476 { INDEX_op_ext8s_i32, { "r", "r" } },
2477 { INDEX_op_ext16s_i32, { "r", "r" } },
2478 { INDEX_op_bswap16_i32, { "r", "r" } },
2479 { INDEX_op_bswap32_i32, { "r", "r" } },
2480
2481 { INDEX_op_brcond_i32, { "r", "ri" } },
2482 { INDEX_op_setcond_i32, { "r", "r", "ri" } },
2483 { INDEX_op_movcond_i32, { "r", "r", "ri", "rZ", "rZ" } },
2484
2485 { INDEX_op_deposit_i32, { "r", "0", "rZ" } },
2486
2487 { INDEX_op_muluh_i32, { "r", "r", "r" } },
2488 { INDEX_op_mulsh_i32, { "r", "r", "r" } },
2489
2490 #if TCG_TARGET_REG_BITS == 64
2491 { INDEX_op_ld8u_i64, { "r", "r" } },
2492 { INDEX_op_ld8s_i64, { "r", "r" } },
2493 { INDEX_op_ld16u_i64, { "r", "r" } },
2494 { INDEX_op_ld16s_i64, { "r", "r" } },
2495 { INDEX_op_ld32u_i64, { "r", "r" } },
2496 { INDEX_op_ld32s_i64, { "r", "r" } },
2497 { INDEX_op_ld_i64, { "r", "r" } },
2498
2499 { INDEX_op_st8_i64, { "r", "r" } },
2500 { INDEX_op_st16_i64, { "r", "r" } },
2501 { INDEX_op_st32_i64, { "r", "r" } },
2502 { INDEX_op_st_i64, { "r", "r" } },
2503
2504 { INDEX_op_add_i64, { "r", "r", "rT" } },
2505 { INDEX_op_sub_i64, { "r", "rI", "rT" } },
2506 { INDEX_op_and_i64, { "r", "r", "ri" } },
2507 { INDEX_op_or_i64, { "r", "r", "rU" } },
2508 { INDEX_op_xor_i64, { "r", "r", "rU" } },
2509 { INDEX_op_andc_i64, { "r", "r", "ri" } },
2510 { INDEX_op_orc_i64, { "r", "r", "r" } },
2511 { INDEX_op_eqv_i64, { "r", "r", "r" } },
2512 { INDEX_op_nand_i64, { "r", "r", "r" } },
2513 { INDEX_op_nor_i64, { "r", "r", "r" } },
2514
2515 { INDEX_op_shl_i64, { "r", "r", "ri" } },
2516 { INDEX_op_shr_i64, { "r", "r", "ri" } },
2517 { INDEX_op_sar_i64, { "r", "r", "ri" } },
2518 { INDEX_op_rotl_i64, { "r", "r", "ri" } },
2519 { INDEX_op_rotr_i64, { "r", "r", "ri" } },
2520
2521 { INDEX_op_mul_i64, { "r", "r", "rI" } },
2522 { INDEX_op_div_i64, { "r", "r", "r" } },
2523 { INDEX_op_divu_i64, { "r", "r", "r" } },
2524
2525 { INDEX_op_neg_i64, { "r", "r" } },
2526 { INDEX_op_not_i64, { "r", "r" } },
2527 { INDEX_op_ext8s_i64, { "r", "r" } },
2528 { INDEX_op_ext16s_i64, { "r", "r" } },
2529 { INDEX_op_ext32s_i64, { "r", "r" } },
2530 { INDEX_op_ext_i32_i64, { "r", "r" } },
2531 { INDEX_op_extu_i32_i64, { "r", "r" } },
2532 { INDEX_op_bswap16_i64, { "r", "r" } },
2533 { INDEX_op_bswap32_i64, { "r", "r" } },
2534 { INDEX_op_bswap64_i64, { "r", "r" } },
2535
2536 { INDEX_op_brcond_i64, { "r", "ri" } },
2537 { INDEX_op_setcond_i64, { "r", "r", "ri" } },
2538 { INDEX_op_movcond_i64, { "r", "r", "ri", "rZ", "rZ" } },
2539
2540 { INDEX_op_deposit_i64, { "r", "0", "rZ" } },
2541
2542 { INDEX_op_mulsh_i64, { "r", "r", "r" } },
2543 { INDEX_op_muluh_i64, { "r", "r", "r" } },
2544 #endif
2545
2546 #if TCG_TARGET_REG_BITS == 32
2547 { INDEX_op_brcond2_i32, { "r", "r", "ri", "ri" } },
2548 { INDEX_op_setcond2_i32, { "r", "r", "r", "ri", "ri" } },
2549 #endif
2550
2551 #if TCG_TARGET_REG_BITS == 64
2552 { INDEX_op_add2_i64, { "r", "r", "r", "r", "rI", "rZM" } },
2553 { INDEX_op_sub2_i64, { "r", "r", "rI", "rZM", "r", "r" } },
2554 #else
2555 { INDEX_op_add2_i32, { "r", "r", "r", "r", "rI", "rZM" } },
2556 { INDEX_op_sub2_i32, { "r", "r", "rI", "rZM", "r", "r" } },
2557 #endif
2558
2559 #if TCG_TARGET_REG_BITS == 64
2560 { INDEX_op_qemu_ld_i32, { "r", "L" } },
2561 { INDEX_op_qemu_st_i32, { "S", "S" } },
2562 { INDEX_op_qemu_ld_i64, { "r", "L" } },
2563 { INDEX_op_qemu_st_i64, { "S", "S" } },
2564 #elif TARGET_LONG_BITS == 32
2565 { INDEX_op_qemu_ld_i32, { "r", "L" } },
2566 { INDEX_op_qemu_st_i32, { "S", "S" } },
2567 { INDEX_op_qemu_ld_i64, { "L", "L", "L" } },
2568 { INDEX_op_qemu_st_i64, { "S", "S", "S" } },
2569 #else
2570 { INDEX_op_qemu_ld_i32, { "r", "L", "L" } },
2571 { INDEX_op_qemu_st_i32, { "S", "S", "S" } },
2572 { INDEX_op_qemu_ld_i64, { "L", "L", "L", "L" } },
2573 { INDEX_op_qemu_st_i64, { "S", "S", "S", "S" } },
2574 #endif
2575
2576 { -1 },
2577 };
2578
2579 static void tcg_target_init(TCGContext *s)
2580 {
2581 unsigned long hwcap = qemu_getauxval(AT_HWCAP);
2582 if (hwcap & PPC_FEATURE_ARCH_2_06) {
2583 have_isa_2_06 = true;
2584 }
2585
2586 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
2587 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff);
2588 tcg_regset_set32(tcg_target_call_clobber_regs, 0,
2589 (1 << TCG_REG_R0) |
2590 (1 << TCG_REG_R2) |
2591 (1 << TCG_REG_R3) |
2592 (1 << TCG_REG_R4) |
2593 (1 << TCG_REG_R5) |
2594 (1 << TCG_REG_R6) |
2595 (1 << TCG_REG_R7) |
2596 (1 << TCG_REG_R8) |
2597 (1 << TCG_REG_R9) |
2598 (1 << TCG_REG_R10) |
2599 (1 << TCG_REG_R11) |
2600 (1 << TCG_REG_R12));
2601
2602 tcg_regset_clear(s->reserved_regs);
2603 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* tcg temp */
2604 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); /* stack pointer */
2605 #if defined(_CALL_SYSV)
2606 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2); /* toc pointer */
2607 #endif
2608 #if defined(_CALL_SYSV) || TCG_TARGET_REG_BITS == 64
2609 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */
2610 #endif
2611 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); /* mem temp */
2612 if (USE_REG_RA) {
2613 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return addr */
2614 }
2615
2616 tcg_add_target_add_op_defs(ppc_op_defs);
2617 }
2618
2619 #ifdef __ELF__
2620 typedef struct {
2621 DebugFrameCIE cie;
2622 DebugFrameFDEHeader fde;
2623 uint8_t fde_def_cfa[4];
2624 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2 + 3];
2625 } DebugFrame;
2626
2627 /* We're expecting a 2 byte uleb128 encoded value. */
2628 QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14));
2629
2630 #if TCG_TARGET_REG_BITS == 64
2631 # define ELF_HOST_MACHINE EM_PPC64
2632 #else
2633 # define ELF_HOST_MACHINE EM_PPC
2634 #endif
2635
2636 static DebugFrame debug_frame = {
2637 .cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */
2638 .cie.id = -1,
2639 .cie.version = 1,
2640 .cie.code_align = 1,
2641 .cie.data_align = (-SZR & 0x7f), /* sleb128 -SZR */
2642 .cie.return_column = 65,
2643
2644 /* Total FDE size does not include the "len" member. */
2645 .fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, fde.cie_offset),
2646
2647 .fde_def_cfa = {
2648 12, TCG_REG_R1, /* DW_CFA_def_cfa r1, ... */
2649 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
2650 (FRAME_SIZE >> 7)
2651 },
2652 .fde_reg_ofs = {
2653 /* DW_CFA_offset_extended_sf, lr, LR_OFFSET */
2654 0x11, 65, (LR_OFFSET / -SZR) & 0x7f,
2655 }
2656 };
2657
2658 void tcg_register_jit(void *buf, size_t buf_size)
2659 {
2660 uint8_t *p = &debug_frame.fde_reg_ofs[3];
2661 int i;
2662
2663 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i, p += 2) {
2664 p[0] = 0x80 + tcg_target_callee_save_regs[i];
2665 p[1] = (FRAME_SIZE - (REG_SAVE_BOT + i * SZR)) / SZR;
2666 }
2667
2668 debug_frame.fde.func_start = (uintptr_t)buf;
2669 debug_frame.fde.func_len = buf_size;
2670
2671 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
2672 }
2673 #endif /* __ELF__ */
2674
2675 static size_t dcache_bsize = 16;
2676 static size_t icache_bsize = 16;
2677
2678 void flush_icache_range(uintptr_t start, uintptr_t stop)
2679 {
2680 uintptr_t p, start1, stop1;
2681 size_t dsize = dcache_bsize;
2682 size_t isize = icache_bsize;
2683
2684 start1 = start & ~(dsize - 1);
2685 stop1 = (stop + dsize - 1) & ~(dsize - 1);
2686 for (p = start1; p < stop1; p += dsize) {
2687 asm volatile ("dcbst 0,%0" : : "r"(p) : "memory");
2688 }
2689 asm volatile ("sync" : : : "memory");
2690
2691 start &= start & ~(isize - 1);
2692 stop1 = (stop + isize - 1) & ~(isize - 1);
2693 for (p = start1; p < stop1; p += isize) {
2694 asm volatile ("icbi 0,%0" : : "r"(p) : "memory");
2695 }
2696 asm volatile ("sync" : : : "memory");
2697 asm volatile ("isync" : : : "memory");
2698 }
2699
2700 #if defined _AIX
2701 #include <sys/systemcfg.h>
2702
2703 static void __attribute__((constructor)) tcg_cache_init(void)
2704 {
2705 icache_bsize = _system_configuration.icache_line;
2706 dcache_bsize = _system_configuration.dcache_line;
2707 }
2708
2709 #elif defined __linux__
2710 static void __attribute__((constructor)) tcg_cache_init(void)
2711 {
2712 unsigned long dsize = qemu_getauxval(AT_DCACHEBSIZE);
2713 unsigned long isize = qemu_getauxval(AT_ICACHEBSIZE);
2714
2715 if (dsize == 0 || isize == 0) {
2716 if (dsize == 0) {
2717 fprintf(stderr, "getauxval AT_DCACHEBSIZE failed\n");
2718 }
2719 if (isize == 0) {
2720 fprintf(stderr, "getauxval AT_ICACHEBSIZE failed\n");
2721 }
2722 exit(1);
2723 }
2724 dcache_bsize = dsize;
2725 icache_bsize = isize;
2726 }
2727
2728 #elif defined __APPLE__
2729 #include <sys/sysctl.h>
2730
2731 static void __attribute__((constructor)) tcg_cache_init(void)
2732 {
2733 size_t len;
2734 unsigned cacheline;
2735 int name[2] = { CTL_HW, HW_CACHELINE };
2736
2737 len = sizeof(cacheline);
2738 if (sysctl(name, 2, &cacheline, &len, NULL, 0)) {
2739 perror("sysctl CTL_HW HW_CACHELINE failed");
2740 exit(1);
2741 }
2742 dcache_bsize = cacheline;
2743 icache_bsize = cacheline;
2744 }
2745
2746 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
2747 #include <sys/sysctl.h>
2748
2749 static void __attribute__((constructor)) tcg_cache_init(void)
2750 {
2751 size_t len = 4;
2752 unsigned cacheline;
2753
2754 if (sysctlbyname ("machdep.cacheline_size", &cacheline, &len, NULL, 0)) {
2755 fprintf(stderr, "sysctlbyname machdep.cacheline_size failed: %s\n",
2756 strerror(errno));
2757 exit(1);
2758 }
2759 dcache_bsize = cacheline;
2760 icache_bsize = cacheline;
2761 }
2762 #endif
QEmu