hw/acpi/pcihp.c

   1 /*
   2  * QEMU<->ACPI BIOS PCI hotplug interface
   3  *
   4  * QEMU supports PCI hotplug via ACPI. This module
   5  * implements the interface between QEMU and the ACPI BIOS.
   6  * Interface specification - see docs/specs/acpi_pci_hotplug.txt
   7  *
   8  * Copyright (c) 2013, Red Hat Inc, Michael S. Tsirkin (mst@redhat.com)
   9  * Copyright (c) 2006 Fabrice Bellard
  10  *
  11  * This library is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU Lesser General Public
  13  * License version 2 as published by the Free Software Foundation.
  14  *
  15  * This library is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  18  * Lesser General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU Lesser General Public
  21  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  22  *
  23  * Contributions after 2012-01-13 are licensed under the terms of the
  24  * GNU GPL, version 2 or (at your option) any later version.
  25  */
  26
  27 #include "hw/acpi/pcihp.h"
  28
  29 #include "hw/hw.h"
  30 #include "hw/i386/pc.h"
  31 #include "hw/pci/pci.h"
  32 #include "hw/acpi/acpi.h"
  33 #include "sysemu/sysemu.h"
  34 #include "exec/ioport.h"
  35 #include "exec/address-spaces.h"
  36 #include "hw/pci/pci_bus.h"
  37 #include "qom/qom-qobject.h"
  38 #include "qapi/qmp/qint.h"
  39
  40 //#define DEBUG
  41
  42 #ifdef DEBUG
  43 # define ACPI_PCIHP_DPRINTF(format, ...)     printf(format, ## __VA_ARGS__)
  44 #else
  45 # define ACPI_PCIHP_DPRINTF(format, ...)     do { } while (0)
  46 #endif
  47
  48 #define ACPI_PCIHP_ADDR 0xae00
  49 #define ACPI_PCIHP_SIZE 0x0014
  50 #define ACPI_PCIHP_LEGACY_SIZE 0x000f
  51 #define PCI_UP_BASE 0x0000
  52 #define PCI_DOWN_BASE 0x0004
  53 #define PCI_EJ_BASE 0x0008
  54 #define PCI_RMV_BASE 0x000c
  55 #define PCI_SEL_BASE 0x0010
  56
  57 typedef struct AcpiPciHpFind {
  58     int bsel;
  59     PCIBus *bus;
  60 } AcpiPciHpFind;
  61
  62 static int acpi_pcihp_get_bsel(PCIBus *bus)
  63 {
  64     Error *local_err = NULL;
  65     int64_t bsel = object_property_get_int(OBJECT(bus), ACPI_PCIHP_PROP_BSEL,
  66                                            &local_err);
  67
  68     if (local_err || bsel < 0 || bsel >= ACPI_PCIHP_MAX_HOTPLUG_BUS) {
  69         if (local_err) {
  70             error_free(local_err);
  71         }
  72         return -1;
  73     } else {
  74         return bsel;
  75     }
  76 }
  77
  78 static void acpi_pcihp_test_hotplug_bus(PCIBus *bus, void *opaque)
  79 {
  80     AcpiPciHpFind *find = opaque;
  81     if (find->bsel == acpi_pcihp_get_bsel(bus)) {
  82         find->bus = bus;
  83     }
  84 }
  85
  86 static PCIBus *acpi_pcihp_find_hotplug_bus(AcpiPciHpState *s, int bsel)
  87 {
  88     AcpiPciHpFind find = { .bsel = bsel, .bus = NULL };
  89
  90     if (bsel < 0) {
  91         return NULL;
  92     }
  93
  94     pci_for_each_bus(s->root, acpi_pcihp_test_hotplug_bus, &find);
  95
  96     /* Make bsel 0 eject root bus if bsel property is not set,
  97      * for compatibility with non acpi setups.
  98      * TODO: really needed?
  99      */
 100     if (!bsel && !find.bus) {
 101         find.bus = s->root;
 102     }
 103     return find.bus;
 104 }
 105
 106 static bool acpi_pcihp_pc_no_hotplug(AcpiPciHpState *s, PCIDevice *dev)
 107 {
 108     PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
 109     DeviceClass *dc = DEVICE_GET_CLASS(dev);
 110     /*
 111      * ACPI doesn't allow hotplug of bridge devices.  Don't allow
 112      * hot-unplug of bridge devices unless they were added by hotplug
 113      * (and so, not described by acpi).
 114      */
 115     return (pc->is_bridge && !dev->qdev.hotplugged) || !dc->hotpluggable;
 116 }
 117
 118 static void acpi_pcihp_eject_slot(AcpiPciHpState *s, unsigned bsel, unsigned slots)
 119 {
 120     BusChild *kid, *next;
 121     int slot = ctz32(slots);
 122     PCIBus *bus = acpi_pcihp_find_hotplug_bus(s, bsel);
 123
 124     if (!bus) {
 125         return;
 126     }
 127
 128     /* Mark request as complete */
 129     s->acpi_pcihp_pci_status[bsel].down &= ~(1U << slot);
 130     s->acpi_pcihp_pci_status[bsel].up &= ~(1U << slot);
 131
 132     QTAILQ_FOREACH_SAFE(kid, &bus->qbus.children, sibling, next) {
 133         DeviceState *qdev = kid->child;
 134         PCIDevice *dev = PCI_DEVICE(qdev);
 135         if (PCI_SLOT(dev->devfn) == slot) {
 136             if (!acpi_pcihp_pc_no_hotplug(s, dev)) {
 137                 object_unparent(OBJECT(qdev));
 138             }
 139         }
 140     }
 141 }
 142
 143 static void acpi_pcihp_update_hotplug_bus(AcpiPciHpState *s, int bsel)
 144 {
 145     BusChild *kid, *next;
 146     PCIBus *bus = acpi_pcihp_find_hotplug_bus(s, bsel);
 147
 148     /* Execute any pending removes during reset */
 149     while (s->acpi_pcihp_pci_status[bsel].down) {
 150         acpi_pcihp_eject_slot(s, bsel, s->acpi_pcihp_pci_status[bsel].down);
 151     }
 152
 153     s->acpi_pcihp_pci_status[bsel].hotplug_enable = ~0;
 154
 155     if (!bus) {
 156         return;
 157     }
 158     QTAILQ_FOREACH_SAFE(kid, &bus->qbus.children, sibling, next) {
 159         DeviceState *qdev = kid->child;
 160         PCIDevice *pdev = PCI_DEVICE(qdev);
 161         int slot = PCI_SLOT(pdev->devfn);
 162
 163         if (acpi_pcihp_pc_no_hotplug(s, pdev)) {
 164             s->acpi_pcihp_pci_status[bsel].hotplug_enable &= ~(1U << slot);
 165         }
 166     }
 167 }
 168
 169 static void acpi_pcihp_update(AcpiPciHpState *s)
 170 {
 171     int i;
 172
 173     for (i = 0; i < ACPI_PCIHP_MAX_HOTPLUG_BUS; ++i) {
 174         acpi_pcihp_update_hotplug_bus(s, i);
 175     }
 176 }
 177
 178 void acpi_pcihp_reset(AcpiPciHpState *s)
 179 {
 180     acpi_pcihp_update(s);
 181 }
 182
 183 void acpi_pcihp_device_plug_cb(ACPIREGS *ar, qemu_irq irq, AcpiPciHpState *s,
 184                                DeviceState *dev, Error **errp)
 185 {
 186     PCIDevice *pdev = PCI_DEVICE(dev);
 187     int slot = PCI_SLOT(pdev->devfn);
 188     int bsel = acpi_pcihp_get_bsel(pdev->bus);
 189     if (bsel < 0) {
 190         error_setg(errp, "Unsupported bus. Bus doesn't have property '"
 191                    ACPI_PCIHP_PROP_BSEL "' set");
 192         return;
 193     }
 194
 195     /* Don't send event when device is enabled during qemu machine creation:
 196      * it is present on boot, no hotplug event is necessary. We do send an
 197      * event when the device is disabled later. */
 198     if (!dev->hotplugged) {
 199         return;
 200     }
 201
 202     s->acpi_pcihp_pci_status[bsel].up |= (1U << slot);
 203
 204     acpi_send_gpe_event(ar, irq, ACPI_PCI_HOTPLUG_STATUS);
 205 }
 206
 207 void acpi_pcihp_device_unplug_cb(ACPIREGS *ar, qemu_irq irq, AcpiPciHpState *s,
 208                                  DeviceState *dev, Error **errp)
 209 {
 210     PCIDevice *pdev = PCI_DEVICE(dev);
 211     int slot = PCI_SLOT(pdev->devfn);
 212     int bsel = acpi_pcihp_get_bsel(pdev->bus);
 213     if (bsel < 0) {
 214         error_setg(errp, "Unsupported bus. Bus doesn't have property '"
 215                    ACPI_PCIHP_PROP_BSEL "' set");
 216         return;
 217     }
 218
 219     s->acpi_pcihp_pci_status[bsel].down |= (1U << slot);
 220
 221     acpi_send_gpe_event(ar, irq, ACPI_PCI_HOTPLUG_STATUS);
 222 }
 223
 224 static uint64_t pci_read(void *opaque, hwaddr addr, unsigned int size)
 225 {
 226     AcpiPciHpState *s = opaque;
 227     uint32_t val = 0;
 228     int bsel = s->hotplug_select;
 229
 230     if (bsel < 0 || bsel >= ACPI_PCIHP_MAX_HOTPLUG_BUS) {
 231         return 0;
 232     }
 233
 234     switch (addr) {
 235     case PCI_UP_BASE:
 236         val = s->acpi_pcihp_pci_status[bsel].up;
 237         if (!s->legacy_piix) {
 238             s->acpi_pcihp_pci_status[bsel].up = 0;
 239         }
 240         ACPI_PCIHP_DPRINTF("pci_up_read %" PRIu32 "\n", val);
 241         break;
 242     case PCI_DOWN_BASE:
 243         val = s->acpi_pcihp_pci_status[bsel].down;
 244         ACPI_PCIHP_DPRINTF("pci_down_read %" PRIu32 "\n", val);
 245         break;
 246     case PCI_EJ_BASE:
 247         /* No feature defined yet */
 248         ACPI_PCIHP_DPRINTF("pci_features_read %" PRIu32 "\n", val);
 249         break;
 250     case PCI_RMV_BASE:
 251         val = s->acpi_pcihp_pci_status[bsel].hotplug_enable;
 252         ACPI_PCIHP_DPRINTF("pci_rmv_read %" PRIu32 "\n", val);
 253         break;
 254     case PCI_SEL_BASE:
 255         val = s->hotplug_select;
 256         ACPI_PCIHP_DPRINTF("pci_sel_read %" PRIu32 "\n", val);
 257     default:
 258         break;
 259     }
 260
 261     return val;
 262 }
 263
 264 static void pci_write(void *opaque, hwaddr addr, uint64_t data,
 265                       unsigned int size)
 266 {
 267     AcpiPciHpState *s = opaque;
 268     switch (addr) {
 269     case PCI_EJ_BASE:
 270         if (s->hotplug_select >= ACPI_PCIHP_MAX_HOTPLUG_BUS) {
 271             break;
 272         }
 273         acpi_pcihp_eject_slot(s, s->hotplug_select, data);
 274         ACPI_PCIHP_DPRINTF("pciej write %" HWADDR_PRIx " <== %" PRIu64 "\n",
 275                       addr, data);
 276         break;
 277     case PCI_SEL_BASE:
 278         s->hotplug_select = data;
 279         ACPI_PCIHP_DPRINTF("pcisel write %" HWADDR_PRIx " <== %" PRIu64 "\n",
 280                       addr, data);
 281     default:
 282         break;
 283     }
 284 }
 285
 286 static const MemoryRegionOps acpi_pcihp_io_ops = {
 287     .read = pci_read,
 288     .write = pci_write,
 289     .endianness = DEVICE_LITTLE_ENDIAN,
 290     .valid = {
 291         .min_access_size = 4,
 292         .max_access_size = 4,
 293     },
 294 };
 295
 296 void acpi_pcihp_init(Object *owner, AcpiPciHpState *s, PCIBus *root_bus,
 297                      MemoryRegion *address_space_io, bool bridges_enabled)
 298 {
 299     s->io_len = ACPI_PCIHP_SIZE;
 300     s->io_base = ACPI_PCIHP_ADDR;
 301
 302     s->root= root_bus;
 303     s->legacy_piix = !bridges_enabled;
 304
 305     if (s->legacy_piix) {
 306         unsigned *bus_bsel = g_malloc(sizeof *bus_bsel);
 307
 308         s->io_len = ACPI_PCIHP_LEGACY_SIZE;
 309
 310         *bus_bsel = ACPI_PCIHP_BSEL_DEFAULT;
 311         object_property_add_uint32_ptr(OBJECT(root_bus), ACPI_PCIHP_PROP_BSEL,
 312                                        bus_bsel, NULL);
 313     }
 314
 315     memory_region_init_io(&s->io, owner, &acpi_pcihp_io_ops, s,
 316                           "acpi-pci-hotplug", s->io_len);
 317     memory_region_add_subregion(address_space_io, s->io_base, &s->io);
 318
 319     object_property_add_uint16_ptr(owner, ACPI_PCIHP_IO_BASE_PROP, &s->io_base,
 320                                    &error_abort);
 321     object_property_add_uint16_ptr(owner, ACPI_PCIHP_IO_LEN_PROP, &s->io_len,
 322                                    &error_abort);
 323 }
 324
 325 const VMStateDescription vmstate_acpi_pcihp_pci_status = {
 326     .name = "acpi_pcihp_pci_status",
 327     .version_id = 1,
 328     .minimum_version_id = 1,
 329     .fields = (VMStateField[]) {
 330         VMSTATE_UINT32(up, AcpiPciHpPciStatus),
 331         VMSTATE_UINT32(down, AcpiPciHpPciStatus),
 332         VMSTATE_END_OF_LIST()
 333     }
 334 };