iotests: 028: Use TEST_IMG override instead of "mv"
[qemu.git] / hw / acpi / nvdimm.c
blob9534418824d2e0cbbf0573f1f8663e5b9a169f91
1 /*
2 * NVDIMM ACPI Implementation
4 * Copyright(C) 2015 Intel Corporation.
6 * Author:
7 * Xiao Guangrong <guangrong.xiao@linux.intel.com>
9 * NFIT is defined in ACPI 6.0: 5.2.25 NVDIMM Firmware Interface Table (NFIT)
10 * and the DSM specification can be found at:
11 * http://pmem.io/documents/NVDIMM_DSM_Interface_Example.pdf
13 * Currently, it only supports PMEM Virtualization.
15 * This library is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU Lesser General Public
17 * License as published by the Free Software Foundation; either
18 * version 2 of the License, or (at your option) any later version.
20 * This library is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
23 * Lesser General Public License for more details.
25 * You should have received a copy of the GNU Lesser General Public
26 * License along with this library; if not, see <http://www.gnu.org/licenses/>
29 #include "hw/acpi/acpi.h"
30 #include "hw/acpi/aml-build.h"
31 #include "hw/mem/nvdimm.h"
33 static int nvdimm_plugged_device_list(Object *obj, void *opaque)
35 GSList **list = opaque;
37 if (object_dynamic_cast(obj, TYPE_NVDIMM)) {
38 DeviceState *dev = DEVICE(obj);
40 if (dev->realized) { /* only realized NVDIMMs matter */
41 *list = g_slist_append(*list, DEVICE(obj));
45 object_child_foreach(obj, nvdimm_plugged_device_list, opaque);
46 return 0;
50 * inquire plugged NVDIMM devices and link them into the list which is
51 * returned to the caller.
53 * Note: it is the caller's responsibility to free the list to avoid
54 * memory leak.
56 static GSList *nvdimm_get_plugged_device_list(void)
58 GSList *list = NULL;
60 object_child_foreach(qdev_get_machine(), nvdimm_plugged_device_list,
61 &list);
62 return list;
65 #define NVDIMM_UUID_LE(a, b, c, d0, d1, d2, d3, d4, d5, d6, d7) \
66 { (a) & 0xff, ((a) >> 8) & 0xff, ((a) >> 16) & 0xff, ((a) >> 24) & 0xff, \
67 (b) & 0xff, ((b) >> 8) & 0xff, (c) & 0xff, ((c) >> 8) & 0xff, \
68 (d0), (d1), (d2), (d3), (d4), (d5), (d6), (d7) }
71 * define Byte Addressable Persistent Memory (PM) Region according to
72 * ACPI 6.0: 5.2.25.1 System Physical Address Range Structure.
74 static const uint8_t nvdimm_nfit_spa_uuid[] =
75 NVDIMM_UUID_LE(0x66f0d379, 0xb4f3, 0x4074, 0xac, 0x43, 0x0d, 0x33,
76 0x18, 0xb7, 0x8c, 0xdb);
79 * NVDIMM Firmware Interface Table
80 * @signature: "NFIT"
82 * It provides information that allows OSPM to enumerate NVDIMM present in
83 * the platform and associate system physical address ranges created by the
84 * NVDIMMs.
86 * It is defined in ACPI 6.0: 5.2.25 NVDIMM Firmware Interface Table (NFIT)
88 struct NvdimmNfitHeader {
89 ACPI_TABLE_HEADER_DEF
90 uint32_t reserved;
91 } QEMU_PACKED;
92 typedef struct NvdimmNfitHeader NvdimmNfitHeader;
95 * define NFIT structures according to ACPI 6.0: 5.2.25 NVDIMM Firmware
96 * Interface Table (NFIT).
100 * System Physical Address Range Structure
102 * It describes the system physical address ranges occupied by NVDIMMs and
103 * the types of the regions.
105 struct NvdimmNfitSpa {
106 uint16_t type;
107 uint16_t length;
108 uint16_t spa_index;
109 uint16_t flags;
110 uint32_t reserved;
111 uint32_t proximity_domain;
112 uint8_t type_guid[16];
113 uint64_t spa_base;
114 uint64_t spa_length;
115 uint64_t mem_attr;
116 } QEMU_PACKED;
117 typedef struct NvdimmNfitSpa NvdimmNfitSpa;
120 * Memory Device to System Physical Address Range Mapping Structure
122 * It enables identifying each NVDIMM region and the corresponding SPA
123 * describing the memory interleave
125 struct NvdimmNfitMemDev {
126 uint16_t type;
127 uint16_t length;
128 uint32_t nfit_handle;
129 uint16_t phys_id;
130 uint16_t region_id;
131 uint16_t spa_index;
132 uint16_t dcr_index;
133 uint64_t region_len;
134 uint64_t region_offset;
135 uint64_t region_dpa;
136 uint16_t interleave_index;
137 uint16_t interleave_ways;
138 uint16_t flags;
139 uint16_t reserved;
140 } QEMU_PACKED;
141 typedef struct NvdimmNfitMemDev NvdimmNfitMemDev;
144 * NVDIMM Control Region Structure
146 * It describes the NVDIMM and if applicable, Block Control Window.
148 struct NvdimmNfitControlRegion {
149 uint16_t type;
150 uint16_t length;
151 uint16_t dcr_index;
152 uint16_t vendor_id;
153 uint16_t device_id;
154 uint16_t revision_id;
155 uint16_t sub_vendor_id;
156 uint16_t sub_device_id;
157 uint16_t sub_revision_id;
158 uint8_t reserved[6];
159 uint32_t serial_number;
160 uint16_t fic;
161 uint16_t num_bcw;
162 uint64_t bcw_size;
163 uint64_t cmd_offset;
164 uint64_t cmd_size;
165 uint64_t status_offset;
166 uint64_t status_size;
167 uint16_t flags;
168 uint8_t reserved2[6];
169 } QEMU_PACKED;
170 typedef struct NvdimmNfitControlRegion NvdimmNfitControlRegion;
173 * Module serial number is a unique number for each device. We use the
174 * slot id of NVDIMM device to generate this number so that each device
175 * associates with a different number.
177 * 0x123456 is a magic number we arbitrarily chose.
179 static uint32_t nvdimm_slot_to_sn(int slot)
181 return 0x123456 + slot;
185 * handle is used to uniquely associate nfit_memdev structure with NVDIMM
186 * ACPI device - nfit_memdev.nfit_handle matches with the value returned
187 * by ACPI device _ADR method.
189 * We generate the handle with the slot id of NVDIMM device and reserve
190 * 0 for NVDIMM root device.
192 static uint32_t nvdimm_slot_to_handle(int slot)
194 return slot + 1;
198 * index uniquely identifies the structure, 0 is reserved which indicates
199 * that the structure is not valid or the associated structure is not
200 * present.
202 * Each NVDIMM device needs two indexes, one for nfit_spa and another for
203 * nfit_dc which are generated by the slot id of NVDIMM device.
205 static uint16_t nvdimm_slot_to_spa_index(int slot)
207 return (slot + 1) << 1;
210 /* See the comments of nvdimm_slot_to_spa_index(). */
211 static uint32_t nvdimm_slot_to_dcr_index(int slot)
213 return nvdimm_slot_to_spa_index(slot) + 1;
216 /* ACPI 6.0: 5.2.25.1 System Physical Address Range Structure */
217 static void
218 nvdimm_build_structure_spa(GArray *structures, DeviceState *dev)
220 NvdimmNfitSpa *nfit_spa;
221 uint64_t addr = object_property_get_int(OBJECT(dev), PC_DIMM_ADDR_PROP,
222 NULL);
223 uint64_t size = object_property_get_int(OBJECT(dev), PC_DIMM_SIZE_PROP,
224 NULL);
225 uint32_t node = object_property_get_int(OBJECT(dev), PC_DIMM_NODE_PROP,
226 NULL);
227 int slot = object_property_get_int(OBJECT(dev), PC_DIMM_SLOT_PROP,
228 NULL);
230 nfit_spa = acpi_data_push(structures, sizeof(*nfit_spa));
232 nfit_spa->type = cpu_to_le16(0 /* System Physical Address Range
233 Structure */);
234 nfit_spa->length = cpu_to_le16(sizeof(*nfit_spa));
235 nfit_spa->spa_index = cpu_to_le16(nvdimm_slot_to_spa_index(slot));
238 * Control region is strict as all the device info, such as SN, index,
239 * is associated with slot id.
241 nfit_spa->flags = cpu_to_le16(1 /* Control region is strictly for
242 management during hot add/online
243 operation */ |
244 2 /* Data in Proximity Domain field is
245 valid*/);
247 /* NUMA node. */
248 nfit_spa->proximity_domain = cpu_to_le32(node);
249 /* the region reported as PMEM. */
250 memcpy(nfit_spa->type_guid, nvdimm_nfit_spa_uuid,
251 sizeof(nvdimm_nfit_spa_uuid));
253 nfit_spa->spa_base = cpu_to_le64(addr);
254 nfit_spa->spa_length = cpu_to_le64(size);
256 /* It is the PMEM and can be cached as writeback. */
257 nfit_spa->mem_attr = cpu_to_le64(0x8ULL /* EFI_MEMORY_WB */ |
258 0x8000ULL /* EFI_MEMORY_NV */);
262 * ACPI 6.0: 5.2.25.2 Memory Device to System Physical Address Range Mapping
263 * Structure
265 static void
266 nvdimm_build_structure_memdev(GArray *structures, DeviceState *dev)
268 NvdimmNfitMemDev *nfit_memdev;
269 uint64_t addr = object_property_get_int(OBJECT(dev), PC_DIMM_ADDR_PROP,
270 NULL);
271 uint64_t size = object_property_get_int(OBJECT(dev), PC_DIMM_SIZE_PROP,
272 NULL);
273 int slot = object_property_get_int(OBJECT(dev), PC_DIMM_SLOT_PROP,
274 NULL);
275 uint32_t handle = nvdimm_slot_to_handle(slot);
277 nfit_memdev = acpi_data_push(structures, sizeof(*nfit_memdev));
279 nfit_memdev->type = cpu_to_le16(1 /* Memory Device to System Address
280 Range Map Structure*/);
281 nfit_memdev->length = cpu_to_le16(sizeof(*nfit_memdev));
282 nfit_memdev->nfit_handle = cpu_to_le32(handle);
285 * associate memory device with System Physical Address Range
286 * Structure.
288 nfit_memdev->spa_index = cpu_to_le16(nvdimm_slot_to_spa_index(slot));
289 /* associate memory device with Control Region Structure. */
290 nfit_memdev->dcr_index = cpu_to_le16(nvdimm_slot_to_dcr_index(slot));
292 /* The memory region on the device. */
293 nfit_memdev->region_len = cpu_to_le64(size);
294 nfit_memdev->region_dpa = cpu_to_le64(addr);
296 /* Only one interleave for PMEM. */
297 nfit_memdev->interleave_ways = cpu_to_le16(1);
301 * ACPI 6.0: 5.2.25.5 NVDIMM Control Region Structure.
303 static void nvdimm_build_structure_dcr(GArray *structures, DeviceState *dev)
305 NvdimmNfitControlRegion *nfit_dcr;
306 int slot = object_property_get_int(OBJECT(dev), PC_DIMM_SLOT_PROP,
307 NULL);
308 uint32_t sn = nvdimm_slot_to_sn(slot);
310 nfit_dcr = acpi_data_push(structures, sizeof(*nfit_dcr));
312 nfit_dcr->type = cpu_to_le16(4 /* NVDIMM Control Region Structure */);
313 nfit_dcr->length = cpu_to_le16(sizeof(*nfit_dcr));
314 nfit_dcr->dcr_index = cpu_to_le16(nvdimm_slot_to_dcr_index(slot));
316 /* vendor: Intel. */
317 nfit_dcr->vendor_id = cpu_to_le16(0x8086);
318 nfit_dcr->device_id = cpu_to_le16(1);
320 /* The _DSM method is following Intel's DSM specification. */
321 nfit_dcr->revision_id = cpu_to_le16(1 /* Current Revision supported
322 in ACPI 6.0 is 1. */);
323 nfit_dcr->serial_number = cpu_to_le32(sn);
324 nfit_dcr->fic = cpu_to_le16(0x201 /* Format Interface Code. See Chapter
325 2: NVDIMM Device Specific Method
326 (DSM) in DSM Spec Rev1.*/);
329 static GArray *nvdimm_build_device_structure(GSList *device_list)
331 GArray *structures = g_array_new(false, true /* clear */, 1);
333 for (; device_list; device_list = device_list->next) {
334 DeviceState *dev = device_list->data;
336 /* build System Physical Address Range Structure. */
337 nvdimm_build_structure_spa(structures, dev);
340 * build Memory Device to System Physical Address Range Mapping
341 * Structure.
343 nvdimm_build_structure_memdev(structures, dev);
345 /* build NVDIMM Control Region Structure. */
346 nvdimm_build_structure_dcr(structures, dev);
349 return structures;
352 static void nvdimm_build_nfit(GSList *device_list, GArray *table_offsets,
353 GArray *table_data, GArray *linker)
355 GArray *structures = nvdimm_build_device_structure(device_list);
356 void *header;
358 acpi_add_table(table_offsets, table_data);
360 /* NFIT header. */
361 header = acpi_data_push(table_data, sizeof(NvdimmNfitHeader));
362 /* NVDIMM device structures. */
363 g_array_append_vals(table_data, structures->data, structures->len);
365 build_header(linker, table_data, header, "NFIT",
366 sizeof(NvdimmNfitHeader) + structures->len, 1, NULL);
367 g_array_free(structures, true);
370 #define NVDIMM_COMMON_DSM "NCAL"
372 static void nvdimm_build_common_dsm(Aml *dev)
374 Aml *method, *ifctx, *function;
375 uint8_t byte_list[1];
377 method = aml_method(NVDIMM_COMMON_DSM, 4, AML_NOTSERIALIZED);
378 function = aml_arg(2);
381 * function 0 is called to inquire what functions are supported by
382 * OSPM
384 ifctx = aml_if(aml_equal(function, aml_int(0)));
385 byte_list[0] = 0 /* No function Supported */;
386 aml_append(ifctx, aml_return(aml_buffer(1, byte_list)));
387 aml_append(method, ifctx);
389 /* No function is supported yet. */
390 byte_list[0] = 1 /* Not Supported */;
391 aml_append(method, aml_return(aml_buffer(1, byte_list)));
393 aml_append(dev, method);
396 static void nvdimm_build_device_dsm(Aml *dev)
398 Aml *method;
400 method = aml_method("_DSM", 4, AML_NOTSERIALIZED);
401 aml_append(method, aml_return(aml_call4(NVDIMM_COMMON_DSM, aml_arg(0),
402 aml_arg(1), aml_arg(2), aml_arg(3))));
403 aml_append(dev, method);
406 static void nvdimm_build_nvdimm_devices(GSList *device_list, Aml *root_dev)
408 for (; device_list; device_list = device_list->next) {
409 DeviceState *dev = device_list->data;
410 int slot = object_property_get_int(OBJECT(dev), PC_DIMM_SLOT_PROP,
411 NULL);
412 uint32_t handle = nvdimm_slot_to_handle(slot);
413 Aml *nvdimm_dev;
415 nvdimm_dev = aml_device("NV%02X", slot);
418 * ACPI 6.0: 9.20 NVDIMM Devices:
420 * _ADR object that is used to supply OSPM with unique address
421 * of the NVDIMM device. This is done by returning the NFIT Device
422 * handle that is used to identify the associated entries in ACPI
423 * table NFIT or _FIT.
425 aml_append(nvdimm_dev, aml_name_decl("_ADR", aml_int(handle)));
427 nvdimm_build_device_dsm(nvdimm_dev);
428 aml_append(root_dev, nvdimm_dev);
432 static void nvdimm_build_ssdt(GSList *device_list, GArray *table_offsets,
433 GArray *table_data, GArray *linker)
435 Aml *ssdt, *sb_scope, *dev;
437 acpi_add_table(table_offsets, table_data);
439 ssdt = init_aml_allocator();
440 acpi_data_push(ssdt->buf, sizeof(AcpiTableHeader));
442 sb_scope = aml_scope("\\_SB");
444 dev = aml_device("NVDR");
447 * ACPI 6.0: 9.20 NVDIMM Devices:
449 * The ACPI Name Space device uses _HID of ACPI0012 to identify the root
450 * NVDIMM interface device. Platform firmware is required to contain one
451 * such device in _SB scope if NVDIMMs support is exposed by platform to
452 * OSPM.
453 * For each NVDIMM present or intended to be supported by platform,
454 * platform firmware also exposes an ACPI Namespace Device under the
455 * root device.
457 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0012")));
459 nvdimm_build_common_dsm(dev);
460 nvdimm_build_device_dsm(dev);
462 nvdimm_build_nvdimm_devices(device_list, dev);
464 aml_append(sb_scope, dev);
466 aml_append(ssdt, sb_scope);
467 /* copy AML table into ACPI tables blob and patch header there */
468 g_array_append_vals(table_data, ssdt->buf->data, ssdt->buf->len);
469 build_header(linker, table_data,
470 (void *)(table_data->data + table_data->len - ssdt->buf->len),
471 "SSDT", ssdt->buf->len, 1, "NVDIMM");
472 free_aml_allocator();
475 void nvdimm_build_acpi(GArray *table_offsets, GArray *table_data,
476 GArray *linker)
478 GSList *device_list;
480 /* no NVDIMM device is plugged. */
481 device_list = nvdimm_get_plugged_device_list();
482 if (!device_list) {
483 return;
485 nvdimm_build_nfit(device_list, table_offsets, table_data, linker);
486 nvdimm_build_ssdt(device_list, table_offsets, table_data, linker);
487 g_slist_free(device_list);