2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2009-2010 Aurelien Jarno <aurelien@aurel32.net>
5 * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #ifndef TCG_TARGET_IA64
26 #define TCG_TARGET_IA64 1
28 /* We only map the first 64 registers */
29 #define TCG_TARGET_NB_REGS 64
96 TCG_AREG0
= TCG_REG_R32
,
99 #define TCG_CT_CONST_ZERO 0x100
100 #define TCG_CT_CONST_S22 0x200
102 /* used for function call generation */
103 #define TCG_REG_CALL_STACK TCG_REG_R12
104 #define TCG_TARGET_STACK_ALIGN 16
105 #define TCG_TARGET_CALL_STACK_OFFSET 16
107 /* optional instructions */
108 #define TCG_TARGET_HAS_div_i32 0
109 #define TCG_TARGET_HAS_rem_i32 0
110 #define TCG_TARGET_HAS_div_i64 0
111 #define TCG_TARGET_HAS_rem_i64 0
112 #define TCG_TARGET_HAS_andc_i32 1
113 #define TCG_TARGET_HAS_andc_i64 1
114 #define TCG_TARGET_HAS_bswap16_i32 1
115 #define TCG_TARGET_HAS_bswap16_i64 1
116 #define TCG_TARGET_HAS_bswap32_i32 1
117 #define TCG_TARGET_HAS_bswap32_i64 1
118 #define TCG_TARGET_HAS_bswap64_i64 1
119 #define TCG_TARGET_HAS_eqv_i32 1
120 #define TCG_TARGET_HAS_eqv_i64 1
121 #define TCG_TARGET_HAS_ext8s_i32 1
122 #define TCG_TARGET_HAS_ext16s_i32 1
123 #define TCG_TARGET_HAS_ext8s_i64 1
124 #define TCG_TARGET_HAS_ext16s_i64 1
125 #define TCG_TARGET_HAS_ext32s_i64 1
126 #define TCG_TARGET_HAS_ext8u_i32 1
127 #define TCG_TARGET_HAS_ext16u_i32 1
128 #define TCG_TARGET_HAS_ext8u_i64 1
129 #define TCG_TARGET_HAS_ext16u_i64 1
130 #define TCG_TARGET_HAS_ext32u_i64 1
131 #define TCG_TARGET_HAS_nand_i32 1
132 #define TCG_TARGET_HAS_nand_i64 1
133 #define TCG_TARGET_HAS_nor_i32 1
134 #define TCG_TARGET_HAS_nor_i64 1
135 #define TCG_TARGET_HAS_orc_i32 1
136 #define TCG_TARGET_HAS_orc_i64 1
137 #define TCG_TARGET_HAS_rot_i32 1
138 #define TCG_TARGET_HAS_rot_i64 1
139 #define TCG_TARGET_HAS_movcond_i32 1
140 #define TCG_TARGET_HAS_movcond_i64 1
141 #define TCG_TARGET_HAS_deposit_i32 1
142 #define TCG_TARGET_HAS_deposit_i64 1
143 #define TCG_TARGET_HAS_add2_i32 0
144 #define TCG_TARGET_HAS_add2_i64 0
145 #define TCG_TARGET_HAS_sub2_i32 0
146 #define TCG_TARGET_HAS_sub2_i64 0
147 #define TCG_TARGET_HAS_mulu2_i32 0
148 #define TCG_TARGET_HAS_mulu2_i64 0
149 #define TCG_TARGET_HAS_muls2_i32 0
150 #define TCG_TARGET_HAS_muls2_i64 0
151 #define TCG_TARGET_HAS_muluh_i32 0
152 #define TCG_TARGET_HAS_muluh_i64 0
153 #define TCG_TARGET_HAS_mulsh_i32 0
154 #define TCG_TARGET_HAS_mulsh_i64 0
156 #define TCG_TARGET_HAS_new_ldst 0
158 #define TCG_TARGET_deposit_i32_valid(ofs, len) ((len) <= 16)
159 #define TCG_TARGET_deposit_i64_valid(ofs, len) ((len) <= 16)
161 /* optional instructions automatically implemented */
162 #define TCG_TARGET_HAS_neg_i32 0 /* sub r1, r0, r3 */
163 #define TCG_TARGET_HAS_neg_i64 0 /* sub r1, r0, r3 */
164 #define TCG_TARGET_HAS_not_i32 0 /* xor r1, -1, r3 */
165 #define TCG_TARGET_HAS_not_i64 0 /* xor r1, -1, r3 */
167 static inline void flush_icache_range(uintptr_t start
, uintptr_t stop
)
169 start
= start
& ~(32UL - 1UL);
170 stop
= (stop
+ (32UL - 1UL)) & ~(32UL - 1UL);
172 for (; start
< stop
; start
+= 32UL) {
173 asm volatile ("fc.i %0" :: "r" (start
));
175 asm volatile (";;sync.i;;srlz.i;;");