hw/ppc/spapr_cpu_core.c

   1 /*
   2  * sPAPR CPU core device, acts as container of CPU thread devices.
   3  *
   4  * Copyright (C) 2016 Bharata B Rao <bharata@linux.vnet.ibm.com>
   5  *
   6  * This work is licensed under the terms of the GNU GPL, version 2 or later.
   7  * See the COPYING file in the top-level directory.
   8  */
   9
  10 #include "qemu/osdep.h"
  11 #include "hw/cpu/core.h"
  12 #include "hw/ppc/spapr_cpu_core.h"
  13 #include "hw/qdev-properties.h"
  14 #include "migration/vmstate.h"
  15 #include "target/ppc/cpu.h"
  16 #include "hw/ppc/spapr.h"
  17 #include "qapi/error.h"
  18 #include "sysemu/cpus.h"
  19 #include "sysemu/kvm.h"
  20 #include "target/ppc/kvm_ppc.h"
  21 #include "hw/ppc/ppc.h"
  22 #include "target/ppc/mmu-hash64.h"
  23 #include "target/ppc/power8-pmu.h"
  24 #include "sysemu/numa.h"
  25 #include "sysemu/reset.h"
  26 #include "sysemu/hw_accel.h"
  27 #include "qemu/error-report.h"
  28
  29 static void spapr_reset_vcpu(PowerPCCPU *cpu)
  30 {
  31     CPUState *cs = CPU(cpu);
  32     CPUPPCState *env = &cpu->env;
  33     PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
  34     SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
  35     target_ulong lpcr;
  36     SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
  37
  38     cpu_reset(cs);
  39
  40     /*
  41      * "PowerPC Processor binding to IEEE 1275" defines the initial MSR state
  42      * as 32bit (MSR_SF=0) in "8.2.1. Initial Register Values".
  43      */
  44     env->msr &= ~(1ULL << MSR_SF);
  45     env->spr[SPR_HIOR] = 0;
  46
  47     lpcr = env->spr[SPR_LPCR];
  48
  49     /* Set emulated LPCR to not send interrupts to hypervisor. Note that
  50      * under KVM, the actual HW LPCR will be set differently by KVM itself,
  51      * the settings below ensure proper operations with TCG in absence of
  52      * a real hypervisor.
  53      *
  54      * Disable Power-saving mode Exit Cause exceptions for the CPU, so
  55      * we don't get spurious wakups before an RTAS start-cpu call.
  56      * For the same reason, set PSSCR_EC.
  57      */
  58     lpcr &= ~(LPCR_VPM1 | LPCR_ISL | LPCR_KBV | pcc->lpcr_pm);
  59     lpcr |= LPCR_LPES0 | LPCR_LPES1;
  60     env->spr[SPR_PSSCR] |= PSSCR_EC;
  61
  62     ppc_store_lpcr(cpu, lpcr);
  63
  64     /* Set a full AMOR so guest can use the AMR as it sees fit */
  65     env->spr[SPR_AMOR] = 0xffffffffffffffffull;
  66
  67     spapr_cpu->vpa_addr = 0;
  68     spapr_cpu->slb_shadow_addr = 0;
  69     spapr_cpu->slb_shadow_size = 0;
  70     spapr_cpu->dtl_addr = 0;
  71     spapr_cpu->dtl_size = 0;
  72
  73     spapr_caps_cpu_apply(spapr, cpu);
  74
  75     kvm_check_mmu(cpu, &error_fatal);
  76
  77     spapr_irq_cpu_intc_reset(spapr, cpu);
  78 }
  79
  80 void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip,
  81                                target_ulong r1, target_ulong r3,
  82                                target_ulong r4)
  83 {
  84     PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
  85     CPUPPCState *env = &cpu->env;
  86
  87     env->nip = nip;
  88     env->gpr[1] = r1;
  89     env->gpr[3] = r3;
  90     env->gpr[4] = r4;
  91     kvmppc_set_reg_ppc_online(cpu, 1);
  92     CPU(cpu)->halted = 0;
  93     /* Enable Power-saving mode Exit Cause exceptions */
  94     ppc_store_lpcr(cpu, env->spr[SPR_LPCR] | pcc->lpcr_pm);
  95 }
  96
  97 /*
  98  * Return the sPAPR CPU core type for @model which essentially is the CPU
  99  * model specified with -cpu cmdline option.
 100  */
 101 const char *spapr_get_cpu_core_type(const char *cpu_type)
 102 {
 103     int len = strlen(cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX);
 104     char *core_type = g_strdup_printf(SPAPR_CPU_CORE_TYPE_NAME("%.*s"),
 105                                       len, cpu_type);
 106     ObjectClass *oc = object_class_by_name(core_type);
 107
 108     g_free(core_type);
 109     if (!oc) {
 110         return NULL;
 111     }
 112
 113     return object_class_get_name(oc);
 114 }
 115
 116 static bool slb_shadow_needed(void *opaque)
 117 {
 118     SpaprCpuState *spapr_cpu = opaque;
 119
 120     return spapr_cpu->slb_shadow_addr != 0;
 121 }
 122
 123 static const VMStateDescription vmstate_spapr_cpu_slb_shadow = {
 124     .name = "spapr_cpu/vpa/slb_shadow",
 125     .version_id = 1,
 126     .minimum_version_id = 1,
 127     .needed = slb_shadow_needed,
 128     .fields = (VMStateField[]) {
 129         VMSTATE_UINT64(slb_shadow_addr, SpaprCpuState),
 130         VMSTATE_UINT64(slb_shadow_size, SpaprCpuState),
 131         VMSTATE_END_OF_LIST()
 132     }
 133 };
 134
 135 static bool dtl_needed(void *opaque)
 136 {
 137     SpaprCpuState *spapr_cpu = opaque;
 138
 139     return spapr_cpu->dtl_addr != 0;
 140 }
 141
 142 static const VMStateDescription vmstate_spapr_cpu_dtl = {
 143     .name = "spapr_cpu/vpa/dtl",
 144     .version_id = 1,
 145     .minimum_version_id = 1,
 146     .needed = dtl_needed,
 147     .fields = (VMStateField[]) {
 148         VMSTATE_UINT64(dtl_addr, SpaprCpuState),
 149         VMSTATE_UINT64(dtl_size, SpaprCpuState),
 150         VMSTATE_END_OF_LIST()
 151     }
 152 };
 153
 154 static bool vpa_needed(void *opaque)
 155 {
 156     SpaprCpuState *spapr_cpu = opaque;
 157
 158     return spapr_cpu->vpa_addr != 0;
 159 }
 160
 161 static const VMStateDescription vmstate_spapr_cpu_vpa = {
 162     .name = "spapr_cpu/vpa",
 163     .version_id = 1,
 164     .minimum_version_id = 1,
 165     .needed = vpa_needed,
 166     .fields = (VMStateField[]) {
 167         VMSTATE_UINT64(vpa_addr, SpaprCpuState),
 168         VMSTATE_END_OF_LIST()
 169     },
 170     .subsections = (const VMStateDescription * []) {
 171         &vmstate_spapr_cpu_slb_shadow,
 172         &vmstate_spapr_cpu_dtl,
 173         NULL
 174     }
 175 };
 176
 177 static const VMStateDescription vmstate_spapr_cpu_state = {
 178     .name = "spapr_cpu",
 179     .version_id = 1,
 180     .minimum_version_id = 1,
 181     .fields = (VMStateField[]) {
 182         VMSTATE_END_OF_LIST()
 183     },
 184     .subsections = (const VMStateDescription * []) {
 185         &vmstate_spapr_cpu_vpa,
 186         NULL
 187     }
 188 };
 189
 190 static void spapr_unrealize_vcpu(PowerPCCPU *cpu, SpaprCpuCore *sc)
 191 {
 192     if (!sc->pre_3_0_migration) {
 193         vmstate_unregister(NULL, &vmstate_spapr_cpu_state, cpu->machine_data);
 194     }
 195     spapr_irq_cpu_intc_destroy(SPAPR_MACHINE(qdev_get_machine()), cpu);
 196     qdev_unrealize(DEVICE(cpu));
 197 }
 198
 199 /*
 200  * Called when CPUs are hot-plugged.
 201  */
 202 static void spapr_cpu_core_reset(DeviceState *dev)
 203 {
 204     CPUCore *cc = CPU_CORE(dev);
 205     SpaprCpuCore *sc = SPAPR_CPU_CORE(dev);
 206     int i;
 207
 208     for (i = 0; i < cc->nr_threads; i++) {
 209         spapr_reset_vcpu(sc->threads[i]);
 210     }
 211 }
 212
 213 /*
 214  * Called by the machine reset.
 215  */
 216 static void spapr_cpu_core_reset_handler(void *opaque)
 217 {
 218     spapr_cpu_core_reset(opaque);
 219 }
 220
 221 static void spapr_delete_vcpu(PowerPCCPU *cpu)
 222 {
 223     SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
 224
 225     cpu->machine_data = NULL;
 226     g_free(spapr_cpu);
 227     object_unparent(OBJECT(cpu));
 228 }
 229
 230 static void spapr_cpu_core_unrealize(DeviceState *dev)
 231 {
 232     SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
 233     CPUCore *cc = CPU_CORE(dev);
 234     int i;
 235
 236     for (i = 0; i < cc->nr_threads; i++) {
 237         if (sc->threads[i]) {
 238             /*
 239              * Since this we can get here from the error path of
 240              * spapr_cpu_core_realize(), make sure we only unrealize
 241              * vCPUs that have already been realized.
 242              */
 243             if (object_property_get_bool(OBJECT(sc->threads[i]), "realized",
 244                                          &error_abort)) {
 245                 spapr_unrealize_vcpu(sc->threads[i], sc);
 246             }
 247             spapr_delete_vcpu(sc->threads[i]);
 248         }
 249     }
 250     g_free(sc->threads);
 251     qemu_unregister_reset(spapr_cpu_core_reset_handler, sc);
 252 }
 253
 254 static bool spapr_realize_vcpu(PowerPCCPU *cpu, SpaprMachineState *spapr,
 255                                SpaprCpuCore *sc, Error **errp)
 256 {
 257     CPUPPCState *env = &cpu->env;
 258     CPUState *cs = CPU(cpu);
 259
 260     if (!qdev_realize(DEVICE(cpu), NULL, errp)) {
 261         return false;
 262     }
 263
 264     cpu_ppc_set_vhyp(cpu, PPC_VIRTUAL_HYPERVISOR(spapr));
 265     kvmppc_set_papr(cpu);
 266
 267     /* Set time-base frequency to 512 MHz. vhyp must be set first. */
 268     cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ);
 269
 270     if (spapr_irq_cpu_intc_create(spapr, cpu, errp) < 0) {
 271         qdev_unrealize(DEVICE(cpu));
 272         return false;
 273     }
 274
 275     if (!sc->pre_3_0_migration) {
 276         vmstate_register(NULL, cs->cpu_index, &vmstate_spapr_cpu_state,
 277                          cpu->machine_data);
 278     }
 279     return true;
 280 }
 281
 282 static PowerPCCPU *spapr_create_vcpu(SpaprCpuCore *sc, int i, Error **errp)
 283 {
 284     SpaprCpuCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(sc);
 285     CPUCore *cc = CPU_CORE(sc);
 286     g_autoptr(Object) obj = NULL;
 287     g_autofree char *id = NULL;
 288     CPUState *cs;
 289     PowerPCCPU *cpu;
 290
 291     obj = object_new(scc->cpu_type);
 292
 293     cs = CPU(obj);
 294     cpu = POWERPC_CPU(obj);
 295     /*
 296      * All CPUs start halted. CPU0 is unhalted from the machine level reset code
 297      * and the rest are explicitly started up by the guest using an RTAS call.
 298      */
 299     cs->start_powered_off = true;
 300     cs->cpu_index = cc->core_id + i;
 301     if (!spapr_set_vcpu_id(cpu, cs->cpu_index, errp)) {
 302         return NULL;
 303     }
 304
 305     cpu->node_id = sc->node_id;
 306
 307     id = g_strdup_printf("thread[%d]", i);
 308     object_property_add_child(OBJECT(sc), id, obj);
 309
 310     cpu->machine_data = g_new0(SpaprCpuState, 1);
 311
 312     return cpu;
 313 }
 314
 315 static void spapr_cpu_core_realize(DeviceState *dev, Error **errp)
 316 {
 317     /* We don't use SPAPR_MACHINE() in order to exit gracefully if the user
 318      * tries to add a sPAPR CPU core to a non-pseries machine.
 319      */
 320     SpaprMachineState *spapr =
 321         (SpaprMachineState *) object_dynamic_cast(qdev_get_machine(),
 322                                                   TYPE_SPAPR_MACHINE);
 323     SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
 324     CPUCore *cc = CPU_CORE(OBJECT(dev));
 325     int i;
 326
 327     if (!spapr) {
 328         error_setg(errp, TYPE_SPAPR_CPU_CORE " needs a pseries machine");
 329         return;
 330     }
 331
 332     qemu_register_reset(spapr_cpu_core_reset_handler, sc);
 333     sc->threads = g_new0(PowerPCCPU *, cc->nr_threads);
 334     for (i = 0; i < cc->nr_threads; i++) {
 335         sc->threads[i] = spapr_create_vcpu(sc, i, errp);
 336         if (!sc->threads[i] ||
 337             !spapr_realize_vcpu(sc->threads[i], spapr, sc, errp)) {
 338             spapr_cpu_core_unrealize(dev);
 339             return;
 340         }
 341     }
 342 }
 343
 344 static Property spapr_cpu_core_properties[] = {
 345     DEFINE_PROP_INT32("node-id", SpaprCpuCore, node_id, CPU_UNSET_NUMA_NODE_ID),
 346     DEFINE_PROP_BOOL("pre-3.0-migration", SpaprCpuCore, pre_3_0_migration,
 347                      false),
 348     DEFINE_PROP_END_OF_LIST()
 349 };
 350
 351 static void spapr_cpu_core_class_init(ObjectClass *oc, void *data)
 352 {
 353     DeviceClass *dc = DEVICE_CLASS(oc);
 354     SpaprCpuCoreClass *scc = SPAPR_CPU_CORE_CLASS(oc);
 355
 356     dc->realize = spapr_cpu_core_realize;
 357     dc->unrealize = spapr_cpu_core_unrealize;
 358     dc->reset = spapr_cpu_core_reset;
 359     device_class_set_props(dc, spapr_cpu_core_properties);
 360     scc->cpu_type = data;
 361 }
 362
 363 #define DEFINE_SPAPR_CPU_CORE_TYPE(cpu_model) \
 364     {                                                   \
 365         .parent = TYPE_SPAPR_CPU_CORE,                  \
 366         .class_data = (void *) POWERPC_CPU_TYPE_NAME(cpu_model), \
 367         .class_init = spapr_cpu_core_class_init,        \
 368         .name = SPAPR_CPU_CORE_TYPE_NAME(cpu_model),    \
 369     }
 370
 371 static const TypeInfo spapr_cpu_core_type_infos[] = {
 372     {
 373         .name = TYPE_SPAPR_CPU_CORE,
 374         .parent = TYPE_CPU_CORE,
 375         .abstract = true,
 376         .instance_size = sizeof(SpaprCpuCore),
 377         .class_size = sizeof(SpaprCpuCoreClass),
 378     },
 379     DEFINE_SPAPR_CPU_CORE_TYPE("970_v2.2"),
 380     DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.0"),
 381     DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.1"),
 382     DEFINE_SPAPR_CPU_CORE_TYPE("power5+_v2.1"),
 383     DEFINE_SPAPR_CPU_CORE_TYPE("power7_v2.3"),
 384     DEFINE_SPAPR_CPU_CORE_TYPE("power7+_v2.1"),
 385     DEFINE_SPAPR_CPU_CORE_TYPE("power8_v2.0"),
 386     DEFINE_SPAPR_CPU_CORE_TYPE("power8e_v2.1"),
 387     DEFINE_SPAPR_CPU_CORE_TYPE("power8nvl_v1.0"),
 388     DEFINE_SPAPR_CPU_CORE_TYPE("power9_v1.0"),
 389     DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"),
 390     DEFINE_SPAPR_CPU_CORE_TYPE("power10_v1.0"),
 391     DEFINE_SPAPR_CPU_CORE_TYPE("power10_v2.0"),
 392 #ifdef CONFIG_KVM
 393     DEFINE_SPAPR_CPU_CORE_TYPE("host"),
 394 #endif
 395 };
 396
 397 DEFINE_TYPES(spapr_cpu_core_type_infos)