2 * QEMU PowerPC XIVE interrupt controller model
4 * Copyright (c) 2017-2018, IBM Corporation.
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
10 #include "qemu/osdep.h"
12 #include "qemu/module.h"
13 #include "qapi/error.h"
14 #include "target/ppc/cpu.h"
15 #include "sysemu/cpus.h"
16 #include "sysemu/dma.h"
17 #include "sysemu/reset.h"
18 #include "hw/qdev-properties.h"
19 #include "migration/vmstate.h"
20 #include "monitor/monitor.h"
22 #include "hw/ppc/xive.h"
23 #include "hw/ppc/xive_regs.h"
27 * XIVE Thread Interrupt Management context
31 * Convert an Interrupt Pending Buffer (IPB) register to a Pending
32 * Interrupt Priority Register (PIPR), which contains the priority of
33 * the most favored pending notification.
35 static uint8_t ipb_to_pipr(uint8_t ibp
)
37 return ibp
? clz32((uint32_t)ibp
<< 24) : 0xff;
40 static uint8_t exception_mask(uint8_t ring
)
48 g_assert_not_reached();
52 static qemu_irq
xive_tctx_output(XiveTCTX
*tctx
, uint8_t ring
)
56 return 0; /* Not supported */
58 return tctx
->os_output
;
61 return tctx
->hv_output
;
67 static uint64_t xive_tctx_accept(XiveTCTX
*tctx
, uint8_t ring
)
69 uint8_t *regs
= &tctx
->regs
[ring
];
70 uint8_t nsr
= regs
[TM_NSR
];
71 uint8_t mask
= exception_mask(ring
);
73 qemu_irq_lower(xive_tctx_output(tctx
, ring
));
75 if (regs
[TM_NSR
] & mask
) {
76 uint8_t cppr
= regs
[TM_PIPR
];
80 /* Reset the pending buffer bit */
81 regs
[TM_IPB
] &= ~xive_priority_to_ipb(cppr
);
82 regs
[TM_PIPR
] = ipb_to_pipr(regs
[TM_IPB
]);
84 /* Drop Exception bit */
85 regs
[TM_NSR
] &= ~mask
;
87 trace_xive_tctx_accept(tctx
->cs
->cpu_index
, ring
,
88 regs
[TM_IPB
], regs
[TM_PIPR
],
89 regs
[TM_CPPR
], regs
[TM_NSR
]);
92 return (nsr
<< 8) | regs
[TM_CPPR
];
95 static void xive_tctx_notify(XiveTCTX
*tctx
, uint8_t ring
)
97 uint8_t *regs
= &tctx
->regs
[ring
];
99 if (regs
[TM_PIPR
] < regs
[TM_CPPR
]) {
102 regs
[TM_NSR
] |= TM_QW1_NSR_EO
;
105 regs
[TM_NSR
] |= (TM_QW3_NSR_HE_PHYS
<< 6);
108 g_assert_not_reached();
110 trace_xive_tctx_notify(tctx
->cs
->cpu_index
, ring
,
111 regs
[TM_IPB
], regs
[TM_PIPR
],
112 regs
[TM_CPPR
], regs
[TM_NSR
]);
113 qemu_irq_raise(xive_tctx_output(tctx
, ring
));
117 static void xive_tctx_set_cppr(XiveTCTX
*tctx
, uint8_t ring
, uint8_t cppr
)
119 uint8_t *regs
= &tctx
->regs
[ring
];
121 trace_xive_tctx_set_cppr(tctx
->cs
->cpu_index
, ring
,
122 regs
[TM_IPB
], regs
[TM_PIPR
],
125 if (cppr
> XIVE_PRIORITY_MAX
) {
129 tctx
->regs
[ring
+ TM_CPPR
] = cppr
;
131 /* CPPR has changed, check if we need to raise a pending exception */
132 xive_tctx_notify(tctx
, ring
);
135 void xive_tctx_ipb_update(XiveTCTX
*tctx
, uint8_t ring
, uint8_t ipb
)
137 uint8_t *regs
= &tctx
->regs
[ring
];
140 regs
[TM_PIPR
] = ipb_to_pipr(regs
[TM_IPB
]);
141 xive_tctx_notify(tctx
, ring
);
145 * XIVE Thread Interrupt Management Area (TIMA)
148 static void xive_tm_set_hv_cppr(XivePresenter
*xptr
, XiveTCTX
*tctx
,
149 hwaddr offset
, uint64_t value
, unsigned size
)
151 xive_tctx_set_cppr(tctx
, TM_QW3_HV_PHYS
, value
& 0xff);
154 static uint64_t xive_tm_ack_hv_reg(XivePresenter
*xptr
, XiveTCTX
*tctx
,
155 hwaddr offset
, unsigned size
)
157 return xive_tctx_accept(tctx
, TM_QW3_HV_PHYS
);
160 static uint64_t xive_tm_pull_pool_ctx(XivePresenter
*xptr
, XiveTCTX
*tctx
,
161 hwaddr offset
, unsigned size
)
163 uint32_t qw2w2_prev
= xive_tctx_word2(&tctx
->regs
[TM_QW2_HV_POOL
]);
166 qw2w2
= xive_set_field32(TM_QW2W2_VP
, qw2w2_prev
, 0);
167 memcpy(&tctx
->regs
[TM_QW2_HV_POOL
+ TM_WORD2
], &qw2w2
, 4);
171 static void xive_tm_vt_push(XivePresenter
*xptr
, XiveTCTX
*tctx
, hwaddr offset
,
172 uint64_t value
, unsigned size
)
174 tctx
->regs
[TM_QW3_HV_PHYS
+ TM_WORD2
] = value
& 0xff;
177 static uint64_t xive_tm_vt_poll(XivePresenter
*xptr
, XiveTCTX
*tctx
,
178 hwaddr offset
, unsigned size
)
180 return tctx
->regs
[TM_QW3_HV_PHYS
+ TM_WORD2
] & 0xff;
184 * Define an access map for each page of the TIMA that we will use in
185 * the memory region ops to filter values when doing loads and stores
186 * of raw registers values
188 * Registers accessibility bits :
196 static const uint8_t xive_tm_hw_view
[] = {
197 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */
198 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-1 OS */
199 0, 0, 3, 3, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */
200 3, 3, 3, 3, 0, 3, 0, 2, 3, 0, 0, 3, 3, 3, 3, 0, /* QW-3 PHYS */
203 static const uint8_t xive_tm_hv_view
[] = {
204 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */
205 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-1 OS */
206 0, 0, 3, 3, 0, 0, 0, 0, 0, 3, 3, 3, 0, 0, 0, 0, /* QW-2 POOL */
207 3, 3, 3, 3, 0, 3, 0, 2, 3, 0, 0, 3, 0, 0, 0, 0, /* QW-3 PHYS */
210 static const uint8_t xive_tm_os_view
[] = {
211 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0, /* QW-0 User */
212 2, 3, 2, 2, 2, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-1 OS */
213 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-2 POOL */
214 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-3 PHYS */
217 static const uint8_t xive_tm_user_view
[] = {
218 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-0 User */
219 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-1 OS */
220 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-2 POOL */
221 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* QW-3 PHYS */
225 * Overall TIMA access map for the thread interrupt management context
228 static const uint8_t *xive_tm_views
[] = {
229 [XIVE_TM_HW_PAGE
] = xive_tm_hw_view
,
230 [XIVE_TM_HV_PAGE
] = xive_tm_hv_view
,
231 [XIVE_TM_OS_PAGE
] = xive_tm_os_view
,
232 [XIVE_TM_USER_PAGE
] = xive_tm_user_view
,
236 * Computes a register access mask for a given offset in the TIMA
238 static uint64_t xive_tm_mask(hwaddr offset
, unsigned size
, bool write
)
240 uint8_t page_offset
= (offset
>> TM_SHIFT
) & 0x3;
241 uint8_t reg_offset
= offset
& 0x3F;
242 uint8_t reg_mask
= write
? 0x1 : 0x2;
246 for (i
= 0; i
< size
; i
++) {
247 if (xive_tm_views
[page_offset
][reg_offset
+ i
] & reg_mask
) {
248 mask
|= (uint64_t) 0xff << (8 * (size
- i
- 1));
255 static void xive_tm_raw_write(XiveTCTX
*tctx
, hwaddr offset
, uint64_t value
,
258 uint8_t ring_offset
= offset
& 0x30;
259 uint8_t reg_offset
= offset
& 0x3F;
260 uint64_t mask
= xive_tm_mask(offset
, size
, true);
264 * Only 4 or 8 bytes stores are allowed and the User ring is
267 if (size
< 4 || !mask
|| ring_offset
== TM_QW0_USER
) {
268 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid write access at TIMA @%"
269 HWADDR_PRIx
"\n", offset
);
274 * Use the register offset for the raw values and filter out
277 for (i
= 0; i
< size
; i
++) {
278 uint8_t byte_mask
= (mask
>> (8 * (size
- i
- 1)));
280 tctx
->regs
[reg_offset
+ i
] = (value
>> (8 * (size
- i
- 1))) &
286 static uint64_t xive_tm_raw_read(XiveTCTX
*tctx
, hwaddr offset
, unsigned size
)
288 uint8_t ring_offset
= offset
& 0x30;
289 uint8_t reg_offset
= offset
& 0x3F;
290 uint64_t mask
= xive_tm_mask(offset
, size
, false);
295 * Only 4 or 8 bytes loads are allowed and the User ring is
298 if (size
< 4 || !mask
|| ring_offset
== TM_QW0_USER
) {
299 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid read access at TIMA @%"
300 HWADDR_PRIx
"\n", offset
);
304 /* Use the register offset for the raw values */
306 for (i
= 0; i
< size
; i
++) {
307 ret
|= (uint64_t) tctx
->regs
[reg_offset
+ i
] << (8 * (size
- i
- 1));
310 /* filter out reserved values */
315 * The TM context is mapped twice within each page. Stores and loads
316 * to the first mapping below 2K write and read the specified values
317 * without modification. The second mapping above 2K performs specific
318 * state changes (side effects) in addition to setting/returning the
319 * interrupt management area context of the processor thread.
321 static uint64_t xive_tm_ack_os_reg(XivePresenter
*xptr
, XiveTCTX
*tctx
,
322 hwaddr offset
, unsigned size
)
324 return xive_tctx_accept(tctx
, TM_QW1_OS
);
327 static void xive_tm_set_os_cppr(XivePresenter
*xptr
, XiveTCTX
*tctx
,
328 hwaddr offset
, uint64_t value
, unsigned size
)
330 xive_tctx_set_cppr(tctx
, TM_QW1_OS
, value
& 0xff);
334 * Adjust the IPB to allow a CPU to process event queues of other
335 * priorities during one physical interrupt cycle.
337 static void xive_tm_set_os_pending(XivePresenter
*xptr
, XiveTCTX
*tctx
,
338 hwaddr offset
, uint64_t value
, unsigned size
)
340 xive_tctx_ipb_update(tctx
, TM_QW1_OS
, xive_priority_to_ipb(value
& 0xff));
343 static void xive_os_cam_decode(uint32_t cam
, uint8_t *nvt_blk
,
344 uint32_t *nvt_idx
, bool *vo
)
347 *nvt_blk
= xive_nvt_blk(cam
);
350 *nvt_idx
= xive_nvt_idx(cam
);
353 *vo
= !!(cam
& TM_QW1W2_VO
);
357 static uint32_t xive_tctx_get_os_cam(XiveTCTX
*tctx
, uint8_t *nvt_blk
,
358 uint32_t *nvt_idx
, bool *vo
)
360 uint32_t qw1w2
= xive_tctx_word2(&tctx
->regs
[TM_QW1_OS
]);
361 uint32_t cam
= be32_to_cpu(qw1w2
);
363 xive_os_cam_decode(cam
, nvt_blk
, nvt_idx
, vo
);
367 static void xive_tctx_set_os_cam(XiveTCTX
*tctx
, uint32_t qw1w2
)
369 memcpy(&tctx
->regs
[TM_QW1_OS
+ TM_WORD2
], &qw1w2
, 4);
372 static uint64_t xive_tm_pull_os_ctx(XivePresenter
*xptr
, XiveTCTX
*tctx
,
373 hwaddr offset
, unsigned size
)
381 qw1w2
= xive_tctx_get_os_cam(tctx
, &nvt_blk
, &nvt_idx
, &vo
);
384 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: pulling invalid NVT %x/%x !?\n",
388 /* Invalidate CAM line */
389 qw1w2_new
= xive_set_field32(TM_QW1W2_VO
, qw1w2
, 0);
390 xive_tctx_set_os_cam(tctx
, qw1w2_new
);
394 static void xive_tctx_need_resend(XiveRouter
*xrtr
, XiveTCTX
*tctx
,
395 uint8_t nvt_blk
, uint32_t nvt_idx
)
401 * Grab the associated NVT to pull the pending bits, and merge
402 * them with the IPB of the thread interrupt context registers
404 if (xive_router_get_nvt(xrtr
, nvt_blk
, nvt_idx
, &nvt
)) {
405 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid NVT %x/%x\n",
410 ipb
= xive_get_field32(NVT_W4_IPB
, nvt
.w4
);
413 /* Reset the NVT value */
414 nvt
.w4
= xive_set_field32(NVT_W4_IPB
, nvt
.w4
, 0);
415 xive_router_write_nvt(xrtr
, nvt_blk
, nvt_idx
, &nvt
, 4);
417 /* Merge in current context */
418 xive_tctx_ipb_update(tctx
, TM_QW1_OS
, ipb
);
423 * Updating the OS CAM line can trigger a resend of interrupt
425 static void xive_tm_push_os_ctx(XivePresenter
*xptr
, XiveTCTX
*tctx
,
426 hwaddr offset
, uint64_t value
, unsigned size
)
428 uint32_t cam
= value
;
429 uint32_t qw1w2
= cpu_to_be32(cam
);
434 xive_os_cam_decode(cam
, &nvt_blk
, &nvt_idx
, &vo
);
436 /* First update the registers */
437 xive_tctx_set_os_cam(tctx
, qw1w2
);
439 /* Check the interrupt pending bits */
441 xive_tctx_need_resend(XIVE_ROUTER(xptr
), tctx
, nvt_blk
, nvt_idx
);
446 * Define a mapping of "special" operations depending on the TIMA page
447 * offset and the size of the operation.
449 typedef struct XiveTmOp
{
453 void (*write_handler
)(XivePresenter
*xptr
, XiveTCTX
*tctx
,
455 uint64_t value
, unsigned size
);
456 uint64_t (*read_handler
)(XivePresenter
*xptr
, XiveTCTX
*tctx
, hwaddr offset
,
460 static const XiveTmOp xive_tm_operations
[] = {
462 * MMIOs below 2K : raw values and special operations without side
465 { XIVE_TM_OS_PAGE
, TM_QW1_OS
+ TM_CPPR
, 1, xive_tm_set_os_cppr
, NULL
},
466 { XIVE_TM_HV_PAGE
, TM_QW1_OS
+ TM_WORD2
, 4, xive_tm_push_os_ctx
, NULL
},
467 { XIVE_TM_HV_PAGE
, TM_QW3_HV_PHYS
+ TM_CPPR
, 1, xive_tm_set_hv_cppr
, NULL
},
468 { XIVE_TM_HV_PAGE
, TM_QW3_HV_PHYS
+ TM_WORD2
, 1, xive_tm_vt_push
, NULL
},
469 { XIVE_TM_HV_PAGE
, TM_QW3_HV_PHYS
+ TM_WORD2
, 1, NULL
, xive_tm_vt_poll
},
471 /* MMIOs above 2K : special operations with side effects */
472 { XIVE_TM_OS_PAGE
, TM_SPC_ACK_OS_REG
, 2, NULL
, xive_tm_ack_os_reg
},
473 { XIVE_TM_OS_PAGE
, TM_SPC_SET_OS_PENDING
, 1, xive_tm_set_os_pending
, NULL
},
474 { XIVE_TM_HV_PAGE
, TM_SPC_PULL_OS_CTX
, 4, NULL
, xive_tm_pull_os_ctx
},
475 { XIVE_TM_HV_PAGE
, TM_SPC_PULL_OS_CTX
, 8, NULL
, xive_tm_pull_os_ctx
},
476 { XIVE_TM_HV_PAGE
, TM_SPC_ACK_HV_REG
, 2, NULL
, xive_tm_ack_hv_reg
},
477 { XIVE_TM_HV_PAGE
, TM_SPC_PULL_POOL_CTX
, 4, NULL
, xive_tm_pull_pool_ctx
},
478 { XIVE_TM_HV_PAGE
, TM_SPC_PULL_POOL_CTX
, 8, NULL
, xive_tm_pull_pool_ctx
},
481 static const XiveTmOp
*xive_tm_find_op(hwaddr offset
, unsigned size
, bool write
)
483 uint8_t page_offset
= (offset
>> TM_SHIFT
) & 0x3;
484 uint32_t op_offset
= offset
& 0xFFF;
487 for (i
= 0; i
< ARRAY_SIZE(xive_tm_operations
); i
++) {
488 const XiveTmOp
*xto
= &xive_tm_operations
[i
];
490 /* Accesses done from a more privileged TIMA page is allowed */
491 if (xto
->page_offset
>= page_offset
&&
492 xto
->op_offset
== op_offset
&&
494 ((write
&& xto
->write_handler
) || (!write
&& xto
->read_handler
))) {
504 void xive_tctx_tm_write(XivePresenter
*xptr
, XiveTCTX
*tctx
, hwaddr offset
,
505 uint64_t value
, unsigned size
)
509 trace_xive_tctx_tm_write(offset
, size
, value
);
512 * TODO: check V bit in Q[0-3]W2
516 * First, check for special operations in the 2K region
518 if (offset
& 0x800) {
519 xto
= xive_tm_find_op(offset
, size
, true);
521 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid write access at TIMA "
522 "@%"HWADDR_PRIx
"\n", offset
);
524 xto
->write_handler(xptr
, tctx
, offset
, value
, size
);
530 * Then, for special operations in the region below 2K.
532 xto
= xive_tm_find_op(offset
, size
, true);
534 xto
->write_handler(xptr
, tctx
, offset
, value
, size
);
539 * Finish with raw access to the register values
541 xive_tm_raw_write(tctx
, offset
, value
, size
);
544 uint64_t xive_tctx_tm_read(XivePresenter
*xptr
, XiveTCTX
*tctx
, hwaddr offset
,
551 * TODO: check V bit in Q[0-3]W2
555 * First, check for special operations in the 2K region
557 if (offset
& 0x800) {
558 xto
= xive_tm_find_op(offset
, size
, false);
560 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid read access to TIMA"
561 "@%"HWADDR_PRIx
"\n", offset
);
564 ret
= xto
->read_handler(xptr
, tctx
, offset
, size
);
569 * Then, for special operations in the region below 2K.
571 xto
= xive_tm_find_op(offset
, size
, false);
573 ret
= xto
->read_handler(xptr
, tctx
, offset
, size
);
578 * Finish with raw access to the register values
580 ret
= xive_tm_raw_read(tctx
, offset
, size
);
582 trace_xive_tctx_tm_read(offset
, size
, ret
);
586 static char *xive_tctx_ring_print(uint8_t *ring
)
588 uint32_t w2
= xive_tctx_word2(ring
);
590 return g_strdup_printf("%02x %02x %02x %02x %02x "
591 "%02x %02x %02x %08x",
592 ring
[TM_NSR
], ring
[TM_CPPR
], ring
[TM_IPB
], ring
[TM_LSMFB
],
593 ring
[TM_ACK_CNT
], ring
[TM_INC
], ring
[TM_AGE
], ring
[TM_PIPR
],
597 static const char * const xive_tctx_ring_names
[] = {
598 "USER", "OS", "POOL", "PHYS",
602 * kvm_irqchip_in_kernel() will cause the compiler to turn this
603 * info a nop if CONFIG_KVM isn't defined.
605 #define xive_in_kernel(xptr) \
606 (kvm_irqchip_in_kernel() && \
608 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); \
609 xpc->in_kernel ? xpc->in_kernel(xptr) : false; \
612 void xive_tctx_pic_print_info(XiveTCTX
*tctx
, Monitor
*mon
)
617 /* Skip partially initialized vCPUs. This can happen on sPAPR when vCPUs
618 * are hot plugged or unplugged.
624 cpu_index
= tctx
->cs
? tctx
->cs
->cpu_index
: -1;
626 if (xive_in_kernel(tctx
->xptr
)) {
627 Error
*local_err
= NULL
;
629 kvmppc_xive_cpu_synchronize_state(tctx
, &local_err
);
631 error_report_err(local_err
);
636 monitor_printf(mon
, "CPU[%04x]: QW NSR CPPR IPB LSMFB ACK# INC AGE PIPR"
639 for (i
= 0; i
< XIVE_TM_RING_COUNT
; i
++) {
640 char *s
= xive_tctx_ring_print(&tctx
->regs
[i
* XIVE_TM_RING_SIZE
]);
641 monitor_printf(mon
, "CPU[%04x]: %4s %s\n", cpu_index
,
642 xive_tctx_ring_names
[i
], s
);
647 void xive_tctx_reset(XiveTCTX
*tctx
)
649 memset(tctx
->regs
, 0, sizeof(tctx
->regs
));
651 /* Set some defaults */
652 tctx
->regs
[TM_QW1_OS
+ TM_LSMFB
] = 0xFF;
653 tctx
->regs
[TM_QW1_OS
+ TM_ACK_CNT
] = 0xFF;
654 tctx
->regs
[TM_QW1_OS
+ TM_AGE
] = 0xFF;
657 * Initialize PIPR to 0xFF to avoid phantom interrupts when the
660 tctx
->regs
[TM_QW1_OS
+ TM_PIPR
] =
661 ipb_to_pipr(tctx
->regs
[TM_QW1_OS
+ TM_IPB
]);
662 tctx
->regs
[TM_QW3_HV_PHYS
+ TM_PIPR
] =
663 ipb_to_pipr(tctx
->regs
[TM_QW3_HV_PHYS
+ TM_IPB
]);
666 static void xive_tctx_realize(DeviceState
*dev
, Error
**errp
)
668 XiveTCTX
*tctx
= XIVE_TCTX(dev
);
675 cpu
= POWERPC_CPU(tctx
->cs
);
677 switch (PPC_INPUT(env
)) {
678 case PPC_FLAGS_INPUT_POWER9
:
679 tctx
->hv_output
= env
->irq_inputs
[POWER9_INPUT_HINT
];
680 tctx
->os_output
= env
->irq_inputs
[POWER9_INPUT_INT
];
684 error_setg(errp
, "XIVE interrupt controller does not support "
685 "this CPU bus model");
689 /* Connect the presenter to the VCPU (required for CPU hotplug) */
690 if (xive_in_kernel(tctx
->xptr
)) {
691 if (kvmppc_xive_cpu_connect(tctx
, errp
) < 0) {
697 static int vmstate_xive_tctx_pre_save(void *opaque
)
699 XiveTCTX
*tctx
= XIVE_TCTX(opaque
);
700 Error
*local_err
= NULL
;
703 if (xive_in_kernel(tctx
->xptr
)) {
704 ret
= kvmppc_xive_cpu_get_state(tctx
, &local_err
);
706 error_report_err(local_err
);
714 static int vmstate_xive_tctx_post_load(void *opaque
, int version_id
)
716 XiveTCTX
*tctx
= XIVE_TCTX(opaque
);
717 Error
*local_err
= NULL
;
720 if (xive_in_kernel(tctx
->xptr
)) {
722 * Required for hotplugged CPU, for which the state comes
723 * after all states of the machine.
725 ret
= kvmppc_xive_cpu_set_state(tctx
, &local_err
);
727 error_report_err(local_err
);
735 static const VMStateDescription vmstate_xive_tctx
= {
736 .name
= TYPE_XIVE_TCTX
,
738 .minimum_version_id
= 1,
739 .pre_save
= vmstate_xive_tctx_pre_save
,
740 .post_load
= vmstate_xive_tctx_post_load
,
741 .fields
= (VMStateField
[]) {
742 VMSTATE_BUFFER(regs
, XiveTCTX
),
743 VMSTATE_END_OF_LIST()
747 static Property xive_tctx_properties
[] = {
748 DEFINE_PROP_LINK("cpu", XiveTCTX
, cs
, TYPE_CPU
, CPUState
*),
749 DEFINE_PROP_LINK("presenter", XiveTCTX
, xptr
, TYPE_XIVE_PRESENTER
,
751 DEFINE_PROP_END_OF_LIST(),
754 static void xive_tctx_class_init(ObjectClass
*klass
, void *data
)
756 DeviceClass
*dc
= DEVICE_CLASS(klass
);
758 dc
->desc
= "XIVE Interrupt Thread Context";
759 dc
->realize
= xive_tctx_realize
;
760 dc
->vmsd
= &vmstate_xive_tctx
;
761 device_class_set_props(dc
, xive_tctx_properties
);
763 * Reason: part of XIVE interrupt controller, needs to be wired up
764 * by xive_tctx_create().
766 dc
->user_creatable
= false;
769 static const TypeInfo xive_tctx_info
= {
770 .name
= TYPE_XIVE_TCTX
,
771 .parent
= TYPE_DEVICE
,
772 .instance_size
= sizeof(XiveTCTX
),
773 .class_init
= xive_tctx_class_init
,
776 Object
*xive_tctx_create(Object
*cpu
, XivePresenter
*xptr
, Error
**errp
)
780 obj
= object_new(TYPE_XIVE_TCTX
);
781 object_property_add_child(cpu
, TYPE_XIVE_TCTX
, obj
);
783 object_property_set_link(obj
, "cpu", cpu
, &error_abort
);
784 object_property_set_link(obj
, "presenter", OBJECT(xptr
), &error_abort
);
785 if (!qdev_realize(DEVICE(obj
), NULL
, errp
)) {
786 object_unparent(obj
);
792 void xive_tctx_destroy(XiveTCTX
*tctx
)
794 Object
*obj
= OBJECT(tctx
);
796 object_unparent(obj
);
803 uint8_t xive_esb_set(uint8_t *pq
, uint8_t value
)
805 uint8_t old_pq
= *pq
& 0x3;
813 bool xive_esb_trigger(uint8_t *pq
)
815 uint8_t old_pq
= *pq
& 0x3;
819 xive_esb_set(pq
, XIVE_ESB_PENDING
);
821 case XIVE_ESB_PENDING
:
822 case XIVE_ESB_QUEUED
:
823 xive_esb_set(pq
, XIVE_ESB_QUEUED
);
826 xive_esb_set(pq
, XIVE_ESB_OFF
);
829 g_assert_not_reached();
833 bool xive_esb_eoi(uint8_t *pq
)
835 uint8_t old_pq
= *pq
& 0x3;
839 case XIVE_ESB_PENDING
:
840 xive_esb_set(pq
, XIVE_ESB_RESET
);
842 case XIVE_ESB_QUEUED
:
843 xive_esb_set(pq
, XIVE_ESB_PENDING
);
846 xive_esb_set(pq
, XIVE_ESB_OFF
);
849 g_assert_not_reached();
854 * XIVE Interrupt Source (or IVSE)
857 uint8_t xive_source_esb_get(XiveSource
*xsrc
, uint32_t srcno
)
859 assert(srcno
< xsrc
->nr_irqs
);
861 return xsrc
->status
[srcno
] & 0x3;
864 uint8_t xive_source_esb_set(XiveSource
*xsrc
, uint32_t srcno
, uint8_t pq
)
866 assert(srcno
< xsrc
->nr_irqs
);
868 return xive_esb_set(&xsrc
->status
[srcno
], pq
);
872 * Returns whether the event notification should be forwarded.
874 static bool xive_source_lsi_trigger(XiveSource
*xsrc
, uint32_t srcno
)
876 uint8_t old_pq
= xive_source_esb_get(xsrc
, srcno
);
878 xive_source_set_asserted(xsrc
, srcno
, true);
882 xive_source_esb_set(xsrc
, srcno
, XIVE_ESB_PENDING
);
890 * Sources can be configured with PQ offloading in which case the check
891 * on the PQ state bits of MSIs is disabled
893 static bool xive_source_esb_disabled(XiveSource
*xsrc
, uint32_t srcno
)
895 return (xsrc
->esb_flags
& XIVE_SRC_PQ_DISABLE
) &&
896 !xive_source_irq_is_lsi(xsrc
, srcno
);
900 * Returns whether the event notification should be forwarded.
902 static bool xive_source_esb_trigger(XiveSource
*xsrc
, uint32_t srcno
)
906 assert(srcno
< xsrc
->nr_irqs
);
908 if (xive_source_esb_disabled(xsrc
, srcno
)) {
912 ret
= xive_esb_trigger(&xsrc
->status
[srcno
]);
914 if (xive_source_irq_is_lsi(xsrc
, srcno
) &&
915 xive_source_esb_get(xsrc
, srcno
) == XIVE_ESB_QUEUED
) {
916 qemu_log_mask(LOG_GUEST_ERROR
,
917 "XIVE: queued an event on LSI IRQ %d\n", srcno
);
924 * Returns whether the event notification should be forwarded.
926 static bool xive_source_esb_eoi(XiveSource
*xsrc
, uint32_t srcno
)
930 assert(srcno
< xsrc
->nr_irqs
);
932 if (xive_source_esb_disabled(xsrc
, srcno
)) {
933 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid EOI for IRQ %d\n", srcno
);
937 ret
= xive_esb_eoi(&xsrc
->status
[srcno
]);
940 * LSI sources do not set the Q bit but they can still be
941 * asserted, in which case we should forward a new event
944 if (xive_source_irq_is_lsi(xsrc
, srcno
) &&
945 xive_source_is_asserted(xsrc
, srcno
)) {
946 ret
= xive_source_lsi_trigger(xsrc
, srcno
);
953 * Forward the source event notification to the Router
955 static void xive_source_notify(XiveSource
*xsrc
, int srcno
)
957 XiveNotifierClass
*xnc
= XIVE_NOTIFIER_GET_CLASS(xsrc
->xive
);
958 bool pq_checked
= !xive_source_esb_disabled(xsrc
, srcno
);
961 xnc
->notify(xsrc
->xive
, srcno
, pq_checked
);
966 * In a two pages ESB MMIO setting, even page is the trigger page, odd
967 * page is for management
969 static inline bool addr_is_even(hwaddr addr
, uint32_t shift
)
971 return !((addr
>> shift
) & 1);
974 static inline bool xive_source_is_trigger_page(XiveSource
*xsrc
, hwaddr addr
)
976 return xive_source_esb_has_2page(xsrc
) &&
977 addr_is_even(addr
, xsrc
->esb_shift
- 1);
982 * Trigger page Management/EOI page
984 * ESB MMIO setting 2 pages 1 or 2 pages
986 * 0x000 .. 0x3FF -1 EOI and return 0|1
987 * 0x400 .. 0x7FF -1 EOI and return 0|1
988 * 0x800 .. 0xBFF -1 return PQ
989 * 0xC00 .. 0xCFF -1 return PQ and atomically PQ=00
990 * 0xD00 .. 0xDFF -1 return PQ and atomically PQ=01
991 * 0xE00 .. 0xDFF -1 return PQ and atomically PQ=10
992 * 0xF00 .. 0xDFF -1 return PQ and atomically PQ=11
994 static uint64_t xive_source_esb_read(void *opaque
, hwaddr addr
, unsigned size
)
996 XiveSource
*xsrc
= XIVE_SOURCE(opaque
);
997 uint32_t offset
= addr
& 0xFFF;
998 uint32_t srcno
= addr
>> xsrc
->esb_shift
;
1001 /* In a two pages ESB MMIO setting, trigger page should not be read */
1002 if (xive_source_is_trigger_page(xsrc
, addr
)) {
1003 qemu_log_mask(LOG_GUEST_ERROR
,
1004 "XIVE: invalid load on IRQ %d trigger page at "
1005 "0x%"HWADDR_PRIx
"\n", srcno
, addr
);
1010 case XIVE_ESB_LOAD_EOI
... XIVE_ESB_LOAD_EOI
+ 0x7FF:
1011 ret
= xive_source_esb_eoi(xsrc
, srcno
);
1013 /* Forward the source event notification for routing */
1015 xive_source_notify(xsrc
, srcno
);
1019 case XIVE_ESB_GET
... XIVE_ESB_GET
+ 0x3FF:
1020 ret
= xive_source_esb_get(xsrc
, srcno
);
1023 case XIVE_ESB_SET_PQ_00
... XIVE_ESB_SET_PQ_00
+ 0x0FF:
1024 case XIVE_ESB_SET_PQ_01
... XIVE_ESB_SET_PQ_01
+ 0x0FF:
1025 case XIVE_ESB_SET_PQ_10
... XIVE_ESB_SET_PQ_10
+ 0x0FF:
1026 case XIVE_ESB_SET_PQ_11
... XIVE_ESB_SET_PQ_11
+ 0x0FF:
1027 ret
= xive_source_esb_set(xsrc
, srcno
, (offset
>> 8) & 0x3);
1030 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid ESB load addr %x\n",
1034 trace_xive_source_esb_read(addr
, srcno
, ret
);
1041 * Trigger page Management/EOI page
1043 * ESB MMIO setting 2 pages 1 or 2 pages
1045 * 0x000 .. 0x3FF Trigger Trigger
1046 * 0x400 .. 0x7FF Trigger EOI
1047 * 0x800 .. 0xBFF Trigger undefined
1048 * 0xC00 .. 0xCFF Trigger PQ=00
1049 * 0xD00 .. 0xDFF Trigger PQ=01
1050 * 0xE00 .. 0xDFF Trigger PQ=10
1051 * 0xF00 .. 0xDFF Trigger PQ=11
1053 static void xive_source_esb_write(void *opaque
, hwaddr addr
,
1054 uint64_t value
, unsigned size
)
1056 XiveSource
*xsrc
= XIVE_SOURCE(opaque
);
1057 uint32_t offset
= addr
& 0xFFF;
1058 uint32_t srcno
= addr
>> xsrc
->esb_shift
;
1059 bool notify
= false;
1061 trace_xive_source_esb_write(addr
, srcno
, value
);
1063 /* In a two pages ESB MMIO setting, trigger page only triggers */
1064 if (xive_source_is_trigger_page(xsrc
, addr
)) {
1065 notify
= xive_source_esb_trigger(xsrc
, srcno
);
1071 notify
= xive_source_esb_trigger(xsrc
, srcno
);
1074 case XIVE_ESB_STORE_EOI
... XIVE_ESB_STORE_EOI
+ 0x3FF:
1075 if (!(xsrc
->esb_flags
& XIVE_SRC_STORE_EOI
)) {
1076 qemu_log_mask(LOG_GUEST_ERROR
,
1077 "XIVE: invalid Store EOI for IRQ %d\n", srcno
);
1081 notify
= xive_source_esb_eoi(xsrc
, srcno
);
1085 * This is an internal offset used to inject triggers when the PQ
1086 * state bits are not controlled locally. Such as for LSIs when
1089 case XIVE_ESB_INJECT
... XIVE_ESB_INJECT
+ 0x3FF:
1093 case XIVE_ESB_SET_PQ_00
... XIVE_ESB_SET_PQ_00
+ 0x0FF:
1094 case XIVE_ESB_SET_PQ_01
... XIVE_ESB_SET_PQ_01
+ 0x0FF:
1095 case XIVE_ESB_SET_PQ_10
... XIVE_ESB_SET_PQ_10
+ 0x0FF:
1096 case XIVE_ESB_SET_PQ_11
... XIVE_ESB_SET_PQ_11
+ 0x0FF:
1097 xive_source_esb_set(xsrc
, srcno
, (offset
>> 8) & 0x3);
1101 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid ESB write addr %x\n",
1107 /* Forward the source event notification for routing */
1109 xive_source_notify(xsrc
, srcno
);
1113 static const MemoryRegionOps xive_source_esb_ops
= {
1114 .read
= xive_source_esb_read
,
1115 .write
= xive_source_esb_write
,
1116 .endianness
= DEVICE_BIG_ENDIAN
,
1118 .min_access_size
= 8,
1119 .max_access_size
= 8,
1122 .min_access_size
= 8,
1123 .max_access_size
= 8,
1127 void xive_source_set_irq(void *opaque
, int srcno
, int val
)
1129 XiveSource
*xsrc
= XIVE_SOURCE(opaque
);
1130 bool notify
= false;
1132 if (xive_source_irq_is_lsi(xsrc
, srcno
)) {
1134 notify
= xive_source_lsi_trigger(xsrc
, srcno
);
1136 xive_source_set_asserted(xsrc
, srcno
, false);
1140 notify
= xive_source_esb_trigger(xsrc
, srcno
);
1144 /* Forward the source event notification for routing */
1146 xive_source_notify(xsrc
, srcno
);
1150 void xive_source_pic_print_info(XiveSource
*xsrc
, uint32_t offset
, Monitor
*mon
)
1154 for (i
= 0; i
< xsrc
->nr_irqs
; i
++) {
1155 uint8_t pq
= xive_source_esb_get(xsrc
, i
);
1157 if (pq
== XIVE_ESB_OFF
) {
1161 monitor_printf(mon
, " %08x %s %c%c%c\n", i
+ offset
,
1162 xive_source_irq_is_lsi(xsrc
, i
) ? "LSI" : "MSI",
1163 pq
& XIVE_ESB_VAL_P
? 'P' : '-',
1164 pq
& XIVE_ESB_VAL_Q
? 'Q' : '-',
1165 xive_source_is_asserted(xsrc
, i
) ? 'A' : ' ');
1169 static void xive_source_reset(void *dev
)
1171 XiveSource
*xsrc
= XIVE_SOURCE(dev
);
1173 /* Do not clear the LSI bitmap */
1175 /* PQs are initialized to 0b01 (Q=1) which corresponds to "ints off" */
1176 memset(xsrc
->status
, XIVE_ESB_OFF
, xsrc
->nr_irqs
);
1179 static void xive_source_realize(DeviceState
*dev
, Error
**errp
)
1181 XiveSource
*xsrc
= XIVE_SOURCE(dev
);
1182 size_t esb_len
= xive_source_esb_len(xsrc
);
1186 if (!xsrc
->nr_irqs
) {
1187 error_setg(errp
, "Number of interrupt needs to be greater than 0");
1191 if (xsrc
->esb_shift
!= XIVE_ESB_4K
&&
1192 xsrc
->esb_shift
!= XIVE_ESB_4K_2PAGE
&&
1193 xsrc
->esb_shift
!= XIVE_ESB_64K
&&
1194 xsrc
->esb_shift
!= XIVE_ESB_64K_2PAGE
) {
1195 error_setg(errp
, "Invalid ESB shift setting");
1199 xsrc
->status
= g_malloc0(xsrc
->nr_irqs
);
1200 xsrc
->lsi_map
= bitmap_new(xsrc
->nr_irqs
);
1202 memory_region_init(&xsrc
->esb_mmio
, OBJECT(xsrc
), "xive.esb", esb_len
);
1203 memory_region_init_io(&xsrc
->esb_mmio_emulated
, OBJECT(xsrc
),
1204 &xive_source_esb_ops
, xsrc
, "xive.esb-emulated",
1206 memory_region_add_subregion(&xsrc
->esb_mmio
, 0, &xsrc
->esb_mmio_emulated
);
1208 qemu_register_reset(xive_source_reset
, dev
);
1211 static const VMStateDescription vmstate_xive_source
= {
1212 .name
= TYPE_XIVE_SOURCE
,
1214 .minimum_version_id
= 1,
1215 .fields
= (VMStateField
[]) {
1216 VMSTATE_UINT32_EQUAL(nr_irqs
, XiveSource
, NULL
),
1217 VMSTATE_VBUFFER_UINT32(status
, XiveSource
, 1, NULL
, nr_irqs
),
1218 VMSTATE_END_OF_LIST()
1223 * The default XIVE interrupt source setting for the ESB MMIOs is two
1224 * 64k pages without Store EOI, to be in sync with KVM.
1226 static Property xive_source_properties
[] = {
1227 DEFINE_PROP_UINT64("flags", XiveSource
, esb_flags
, 0),
1228 DEFINE_PROP_UINT32("nr-irqs", XiveSource
, nr_irqs
, 0),
1229 DEFINE_PROP_UINT32("shift", XiveSource
, esb_shift
, XIVE_ESB_64K_2PAGE
),
1230 DEFINE_PROP_LINK("xive", XiveSource
, xive
, TYPE_XIVE_NOTIFIER
,
1232 DEFINE_PROP_END_OF_LIST(),
1235 static void xive_source_class_init(ObjectClass
*klass
, void *data
)
1237 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1239 dc
->desc
= "XIVE Interrupt Source";
1240 device_class_set_props(dc
, xive_source_properties
);
1241 dc
->realize
= xive_source_realize
;
1242 dc
->vmsd
= &vmstate_xive_source
;
1244 * Reason: part of XIVE interrupt controller, needs to be wired up,
1245 * e.g. by spapr_xive_instance_init().
1247 dc
->user_creatable
= false;
1250 static const TypeInfo xive_source_info
= {
1251 .name
= TYPE_XIVE_SOURCE
,
1252 .parent
= TYPE_DEVICE
,
1253 .instance_size
= sizeof(XiveSource
),
1254 .class_init
= xive_source_class_init
,
1261 void xive_end_queue_pic_print_info(XiveEND
*end
, uint32_t width
, Monitor
*mon
)
1263 uint64_t qaddr_base
= xive_end_qaddr(end
);
1264 uint32_t qsize
= xive_get_field32(END_W0_QSIZE
, end
->w0
);
1265 uint32_t qindex
= xive_get_field32(END_W1_PAGE_OFF
, end
->w1
);
1266 uint32_t qentries
= 1 << (qsize
+ 10);
1270 * print out the [ (qindex - (width - 1)) .. (qindex + 1)] window
1272 monitor_printf(mon
, " [ ");
1273 qindex
= (qindex
- (width
- 1)) & (qentries
- 1);
1274 for (i
= 0; i
< width
; i
++) {
1275 uint64_t qaddr
= qaddr_base
+ (qindex
<< 2);
1276 uint32_t qdata
= -1;
1278 if (dma_memory_read(&address_space_memory
, qaddr
,
1279 &qdata
, sizeof(qdata
), MEMTXATTRS_UNSPECIFIED
)) {
1280 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: failed to read EQ @0x%"
1281 HWADDR_PRIx
"\n", qaddr
);
1284 monitor_printf(mon
, "%s%08x ", i
== width
- 1 ? "^" : "",
1285 be32_to_cpu(qdata
));
1286 qindex
= (qindex
+ 1) & (qentries
- 1);
1288 monitor_printf(mon
, "]");
1291 void xive_end_pic_print_info(XiveEND
*end
, uint32_t end_idx
, Monitor
*mon
)
1293 uint64_t qaddr_base
= xive_end_qaddr(end
);
1294 uint32_t qindex
= xive_get_field32(END_W1_PAGE_OFF
, end
->w1
);
1295 uint32_t qgen
= xive_get_field32(END_W1_GENERATION
, end
->w1
);
1296 uint32_t qsize
= xive_get_field32(END_W0_QSIZE
, end
->w0
);
1297 uint32_t qentries
= 1 << (qsize
+ 10);
1299 uint32_t nvt_blk
= xive_get_field32(END_W6_NVT_BLOCK
, end
->w6
);
1300 uint32_t nvt_idx
= xive_get_field32(END_W6_NVT_INDEX
, end
->w6
);
1301 uint8_t priority
= xive_get_field32(END_W7_F0_PRIORITY
, end
->w7
);
1304 if (!xive_end_is_valid(end
)) {
1308 pq
= xive_get_field32(END_W1_ESn
, end
->w1
);
1310 monitor_printf(mon
, " %08x %c%c %c%c%c%c%c%c%c%c prio:%d nvt:%02x/%04x",
1312 pq
& XIVE_ESB_VAL_P
? 'P' : '-',
1313 pq
& XIVE_ESB_VAL_Q
? 'Q' : '-',
1314 xive_end_is_valid(end
) ? 'v' : '-',
1315 xive_end_is_enqueue(end
) ? 'q' : '-',
1316 xive_end_is_notify(end
) ? 'n' : '-',
1317 xive_end_is_backlog(end
) ? 'b' : '-',
1318 xive_end_is_escalate(end
) ? 'e' : '-',
1319 xive_end_is_uncond_escalation(end
) ? 'u' : '-',
1320 xive_end_is_silent_escalation(end
) ? 's' : '-',
1321 xive_end_is_firmware(end
) ? 'f' : '-',
1322 priority
, nvt_blk
, nvt_idx
);
1325 monitor_printf(mon
, " eq:@%08"PRIx64
"% 6d/%5d ^%d",
1326 qaddr_base
, qindex
, qentries
, qgen
);
1327 xive_end_queue_pic_print_info(end
, 6, mon
);
1329 monitor_printf(mon
, "\n");
1332 static void xive_end_enqueue(XiveEND
*end
, uint32_t data
)
1334 uint64_t qaddr_base
= xive_end_qaddr(end
);
1335 uint32_t qsize
= xive_get_field32(END_W0_QSIZE
, end
->w0
);
1336 uint32_t qindex
= xive_get_field32(END_W1_PAGE_OFF
, end
->w1
);
1337 uint32_t qgen
= xive_get_field32(END_W1_GENERATION
, end
->w1
);
1339 uint64_t qaddr
= qaddr_base
+ (qindex
<< 2);
1340 uint32_t qdata
= cpu_to_be32((qgen
<< 31) | (data
& 0x7fffffff));
1341 uint32_t qentries
= 1 << (qsize
+ 10);
1343 if (dma_memory_write(&address_space_memory
, qaddr
,
1344 &qdata
, sizeof(qdata
), MEMTXATTRS_UNSPECIFIED
)) {
1345 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: failed to write END data @0x%"
1346 HWADDR_PRIx
"\n", qaddr
);
1350 qindex
= (qindex
+ 1) & (qentries
- 1);
1353 end
->w1
= xive_set_field32(END_W1_GENERATION
, end
->w1
, qgen
);
1355 end
->w1
= xive_set_field32(END_W1_PAGE_OFF
, end
->w1
, qindex
);
1358 void xive_end_eas_pic_print_info(XiveEND
*end
, uint32_t end_idx
,
1361 XiveEAS
*eas
= (XiveEAS
*) &end
->w4
;
1364 if (!xive_end_is_escalate(end
)) {
1368 pq
= xive_get_field32(END_W1_ESe
, end
->w1
);
1370 monitor_printf(mon
, " %08x %c%c %c%c end:%02x/%04x data:%08x\n",
1372 pq
& XIVE_ESB_VAL_P
? 'P' : '-',
1373 pq
& XIVE_ESB_VAL_Q
? 'Q' : '-',
1374 xive_eas_is_valid(eas
) ? 'V' : ' ',
1375 xive_eas_is_masked(eas
) ? 'M' : ' ',
1376 (uint8_t) xive_get_field64(EAS_END_BLOCK
, eas
->w
),
1377 (uint32_t) xive_get_field64(EAS_END_INDEX
, eas
->w
),
1378 (uint32_t) xive_get_field64(EAS_END_DATA
, eas
->w
));
1382 * XIVE Router (aka. Virtualization Controller or IVRE)
1385 int xive_router_get_eas(XiveRouter
*xrtr
, uint8_t eas_blk
, uint32_t eas_idx
,
1388 XiveRouterClass
*xrc
= XIVE_ROUTER_GET_CLASS(xrtr
);
1390 return xrc
->get_eas(xrtr
, eas_blk
, eas_idx
, eas
);
1394 int xive_router_get_pq(XiveRouter
*xrtr
, uint8_t eas_blk
, uint32_t eas_idx
,
1397 XiveRouterClass
*xrc
= XIVE_ROUTER_GET_CLASS(xrtr
);
1399 return xrc
->get_pq(xrtr
, eas_blk
, eas_idx
, pq
);
1403 int xive_router_set_pq(XiveRouter
*xrtr
, uint8_t eas_blk
, uint32_t eas_idx
,
1406 XiveRouterClass
*xrc
= XIVE_ROUTER_GET_CLASS(xrtr
);
1408 return xrc
->set_pq(xrtr
, eas_blk
, eas_idx
, pq
);
1411 int xive_router_get_end(XiveRouter
*xrtr
, uint8_t end_blk
, uint32_t end_idx
,
1414 XiveRouterClass
*xrc
= XIVE_ROUTER_GET_CLASS(xrtr
);
1416 return xrc
->get_end(xrtr
, end_blk
, end_idx
, end
);
1419 int xive_router_write_end(XiveRouter
*xrtr
, uint8_t end_blk
, uint32_t end_idx
,
1420 XiveEND
*end
, uint8_t word_number
)
1422 XiveRouterClass
*xrc
= XIVE_ROUTER_GET_CLASS(xrtr
);
1424 return xrc
->write_end(xrtr
, end_blk
, end_idx
, end
, word_number
);
1427 int xive_router_get_nvt(XiveRouter
*xrtr
, uint8_t nvt_blk
, uint32_t nvt_idx
,
1430 XiveRouterClass
*xrc
= XIVE_ROUTER_GET_CLASS(xrtr
);
1432 return xrc
->get_nvt(xrtr
, nvt_blk
, nvt_idx
, nvt
);
1435 int xive_router_write_nvt(XiveRouter
*xrtr
, uint8_t nvt_blk
, uint32_t nvt_idx
,
1436 XiveNVT
*nvt
, uint8_t word_number
)
1438 XiveRouterClass
*xrc
= XIVE_ROUTER_GET_CLASS(xrtr
);
1440 return xrc
->write_nvt(xrtr
, nvt_blk
, nvt_idx
, nvt
, word_number
);
1443 static int xive_router_get_block_id(XiveRouter
*xrtr
)
1445 XiveRouterClass
*xrc
= XIVE_ROUTER_GET_CLASS(xrtr
);
1447 return xrc
->get_block_id(xrtr
);
1450 static void xive_router_realize(DeviceState
*dev
, Error
**errp
)
1452 XiveRouter
*xrtr
= XIVE_ROUTER(dev
);
1458 * Encode the HW CAM line in the block group mode format :
1460 * chip << 19 | 0000000 0 0001 thread (7Bit)
1462 static uint32_t xive_tctx_hw_cam_line(XivePresenter
*xptr
, XiveTCTX
*tctx
)
1464 CPUPPCState
*env
= &POWERPC_CPU(tctx
->cs
)->env
;
1465 uint32_t pir
= env
->spr_cb
[SPR_PIR
].default_value
;
1466 uint8_t blk
= xive_router_get_block_id(XIVE_ROUTER(xptr
));
1468 return xive_nvt_cam_line(blk
, 1 << 7 | (pir
& 0x7f));
1472 * The thread context register words are in big-endian format.
1474 int xive_presenter_tctx_match(XivePresenter
*xptr
, XiveTCTX
*tctx
,
1476 uint8_t nvt_blk
, uint32_t nvt_idx
,
1477 bool cam_ignore
, uint32_t logic_serv
)
1479 uint32_t cam
= xive_nvt_cam_line(nvt_blk
, nvt_idx
);
1480 uint32_t qw3w2
= xive_tctx_word2(&tctx
->regs
[TM_QW3_HV_PHYS
]);
1481 uint32_t qw2w2
= xive_tctx_word2(&tctx
->regs
[TM_QW2_HV_POOL
]);
1482 uint32_t qw1w2
= xive_tctx_word2(&tctx
->regs
[TM_QW1_OS
]);
1483 uint32_t qw0w2
= xive_tctx_word2(&tctx
->regs
[TM_QW0_USER
]);
1486 * TODO (PowerNV): ignore mode. The low order bits of the NVT
1487 * identifier are ignored in the "CAM" match.
1491 if (cam_ignore
== true) {
1493 * F=0 & i=1: Logical server notification (bits ignored at
1494 * the end of the NVT identifier)
1496 qemu_log_mask(LOG_UNIMP
, "XIVE: no support for LS NVT %x/%x\n",
1501 /* F=0 & i=0: Specific NVT notification */
1504 if ((be32_to_cpu(qw3w2
) & TM_QW3W2_VT
) &&
1505 cam
== xive_tctx_hw_cam_line(xptr
, tctx
)) {
1506 return TM_QW3_HV_PHYS
;
1510 if ((be32_to_cpu(qw2w2
) & TM_QW2W2_VP
) &&
1511 cam
== xive_get_field32(TM_QW2W2_POOL_CAM
, qw2w2
)) {
1512 return TM_QW2_HV_POOL
;
1516 if ((be32_to_cpu(qw1w2
) & TM_QW1W2_VO
) &&
1517 cam
== xive_get_field32(TM_QW1W2_OS_CAM
, qw1w2
)) {
1521 /* F=1 : User level Event-Based Branch (EBB) notification */
1524 if ((be32_to_cpu(qw1w2
) & TM_QW1W2_VO
) &&
1525 (cam
== xive_get_field32(TM_QW1W2_OS_CAM
, qw1w2
)) &&
1526 (be32_to_cpu(qw0w2
) & TM_QW0W2_VU
) &&
1527 (logic_serv
== xive_get_field32(TM_QW0W2_LOGIC_SERV
, qw0w2
))) {
1535 * This is our simple Xive Presenter Engine model. It is merged in the
1536 * Router as it does not require an extra object.
1538 * It receives notification requests sent by the IVRE to find one
1539 * matching NVT (or more) dispatched on the processor threads. In case
1540 * of a single NVT notification, the process is abreviated and the
1541 * thread is signaled if a match is found. In case of a logical server
1542 * notification (bits ignored at the end of the NVT identifier), the
1543 * IVPE and IVRE select a winning thread using different filters. This
1544 * involves 2 or 3 exchanges on the PowerBus that the model does not
1547 * The parameters represent what is sent on the PowerBus
1549 bool xive_presenter_notify(XiveFabric
*xfb
, uint8_t format
,
1550 uint8_t nvt_blk
, uint32_t nvt_idx
,
1551 bool cam_ignore
, uint8_t priority
,
1552 uint32_t logic_serv
)
1554 XiveFabricClass
*xfc
= XIVE_FABRIC_GET_CLASS(xfb
);
1555 XiveTCTXMatch match
= { .tctx
= NULL
, .ring
= 0 };
1559 * Ask the machine to scan the interrupt controllers for a match
1561 count
= xfc
->match_nvt(xfb
, format
, nvt_blk
, nvt_idx
, cam_ignore
,
1562 priority
, logic_serv
, &match
);
1567 /* handle CPU exception delivery */
1569 trace_xive_presenter_notify(nvt_blk
, nvt_idx
, match
.ring
);
1570 xive_tctx_ipb_update(match
.tctx
, match
.ring
,
1571 xive_priority_to_ipb(priority
));
1578 * Notification using the END ESe/ESn bit (Event State Buffer for
1579 * escalation and notification). Provide further coalescing in the
1582 static bool xive_router_end_es_notify(XiveRouter
*xrtr
, uint8_t end_blk
,
1583 uint32_t end_idx
, XiveEND
*end
,
1584 uint32_t end_esmask
)
1586 uint8_t pq
= xive_get_field32(end_esmask
, end
->w1
);
1587 bool notify
= xive_esb_trigger(&pq
);
1589 if (pq
!= xive_get_field32(end_esmask
, end
->w1
)) {
1590 end
->w1
= xive_set_field32(end_esmask
, end
->w1
, pq
);
1591 xive_router_write_end(xrtr
, end_blk
, end_idx
, end
, 1);
1594 /* ESe/n[Q]=1 : end of notification */
1599 * An END trigger can come from an event trigger (IPI or HW) or from
1600 * another chip. We don't model the PowerBus but the END trigger
1601 * message has the same parameters than in the function below.
1603 static void xive_router_end_notify(XiveRouter
*xrtr
, uint8_t end_blk
,
1604 uint32_t end_idx
, uint32_t end_data
)
1614 /* END cache lookup */
1615 if (xive_router_get_end(xrtr
, end_blk
, end_idx
, &end
)) {
1616 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: No END %x/%x\n", end_blk
,
1621 if (!xive_end_is_valid(&end
)) {
1622 trace_xive_router_end_notify(end_blk
, end_idx
, end_data
);
1623 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: END %x/%x is invalid\n",
1628 if (xive_end_is_enqueue(&end
)) {
1629 xive_end_enqueue(&end
, end_data
);
1630 /* Enqueuing event data modifies the EQ toggle and index */
1631 xive_router_write_end(xrtr
, end_blk
, end_idx
, &end
, 1);
1635 * When the END is silent, we skip the notification part.
1637 if (xive_end_is_silent_escalation(&end
)) {
1642 * The W7 format depends on the F bit in W6. It defines the type
1643 * of the notification :
1645 * F=0 : single or multiple NVT notification
1646 * F=1 : User level Event-Based Branch (EBB) notification, no
1649 format
= xive_get_field32(END_W6_FORMAT_BIT
, end
.w6
);
1650 priority
= xive_get_field32(END_W7_F0_PRIORITY
, end
.w7
);
1652 /* The END is masked */
1653 if (format
== 0 && priority
== 0xff) {
1658 * Check the END ESn (Event State Buffer for notification) for
1659 * even further coalescing in the Router
1661 if (!xive_end_is_notify(&end
)) {
1662 /* ESn[Q]=1 : end of notification */
1663 if (!xive_router_end_es_notify(xrtr
, end_blk
, end_idx
,
1664 &end
, END_W1_ESn
)) {
1670 * Follows IVPE notification
1672 nvt_blk
= xive_get_field32(END_W6_NVT_BLOCK
, end
.w6
);
1673 nvt_idx
= xive_get_field32(END_W6_NVT_INDEX
, end
.w6
);
1675 /* NVT cache lookup */
1676 if (xive_router_get_nvt(xrtr
, nvt_blk
, nvt_idx
, &nvt
)) {
1677 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: no NVT %x/%x\n",
1682 if (!xive_nvt_is_valid(&nvt
)) {
1683 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: NVT %x/%x is invalid\n",
1688 found
= xive_presenter_notify(xrtr
->xfb
, format
, nvt_blk
, nvt_idx
,
1689 xive_get_field32(END_W7_F0_IGNORE
, end
.w7
),
1691 xive_get_field32(END_W7_F1_LOG_SERVER_ID
, end
.w7
));
1693 /* TODO: Auto EOI. */
1700 * If no matching NVT is dispatched on a HW thread :
1701 * - specific VP: update the NVT structure if backlog is activated
1702 * - logical server : forward request to IVPE (not supported)
1704 if (xive_end_is_backlog(&end
)) {
1708 qemu_log_mask(LOG_GUEST_ERROR
,
1709 "XIVE: END %x/%x invalid config: F1 & backlog\n",
1714 * Record the IPB in the associated NVT structure for later
1715 * use. The presenter will resend the interrupt when the vCPU
1716 * is dispatched again on a HW thread.
1718 ipb
= xive_get_field32(NVT_W4_IPB
, nvt
.w4
) |
1719 xive_priority_to_ipb(priority
);
1720 nvt
.w4
= xive_set_field32(NVT_W4_IPB
, nvt
.w4
, ipb
);
1721 xive_router_write_nvt(xrtr
, nvt_blk
, nvt_idx
, &nvt
, 4);
1724 * On HW, follows a "Broadcast Backlog" to IVPEs
1730 * If activated, escalate notification using the ESe PQ bits and
1733 if (!xive_end_is_escalate(&end
)) {
1738 * Check the END ESe (Event State Buffer for escalation) for even
1739 * further coalescing in the Router
1741 if (!xive_end_is_uncond_escalation(&end
)) {
1742 /* ESe[Q]=1 : end of notification */
1743 if (!xive_router_end_es_notify(xrtr
, end_blk
, end_idx
,
1744 &end
, END_W1_ESe
)) {
1749 trace_xive_router_end_escalate(end_blk
, end_idx
,
1750 (uint8_t) xive_get_field32(END_W4_ESC_END_BLOCK
, end
.w4
),
1751 (uint32_t) xive_get_field32(END_W4_ESC_END_INDEX
, end
.w4
),
1752 (uint32_t) xive_get_field32(END_W5_ESC_END_DATA
, end
.w5
));
1754 * The END trigger becomes an Escalation trigger
1756 xive_router_end_notify(xrtr
,
1757 xive_get_field32(END_W4_ESC_END_BLOCK
, end
.w4
),
1758 xive_get_field32(END_W4_ESC_END_INDEX
, end
.w4
),
1759 xive_get_field32(END_W5_ESC_END_DATA
, end
.w5
));
1762 void xive_router_notify(XiveNotifier
*xn
, uint32_t lisn
, bool pq_checked
)
1764 XiveRouter
*xrtr
= XIVE_ROUTER(xn
);
1765 uint8_t eas_blk
= XIVE_EAS_BLOCK(lisn
);
1766 uint32_t eas_idx
= XIVE_EAS_INDEX(lisn
);
1769 /* EAS cache lookup */
1770 if (xive_router_get_eas(xrtr
, eas_blk
, eas_idx
, &eas
)) {
1771 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: Unknown LISN %x\n", lisn
);
1779 /* PQ cache lookup */
1780 if (xive_router_get_pq(xrtr
, eas_blk
, eas_idx
, &pq
)) {
1782 g_assert_not_reached();
1785 notify
= xive_esb_trigger(&pq
);
1787 if (xive_router_set_pq(xrtr
, eas_blk
, eas_idx
, &pq
)) {
1789 g_assert_not_reached();
1797 if (!xive_eas_is_valid(&eas
)) {
1798 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid LISN %x\n", lisn
);
1802 if (xive_eas_is_masked(&eas
)) {
1803 /* Notification completed */
1808 * The event trigger becomes an END trigger
1810 xive_router_end_notify(xrtr
,
1811 xive_get_field64(EAS_END_BLOCK
, eas
.w
),
1812 xive_get_field64(EAS_END_INDEX
, eas
.w
),
1813 xive_get_field64(EAS_END_DATA
, eas
.w
));
1816 static Property xive_router_properties
[] = {
1817 DEFINE_PROP_LINK("xive-fabric", XiveRouter
, xfb
,
1818 TYPE_XIVE_FABRIC
, XiveFabric
*),
1819 DEFINE_PROP_END_OF_LIST(),
1822 static void xive_router_class_init(ObjectClass
*klass
, void *data
)
1824 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1825 XiveNotifierClass
*xnc
= XIVE_NOTIFIER_CLASS(klass
);
1827 dc
->desc
= "XIVE Router Engine";
1828 device_class_set_props(dc
, xive_router_properties
);
1829 /* Parent is SysBusDeviceClass. No need to call its realize hook */
1830 dc
->realize
= xive_router_realize
;
1831 xnc
->notify
= xive_router_notify
;
1834 static const TypeInfo xive_router_info
= {
1835 .name
= TYPE_XIVE_ROUTER
,
1836 .parent
= TYPE_SYS_BUS_DEVICE
,
1838 .instance_size
= sizeof(XiveRouter
),
1839 .class_size
= sizeof(XiveRouterClass
),
1840 .class_init
= xive_router_class_init
,
1841 .interfaces
= (InterfaceInfo
[]) {
1842 { TYPE_XIVE_NOTIFIER
},
1843 { TYPE_XIVE_PRESENTER
},
1848 void xive_eas_pic_print_info(XiveEAS
*eas
, uint32_t lisn
, Monitor
*mon
)
1850 if (!xive_eas_is_valid(eas
)) {
1854 monitor_printf(mon
, " %08x %s end:%02x/%04x data:%08x\n",
1855 lisn
, xive_eas_is_masked(eas
) ? "M" : " ",
1856 (uint8_t) xive_get_field64(EAS_END_BLOCK
, eas
->w
),
1857 (uint32_t) xive_get_field64(EAS_END_INDEX
, eas
->w
),
1858 (uint32_t) xive_get_field64(EAS_END_DATA
, eas
->w
));
1862 * END ESB MMIO loads
1864 static uint64_t xive_end_source_read(void *opaque
, hwaddr addr
, unsigned size
)
1866 XiveENDSource
*xsrc
= XIVE_END_SOURCE(opaque
);
1867 uint32_t offset
= addr
& 0xFFF;
1871 uint32_t end_esmask
;
1876 * The block id should be deduced from the load address on the END
1877 * ESB MMIO but our model only supports a single block per XIVE chip.
1879 end_blk
= xive_router_get_block_id(xsrc
->xrtr
);
1880 end_idx
= addr
>> (xsrc
->esb_shift
+ 1);
1882 trace_xive_end_source_read(end_blk
, end_idx
, addr
);
1884 if (xive_router_get_end(xsrc
->xrtr
, end_blk
, end_idx
, &end
)) {
1885 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: No END %x/%x\n", end_blk
,
1890 if (!xive_end_is_valid(&end
)) {
1891 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: END %x/%x is invalid\n",
1896 end_esmask
= addr_is_even(addr
, xsrc
->esb_shift
) ? END_W1_ESn
: END_W1_ESe
;
1897 pq
= xive_get_field32(end_esmask
, end
.w1
);
1900 case XIVE_ESB_LOAD_EOI
... XIVE_ESB_LOAD_EOI
+ 0x7FF:
1901 ret
= xive_esb_eoi(&pq
);
1903 /* Forward the source event notification for routing ?? */
1906 case XIVE_ESB_GET
... XIVE_ESB_GET
+ 0x3FF:
1910 case XIVE_ESB_SET_PQ_00
... XIVE_ESB_SET_PQ_00
+ 0x0FF:
1911 case XIVE_ESB_SET_PQ_01
... XIVE_ESB_SET_PQ_01
+ 0x0FF:
1912 case XIVE_ESB_SET_PQ_10
... XIVE_ESB_SET_PQ_10
+ 0x0FF:
1913 case XIVE_ESB_SET_PQ_11
... XIVE_ESB_SET_PQ_11
+ 0x0FF:
1914 ret
= xive_esb_set(&pq
, (offset
>> 8) & 0x3);
1917 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid END ESB load addr %d\n",
1922 if (pq
!= xive_get_field32(end_esmask
, end
.w1
)) {
1923 end
.w1
= xive_set_field32(end_esmask
, end
.w1
, pq
);
1924 xive_router_write_end(xsrc
->xrtr
, end_blk
, end_idx
, &end
, 1);
1931 * END ESB MMIO stores are invalid
1933 static void xive_end_source_write(void *opaque
, hwaddr addr
,
1934 uint64_t value
, unsigned size
)
1936 qemu_log_mask(LOG_GUEST_ERROR
, "XIVE: invalid ESB write addr 0x%"
1937 HWADDR_PRIx
"\n", addr
);
1940 static const MemoryRegionOps xive_end_source_ops
= {
1941 .read
= xive_end_source_read
,
1942 .write
= xive_end_source_write
,
1943 .endianness
= DEVICE_BIG_ENDIAN
,
1945 .min_access_size
= 8,
1946 .max_access_size
= 8,
1949 .min_access_size
= 8,
1950 .max_access_size
= 8,
1954 static void xive_end_source_realize(DeviceState
*dev
, Error
**errp
)
1956 XiveENDSource
*xsrc
= XIVE_END_SOURCE(dev
);
1960 if (!xsrc
->nr_ends
) {
1961 error_setg(errp
, "Number of interrupt needs to be greater than 0");
1965 if (xsrc
->esb_shift
!= XIVE_ESB_4K
&&
1966 xsrc
->esb_shift
!= XIVE_ESB_64K
) {
1967 error_setg(errp
, "Invalid ESB shift setting");
1972 * Each END is assigned an even/odd pair of MMIO pages, the even page
1973 * manages the ESn field while the odd page manages the ESe field.
1975 memory_region_init_io(&xsrc
->esb_mmio
, OBJECT(xsrc
),
1976 &xive_end_source_ops
, xsrc
, "xive.end",
1977 (1ull << (xsrc
->esb_shift
+ 1)) * xsrc
->nr_ends
);
1980 static Property xive_end_source_properties
[] = {
1981 DEFINE_PROP_UINT32("nr-ends", XiveENDSource
, nr_ends
, 0),
1982 DEFINE_PROP_UINT32("shift", XiveENDSource
, esb_shift
, XIVE_ESB_64K
),
1983 DEFINE_PROP_LINK("xive", XiveENDSource
, xrtr
, TYPE_XIVE_ROUTER
,
1985 DEFINE_PROP_END_OF_LIST(),
1988 static void xive_end_source_class_init(ObjectClass
*klass
, void *data
)
1990 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1992 dc
->desc
= "XIVE END Source";
1993 device_class_set_props(dc
, xive_end_source_properties
);
1994 dc
->realize
= xive_end_source_realize
;
1996 * Reason: part of XIVE interrupt controller, needs to be wired up,
1997 * e.g. by spapr_xive_instance_init().
1999 dc
->user_creatable
= false;
2002 static const TypeInfo xive_end_source_info
= {
2003 .name
= TYPE_XIVE_END_SOURCE
,
2004 .parent
= TYPE_DEVICE
,
2005 .instance_size
= sizeof(XiveENDSource
),
2006 .class_init
= xive_end_source_class_init
,
2012 static const TypeInfo xive_notifier_info
= {
2013 .name
= TYPE_XIVE_NOTIFIER
,
2014 .parent
= TYPE_INTERFACE
,
2015 .class_size
= sizeof(XiveNotifierClass
),
2021 static const TypeInfo xive_presenter_info
= {
2022 .name
= TYPE_XIVE_PRESENTER
,
2023 .parent
= TYPE_INTERFACE
,
2024 .class_size
= sizeof(XivePresenterClass
),
2030 static const TypeInfo xive_fabric_info
= {
2031 .name
= TYPE_XIVE_FABRIC
,
2032 .parent
= TYPE_INTERFACE
,
2033 .class_size
= sizeof(XiveFabricClass
),
2036 static void xive_register_types(void)
2038 type_register_static(&xive_fabric_info
);
2039 type_register_static(&xive_source_info
);
2040 type_register_static(&xive_notifier_info
);
2041 type_register_static(&xive_presenter_info
);
2042 type_register_static(&xive_router_info
);
2043 type_register_static(&xive_end_source_info
);
2044 type_register_static(&xive_tctx_info
);
2047 type_init(xive_register_types
)