2 * ARM GICv3 emulation: Redistributor
4 * Copyright (c) 2015 Huawei.
5 * Copyright (c) 2016 Linaro Limited.
6 * Written by Shlomo Pongratz, Peter Maydell
8 * This code is licensed under the GPL, version 2 or (at your option)
12 #include "qemu/osdep.h"
15 #include "gicv3_internal.h"
17 static uint32_t mask_group(GICv3CPUState
*cs
, MemTxAttrs attrs
)
19 /* Return a 32-bit mask which should be applied for this set of 32
20 * interrupts; each bit is 1 if access is permitted by the
21 * combination of attrs.secure and GICR_GROUPR. (GICR_NSACR does
22 * not affect config register accesses, unlike GICD_NSACR.)
24 if (!attrs
.secure
&& !(cs
->gic
->gicd_ctlr
& GICD_CTLR_DS
)) {
25 /* bits for Group 0 or Secure Group 1 interrupts are RAZ/WI */
26 return cs
->gicr_igroupr0
;
31 static int gicr_ns_access(GICv3CPUState
*cs
, int irq
)
33 /* Return the 2 bit NSACR.NS_access field for this SGI */
35 return extract32(cs
->gicr_nsacr
, irq
* 2, 2);
38 static void gicr_write_set_bitmap_reg(GICv3CPUState
*cs
, MemTxAttrs attrs
,
39 uint32_t *reg
, uint32_t val
)
41 /* Helper routine to implement writing to a "set-bitmap" register */
42 val
&= mask_group(cs
, attrs
);
44 gicv3_redist_update(cs
);
47 static void gicr_write_clear_bitmap_reg(GICv3CPUState
*cs
, MemTxAttrs attrs
,
48 uint32_t *reg
, uint32_t val
)
50 /* Helper routine to implement writing to a "clear-bitmap" register */
51 val
&= mask_group(cs
, attrs
);
53 gicv3_redist_update(cs
);
56 static uint32_t gicr_read_bitmap_reg(GICv3CPUState
*cs
, MemTxAttrs attrs
,
59 reg
&= mask_group(cs
, attrs
);
63 static uint8_t gicr_read_ipriorityr(GICv3CPUState
*cs
, MemTxAttrs attrs
,
66 /* Read the value of GICR_IPRIORITYR<n> for the specified interrupt,
67 * honouring security state (these are RAZ/WI for Group 0 or Secure
68 * Group 1 interrupts).
72 prio
= cs
->gicr_ipriorityr
[irq
];
74 if (!attrs
.secure
&& !(cs
->gic
->gicd_ctlr
& GICD_CTLR_DS
)) {
75 if (!(cs
->gicr_igroupr0
& (1U << irq
))) {
76 /* Fields for Group 0 or Secure Group 1 interrupts are RAZ/WI */
79 /* NS view of the interrupt priority */
80 prio
= (prio
<< 1) & 0xff;
85 static void gicr_write_ipriorityr(GICv3CPUState
*cs
, MemTxAttrs attrs
, int irq
,
88 /* Write the value of GICD_IPRIORITYR<n> for the specified interrupt,
89 * honouring security state (these are RAZ/WI for Group 0 or Secure
90 * Group 1 interrupts).
92 if (!attrs
.secure
&& !(cs
->gic
->gicd_ctlr
& GICD_CTLR_DS
)) {
93 if (!(cs
->gicr_igroupr0
& (1U << irq
))) {
94 /* Fields for Group 0 or Secure Group 1 interrupts are RAZ/WI */
97 /* NS view of the interrupt priority */
98 value
= 0x80 | (value
>> 1);
100 cs
->gicr_ipriorityr
[irq
] = value
;
103 static MemTxResult
gicr_readb(GICv3CPUState
*cs
, hwaddr offset
,
104 uint64_t *data
, MemTxAttrs attrs
)
107 case GICR_IPRIORITYR
... GICR_IPRIORITYR
+ 0x1f:
108 *data
= gicr_read_ipriorityr(cs
, attrs
, offset
- GICR_IPRIORITYR
);
115 static MemTxResult
gicr_writeb(GICv3CPUState
*cs
, hwaddr offset
,
116 uint64_t value
, MemTxAttrs attrs
)
119 case GICR_IPRIORITYR
... GICR_IPRIORITYR
+ 0x1f:
120 gicr_write_ipriorityr(cs
, attrs
, offset
- GICR_IPRIORITYR
, value
);
121 gicv3_redist_update(cs
);
128 static MemTxResult
gicr_readl(GICv3CPUState
*cs
, hwaddr offset
,
129 uint64_t *data
, MemTxAttrs attrs
)
133 *data
= cs
->gicr_ctlr
;
136 *data
= gicv3_iidr();
139 *data
= extract64(cs
->gicr_typer
, 0, 32);
142 *data
= extract64(cs
->gicr_typer
, 32, 32);
145 /* RAZ/WI for us (this is an optional register and our implementation
146 * does not track RO/WO/reserved violations to report them to the guest)
151 *data
= cs
->gicr_waker
;
154 *data
= extract64(cs
->gicr_propbaser
, 0, 32);
156 case GICR_PROPBASER
+ 4:
157 *data
= extract64(cs
->gicr_propbaser
, 32, 32);
160 *data
= extract64(cs
->gicr_pendbaser
, 0, 32);
162 case GICR_PENDBASER
+ 4:
163 *data
= extract64(cs
->gicr_pendbaser
, 32, 32);
166 if (!attrs
.secure
&& !(cs
->gic
->gicd_ctlr
& GICD_CTLR_DS
)) {
170 *data
= cs
->gicr_igroupr0
;
172 case GICR_ISENABLER0
:
173 case GICR_ICENABLER0
:
174 *data
= gicr_read_bitmap_reg(cs
, attrs
, cs
->gicr_ienabler0
);
179 /* The pending register reads as the logical OR of the pending
180 * latch and the input line level for level-triggered interrupts.
182 uint32_t val
= cs
->gicr_ipendr0
| (~cs
->edge_trigger
& cs
->level
);
183 *data
= gicr_read_bitmap_reg(cs
, attrs
, val
);
186 case GICR_ISACTIVER0
:
187 case GICR_ICACTIVER0
:
188 *data
= gicr_read_bitmap_reg(cs
, attrs
, cs
->gicr_iactiver0
);
190 case GICR_IPRIORITYR
... GICR_IPRIORITYR
+ 0x1f:
192 int i
, irq
= offset
- GICR_IPRIORITYR
;
195 for (i
= irq
+ 3; i
>= irq
; i
--) {
197 value
|= gicr_read_ipriorityr(cs
, attrs
, i
);
205 /* Our edge_trigger bitmap is one bit per irq; take the correct
206 * half of it, and spread it out into the odd bits.
210 value
= cs
->edge_trigger
& mask_group(cs
, attrs
);
211 value
= extract32(value
, (offset
== GICR_ICFGR1
) ? 16 : 0, 16);
212 value
= half_shuffle32(value
) << 1;
217 if ((cs
->gic
->gicd_ctlr
& GICD_CTLR_DS
) || !attrs
.secure
) {
218 /* RAZ/WI if security disabled, or if
219 * security enabled and this is an NS access
224 *data
= cs
->gicr_igrpmodr0
;
227 if ((cs
->gic
->gicd_ctlr
& GICD_CTLR_DS
) || !attrs
.secure
) {
228 /* RAZ/WI if security disabled, or if
229 * security enabled and this is an NS access
234 *data
= cs
->gicr_nsacr
;
236 case GICR_IDREGS
... GICR_IDREGS
+ 0x2f:
237 *data
= gicv3_idreg(offset
- GICR_IDREGS
);
244 static MemTxResult
gicr_writel(GICv3CPUState
*cs
, hwaddr offset
,
245 uint64_t value
, MemTxAttrs attrs
)
249 /* For our implementation, GICR_TYPER.DPGS is 0 and so all
250 * the DPG bits are RAZ/WI. We don't do anything asynchronously,
251 * so UWP and RWP are RAZ/WI. GICR_TYPER.LPIS is 1 (we
252 * implement LPIs) so Enable_LPIs is programmable.
254 if (cs
->gicr_typer
& GICR_TYPER_PLPIS
) {
255 if (value
& GICR_CTLR_ENABLE_LPIS
) {
256 cs
->gicr_ctlr
|= GICR_CTLR_ENABLE_LPIS
;
257 /* Check for any pending interr in pending table */
258 gicv3_redist_update_lpi(cs
);
260 cs
->gicr_ctlr
&= ~GICR_CTLR_ENABLE_LPIS
;
261 /* cs->hppi might have been an LPI; recalculate */
262 gicv3_redist_update(cs
);
267 /* RAZ/WI for our implementation */
270 /* Only the ProcessorSleep bit is writeable. When the guest sets
271 * it it requests that we transition the channel between the
272 * redistributor and the cpu interface to quiescent, and that
273 * we set the ChildrenAsleep bit once the inteface has reached the
275 * Setting the ProcessorSleep to 0 reverses the quiescing, and
276 * ChildrenAsleep is cleared once the transition is complete.
277 * Since our interface is not asynchronous, we complete these
278 * transitions instantaneously, so we set ChildrenAsleep to the
279 * same value as ProcessorSleep here.
281 value
&= GICR_WAKER_ProcessorSleep
;
282 if (value
& GICR_WAKER_ProcessorSleep
) {
283 value
|= GICR_WAKER_ChildrenAsleep
;
285 cs
->gicr_waker
= value
;
288 cs
->gicr_propbaser
= deposit64(cs
->gicr_propbaser
, 0, 32, value
);
290 case GICR_PROPBASER
+ 4:
291 cs
->gicr_propbaser
= deposit64(cs
->gicr_propbaser
, 32, 32, value
);
294 cs
->gicr_pendbaser
= deposit64(cs
->gicr_pendbaser
, 0, 32, value
);
296 case GICR_PENDBASER
+ 4:
297 cs
->gicr_pendbaser
= deposit64(cs
->gicr_pendbaser
, 32, 32, value
);
300 if (!attrs
.secure
&& !(cs
->gic
->gicd_ctlr
& GICD_CTLR_DS
)) {
303 cs
->gicr_igroupr0
= value
;
304 gicv3_redist_update(cs
);
306 case GICR_ISENABLER0
:
307 gicr_write_set_bitmap_reg(cs
, attrs
, &cs
->gicr_ienabler0
, value
);
309 case GICR_ICENABLER0
:
310 gicr_write_clear_bitmap_reg(cs
, attrs
, &cs
->gicr_ienabler0
, value
);
313 gicr_write_set_bitmap_reg(cs
, attrs
, &cs
->gicr_ipendr0
, value
);
316 gicr_write_clear_bitmap_reg(cs
, attrs
, &cs
->gicr_ipendr0
, value
);
318 case GICR_ISACTIVER0
:
319 gicr_write_set_bitmap_reg(cs
, attrs
, &cs
->gicr_iactiver0
, value
);
321 case GICR_ICACTIVER0
:
322 gicr_write_clear_bitmap_reg(cs
, attrs
, &cs
->gicr_iactiver0
, value
);
324 case GICR_IPRIORITYR
... GICR_IPRIORITYR
+ 0x1f:
326 int i
, irq
= offset
- GICR_IPRIORITYR
;
328 for (i
= irq
; i
< irq
+ 4; i
++, value
>>= 8) {
329 gicr_write_ipriorityr(cs
, attrs
, i
, value
);
331 gicv3_redist_update(cs
);
335 /* Register is all RAZ/WI or RAO/WI bits */
341 /* Since our edge_trigger bitmap is one bit per irq, our input
342 * 32-bits will compress down into 16 bits which we need
343 * to write into the bitmap.
345 value
= half_unshuffle32(value
>> 1) << 16;
346 mask
= mask_group(cs
, attrs
) & 0xffff0000U
;
348 cs
->edge_trigger
&= ~mask
;
349 cs
->edge_trigger
|= (value
& mask
);
351 gicv3_redist_update(cs
);
355 if ((cs
->gic
->gicd_ctlr
& GICD_CTLR_DS
) || !attrs
.secure
) {
356 /* RAZ/WI if security disabled, or if
357 * security enabled and this is an NS access
361 cs
->gicr_igrpmodr0
= value
;
362 gicv3_redist_update(cs
);
365 if ((cs
->gic
->gicd_ctlr
& GICD_CTLR_DS
) || !attrs
.secure
) {
366 /* RAZ/WI if security disabled, or if
367 * security enabled and this is an NS access
371 cs
->gicr_nsacr
= value
;
372 /* no update required as this only affects access permission checks */
376 case GICR_IDREGS
... GICR_IDREGS
+ 0x2f:
377 /* RO registers, ignore the write */
378 qemu_log_mask(LOG_GUEST_ERROR
,
379 "%s: invalid guest write to RO register at offset "
380 TARGET_FMT_plx
"\n", __func__
, offset
);
387 static MemTxResult
gicr_readll(GICv3CPUState
*cs
, hwaddr offset
,
388 uint64_t *data
, MemTxAttrs attrs
)
392 *data
= cs
->gicr_typer
;
395 *data
= cs
->gicr_propbaser
;
398 *data
= cs
->gicr_pendbaser
;
405 static MemTxResult
gicr_writell(GICv3CPUState
*cs
, hwaddr offset
,
406 uint64_t value
, MemTxAttrs attrs
)
410 cs
->gicr_propbaser
= value
;
413 cs
->gicr_pendbaser
= value
;
416 /* RO register, ignore the write */
417 qemu_log_mask(LOG_GUEST_ERROR
,
418 "%s: invalid guest write to RO register at offset "
419 TARGET_FMT_plx
"\n", __func__
, offset
);
426 MemTxResult
gicv3_redist_read(void *opaque
, hwaddr offset
, uint64_t *data
,
427 unsigned size
, MemTxAttrs attrs
)
429 GICv3RedistRegion
*region
= opaque
;
430 GICv3State
*s
= region
->gic
;
435 assert((offset
& (size
- 1)) == 0);
438 * There are (for GICv3) two 64K redistributor pages per CPU.
439 * In some cases the redistributor pages for all CPUs are not
440 * contiguous (eg on the virt board they are split into two
441 * parts if there are too many CPUs to all fit in the same place
442 * in the memory map); if so then the GIC has multiple MemoryRegions
443 * for the redistributors.
445 cpuidx
= region
->cpuidx
+ offset
/ GICV3_REDIST_SIZE
;
446 offset
%= GICV3_REDIST_SIZE
;
448 cs
= &s
->cpu
[cpuidx
];
452 r
= gicr_readb(cs
, offset
, data
, attrs
);
455 r
= gicr_readl(cs
, offset
, data
, attrs
);
458 r
= gicr_readll(cs
, offset
, data
, attrs
);
466 qemu_log_mask(LOG_GUEST_ERROR
,
467 "%s: invalid guest read at offset " TARGET_FMT_plx
468 " size %u\n", __func__
, offset
, size
);
469 trace_gicv3_redist_badread(gicv3_redist_affid(cs
), offset
,
471 /* The spec requires that reserved registers are RAZ/WI;
472 * so use MEMTX_ERROR returns from leaf functions as a way to
473 * trigger the guest-error logging but don't return it to
474 * the caller, or we'll cause a spurious guest data abort.
479 trace_gicv3_redist_read(gicv3_redist_affid(cs
), offset
, *data
,
485 MemTxResult
gicv3_redist_write(void *opaque
, hwaddr offset
, uint64_t data
,
486 unsigned size
, MemTxAttrs attrs
)
488 GICv3RedistRegion
*region
= opaque
;
489 GICv3State
*s
= region
->gic
;
494 assert((offset
& (size
- 1)) == 0);
497 * There are (for GICv3) two 64K redistributor pages per CPU.
498 * In some cases the redistributor pages for all CPUs are not
499 * contiguous (eg on the virt board they are split into two
500 * parts if there are too many CPUs to all fit in the same place
501 * in the memory map); if so then the GIC has multiple MemoryRegions
502 * for the redistributors.
504 cpuidx
= region
->cpuidx
+ offset
/ GICV3_REDIST_SIZE
;
505 offset
%= GICV3_REDIST_SIZE
;
507 cs
= &s
->cpu
[cpuidx
];
511 r
= gicr_writeb(cs
, offset
, data
, attrs
);
514 r
= gicr_writel(cs
, offset
, data
, attrs
);
517 r
= gicr_writell(cs
, offset
, data
, attrs
);
525 qemu_log_mask(LOG_GUEST_ERROR
,
526 "%s: invalid guest write at offset " TARGET_FMT_plx
527 " size %u\n", __func__
, offset
, size
);
528 trace_gicv3_redist_badwrite(gicv3_redist_affid(cs
), offset
, data
,
530 /* The spec requires that reserved registers are RAZ/WI;
531 * so use MEMTX_ERROR returns from leaf functions as a way to
532 * trigger the guest-error logging but don't return it to
533 * the caller, or we'll cause a spurious guest data abort.
537 trace_gicv3_redist_write(gicv3_redist_affid(cs
), offset
, data
,
543 static void gicv3_redist_check_lpi_priority(GICv3CPUState
*cs
, int irq
)
545 AddressSpace
*as
= &cs
->gic
->dma_as
;
546 uint64_t lpict_baddr
;
550 lpict_baddr
= cs
->gicr_propbaser
& R_GICR_PROPBASER_PHYADDR_MASK
;
552 address_space_read(as
, lpict_baddr
+ ((irq
- GICV3_LPI_INTID_START
) *
553 sizeof(lpite
)), MEMTXATTRS_UNSPECIFIED
, &lpite
,
556 if (!(lpite
& LPI_CTE_ENABLED
)) {
560 if (cs
->gic
->gicd_ctlr
& GICD_CTLR_DS
) {
561 prio
= lpite
& LPI_PRIORITY_MASK
;
563 prio
= ((lpite
& LPI_PRIORITY_MASK
) >> 1) | 0x80;
566 if ((prio
< cs
->hpplpi
.prio
) ||
567 ((prio
== cs
->hpplpi
.prio
) && (irq
<= cs
->hpplpi
.irq
))) {
568 cs
->hpplpi
.irq
= irq
;
569 cs
->hpplpi
.prio
= prio
;
570 /* LPIs are always non-secure Grp1 interrupts */
571 cs
->hpplpi
.grp
= GICV3_G1NS
;
575 void gicv3_redist_update_lpi_only(GICv3CPUState
*cs
)
578 * This function scans the LPI pending table and for each pending
579 * LPI, reads the corresponding entry from LPI configuration table
580 * to extract the priority info and determine if the current LPI
581 * priority is lower than the last computed high priority lpi interrupt.
582 * If yes, replace current LPI as the new high priority lpi interrupt.
584 AddressSpace
*as
= &cs
->gic
->dma_as
;
585 uint64_t lpipt_baddr
;
586 uint32_t pendt_size
= 0;
591 idbits
= MIN(FIELD_EX64(cs
->gicr_propbaser
, GICR_PROPBASER
, IDBITS
),
594 if (!(cs
->gicr_ctlr
& GICR_CTLR_ENABLE_LPIS
)) {
598 cs
->hpplpi
.prio
= 0xff;
600 lpipt_baddr
= cs
->gicr_pendbaser
& R_GICR_PENDBASER_PHYADDR_MASK
;
602 /* Determine the highest priority pending interrupt among LPIs */
603 pendt_size
= (1ULL << (idbits
+ 1));
605 for (i
= GICV3_LPI_INTID_START
/ 8; i
< pendt_size
/ 8; i
++) {
606 address_space_read(as
, lpipt_baddr
+ i
, MEMTXATTRS_UNSPECIFIED
, &pend
,
611 gicv3_redist_check_lpi_priority(cs
, i
* 8 + bit
);
617 void gicv3_redist_update_lpi(GICv3CPUState
*cs
)
619 gicv3_redist_update_lpi_only(cs
);
620 gicv3_redist_update(cs
);
623 void gicv3_redist_lpi_pending(GICv3CPUState
*cs
, int irq
, int level
)
626 * This function updates the pending bit in lpi pending table for
627 * the irq being activated or deactivated.
629 AddressSpace
*as
= &cs
->gic
->dma_as
;
630 uint64_t lpipt_baddr
;
635 * get the bit value corresponding to this irq in the
638 lpipt_baddr
= cs
->gicr_pendbaser
& R_GICR_PENDBASER_PHYADDR_MASK
;
640 address_space_read(as
, lpipt_baddr
+ ((irq
/ 8) * sizeof(pend
)),
641 MEMTXATTRS_UNSPECIFIED
, &pend
, sizeof(pend
));
643 ispend
= extract32(pend
, irq
% 8, 1);
645 /* no change in the value of pending bit, return */
646 if (ispend
== level
) {
649 pend
= deposit32(pend
, irq
% 8, 1, level
? 1 : 0);
651 address_space_write(as
, lpipt_baddr
+ ((irq
/ 8) * sizeof(pend
)),
652 MEMTXATTRS_UNSPECIFIED
, &pend
, sizeof(pend
));
655 * check if this LPI is better than the current hpplpi, if yes
656 * just set hpplpi.prio and .irq without doing a full rescan
659 gicv3_redist_check_lpi_priority(cs
, irq
);
660 gicv3_redist_update(cs
);
662 if (irq
== cs
->hpplpi
.irq
) {
663 gicv3_redist_update_lpi(cs
);
668 void gicv3_redist_process_lpi(GICv3CPUState
*cs
, int irq
, int level
)
672 idbits
= MIN(FIELD_EX64(cs
->gicr_propbaser
, GICR_PROPBASER
, IDBITS
),
675 if (!(cs
->gicr_ctlr
& GICR_CTLR_ENABLE_LPIS
) ||
676 (irq
> (1ULL << (idbits
+ 1)) - 1) || irq
< GICV3_LPI_INTID_START
) {
680 /* set/clear the pending bit for this irq */
681 gicv3_redist_lpi_pending(cs
, irq
, level
);
684 void gicv3_redist_mov_lpi(GICv3CPUState
*src
, GICv3CPUState
*dest
, int irq
)
687 * Move the specified LPI's pending state from the source redistributor
688 * to the destination.
690 * If LPIs are disabled on dest this is CONSTRAINED UNPREDICTABLE:
691 * we choose to NOP. If LPIs are disabled on source there's nothing
692 * to be transferred anyway.
694 AddressSpace
*as
= &src
->gic
->dma_as
;
700 if (!(src
->gicr_ctlr
& GICR_CTLR_ENABLE_LPIS
) ||
701 !(dest
->gicr_ctlr
& GICR_CTLR_ENABLE_LPIS
)) {
705 idbits
= MIN(FIELD_EX64(src
->gicr_propbaser
, GICR_PROPBASER
, IDBITS
),
707 idbits
= MIN(FIELD_EX64(dest
->gicr_propbaser
, GICR_PROPBASER
, IDBITS
),
710 pendt_size
= 1ULL << (idbits
+ 1);
711 if ((irq
/ 8) >= pendt_size
) {
715 src_baddr
= src
->gicr_pendbaser
& R_GICR_PENDBASER_PHYADDR_MASK
;
717 address_space_read(as
, src_baddr
+ (irq
/ 8),
718 MEMTXATTRS_UNSPECIFIED
, &src_pend
, sizeof(src_pend
));
719 if (!extract32(src_pend
, irq
% 8, 1)) {
720 /* Not pending on source, nothing to do */
723 src_pend
&= ~(1 << (irq
% 8));
724 address_space_write(as
, src_baddr
+ (irq
/ 8),
725 MEMTXATTRS_UNSPECIFIED
, &src_pend
, sizeof(src_pend
));
726 if (irq
== src
->hpplpi
.irq
) {
728 * We just made this LPI not-pending so only need to update
729 * if it was previously the highest priority pending LPI
731 gicv3_redist_update_lpi(src
);
733 /* Mark it pending on the destination */
734 gicv3_redist_lpi_pending(dest
, irq
, 1);
737 void gicv3_redist_movall_lpis(GICv3CPUState
*src
, GICv3CPUState
*dest
)
740 * We must move all pending LPIs from the source redistributor
741 * to the destination. That is, for every pending LPI X on
742 * src, we must set it not-pending on src and pending on dest.
743 * LPIs that are already pending on dest are not cleared.
745 * If LPIs are disabled on dest this is CONSTRAINED UNPREDICTABLE:
746 * we choose to NOP. If LPIs are disabled on source there's nothing
747 * to be transferred anyway.
749 AddressSpace
*as
= &src
->gic
->dma_as
;
752 uint64_t src_baddr
, dest_baddr
;
755 if (!(src
->gicr_ctlr
& GICR_CTLR_ENABLE_LPIS
) ||
756 !(dest
->gicr_ctlr
& GICR_CTLR_ENABLE_LPIS
)) {
760 idbits
= MIN(FIELD_EX64(src
->gicr_propbaser
, GICR_PROPBASER
, IDBITS
),
762 idbits
= MIN(FIELD_EX64(dest
->gicr_propbaser
, GICR_PROPBASER
, IDBITS
),
765 pendt_size
= 1ULL << (idbits
+ 1);
766 src_baddr
= src
->gicr_pendbaser
& R_GICR_PENDBASER_PHYADDR_MASK
;
767 dest_baddr
= dest
->gicr_pendbaser
& R_GICR_PENDBASER_PHYADDR_MASK
;
769 for (i
= GICV3_LPI_INTID_START
/ 8; i
< pendt_size
/ 8; i
++) {
770 uint8_t src_pend
, dest_pend
;
772 address_space_read(as
, src_baddr
+ i
, MEMTXATTRS_UNSPECIFIED
,
773 &src_pend
, sizeof(src_pend
));
777 address_space_read(as
, dest_baddr
+ i
, MEMTXATTRS_UNSPECIFIED
,
778 &dest_pend
, sizeof(dest_pend
));
779 dest_pend
|= src_pend
;
781 address_space_write(as
, src_baddr
+ i
, MEMTXATTRS_UNSPECIFIED
,
782 &src_pend
, sizeof(src_pend
));
783 address_space_write(as
, dest_baddr
+ i
, MEMTXATTRS_UNSPECIFIED
,
784 &dest_pend
, sizeof(dest_pend
));
787 gicv3_redist_update_lpi(src
);
788 gicv3_redist_update_lpi(dest
);
791 void gicv3_redist_set_irq(GICv3CPUState
*cs
, int irq
, int level
)
793 /* Update redistributor state for a change in an external PPI input line */
794 if (level
== extract32(cs
->level
, irq
, 1)) {
798 trace_gicv3_redist_set_irq(gicv3_redist_affid(cs
), irq
, level
);
800 cs
->level
= deposit32(cs
->level
, irq
, 1, level
);
803 /* 0->1 edges latch the pending bit for edge-triggered interrupts */
804 if (extract32(cs
->edge_trigger
, irq
, 1)) {
805 cs
->gicr_ipendr0
= deposit32(cs
->gicr_ipendr0
, irq
, 1, 1);
809 gicv3_redist_update(cs
);
812 void gicv3_redist_send_sgi(GICv3CPUState
*cs
, int grp
, int irq
, bool ns
)
814 /* Update redistributor state for a generated SGI */
815 int irqgrp
= gicv3_irq_group(cs
->gic
, cs
, irq
);
817 /* If we are asked for a Secure Group 1 SGI and it's actually
818 * configured as Secure Group 0 this is OK (subject to the usual
821 if (grp
== GICV3_G1
&& irqgrp
== GICV3_G0
) {
829 if (ns
&& !(cs
->gic
->gicd_ctlr
& GICD_CTLR_DS
)) {
830 /* If security is enabled we must test the NSACR bits */
831 int nsaccess
= gicr_ns_access(cs
, irq
);
833 if ((irqgrp
== GICV3_G0
&& nsaccess
< 1) ||
834 (irqgrp
== GICV3_G1
&& nsaccess
< 2)) {
839 /* OK, we can accept the SGI */
840 trace_gicv3_redist_send_sgi(gicv3_redist_affid(cs
), irq
);
841 cs
->gicr_ipendr0
= deposit32(cs
->gicr_ipendr0
, irq
, 1, 1);
842 gicv3_redist_update(cs
);