hw/xio3130_downstream.c

   1 /*
   2  * x3130_downstream.c
   3  * TI X3130 pci express downstream port switch
   4  *
   5  * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
   6  *                    VA Linux Systems Japan K.K.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License along
  19  * with this program; if not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include "pci_ids.h"
  23 #include "msi.h"
  24 #include "pcie.h"
  25 #include "xio3130_downstream.h"
  26
  27 #define PCI_DEVICE_ID_TI_XIO3130D       0x8233  /* downstream port */
  28 #define XIO3130_REVISION                0x1
  29 #define XIO3130_MSI_OFFSET              0x70
  30 #define XIO3130_MSI_SUPPORTED_FLAGS     PCI_MSI_FLAGS_64BIT
  31 #define XIO3130_MSI_NR_VECTOR           1
  32 #define XIO3130_SSVID_OFFSET            0x80
  33 #define XIO3130_SSVID_SVID              0
  34 #define XIO3130_SSVID_SSID              0
  35 #define XIO3130_EXP_OFFSET              0x90
  36 #define XIO3130_AER_OFFSET              0x100
  37
  38 static void xio3130_downstream_write_config(PCIDevice *d, uint32_t address,
  39                                          uint32_t val, int len)
  40 {
  41     uint16_t sltctl =
  42         pci_get_word(d->config + d->exp.exp_cap + PCI_EXP_SLTCTL);
  43
  44     pci_bridge_write_config(d, address, val, len);
  45     pcie_cap_flr_write_config(d, address, val, len);
  46     pcie_cap_slot_write_config(d, address, val, len, sltctl);
  47     msi_write_config(d, address, val, len);
  48     /* TODO: AER */
  49 }
  50
  51 static void xio3130_downstream_reset(DeviceState *qdev)
  52 {
  53     PCIDevice *d = DO_UPCAST(PCIDevice, qdev, qdev);
  54     msi_reset(d);
  55     pcie_cap_deverr_reset(d);
  56     pcie_cap_slot_reset(d);
  57     pcie_cap_ari_reset(d);
  58     pci_bridge_reset(qdev);
  59 }
  60
  61 static int xio3130_downstream_initfn(PCIDevice *d)
  62 {
  63     PCIBridge* br = DO_UPCAST(PCIBridge, dev, d);
  64     PCIEPort *p = DO_UPCAST(PCIEPort, br, br);
  65     PCIESlot *s = DO_UPCAST(PCIESlot, port, p);
  66     int rc;
  67
  68     rc = pci_bridge_initfn(d);
  69     if (rc < 0) {
  70         return rc;
  71     }
  72
  73     pcie_port_init_reg(d);
  74     pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_TI);
  75     pci_config_set_device_id(d->config, PCI_DEVICE_ID_TI_XIO3130D);
  76     d->config[PCI_REVISION_ID] = XIO3130_REVISION;
  77
  78     rc = msi_init(d, XIO3130_MSI_OFFSET, XIO3130_MSI_NR_VECTOR,
  79                   XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT,
  80                   XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT);
  81     if (rc < 0) {
  82         return rc;
  83     }
  84     rc = pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET,
  85                                XIO3130_SSVID_SVID, XIO3130_SSVID_SSID);
  86     if (rc < 0) {
  87         return rc;
  88     }
  89     rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_DOWNSTREAM,
  90                        p->port);
  91     if (rc < 0) {
  92         return rc;
  93     }
  94     pcie_cap_flr_init(d);       /* TODO: implement FLR */
  95     pcie_cap_deverr_init(d);
  96     pcie_cap_slot_init(d, s->slot);
  97     pcie_chassis_create(s->chassis);
  98     rc = pcie_chassis_add_slot(s);
  99     if (rc < 0) {
 100         return rc;
 101     }
 102     pcie_cap_ari_init(d);
 103     /* TODO: AER */
 104
 105     return 0;
 106 }
 107
 108 static int xio3130_downstream_exitfn(PCIDevice *d)
 109 {
 110     /* TODO: AER */
 111     msi_uninit(d);
 112     pcie_cap_exit(d);
 113     return pci_bridge_exitfn(d);
 114 }
 115
 116 PCIESlot *xio3130_downstream_init(PCIBus *bus, int devfn, bool multifunction,
 117                                   const char *bus_name, pci_map_irq_fn map_irq,
 118                                   uint8_t port, uint8_t chassis,
 119                                   uint16_t slot)
 120 {
 121     PCIDevice *d;
 122     PCIBridge *br;
 123     DeviceState *qdev;
 124
 125     d = pci_create_multifunction(bus, devfn, multifunction,
 126                                  "xio3130-downstream");
 127     if (!d) {
 128         return NULL;
 129     }
 130     br = DO_UPCAST(PCIBridge, dev, d);
 131
 132     qdev = &br->dev.qdev;
 133     pci_bridge_map_irq(br, bus_name, map_irq);
 134     qdev_prop_set_uint8(qdev, "port", port);
 135     qdev_prop_set_uint8(qdev, "chassis", chassis);
 136     qdev_prop_set_uint16(qdev, "slot", slot);
 137     qdev_init_nofail(qdev);
 138
 139     return DO_UPCAST(PCIESlot, port, DO_UPCAST(PCIEPort, br, br));
 140 }
 141
 142 static const VMStateDescription vmstate_xio3130_downstream = {
 143     .name = "xio3130-express-downstream-port",
 144     .version_id = 1,
 145     .minimum_version_id = 1,
 146     .minimum_version_id_old = 1,
 147     .fields = (VMStateField[]) {
 148         VMSTATE_PCIE_DEVICE(port.br.dev, PCIESlot),
 149         /* TODO: AER */
 150         VMSTATE_END_OF_LIST()
 151     }
 152 };
 153
 154 static PCIDeviceInfo xio3130_downstream_info = {
 155     .qdev.name = "xio3130-downstream",
 156     .qdev.desc = "TI X3130 Downstream Port of PCI Express Switch",
 157     .qdev.size = sizeof(PCIESlot),
 158     .qdev.reset = xio3130_downstream_reset,
 159     .qdev.vmsd = &vmstate_xio3130_downstream,
 160
 161     .is_express = 1,
 162     .is_bridge = 1,
 163     .config_write = xio3130_downstream_write_config,
 164     .init = xio3130_downstream_initfn,
 165     .exit = xio3130_downstream_exitfn,
 166
 167     .qdev.props = (Property[]) {
 168         DEFINE_PROP_UINT8("port", PCIESlot, port.port, 0),
 169         DEFINE_PROP_UINT8("chassis", PCIESlot, chassis, 0),
 170         DEFINE_PROP_UINT16("slot", PCIESlot, slot, 0),
 171         /* TODO: AER */
 172         DEFINE_PROP_END_OF_LIST(),
 173     }
 174 };
 175
 176 static void xio3130_downstream_register(void)
 177 {
 178     pci_qdev_register(&xio3130_downstream_info);
 179 }
 180
 181 device_init(xio3130_downstream_register);
 182
 183 /*
 184  * Local variables:
 185  *  c-indent-level: 4
 186  *  c-basic-offset: 4
 187  *  tab-width: 8
 188  *  indent-tab-mode: nil
 189  * End:
 190  */