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block: Use blk_co_ioctl() for all BB level ioctls
[qemu.git] / target-m68k / translate.c
blob6c6173a09ed443c21d4cd93d83f4022f25714ff0
1 /*
2 * m68k translation
3 *
4 * Copyright (c) 2005-2007 CodeSourcery
5 * Written by Paul Brook
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "cpu.h"
23 #include "disas/disas.h"
24 #include "exec/exec-all.h"
25 #include "tcg-op.h"
26 #include "qemu/log.h"
27 #include "exec/cpu_ldst.h"
28
29 #include "exec/helper-proto.h"
30 #include "exec/helper-gen.h"
31
32 #include "trace-tcg.h"
33 #include "exec/log.h"
34
35
36 //#define DEBUG_DISPATCH 1
37
38 /* Fake floating point. */
39 #define tcg_gen_mov_f64 tcg_gen_mov_i64
40 #define tcg_gen_qemu_ldf64 tcg_gen_qemu_ld64
41 #define tcg_gen_qemu_stf64 tcg_gen_qemu_st64
42
43 #define DEFO32(name, offset) static TCGv QREG_##name;
44 #define DEFO64(name, offset) static TCGv_i64 QREG_##name;
45 #define DEFF64(name, offset) static TCGv_i64 QREG_##name;
46 #include "qregs.def"
47 #undef DEFO32
48 #undef DEFO64
49 #undef DEFF64
50
51 static TCGv_i32 cpu_halted;
52 static TCGv_i32 cpu_exception_index;
53
54 static TCGv_env cpu_env;
55
56 static char cpu_reg_names[3*8*3 + 5*4];
57 static TCGv cpu_dregs[8];
58 static TCGv cpu_aregs[8];
59 static TCGv_i64 cpu_fregs[8];
60 static TCGv_i64 cpu_macc[4];
61
62 #define REG(insn, pos) (((insn) >> (pos)) & 7)
63 #define DREG(insn, pos) cpu_dregs[REG(insn, pos)]
64 #define AREG(insn, pos) cpu_aregs[REG(insn, pos)]
65 #define FREG(insn, pos) cpu_fregs[REG(insn, pos)]
66 #define MACREG(acc) cpu_macc[acc]
67 #define QREG_SP cpu_aregs[7]
68
69 static TCGv NULL_QREG;
70 #define IS_NULL_QREG(t) (TCGV_EQUAL(t, NULL_QREG))
71 /* Used to distinguish stores from bad addressing modes. */
72 static TCGv store_dummy;
73
74 #include "exec/gen-icount.h"
75
76 void m68k_tcg_init(void)
77 {
78 char *p;
79 int i;
80
81 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
82 tcg_ctx.tcg_env = cpu_env;
83
84 #define DEFO32(name, offset) \
85 QREG_##name = tcg_global_mem_new_i32(cpu_env, \
86 offsetof(CPUM68KState, offset), #name);
87 #define DEFO64(name, offset) \
88 QREG_##name = tcg_global_mem_new_i64(cpu_env, \
89 offsetof(CPUM68KState, offset), #name);
90 #define DEFF64(name, offset) DEFO64(name, offset)
91 #include "qregs.def"
92 #undef DEFO32
93 #undef DEFO64
94 #undef DEFF64
95
96 cpu_halted = tcg_global_mem_new_i32(cpu_env,
97 -offsetof(M68kCPU, env) +
98 offsetof(CPUState, halted), "HALTED");
99 cpu_exception_index = tcg_global_mem_new_i32(cpu_env,
100 -offsetof(M68kCPU, env) +
101 offsetof(CPUState, exception_index),
102 "EXCEPTION");
103
104 p = cpu_reg_names;
105 for (i = 0; i < 8; i++) {
106 sprintf(p, "D%d", i);
107 cpu_dregs[i] = tcg_global_mem_new(cpu_env,
108 offsetof(CPUM68KState, dregs[i]), p);
109 p += 3;
110 sprintf(p, "A%d", i);
111 cpu_aregs[i] = tcg_global_mem_new(cpu_env,
112 offsetof(CPUM68KState, aregs[i]), p);
113 p += 3;
114 sprintf(p, "F%d", i);
115 cpu_fregs[i] = tcg_global_mem_new_i64(cpu_env,
116 offsetof(CPUM68KState, fregs[i]), p);
117 p += 3;
118 }
119 for (i = 0; i < 4; i++) {
120 sprintf(p, "ACC%d", i);
121 cpu_macc[i] = tcg_global_mem_new_i64(cpu_env,
122 offsetof(CPUM68KState, macc[i]), p);
123 p += 5;
124 }
125
126 NULL_QREG = tcg_global_mem_new(cpu_env, -4, "NULL");
127 store_dummy = tcg_global_mem_new(cpu_env, -8, "NULL");
128 }
129
130 /* internal defines */
131 typedef struct DisasContext {
132 CPUM68KState *env;
133 target_ulong insn_pc; /* Start of the current instruction. */
134 target_ulong pc;
135 int is_jmp;
136 CCOp cc_op; /* Current CC operation */
137 int cc_op_synced;
138 int user;
139 uint32_t fpcr;
140 struct TranslationBlock *tb;
141 int singlestep_enabled;
142 TCGv_i64 mactmp;
143 int done_mac;
144 } DisasContext;
145
146 #define DISAS_JUMP_NEXT 4
147
148 #if defined(CONFIG_USER_ONLY)
149 #define IS_USER(s) 1
150 #else
151 #define IS_USER(s) s->user
152 #endif
153
154 /* XXX: move that elsewhere */
155 /* ??? Fix exceptions. */
156 static void *gen_throws_exception;
157 #define gen_last_qop NULL
158
159 typedef void (*disas_proc)(CPUM68KState *env, DisasContext *s, uint16_t insn);
160
161 #ifdef DEBUG_DISPATCH
162 #define DISAS_INSN(name) \
163 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
164 uint16_t insn); \
165 static void disas_##name(CPUM68KState *env, DisasContext *s, \
166 uint16_t insn) \
167 { \
168 qemu_log("Dispatch " #name "\n"); \
169 real_disas_##name(env, s, insn); \
170 } \
171 static void real_disas_##name(CPUM68KState *env, DisasContext *s, \
172 uint16_t insn)
173 #else
174 #define DISAS_INSN(name) \
175 static void disas_##name(CPUM68KState *env, DisasContext *s, \
176 uint16_t insn)
177 #endif
178
179 static const uint8_t cc_op_live[CC_OP_NB] = {
180 [CC_OP_FLAGS] = CCF_C | CCF_V | CCF_Z | CCF_N | CCF_X,
181 [CC_OP_ADD] = CCF_X | CCF_N | CCF_V,
182 [CC_OP_SUB] = CCF_X | CCF_N | CCF_V,
183 [CC_OP_CMP] = CCF_X | CCF_N | CCF_V,
184 [CC_OP_LOGIC] = CCF_X | CCF_N
185 };
186
187 static void set_cc_op(DisasContext *s, CCOp op)
188 {
189 CCOp old_op = s->cc_op;
190 int dead;
191
192 if (old_op == op) {
193 return;
194 }
195 s->cc_op = op;
196 s->cc_op_synced = 0;
197
198 /* Discard CC computation that will no longer be used.
199 Note that X and N are never dead. */
200 dead = cc_op_live[old_op] & ~cc_op_live[op];
201 if (dead & CCF_C) {
202 tcg_gen_discard_i32(QREG_CC_C);
203 }
204 if (dead & CCF_Z) {
205 tcg_gen_discard_i32(QREG_CC_Z);
206 }
207 if (dead & CCF_V) {
208 tcg_gen_discard_i32(QREG_CC_V);
209 }
210 }
211
212 /* Update the CPU env CC_OP state. */
213 static void update_cc_op(DisasContext *s)
214 {
215 if (!s->cc_op_synced) {
216 s->cc_op_synced = 1;
217 tcg_gen_movi_i32(QREG_CC_OP, s->cc_op);
218 }
219 }
220
221 /* Generate a load from the specified address. Narrow values are
222 sign extended to full register width. */
223 static inline TCGv gen_load(DisasContext * s, int opsize, TCGv addr, int sign)
224 {
225 TCGv tmp;
226 int index = IS_USER(s);
227 tmp = tcg_temp_new_i32();
228 switch(opsize) {
229 case OS_BYTE:
230 if (sign)
231 tcg_gen_qemu_ld8s(tmp, addr, index);
232 else
233 tcg_gen_qemu_ld8u(tmp, addr, index);
234 break;
235 case OS_WORD:
236 if (sign)
237 tcg_gen_qemu_ld16s(tmp, addr, index);
238 else
239 tcg_gen_qemu_ld16u(tmp, addr, index);
240 break;
241 case OS_LONG:
242 case OS_SINGLE:
243 tcg_gen_qemu_ld32u(tmp, addr, index);
244 break;
245 default:
246 g_assert_not_reached();
247 }
248 gen_throws_exception = gen_last_qop;
249 return tmp;
250 }
251
252 static inline TCGv_i64 gen_load64(DisasContext * s, TCGv addr)
253 {
254 TCGv_i64 tmp;
255 int index = IS_USER(s);
256 tmp = tcg_temp_new_i64();
257 tcg_gen_qemu_ldf64(tmp, addr, index);
258 gen_throws_exception = gen_last_qop;
259 return tmp;
260 }
261
262 /* Generate a store. */
263 static inline void gen_store(DisasContext *s, int opsize, TCGv addr, TCGv val)
264 {
265 int index = IS_USER(s);
266 switch(opsize) {
267 case OS_BYTE:
268 tcg_gen_qemu_st8(val, addr, index);
269 break;
270 case OS_WORD:
271 tcg_gen_qemu_st16(val, addr, index);
272 break;
273 case OS_LONG:
274 case OS_SINGLE:
275 tcg_gen_qemu_st32(val, addr, index);
276 break;
277 default:
278 g_assert_not_reached();
279 }
280 gen_throws_exception = gen_last_qop;
281 }
282
283 static inline void gen_store64(DisasContext *s, TCGv addr, TCGv_i64 val)
284 {
285 int index = IS_USER(s);
286 tcg_gen_qemu_stf64(val, addr, index);
287 gen_throws_exception = gen_last_qop;
288 }
289
290 typedef enum {
291 EA_STORE,
292 EA_LOADU,
293 EA_LOADS
294 } ea_what;
295
296 /* Generate an unsigned load if VAL is 0 a signed load if val is -1,
297 otherwise generate a store. */
298 static TCGv gen_ldst(DisasContext *s, int opsize, TCGv addr, TCGv val,
299 ea_what what)
300 {
301 if (what == EA_STORE) {
302 gen_store(s, opsize, addr, val);
303 return store_dummy;
304 } else {
305 return gen_load(s, opsize, addr, what == EA_LOADS);
306 }
307 }
308
309 /* Read a 16-bit immediate constant */
310 static inline uint16_t read_im16(CPUM68KState *env, DisasContext *s)
311 {
312 uint16_t im;
313 im = cpu_lduw_code(env, s->pc);
314 s->pc += 2;
315 return im;
316 }
317
318 /* Read an 8-bit immediate constant */
319 static inline uint8_t read_im8(CPUM68KState *env, DisasContext *s)
320 {
321 return read_im16(env, s);
322 }
323
324 /* Read a 32-bit immediate constant. */
325 static inline uint32_t read_im32(CPUM68KState *env, DisasContext *s)
326 {
327 uint32_t im;
328 im = read_im16(env, s) << 16;
329 im |= 0xffff & read_im16(env, s);
330 return im;
331 }
332
333 /* Calculate and address index. */
334 static TCGv gen_addr_index(uint16_t ext, TCGv tmp)
335 {
336 TCGv add;
337 int scale;
338
339 add = (ext & 0x8000) ? AREG(ext, 12) : DREG(ext, 12);
340 if ((ext & 0x800) == 0) {
341 tcg_gen_ext16s_i32(tmp, add);
342 add = tmp;
343 }
344 scale = (ext >> 9) & 3;
345 if (scale != 0) {
346 tcg_gen_shli_i32(tmp, add, scale);
347 add = tmp;
348 }
349 return add;
350 }
351
352 /* Handle a base + index + displacement effective addresss.
353 A NULL_QREG base means pc-relative. */
354 static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, TCGv base)
355 {
356 uint32_t offset;
357 uint16_t ext;
358 TCGv add;
359 TCGv tmp;
360 uint32_t bd, od;
361
362 offset = s->pc;
363 ext = read_im16(env, s);
364
365 if ((ext & 0x800) == 0 && !m68k_feature(s->env, M68K_FEATURE_WORD_INDEX))
366 return NULL_QREG;
367
368 if (m68k_feature(s->env, M68K_FEATURE_M68000) &&
369 !m68k_feature(s->env, M68K_FEATURE_SCALED_INDEX)) {
370 ext &= ~(3 << 9);
371 }
372
373 if (ext & 0x100) {
374 /* full extension word format */
375 if (!m68k_feature(s->env, M68K_FEATURE_EXT_FULL))
376 return NULL_QREG;
377
378 if ((ext & 0x30) > 0x10) {
379 /* base displacement */
380 if ((ext & 0x30) == 0x20) {
381 bd = (int16_t)read_im16(env, s);
382 } else {
383 bd = read_im32(env, s);
384 }
385 } else {
386 bd = 0;
387 }
388 tmp = tcg_temp_new();
389 if ((ext & 0x44) == 0) {
390 /* pre-index */
391 add = gen_addr_index(ext, tmp);
392 } else {
393 add = NULL_QREG;
394 }
395 if ((ext & 0x80) == 0) {
396 /* base not suppressed */
397 if (IS_NULL_QREG(base)) {
398 base = tcg_const_i32(offset + bd);
399 bd = 0;
400 }
401 if (!IS_NULL_QREG(add)) {
402 tcg_gen_add_i32(tmp, add, base);
403 add = tmp;
404 } else {
405 add = base;
406 }
407 }
408 if (!IS_NULL_QREG(add)) {
409 if (bd != 0) {
410 tcg_gen_addi_i32(tmp, add, bd);
411 add = tmp;
412 }
413 } else {
414 add = tcg_const_i32(bd);
415 }
416 if ((ext & 3) != 0) {
417 /* memory indirect */
418 base = gen_load(s, OS_LONG, add, 0);
419 if ((ext & 0x44) == 4) {
420 add = gen_addr_index(ext, tmp);
421 tcg_gen_add_i32(tmp, add, base);
422 add = tmp;
423 } else {
424 add = base;
425 }
426 if ((ext & 3) > 1) {
427 /* outer displacement */
428 if ((ext & 3) == 2) {
429 od = (int16_t)read_im16(env, s);
430 } else {
431 od = read_im32(env, s);
432 }
433 } else {
434 od = 0;
435 }
436 if (od != 0) {
437 tcg_gen_addi_i32(tmp, add, od);
438 add = tmp;
439 }
440 }
441 } else {
442 /* brief extension word format */
443 tmp = tcg_temp_new();
444 add = gen_addr_index(ext, tmp);
445 if (!IS_NULL_QREG(base)) {
446 tcg_gen_add_i32(tmp, add, base);
447 if ((int8_t)ext)
448 tcg_gen_addi_i32(tmp, tmp, (int8_t)ext);
449 } else {
450 tcg_gen_addi_i32(tmp, add, offset + (int8_t)ext);
451 }
452 add = tmp;
453 }
454 return add;
455 }
456
457 /* Evaluate all the CC flags. */
458
459 static void gen_flush_flags(DisasContext *s)
460 {
461 TCGv t0, t1;
462
463 switch (s->cc_op) {
464 case CC_OP_FLAGS:
465 return;
466
467 case CC_OP_ADD:
468 tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X);
469 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
470 /* Compute signed overflow for addition. */
471 t0 = tcg_temp_new();
472 t1 = tcg_temp_new();
473 tcg_gen_sub_i32(t0, QREG_CC_N, QREG_CC_V);
474 tcg_gen_xor_i32(t1, QREG_CC_N, QREG_CC_V);
475 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_V, t0);
476 tcg_temp_free(t0);
477 tcg_gen_andc_i32(QREG_CC_V, t1, QREG_CC_V);
478 tcg_temp_free(t1);
479 break;
480
481 case CC_OP_SUB:
482 tcg_gen_mov_i32(QREG_CC_C, QREG_CC_X);
483 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
484 /* Compute signed overflow for subtraction. */
485 t0 = tcg_temp_new();
486 t1 = tcg_temp_new();
487 tcg_gen_add_i32(t0, QREG_CC_N, QREG_CC_V);
488 tcg_gen_xor_i32(t1, QREG_CC_N, QREG_CC_V);
489 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_V, t0);
490 tcg_temp_free(t0);
491 tcg_gen_and_i32(QREG_CC_V, QREG_CC_V, t1);
492 tcg_temp_free(t1);
493 break;
494
495 case CC_OP_CMP:
496 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_C, QREG_CC_N, QREG_CC_V);
497 tcg_gen_sub_i32(QREG_CC_Z, QREG_CC_N, QREG_CC_V);
498 /* Compute signed overflow for subtraction. */
499 t0 = tcg_temp_new();
500 tcg_gen_xor_i32(t0, QREG_CC_Z, QREG_CC_N);
501 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_V, QREG_CC_N);
502 tcg_gen_and_i32(QREG_CC_V, QREG_CC_V, t0);
503 tcg_temp_free(t0);
504 tcg_gen_mov_i32(QREG_CC_N, QREG_CC_Z);
505 break;
506
507 case CC_OP_LOGIC:
508 tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
509 tcg_gen_movi_i32(QREG_CC_C, 0);
510 tcg_gen_movi_i32(QREG_CC_V, 0);
511 break;
512
513 case CC_OP_DYNAMIC:
514 gen_helper_flush_flags(cpu_env, QREG_CC_OP);
515 break;
516
517 default:
518 t0 = tcg_const_i32(s->cc_op);
519 gen_helper_flush_flags(cpu_env, t0);
520 tcg_temp_free(t0);
521 break;
522 }
523
524 /* Note that flush_flags also assigned to env->cc_op. */
525 s->cc_op = CC_OP_FLAGS;
526 s->cc_op_synced = 1;
527 }
528
529 /* Sign or zero extend a value. */
530
531 static inline void gen_ext(TCGv res, TCGv val, int opsize, int sign)
532 {
533 switch (opsize) {
534 case OS_BYTE:
535 if (sign) {
536 tcg_gen_ext8s_i32(res, val);
537 } else {
538 tcg_gen_ext8u_i32(res, val);
539 }
540 break;
541 case OS_WORD:
542 if (sign) {
543 tcg_gen_ext16s_i32(res, val);
544 } else {
545 tcg_gen_ext16u_i32(res, val);
546 }
547 break;
548 case OS_LONG:
549 tcg_gen_mov_i32(res, val);
550 break;
551 default:
552 g_assert_not_reached();
553 }
554 }
555
556 static TCGv gen_extend(TCGv val, int opsize, int sign)
557 {
558 TCGv tmp;
559
560 if (opsize == OS_LONG) {
561 tmp = val;
562 } else {
563 tmp = tcg_temp_new();
564 gen_ext(tmp, val, opsize, sign);
565 }
566
567 return tmp;
568 }
569
570 static void gen_logic_cc(DisasContext *s, TCGv val, int opsize)
571 {
572 gen_ext(QREG_CC_N, val, opsize, 1);
573 set_cc_op(s, CC_OP_LOGIC);
574 }
575
576 static void gen_update_cc_add(TCGv dest, TCGv src)
577 {
578 tcg_gen_mov_i32(QREG_CC_N, dest);
579 tcg_gen_mov_i32(QREG_CC_V, src);
580 }
581
582 static inline int opsize_bytes(int opsize)
583 {
584 switch (opsize) {
585 case OS_BYTE: return 1;
586 case OS_WORD: return 2;
587 case OS_LONG: return 4;
588 case OS_SINGLE: return 4;
589 case OS_DOUBLE: return 8;
590 case OS_EXTENDED: return 12;
591 case OS_PACKED: return 12;
592 default:
593 g_assert_not_reached();
594 }
595 }
596
597 static inline int insn_opsize(int insn)
598 {
599 switch ((insn >> 6) & 3) {
600 case 0: return OS_BYTE;
601 case 1: return OS_WORD;
602 case 2: return OS_LONG;
603 default:
604 g_assert_not_reached();
605 }
606 }
607
608 /* Assign value to a register. If the width is less than the register width
609 only the low part of the register is set. */
610 static void gen_partset_reg(int opsize, TCGv reg, TCGv val)
611 {
612 TCGv tmp;
613 switch (opsize) {
614 case OS_BYTE:
615 tcg_gen_andi_i32(reg, reg, 0xffffff00);
616 tmp = tcg_temp_new();
617 tcg_gen_ext8u_i32(tmp, val);
618 tcg_gen_or_i32(reg, reg, tmp);
619 break;
620 case OS_WORD:
621 tcg_gen_andi_i32(reg, reg, 0xffff0000);
622 tmp = tcg_temp_new();
623 tcg_gen_ext16u_i32(tmp, val);
624 tcg_gen_or_i32(reg, reg, tmp);
625 break;
626 case OS_LONG:
627 case OS_SINGLE:
628 tcg_gen_mov_i32(reg, val);
629 break;
630 default:
631 g_assert_not_reached();
632 }
633 }
634
635 /* Generate code for an "effective address". Does not adjust the base
636 register for autoincrement addressing modes. */
637 static TCGv gen_lea(CPUM68KState *env, DisasContext *s, uint16_t insn,
638 int opsize)
639 {
640 TCGv reg;
641 TCGv tmp;
642 uint16_t ext;
643 uint32_t offset;
644
645 switch ((insn >> 3) & 7) {
646 case 0: /* Data register direct. */
647 case 1: /* Address register direct. */
648 return NULL_QREG;
649 case 2: /* Indirect register */
650 case 3: /* Indirect postincrement. */
651 return AREG(insn, 0);
652 case 4: /* Indirect predecrememnt. */
653 reg = AREG(insn, 0);
654 tmp = tcg_temp_new();
655 tcg_gen_subi_i32(tmp, reg, opsize_bytes(opsize));
656 return tmp;
657 case 5: /* Indirect displacement. */
658 reg = AREG(insn, 0);
659 tmp = tcg_temp_new();
660 ext = read_im16(env, s);
661 tcg_gen_addi_i32(tmp, reg, (int16_t)ext);
662 return tmp;
663 case 6: /* Indirect index + displacement. */
664 reg = AREG(insn, 0);
665 return gen_lea_indexed(env, s, reg);
666 case 7: /* Other */
667 switch (insn & 7) {
668 case 0: /* Absolute short. */
669 offset = (int16_t)read_im16(env, s);
670 return tcg_const_i32(offset);
671 case 1: /* Absolute long. */
672 offset = read_im32(env, s);
673 return tcg_const_i32(offset);
674 case 2: /* pc displacement */
675 offset = s->pc;
676 offset += (int16_t)read_im16(env, s);
677 return tcg_const_i32(offset);
678 case 3: /* pc index+displacement. */
679 return gen_lea_indexed(env, s, NULL_QREG);
680 case 4: /* Immediate. */
681 default:
682 return NULL_QREG;
683 }
684 }
685 /* Should never happen. */
686 return NULL_QREG;
687 }
688
689 /* Helper function for gen_ea. Reuse the computed address between the
690 for read/write operands. */
691 static inline TCGv gen_ea_once(CPUM68KState *env, DisasContext *s,
692 uint16_t insn, int opsize, TCGv val,
693 TCGv *addrp, ea_what what)
694 {
695 TCGv tmp;
696
697 if (addrp && what == EA_STORE) {
698 tmp = *addrp;
699 } else {
700 tmp = gen_lea(env, s, insn, opsize);
701 if (IS_NULL_QREG(tmp))
702 return tmp;
703 if (addrp)
704 *addrp = tmp;
705 }
706 return gen_ldst(s, opsize, tmp, val, what);
707 }
708
709 /* Generate code to load/store a value from/into an EA. If VAL > 0 this is
710 a write otherwise it is a read (0 == sign extend, -1 == zero extend).
711 ADDRP is non-null for readwrite operands. */
712 static TCGv gen_ea(CPUM68KState *env, DisasContext *s, uint16_t insn,
713 int opsize, TCGv val, TCGv *addrp, ea_what what)
714 {
715 TCGv reg;
716 TCGv result;
717 uint32_t offset;
718
719 switch ((insn >> 3) & 7) {
720 case 0: /* Data register direct. */
721 reg = DREG(insn, 0);
722 if (what == EA_STORE) {
723 gen_partset_reg(opsize, reg, val);
724 return store_dummy;
725 } else {
726 return gen_extend(reg, opsize, what == EA_LOADS);
727 }
728 case 1: /* Address register direct. */
729 reg = AREG(insn, 0);
730 if (what == EA_STORE) {
731 tcg_gen_mov_i32(reg, val);
732 return store_dummy;
733 } else {
734 return gen_extend(reg, opsize, what == EA_LOADS);
735 }
736 case 2: /* Indirect register */
737 reg = AREG(insn, 0);
738 return gen_ldst(s, opsize, reg, val, what);
739 case 3: /* Indirect postincrement. */
740 reg = AREG(insn, 0);
741 result = gen_ldst(s, opsize, reg, val, what);
742 /* ??? This is not exception safe. The instruction may still
743 fault after this point. */
744 if (what == EA_STORE || !addrp)
745 tcg_gen_addi_i32(reg, reg, opsize_bytes(opsize));
746 return result;
747 case 4: /* Indirect predecrememnt. */
748 {
749 TCGv tmp;
750 if (addrp && what == EA_STORE) {
751 tmp = *addrp;
752 } else {
753 tmp = gen_lea(env, s, insn, opsize);
754 if (IS_NULL_QREG(tmp))
755 return tmp;
756 if (addrp)
757 *addrp = tmp;
758 }
759 result = gen_ldst(s, opsize, tmp, val, what);
760 /* ??? This is not exception safe. The instruction may still
761 fault after this point. */
762 if (what == EA_STORE || !addrp) {
763 reg = AREG(insn, 0);
764 tcg_gen_mov_i32(reg, tmp);
765 }
766 }
767 return result;
768 case 5: /* Indirect displacement. */
769 case 6: /* Indirect index + displacement. */
770 return gen_ea_once(env, s, insn, opsize, val, addrp, what);
771 case 7: /* Other */
772 switch (insn & 7) {
773 case 0: /* Absolute short. */
774 case 1: /* Absolute long. */
775 case 2: /* pc displacement */
776 case 3: /* pc index+displacement. */
777 return gen_ea_once(env, s, insn, opsize, val, addrp, what);
778 case 4: /* Immediate. */
779 /* Sign extend values for consistency. */
780 switch (opsize) {
781 case OS_BYTE:
782 if (what == EA_LOADS) {
783 offset = (int8_t)read_im8(env, s);
784 } else {
785 offset = read_im8(env, s);
786 }
787 break;
788 case OS_WORD:
789 if (what == EA_LOADS) {
790 offset = (int16_t)read_im16(env, s);
791 } else {
792 offset = read_im16(env, s);
793 }
794 break;
795 case OS_LONG:
796 offset = read_im32(env, s);
797 break;
798 default:
799 g_assert_not_reached();
800 }
801 return tcg_const_i32(offset);
802 default:
803 return NULL_QREG;
804 }
805 }
806 /* Should never happen. */
807 return NULL_QREG;
808 }
809
810 typedef struct {
811 TCGCond tcond;
812 bool g1;
813 bool g2;
814 TCGv v1;
815 TCGv v2;
816 } DisasCompare;
817
818 static void gen_cc_cond(DisasCompare *c, DisasContext *s, int cond)
819 {
820 TCGv tmp, tmp2;
821 TCGCond tcond;
822 CCOp op = s->cc_op;
823
824 /* The CC_OP_CMP form can handle most normal comparisons directly. */
825 if (op == CC_OP_CMP) {
826 c->g1 = c->g2 = 1;
827 c->v1 = QREG_CC_N;
828 c->v2 = QREG_CC_V;
829 switch (cond) {
830 case 2: /* HI */
831 case 3: /* LS */
832 tcond = TCG_COND_LEU;
833 goto done;
834 case 4: /* CC */
835 case 5: /* CS */
836 tcond = TCG_COND_LTU;
837 goto done;
838 case 6: /* NE */
839 case 7: /* EQ */
840 tcond = TCG_COND_EQ;
841 goto done;
842 case 10: /* PL */
843 case 11: /* MI */
844 c->g1 = c->g2 = 0;
845 c->v2 = tcg_const_i32(0);
846 c->v1 = tmp = tcg_temp_new();
847 tcg_gen_sub_i32(tmp, QREG_CC_N, QREG_CC_V);
848 /* fallthru */
849 case 12: /* GE */
850 case 13: /* LT */
851 tcond = TCG_COND_LT;
852 goto done;
853 case 14: /* GT */
854 case 15: /* LE */
855 tcond = TCG_COND_LE;
856 goto done;
857 }
858 }
859
860 c->g1 = 1;
861 c->g2 = 0;
862 c->v2 = tcg_const_i32(0);
863
864 switch (cond) {
865 case 0: /* T */
866 case 1: /* F */
867 c->v1 = c->v2;
868 tcond = TCG_COND_NEVER;
869 goto done;
870 case 14: /* GT (!(Z || (N ^ V))) */
871 case 15: /* LE (Z || (N ^ V)) */
872 /* Logic operations clear V, which simplifies LE to (Z || N),
873 and since Z and N are co-located, this becomes a normal
874 comparison vs N. */
875 if (op == CC_OP_LOGIC) {
876 c->v1 = QREG_CC_N;
877 tcond = TCG_COND_LE;
878 goto done;
879 }
880 break;
881 case 12: /* GE (!(N ^ V)) */
882 case 13: /* LT (N ^ V) */
883 /* Logic operations clear V, which simplifies this to N. */
884 if (op != CC_OP_LOGIC) {
885 break;
886 }
887 /* fallthru */
888 case 10: /* PL (!N) */
889 case 11: /* MI (N) */
890 /* Several cases represent N normally. */
891 if (op == CC_OP_ADD || op == CC_OP_SUB || op == CC_OP_LOGIC) {
892 c->v1 = QREG_CC_N;
893 tcond = TCG_COND_LT;
894 goto done;
895 }
896 break;
897 case 6: /* NE (!Z) */
898 case 7: /* EQ (Z) */
899 /* Some cases fold Z into N. */
900 if (op == CC_OP_ADD || op == CC_OP_SUB || op == CC_OP_LOGIC) {
901 tcond = TCG_COND_EQ;
902 c->v1 = QREG_CC_N;
903 goto done;
904 }
905 break;
906 case 4: /* CC (!C) */
907 case 5: /* CS (C) */
908 /* Some cases fold C into X. */
909 if (op == CC_OP_ADD || op == CC_OP_SUB) {
910 tcond = TCG_COND_NE;
911 c->v1 = QREG_CC_X;
912 goto done;
913 }
914 /* fallthru */
915 case 8: /* VC (!V) */
916 case 9: /* VS (V) */
917 /* Logic operations clear V and C. */
918 if (op == CC_OP_LOGIC) {
919 tcond = TCG_COND_NEVER;
920 c->v1 = c->v2;
921 goto done;
922 }
923 break;
924 }
925
926 /* Otherwise, flush flag state to CC_OP_FLAGS. */
927 gen_flush_flags(s);
928
929 switch (cond) {
930 case 0: /* T */
931 case 1: /* F */
932 default:
933 /* Invalid, or handled above. */
934 abort();
935 case 2: /* HI (!C && !Z) -> !(C || Z)*/
936 case 3: /* LS (C || Z) */
937 c->v1 = tmp = tcg_temp_new();
938 c->g1 = 0;
939 tcg_gen_setcond_i32(TCG_COND_EQ, tmp, QREG_CC_Z, c->v2);
940 tcg_gen_or_i32(tmp, tmp, QREG_CC_C);
941 tcond = TCG_COND_NE;
942 break;
943 case 4: /* CC (!C) */
944 case 5: /* CS (C) */
945 c->v1 = QREG_CC_C;
946 tcond = TCG_COND_NE;
947 break;
948 case 6: /* NE (!Z) */
949 case 7: /* EQ (Z) */
950 c->v1 = QREG_CC_Z;
951 tcond = TCG_COND_EQ;
952 break;
953 case 8: /* VC (!V) */
954 case 9: /* VS (V) */
955 c->v1 = QREG_CC_V;
956 tcond = TCG_COND_LT;
957 break;
958 case 10: /* PL (!N) */
959 case 11: /* MI (N) */
960 c->v1 = QREG_CC_N;
961 tcond = TCG_COND_LT;
962 break;
963 case 12: /* GE (!(N ^ V)) */
964 case 13: /* LT (N ^ V) */
965 c->v1 = tmp = tcg_temp_new();
966 c->g1 = 0;
967 tcg_gen_xor_i32(tmp, QREG_CC_N, QREG_CC_V);
968 tcond = TCG_COND_LT;
969 break;
970 case 14: /* GT (!(Z || (N ^ V))) */
971 case 15: /* LE (Z || (N ^ V)) */
972 c->v1 = tmp = tcg_temp_new();
973 c->g1 = 0;
974 tcg_gen_setcond_i32(TCG_COND_EQ, tmp, QREG_CC_Z, c->v2);
975 tcg_gen_neg_i32(tmp, tmp);
976 tmp2 = tcg_temp_new();
977 tcg_gen_xor_i32(tmp2, QREG_CC_N, QREG_CC_V);
978 tcg_gen_or_i32(tmp, tmp, tmp2);
979 tcg_temp_free(tmp2);
980 tcond = TCG_COND_LT;
981 break;
982 }
983
984 done:
985 if ((cond & 1) == 0) {
986 tcond = tcg_invert_cond(tcond);
987 }
988 c->tcond = tcond;
989 }
990
991 static void free_cond(DisasCompare *c)
992 {
993 if (!c->g1) {
994 tcg_temp_free(c->v1);
995 }
996 if (!c->g2) {
997 tcg_temp_free(c->v2);
998 }
999 }
1000
1001 static void gen_jmpcc(DisasContext *s, int cond, TCGLabel *l1)
1002 {
1003 DisasCompare c;
1004
1005 gen_cc_cond(&c, s, cond);
1006 update_cc_op(s);
1007 tcg_gen_brcond_i32(c.tcond, c.v1, c.v2, l1);
1008 free_cond(&c);
1009 }
1010
1011 DISAS_INSN(scc)
1012 {
1013 DisasCompare c;
1014 int cond;
1015 TCGv reg, tmp;
1016
1017 cond = (insn >> 8) & 0xf;
1018 gen_cc_cond(&c, s, cond);
1019
1020 tmp = tcg_temp_new();
1021 tcg_gen_setcond_i32(c.tcond, tmp, c.v1, c.v2);
1022 free_cond(&c);
1023
1024 reg = DREG(insn, 0);
1025 tcg_gen_neg_i32(tmp, tmp);
1026 tcg_gen_deposit_i32(reg, reg, tmp, 0, 8);
1027 tcg_temp_free(tmp);
1028 }
1029
1030 /* Force a TB lookup after an instruction that changes the CPU state. */
1031 static void gen_lookup_tb(DisasContext *s)
1032 {
1033 update_cc_op(s);
1034 tcg_gen_movi_i32(QREG_PC, s->pc);
1035 s->is_jmp = DISAS_UPDATE;
1036 }
1037
1038 /* Generate a jump to an immediate address. */
1039 static void gen_jmp_im(DisasContext *s, uint32_t dest)
1040 {
1041 update_cc_op(s);
1042 tcg_gen_movi_i32(QREG_PC, dest);
1043 s->is_jmp = DISAS_JUMP;
1044 }
1045
1046 /* Generate a jump to the address in qreg DEST. */
1047 static void gen_jmp(DisasContext *s, TCGv dest)
1048 {
1049 update_cc_op(s);
1050 tcg_gen_mov_i32(QREG_PC, dest);
1051 s->is_jmp = DISAS_JUMP;
1052 }
1053
1054 static void gen_exception(DisasContext *s, uint32_t where, int nr)
1055 {
1056 update_cc_op(s);
1057 gen_jmp_im(s, where);
1058 gen_helper_raise_exception(cpu_env, tcg_const_i32(nr));
1059 }
1060
1061 static inline void gen_addr_fault(DisasContext *s)
1062 {
1063 gen_exception(s, s->insn_pc, EXCP_ADDRESS);
1064 }
1065
1066 #define SRC_EA(env, result, opsize, op_sign, addrp) do { \
1067 result = gen_ea(env, s, insn, opsize, NULL_QREG, addrp, \
1068 op_sign ? EA_LOADS : EA_LOADU); \
1069 if (IS_NULL_QREG(result)) { \
1070 gen_addr_fault(s); \
1071 return; \
1072 } \
1073 } while (0)
1074
1075 #define DEST_EA(env, insn, opsize, val, addrp) do { \
1076 TCGv ea_result = gen_ea(env, s, insn, opsize, val, addrp, EA_STORE); \
1077 if (IS_NULL_QREG(ea_result)) { \
1078 gen_addr_fault(s); \
1079 return; \
1080 } \
1081 } while (0)
1082
1083 static inline bool use_goto_tb(DisasContext *s, uint32_t dest)
1084 {
1085 #ifndef CONFIG_USER_ONLY
1086 return (s->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) ||
1087 (s->insn_pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
1088 #else
1089 return true;
1090 #endif
1091 }
1092
1093 /* Generate a jump to an immediate address. */
1094 static void gen_jmp_tb(DisasContext *s, int n, uint32_t dest)
1095 {
1096 if (unlikely(s->singlestep_enabled)) {
1097 gen_exception(s, dest, EXCP_DEBUG);
1098 } else if (use_goto_tb(s, dest)) {
1099 tcg_gen_goto_tb(n);
1100 tcg_gen_movi_i32(QREG_PC, dest);
1101 tcg_gen_exit_tb((uintptr_t)s->tb + n);
1102 } else {
1103 gen_jmp_im(s, dest);
1104 tcg_gen_exit_tb(0);
1105 }
1106 s->is_jmp = DISAS_TB_JUMP;
1107 }
1108
1109 DISAS_INSN(undef_mac)
1110 {
1111 gen_exception(s, s->pc - 2, EXCP_LINEA);
1112 }
1113
1114 DISAS_INSN(undef_fpu)
1115 {
1116 gen_exception(s, s->pc - 2, EXCP_LINEF);
1117 }
1118
1119 DISAS_INSN(undef)
1120 {
1121 M68kCPU *cpu = m68k_env_get_cpu(env);
1122
1123 gen_exception(s, s->pc - 2, EXCP_UNSUPPORTED);
1124 cpu_abort(CPU(cpu), "Illegal instruction: %04x @ %08x", insn, s->pc - 2);
1125 }
1126
1127 DISAS_INSN(mulw)
1128 {
1129 TCGv reg;
1130 TCGv tmp;
1131 TCGv src;
1132 int sign;
1133
1134 sign = (insn & 0x100) != 0;
1135 reg = DREG(insn, 9);
1136 tmp = tcg_temp_new();
1137 if (sign)
1138 tcg_gen_ext16s_i32(tmp, reg);
1139 else
1140 tcg_gen_ext16u_i32(tmp, reg);
1141 SRC_EA(env, src, OS_WORD, sign, NULL);
1142 tcg_gen_mul_i32(tmp, tmp, src);
1143 tcg_gen_mov_i32(reg, tmp);
1144 gen_logic_cc(s, tmp, OS_WORD);
1145 }
1146
1147 DISAS_INSN(divw)
1148 {
1149 TCGv reg;
1150 TCGv tmp;
1151 TCGv src;
1152 int sign;
1153
1154 sign = (insn & 0x100) != 0;
1155 reg = DREG(insn, 9);
1156 if (sign) {
1157 tcg_gen_ext16s_i32(QREG_DIV1, reg);
1158 } else {
1159 tcg_gen_ext16u_i32(QREG_DIV1, reg);
1160 }
1161 SRC_EA(env, src, OS_WORD, sign, NULL);
1162 tcg_gen_mov_i32(QREG_DIV2, src);
1163 if (sign) {
1164 gen_helper_divs(cpu_env, tcg_const_i32(1));
1165 } else {
1166 gen_helper_divu(cpu_env, tcg_const_i32(1));
1167 }
1168
1169 tmp = tcg_temp_new();
1170 src = tcg_temp_new();
1171 tcg_gen_ext16u_i32(tmp, QREG_DIV1);
1172 tcg_gen_shli_i32(src, QREG_DIV2, 16);
1173 tcg_gen_or_i32(reg, tmp, src);
1174
1175 set_cc_op(s, CC_OP_FLAGS);
1176 }
1177
1178 DISAS_INSN(divl)
1179 {
1180 TCGv num;
1181 TCGv den;
1182 TCGv reg;
1183 uint16_t ext;
1184
1185 ext = read_im16(env, s);
1186 if (ext & 0x87f8) {
1187 gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED);
1188 return;
1189 }
1190 num = DREG(ext, 12);
1191 reg = DREG(ext, 0);
1192 tcg_gen_mov_i32(QREG_DIV1, num);
1193 SRC_EA(env, den, OS_LONG, 0, NULL);
1194 tcg_gen_mov_i32(QREG_DIV2, den);
1195 if (ext & 0x0800) {
1196 gen_helper_divs(cpu_env, tcg_const_i32(0));
1197 } else {
1198 gen_helper_divu(cpu_env, tcg_const_i32(0));
1199 }
1200 if ((ext & 7) == ((ext >> 12) & 7)) {
1201 /* div */
1202 tcg_gen_mov_i32 (reg, QREG_DIV1);
1203 } else {
1204 /* rem */
1205 tcg_gen_mov_i32 (reg, QREG_DIV2);
1206 }
1207 set_cc_op(s, CC_OP_FLAGS);
1208 }
1209
1210 DISAS_INSN(addsub)
1211 {
1212 TCGv reg;
1213 TCGv dest;
1214 TCGv src;
1215 TCGv tmp;
1216 TCGv addr;
1217 int add;
1218
1219 add = (insn & 0x4000) != 0;
1220 reg = DREG(insn, 9);
1221 dest = tcg_temp_new();
1222 if (insn & 0x100) {
1223 SRC_EA(env, tmp, OS_LONG, 0, &addr);
1224 src = reg;
1225 } else {
1226 tmp = reg;
1227 SRC_EA(env, src, OS_LONG, 0, NULL);
1228 }
1229 if (add) {
1230 tcg_gen_add_i32(dest, tmp, src);
1231 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, src);
1232 set_cc_op(s, CC_OP_ADD);
1233 } else {
1234 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, tmp, src);
1235 tcg_gen_sub_i32(dest, tmp, src);
1236 set_cc_op(s, CC_OP_SUB);
1237 }
1238 gen_update_cc_add(dest, src);
1239 if (insn & 0x100) {
1240 DEST_EA(env, insn, OS_LONG, dest, &addr);
1241 } else {
1242 tcg_gen_mov_i32(reg, dest);
1243 }
1244 }
1245
1246
1247 /* Reverse the order of the bits in REG. */
1248 DISAS_INSN(bitrev)
1249 {
1250 TCGv reg;
1251 reg = DREG(insn, 0);
1252 gen_helper_bitrev(reg, reg);
1253 }
1254
1255 DISAS_INSN(bitop_reg)
1256 {
1257 int opsize;
1258 int op;
1259 TCGv src1;
1260 TCGv src2;
1261 TCGv tmp;
1262 TCGv addr;
1263 TCGv dest;
1264
1265 if ((insn & 0x38) != 0)
1266 opsize = OS_BYTE;
1267 else
1268 opsize = OS_LONG;
1269 op = (insn >> 6) & 3;
1270
1271 gen_flush_flags(s);
1272
1273 SRC_EA(env, src1, opsize, 0, op ? &addr: NULL);
1274 src2 = DREG(insn, 9);
1275 dest = tcg_temp_new();
1276
1277 tmp = tcg_temp_new();
1278 if (opsize == OS_BYTE)
1279 tcg_gen_andi_i32(tmp, src2, 7);
1280 else
1281 tcg_gen_andi_i32(tmp, src2, 31);
1282
1283 src2 = tcg_const_i32(1);
1284 tcg_gen_shl_i32(src2, src2, tmp);
1285 tcg_temp_free(tmp);
1286
1287 tcg_gen_and_i32(QREG_CC_Z, src1, src2);
1288
1289 switch (op) {
1290 case 1: /* bchg */
1291 tcg_gen_xor_i32(dest, src1, src2);
1292 break;
1293 case 2: /* bclr */
1294 tcg_gen_andc_i32(dest, src1, src2);
1295 break;
1296 case 3: /* bset */
1297 tcg_gen_or_i32(dest, src1, src2);
1298 break;
1299 default: /* btst */
1300 break;
1301 }
1302 tcg_temp_free(src2);
1303 if (op) {
1304 DEST_EA(env, insn, opsize, dest, &addr);
1305 }
1306 tcg_temp_free(dest);
1307 }
1308
1309 DISAS_INSN(sats)
1310 {
1311 TCGv reg;
1312 reg = DREG(insn, 0);
1313 gen_flush_flags(s);
1314 gen_helper_sats(reg, reg, QREG_CC_V);
1315 gen_logic_cc(s, reg, OS_LONG);
1316 }
1317
1318 static void gen_push(DisasContext *s, TCGv val)
1319 {
1320 TCGv tmp;
1321
1322 tmp = tcg_temp_new();
1323 tcg_gen_subi_i32(tmp, QREG_SP, 4);
1324 gen_store(s, OS_LONG, tmp, val);
1325 tcg_gen_mov_i32(QREG_SP, tmp);
1326 }
1327
1328 DISAS_INSN(movem)
1329 {
1330 TCGv addr;
1331 int i;
1332 uint16_t mask;
1333 TCGv reg;
1334 TCGv tmp;
1335 int is_load;
1336
1337 mask = read_im16(env, s);
1338 tmp = gen_lea(env, s, insn, OS_LONG);
1339 if (IS_NULL_QREG(tmp)) {
1340 gen_addr_fault(s);
1341 return;
1342 }
1343 addr = tcg_temp_new();
1344 tcg_gen_mov_i32(addr, tmp);
1345 is_load = ((insn & 0x0400) != 0);
1346 for (i = 0; i < 16; i++, mask >>= 1) {
1347 if (mask & 1) {
1348 if (i < 8)
1349 reg = DREG(i, 0);
1350 else
1351 reg = AREG(i, 0);
1352 if (is_load) {
1353 tmp = gen_load(s, OS_LONG, addr, 0);
1354 tcg_gen_mov_i32(reg, tmp);
1355 } else {
1356 gen_store(s, OS_LONG, addr, reg);
1357 }
1358 if (mask != 1)
1359 tcg_gen_addi_i32(addr, addr, 4);
1360 }
1361 }
1362 }
1363
1364 DISAS_INSN(bitop_im)
1365 {
1366 int opsize;
1367 int op;
1368 TCGv src1;
1369 uint32_t mask;
1370 int bitnum;
1371 TCGv tmp;
1372 TCGv addr;
1373
1374 if ((insn & 0x38) != 0)
1375 opsize = OS_BYTE;
1376 else
1377 opsize = OS_LONG;
1378 op = (insn >> 6) & 3;
1379
1380 bitnum = read_im16(env, s);
1381 if (bitnum & 0xff00) {
1382 disas_undef(env, s, insn);
1383 return;
1384 }
1385
1386 gen_flush_flags(s);
1387
1388 SRC_EA(env, src1, opsize, 0, op ? &addr: NULL);
1389
1390 if (opsize == OS_BYTE)
1391 bitnum &= 7;
1392 else
1393 bitnum &= 31;
1394 mask = 1 << bitnum;
1395
1396 tcg_gen_andi_i32(QREG_CC_Z, src1, mask);
1397
1398 if (op) {
1399 tmp = tcg_temp_new();
1400 switch (op) {
1401 case 1: /* bchg */
1402 tcg_gen_xori_i32(tmp, src1, mask);
1403 break;
1404 case 2: /* bclr */
1405 tcg_gen_andi_i32(tmp, src1, ~mask);
1406 break;
1407 case 3: /* bset */
1408 tcg_gen_ori_i32(tmp, src1, mask);
1409 break;
1410 default: /* btst */
1411 break;
1412 }
1413 DEST_EA(env, insn, opsize, tmp, &addr);
1414 tcg_temp_free(tmp);
1415 }
1416 }
1417
1418 DISAS_INSN(arith_im)
1419 {
1420 int op;
1421 uint32_t im;
1422 TCGv src1;
1423 TCGv dest;
1424 TCGv addr;
1425
1426 op = (insn >> 9) & 7;
1427 SRC_EA(env, src1, OS_LONG, 0, (op == 6) ? NULL : &addr);
1428 im = read_im32(env, s);
1429 dest = tcg_temp_new();
1430 switch (op) {
1431 case 0: /* ori */
1432 tcg_gen_ori_i32(dest, src1, im);
1433 gen_logic_cc(s, dest, OS_LONG);
1434 break;
1435 case 1: /* andi */
1436 tcg_gen_andi_i32(dest, src1, im);
1437 gen_logic_cc(s, dest, OS_LONG);
1438 break;
1439 case 2: /* subi */
1440 tcg_gen_mov_i32(dest, src1);
1441 tcg_gen_setcondi_i32(TCG_COND_LTU, QREG_CC_X, dest, im);
1442 tcg_gen_subi_i32(dest, dest, im);
1443 gen_update_cc_add(dest, tcg_const_i32(im));
1444 set_cc_op(s, CC_OP_SUB);
1445 break;
1446 case 3: /* addi */
1447 tcg_gen_mov_i32(dest, src1);
1448 tcg_gen_addi_i32(dest, dest, im);
1449 gen_update_cc_add(dest, tcg_const_i32(im));
1450 tcg_gen_setcondi_i32(TCG_COND_LTU, QREG_CC_X, dest, im);
1451 set_cc_op(s, CC_OP_ADD);
1452 break;
1453 case 5: /* eori */
1454 tcg_gen_xori_i32(dest, src1, im);
1455 gen_logic_cc(s, dest, OS_LONG);
1456 break;
1457 case 6: /* cmpi */
1458 gen_update_cc_add(src1, tcg_const_i32(im));
1459 set_cc_op(s, CC_OP_CMP);
1460 break;
1461 default:
1462 abort();
1463 }
1464 if (op != 6) {
1465 DEST_EA(env, insn, OS_LONG, dest, &addr);
1466 }
1467 }
1468
1469 DISAS_INSN(byterev)
1470 {
1471 TCGv reg;
1472
1473 reg = DREG(insn, 0);
1474 tcg_gen_bswap32_i32(reg, reg);
1475 }
1476
1477 DISAS_INSN(move)
1478 {
1479 TCGv src;
1480 TCGv dest;
1481 int op;
1482 int opsize;
1483
1484 switch (insn >> 12) {
1485 case 1: /* move.b */
1486 opsize = OS_BYTE;
1487 break;
1488 case 2: /* move.l */
1489 opsize = OS_LONG;
1490 break;
1491 case 3: /* move.w */
1492 opsize = OS_WORD;
1493 break;
1494 default:
1495 abort();
1496 }
1497 SRC_EA(env, src, opsize, 1, NULL);
1498 op = (insn >> 6) & 7;
1499 if (op == 1) {
1500 /* movea */
1501 /* The value will already have been sign extended. */
1502 dest = AREG(insn, 9);
1503 tcg_gen_mov_i32(dest, src);
1504 } else {
1505 /* normal move */
1506 uint16_t dest_ea;
1507 dest_ea = ((insn >> 9) & 7) | (op << 3);
1508 DEST_EA(env, dest_ea, opsize, src, NULL);
1509 /* This will be correct because loads sign extend. */
1510 gen_logic_cc(s, src, opsize);
1511 }
1512 }
1513
1514 DISAS_INSN(negx)
1515 {
1516 TCGv reg;
1517
1518 gen_flush_flags(s);
1519 reg = DREG(insn, 0);
1520 gen_helper_subx_cc(reg, cpu_env, tcg_const_i32(0), reg);
1521 }
1522
1523 DISAS_INSN(lea)
1524 {
1525 TCGv reg;
1526 TCGv tmp;
1527
1528 reg = AREG(insn, 9);
1529 tmp = gen_lea(env, s, insn, OS_LONG);
1530 if (IS_NULL_QREG(tmp)) {
1531 gen_addr_fault(s);
1532 return;
1533 }
1534 tcg_gen_mov_i32(reg, tmp);
1535 }
1536
1537 DISAS_INSN(clr)
1538 {
1539 int opsize;
1540
1541 opsize = insn_opsize(insn);
1542 DEST_EA(env, insn, opsize, tcg_const_i32(0), NULL);
1543 gen_logic_cc(s, tcg_const_i32(0), opsize);
1544 }
1545
1546 static TCGv gen_get_ccr(DisasContext *s)
1547 {
1548 TCGv dest;
1549
1550 gen_flush_flags(s);
1551 update_cc_op(s);
1552 dest = tcg_temp_new();
1553 gen_helper_get_ccr(dest, cpu_env);
1554 return dest;
1555 }
1556
1557 DISAS_INSN(move_from_ccr)
1558 {
1559 TCGv ccr;
1560
1561 ccr = gen_get_ccr(s);
1562 DEST_EA(env, insn, OS_WORD, ccr, NULL);
1563 }
1564
1565 DISAS_INSN(neg)
1566 {
1567 TCGv reg;
1568 TCGv src1;
1569
1570 reg = DREG(insn, 0);
1571 src1 = tcg_temp_new();
1572 tcg_gen_mov_i32(src1, reg);
1573 tcg_gen_neg_i32(reg, src1);
1574 gen_update_cc_add(reg, src1);
1575 tcg_gen_setcondi_i32(TCG_COND_NE, QREG_CC_X, src1, 0);
1576 set_cc_op(s, CC_OP_SUB);
1577 }
1578
1579 static void gen_set_sr_im(DisasContext *s, uint16_t val, int ccr_only)
1580 {
1581 if (ccr_only) {
1582 tcg_gen_movi_i32(QREG_CC_C, val & CCF_C ? 1 : 0);
1583 tcg_gen_movi_i32(QREG_CC_V, val & CCF_V ? -1 : 0);
1584 tcg_gen_movi_i32(QREG_CC_Z, val & CCF_Z ? 0 : 1);
1585 tcg_gen_movi_i32(QREG_CC_N, val & CCF_N ? -1 : 0);
1586 tcg_gen_movi_i32(QREG_CC_X, val & CCF_X ? 1 : 0);
1587 } else {
1588 gen_helper_set_sr(cpu_env, tcg_const_i32(val));
1589 }
1590 set_cc_op(s, CC_OP_FLAGS);
1591 }
1592
1593 static void gen_set_sr(CPUM68KState *env, DisasContext *s, uint16_t insn,
1594 int ccr_only)
1595 {
1596 if ((insn & 0x38) == 0) {
1597 if (ccr_only) {
1598 gen_helper_set_ccr(cpu_env, DREG(insn, 0));
1599 } else {
1600 gen_helper_set_sr(cpu_env, DREG(insn, 0));
1601 }
1602 set_cc_op(s, CC_OP_FLAGS);
1603 } else if ((insn & 0x3f) == 0x3c) {
1604 uint16_t val;
1605 val = read_im16(env, s);
1606 gen_set_sr_im(s, val, ccr_only);
1607 } else {
1608 disas_undef(env, s, insn);
1609 }
1610 }
1611
1612
1613 DISAS_INSN(move_to_ccr)
1614 {
1615 gen_set_sr(env, s, insn, 1);
1616 }
1617
1618 DISAS_INSN(not)
1619 {
1620 TCGv reg;
1621
1622 reg = DREG(insn, 0);
1623 tcg_gen_not_i32(reg, reg);
1624 gen_logic_cc(s, reg, OS_LONG);
1625 }
1626
1627 DISAS_INSN(swap)
1628 {
1629 TCGv src1;
1630 TCGv src2;
1631 TCGv reg;
1632
1633 src1 = tcg_temp_new();
1634 src2 = tcg_temp_new();
1635 reg = DREG(insn, 0);
1636 tcg_gen_shli_i32(src1, reg, 16);
1637 tcg_gen_shri_i32(src2, reg, 16);
1638 tcg_gen_or_i32(reg, src1, src2);
1639 gen_logic_cc(s, reg, OS_LONG);
1640 }
1641
1642 DISAS_INSN(pea)
1643 {
1644 TCGv tmp;
1645
1646 tmp = gen_lea(env, s, insn, OS_LONG);
1647 if (IS_NULL_QREG(tmp)) {
1648 gen_addr_fault(s);
1649 return;
1650 }
1651 gen_push(s, tmp);
1652 }
1653
1654 DISAS_INSN(ext)
1655 {
1656 int op;
1657 TCGv reg;
1658 TCGv tmp;
1659
1660 reg = DREG(insn, 0);
1661 op = (insn >> 6) & 7;
1662 tmp = tcg_temp_new();
1663 if (op == 3)
1664 tcg_gen_ext16s_i32(tmp, reg);
1665 else
1666 tcg_gen_ext8s_i32(tmp, reg);
1667 if (op == 2)
1668 gen_partset_reg(OS_WORD, reg, tmp);
1669 else
1670 tcg_gen_mov_i32(reg, tmp);
1671 gen_logic_cc(s, tmp, OS_LONG);
1672 }
1673
1674 DISAS_INSN(tst)
1675 {
1676 int opsize;
1677 TCGv tmp;
1678
1679 opsize = insn_opsize(insn);
1680 SRC_EA(env, tmp, opsize, 1, NULL);
1681 gen_logic_cc(s, tmp, opsize);
1682 }
1683
1684 DISAS_INSN(pulse)
1685 {
1686 /* Implemented as a NOP. */
1687 }
1688
1689 DISAS_INSN(illegal)
1690 {
1691 gen_exception(s, s->pc - 2, EXCP_ILLEGAL);
1692 }
1693
1694 /* ??? This should be atomic. */
1695 DISAS_INSN(tas)
1696 {
1697 TCGv dest;
1698 TCGv src1;
1699 TCGv addr;
1700
1701 dest = tcg_temp_new();
1702 SRC_EA(env, src1, OS_BYTE, 1, &addr);
1703 gen_logic_cc(s, src1, OS_BYTE);
1704 tcg_gen_ori_i32(dest, src1, 0x80);
1705 DEST_EA(env, insn, OS_BYTE, dest, &addr);
1706 }
1707
1708 DISAS_INSN(mull)
1709 {
1710 uint16_t ext;
1711 TCGv reg;
1712 TCGv src1;
1713 TCGv dest;
1714
1715 /* The upper 32 bits of the product are discarded, so
1716 muls.l and mulu.l are functionally equivalent. */
1717 ext = read_im16(env, s);
1718 if (ext & 0x87ff) {
1719 gen_exception(s, s->pc - 4, EXCP_UNSUPPORTED);
1720 return;
1721 }
1722 reg = DREG(ext, 12);
1723 SRC_EA(env, src1, OS_LONG, 0, NULL);
1724 dest = tcg_temp_new();
1725 tcg_gen_mul_i32(dest, src1, reg);
1726 tcg_gen_mov_i32(reg, dest);
1727 /* Unlike m68k, coldfire always clears the overflow bit. */
1728 gen_logic_cc(s, dest, OS_LONG);
1729 }
1730
1731 DISAS_INSN(link)
1732 {
1733 int16_t offset;
1734 TCGv reg;
1735 TCGv tmp;
1736
1737 offset = cpu_ldsw_code(env, s->pc);
1738 s->pc += 2;
1739 reg = AREG(insn, 0);
1740 tmp = tcg_temp_new();
1741 tcg_gen_subi_i32(tmp, QREG_SP, 4);
1742 gen_store(s, OS_LONG, tmp, reg);
1743 if ((insn & 7) != 7)
1744 tcg_gen_mov_i32(reg, tmp);
1745 tcg_gen_addi_i32(QREG_SP, tmp, offset);
1746 }
1747
1748 DISAS_INSN(unlk)
1749 {
1750 TCGv src;
1751 TCGv reg;
1752 TCGv tmp;
1753
1754 src = tcg_temp_new();
1755 reg = AREG(insn, 0);
1756 tcg_gen_mov_i32(src, reg);
1757 tmp = gen_load(s, OS_LONG, src, 0);
1758 tcg_gen_mov_i32(reg, tmp);
1759 tcg_gen_addi_i32(QREG_SP, src, 4);
1760 }
1761
1762 DISAS_INSN(nop)
1763 {
1764 }
1765
1766 DISAS_INSN(rts)
1767 {
1768 TCGv tmp;
1769
1770 tmp = gen_load(s, OS_LONG, QREG_SP, 0);
1771 tcg_gen_addi_i32(QREG_SP, QREG_SP, 4);
1772 gen_jmp(s, tmp);
1773 }
1774
1775 DISAS_INSN(jump)
1776 {
1777 TCGv tmp;
1778
1779 /* Load the target address first to ensure correct exception
1780 behavior. */
1781 tmp = gen_lea(env, s, insn, OS_LONG);
1782 if (IS_NULL_QREG(tmp)) {
1783 gen_addr_fault(s);
1784 return;
1785 }
1786 if ((insn & 0x40) == 0) {
1787 /* jsr */
1788 gen_push(s, tcg_const_i32(s->pc));
1789 }
1790 gen_jmp(s, tmp);
1791 }
1792
1793 DISAS_INSN(addsubq)
1794 {
1795 TCGv src1;
1796 TCGv src2;
1797 TCGv dest;
1798 int val;
1799 TCGv addr;
1800
1801 SRC_EA(env, src1, OS_LONG, 0, &addr);
1802 val = (insn >> 9) & 7;
1803 if (val == 0)
1804 val = 8;
1805 dest = tcg_temp_new();
1806 tcg_gen_mov_i32(dest, src1);
1807 if ((insn & 0x38) == 0x08) {
1808 /* Don't update condition codes if the destination is an
1809 address register. */
1810 if (insn & 0x0100) {
1811 tcg_gen_subi_i32(dest, dest, val);
1812 } else {
1813 tcg_gen_addi_i32(dest, dest, val);
1814 }
1815 } else {
1816 src2 = tcg_const_i32(val);
1817 if (insn & 0x0100) {
1818 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, src2);
1819 tcg_gen_sub_i32(dest, dest, src2);
1820 set_cc_op(s, CC_OP_SUB);
1821 } else {
1822 tcg_gen_add_i32(dest, dest, src2);
1823 tcg_gen_setcond_i32(TCG_COND_LTU, QREG_CC_X, dest, src2);
1824 set_cc_op(s, CC_OP_ADD);
1825 }
1826 gen_update_cc_add(dest, src2);
1827 }
1828 DEST_EA(env, insn, OS_LONG, dest, &addr);
1829 }
1830
1831 DISAS_INSN(tpf)
1832 {
1833 switch (insn & 7) {
1834 case 2: /* One extension word. */
1835 s->pc += 2;
1836 break;
1837 case 3: /* Two extension words. */
1838 s->pc += 4;
1839 break;
1840 case 4: /* No extension words. */
1841 break;
1842 default:
1843 disas_undef(env, s, insn);
1844 }
1845 }
1846
1847 DISAS_INSN(branch)
1848 {
1849 int32_t offset;
1850 uint32_t base;
1851 int op;
1852 TCGLabel *l1;
1853
1854 base = s->pc;
1855 op = (insn >> 8) & 0xf;
1856 offset = (int8_t)insn;
1857 if (offset == 0) {
1858 offset = (int16_t)read_im16(env, s);
1859 } else if (offset == -1) {
1860 offset = read_im32(env, s);
1861 }
1862 if (op == 1) {
1863 /* bsr */
1864 gen_push(s, tcg_const_i32(s->pc));
1865 }
1866 if (op > 1) {
1867 /* Bcc */
1868 l1 = gen_new_label();
1869 gen_jmpcc(s, ((insn >> 8) & 0xf) ^ 1, l1);
1870 gen_jmp_tb(s, 1, base + offset);
1871 gen_set_label(l1);
1872 gen_jmp_tb(s, 0, s->pc);
1873 } else {
1874 /* Unconditional branch. */
1875 gen_jmp_tb(s, 0, base + offset);
1876 }
1877 }
1878
1879 DISAS_INSN(moveq)
1880 {
1881 uint32_t val;
1882
1883 val = (int8_t)insn;
1884 tcg_gen_movi_i32(DREG(insn, 9), val);
1885 gen_logic_cc(s, tcg_const_i32(val), OS_LONG);
1886 }
1887
1888 DISAS_INSN(mvzs)
1889 {
1890 int opsize;
1891 TCGv src;
1892 TCGv reg;
1893
1894 if (insn & 0x40)
1895 opsize = OS_WORD;
1896 else
1897 opsize = OS_BYTE;
1898 SRC_EA(env, src, opsize, (insn & 0x80) == 0, NULL);
1899 reg = DREG(insn, 9);
1900 tcg_gen_mov_i32(reg, src);
1901 gen_logic_cc(s, src, opsize);
1902 }
1903
1904 DISAS_INSN(or)
1905 {
1906 TCGv reg;
1907 TCGv dest;
1908 TCGv src;
1909 TCGv addr;
1910
1911 reg = DREG(insn, 9);
1912 dest = tcg_temp_new();
1913 if (insn & 0x100) {
1914 SRC_EA(env, src, OS_LONG, 0, &addr);
1915 tcg_gen_or_i32(dest, src, reg);
1916 DEST_EA(env, insn, OS_LONG, dest, &addr);
1917 } else {
1918 SRC_EA(env, src, OS_LONG, 0, NULL);
1919 tcg_gen_or_i32(dest, src, reg);
1920 tcg_gen_mov_i32(reg, dest);
1921 }
1922 gen_logic_cc(s, dest, OS_LONG);
1923 }
1924
1925 DISAS_INSN(suba)
1926 {
1927 TCGv src;
1928 TCGv reg;
1929
1930 SRC_EA(env, src, OS_LONG, 0, NULL);
1931 reg = AREG(insn, 9);
1932 tcg_gen_sub_i32(reg, reg, src);
1933 }
1934
1935 DISAS_INSN(subx)
1936 {
1937 TCGv reg;
1938 TCGv src;
1939
1940 gen_flush_flags(s);
1941 reg = DREG(insn, 9);
1942 src = DREG(insn, 0);
1943 gen_helper_subx_cc(reg, cpu_env, reg, src);
1944 }
1945
1946 DISAS_INSN(mov3q)
1947 {
1948 TCGv src;
1949 int val;
1950
1951 val = (insn >> 9) & 7;
1952 if (val == 0)
1953 val = -1;
1954 src = tcg_const_i32(val);
1955 gen_logic_cc(s, src, OS_LONG);
1956 DEST_EA(env, insn, OS_LONG, src, NULL);
1957 }
1958
1959 DISAS_INSN(cmp)
1960 {
1961 TCGv src;
1962 TCGv reg;
1963 int opsize;
1964
1965 opsize = insn_opsize(insn);
1966 SRC_EA(env, src, opsize, -1, NULL);
1967 reg = DREG(insn, 9);
1968 gen_update_cc_add(reg, src);
1969 set_cc_op(s, CC_OP_CMP);
1970 }
1971
1972 DISAS_INSN(cmpa)
1973 {
1974 int opsize;
1975 TCGv src;
1976 TCGv reg;
1977
1978 if (insn & 0x100) {
1979 opsize = OS_LONG;
1980 } else {
1981 opsize = OS_WORD;
1982 }
1983 SRC_EA(env, src, opsize, 1, NULL);
1984 reg = AREG(insn, 9);
1985 gen_update_cc_add(reg, src);
1986 set_cc_op(s, CC_OP_CMP);
1987 }
1988
1989 DISAS_INSN(eor)
1990 {
1991 TCGv src;
1992 TCGv reg;
1993 TCGv dest;
1994 TCGv addr;
1995
1996 SRC_EA(env, src, OS_LONG, 0, &addr);
1997 reg = DREG(insn, 9);
1998 dest = tcg_temp_new();
1999 tcg_gen_xor_i32(dest, src, reg);
2000 gen_logic_cc(s, dest, OS_LONG);
2001 DEST_EA(env, insn, OS_LONG, dest, &addr);
2002 }
2003
2004 DISAS_INSN(and)
2005 {
2006 TCGv src;
2007 TCGv reg;
2008 TCGv dest;
2009 TCGv addr;
2010
2011 reg = DREG(insn, 9);
2012 dest = tcg_temp_new();
2013 if (insn & 0x100) {
2014 SRC_EA(env, src, OS_LONG, 0, &addr);
2015 tcg_gen_and_i32(dest, src, reg);
2016 DEST_EA(env, insn, OS_LONG, dest, &addr);
2017 } else {
2018 SRC_EA(env, src, OS_LONG, 0, NULL);
2019 tcg_gen_and_i32(dest, src, reg);
2020 tcg_gen_mov_i32(reg, dest);
2021 }
2022 gen_logic_cc(s, dest, OS_LONG);
2023 }
2024
2025 DISAS_INSN(adda)
2026 {
2027 TCGv src;
2028 TCGv reg;
2029
2030 SRC_EA(env, src, OS_LONG, 0, NULL);
2031 reg = AREG(insn, 9);
2032 tcg_gen_add_i32(reg, reg, src);
2033 }
2034
2035 DISAS_INSN(addx)
2036 {
2037 TCGv reg;
2038 TCGv src;
2039
2040 gen_flush_flags(s);
2041 reg = DREG(insn, 9);
2042 src = DREG(insn, 0);
2043 gen_helper_addx_cc(reg, cpu_env, reg, src);
2044 }
2045
2046 /* TODO: This could be implemented without helper functions. */
2047 DISAS_INSN(shift_im)
2048 {
2049 TCGv reg;
2050 int tmp;
2051 TCGv shift;
2052
2053 set_cc_op(s, CC_OP_FLAGS);
2054
2055 reg = DREG(insn, 0);
2056 tmp = (insn >> 9) & 7;
2057 if (tmp == 0)
2058 tmp = 8;
2059 shift = tcg_const_i32(tmp);
2060 /* No need to flush flags becuse we know we will set C flag. */
2061 if (insn & 0x100) {
2062 gen_helper_shl_cc(reg, cpu_env, reg, shift);
2063 } else {
2064 if (insn & 8) {
2065 gen_helper_shr_cc(reg, cpu_env, reg, shift);
2066 } else {
2067 gen_helper_sar_cc(reg, cpu_env, reg, shift);
2068 }
2069 }
2070 }
2071
2072 DISAS_INSN(shift_reg)
2073 {
2074 TCGv reg;
2075 TCGv shift;
2076
2077 reg = DREG(insn, 0);
2078 shift = DREG(insn, 9);
2079 if (insn & 0x100) {
2080 gen_helper_shl_cc(reg, cpu_env, reg, shift);
2081 } else {
2082 if (insn & 8) {
2083 gen_helper_shr_cc(reg, cpu_env, reg, shift);
2084 } else {
2085 gen_helper_sar_cc(reg, cpu_env, reg, shift);
2086 }
2087 }
2088 set_cc_op(s, CC_OP_FLAGS);
2089 }
2090
2091 DISAS_INSN(ff1)
2092 {
2093 TCGv reg;
2094 reg = DREG(insn, 0);
2095 gen_logic_cc(s, reg, OS_LONG);
2096 gen_helper_ff1(reg, reg);
2097 }
2098
2099 static TCGv gen_get_sr(DisasContext *s)
2100 {
2101 TCGv ccr;
2102 TCGv sr;
2103
2104 ccr = gen_get_ccr(s);
2105 sr = tcg_temp_new();
2106 tcg_gen_andi_i32(sr, QREG_SR, 0xffe0);
2107 tcg_gen_or_i32(sr, sr, ccr);
2108 return sr;
2109 }
2110
2111 DISAS_INSN(strldsr)
2112 {
2113 uint16_t ext;
2114 uint32_t addr;
2115
2116 addr = s->pc - 2;
2117 ext = read_im16(env, s);
2118 if (ext != 0x46FC) {
2119 gen_exception(s, addr, EXCP_UNSUPPORTED);
2120 return;
2121 }
2122 ext = read_im16(env, s);
2123 if (IS_USER(s) || (ext & SR_S) == 0) {
2124 gen_exception(s, addr, EXCP_PRIVILEGE);
2125 return;
2126 }
2127 gen_push(s, gen_get_sr(s));
2128 gen_set_sr_im(s, ext, 0);
2129 }
2130
2131 DISAS_INSN(move_from_sr)
2132 {
2133 TCGv sr;
2134
2135 if (IS_USER(s) && !m68k_feature(env, M68K_FEATURE_M68000)) {
2136 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2137 return;
2138 }
2139 sr = gen_get_sr(s);
2140 DEST_EA(env, insn, OS_WORD, sr, NULL);
2141 }
2142
2143 DISAS_INSN(move_to_sr)
2144 {
2145 if (IS_USER(s)) {
2146 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2147 return;
2148 }
2149 gen_set_sr(env, s, insn, 0);
2150 gen_lookup_tb(s);
2151 }
2152
2153 DISAS_INSN(move_from_usp)
2154 {
2155 if (IS_USER(s)) {
2156 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2157 return;
2158 }
2159 tcg_gen_ld_i32(AREG(insn, 0), cpu_env,
2160 offsetof(CPUM68KState, sp[M68K_USP]));
2161 }
2162
2163 DISAS_INSN(move_to_usp)
2164 {
2165 if (IS_USER(s)) {
2166 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2167 return;
2168 }
2169 tcg_gen_st_i32(AREG(insn, 0), cpu_env,
2170 offsetof(CPUM68KState, sp[M68K_USP]));
2171 }
2172
2173 DISAS_INSN(halt)
2174 {
2175 gen_exception(s, s->pc, EXCP_HALT_INSN);
2176 }
2177
2178 DISAS_INSN(stop)
2179 {
2180 uint16_t ext;
2181
2182 if (IS_USER(s)) {
2183 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2184 return;
2185 }
2186
2187 ext = read_im16(env, s);
2188
2189 gen_set_sr_im(s, ext, 0);
2190 tcg_gen_movi_i32(cpu_halted, 1);
2191 gen_exception(s, s->pc, EXCP_HLT);
2192 }
2193
2194 DISAS_INSN(rte)
2195 {
2196 if (IS_USER(s)) {
2197 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2198 return;
2199 }
2200 gen_exception(s, s->pc - 2, EXCP_RTE);
2201 }
2202
2203 DISAS_INSN(movec)
2204 {
2205 uint16_t ext;
2206 TCGv reg;
2207
2208 if (IS_USER(s)) {
2209 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2210 return;
2211 }
2212
2213 ext = read_im16(env, s);
2214
2215 if (ext & 0x8000) {
2216 reg = AREG(ext, 12);
2217 } else {
2218 reg = DREG(ext, 12);
2219 }
2220 gen_helper_movec(cpu_env, tcg_const_i32(ext & 0xfff), reg);
2221 gen_lookup_tb(s);
2222 }
2223
2224 DISAS_INSN(intouch)
2225 {
2226 if (IS_USER(s)) {
2227 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2228 return;
2229 }
2230 /* ICache fetch. Implement as no-op. */
2231 }
2232
2233 DISAS_INSN(cpushl)
2234 {
2235 if (IS_USER(s)) {
2236 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2237 return;
2238 }
2239 /* Cache push/invalidate. Implement as no-op. */
2240 }
2241
2242 DISAS_INSN(wddata)
2243 {
2244 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2245 }
2246
2247 DISAS_INSN(wdebug)
2248 {
2249 M68kCPU *cpu = m68k_env_get_cpu(env);
2250
2251 if (IS_USER(s)) {
2252 gen_exception(s, s->pc - 2, EXCP_PRIVILEGE);
2253 return;
2254 }
2255 /* TODO: Implement wdebug. */
2256 cpu_abort(CPU(cpu), "WDEBUG not implemented");
2257 }
2258
2259 DISAS_INSN(trap)
2260 {
2261 gen_exception(s, s->pc - 2, EXCP_TRAP0 + (insn & 0xf));
2262 }
2263
2264 /* ??? FP exceptions are not implemented. Most exceptions are deferred until
2265 immediately before the next FP instruction is executed. */
2266 DISAS_INSN(fpu)
2267 {
2268 uint16_t ext;
2269 int32_t offset;
2270 int opmode;
2271 TCGv_i64 src;
2272 TCGv_i64 dest;
2273 TCGv_i64 res;
2274 TCGv tmp32;
2275 int round;
2276 int set_dest;
2277 int opsize;
2278
2279 ext = read_im16(env, s);
2280 opmode = ext & 0x7f;
2281 switch ((ext >> 13) & 7) {
2282 case 0: case 2:
2283 break;
2284 case 1:
2285 goto undef;
2286 case 3: /* fmove out */
2287 src = FREG(ext, 7);
2288 tmp32 = tcg_temp_new_i32();
2289 /* fmove */
2290 /* ??? TODO: Proper behavior on overflow. */
2291 switch ((ext >> 10) & 7) {
2292 case 0:
2293 opsize = OS_LONG;
2294 gen_helper_f64_to_i32(tmp32, cpu_env, src);
2295 break;
2296 case 1:
2297 opsize = OS_SINGLE;
2298 gen_helper_f64_to_f32(tmp32, cpu_env, src);
2299 break;
2300 case 4:
2301 opsize = OS_WORD;
2302 gen_helper_f64_to_i32(tmp32, cpu_env, src);
2303 break;
2304 case 5: /* OS_DOUBLE */
2305 tcg_gen_mov_i32(tmp32, AREG(insn, 0));
2306 switch ((insn >> 3) & 7) {
2307 case 2:
2308 case 3:
2309 break;
2310 case 4:
2311 tcg_gen_addi_i32(tmp32, tmp32, -8);
2312 break;
2313 case 5:
2314 offset = cpu_ldsw_code(env, s->pc);
2315 s->pc += 2;
2316 tcg_gen_addi_i32(tmp32, tmp32, offset);
2317 break;
2318 default:
2319 goto undef;
2320 }
2321 gen_store64(s, tmp32, src);
2322 switch ((insn >> 3) & 7) {
2323 case 3:
2324 tcg_gen_addi_i32(tmp32, tmp32, 8);
2325 tcg_gen_mov_i32(AREG(insn, 0), tmp32);
2326 break;
2327 case 4:
2328 tcg_gen_mov_i32(AREG(insn, 0), tmp32);
2329 break;
2330 }
2331 tcg_temp_free_i32(tmp32);
2332 return;
2333 case 6:
2334 opsize = OS_BYTE;
2335 gen_helper_f64_to_i32(tmp32, cpu_env, src);
2336 break;
2337 default:
2338 goto undef;
2339 }
2340 DEST_EA(env, insn, opsize, tmp32, NULL);
2341 tcg_temp_free_i32(tmp32);
2342 return;
2343 case 4: /* fmove to control register. */
2344 switch ((ext >> 10) & 7) {
2345 case 4: /* FPCR */
2346 /* Not implemented. Ignore writes. */
2347 break;
2348 case 1: /* FPIAR */
2349 case 2: /* FPSR */
2350 default:
2351 cpu_abort(NULL, "Unimplemented: fmove to control %d",
2352 (ext >> 10) & 7);
2353 }
2354 break;
2355 case 5: /* fmove from control register. */
2356 switch ((ext >> 10) & 7) {
2357 case 4: /* FPCR */
2358 /* Not implemented. Always return zero. */
2359 tmp32 = tcg_const_i32(0);
2360 break;
2361 case 1: /* FPIAR */
2362 case 2: /* FPSR */
2363 default:
2364 cpu_abort(NULL, "Unimplemented: fmove from control %d",
2365 (ext >> 10) & 7);
2366 goto undef;
2367 }
2368 DEST_EA(env, insn, OS_LONG, tmp32, NULL);
2369 break;
2370 case 6: /* fmovem */
2371 case 7:
2372 {
2373 TCGv addr;
2374 uint16_t mask;
2375 int i;
2376 if ((ext & 0x1f00) != 0x1000 || (ext & 0xff) == 0)
2377 goto undef;
2378 tmp32 = gen_lea(env, s, insn, OS_LONG);
2379 if (IS_NULL_QREG(tmp32)) {
2380 gen_addr_fault(s);
2381 return;
2382 }
2383 addr = tcg_temp_new_i32();
2384 tcg_gen_mov_i32(addr, tmp32);
2385 mask = 0x80;
2386 for (i = 0; i < 8; i++) {
2387 if (ext & mask) {
2388 dest = FREG(i, 0);
2389 if (ext & (1 << 13)) {
2390 /* store */
2391 tcg_gen_qemu_stf64(dest, addr, IS_USER(s));
2392 } else {
2393 /* load */
2394 tcg_gen_qemu_ldf64(dest, addr, IS_USER(s));
2395 }
2396 if (ext & (mask - 1))
2397 tcg_gen_addi_i32(addr, addr, 8);
2398 }
2399 mask >>= 1;
2400 }
2401 tcg_temp_free_i32(addr);
2402 }
2403 return;
2404 }
2405 if (ext & (1 << 14)) {
2406 /* Source effective address. */
2407 switch ((ext >> 10) & 7) {
2408 case 0: opsize = OS_LONG; break;
2409 case 1: opsize = OS_SINGLE; break;
2410 case 4: opsize = OS_WORD; break;
2411 case 5: opsize = OS_DOUBLE; break;
2412 case 6: opsize = OS_BYTE; break;
2413 default:
2414 goto undef;
2415 }
2416 if (opsize == OS_DOUBLE) {
2417 tmp32 = tcg_temp_new_i32();
2418 tcg_gen_mov_i32(tmp32, AREG(insn, 0));
2419 switch ((insn >> 3) & 7) {
2420 case 2:
2421 case 3:
2422 break;
2423 case 4:
2424 tcg_gen_addi_i32(tmp32, tmp32, -8);
2425 break;
2426 case 5:
2427 offset = cpu_ldsw_code(env, s->pc);
2428 s->pc += 2;
2429 tcg_gen_addi_i32(tmp32, tmp32, offset);
2430 break;
2431 case 7:
2432 offset = cpu_ldsw_code(env, s->pc);
2433 offset += s->pc - 2;
2434 s->pc += 2;
2435 tcg_gen_addi_i32(tmp32, tmp32, offset);
2436 break;
2437 default:
2438 goto undef;
2439 }
2440 src = gen_load64(s, tmp32);
2441 switch ((insn >> 3) & 7) {
2442 case 3:
2443 tcg_gen_addi_i32(tmp32, tmp32, 8);
2444 tcg_gen_mov_i32(AREG(insn, 0), tmp32);
2445 break;
2446 case 4:
2447 tcg_gen_mov_i32(AREG(insn, 0), tmp32);
2448 break;
2449 }
2450 tcg_temp_free_i32(tmp32);
2451 } else {
2452 SRC_EA(env, tmp32, opsize, 1, NULL);
2453 src = tcg_temp_new_i64();
2454 switch (opsize) {
2455 case OS_LONG:
2456 case OS_WORD:
2457 case OS_BYTE:
2458 gen_helper_i32_to_f64(src, cpu_env, tmp32);
2459 break;
2460 case OS_SINGLE:
2461 gen_helper_f32_to_f64(src, cpu_env, tmp32);
2462 break;
2463 }
2464 }
2465 } else {
2466 /* Source register. */
2467 src = FREG(ext, 10);
2468 }
2469 dest = FREG(ext, 7);
2470 res = tcg_temp_new_i64();
2471 if (opmode != 0x3a)
2472 tcg_gen_mov_f64(res, dest);
2473 round = 1;
2474 set_dest = 1;
2475 switch (opmode) {
2476 case 0: case 0x40: case 0x44: /* fmove */
2477 tcg_gen_mov_f64(res, src);
2478 break;
2479 case 1: /* fint */
2480 gen_helper_iround_f64(res, cpu_env, src);
2481 round = 0;
2482 break;
2483 case 3: /* fintrz */
2484 gen_helper_itrunc_f64(res, cpu_env, src);
2485 round = 0;
2486 break;
2487 case 4: case 0x41: case 0x45: /* fsqrt */
2488 gen_helper_sqrt_f64(res, cpu_env, src);
2489 break;
2490 case 0x18: case 0x58: case 0x5c: /* fabs */
2491 gen_helper_abs_f64(res, src);
2492 break;
2493 case 0x1a: case 0x5a: case 0x5e: /* fneg */
2494 gen_helper_chs_f64(res, src);
2495 break;
2496 case 0x20: case 0x60: case 0x64: /* fdiv */
2497 gen_helper_div_f64(res, cpu_env, res, src);
2498 break;
2499 case 0x22: case 0x62: case 0x66: /* fadd */
2500 gen_helper_add_f64(res, cpu_env, res, src);
2501 break;
2502 case 0x23: case 0x63: case 0x67: /* fmul */
2503 gen_helper_mul_f64(res, cpu_env, res, src);
2504 break;
2505 case 0x28: case 0x68: case 0x6c: /* fsub */
2506 gen_helper_sub_f64(res, cpu_env, res, src);
2507 break;
2508 case 0x38: /* fcmp */
2509 gen_helper_sub_cmp_f64(res, cpu_env, res, src);
2510 set_dest = 0;
2511 round = 0;
2512 break;
2513 case 0x3a: /* ftst */
2514 tcg_gen_mov_f64(res, src);
2515 set_dest = 0;
2516 round = 0;
2517 break;
2518 default:
2519 goto undef;
2520 }
2521 if (ext & (1 << 14)) {
2522 tcg_temp_free_i64(src);
2523 }
2524 if (round) {
2525 if (opmode & 0x40) {
2526 if ((opmode & 0x4) != 0)
2527 round = 0;
2528 } else if ((s->fpcr & M68K_FPCR_PREC) == 0) {
2529 round = 0;
2530 }
2531 }
2532 if (round) {
2533 TCGv tmp = tcg_temp_new_i32();
2534 gen_helper_f64_to_f32(tmp, cpu_env, res);
2535 gen_helper_f32_to_f64(res, cpu_env, tmp);
2536 tcg_temp_free_i32(tmp);
2537 }
2538 tcg_gen_mov_f64(QREG_FP_RESULT, res);
2539 if (set_dest) {
2540 tcg_gen_mov_f64(dest, res);
2541 }
2542 tcg_temp_free_i64(res);
2543 return;
2544 undef:
2545 /* FIXME: Is this right for offset addressing modes? */
2546 s->pc -= 2;
2547 disas_undef_fpu(env, s, insn);
2548 }
2549
2550 DISAS_INSN(fbcc)
2551 {
2552 uint32_t offset;
2553 uint32_t addr;
2554 TCGv flag;
2555 TCGLabel *l1;
2556
2557 addr = s->pc;
2558 offset = cpu_ldsw_code(env, s->pc);
2559 s->pc += 2;
2560 if (insn & (1 << 6)) {
2561 offset = (offset << 16) | read_im16(env, s);
2562 }
2563
2564 l1 = gen_new_label();
2565 /* TODO: Raise BSUN exception. */
2566 flag = tcg_temp_new();
2567 gen_helper_compare_f64(flag, cpu_env, QREG_FP_RESULT);
2568 /* Jump to l1 if condition is true. */
2569 switch (insn & 0xf) {
2570 case 0: /* f */
2571 break;
2572 case 1: /* eq (=0) */
2573 tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(0), l1);
2574 break;
2575 case 2: /* ogt (=1) */
2576 tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(1), l1);
2577 break;
2578 case 3: /* oge (=0 or =1) */
2579 tcg_gen_brcond_i32(TCG_COND_LEU, flag, tcg_const_i32(1), l1);
2580 break;
2581 case 4: /* olt (=-1) */
2582 tcg_gen_brcond_i32(TCG_COND_LT, flag, tcg_const_i32(0), l1);
2583 break;
2584 case 5: /* ole (=-1 or =0) */
2585 tcg_gen_brcond_i32(TCG_COND_LE, flag, tcg_const_i32(0), l1);
2586 break;
2587 case 6: /* ogl (=-1 or =1) */
2588 tcg_gen_andi_i32(flag, flag, 1);
2589 tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(0), l1);
2590 break;
2591 case 7: /* or (=2) */
2592 tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(2), l1);
2593 break;
2594 case 8: /* un (<2) */
2595 tcg_gen_brcond_i32(TCG_COND_LT, flag, tcg_const_i32(2), l1);
2596 break;
2597 case 9: /* ueq (=0 or =2) */
2598 tcg_gen_andi_i32(flag, flag, 1);
2599 tcg_gen_brcond_i32(TCG_COND_EQ, flag, tcg_const_i32(0), l1);
2600 break;
2601 case 10: /* ugt (>0) */
2602 tcg_gen_brcond_i32(TCG_COND_GT, flag, tcg_const_i32(0), l1);
2603 break;
2604 case 11: /* uge (>=0) */
2605 tcg_gen_brcond_i32(TCG_COND_GE, flag, tcg_const_i32(0), l1);
2606 break;
2607 case 12: /* ult (=-1 or =2) */
2608 tcg_gen_brcond_i32(TCG_COND_GEU, flag, tcg_const_i32(2), l1);
2609 break;
2610 case 13: /* ule (!=1) */
2611 tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(1), l1);
2612 break;
2613 case 14: /* ne (!=0) */
2614 tcg_gen_brcond_i32(TCG_COND_NE, flag, tcg_const_i32(0), l1);
2615 break;
2616 case 15: /* t */
2617 tcg_gen_br(l1);
2618 break;
2619 }
2620 gen_jmp_tb(s, 0, s->pc);
2621 gen_set_label(l1);
2622 gen_jmp_tb(s, 1, addr + offset);
2623 }
2624
2625 DISAS_INSN(frestore)
2626 {
2627 M68kCPU *cpu = m68k_env_get_cpu(env);
2628
2629 /* TODO: Implement frestore. */
2630 cpu_abort(CPU(cpu), "FRESTORE not implemented");
2631 }
2632
2633 DISAS_INSN(fsave)
2634 {
2635 M68kCPU *cpu = m68k_env_get_cpu(env);
2636
2637 /* TODO: Implement fsave. */
2638 cpu_abort(CPU(cpu), "FSAVE not implemented");
2639 }
2640
2641 static inline TCGv gen_mac_extract_word(DisasContext *s, TCGv val, int upper)
2642 {
2643 TCGv tmp = tcg_temp_new();
2644 if (s->env->macsr & MACSR_FI) {
2645 if (upper)
2646 tcg_gen_andi_i32(tmp, val, 0xffff0000);
2647 else
2648 tcg_gen_shli_i32(tmp, val, 16);
2649 } else if (s->env->macsr & MACSR_SU) {
2650 if (upper)
2651 tcg_gen_sari_i32(tmp, val, 16);
2652 else
2653 tcg_gen_ext16s_i32(tmp, val);
2654 } else {
2655 if (upper)
2656 tcg_gen_shri_i32(tmp, val, 16);
2657 else
2658 tcg_gen_ext16u_i32(tmp, val);
2659 }
2660 return tmp;
2661 }
2662
2663 static void gen_mac_clear_flags(void)
2664 {
2665 tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR,
2666 ~(MACSR_V | MACSR_Z | MACSR_N | MACSR_EV));
2667 }
2668
2669 DISAS_INSN(mac)
2670 {
2671 TCGv rx;
2672 TCGv ry;
2673 uint16_t ext;
2674 int acc;
2675 TCGv tmp;
2676 TCGv addr;
2677 TCGv loadval;
2678 int dual;
2679 TCGv saved_flags;
2680
2681 if (!s->done_mac) {
2682 s->mactmp = tcg_temp_new_i64();
2683 s->done_mac = 1;
2684 }
2685
2686 ext = read_im16(env, s);
2687
2688 acc = ((insn >> 7) & 1) | ((ext >> 3) & 2);
2689 dual = ((insn & 0x30) != 0 && (ext & 3) != 0);
2690 if (dual && !m68k_feature(s->env, M68K_FEATURE_CF_EMAC_B)) {
2691 disas_undef(env, s, insn);
2692 return;
2693 }
2694 if (insn & 0x30) {
2695 /* MAC with load. */
2696 tmp = gen_lea(env, s, insn, OS_LONG);
2697 addr = tcg_temp_new();
2698 tcg_gen_and_i32(addr, tmp, QREG_MAC_MASK);
2699 /* Load the value now to ensure correct exception behavior.
2700 Perform writeback after reading the MAC inputs. */
2701 loadval = gen_load(s, OS_LONG, addr, 0);
2702
2703 acc ^= 1;
2704 rx = (ext & 0x8000) ? AREG(ext, 12) : DREG(insn, 12);
2705 ry = (ext & 8) ? AREG(ext, 0) : DREG(ext, 0);
2706 } else {
2707 loadval = addr = NULL_QREG;
2708 rx = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9);
2709 ry = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
2710 }
2711
2712 gen_mac_clear_flags();
2713 #if 0
2714 l1 = -1;
2715 /* Disabled because conditional branches clobber temporary vars. */
2716 if ((s->env->macsr & MACSR_OMC) != 0 && !dual) {
2717 /* Skip the multiply if we know we will ignore it. */
2718 l1 = gen_new_label();
2719 tmp = tcg_temp_new();
2720 tcg_gen_andi_i32(tmp, QREG_MACSR, 1 << (acc + 8));
2721 gen_op_jmp_nz32(tmp, l1);
2722 }
2723 #endif
2724
2725 if ((ext & 0x0800) == 0) {
2726 /* Word. */
2727 rx = gen_mac_extract_word(s, rx, (ext & 0x80) != 0);
2728 ry = gen_mac_extract_word(s, ry, (ext & 0x40) != 0);
2729 }
2730 if (s->env->macsr & MACSR_FI) {
2731 gen_helper_macmulf(s->mactmp, cpu_env, rx, ry);
2732 } else {
2733 if (s->env->macsr & MACSR_SU)
2734 gen_helper_macmuls(s->mactmp, cpu_env, rx, ry);
2735 else
2736 gen_helper_macmulu(s->mactmp, cpu_env, rx, ry);
2737 switch ((ext >> 9) & 3) {
2738 case 1:
2739 tcg_gen_shli_i64(s->mactmp, s->mactmp, 1);
2740 break;
2741 case 3:
2742 tcg_gen_shri_i64(s->mactmp, s->mactmp, 1);
2743 break;
2744 }
2745 }
2746
2747 if (dual) {
2748 /* Save the overflow flag from the multiply. */
2749 saved_flags = tcg_temp_new();
2750 tcg_gen_mov_i32(saved_flags, QREG_MACSR);
2751 } else {
2752 saved_flags = NULL_QREG;
2753 }
2754
2755 #if 0
2756 /* Disabled because conditional branches clobber temporary vars. */
2757 if ((s->env->macsr & MACSR_OMC) != 0 && dual) {
2758 /* Skip the accumulate if the value is already saturated. */
2759 l1 = gen_new_label();
2760 tmp = tcg_temp_new();
2761 gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc));
2762 gen_op_jmp_nz32(tmp, l1);
2763 }
2764 #endif
2765
2766 if (insn & 0x100)
2767 tcg_gen_sub_i64(MACREG(acc), MACREG(acc), s->mactmp);
2768 else
2769 tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp);
2770
2771 if (s->env->macsr & MACSR_FI)
2772 gen_helper_macsatf(cpu_env, tcg_const_i32(acc));
2773 else if (s->env->macsr & MACSR_SU)
2774 gen_helper_macsats(cpu_env, tcg_const_i32(acc));
2775 else
2776 gen_helper_macsatu(cpu_env, tcg_const_i32(acc));
2777
2778 #if 0
2779 /* Disabled because conditional branches clobber temporary vars. */
2780 if (l1 != -1)
2781 gen_set_label(l1);
2782 #endif
2783
2784 if (dual) {
2785 /* Dual accumulate variant. */
2786 acc = (ext >> 2) & 3;
2787 /* Restore the overflow flag from the multiplier. */
2788 tcg_gen_mov_i32(QREG_MACSR, saved_flags);
2789 #if 0
2790 /* Disabled because conditional branches clobber temporary vars. */
2791 if ((s->env->macsr & MACSR_OMC) != 0) {
2792 /* Skip the accumulate if the value is already saturated. */
2793 l1 = gen_new_label();
2794 tmp = tcg_temp_new();
2795 gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc));
2796 gen_op_jmp_nz32(tmp, l1);
2797 }
2798 #endif
2799 if (ext & 2)
2800 tcg_gen_sub_i64(MACREG(acc), MACREG(acc), s->mactmp);
2801 else
2802 tcg_gen_add_i64(MACREG(acc), MACREG(acc), s->mactmp);
2803 if (s->env->macsr & MACSR_FI)
2804 gen_helper_macsatf(cpu_env, tcg_const_i32(acc));
2805 else if (s->env->macsr & MACSR_SU)
2806 gen_helper_macsats(cpu_env, tcg_const_i32(acc));
2807 else
2808 gen_helper_macsatu(cpu_env, tcg_const_i32(acc));
2809 #if 0
2810 /* Disabled because conditional branches clobber temporary vars. */
2811 if (l1 != -1)
2812 gen_set_label(l1);
2813 #endif
2814 }
2815 gen_helper_mac_set_flags(cpu_env, tcg_const_i32(acc));
2816
2817 if (insn & 0x30) {
2818 TCGv rw;
2819 rw = (insn & 0x40) ? AREG(insn, 9) : DREG(insn, 9);
2820 tcg_gen_mov_i32(rw, loadval);
2821 /* FIXME: Should address writeback happen with the masked or
2822 unmasked value? */
2823 switch ((insn >> 3) & 7) {
2824 case 3: /* Post-increment. */
2825 tcg_gen_addi_i32(AREG(insn, 0), addr, 4);
2826 break;
2827 case 4: /* Pre-decrement. */
2828 tcg_gen_mov_i32(AREG(insn, 0), addr);
2829 }
2830 }
2831 }
2832
2833 DISAS_INSN(from_mac)
2834 {
2835 TCGv rx;
2836 TCGv_i64 acc;
2837 int accnum;
2838
2839 rx = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
2840 accnum = (insn >> 9) & 3;
2841 acc = MACREG(accnum);
2842 if (s->env->macsr & MACSR_FI) {
2843 gen_helper_get_macf(rx, cpu_env, acc);
2844 } else if ((s->env->macsr & MACSR_OMC) == 0) {
2845 tcg_gen_extrl_i64_i32(rx, acc);
2846 } else if (s->env->macsr & MACSR_SU) {
2847 gen_helper_get_macs(rx, acc);
2848 } else {
2849 gen_helper_get_macu(rx, acc);
2850 }
2851 if (insn & 0x40) {
2852 tcg_gen_movi_i64(acc, 0);
2853 tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum));
2854 }
2855 }
2856
2857 DISAS_INSN(move_mac)
2858 {
2859 /* FIXME: This can be done without a helper. */
2860 int src;
2861 TCGv dest;
2862 src = insn & 3;
2863 dest = tcg_const_i32((insn >> 9) & 3);
2864 gen_helper_mac_move(cpu_env, dest, tcg_const_i32(src));
2865 gen_mac_clear_flags();
2866 gen_helper_mac_set_flags(cpu_env, dest);
2867 }
2868
2869 DISAS_INSN(from_macsr)
2870 {
2871 TCGv reg;
2872
2873 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
2874 tcg_gen_mov_i32(reg, QREG_MACSR);
2875 }
2876
2877 DISAS_INSN(from_mask)
2878 {
2879 TCGv reg;
2880 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
2881 tcg_gen_mov_i32(reg, QREG_MAC_MASK);
2882 }
2883
2884 DISAS_INSN(from_mext)
2885 {
2886 TCGv reg;
2887 TCGv acc;
2888 reg = (insn & 8) ? AREG(insn, 0) : DREG(insn, 0);
2889 acc = tcg_const_i32((insn & 0x400) ? 2 : 0);
2890 if (s->env->macsr & MACSR_FI)
2891 gen_helper_get_mac_extf(reg, cpu_env, acc);
2892 else
2893 gen_helper_get_mac_exti(reg, cpu_env, acc);
2894 }
2895
2896 DISAS_INSN(macsr_to_ccr)
2897 {
2898 TCGv tmp = tcg_temp_new();
2899 tcg_gen_andi_i32(tmp, QREG_MACSR, 0xf);
2900 gen_helper_set_sr(cpu_env, tmp);
2901 tcg_temp_free(tmp);
2902 set_cc_op(s, CC_OP_FLAGS);
2903 }
2904
2905 DISAS_INSN(to_mac)
2906 {
2907 TCGv_i64 acc;
2908 TCGv val;
2909 int accnum;
2910 accnum = (insn >> 9) & 3;
2911 acc = MACREG(accnum);
2912 SRC_EA(env, val, OS_LONG, 0, NULL);
2913 if (s->env->macsr & MACSR_FI) {
2914 tcg_gen_ext_i32_i64(acc, val);
2915 tcg_gen_shli_i64(acc, acc, 8);
2916 } else if (s->env->macsr & MACSR_SU) {
2917 tcg_gen_ext_i32_i64(acc, val);
2918 } else {
2919 tcg_gen_extu_i32_i64(acc, val);
2920 }
2921 tcg_gen_andi_i32(QREG_MACSR, QREG_MACSR, ~(MACSR_PAV0 << accnum));
2922 gen_mac_clear_flags();
2923 gen_helper_mac_set_flags(cpu_env, tcg_const_i32(accnum));
2924 }
2925
2926 DISAS_INSN(to_macsr)
2927 {
2928 TCGv val;
2929 SRC_EA(env, val, OS_LONG, 0, NULL);
2930 gen_helper_set_macsr(cpu_env, val);
2931 gen_lookup_tb(s);
2932 }
2933
2934 DISAS_INSN(to_mask)
2935 {
2936 TCGv val;
2937 SRC_EA(env, val, OS_LONG, 0, NULL);
2938 tcg_gen_ori_i32(QREG_MAC_MASK, val, 0xffff0000);
2939 }
2940
2941 DISAS_INSN(to_mext)
2942 {
2943 TCGv val;
2944 TCGv acc;
2945 SRC_EA(env, val, OS_LONG, 0, NULL);
2946 acc = tcg_const_i32((insn & 0x400) ? 2 : 0);
2947 if (s->env->macsr & MACSR_FI)
2948 gen_helper_set_mac_extf(cpu_env, val, acc);
2949 else if (s->env->macsr & MACSR_SU)
2950 gen_helper_set_mac_exts(cpu_env, val, acc);
2951 else
2952 gen_helper_set_mac_extu(cpu_env, val, acc);
2953 }
2954
2955 static disas_proc opcode_table[65536];
2956
2957 static void
2958 register_opcode (disas_proc proc, uint16_t opcode, uint16_t mask)
2959 {
2960 int i;
2961 int from;
2962 int to;
2963
2964 /* Sanity check. All set bits must be included in the mask. */
2965 if (opcode & ~mask) {
2966 fprintf(stderr,
2967 "qemu internal error: bogus opcode definition %04x/%04x\n",
2968 opcode, mask);
2969 abort();
2970 }
2971 /* This could probably be cleverer. For now just optimize the case where
2972 the top bits are known. */
2973 /* Find the first zero bit in the mask. */
2974 i = 0x8000;
2975 while ((i & mask) != 0)
2976 i >>= 1;
2977 /* Iterate over all combinations of this and lower bits. */
2978 if (i == 0)
2979 i = 1;
2980 else
2981 i <<= 1;
2982 from = opcode & ~(i - 1);
2983 to = from + i;
2984 for (i = from; i < to; i++) {
2985 if ((i & mask) == opcode)
2986 opcode_table[i] = proc;
2987 }
2988 }
2989
2990 /* Register m68k opcode handlers. Order is important.
2991 Later insn override earlier ones. */
2992 void register_m68k_insns (CPUM68KState *env)
2993 {
2994 /* Build the opcode table only once to avoid
2995 multithreading issues. */
2996 if (opcode_table[0] != NULL) {
2997 return;
2998 }
2999
3000 /* use BASE() for instruction available
3001 * for CF_ISA_A and M68000.
3002 */
3003 #define BASE(name, opcode, mask) \
3004 register_opcode(disas_##name, 0x##opcode, 0x##mask)
3005 #define INSN(name, opcode, mask, feature) do { \
3006 if (m68k_feature(env, M68K_FEATURE_##feature)) \
3007 BASE(name, opcode, mask); \
3008 } while(0)
3009 BASE(undef, 0000, 0000);
3010 INSN(arith_im, 0080, fff8, CF_ISA_A);
3011 INSN(arith_im, 0000, ff00, M68000);
3012 INSN(undef, 00c0, ffc0, M68000);
3013 INSN(bitrev, 00c0, fff8, CF_ISA_APLUSC);
3014 BASE(bitop_reg, 0100, f1c0);
3015 BASE(bitop_reg, 0140, f1c0);
3016 BASE(bitop_reg, 0180, f1c0);
3017 BASE(bitop_reg, 01c0, f1c0);
3018 INSN(arith_im, 0280, fff8, CF_ISA_A);
3019 INSN(arith_im, 0200, ff00, M68000);
3020 INSN(undef, 02c0, ffc0, M68000);
3021 INSN(byterev, 02c0, fff8, CF_ISA_APLUSC);
3022 INSN(arith_im, 0480, fff8, CF_ISA_A);
3023 INSN(arith_im, 0400, ff00, M68000);
3024 INSN(undef, 04c0, ffc0, M68000);
3025 INSN(arith_im, 0600, ff00, M68000);
3026 INSN(undef, 06c0, ffc0, M68000);
3027 INSN(ff1, 04c0, fff8, CF_ISA_APLUSC);
3028 INSN(arith_im, 0680, fff8, CF_ISA_A);
3029 INSN(arith_im, 0c00, ff38, CF_ISA_A);
3030 INSN(arith_im, 0c00, ff00, M68000);
3031 BASE(bitop_im, 0800, ffc0);
3032 BASE(bitop_im, 0840, ffc0);
3033 BASE(bitop_im, 0880, ffc0);
3034 BASE(bitop_im, 08c0, ffc0);
3035 INSN(arith_im, 0a80, fff8, CF_ISA_A);
3036 INSN(arith_im, 0a00, ff00, M68000);
3037 BASE(move, 1000, f000);
3038 BASE(move, 2000, f000);
3039 BASE(move, 3000, f000);
3040 INSN(strldsr, 40e7, ffff, CF_ISA_APLUSC);
3041 INSN(negx, 4080, fff8, CF_ISA_A);
3042 INSN(move_from_sr, 40c0, fff8, CF_ISA_A);
3043 INSN(move_from_sr, 40c0, ffc0, M68000);
3044 BASE(lea, 41c0, f1c0);
3045 BASE(clr, 4200, ff00);
3046 BASE(undef, 42c0, ffc0);
3047 INSN(move_from_ccr, 42c0, fff8, CF_ISA_A);
3048 INSN(move_from_ccr, 42c0, ffc0, M68000);
3049 INSN(neg, 4480, fff8, CF_ISA_A);
3050 INSN(neg, 4400, ff00, M68000);
3051 INSN(undef, 44c0, ffc0, M68000);
3052 BASE(move_to_ccr, 44c0, ffc0);
3053 INSN(not, 4680, fff8, CF_ISA_A);
3054 INSN(not, 4600, ff00, M68000);
3055 INSN(undef, 46c0, ffc0, M68000);
3056 INSN(move_to_sr, 46c0, ffc0, CF_ISA_A);
3057 BASE(pea, 4840, ffc0);
3058 BASE(swap, 4840, fff8);
3059 BASE(movem, 48c0, fbc0);
3060 BASE(ext, 4880, fff8);
3061 BASE(ext, 48c0, fff8);
3062 BASE(ext, 49c0, fff8);
3063 BASE(tst, 4a00, ff00);
3064 INSN(tas, 4ac0, ffc0, CF_ISA_B);
3065 INSN(tas, 4ac0, ffc0, M68000);
3066 INSN(halt, 4ac8, ffff, CF_ISA_A);
3067 INSN(pulse, 4acc, ffff, CF_ISA_A);
3068 BASE(illegal, 4afc, ffff);
3069 INSN(mull, 4c00, ffc0, CF_ISA_A);
3070 INSN(mull, 4c00, ffc0, LONG_MULDIV);
3071 INSN(divl, 4c40, ffc0, CF_ISA_A);
3072 INSN(divl, 4c40, ffc0, LONG_MULDIV);
3073 INSN(sats, 4c80, fff8, CF_ISA_B);
3074 BASE(trap, 4e40, fff0);
3075 BASE(link, 4e50, fff8);
3076 BASE(unlk, 4e58, fff8);
3077 INSN(move_to_usp, 4e60, fff8, USP);
3078 INSN(move_from_usp, 4e68, fff8, USP);
3079 BASE(nop, 4e71, ffff);
3080 BASE(stop, 4e72, ffff);
3081 BASE(rte, 4e73, ffff);
3082 BASE(rts, 4e75, ffff);
3083 INSN(movec, 4e7b, ffff, CF_ISA_A);
3084 BASE(jump, 4e80, ffc0);
3085 INSN(jump, 4ec0, ffc0, CF_ISA_A);
3086 INSN(addsubq, 5180, f1c0, CF_ISA_A);
3087 INSN(jump, 4ec0, ffc0, M68000);
3088 INSN(addsubq, 5000, f080, M68000);
3089 INSN(addsubq, 5080, f0c0, M68000);
3090 INSN(scc, 50c0, f0f8, CF_ISA_A);
3091 INSN(addsubq, 5080, f1c0, CF_ISA_A);
3092 INSN(tpf, 51f8, fff8, CF_ISA_A);
3093
3094 /* Branch instructions. */
3095 BASE(branch, 6000, f000);
3096 /* Disable long branch instructions, then add back the ones we want. */
3097 BASE(undef, 60ff, f0ff); /* All long branches. */
3098 INSN(branch, 60ff, f0ff, CF_ISA_B);
3099 INSN(undef, 60ff, ffff, CF_ISA_B); /* bra.l */
3100 INSN(branch, 60ff, ffff, BRAL);
3101 INSN(branch, 60ff, f0ff, BCCL);
3102
3103 BASE(moveq, 7000, f100);
3104 INSN(mvzs, 7100, f100, CF_ISA_B);
3105 BASE(or, 8000, f000);
3106 BASE(divw, 80c0, f0c0);
3107 BASE(addsub, 9000, f000);
3108 INSN(subx, 9180, f1f8, CF_ISA_A);
3109 INSN(suba, 91c0, f1c0, CF_ISA_A);
3110
3111 BASE(undef_mac, a000, f000);
3112 INSN(mac, a000, f100, CF_EMAC);
3113 INSN(from_mac, a180, f9b0, CF_EMAC);
3114 INSN(move_mac, a110, f9fc, CF_EMAC);
3115 INSN(from_macsr,a980, f9f0, CF_EMAC);
3116 INSN(from_mask, ad80, fff0, CF_EMAC);
3117 INSN(from_mext, ab80, fbf0, CF_EMAC);
3118 INSN(macsr_to_ccr, a9c0, ffff, CF_EMAC);
3119 INSN(to_mac, a100, f9c0, CF_EMAC);
3120 INSN(to_macsr, a900, ffc0, CF_EMAC);
3121 INSN(to_mext, ab00, fbc0, CF_EMAC);
3122 INSN(to_mask, ad00, ffc0, CF_EMAC);
3123
3124 INSN(mov3q, a140, f1c0, CF_ISA_B);
3125 INSN(cmp, b000, f1c0, CF_ISA_B); /* cmp.b */
3126 INSN(cmp, b040, f1c0, CF_ISA_B); /* cmp.w */
3127 INSN(cmpa, b0c0, f1c0, CF_ISA_B); /* cmpa.w */
3128 INSN(cmp, b080, f1c0, CF_ISA_A);
3129 INSN(cmpa, b1c0, f1c0, CF_ISA_A);
3130 INSN(cmp, b000, f100, M68000);
3131 INSN(eor, b100, f100, M68000);
3132 INSN(cmpa, b0c0, f0c0, M68000);
3133 INSN(eor, b180, f1c0, CF_ISA_A);
3134 BASE(and, c000, f000);
3135 BASE(mulw, c0c0, f0c0);
3136 BASE(addsub, d000, f000);
3137 INSN(addx, d180, f1f8, CF_ISA_A);
3138 INSN(adda, d1c0, f1c0, CF_ISA_A);
3139 INSN(adda, d0c0, f0c0, M68000);
3140 INSN(shift_im, e080, f0f0, CF_ISA_A);
3141 INSN(shift_reg, e0a0, f0f0, CF_ISA_A);
3142 INSN(undef_fpu, f000, f000, CF_ISA_A);
3143 INSN(fpu, f200, ffc0, CF_FPU);
3144 INSN(fbcc, f280, ffc0, CF_FPU);
3145 INSN(frestore, f340, ffc0, CF_FPU);
3146 INSN(fsave, f340, ffc0, CF_FPU);
3147 INSN(intouch, f340, ffc0, CF_ISA_A);
3148 INSN(cpushl, f428, ff38, CF_ISA_A);
3149 INSN(wddata, fb00, ff00, CF_ISA_A);
3150 INSN(wdebug, fbc0, ffc0, CF_ISA_A);
3151 #undef INSN
3152 }
3153
3154 /* ??? Some of this implementation is not exception safe. We should always
3155 write back the result to memory before setting the condition codes. */
3156 static void disas_m68k_insn(CPUM68KState * env, DisasContext *s)
3157 {
3158 uint16_t insn;
3159
3160 insn = read_im16(env, s);
3161
3162 opcode_table[insn](env, s, insn);
3163 }
3164
3165 /* generate intermediate code for basic block 'tb'. */
3166 void gen_intermediate_code(CPUM68KState *env, TranslationBlock *tb)
3167 {
3168 M68kCPU *cpu = m68k_env_get_cpu(env);
3169 CPUState *cs = CPU(cpu);
3170 DisasContext dc1, *dc = &dc1;
3171 target_ulong pc_start;
3172 int pc_offset;
3173 int num_insns;
3174 int max_insns;
3175
3176 /* generate intermediate code */
3177 pc_start = tb->pc;
3178
3179 dc->tb = tb;
3180
3181 dc->env = env;
3182 dc->is_jmp = DISAS_NEXT;
3183 dc->pc = pc_start;
3184 dc->cc_op = CC_OP_DYNAMIC;
3185 dc->cc_op_synced = 1;
3186 dc->singlestep_enabled = cs->singlestep_enabled;
3187 dc->fpcr = env->fpcr;
3188 dc->user = (env->sr & SR_S) == 0;
3189 dc->done_mac = 0;
3190 num_insns = 0;
3191 max_insns = tb->cflags & CF_COUNT_MASK;
3192 if (max_insns == 0) {
3193 max_insns = CF_COUNT_MASK;
3194 }
3195 if (max_insns > TCG_MAX_INSNS) {
3196 max_insns = TCG_MAX_INSNS;
3197 }
3198
3199 gen_tb_start(tb);
3200 do {
3201 pc_offset = dc->pc - pc_start;
3202 gen_throws_exception = NULL;
3203 tcg_gen_insn_start(dc->pc, dc->cc_op);
3204 num_insns++;
3205
3206 if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
3207 gen_exception(dc, dc->pc, EXCP_DEBUG);
3208 dc->is_jmp = DISAS_JUMP;
3209 /* The address covered by the breakpoint must be included in
3210 [tb->pc, tb->pc + tb->size) in order to for it to be
3211 properly cleared -- thus we increment the PC here so that
3212 the logic setting tb->size below does the right thing. */
3213 dc->pc += 2;
3214 break;
3215 }
3216
3217 if (num_insns == max_insns && (tb->cflags & CF_LAST_IO)) {
3218 gen_io_start();
3219 }
3220
3221 dc->insn_pc = dc->pc;
3222 disas_m68k_insn(env, dc);
3223 } while (!dc->is_jmp && !tcg_op_buf_full() &&
3224 !cs->singlestep_enabled &&
3225 !singlestep &&
3226 (pc_offset) < (TARGET_PAGE_SIZE - 32) &&
3227 num_insns < max_insns);
3228
3229 if (tb->cflags & CF_LAST_IO)
3230 gen_io_end();
3231 if (unlikely(cs->singlestep_enabled)) {
3232 /* Make sure the pc is updated, and raise a debug exception. */
3233 if (!dc->is_jmp) {
3234 update_cc_op(dc);
3235 tcg_gen_movi_i32(QREG_PC, dc->pc);
3236 }
3237 gen_helper_raise_exception(cpu_env, tcg_const_i32(EXCP_DEBUG));
3238 } else {
3239 switch(dc->is_jmp) {
3240 case DISAS_NEXT:
3241 update_cc_op(dc);
3242 gen_jmp_tb(dc, 0, dc->pc);
3243 break;
3244 default:
3245 case DISAS_JUMP:
3246 case DISAS_UPDATE:
3247 update_cc_op(dc);
3248 /* indicate that the hash table must be used to find the next TB */
3249 tcg_gen_exit_tb(0);
3250 break;
3251 case DISAS_TB_JUMP:
3252 /* nothing more to generate */
3253 break;
3254 }
3255 }
3256 gen_tb_end(tb, num_insns);
3257
3258 #ifdef DEBUG_DISAS
3259 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
3260 && qemu_log_in_addr_range(pc_start)) {
3261 qemu_log("----------------\n");
3262 qemu_log("IN: %s\n", lookup_symbol(pc_start));
3263 log_target_disas(cs, pc_start, dc->pc - pc_start, 0);
3264 qemu_log("\n");
3265 }
3266 #endif
3267 tb->size = dc->pc - pc_start;
3268 tb->icount = num_insns;
3269 }
3270
3271 void m68k_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
3272 int flags)
3273 {
3274 M68kCPU *cpu = M68K_CPU(cs);
3275 CPUM68KState *env = &cpu->env;
3276 int i;
3277 uint16_t sr;
3278 CPU_DoubleU u;
3279 for (i = 0; i < 8; i++)
3280 {
3281 u.d = env->fregs[i];
3282 cpu_fprintf(f, "D%d = %08x A%d = %08x F%d = %08x%08x (%12g)\n",
3283 i, env->dregs[i], i, env->aregs[i],
3284 i, u.l.upper, u.l.lower, *(double *)&u.d);
3285 }
3286 cpu_fprintf (f, "PC = %08x ", env->pc);
3287 sr = env->sr | cpu_m68k_get_ccr(env);
3288 cpu_fprintf(f, "SR = %04x %c%c%c%c%c ", sr, (sr & CCF_X) ? 'X' : '-',
3289 (sr & CCF_N) ? 'N' : '-', (sr & CCF_Z) ? 'Z' : '-',
3290 (sr & CCF_V) ? 'V' : '-', (sr & CCF_C) ? 'C' : '-');
3291 cpu_fprintf (f, "FPRESULT = %12g\n", *(double *)&env->fp_result);
3292 }
3293
3294 void restore_state_to_opc(CPUM68KState *env, TranslationBlock *tb,
3295 target_ulong *data)
3296 {
3297 int cc_op = data[1];
3298 env->pc = data[0];
3299 if (cc_op != CC_OP_DYNAMIC) {
3300 env->cc_op = cc_op;
3301 }
3302 }
QEmu