4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
22 #include "exec/exec-all.h"
23 #include "tcg/tcg-op.h"
24 #include "tcg/tcg-op-gvec.h"
27 #include "translate.h"
28 #include "internals.h"
29 #include "qemu/host-utils.h"
31 #include "semihosting/semihost.h"
32 #include "exec/gen-icount.h"
34 #include "exec/helper-proto.h"
35 #include "exec/helper-gen.h"
38 #include "translate-a64.h"
39 #include "qemu/atomic128.h"
41 static TCGv_i64 cpu_X
[32];
42 static TCGv_i64 cpu_pc
;
44 /* Load/store exclusive handling */
45 static TCGv_i64 cpu_exclusive_high
;
47 static const char *regnames
[] = {
48 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
49 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
50 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
51 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
55 A64_SHIFT_TYPE_LSL
= 0,
56 A64_SHIFT_TYPE_LSR
= 1,
57 A64_SHIFT_TYPE_ASR
= 2,
58 A64_SHIFT_TYPE_ROR
= 3
61 /* Table based decoder typedefs - used when the relevant bits for decode
62 * are too awkwardly scattered across the instruction (eg SIMD).
64 typedef void AArch64DecodeFn(DisasContext
*s
, uint32_t insn
);
66 typedef struct AArch64DecodeTable
{
69 AArch64DecodeFn
*disas_fn
;
72 /* initialize TCG globals. */
73 void a64_translate_init(void)
77 cpu_pc
= tcg_global_mem_new_i64(cpu_env
,
78 offsetof(CPUARMState
, pc
),
80 for (i
= 0; i
< 32; i
++) {
81 cpu_X
[i
] = tcg_global_mem_new_i64(cpu_env
,
82 offsetof(CPUARMState
, xregs
[i
]),
86 cpu_exclusive_high
= tcg_global_mem_new_i64(cpu_env
,
87 offsetof(CPUARMState
, exclusive_high
), "exclusive_high");
91 * Return the core mmu_idx to use for A64 "unprivileged load/store" insns
93 static int get_a64_user_mem_index(DisasContext
*s
)
96 * If AccType_UNPRIV is not used, the insn uses AccType_NORMAL,
97 * which is the usual mmu_idx for this cpu state.
99 ARMMMUIdx useridx
= s
->mmu_idx
;
103 * We have pre-computed the condition for AccType_UNPRIV.
104 * Therefore we should never get here with a mmu_idx for
105 * which we do not know the corresponding user mmu_idx.
108 case ARMMMUIdx_E10_1
:
109 case ARMMMUIdx_E10_1_PAN
:
110 useridx
= ARMMMUIdx_E10_0
;
112 case ARMMMUIdx_E20_2
:
113 case ARMMMUIdx_E20_2_PAN
:
114 useridx
= ARMMMUIdx_E20_0
;
116 case ARMMMUIdx_SE10_1
:
117 case ARMMMUIdx_SE10_1_PAN
:
118 useridx
= ARMMMUIdx_SE10_0
;
120 case ARMMMUIdx_SE20_2
:
121 case ARMMMUIdx_SE20_2_PAN
:
122 useridx
= ARMMMUIdx_SE20_0
;
125 g_assert_not_reached();
128 return arm_to_core_mmu_idx(useridx
);
131 static void reset_btype(DisasContext
*s
)
134 TCGv_i32 zero
= tcg_const_i32(0);
135 tcg_gen_st_i32(zero
, cpu_env
, offsetof(CPUARMState
, btype
));
136 tcg_temp_free_i32(zero
);
141 static void set_btype(DisasContext
*s
, int val
)
145 /* BTYPE is a 2-bit field, and 0 should be done with reset_btype. */
146 tcg_debug_assert(val
>= 1 && val
<= 3);
148 tcg_val
= tcg_const_i32(val
);
149 tcg_gen_st_i32(tcg_val
, cpu_env
, offsetof(CPUARMState
, btype
));
150 tcg_temp_free_i32(tcg_val
);
154 void gen_a64_set_pc_im(uint64_t val
)
156 tcg_gen_movi_i64(cpu_pc
, val
);
160 * Handle Top Byte Ignore (TBI) bits.
162 * If address tagging is enabled via the TCR TBI bits:
163 * + for EL2 and EL3 there is only one TBI bit, and if it is set
164 * then the address is zero-extended, clearing bits [63:56]
165 * + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0
166 * and TBI1 controls addressses with bit 55 == 1.
167 * If the appropriate TBI bit is set for the address then
168 * the address is sign-extended from bit 55 into bits [63:56]
170 * Here We have concatenated TBI{1,0} into tbi.
172 static void gen_top_byte_ignore(DisasContext
*s
, TCGv_i64 dst
,
173 TCGv_i64 src
, int tbi
)
176 /* Load unmodified address */
177 tcg_gen_mov_i64(dst
, src
);
178 } else if (!regime_has_2_ranges(s
->mmu_idx
)) {
179 /* Force tag byte to all zero */
180 tcg_gen_extract_i64(dst
, src
, 0, 56);
182 /* Sign-extend from bit 55. */
183 tcg_gen_sextract_i64(dst
, src
, 0, 56);
187 /* tbi0 but !tbi1: only use the extension if positive */
188 tcg_gen_and_i64(dst
, dst
, src
);
191 /* !tbi0 but tbi1: only use the extension if negative */
192 tcg_gen_or_i64(dst
, dst
, src
);
195 /* tbi0 and tbi1: always use the extension */
198 g_assert_not_reached();
203 static void gen_a64_set_pc(DisasContext
*s
, TCGv_i64 src
)
206 * If address tagging is enabled for instructions via the TCR TBI bits,
207 * then loading an address into the PC will clear out any tag.
209 gen_top_byte_ignore(s
, cpu_pc
, src
, s
->tbii
);
213 * Handle MTE and/or TBI.
215 * For TBI, ideally, we would do nothing. Proper behaviour on fault is
216 * for the tag to be present in the FAR_ELx register. But for user-only
217 * mode we do not have a TLB with which to implement this, so we must
218 * remove the top byte now.
220 * Always return a fresh temporary that we can increment independently
221 * of the write-back address.
224 TCGv_i64
clean_data_tbi(DisasContext
*s
, TCGv_i64 addr
)
226 TCGv_i64 clean
= new_tmp_a64(s
);
227 #ifdef CONFIG_USER_ONLY
228 gen_top_byte_ignore(s
, clean
, addr
, s
->tbid
);
230 tcg_gen_mov_i64(clean
, addr
);
235 /* Insert a zero tag into src, with the result at dst. */
236 static void gen_address_with_allocation_tag0(TCGv_i64 dst
, TCGv_i64 src
)
238 tcg_gen_andi_i64(dst
, src
, ~MAKE_64BIT_MASK(56, 4));
241 static void gen_probe_access(DisasContext
*s
, TCGv_i64 ptr
,
242 MMUAccessType acc
, int log2_size
)
244 TCGv_i32 t_acc
= tcg_const_i32(acc
);
245 TCGv_i32 t_idx
= tcg_const_i32(get_mem_index(s
));
246 TCGv_i32 t_size
= tcg_const_i32(1 << log2_size
);
248 gen_helper_probe_access(cpu_env
, ptr
, t_acc
, t_idx
, t_size
);
249 tcg_temp_free_i32(t_acc
);
250 tcg_temp_free_i32(t_idx
);
251 tcg_temp_free_i32(t_size
);
255 * For MTE, check a single logical or atomic access. This probes a single
256 * address, the exact one specified. The size and alignment of the access
257 * is not relevant to MTE, per se, but watchpoints do require the size,
258 * and we want to recognize those before making any other changes to state.
260 static TCGv_i64
gen_mte_check1_mmuidx(DisasContext
*s
, TCGv_i64 addr
,
261 bool is_write
, bool tag_checked
,
262 int log2_size
, bool is_unpriv
,
265 if (tag_checked
&& s
->mte_active
[is_unpriv
]) {
270 desc
= FIELD_DP32(desc
, MTEDESC
, MIDX
, core_idx
);
271 desc
= FIELD_DP32(desc
, MTEDESC
, TBI
, s
->tbid
);
272 desc
= FIELD_DP32(desc
, MTEDESC
, TCMA
, s
->tcma
);
273 desc
= FIELD_DP32(desc
, MTEDESC
, WRITE
, is_write
);
274 desc
= FIELD_DP32(desc
, MTEDESC
, SIZEM1
, (1 << log2_size
) - 1);
275 tcg_desc
= tcg_const_i32(desc
);
277 ret
= new_tmp_a64(s
);
278 gen_helper_mte_check(ret
, cpu_env
, tcg_desc
, addr
);
279 tcg_temp_free_i32(tcg_desc
);
283 return clean_data_tbi(s
, addr
);
286 TCGv_i64
gen_mte_check1(DisasContext
*s
, TCGv_i64 addr
, bool is_write
,
287 bool tag_checked
, int log2_size
)
289 return gen_mte_check1_mmuidx(s
, addr
, is_write
, tag_checked
, log2_size
,
290 false, get_mem_index(s
));
294 * For MTE, check multiple logical sequential accesses.
296 TCGv_i64
gen_mte_checkN(DisasContext
*s
, TCGv_i64 addr
, bool is_write
,
297 bool tag_checked
, int size
)
299 if (tag_checked
&& s
->mte_active
[0]) {
304 desc
= FIELD_DP32(desc
, MTEDESC
, MIDX
, get_mem_index(s
));
305 desc
= FIELD_DP32(desc
, MTEDESC
, TBI
, s
->tbid
);
306 desc
= FIELD_DP32(desc
, MTEDESC
, TCMA
, s
->tcma
);
307 desc
= FIELD_DP32(desc
, MTEDESC
, WRITE
, is_write
);
308 desc
= FIELD_DP32(desc
, MTEDESC
, SIZEM1
, size
- 1);
309 tcg_desc
= tcg_const_i32(desc
);
311 ret
= new_tmp_a64(s
);
312 gen_helper_mte_check(ret
, cpu_env
, tcg_desc
, addr
);
313 tcg_temp_free_i32(tcg_desc
);
317 return clean_data_tbi(s
, addr
);
320 typedef struct DisasCompare64
{
325 static void a64_test_cc(DisasCompare64
*c64
, int cc
)
329 arm_test_cc(&c32
, cc
);
331 /* Sign-extend the 32-bit value so that the GE/LT comparisons work
332 * properly. The NE/EQ comparisons are also fine with this choice. */
333 c64
->cond
= c32
.cond
;
334 c64
->value
= tcg_temp_new_i64();
335 tcg_gen_ext_i32_i64(c64
->value
, c32
.value
);
340 static void a64_free_cc(DisasCompare64
*c64
)
342 tcg_temp_free_i64(c64
->value
);
345 static void gen_exception_internal(int excp
)
347 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
349 assert(excp_is_internal(excp
));
350 gen_helper_exception_internal(cpu_env
, tcg_excp
);
351 tcg_temp_free_i32(tcg_excp
);
354 static void gen_exception_internal_insn(DisasContext
*s
, uint64_t pc
, int excp
)
356 gen_a64_set_pc_im(pc
);
357 gen_exception_internal(excp
);
358 s
->base
.is_jmp
= DISAS_NORETURN
;
361 static void gen_exception_bkpt_insn(DisasContext
*s
, uint32_t syndrome
)
365 gen_a64_set_pc_im(s
->pc_curr
);
366 tcg_syn
= tcg_const_i32(syndrome
);
367 gen_helper_exception_bkpt_insn(cpu_env
, tcg_syn
);
368 tcg_temp_free_i32(tcg_syn
);
369 s
->base
.is_jmp
= DISAS_NORETURN
;
372 static void gen_step_complete_exception(DisasContext
*s
)
374 /* We just completed step of an insn. Move from Active-not-pending
375 * to Active-pending, and then also take the swstep exception.
376 * This corresponds to making the (IMPDEF) choice to prioritize
377 * swstep exceptions over asynchronous exceptions taken to an exception
378 * level where debug is disabled. This choice has the advantage that
379 * we do not need to maintain internal state corresponding to the
380 * ISV/EX syndrome bits between completion of the step and generation
381 * of the exception, and our syndrome information is always correct.
384 gen_swstep_exception(s
, 1, s
->is_ldex
);
385 s
->base
.is_jmp
= DISAS_NORETURN
;
388 static inline bool use_goto_tb(DisasContext
*s
, uint64_t dest
)
393 return translator_use_goto_tb(&s
->base
, dest
);
396 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
398 if (use_goto_tb(s
, dest
)) {
400 gen_a64_set_pc_im(dest
);
401 tcg_gen_exit_tb(s
->base
.tb
, n
);
402 s
->base
.is_jmp
= DISAS_NORETURN
;
404 gen_a64_set_pc_im(dest
);
406 gen_step_complete_exception(s
);
408 tcg_gen_lookup_and_goto_ptr();
409 s
->base
.is_jmp
= DISAS_NORETURN
;
414 static void init_tmp_a64_array(DisasContext
*s
)
416 #ifdef CONFIG_DEBUG_TCG
417 memset(s
->tmp_a64
, 0, sizeof(s
->tmp_a64
));
419 s
->tmp_a64_count
= 0;
422 static void free_tmp_a64(DisasContext
*s
)
425 for (i
= 0; i
< s
->tmp_a64_count
; i
++) {
426 tcg_temp_free_i64(s
->tmp_a64
[i
]);
428 init_tmp_a64_array(s
);
431 TCGv_i64
new_tmp_a64(DisasContext
*s
)
433 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
434 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_new_i64();
437 TCGv_i64
new_tmp_a64_local(DisasContext
*s
)
439 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
440 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_local_new_i64();
443 TCGv_i64
new_tmp_a64_zero(DisasContext
*s
)
445 TCGv_i64 t
= new_tmp_a64(s
);
446 tcg_gen_movi_i64(t
, 0);
451 * Register access functions
453 * These functions are used for directly accessing a register in where
454 * changes to the final register value are likely to be made. If you
455 * need to use a register for temporary calculation (e.g. index type
456 * operations) use the read_* form.
458 * B1.2.1 Register mappings
460 * In instruction register encoding 31 can refer to ZR (zero register) or
461 * the SP (stack pointer) depending on context. In QEMU's case we map SP
462 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
463 * This is the point of the _sp forms.
465 TCGv_i64
cpu_reg(DisasContext
*s
, int reg
)
468 return new_tmp_a64_zero(s
);
474 /* register access for when 31 == SP */
475 TCGv_i64
cpu_reg_sp(DisasContext
*s
, int reg
)
480 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
481 * representing the register contents. This TCGv is an auto-freed
482 * temporary so it need not be explicitly freed, and may be modified.
484 TCGv_i64
read_cpu_reg(DisasContext
*s
, int reg
, int sf
)
486 TCGv_i64 v
= new_tmp_a64(s
);
489 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
491 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
494 tcg_gen_movi_i64(v
, 0);
499 TCGv_i64
read_cpu_reg_sp(DisasContext
*s
, int reg
, int sf
)
501 TCGv_i64 v
= new_tmp_a64(s
);
503 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
505 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
510 /* Return the offset into CPUARMState of a slice (from
511 * the least significant end) of FP register Qn (ie
513 * (Note that this is not the same mapping as for A32; see cpu.h)
515 static inline int fp_reg_offset(DisasContext
*s
, int regno
, MemOp size
)
517 return vec_reg_offset(s
, regno
, 0, size
);
520 /* Offset of the high half of the 128 bit vector Qn */
521 static inline int fp_reg_hi_offset(DisasContext
*s
, int regno
)
523 return vec_reg_offset(s
, regno
, 1, MO_64
);
526 /* Convenience accessors for reading and writing single and double
527 * FP registers. Writing clears the upper parts of the associated
528 * 128 bit vector register, as required by the architecture.
529 * Note that unlike the GP register accessors, the values returned
530 * by the read functions must be manually freed.
532 static TCGv_i64
read_fp_dreg(DisasContext
*s
, int reg
)
534 TCGv_i64 v
= tcg_temp_new_i64();
536 tcg_gen_ld_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
540 static TCGv_i32
read_fp_sreg(DisasContext
*s
, int reg
)
542 TCGv_i32 v
= tcg_temp_new_i32();
544 tcg_gen_ld_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_32
));
548 static TCGv_i32
read_fp_hreg(DisasContext
*s
, int reg
)
550 TCGv_i32 v
= tcg_temp_new_i32();
552 tcg_gen_ld16u_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_16
));
556 /* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64).
557 * If SVE is not enabled, then there are only 128 bits in the vector.
559 static void clear_vec_high(DisasContext
*s
, bool is_q
, int rd
)
561 unsigned ofs
= fp_reg_offset(s
, rd
, MO_64
);
562 unsigned vsz
= vec_full_reg_size(s
);
564 /* Nop move, with side effect of clearing the tail. */
565 tcg_gen_gvec_mov(MO_64
, ofs
, ofs
, is_q
? 16 : 8, vsz
);
568 void write_fp_dreg(DisasContext
*s
, int reg
, TCGv_i64 v
)
570 unsigned ofs
= fp_reg_offset(s
, reg
, MO_64
);
572 tcg_gen_st_i64(v
, cpu_env
, ofs
);
573 clear_vec_high(s
, false, reg
);
576 static void write_fp_sreg(DisasContext
*s
, int reg
, TCGv_i32 v
)
578 TCGv_i64 tmp
= tcg_temp_new_i64();
580 tcg_gen_extu_i32_i64(tmp
, v
);
581 write_fp_dreg(s
, reg
, tmp
);
582 tcg_temp_free_i64(tmp
);
585 /* Expand a 2-operand AdvSIMD vector operation using an expander function. */
586 static void gen_gvec_fn2(DisasContext
*s
, bool is_q
, int rd
, int rn
,
587 GVecGen2Fn
*gvec_fn
, int vece
)
589 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
590 is_q
? 16 : 8, vec_full_reg_size(s
));
593 /* Expand a 2-operand + immediate AdvSIMD vector operation using
594 * an expander function.
596 static void gen_gvec_fn2i(DisasContext
*s
, bool is_q
, int rd
, int rn
,
597 int64_t imm
, GVecGen2iFn
*gvec_fn
, int vece
)
599 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
600 imm
, is_q
? 16 : 8, vec_full_reg_size(s
));
603 /* Expand a 3-operand AdvSIMD vector operation using an expander function. */
604 static void gen_gvec_fn3(DisasContext
*s
, bool is_q
, int rd
, int rn
, int rm
,
605 GVecGen3Fn
*gvec_fn
, int vece
)
607 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
608 vec_full_reg_offset(s
, rm
), is_q
? 16 : 8, vec_full_reg_size(s
));
611 /* Expand a 4-operand AdvSIMD vector operation using an expander function. */
612 static void gen_gvec_fn4(DisasContext
*s
, bool is_q
, int rd
, int rn
, int rm
,
613 int rx
, GVecGen4Fn
*gvec_fn
, int vece
)
615 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
616 vec_full_reg_offset(s
, rm
), vec_full_reg_offset(s
, rx
),
617 is_q
? 16 : 8, vec_full_reg_size(s
));
620 /* Expand a 2-operand operation using an out-of-line helper. */
621 static void gen_gvec_op2_ool(DisasContext
*s
, bool is_q
, int rd
,
622 int rn
, int data
, gen_helper_gvec_2
*fn
)
624 tcg_gen_gvec_2_ool(vec_full_reg_offset(s
, rd
),
625 vec_full_reg_offset(s
, rn
),
626 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
629 /* Expand a 3-operand operation using an out-of-line helper. */
630 static void gen_gvec_op3_ool(DisasContext
*s
, bool is_q
, int rd
,
631 int rn
, int rm
, int data
, gen_helper_gvec_3
*fn
)
633 tcg_gen_gvec_3_ool(vec_full_reg_offset(s
, rd
),
634 vec_full_reg_offset(s
, rn
),
635 vec_full_reg_offset(s
, rm
),
636 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
639 /* Expand a 3-operand + fpstatus pointer + simd data value operation using
640 * an out-of-line helper.
642 static void gen_gvec_op3_fpst(DisasContext
*s
, bool is_q
, int rd
, int rn
,
643 int rm
, bool is_fp16
, int data
,
644 gen_helper_gvec_3_ptr
*fn
)
646 TCGv_ptr fpst
= fpstatus_ptr(is_fp16
? FPST_FPCR_F16
: FPST_FPCR
);
647 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
648 vec_full_reg_offset(s
, rn
),
649 vec_full_reg_offset(s
, rm
), fpst
,
650 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
651 tcg_temp_free_ptr(fpst
);
654 /* Expand a 3-operand + qc + operation using an out-of-line helper. */
655 static void gen_gvec_op3_qc(DisasContext
*s
, bool is_q
, int rd
, int rn
,
656 int rm
, gen_helper_gvec_3_ptr
*fn
)
658 TCGv_ptr qc_ptr
= tcg_temp_new_ptr();
660 tcg_gen_addi_ptr(qc_ptr
, cpu_env
, offsetof(CPUARMState
, vfp
.qc
));
661 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
662 vec_full_reg_offset(s
, rn
),
663 vec_full_reg_offset(s
, rm
), qc_ptr
,
664 is_q
? 16 : 8, vec_full_reg_size(s
), 0, fn
);
665 tcg_temp_free_ptr(qc_ptr
);
668 /* Expand a 4-operand operation using an out-of-line helper. */
669 static void gen_gvec_op4_ool(DisasContext
*s
, bool is_q
, int rd
, int rn
,
670 int rm
, int ra
, int data
, gen_helper_gvec_4
*fn
)
672 tcg_gen_gvec_4_ool(vec_full_reg_offset(s
, rd
),
673 vec_full_reg_offset(s
, rn
),
674 vec_full_reg_offset(s
, rm
),
675 vec_full_reg_offset(s
, ra
),
676 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
680 * Expand a 4-operand + fpstatus pointer + simd data value operation using
681 * an out-of-line helper.
683 static void gen_gvec_op4_fpst(DisasContext
*s
, bool is_q
, int rd
, int rn
,
684 int rm
, int ra
, bool is_fp16
, int data
,
685 gen_helper_gvec_4_ptr
*fn
)
687 TCGv_ptr fpst
= fpstatus_ptr(is_fp16
? FPST_FPCR_F16
: FPST_FPCR
);
688 tcg_gen_gvec_4_ptr(vec_full_reg_offset(s
, rd
),
689 vec_full_reg_offset(s
, rn
),
690 vec_full_reg_offset(s
, rm
),
691 vec_full_reg_offset(s
, ra
), fpst
,
692 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
693 tcg_temp_free_ptr(fpst
);
696 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
697 * than the 32 bit equivalent.
699 static inline void gen_set_NZ64(TCGv_i64 result
)
701 tcg_gen_extr_i64_i32(cpu_ZF
, cpu_NF
, result
);
702 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, cpu_NF
);
705 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
706 static inline void gen_logic_CC(int sf
, TCGv_i64 result
)
709 gen_set_NZ64(result
);
711 tcg_gen_extrl_i64_i32(cpu_ZF
, result
);
712 tcg_gen_mov_i32(cpu_NF
, cpu_ZF
);
714 tcg_gen_movi_i32(cpu_CF
, 0);
715 tcg_gen_movi_i32(cpu_VF
, 0);
718 /* dest = T0 + T1; compute C, N, V and Z flags */
719 static void gen_add_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
722 TCGv_i64 result
, flag
, tmp
;
723 result
= tcg_temp_new_i64();
724 flag
= tcg_temp_new_i64();
725 tmp
= tcg_temp_new_i64();
727 tcg_gen_movi_i64(tmp
, 0);
728 tcg_gen_add2_i64(result
, flag
, t0
, tmp
, t1
, tmp
);
730 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
732 gen_set_NZ64(result
);
734 tcg_gen_xor_i64(flag
, result
, t0
);
735 tcg_gen_xor_i64(tmp
, t0
, t1
);
736 tcg_gen_andc_i64(flag
, flag
, tmp
);
737 tcg_temp_free_i64(tmp
);
738 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
740 tcg_gen_mov_i64(dest
, result
);
741 tcg_temp_free_i64(result
);
742 tcg_temp_free_i64(flag
);
744 /* 32 bit arithmetic */
745 TCGv_i32 t0_32
= tcg_temp_new_i32();
746 TCGv_i32 t1_32
= tcg_temp_new_i32();
747 TCGv_i32 tmp
= tcg_temp_new_i32();
749 tcg_gen_movi_i32(tmp
, 0);
750 tcg_gen_extrl_i64_i32(t0_32
, t0
);
751 tcg_gen_extrl_i64_i32(t1_32
, t1
);
752 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, t1_32
, tmp
);
753 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
754 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
755 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
756 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
757 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
759 tcg_temp_free_i32(tmp
);
760 tcg_temp_free_i32(t0_32
);
761 tcg_temp_free_i32(t1_32
);
765 /* dest = T0 - T1; compute C, N, V and Z flags */
766 static void gen_sub_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
769 /* 64 bit arithmetic */
770 TCGv_i64 result
, flag
, tmp
;
772 result
= tcg_temp_new_i64();
773 flag
= tcg_temp_new_i64();
774 tcg_gen_sub_i64(result
, t0
, t1
);
776 gen_set_NZ64(result
);
778 tcg_gen_setcond_i64(TCG_COND_GEU
, flag
, t0
, t1
);
779 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
781 tcg_gen_xor_i64(flag
, result
, t0
);
782 tmp
= tcg_temp_new_i64();
783 tcg_gen_xor_i64(tmp
, t0
, t1
);
784 tcg_gen_and_i64(flag
, flag
, tmp
);
785 tcg_temp_free_i64(tmp
);
786 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
787 tcg_gen_mov_i64(dest
, result
);
788 tcg_temp_free_i64(flag
);
789 tcg_temp_free_i64(result
);
791 /* 32 bit arithmetic */
792 TCGv_i32 t0_32
= tcg_temp_new_i32();
793 TCGv_i32 t1_32
= tcg_temp_new_i32();
796 tcg_gen_extrl_i64_i32(t0_32
, t0
);
797 tcg_gen_extrl_i64_i32(t1_32
, t1
);
798 tcg_gen_sub_i32(cpu_NF
, t0_32
, t1_32
);
799 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
800 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0_32
, t1_32
);
801 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
802 tmp
= tcg_temp_new_i32();
803 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
804 tcg_temp_free_i32(t0_32
);
805 tcg_temp_free_i32(t1_32
);
806 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
807 tcg_temp_free_i32(tmp
);
808 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
812 /* dest = T0 + T1 + CF; do not compute flags. */
813 static void gen_adc(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
815 TCGv_i64 flag
= tcg_temp_new_i64();
816 tcg_gen_extu_i32_i64(flag
, cpu_CF
);
817 tcg_gen_add_i64(dest
, t0
, t1
);
818 tcg_gen_add_i64(dest
, dest
, flag
);
819 tcg_temp_free_i64(flag
);
822 tcg_gen_ext32u_i64(dest
, dest
);
826 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
827 static void gen_adc_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
830 TCGv_i64 result
, cf_64
, vf_64
, tmp
;
831 result
= tcg_temp_new_i64();
832 cf_64
= tcg_temp_new_i64();
833 vf_64
= tcg_temp_new_i64();
834 tmp
= tcg_const_i64(0);
836 tcg_gen_extu_i32_i64(cf_64
, cpu_CF
);
837 tcg_gen_add2_i64(result
, cf_64
, t0
, tmp
, cf_64
, tmp
);
838 tcg_gen_add2_i64(result
, cf_64
, result
, cf_64
, t1
, tmp
);
839 tcg_gen_extrl_i64_i32(cpu_CF
, cf_64
);
840 gen_set_NZ64(result
);
842 tcg_gen_xor_i64(vf_64
, result
, t0
);
843 tcg_gen_xor_i64(tmp
, t0
, t1
);
844 tcg_gen_andc_i64(vf_64
, vf_64
, tmp
);
845 tcg_gen_extrh_i64_i32(cpu_VF
, vf_64
);
847 tcg_gen_mov_i64(dest
, result
);
849 tcg_temp_free_i64(tmp
);
850 tcg_temp_free_i64(vf_64
);
851 tcg_temp_free_i64(cf_64
);
852 tcg_temp_free_i64(result
);
854 TCGv_i32 t0_32
, t1_32
, tmp
;
855 t0_32
= tcg_temp_new_i32();
856 t1_32
= tcg_temp_new_i32();
857 tmp
= tcg_const_i32(0);
859 tcg_gen_extrl_i64_i32(t0_32
, t0
);
860 tcg_gen_extrl_i64_i32(t1_32
, t1
);
861 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, cpu_CF
, tmp
);
862 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1_32
, tmp
);
864 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
865 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
866 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
867 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
868 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
870 tcg_temp_free_i32(tmp
);
871 tcg_temp_free_i32(t1_32
);
872 tcg_temp_free_i32(t0_32
);
877 * Load/Store generators
881 * Store from GPR register to memory.
883 static void do_gpr_st_memidx(DisasContext
*s
, TCGv_i64 source
,
884 TCGv_i64 tcg_addr
, MemOp memop
, int memidx
,
886 unsigned int iss_srt
,
887 bool iss_sf
, bool iss_ar
)
889 memop
= finalize_memop(s
, memop
);
890 tcg_gen_qemu_st_i64(source
, tcg_addr
, memidx
, memop
);
895 syn
= syn_data_abort_with_iss(0,
901 0, 0, 0, 0, 0, false);
902 disas_set_insn_syndrome(s
, syn
);
906 static void do_gpr_st(DisasContext
*s
, TCGv_i64 source
,
907 TCGv_i64 tcg_addr
, MemOp memop
,
909 unsigned int iss_srt
,
910 bool iss_sf
, bool iss_ar
)
912 do_gpr_st_memidx(s
, source
, tcg_addr
, memop
, get_mem_index(s
),
913 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
917 * Load from memory to GPR register
919 static void do_gpr_ld_memidx(DisasContext
*s
, TCGv_i64 dest
, TCGv_i64 tcg_addr
,
920 MemOp memop
, bool extend
, int memidx
,
921 bool iss_valid
, unsigned int iss_srt
,
922 bool iss_sf
, bool iss_ar
)
924 memop
= finalize_memop(s
, memop
);
925 tcg_gen_qemu_ld_i64(dest
, tcg_addr
, memidx
, memop
);
927 if (extend
&& (memop
& MO_SIGN
)) {
928 g_assert((memop
& MO_SIZE
) <= MO_32
);
929 tcg_gen_ext32u_i64(dest
, dest
);
935 syn
= syn_data_abort_with_iss(0,
937 (memop
& MO_SIGN
) != 0,
941 0, 0, 0, 0, 0, false);
942 disas_set_insn_syndrome(s
, syn
);
946 static void do_gpr_ld(DisasContext
*s
, TCGv_i64 dest
, TCGv_i64 tcg_addr
,
947 MemOp memop
, bool extend
,
948 bool iss_valid
, unsigned int iss_srt
,
949 bool iss_sf
, bool iss_ar
)
951 do_gpr_ld_memidx(s
, dest
, tcg_addr
, memop
, extend
, get_mem_index(s
),
952 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
956 * Store from FP register to memory
958 static void do_fp_st(DisasContext
*s
, int srcidx
, TCGv_i64 tcg_addr
, int size
)
960 /* This writes the bottom N bits of a 128 bit wide vector to memory */
961 TCGv_i64 tmplo
= tcg_temp_new_i64();
964 tcg_gen_ld_i64(tmplo
, cpu_env
, fp_reg_offset(s
, srcidx
, MO_64
));
967 mop
= finalize_memop(s
, size
);
968 tcg_gen_qemu_st_i64(tmplo
, tcg_addr
, get_mem_index(s
), mop
);
970 bool be
= s
->be_data
== MO_BE
;
971 TCGv_i64 tcg_hiaddr
= tcg_temp_new_i64();
972 TCGv_i64 tmphi
= tcg_temp_new_i64();
974 tcg_gen_ld_i64(tmphi
, cpu_env
, fp_reg_hi_offset(s
, srcidx
));
976 mop
= s
->be_data
| MO_UQ
;
977 tcg_gen_qemu_st_i64(be
? tmphi
: tmplo
, tcg_addr
, get_mem_index(s
),
978 mop
| (s
->align_mem
? MO_ALIGN_16
: 0));
979 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
980 tcg_gen_qemu_st_i64(be
? tmplo
: tmphi
, tcg_hiaddr
,
981 get_mem_index(s
), mop
);
983 tcg_temp_free_i64(tcg_hiaddr
);
984 tcg_temp_free_i64(tmphi
);
987 tcg_temp_free_i64(tmplo
);
991 * Load from memory to FP register
993 static void do_fp_ld(DisasContext
*s
, int destidx
, TCGv_i64 tcg_addr
, int size
)
995 /* This always zero-extends and writes to a full 128 bit wide vector */
996 TCGv_i64 tmplo
= tcg_temp_new_i64();
997 TCGv_i64 tmphi
= NULL
;
1001 mop
= finalize_memop(s
, size
);
1002 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), mop
);
1004 bool be
= s
->be_data
== MO_BE
;
1005 TCGv_i64 tcg_hiaddr
;
1007 tmphi
= tcg_temp_new_i64();
1008 tcg_hiaddr
= tcg_temp_new_i64();
1010 mop
= s
->be_data
| MO_UQ
;
1011 tcg_gen_qemu_ld_i64(be
? tmphi
: tmplo
, tcg_addr
, get_mem_index(s
),
1012 mop
| (s
->align_mem
? MO_ALIGN_16
: 0));
1013 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
1014 tcg_gen_qemu_ld_i64(be
? tmplo
: tmphi
, tcg_hiaddr
,
1015 get_mem_index(s
), mop
);
1016 tcg_temp_free_i64(tcg_hiaddr
);
1019 tcg_gen_st_i64(tmplo
, cpu_env
, fp_reg_offset(s
, destidx
, MO_64
));
1020 tcg_temp_free_i64(tmplo
);
1023 tcg_gen_st_i64(tmphi
, cpu_env
, fp_reg_hi_offset(s
, destidx
));
1024 tcg_temp_free_i64(tmphi
);
1026 clear_vec_high(s
, tmphi
!= NULL
, destidx
);
1030 * Vector load/store helpers.
1032 * The principal difference between this and a FP load is that we don't
1033 * zero extend as we are filling a partial chunk of the vector register.
1034 * These functions don't support 128 bit loads/stores, which would be
1035 * normal load/store operations.
1037 * The _i32 versions are useful when operating on 32 bit quantities
1038 * (eg for floating point single or using Neon helper functions).
1041 /* Get value of an element within a vector register */
1042 static void read_vec_element(DisasContext
*s
, TCGv_i64 tcg_dest
, int srcidx
,
1043 int element
, MemOp memop
)
1045 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
1046 switch ((unsigned)memop
) {
1048 tcg_gen_ld8u_i64(tcg_dest
, cpu_env
, vect_off
);
1051 tcg_gen_ld16u_i64(tcg_dest
, cpu_env
, vect_off
);
1054 tcg_gen_ld32u_i64(tcg_dest
, cpu_env
, vect_off
);
1057 tcg_gen_ld8s_i64(tcg_dest
, cpu_env
, vect_off
);
1060 tcg_gen_ld16s_i64(tcg_dest
, cpu_env
, vect_off
);
1063 tcg_gen_ld32s_i64(tcg_dest
, cpu_env
, vect_off
);
1067 tcg_gen_ld_i64(tcg_dest
, cpu_env
, vect_off
);
1070 g_assert_not_reached();
1074 static void read_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_dest
, int srcidx
,
1075 int element
, MemOp memop
)
1077 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
1080 tcg_gen_ld8u_i32(tcg_dest
, cpu_env
, vect_off
);
1083 tcg_gen_ld16u_i32(tcg_dest
, cpu_env
, vect_off
);
1086 tcg_gen_ld8s_i32(tcg_dest
, cpu_env
, vect_off
);
1089 tcg_gen_ld16s_i32(tcg_dest
, cpu_env
, vect_off
);
1093 tcg_gen_ld_i32(tcg_dest
, cpu_env
, vect_off
);
1096 g_assert_not_reached();
1100 /* Set value of an element within a vector register */
1101 static void write_vec_element(DisasContext
*s
, TCGv_i64 tcg_src
, int destidx
,
1102 int element
, MemOp memop
)
1104 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1107 tcg_gen_st8_i64(tcg_src
, cpu_env
, vect_off
);
1110 tcg_gen_st16_i64(tcg_src
, cpu_env
, vect_off
);
1113 tcg_gen_st32_i64(tcg_src
, cpu_env
, vect_off
);
1116 tcg_gen_st_i64(tcg_src
, cpu_env
, vect_off
);
1119 g_assert_not_reached();
1123 static void write_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_src
,
1124 int destidx
, int element
, MemOp memop
)
1126 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1129 tcg_gen_st8_i32(tcg_src
, cpu_env
, vect_off
);
1132 tcg_gen_st16_i32(tcg_src
, cpu_env
, vect_off
);
1135 tcg_gen_st_i32(tcg_src
, cpu_env
, vect_off
);
1138 g_assert_not_reached();
1142 /* Store from vector register to memory */
1143 static void do_vec_st(DisasContext
*s
, int srcidx
, int element
,
1144 TCGv_i64 tcg_addr
, MemOp mop
)
1146 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1148 read_vec_element(s
, tcg_tmp
, srcidx
, element
, mop
& MO_SIZE
);
1149 tcg_gen_qemu_st_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), mop
);
1151 tcg_temp_free_i64(tcg_tmp
);
1154 /* Load from memory to vector register */
1155 static void do_vec_ld(DisasContext
*s
, int destidx
, int element
,
1156 TCGv_i64 tcg_addr
, MemOp mop
)
1158 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1160 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), mop
);
1161 write_vec_element(s
, tcg_tmp
, destidx
, element
, mop
& MO_SIZE
);
1163 tcg_temp_free_i64(tcg_tmp
);
1166 /* Check that FP/Neon access is enabled. If it is, return
1167 * true. If not, emit code to generate an appropriate exception,
1168 * and return false; the caller should not emit any code for
1169 * the instruction. Note that this check must happen after all
1170 * unallocated-encoding checks (otherwise the syndrome information
1171 * for the resulting exception will be incorrect).
1173 static bool fp_access_check(DisasContext
*s
)
1175 if (s
->fp_excp_el
) {
1176 assert(!s
->fp_access_checked
);
1177 s
->fp_access_checked
= true;
1179 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
,
1180 syn_fp_access_trap(1, 0xe, false), s
->fp_excp_el
);
1183 s
->fp_access_checked
= true;
1187 /* Check that SVE access is enabled. If it is, return true.
1188 * If not, emit code to generate an appropriate exception and return false.
1190 bool sve_access_check(DisasContext
*s
)
1192 if (s
->sve_excp_el
) {
1193 assert(!s
->sve_access_checked
);
1194 s
->sve_access_checked
= true;
1196 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
,
1197 syn_sve_access_trap(), s
->sve_excp_el
);
1200 s
->sve_access_checked
= true;
1201 return fp_access_check(s
);
1205 * This utility function is for doing register extension with an
1206 * optional shift. You will likely want to pass a temporary for the
1207 * destination register. See DecodeRegExtend() in the ARM ARM.
1209 static void ext_and_shift_reg(TCGv_i64 tcg_out
, TCGv_i64 tcg_in
,
1210 int option
, unsigned int shift
)
1212 int extsize
= extract32(option
, 0, 2);
1213 bool is_signed
= extract32(option
, 2, 1);
1218 tcg_gen_ext8s_i64(tcg_out
, tcg_in
);
1221 tcg_gen_ext16s_i64(tcg_out
, tcg_in
);
1224 tcg_gen_ext32s_i64(tcg_out
, tcg_in
);
1227 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1233 tcg_gen_ext8u_i64(tcg_out
, tcg_in
);
1236 tcg_gen_ext16u_i64(tcg_out
, tcg_in
);
1239 tcg_gen_ext32u_i64(tcg_out
, tcg_in
);
1242 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1248 tcg_gen_shli_i64(tcg_out
, tcg_out
, shift
);
1252 static inline void gen_check_sp_alignment(DisasContext
*s
)
1254 /* The AArch64 architecture mandates that (if enabled via PSTATE
1255 * or SCTLR bits) there is a check that SP is 16-aligned on every
1256 * SP-relative load or store (with an exception generated if it is not).
1257 * In line with general QEMU practice regarding misaligned accesses,
1258 * we omit these checks for the sake of guest program performance.
1259 * This function is provided as a hook so we can more easily add these
1260 * checks in future (possibly as a "favour catching guest program bugs
1261 * over speed" user selectable option).
1266 * This provides a simple table based table lookup decoder. It is
1267 * intended to be used when the relevant bits for decode are too
1268 * awkwardly placed and switch/if based logic would be confusing and
1269 * deeply nested. Since it's a linear search through the table, tables
1270 * should be kept small.
1272 * It returns the first handler where insn & mask == pattern, or
1273 * NULL if there is no match.
1274 * The table is terminated by an empty mask (i.e. 0)
1276 static inline AArch64DecodeFn
*lookup_disas_fn(const AArch64DecodeTable
*table
,
1279 const AArch64DecodeTable
*tptr
= table
;
1281 while (tptr
->mask
) {
1282 if ((insn
& tptr
->mask
) == tptr
->pattern
) {
1283 return tptr
->disas_fn
;
1291 * The instruction disassembly implemented here matches
1292 * the instruction encoding classifications in chapter C4
1293 * of the ARM Architecture Reference Manual (DDI0487B_a);
1294 * classification names and decode diagrams here should generally
1295 * match up with those in the manual.
1298 /* Unconditional branch (immediate)
1300 * +----+-----------+-------------------------------------+
1301 * | op | 0 0 1 0 1 | imm26 |
1302 * +----+-----------+-------------------------------------+
1304 static void disas_uncond_b_imm(DisasContext
*s
, uint32_t insn
)
1306 uint64_t addr
= s
->pc_curr
+ sextract32(insn
, 0, 26) * 4;
1308 if (insn
& (1U << 31)) {
1309 /* BL Branch with link */
1310 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->base
.pc_next
);
1313 /* B Branch / BL Branch with link */
1315 gen_goto_tb(s
, 0, addr
);
1318 /* Compare and branch (immediate)
1319 * 31 30 25 24 23 5 4 0
1320 * +----+-------------+----+---------------------+--------+
1321 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
1322 * +----+-------------+----+---------------------+--------+
1324 static void disas_comp_b_imm(DisasContext
*s
, uint32_t insn
)
1326 unsigned int sf
, op
, rt
;
1328 TCGLabel
*label_match
;
1331 sf
= extract32(insn
, 31, 1);
1332 op
= extract32(insn
, 24, 1); /* 0: CBZ; 1: CBNZ */
1333 rt
= extract32(insn
, 0, 5);
1334 addr
= s
->pc_curr
+ sextract32(insn
, 5, 19) * 4;
1336 tcg_cmp
= read_cpu_reg(s
, rt
, sf
);
1337 label_match
= gen_new_label();
1340 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1341 tcg_cmp
, 0, label_match
);
1343 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1344 gen_set_label(label_match
);
1345 gen_goto_tb(s
, 1, addr
);
1348 /* Test and branch (immediate)
1349 * 31 30 25 24 23 19 18 5 4 0
1350 * +----+-------------+----+-------+-------------+------+
1351 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
1352 * +----+-------------+----+-------+-------------+------+
1354 static void disas_test_b_imm(DisasContext
*s
, uint32_t insn
)
1356 unsigned int bit_pos
, op
, rt
;
1358 TCGLabel
*label_match
;
1361 bit_pos
= (extract32(insn
, 31, 1) << 5) | extract32(insn
, 19, 5);
1362 op
= extract32(insn
, 24, 1); /* 0: TBZ; 1: TBNZ */
1363 addr
= s
->pc_curr
+ sextract32(insn
, 5, 14) * 4;
1364 rt
= extract32(insn
, 0, 5);
1366 tcg_cmp
= tcg_temp_new_i64();
1367 tcg_gen_andi_i64(tcg_cmp
, cpu_reg(s
, rt
), (1ULL << bit_pos
));
1368 label_match
= gen_new_label();
1371 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1372 tcg_cmp
, 0, label_match
);
1373 tcg_temp_free_i64(tcg_cmp
);
1374 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1375 gen_set_label(label_match
);
1376 gen_goto_tb(s
, 1, addr
);
1379 /* Conditional branch (immediate)
1380 * 31 25 24 23 5 4 3 0
1381 * +---------------+----+---------------------+----+------+
1382 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
1383 * +---------------+----+---------------------+----+------+
1385 static void disas_cond_b_imm(DisasContext
*s
, uint32_t insn
)
1390 if ((insn
& (1 << 4)) || (insn
& (1 << 24))) {
1391 unallocated_encoding(s
);
1394 addr
= s
->pc_curr
+ sextract32(insn
, 5, 19) * 4;
1395 cond
= extract32(insn
, 0, 4);
1399 /* genuinely conditional branches */
1400 TCGLabel
*label_match
= gen_new_label();
1401 arm_gen_test_cc(cond
, label_match
);
1402 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1403 gen_set_label(label_match
);
1404 gen_goto_tb(s
, 1, addr
);
1406 /* 0xe and 0xf are both "always" conditions */
1407 gen_goto_tb(s
, 0, addr
);
1411 /* HINT instruction group, including various allocated HINTs */
1412 static void handle_hint(DisasContext
*s
, uint32_t insn
,
1413 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1415 unsigned int selector
= crm
<< 3 | op2
;
1418 unallocated_encoding(s
);
1423 case 0b00000: /* NOP */
1425 case 0b00011: /* WFI */
1426 s
->base
.is_jmp
= DISAS_WFI
;
1428 case 0b00001: /* YIELD */
1429 /* When running in MTTCG we don't generate jumps to the yield and
1430 * WFE helpers as it won't affect the scheduling of other vCPUs.
1431 * If we wanted to more completely model WFE/SEV so we don't busy
1432 * spin unnecessarily we would need to do something more involved.
1434 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1435 s
->base
.is_jmp
= DISAS_YIELD
;
1438 case 0b00010: /* WFE */
1439 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1440 s
->base
.is_jmp
= DISAS_WFE
;
1443 case 0b00100: /* SEV */
1444 case 0b00101: /* SEVL */
1445 /* we treat all as NOP at least for now */
1447 case 0b00111: /* XPACLRI */
1448 if (s
->pauth_active
) {
1449 gen_helper_xpaci(cpu_X
[30], cpu_env
, cpu_X
[30]);
1452 case 0b01000: /* PACIA1716 */
1453 if (s
->pauth_active
) {
1454 gen_helper_pacia(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1457 case 0b01010: /* PACIB1716 */
1458 if (s
->pauth_active
) {
1459 gen_helper_pacib(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1462 case 0b01100: /* AUTIA1716 */
1463 if (s
->pauth_active
) {
1464 gen_helper_autia(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1467 case 0b01110: /* AUTIB1716 */
1468 if (s
->pauth_active
) {
1469 gen_helper_autib(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1472 case 0b11000: /* PACIAZ */
1473 if (s
->pauth_active
) {
1474 gen_helper_pacia(cpu_X
[30], cpu_env
, cpu_X
[30],
1475 new_tmp_a64_zero(s
));
1478 case 0b11001: /* PACIASP */
1479 if (s
->pauth_active
) {
1480 gen_helper_pacia(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1483 case 0b11010: /* PACIBZ */
1484 if (s
->pauth_active
) {
1485 gen_helper_pacib(cpu_X
[30], cpu_env
, cpu_X
[30],
1486 new_tmp_a64_zero(s
));
1489 case 0b11011: /* PACIBSP */
1490 if (s
->pauth_active
) {
1491 gen_helper_pacib(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1494 case 0b11100: /* AUTIAZ */
1495 if (s
->pauth_active
) {
1496 gen_helper_autia(cpu_X
[30], cpu_env
, cpu_X
[30],
1497 new_tmp_a64_zero(s
));
1500 case 0b11101: /* AUTIASP */
1501 if (s
->pauth_active
) {
1502 gen_helper_autia(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1505 case 0b11110: /* AUTIBZ */
1506 if (s
->pauth_active
) {
1507 gen_helper_autib(cpu_X
[30], cpu_env
, cpu_X
[30],
1508 new_tmp_a64_zero(s
));
1511 case 0b11111: /* AUTIBSP */
1512 if (s
->pauth_active
) {
1513 gen_helper_autib(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1517 /* default specified as NOP equivalent */
1522 static void gen_clrex(DisasContext
*s
, uint32_t insn
)
1524 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1527 /* CLREX, DSB, DMB, ISB */
1528 static void handle_sync(DisasContext
*s
, uint32_t insn
,
1529 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1534 unallocated_encoding(s
);
1545 case 1: /* MBReqTypes_Reads */
1546 bar
= TCG_BAR_SC
| TCG_MO_LD_LD
| TCG_MO_LD_ST
;
1548 case 2: /* MBReqTypes_Writes */
1549 bar
= TCG_BAR_SC
| TCG_MO_ST_ST
;
1551 default: /* MBReqTypes_All */
1552 bar
= TCG_BAR_SC
| TCG_MO_ALL
;
1558 /* We need to break the TB after this insn to execute
1559 * a self-modified code correctly and also to take
1560 * any pending interrupts immediately.
1563 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1567 if (crm
!= 0 || !dc_isar_feature(aa64_sb
, s
)) {
1568 goto do_unallocated
;
1571 * TODO: There is no speculation barrier opcode for TCG;
1572 * MB and end the TB instead.
1574 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_SC
);
1575 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1580 unallocated_encoding(s
);
1585 static void gen_xaflag(void)
1587 TCGv_i32 z
= tcg_temp_new_i32();
1589 tcg_gen_setcondi_i32(TCG_COND_EQ
, z
, cpu_ZF
, 0);
1598 tcg_gen_or_i32(cpu_NF
, cpu_CF
, z
);
1599 tcg_gen_subi_i32(cpu_NF
, cpu_NF
, 1);
1602 tcg_gen_and_i32(cpu_ZF
, z
, cpu_CF
);
1603 tcg_gen_xori_i32(cpu_ZF
, cpu_ZF
, 1);
1605 /* (!C & Z) << 31 -> -(Z & ~C) */
1606 tcg_gen_andc_i32(cpu_VF
, z
, cpu_CF
);
1607 tcg_gen_neg_i32(cpu_VF
, cpu_VF
);
1610 tcg_gen_or_i32(cpu_CF
, cpu_CF
, z
);
1612 tcg_temp_free_i32(z
);
1615 static void gen_axflag(void)
1617 tcg_gen_sari_i32(cpu_VF
, cpu_VF
, 31); /* V ? -1 : 0 */
1618 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, cpu_VF
); /* C & !V */
1620 /* !(Z | V) -> !(!ZF | V) -> ZF & !V -> ZF & ~VF */
1621 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, cpu_VF
);
1623 tcg_gen_movi_i32(cpu_NF
, 0);
1624 tcg_gen_movi_i32(cpu_VF
, 0);
1627 /* MSR (immediate) - move immediate to processor state field */
1628 static void handle_msr_i(DisasContext
*s
, uint32_t insn
,
1629 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1632 int op
= op1
<< 3 | op2
;
1634 /* End the TB by default, chaining is ok. */
1635 s
->base
.is_jmp
= DISAS_TOO_MANY
;
1638 case 0x00: /* CFINV */
1639 if (crm
!= 0 || !dc_isar_feature(aa64_condm_4
, s
)) {
1640 goto do_unallocated
;
1642 tcg_gen_xori_i32(cpu_CF
, cpu_CF
, 1);
1643 s
->base
.is_jmp
= DISAS_NEXT
;
1646 case 0x01: /* XAFlag */
1647 if (crm
!= 0 || !dc_isar_feature(aa64_condm_5
, s
)) {
1648 goto do_unallocated
;
1651 s
->base
.is_jmp
= DISAS_NEXT
;
1654 case 0x02: /* AXFlag */
1655 if (crm
!= 0 || !dc_isar_feature(aa64_condm_5
, s
)) {
1656 goto do_unallocated
;
1659 s
->base
.is_jmp
= DISAS_NEXT
;
1662 case 0x03: /* UAO */
1663 if (!dc_isar_feature(aa64_uao
, s
) || s
->current_el
== 0) {
1664 goto do_unallocated
;
1667 set_pstate_bits(PSTATE_UAO
);
1669 clear_pstate_bits(PSTATE_UAO
);
1671 t1
= tcg_const_i32(s
->current_el
);
1672 gen_helper_rebuild_hflags_a64(cpu_env
, t1
);
1673 tcg_temp_free_i32(t1
);
1676 case 0x04: /* PAN */
1677 if (!dc_isar_feature(aa64_pan
, s
) || s
->current_el
== 0) {
1678 goto do_unallocated
;
1681 set_pstate_bits(PSTATE_PAN
);
1683 clear_pstate_bits(PSTATE_PAN
);
1685 t1
= tcg_const_i32(s
->current_el
);
1686 gen_helper_rebuild_hflags_a64(cpu_env
, t1
);
1687 tcg_temp_free_i32(t1
);
1690 case 0x05: /* SPSel */
1691 if (s
->current_el
== 0) {
1692 goto do_unallocated
;
1694 t1
= tcg_const_i32(crm
& PSTATE_SP
);
1695 gen_helper_msr_i_spsel(cpu_env
, t1
);
1696 tcg_temp_free_i32(t1
);
1699 case 0x19: /* SSBS */
1700 if (!dc_isar_feature(aa64_ssbs
, s
)) {
1701 goto do_unallocated
;
1704 set_pstate_bits(PSTATE_SSBS
);
1706 clear_pstate_bits(PSTATE_SSBS
);
1708 /* Don't need to rebuild hflags since SSBS is a nop */
1711 case 0x1a: /* DIT */
1712 if (!dc_isar_feature(aa64_dit
, s
)) {
1713 goto do_unallocated
;
1716 set_pstate_bits(PSTATE_DIT
);
1718 clear_pstate_bits(PSTATE_DIT
);
1720 /* There's no need to rebuild hflags because DIT is a nop */
1723 case 0x1e: /* DAIFSet */
1724 t1
= tcg_const_i32(crm
);
1725 gen_helper_msr_i_daifset(cpu_env
, t1
);
1726 tcg_temp_free_i32(t1
);
1729 case 0x1f: /* DAIFClear */
1730 t1
= tcg_const_i32(crm
);
1731 gen_helper_msr_i_daifclear(cpu_env
, t1
);
1732 tcg_temp_free_i32(t1
);
1733 /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */
1734 s
->base
.is_jmp
= DISAS_UPDATE_EXIT
;
1737 case 0x1c: /* TCO */
1738 if (dc_isar_feature(aa64_mte
, s
)) {
1739 /* Full MTE is enabled -- set the TCO bit as directed. */
1741 set_pstate_bits(PSTATE_TCO
);
1743 clear_pstate_bits(PSTATE_TCO
);
1745 t1
= tcg_const_i32(s
->current_el
);
1746 gen_helper_rebuild_hflags_a64(cpu_env
, t1
);
1747 tcg_temp_free_i32(t1
);
1748 /* Many factors, including TCO, go into MTE_ACTIVE. */
1749 s
->base
.is_jmp
= DISAS_UPDATE_NOCHAIN
;
1750 } else if (dc_isar_feature(aa64_mte_insn_reg
, s
)) {
1751 /* Only "instructions accessible at EL0" -- PSTATE.TCO is WI. */
1752 s
->base
.is_jmp
= DISAS_NEXT
;
1754 goto do_unallocated
;
1760 unallocated_encoding(s
);
1765 static void gen_get_nzcv(TCGv_i64 tcg_rt
)
1767 TCGv_i32 tmp
= tcg_temp_new_i32();
1768 TCGv_i32 nzcv
= tcg_temp_new_i32();
1770 /* build bit 31, N */
1771 tcg_gen_andi_i32(nzcv
, cpu_NF
, (1U << 31));
1772 /* build bit 30, Z */
1773 tcg_gen_setcondi_i32(TCG_COND_EQ
, tmp
, cpu_ZF
, 0);
1774 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 30, 1);
1775 /* build bit 29, C */
1776 tcg_gen_deposit_i32(nzcv
, nzcv
, cpu_CF
, 29, 1);
1777 /* build bit 28, V */
1778 tcg_gen_shri_i32(tmp
, cpu_VF
, 31);
1779 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 28, 1);
1780 /* generate result */
1781 tcg_gen_extu_i32_i64(tcg_rt
, nzcv
);
1783 tcg_temp_free_i32(nzcv
);
1784 tcg_temp_free_i32(tmp
);
1787 static void gen_set_nzcv(TCGv_i64 tcg_rt
)
1789 TCGv_i32 nzcv
= tcg_temp_new_i32();
1791 /* take NZCV from R[t] */
1792 tcg_gen_extrl_i64_i32(nzcv
, tcg_rt
);
1795 tcg_gen_andi_i32(cpu_NF
, nzcv
, (1U << 31));
1797 tcg_gen_andi_i32(cpu_ZF
, nzcv
, (1 << 30));
1798 tcg_gen_setcondi_i32(TCG_COND_EQ
, cpu_ZF
, cpu_ZF
, 0);
1800 tcg_gen_andi_i32(cpu_CF
, nzcv
, (1 << 29));
1801 tcg_gen_shri_i32(cpu_CF
, cpu_CF
, 29);
1803 tcg_gen_andi_i32(cpu_VF
, nzcv
, (1 << 28));
1804 tcg_gen_shli_i32(cpu_VF
, cpu_VF
, 3);
1805 tcg_temp_free_i32(nzcv
);
1808 /* MRS - move from system register
1809 * MSR (register) - move to system register
1812 * These are all essentially the same insn in 'read' and 'write'
1813 * versions, with varying op0 fields.
1815 static void handle_sys(DisasContext
*s
, uint32_t insn
, bool isread
,
1816 unsigned int op0
, unsigned int op1
, unsigned int op2
,
1817 unsigned int crn
, unsigned int crm
, unsigned int rt
)
1819 const ARMCPRegInfo
*ri
;
1822 ri
= get_arm_cp_reginfo(s
->cp_regs
,
1823 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP
,
1824 crn
, crm
, op0
, op1
, op2
));
1827 /* Unknown register; this might be a guest error or a QEMU
1828 * unimplemented feature.
1830 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch64 "
1831 "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
1832 isread
? "read" : "write", op0
, op1
, crn
, crm
, op2
);
1833 unallocated_encoding(s
);
1837 /* Check access permissions */
1838 if (!cp_access_ok(s
->current_el
, ri
, isread
)) {
1839 unallocated_encoding(s
);
1844 /* Emit code to perform further access permissions checks at
1845 * runtime; this may result in an exception.
1848 TCGv_i32 tcg_syn
, tcg_isread
;
1851 gen_a64_set_pc_im(s
->pc_curr
);
1852 tmpptr
= tcg_const_ptr(ri
);
1853 syndrome
= syn_aa64_sysregtrap(op0
, op1
, op2
, crn
, crm
, rt
, isread
);
1854 tcg_syn
= tcg_const_i32(syndrome
);
1855 tcg_isread
= tcg_const_i32(isread
);
1856 gen_helper_access_check_cp_reg(cpu_env
, tmpptr
, tcg_syn
, tcg_isread
);
1857 tcg_temp_free_ptr(tmpptr
);
1858 tcg_temp_free_i32(tcg_syn
);
1859 tcg_temp_free_i32(tcg_isread
);
1860 } else if (ri
->type
& ARM_CP_RAISES_EXC
) {
1862 * The readfn or writefn might raise an exception;
1863 * synchronize the CPU state in case it does.
1865 gen_a64_set_pc_im(s
->pc_curr
);
1868 /* Handle special cases first */
1869 switch (ri
->type
& ~(ARM_CP_FLAG_MASK
& ~ARM_CP_SPECIAL
)) {
1873 tcg_rt
= cpu_reg(s
, rt
);
1875 gen_get_nzcv(tcg_rt
);
1877 gen_set_nzcv(tcg_rt
);
1880 case ARM_CP_CURRENTEL
:
1881 /* Reads as current EL value from pstate, which is
1882 * guaranteed to be constant by the tb flags.
1884 tcg_rt
= cpu_reg(s
, rt
);
1885 tcg_gen_movi_i64(tcg_rt
, s
->current_el
<< 2);
1888 /* Writes clear the aligned block of memory which rt points into. */
1889 if (s
->mte_active
[0]) {
1893 desc
= FIELD_DP32(desc
, MTEDESC
, MIDX
, get_mem_index(s
));
1894 desc
= FIELD_DP32(desc
, MTEDESC
, TBI
, s
->tbid
);
1895 desc
= FIELD_DP32(desc
, MTEDESC
, TCMA
, s
->tcma
);
1896 t_desc
= tcg_const_i32(desc
);
1898 tcg_rt
= new_tmp_a64(s
);
1899 gen_helper_mte_check_zva(tcg_rt
, cpu_env
, t_desc
, cpu_reg(s
, rt
));
1900 tcg_temp_free_i32(t_desc
);
1902 tcg_rt
= clean_data_tbi(s
, cpu_reg(s
, rt
));
1904 gen_helper_dc_zva(cpu_env
, tcg_rt
);
1908 TCGv_i64 clean_addr
, tag
;
1911 * DC_GVA, like DC_ZVA, requires that we supply the original
1912 * pointer for an invalid page. Probe that address first.
1914 tcg_rt
= cpu_reg(s
, rt
);
1915 clean_addr
= clean_data_tbi(s
, tcg_rt
);
1916 gen_probe_access(s
, clean_addr
, MMU_DATA_STORE
, MO_8
);
1919 /* Extract the tag from the register to match STZGM. */
1920 tag
= tcg_temp_new_i64();
1921 tcg_gen_shri_i64(tag
, tcg_rt
, 56);
1922 gen_helper_stzgm_tags(cpu_env
, clean_addr
, tag
);
1923 tcg_temp_free_i64(tag
);
1927 case ARM_CP_DC_GZVA
:
1929 TCGv_i64 clean_addr
, tag
;
1931 /* For DC_GZVA, we can rely on DC_ZVA for the proper fault. */
1932 tcg_rt
= cpu_reg(s
, rt
);
1933 clean_addr
= clean_data_tbi(s
, tcg_rt
);
1934 gen_helper_dc_zva(cpu_env
, clean_addr
);
1937 /* Extract the tag from the register to match STZGM. */
1938 tag
= tcg_temp_new_i64();
1939 tcg_gen_shri_i64(tag
, tcg_rt
, 56);
1940 gen_helper_stzgm_tags(cpu_env
, clean_addr
, tag
);
1941 tcg_temp_free_i64(tag
);
1948 if ((ri
->type
& ARM_CP_FPU
) && !fp_access_check(s
)) {
1950 } else if ((ri
->type
& ARM_CP_SVE
) && !sve_access_check(s
)) {
1954 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1958 tcg_rt
= cpu_reg(s
, rt
);
1961 if (ri
->type
& ARM_CP_CONST
) {
1962 tcg_gen_movi_i64(tcg_rt
, ri
->resetvalue
);
1963 } else if (ri
->readfn
) {
1965 tmpptr
= tcg_const_ptr(ri
);
1966 gen_helper_get_cp_reg64(tcg_rt
, cpu_env
, tmpptr
);
1967 tcg_temp_free_ptr(tmpptr
);
1969 tcg_gen_ld_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1972 if (ri
->type
& ARM_CP_CONST
) {
1973 /* If not forbidden by access permissions, treat as WI */
1975 } else if (ri
->writefn
) {
1977 tmpptr
= tcg_const_ptr(ri
);
1978 gen_helper_set_cp_reg64(cpu_env
, tmpptr
, tcg_rt
);
1979 tcg_temp_free_ptr(tmpptr
);
1981 tcg_gen_st_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1985 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1986 /* I/O operations must end the TB here (whether read or write) */
1987 s
->base
.is_jmp
= DISAS_UPDATE_EXIT
;
1989 if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
1991 * A write to any coprocessor regiser that ends a TB
1992 * must rebuild the hflags for the next TB.
1994 TCGv_i32 tcg_el
= tcg_const_i32(s
->current_el
);
1995 gen_helper_rebuild_hflags_a64(cpu_env
, tcg_el
);
1996 tcg_temp_free_i32(tcg_el
);
1998 * We default to ending the TB on a coprocessor register write,
1999 * but allow this to be suppressed by the register definition
2000 * (usually only necessary to work around guest bugs).
2002 s
->base
.is_jmp
= DISAS_UPDATE_EXIT
;
2007 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
2008 * +---------------------+---+-----+-----+-------+-------+-----+------+
2009 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
2010 * +---------------------+---+-----+-----+-------+-------+-----+------+
2012 static void disas_system(DisasContext
*s
, uint32_t insn
)
2014 unsigned int l
, op0
, op1
, crn
, crm
, op2
, rt
;
2015 l
= extract32(insn
, 21, 1);
2016 op0
= extract32(insn
, 19, 2);
2017 op1
= extract32(insn
, 16, 3);
2018 crn
= extract32(insn
, 12, 4);
2019 crm
= extract32(insn
, 8, 4);
2020 op2
= extract32(insn
, 5, 3);
2021 rt
= extract32(insn
, 0, 5);
2024 if (l
|| rt
!= 31) {
2025 unallocated_encoding(s
);
2029 case 2: /* HINT (including allocated hints like NOP, YIELD, etc) */
2030 handle_hint(s
, insn
, op1
, op2
, crm
);
2032 case 3: /* CLREX, DSB, DMB, ISB */
2033 handle_sync(s
, insn
, op1
, op2
, crm
);
2035 case 4: /* MSR (immediate) */
2036 handle_msr_i(s
, insn
, op1
, op2
, crm
);
2039 unallocated_encoding(s
);
2044 handle_sys(s
, insn
, l
, op0
, op1
, op2
, crn
, crm
, rt
);
2047 /* Exception generation
2049 * 31 24 23 21 20 5 4 2 1 0
2050 * +-----------------+-----+------------------------+-----+----+
2051 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
2052 * +-----------------------+------------------------+----------+
2054 static void disas_exc(DisasContext
*s
, uint32_t insn
)
2056 int opc
= extract32(insn
, 21, 3);
2057 int op2_ll
= extract32(insn
, 0, 5);
2058 int imm16
= extract32(insn
, 5, 16);
2063 /* For SVC, HVC and SMC we advance the single-step state
2064 * machine before taking the exception. This is architecturally
2065 * mandated, to ensure that single-stepping a system call
2066 * instruction works properly.
2071 gen_exception_insn(s
, s
->base
.pc_next
, EXCP_SWI
,
2072 syn_aa64_svc(imm16
), default_exception_el(s
));
2075 if (s
->current_el
== 0) {
2076 unallocated_encoding(s
);
2079 /* The pre HVC helper handles cases when HVC gets trapped
2080 * as an undefined insn by runtime configuration.
2082 gen_a64_set_pc_im(s
->pc_curr
);
2083 gen_helper_pre_hvc(cpu_env
);
2085 gen_exception_insn(s
, s
->base
.pc_next
, EXCP_HVC
,
2086 syn_aa64_hvc(imm16
), 2);
2089 if (s
->current_el
== 0) {
2090 unallocated_encoding(s
);
2093 gen_a64_set_pc_im(s
->pc_curr
);
2094 tmp
= tcg_const_i32(syn_aa64_smc(imm16
));
2095 gen_helper_pre_smc(cpu_env
, tmp
);
2096 tcg_temp_free_i32(tmp
);
2098 gen_exception_insn(s
, s
->base
.pc_next
, EXCP_SMC
,
2099 syn_aa64_smc(imm16
), 3);
2102 unallocated_encoding(s
);
2108 unallocated_encoding(s
);
2112 gen_exception_bkpt_insn(s
, syn_aa64_bkpt(imm16
));
2116 unallocated_encoding(s
);
2119 /* HLT. This has two purposes.
2120 * Architecturally, it is an external halting debug instruction.
2121 * Since QEMU doesn't implement external debug, we treat this as
2122 * it is required for halting debug disabled: it will UNDEF.
2123 * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
2125 if (semihosting_enabled() && imm16
== 0xf000) {
2126 #ifndef CONFIG_USER_ONLY
2127 /* In system mode, don't allow userspace access to semihosting,
2128 * to provide some semblance of security (and for consistency
2129 * with our 32-bit semihosting).
2131 if (s
->current_el
== 0) {
2132 unsupported_encoding(s
, insn
);
2136 gen_exception_internal_insn(s
, s
->pc_curr
, EXCP_SEMIHOST
);
2138 unsupported_encoding(s
, insn
);
2142 if (op2_ll
< 1 || op2_ll
> 3) {
2143 unallocated_encoding(s
);
2146 /* DCPS1, DCPS2, DCPS3 */
2147 unsupported_encoding(s
, insn
);
2150 unallocated_encoding(s
);
2155 /* Unconditional branch (register)
2156 * 31 25 24 21 20 16 15 10 9 5 4 0
2157 * +---------------+-------+-------+-------+------+-------+
2158 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
2159 * +---------------+-------+-------+-------+------+-------+
2161 static void disas_uncond_b_reg(DisasContext
*s
, uint32_t insn
)
2163 unsigned int opc
, op2
, op3
, rn
, op4
;
2164 unsigned btype_mod
= 2; /* 0: BR, 1: BLR, 2: other */
2168 opc
= extract32(insn
, 21, 4);
2169 op2
= extract32(insn
, 16, 5);
2170 op3
= extract32(insn
, 10, 6);
2171 rn
= extract32(insn
, 5, 5);
2172 op4
= extract32(insn
, 0, 5);
2175 goto do_unallocated
;
2187 goto do_unallocated
;
2189 dst
= cpu_reg(s
, rn
);
2194 if (!dc_isar_feature(aa64_pauth
, s
)) {
2195 goto do_unallocated
;
2199 if (rn
!= 0x1f || op4
!= 0x1f) {
2200 goto do_unallocated
;
2203 modifier
= cpu_X
[31];
2205 /* BRAAZ, BRABZ, BLRAAZ, BLRABZ */
2207 goto do_unallocated
;
2209 modifier
= new_tmp_a64_zero(s
);
2211 if (s
->pauth_active
) {
2212 dst
= new_tmp_a64(s
);
2214 gen_helper_autia(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2216 gen_helper_autib(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2219 dst
= cpu_reg(s
, rn
);
2224 goto do_unallocated
;
2226 gen_a64_set_pc(s
, dst
);
2227 /* BLR also needs to load return address */
2229 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->base
.pc_next
);
2235 if (!dc_isar_feature(aa64_pauth
, s
)) {
2236 goto do_unallocated
;
2238 if ((op3
& ~1) != 2) {
2239 goto do_unallocated
;
2241 btype_mod
= opc
& 1;
2242 if (s
->pauth_active
) {
2243 dst
= new_tmp_a64(s
);
2244 modifier
= cpu_reg_sp(s
, op4
);
2246 gen_helper_autia(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2248 gen_helper_autib(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2251 dst
= cpu_reg(s
, rn
);
2253 gen_a64_set_pc(s
, dst
);
2254 /* BLRAA also needs to load return address */
2256 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->base
.pc_next
);
2261 if (s
->current_el
== 0) {
2262 goto do_unallocated
;
2267 goto do_unallocated
;
2269 dst
= tcg_temp_new_i64();
2270 tcg_gen_ld_i64(dst
, cpu_env
,
2271 offsetof(CPUARMState
, elr_el
[s
->current_el
]));
2274 case 2: /* ERETAA */
2275 case 3: /* ERETAB */
2276 if (!dc_isar_feature(aa64_pauth
, s
)) {
2277 goto do_unallocated
;
2279 if (rn
!= 0x1f || op4
!= 0x1f) {
2280 goto do_unallocated
;
2282 dst
= tcg_temp_new_i64();
2283 tcg_gen_ld_i64(dst
, cpu_env
,
2284 offsetof(CPUARMState
, elr_el
[s
->current_el
]));
2285 if (s
->pauth_active
) {
2286 modifier
= cpu_X
[31];
2288 gen_helper_autia(dst
, cpu_env
, dst
, modifier
);
2290 gen_helper_autib(dst
, cpu_env
, dst
, modifier
);
2296 goto do_unallocated
;
2298 if (tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) {
2302 gen_helper_exception_return(cpu_env
, dst
);
2303 tcg_temp_free_i64(dst
);
2304 /* Must exit loop to check un-masked IRQs */
2305 s
->base
.is_jmp
= DISAS_EXIT
;
2309 if (op3
!= 0 || op4
!= 0 || rn
!= 0x1f) {
2310 goto do_unallocated
;
2312 unsupported_encoding(s
, insn
);
2318 unallocated_encoding(s
);
2322 switch (btype_mod
) {
2324 if (dc_isar_feature(aa64_bti
, s
)) {
2325 /* BR to {x16,x17} or !guard -> 1, else 3. */
2326 set_btype(s
, rn
== 16 || rn
== 17 || !s
->guarded_page
? 1 : 3);
2331 if (dc_isar_feature(aa64_bti
, s
)) {
2332 /* BLR sets BTYPE to 2, regardless of source guarded page. */
2337 default: /* RET or none of the above. */
2338 /* BTYPE will be set to 0 by normal end-of-insn processing. */
2342 s
->base
.is_jmp
= DISAS_JUMP
;
2345 /* Branches, exception generating and system instructions */
2346 static void disas_b_exc_sys(DisasContext
*s
, uint32_t insn
)
2348 switch (extract32(insn
, 25, 7)) {
2349 case 0x0a: case 0x0b:
2350 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
2351 disas_uncond_b_imm(s
, insn
);
2353 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
2354 disas_comp_b_imm(s
, insn
);
2356 case 0x1b: case 0x5b: /* Test & branch (immediate) */
2357 disas_test_b_imm(s
, insn
);
2359 case 0x2a: /* Conditional branch (immediate) */
2360 disas_cond_b_imm(s
, insn
);
2362 case 0x6a: /* Exception generation / System */
2363 if (insn
& (1 << 24)) {
2364 if (extract32(insn
, 22, 2) == 0) {
2365 disas_system(s
, insn
);
2367 unallocated_encoding(s
);
2373 case 0x6b: /* Unconditional branch (register) */
2374 disas_uncond_b_reg(s
, insn
);
2377 unallocated_encoding(s
);
2383 * Load/Store exclusive instructions are implemented by remembering
2384 * the value/address loaded, and seeing if these are the same
2385 * when the store is performed. This is not actually the architecturally
2386 * mandated semantics, but it works for typical guest code sequences
2387 * and avoids having to monitor regular stores.
2389 * The store exclusive uses the atomic cmpxchg primitives to avoid
2390 * races in multi-threaded linux-user and when MTTCG softmmu is
2393 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
2394 TCGv_i64 addr
, int size
, bool is_pair
)
2396 int idx
= get_mem_index(s
);
2397 MemOp memop
= s
->be_data
;
2399 g_assert(size
<= 3);
2401 g_assert(size
>= 2);
2403 /* The pair must be single-copy atomic for the doubleword. */
2404 memop
|= MO_64
| MO_ALIGN
;
2405 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2406 if (s
->be_data
== MO_LE
) {
2407 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 0, 32);
2408 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 32, 32);
2410 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 32, 32);
2411 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 0, 32);
2414 /* The pair must be single-copy atomic for *each* doubleword, not
2415 the entire quadword, however it must be quadword aligned. */
2417 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
,
2418 memop
| MO_ALIGN_16
);
2420 TCGv_i64 addr2
= tcg_temp_new_i64();
2421 tcg_gen_addi_i64(addr2
, addr
, 8);
2422 tcg_gen_qemu_ld_i64(cpu_exclusive_high
, addr2
, idx
, memop
);
2423 tcg_temp_free_i64(addr2
);
2425 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2426 tcg_gen_mov_i64(cpu_reg(s
, rt2
), cpu_exclusive_high
);
2429 memop
|= size
| MO_ALIGN
;
2430 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2431 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2433 tcg_gen_mov_i64(cpu_exclusive_addr
, addr
);
2436 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
2437 TCGv_i64 addr
, int size
, int is_pair
)
2439 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
2440 * && (!is_pair || env->exclusive_high == [addr + datasize])) {
2443 * [addr + datasize] = {Rt2};
2449 * env->exclusive_addr = -1;
2451 TCGLabel
*fail_label
= gen_new_label();
2452 TCGLabel
*done_label
= gen_new_label();
2455 tcg_gen_brcond_i64(TCG_COND_NE
, addr
, cpu_exclusive_addr
, fail_label
);
2457 tmp
= tcg_temp_new_i64();
2460 if (s
->be_data
== MO_LE
) {
2461 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2463 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt2
), cpu_reg(s
, rt
));
2465 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
,
2466 cpu_exclusive_val
, tmp
,
2468 MO_64
| MO_ALIGN
| s
->be_data
);
2469 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2470 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2471 if (!HAVE_CMPXCHG128
) {
2472 gen_helper_exit_atomic(cpu_env
);
2473 s
->base
.is_jmp
= DISAS_NORETURN
;
2474 } else if (s
->be_data
== MO_LE
) {
2475 gen_helper_paired_cmpxchg64_le_parallel(tmp
, cpu_env
,
2480 gen_helper_paired_cmpxchg64_be_parallel(tmp
, cpu_env
,
2485 } else if (s
->be_data
== MO_LE
) {
2486 gen_helper_paired_cmpxchg64_le(tmp
, cpu_env
, cpu_exclusive_addr
,
2487 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2489 gen_helper_paired_cmpxchg64_be(tmp
, cpu_env
, cpu_exclusive_addr
,
2490 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2493 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
, cpu_exclusive_val
,
2494 cpu_reg(s
, rt
), get_mem_index(s
),
2495 size
| MO_ALIGN
| s
->be_data
);
2496 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2498 tcg_gen_mov_i64(cpu_reg(s
, rd
), tmp
);
2499 tcg_temp_free_i64(tmp
);
2500 tcg_gen_br(done_label
);
2502 gen_set_label(fail_label
);
2503 tcg_gen_movi_i64(cpu_reg(s
, rd
), 1);
2504 gen_set_label(done_label
);
2505 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
2508 static void gen_compare_and_swap(DisasContext
*s
, int rs
, int rt
,
2511 TCGv_i64 tcg_rs
= cpu_reg(s
, rs
);
2512 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2513 int memidx
= get_mem_index(s
);
2514 TCGv_i64 clean_addr
;
2517 gen_check_sp_alignment(s
);
2519 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
), true, rn
!= 31, size
);
2520 tcg_gen_atomic_cmpxchg_i64(tcg_rs
, clean_addr
, tcg_rs
, tcg_rt
, memidx
,
2521 size
| MO_ALIGN
| s
->be_data
);
2524 static void gen_compare_and_swap_pair(DisasContext
*s
, int rs
, int rt
,
2527 TCGv_i64 s1
= cpu_reg(s
, rs
);
2528 TCGv_i64 s2
= cpu_reg(s
, rs
+ 1);
2529 TCGv_i64 t1
= cpu_reg(s
, rt
);
2530 TCGv_i64 t2
= cpu_reg(s
, rt
+ 1);
2531 TCGv_i64 clean_addr
;
2532 int memidx
= get_mem_index(s
);
2535 gen_check_sp_alignment(s
);
2538 /* This is a single atomic access, despite the "pair". */
2539 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
), true, rn
!= 31, size
+ 1);
2542 TCGv_i64 cmp
= tcg_temp_new_i64();
2543 TCGv_i64 val
= tcg_temp_new_i64();
2545 if (s
->be_data
== MO_LE
) {
2546 tcg_gen_concat32_i64(val
, t1
, t2
);
2547 tcg_gen_concat32_i64(cmp
, s1
, s2
);
2549 tcg_gen_concat32_i64(val
, t2
, t1
);
2550 tcg_gen_concat32_i64(cmp
, s2
, s1
);
2553 tcg_gen_atomic_cmpxchg_i64(cmp
, clean_addr
, cmp
, val
, memidx
,
2554 MO_64
| MO_ALIGN
| s
->be_data
);
2555 tcg_temp_free_i64(val
);
2557 if (s
->be_data
== MO_LE
) {
2558 tcg_gen_extr32_i64(s1
, s2
, cmp
);
2560 tcg_gen_extr32_i64(s2
, s1
, cmp
);
2562 tcg_temp_free_i64(cmp
);
2563 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2564 if (HAVE_CMPXCHG128
) {
2565 TCGv_i32 tcg_rs
= tcg_const_i32(rs
);
2566 if (s
->be_data
== MO_LE
) {
2567 gen_helper_casp_le_parallel(cpu_env
, tcg_rs
,
2568 clean_addr
, t1
, t2
);
2570 gen_helper_casp_be_parallel(cpu_env
, tcg_rs
,
2571 clean_addr
, t1
, t2
);
2573 tcg_temp_free_i32(tcg_rs
);
2575 gen_helper_exit_atomic(cpu_env
);
2576 s
->base
.is_jmp
= DISAS_NORETURN
;
2579 TCGv_i64 d1
= tcg_temp_new_i64();
2580 TCGv_i64 d2
= tcg_temp_new_i64();
2581 TCGv_i64 a2
= tcg_temp_new_i64();
2582 TCGv_i64 c1
= tcg_temp_new_i64();
2583 TCGv_i64 c2
= tcg_temp_new_i64();
2584 TCGv_i64 zero
= tcg_const_i64(0);
2586 /* Load the two words, in memory order. */
2587 tcg_gen_qemu_ld_i64(d1
, clean_addr
, memidx
,
2588 MO_64
| MO_ALIGN_16
| s
->be_data
);
2589 tcg_gen_addi_i64(a2
, clean_addr
, 8);
2590 tcg_gen_qemu_ld_i64(d2
, a2
, memidx
, MO_64
| s
->be_data
);
2592 /* Compare the two words, also in memory order. */
2593 tcg_gen_setcond_i64(TCG_COND_EQ
, c1
, d1
, s1
);
2594 tcg_gen_setcond_i64(TCG_COND_EQ
, c2
, d2
, s2
);
2595 tcg_gen_and_i64(c2
, c2
, c1
);
2597 /* If compare equal, write back new data, else write back old data. */
2598 tcg_gen_movcond_i64(TCG_COND_NE
, c1
, c2
, zero
, t1
, d1
);
2599 tcg_gen_movcond_i64(TCG_COND_NE
, c2
, c2
, zero
, t2
, d2
);
2600 tcg_gen_qemu_st_i64(c1
, clean_addr
, memidx
, MO_64
| s
->be_data
);
2601 tcg_gen_qemu_st_i64(c2
, a2
, memidx
, MO_64
| s
->be_data
);
2602 tcg_temp_free_i64(a2
);
2603 tcg_temp_free_i64(c1
);
2604 tcg_temp_free_i64(c2
);
2605 tcg_temp_free_i64(zero
);
2607 /* Write back the data from memory to Rs. */
2608 tcg_gen_mov_i64(s1
, d1
);
2609 tcg_gen_mov_i64(s2
, d2
);
2610 tcg_temp_free_i64(d1
);
2611 tcg_temp_free_i64(d2
);
2615 /* Update the Sixty-Four bit (SF) registersize. This logic is derived
2616 * from the ARMv8 specs for LDR (Shared decode for all encodings).
2618 static bool disas_ldst_compute_iss_sf(int size
, bool is_signed
, int opc
)
2620 int opc0
= extract32(opc
, 0, 1);
2624 regsize
= opc0
? 32 : 64;
2626 regsize
= size
== 3 ? 64 : 32;
2628 return regsize
== 64;
2631 /* Load/store exclusive
2633 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
2634 * +-----+-------------+----+---+----+------+----+-------+------+------+
2635 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
2636 * +-----+-------------+----+---+----+------+----+-------+------+------+
2638 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
2639 * L: 0 -> store, 1 -> load
2640 * o2: 0 -> exclusive, 1 -> not
2641 * o1: 0 -> single register, 1 -> register pair
2642 * o0: 1 -> load-acquire/store-release, 0 -> not
2644 static void disas_ldst_excl(DisasContext
*s
, uint32_t insn
)
2646 int rt
= extract32(insn
, 0, 5);
2647 int rn
= extract32(insn
, 5, 5);
2648 int rt2
= extract32(insn
, 10, 5);
2649 int rs
= extract32(insn
, 16, 5);
2650 int is_lasr
= extract32(insn
, 15, 1);
2651 int o2_L_o1_o0
= extract32(insn
, 21, 3) * 2 | is_lasr
;
2652 int size
= extract32(insn
, 30, 2);
2653 TCGv_i64 clean_addr
;
2655 switch (o2_L_o1_o0
) {
2656 case 0x0: /* STXR */
2657 case 0x1: /* STLXR */
2659 gen_check_sp_alignment(s
);
2662 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2664 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2665 true, rn
!= 31, size
);
2666 gen_store_exclusive(s
, rs
, rt
, rt2
, clean_addr
, size
, false);
2669 case 0x4: /* LDXR */
2670 case 0x5: /* LDAXR */
2672 gen_check_sp_alignment(s
);
2674 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2675 false, rn
!= 31, size
);
2677 gen_load_exclusive(s
, rt
, rt2
, clean_addr
, size
, false);
2679 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2683 case 0x8: /* STLLR */
2684 if (!dc_isar_feature(aa64_lor
, s
)) {
2687 /* StoreLORelease is the same as Store-Release for QEMU. */
2689 case 0x9: /* STLR */
2690 /* Generate ISS for non-exclusive accesses including LASR. */
2692 gen_check_sp_alignment(s
);
2694 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2695 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2696 true, rn
!= 31, size
);
2697 /* TODO: ARMv8.4-LSE SCTLR.nAA */
2698 do_gpr_st(s
, cpu_reg(s
, rt
), clean_addr
, size
| MO_ALIGN
, true, rt
,
2699 disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2702 case 0xc: /* LDLAR */
2703 if (!dc_isar_feature(aa64_lor
, s
)) {
2706 /* LoadLOAcquire is the same as Load-Acquire for QEMU. */
2708 case 0xd: /* LDAR */
2709 /* Generate ISS for non-exclusive accesses including LASR. */
2711 gen_check_sp_alignment(s
);
2713 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2714 false, rn
!= 31, size
);
2715 /* TODO: ARMv8.4-LSE SCTLR.nAA */
2716 do_gpr_ld(s
, cpu_reg(s
, rt
), clean_addr
, size
| MO_ALIGN
, false, true,
2717 rt
, disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2718 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2721 case 0x2: case 0x3: /* CASP / STXP */
2722 if (size
& 2) { /* STXP / STLXP */
2724 gen_check_sp_alignment(s
);
2727 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2729 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2730 true, rn
!= 31, size
);
2731 gen_store_exclusive(s
, rs
, rt
, rt2
, clean_addr
, size
, true);
2735 && ((rt
| rs
) & 1) == 0
2736 && dc_isar_feature(aa64_atomics
, s
)) {
2738 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2743 case 0x6: case 0x7: /* CASPA / LDXP */
2744 if (size
& 2) { /* LDXP / LDAXP */
2746 gen_check_sp_alignment(s
);
2748 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
),
2749 false, rn
!= 31, size
);
2751 gen_load_exclusive(s
, rt
, rt2
, clean_addr
, size
, true);
2753 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2758 && ((rt
| rs
) & 1) == 0
2759 && dc_isar_feature(aa64_atomics
, s
)) {
2760 /* CASPA / CASPAL */
2761 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2767 case 0xb: /* CASL */
2768 case 0xe: /* CASA */
2769 case 0xf: /* CASAL */
2770 if (rt2
== 31 && dc_isar_feature(aa64_atomics
, s
)) {
2771 gen_compare_and_swap(s
, rs
, rt
, rn
, size
);
2776 unallocated_encoding(s
);
2780 * Load register (literal)
2782 * 31 30 29 27 26 25 24 23 5 4 0
2783 * +-----+-------+---+-----+-------------------+-------+
2784 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
2785 * +-----+-------+---+-----+-------------------+-------+
2787 * V: 1 -> vector (simd/fp)
2788 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
2789 * 10-> 32 bit signed, 11 -> prefetch
2790 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
2792 static void disas_ld_lit(DisasContext
*s
, uint32_t insn
)
2794 int rt
= extract32(insn
, 0, 5);
2795 int64_t imm
= sextract32(insn
, 5, 19) << 2;
2796 bool is_vector
= extract32(insn
, 26, 1);
2797 int opc
= extract32(insn
, 30, 2);
2798 bool is_signed
= false;
2800 TCGv_i64 tcg_rt
, clean_addr
;
2804 unallocated_encoding(s
);
2808 if (!fp_access_check(s
)) {
2813 /* PRFM (literal) : prefetch */
2816 size
= 2 + extract32(opc
, 0, 1);
2817 is_signed
= extract32(opc
, 1, 1);
2820 tcg_rt
= cpu_reg(s
, rt
);
2822 clean_addr
= tcg_const_i64(s
->pc_curr
+ imm
);
2824 do_fp_ld(s
, rt
, clean_addr
, size
);
2826 /* Only unsigned 32bit loads target 32bit registers. */
2827 bool iss_sf
= opc
!= 0;
2829 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
+ is_signed
* MO_SIGN
,
2830 false, true, rt
, iss_sf
, false);
2832 tcg_temp_free_i64(clean_addr
);
2836 * LDNP (Load Pair - non-temporal hint)
2837 * LDP (Load Pair - non vector)
2838 * LDPSW (Load Pair Signed Word - non vector)
2839 * STNP (Store Pair - non-temporal hint)
2840 * STP (Store Pair - non vector)
2841 * LDNP (Load Pair of SIMD&FP - non-temporal hint)
2842 * LDP (Load Pair of SIMD&FP)
2843 * STNP (Store Pair of SIMD&FP - non-temporal hint)
2844 * STP (Store Pair of SIMD&FP)
2846 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
2847 * +-----+-------+---+---+-------+---+-----------------------------+
2848 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
2849 * +-----+-------+---+---+-------+---+-------+-------+------+------+
2851 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
2853 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
2854 * V: 0 -> GPR, 1 -> Vector
2855 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
2856 * 10 -> signed offset, 11 -> pre-index
2857 * L: 0 -> Store 1 -> Load
2859 * Rt, Rt2 = GPR or SIMD registers to be stored
2860 * Rn = general purpose register containing address
2861 * imm7 = signed offset (multiple of 4 or 8 depending on size)
2863 static void disas_ldst_pair(DisasContext
*s
, uint32_t insn
)
2865 int rt
= extract32(insn
, 0, 5);
2866 int rn
= extract32(insn
, 5, 5);
2867 int rt2
= extract32(insn
, 10, 5);
2868 uint64_t offset
= sextract64(insn
, 15, 7);
2869 int index
= extract32(insn
, 23, 2);
2870 bool is_vector
= extract32(insn
, 26, 1);
2871 bool is_load
= extract32(insn
, 22, 1);
2872 int opc
= extract32(insn
, 30, 2);
2874 bool is_signed
= false;
2875 bool postindex
= false;
2877 bool set_tag
= false;
2879 TCGv_i64 clean_addr
, dirty_addr
;
2884 unallocated_encoding(s
);
2890 } else if (opc
== 1 && !is_load
) {
2892 if (!dc_isar_feature(aa64_mte_insn_reg
, s
) || index
== 0) {
2893 unallocated_encoding(s
);
2899 size
= 2 + extract32(opc
, 1, 1);
2900 is_signed
= extract32(opc
, 0, 1);
2901 if (!is_load
&& is_signed
) {
2902 unallocated_encoding(s
);
2908 case 1: /* post-index */
2913 /* signed offset with "non-temporal" hint. Since we don't emulate
2914 * caches we don't care about hints to the cache system about
2915 * data access patterns, and handle this identically to plain
2919 /* There is no non-temporal-hint version of LDPSW */
2920 unallocated_encoding(s
);
2925 case 2: /* signed offset, rn not updated */
2928 case 3: /* pre-index */
2934 if (is_vector
&& !fp_access_check(s
)) {
2938 offset
<<= (set_tag
? LOG2_TAG_GRANULE
: size
);
2941 gen_check_sp_alignment(s
);
2944 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
2946 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
2952 * TODO: We could rely on the stores below, at least for
2953 * system mode, if we arrange to add MO_ALIGN_16.
2955 gen_helper_stg_stub(cpu_env
, dirty_addr
);
2956 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2957 gen_helper_stg_parallel(cpu_env
, dirty_addr
, dirty_addr
);
2959 gen_helper_stg(cpu_env
, dirty_addr
, dirty_addr
);
2963 clean_addr
= gen_mte_checkN(s
, dirty_addr
, !is_load
,
2964 (wback
|| rn
!= 31) && !set_tag
, 2 << size
);
2968 do_fp_ld(s
, rt
, clean_addr
, size
);
2970 do_fp_st(s
, rt
, clean_addr
, size
);
2972 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2974 do_fp_ld(s
, rt2
, clean_addr
, size
);
2976 do_fp_st(s
, rt2
, clean_addr
, size
);
2979 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2980 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt2
);
2983 TCGv_i64 tmp
= tcg_temp_new_i64();
2985 /* Do not modify tcg_rt before recognizing any exception
2986 * from the second load.
2988 do_gpr_ld(s
, tmp
, clean_addr
, size
+ is_signed
* MO_SIGN
,
2989 false, false, 0, false, false);
2990 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2991 do_gpr_ld(s
, tcg_rt2
, clean_addr
, size
+ is_signed
* MO_SIGN
,
2992 false, false, 0, false, false);
2994 tcg_gen_mov_i64(tcg_rt
, tmp
);
2995 tcg_temp_free_i64(tmp
);
2997 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
2998 false, 0, false, false);
2999 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
3000 do_gpr_st(s
, tcg_rt2
, clean_addr
, size
,
3001 false, 0, false, false);
3007 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3009 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), dirty_addr
);
3014 * Load/store (immediate post-indexed)
3015 * Load/store (immediate pre-indexed)
3016 * Load/store (unscaled immediate)
3018 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
3019 * +----+-------+---+-----+-----+---+--------+-----+------+------+
3020 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
3021 * +----+-------+---+-----+-----+---+--------+-----+------+------+
3023 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
3025 * V = 0 -> non-vector
3026 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
3027 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
3029 static void disas_ldst_reg_imm9(DisasContext
*s
, uint32_t insn
,
3035 int rn
= extract32(insn
, 5, 5);
3036 int imm9
= sextract32(insn
, 12, 9);
3037 int idx
= extract32(insn
, 10, 2);
3038 bool is_signed
= false;
3039 bool is_store
= false;
3040 bool is_extended
= false;
3041 bool is_unpriv
= (idx
== 2);
3042 bool iss_valid
= !is_vector
;
3047 TCGv_i64 clean_addr
, dirty_addr
;
3050 size
|= (opc
& 2) << 1;
3051 if (size
> 4 || is_unpriv
) {
3052 unallocated_encoding(s
);
3055 is_store
= ((opc
& 1) == 0);
3056 if (!fp_access_check(s
)) {
3060 if (size
== 3 && opc
== 2) {
3061 /* PRFM - prefetch */
3063 unallocated_encoding(s
);
3068 if (opc
== 3 && size
> 1) {
3069 unallocated_encoding(s
);
3072 is_store
= (opc
== 0);
3073 is_signed
= extract32(opc
, 1, 1);
3074 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
3092 g_assert_not_reached();
3096 gen_check_sp_alignment(s
);
3099 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3101 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, imm9
);
3104 memidx
= is_unpriv
? get_a64_user_mem_index(s
) : get_mem_index(s
);
3105 clean_addr
= gen_mte_check1_mmuidx(s
, dirty_addr
, is_store
,
3106 writeback
|| rn
!= 31,
3107 size
, is_unpriv
, memidx
);
3111 do_fp_st(s
, rt
, clean_addr
, size
);
3113 do_fp_ld(s
, rt
, clean_addr
, size
);
3116 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3117 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3120 do_gpr_st_memidx(s
, tcg_rt
, clean_addr
, size
, memidx
,
3121 iss_valid
, rt
, iss_sf
, false);
3123 do_gpr_ld_memidx(s
, tcg_rt
, clean_addr
, size
+ is_signed
* MO_SIGN
,
3124 is_extended
, memidx
,
3125 iss_valid
, rt
, iss_sf
, false);
3130 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
3132 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, imm9
);
3134 tcg_gen_mov_i64(tcg_rn
, dirty_addr
);
3139 * Load/store (register offset)
3141 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3142 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
3143 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
3144 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
3147 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
3148 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
3150 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
3151 * opc<0>: 0 -> store, 1 -> load
3152 * V: 1 -> vector/simd
3153 * opt: extend encoding (see DecodeRegExtend)
3154 * S: if S=1 then scale (essentially index by sizeof(size))
3155 * Rt: register to transfer into/out of
3156 * Rn: address register or SP for base
3157 * Rm: offset register or ZR for offset
3159 static void disas_ldst_reg_roffset(DisasContext
*s
, uint32_t insn
,
3165 int rn
= extract32(insn
, 5, 5);
3166 int shift
= extract32(insn
, 12, 1);
3167 int rm
= extract32(insn
, 16, 5);
3168 int opt
= extract32(insn
, 13, 3);
3169 bool is_signed
= false;
3170 bool is_store
= false;
3171 bool is_extended
= false;
3173 TCGv_i64 tcg_rm
, clean_addr
, dirty_addr
;
3175 if (extract32(opt
, 1, 1) == 0) {
3176 unallocated_encoding(s
);
3181 size
|= (opc
& 2) << 1;
3183 unallocated_encoding(s
);
3186 is_store
= !extract32(opc
, 0, 1);
3187 if (!fp_access_check(s
)) {
3191 if (size
== 3 && opc
== 2) {
3192 /* PRFM - prefetch */
3195 if (opc
== 3 && size
> 1) {
3196 unallocated_encoding(s
);
3199 is_store
= (opc
== 0);
3200 is_signed
= extract32(opc
, 1, 1);
3201 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
3205 gen_check_sp_alignment(s
);
3207 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3209 tcg_rm
= read_cpu_reg(s
, rm
, 1);
3210 ext_and_shift_reg(tcg_rm
, tcg_rm
, opt
, shift
? size
: 0);
3212 tcg_gen_add_i64(dirty_addr
, dirty_addr
, tcg_rm
);
3213 clean_addr
= gen_mte_check1(s
, dirty_addr
, is_store
, true, size
);
3217 do_fp_st(s
, rt
, clean_addr
, size
);
3219 do_fp_ld(s
, rt
, clean_addr
, size
);
3222 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3223 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3225 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
3226 true, rt
, iss_sf
, false);
3228 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
+ is_signed
* MO_SIGN
,
3229 is_extended
, true, rt
, iss_sf
, false);
3235 * Load/store (unsigned immediate)
3237 * 31 30 29 27 26 25 24 23 22 21 10 9 5
3238 * +----+-------+---+-----+-----+------------+-------+------+
3239 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
3240 * +----+-------+---+-----+-----+------------+-------+------+
3243 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
3244 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
3246 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
3247 * opc<0>: 0 -> store, 1 -> load
3248 * Rn: base address register (inc SP)
3249 * Rt: target register
3251 static void disas_ldst_reg_unsigned_imm(DisasContext
*s
, uint32_t insn
,
3257 int rn
= extract32(insn
, 5, 5);
3258 unsigned int imm12
= extract32(insn
, 10, 12);
3259 unsigned int offset
;
3261 TCGv_i64 clean_addr
, dirty_addr
;
3264 bool is_signed
= false;
3265 bool is_extended
= false;
3268 size
|= (opc
& 2) << 1;
3270 unallocated_encoding(s
);
3273 is_store
= !extract32(opc
, 0, 1);
3274 if (!fp_access_check(s
)) {
3278 if (size
== 3 && opc
== 2) {
3279 /* PRFM - prefetch */
3282 if (opc
== 3 && size
> 1) {
3283 unallocated_encoding(s
);
3286 is_store
= (opc
== 0);
3287 is_signed
= extract32(opc
, 1, 1);
3288 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
3292 gen_check_sp_alignment(s
);
3294 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3295 offset
= imm12
<< size
;
3296 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3297 clean_addr
= gen_mte_check1(s
, dirty_addr
, is_store
, rn
!= 31, size
);
3301 do_fp_st(s
, rt
, clean_addr
, size
);
3303 do_fp_ld(s
, rt
, clean_addr
, size
);
3306 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3307 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3309 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
3310 true, rt
, iss_sf
, false);
3312 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
+ is_signed
* MO_SIGN
,
3313 is_extended
, true, rt
, iss_sf
, false);
3318 /* Atomic memory operations
3320 * 31 30 27 26 24 22 21 16 15 12 10 5 0
3321 * +------+-------+---+-----+-----+---+----+----+-----+-----+----+-----+
3322 * | size | 1 1 1 | V | 0 0 | A R | 1 | Rs | o3 | opc | 0 0 | Rn | Rt |
3323 * +------+-------+---+-----+-----+--------+----+-----+-----+----+-----+
3325 * Rt: the result register
3326 * Rn: base address or SP
3327 * Rs: the source register for the operation
3328 * V: vector flag (always 0 as of v8.3)
3332 static void disas_ldst_atomic(DisasContext
*s
, uint32_t insn
,
3333 int size
, int rt
, bool is_vector
)
3335 int rs
= extract32(insn
, 16, 5);
3336 int rn
= extract32(insn
, 5, 5);
3337 int o3_opc
= extract32(insn
, 12, 4);
3338 bool r
= extract32(insn
, 22, 1);
3339 bool a
= extract32(insn
, 23, 1);
3340 TCGv_i64 tcg_rs
, tcg_rt
, clean_addr
;
3341 AtomicThreeOpFn
*fn
= NULL
;
3342 MemOp mop
= s
->be_data
| size
| MO_ALIGN
;
3344 if (is_vector
|| !dc_isar_feature(aa64_atomics
, s
)) {
3345 unallocated_encoding(s
);
3349 case 000: /* LDADD */
3350 fn
= tcg_gen_atomic_fetch_add_i64
;
3352 case 001: /* LDCLR */
3353 fn
= tcg_gen_atomic_fetch_and_i64
;
3355 case 002: /* LDEOR */
3356 fn
= tcg_gen_atomic_fetch_xor_i64
;
3358 case 003: /* LDSET */
3359 fn
= tcg_gen_atomic_fetch_or_i64
;
3361 case 004: /* LDSMAX */
3362 fn
= tcg_gen_atomic_fetch_smax_i64
;
3365 case 005: /* LDSMIN */
3366 fn
= tcg_gen_atomic_fetch_smin_i64
;
3369 case 006: /* LDUMAX */
3370 fn
= tcg_gen_atomic_fetch_umax_i64
;
3372 case 007: /* LDUMIN */
3373 fn
= tcg_gen_atomic_fetch_umin_i64
;
3376 fn
= tcg_gen_atomic_xchg_i64
;
3378 case 014: /* LDAPR, LDAPRH, LDAPRB */
3379 if (!dc_isar_feature(aa64_rcpc_8_3
, s
) ||
3380 rs
!= 31 || a
!= 1 || r
!= 0) {
3381 unallocated_encoding(s
);
3386 unallocated_encoding(s
);
3391 gen_check_sp_alignment(s
);
3393 clean_addr
= gen_mte_check1(s
, cpu_reg_sp(s
, rn
), false, rn
!= 31, size
);
3395 if (o3_opc
== 014) {
3397 * LDAPR* are a special case because they are a simple load, not a
3398 * fetch-and-do-something op.
3399 * The architectural consistency requirements here are weaker than
3400 * full load-acquire (we only need "load-acquire processor consistent"),
3401 * but we choose to implement them as full LDAQ.
3403 do_gpr_ld(s
, cpu_reg(s
, rt
), clean_addr
, size
, false,
3404 true, rt
, disas_ldst_compute_iss_sf(size
, false, 0), true);
3405 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
3409 tcg_rs
= read_cpu_reg(s
, rs
, true);
3410 tcg_rt
= cpu_reg(s
, rt
);
3412 if (o3_opc
== 1) { /* LDCLR */
3413 tcg_gen_not_i64(tcg_rs
, tcg_rs
);
3416 /* The tcg atomic primitives are all full barriers. Therefore we
3417 * can ignore the Acquire and Release bits of this instruction.
3419 fn(tcg_rt
, clean_addr
, tcg_rs
, get_mem_index(s
), mop
);
3421 if ((mop
& MO_SIGN
) && size
!= MO_64
) {
3422 tcg_gen_ext32u_i64(tcg_rt
, tcg_rt
);
3427 * PAC memory operations
3429 * 31 30 27 26 24 22 21 12 11 10 5 0
3430 * +------+-------+---+-----+-----+---+--------+---+---+----+-----+
3431 * | size | 1 1 1 | V | 0 0 | M S | 1 | imm9 | W | 1 | Rn | Rt |
3432 * +------+-------+---+-----+-----+---+--------+---+---+----+-----+
3434 * Rt: the result register
3435 * Rn: base address or SP
3436 * V: vector flag (always 0 as of v8.3)
3437 * M: clear for key DA, set for key DB
3438 * W: pre-indexing flag
3441 static void disas_ldst_pac(DisasContext
*s
, uint32_t insn
,
3442 int size
, int rt
, bool is_vector
)
3444 int rn
= extract32(insn
, 5, 5);
3445 bool is_wback
= extract32(insn
, 11, 1);
3446 bool use_key_a
= !extract32(insn
, 23, 1);
3448 TCGv_i64 clean_addr
, dirty_addr
, tcg_rt
;
3450 if (size
!= 3 || is_vector
|| !dc_isar_feature(aa64_pauth
, s
)) {
3451 unallocated_encoding(s
);
3456 gen_check_sp_alignment(s
);
3458 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3460 if (s
->pauth_active
) {
3462 gen_helper_autda(dirty_addr
, cpu_env
, dirty_addr
,
3463 new_tmp_a64_zero(s
));
3465 gen_helper_autdb(dirty_addr
, cpu_env
, dirty_addr
,
3466 new_tmp_a64_zero(s
));
3470 /* Form the 10-bit signed, scaled offset. */
3471 offset
= (extract32(insn
, 22, 1) << 9) | extract32(insn
, 12, 9);
3472 offset
= sextract32(offset
<< size
, 0, 10 + size
);
3473 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3475 /* Note that "clean" and "dirty" here refer to TBI not PAC. */
3476 clean_addr
= gen_mte_check1(s
, dirty_addr
, false,
3477 is_wback
|| rn
!= 31, size
);
3479 tcg_rt
= cpu_reg(s
, rt
);
3480 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
,
3481 /* extend */ false, /* iss_valid */ !is_wback
,
3482 /* iss_srt */ rt
, /* iss_sf */ true, /* iss_ar */ false);
3485 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), dirty_addr
);
3490 * LDAPR/STLR (unscaled immediate)
3492 * 31 30 24 22 21 12 10 5 0
3493 * +------+-------------+-----+---+--------+-----+----+-----+
3494 * | size | 0 1 1 0 0 1 | opc | 0 | imm9 | 0 0 | Rn | Rt |
3495 * +------+-------------+-----+---+--------+-----+----+-----+
3497 * Rt: source or destination register
3499 * imm9: unscaled immediate offset
3500 * opc: 00: STLUR*, 01/10/11: various LDAPUR*
3501 * size: size of load/store
3503 static void disas_ldst_ldapr_stlr(DisasContext
*s
, uint32_t insn
)
3505 int rt
= extract32(insn
, 0, 5);
3506 int rn
= extract32(insn
, 5, 5);
3507 int offset
= sextract32(insn
, 12, 9);
3508 int opc
= extract32(insn
, 22, 2);
3509 int size
= extract32(insn
, 30, 2);
3510 TCGv_i64 clean_addr
, dirty_addr
;
3511 bool is_store
= false;
3512 bool extend
= false;
3516 if (!dc_isar_feature(aa64_rcpc_8_4
, s
)) {
3517 unallocated_encoding(s
);
3521 /* TODO: ARMv8.4-LSE SCTLR.nAA */
3522 mop
= size
| MO_ALIGN
;
3525 case 0: /* STLURB */
3528 case 1: /* LDAPUR* */
3530 case 2: /* LDAPURS* 64-bit variant */
3532 unallocated_encoding(s
);
3537 case 3: /* LDAPURS* 32-bit variant */
3539 unallocated_encoding(s
);
3543 extend
= true; /* zero-extend 32->64 after signed load */
3546 g_assert_not_reached();
3549 iss_sf
= disas_ldst_compute_iss_sf(size
, (mop
& MO_SIGN
) != 0, opc
);
3552 gen_check_sp_alignment(s
);
3555 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3556 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3557 clean_addr
= clean_data_tbi(s
, dirty_addr
);
3560 /* Store-Release semantics */
3561 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
3562 do_gpr_st(s
, cpu_reg(s
, rt
), clean_addr
, mop
, true, rt
, iss_sf
, true);
3565 * Load-AcquirePC semantics; we implement as the slightly more
3566 * restrictive Load-Acquire.
3568 do_gpr_ld(s
, cpu_reg(s
, rt
), clean_addr
, mop
,
3569 extend
, true, rt
, iss_sf
, true);
3570 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
3574 /* Load/store register (all forms) */
3575 static void disas_ldst_reg(DisasContext
*s
, uint32_t insn
)
3577 int rt
= extract32(insn
, 0, 5);
3578 int opc
= extract32(insn
, 22, 2);
3579 bool is_vector
= extract32(insn
, 26, 1);
3580 int size
= extract32(insn
, 30, 2);
3582 switch (extract32(insn
, 24, 2)) {
3584 if (extract32(insn
, 21, 1) == 0) {
3585 /* Load/store register (unscaled immediate)
3586 * Load/store immediate pre/post-indexed
3587 * Load/store register unprivileged
3589 disas_ldst_reg_imm9(s
, insn
, opc
, size
, rt
, is_vector
);
3592 switch (extract32(insn
, 10, 2)) {
3594 disas_ldst_atomic(s
, insn
, size
, rt
, is_vector
);
3597 disas_ldst_reg_roffset(s
, insn
, opc
, size
, rt
, is_vector
);
3600 disas_ldst_pac(s
, insn
, size
, rt
, is_vector
);
3605 disas_ldst_reg_unsigned_imm(s
, insn
, opc
, size
, rt
, is_vector
);
3608 unallocated_encoding(s
);
3611 /* AdvSIMD load/store multiple structures
3613 * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
3614 * +---+---+---------------+---+-------------+--------+------+------+------+
3615 * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
3616 * +---+---+---------------+---+-------------+--------+------+------+------+
3618 * AdvSIMD load/store multiple structures (post-indexed)
3620 * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
3621 * +---+---+---------------+---+---+---------+--------+------+------+------+
3622 * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
3623 * +---+---+---------------+---+---+---------+--------+------+------+------+
3625 * Rt: first (or only) SIMD&FP register to be transferred
3626 * Rn: base address or SP
3627 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3629 static void disas_ldst_multiple_struct(DisasContext
*s
, uint32_t insn
)
3631 int rt
= extract32(insn
, 0, 5);
3632 int rn
= extract32(insn
, 5, 5);
3633 int rm
= extract32(insn
, 16, 5);
3634 int size
= extract32(insn
, 10, 2);
3635 int opcode
= extract32(insn
, 12, 4);
3636 bool is_store
= !extract32(insn
, 22, 1);
3637 bool is_postidx
= extract32(insn
, 23, 1);
3638 bool is_q
= extract32(insn
, 30, 1);
3639 TCGv_i64 clean_addr
, tcg_rn
, tcg_ebytes
;
3640 MemOp endian
, align
, mop
;
3642 int total
; /* total bytes */
3643 int elements
; /* elements per vector */
3644 int rpt
; /* num iterations */
3645 int selem
; /* structure elements */
3648 if (extract32(insn
, 31, 1) || extract32(insn
, 21, 1)) {
3649 unallocated_encoding(s
);
3653 if (!is_postidx
&& rm
!= 0) {
3654 unallocated_encoding(s
);
3658 /* From the shared decode logic */
3689 unallocated_encoding(s
);
3693 if (size
== 3 && !is_q
&& selem
!= 1) {
3695 unallocated_encoding(s
);
3699 if (!fp_access_check(s
)) {
3704 gen_check_sp_alignment(s
);
3707 /* For our purposes, bytes are always little-endian. */
3708 endian
= s
->be_data
;
3713 total
= rpt
* selem
* (is_q
? 16 : 8);
3714 tcg_rn
= cpu_reg_sp(s
, rn
);
3717 * Issue the MTE check vs the logical repeat count, before we
3718 * promote consecutive little-endian elements below.
3720 clean_addr
= gen_mte_checkN(s
, tcg_rn
, is_store
, is_postidx
|| rn
!= 31,
3724 * Consecutive little-endian elements from a single register
3725 * can be promoted to a larger little-endian operation.
3728 if (selem
== 1 && endian
== MO_LE
) {
3729 align
= pow2_align(size
);
3732 if (!s
->align_mem
) {
3735 mop
= endian
| size
| align
;
3737 elements
= (is_q
? 16 : 8) >> size
;
3738 tcg_ebytes
= tcg_const_i64(1 << size
);
3739 for (r
= 0; r
< rpt
; r
++) {
3741 for (e
= 0; e
< elements
; e
++) {
3743 for (xs
= 0; xs
< selem
; xs
++) {
3744 int tt
= (rt
+ r
+ xs
) % 32;
3746 do_vec_st(s
, tt
, e
, clean_addr
, mop
);
3748 do_vec_ld(s
, tt
, e
, clean_addr
, mop
);
3750 tcg_gen_add_i64(clean_addr
, clean_addr
, tcg_ebytes
);
3754 tcg_temp_free_i64(tcg_ebytes
);
3757 /* For non-quad operations, setting a slice of the low
3758 * 64 bits of the register clears the high 64 bits (in
3759 * the ARM ARM pseudocode this is implicit in the fact
3760 * that 'rval' is a 64 bit wide variable).
3761 * For quad operations, we might still need to zero the
3764 for (r
= 0; r
< rpt
* selem
; r
++) {
3765 int tt
= (rt
+ r
) % 32;
3766 clear_vec_high(s
, is_q
, tt
);
3772 tcg_gen_addi_i64(tcg_rn
, tcg_rn
, total
);
3774 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3779 /* AdvSIMD load/store single structure
3781 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3782 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3783 * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
3784 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3786 * AdvSIMD load/store single structure (post-indexed)
3788 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3789 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3790 * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
3791 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3793 * Rt: first (or only) SIMD&FP register to be transferred
3794 * Rn: base address or SP
3795 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3796 * index = encoded in Q:S:size dependent on size
3798 * lane_size = encoded in R, opc
3799 * transfer width = encoded in opc, S, size
3801 static void disas_ldst_single_struct(DisasContext
*s
, uint32_t insn
)
3803 int rt
= extract32(insn
, 0, 5);
3804 int rn
= extract32(insn
, 5, 5);
3805 int rm
= extract32(insn
, 16, 5);
3806 int size
= extract32(insn
, 10, 2);
3807 int S
= extract32(insn
, 12, 1);
3808 int opc
= extract32(insn
, 13, 3);
3809 int R
= extract32(insn
, 21, 1);
3810 int is_load
= extract32(insn
, 22, 1);
3811 int is_postidx
= extract32(insn
, 23, 1);
3812 int is_q
= extract32(insn
, 30, 1);
3814 int scale
= extract32(opc
, 1, 2);
3815 int selem
= (extract32(opc
, 0, 1) << 1 | R
) + 1;
3816 bool replicate
= false;
3817 int index
= is_q
<< 3 | S
<< 2 | size
;
3819 TCGv_i64 clean_addr
, tcg_rn
, tcg_ebytes
;
3822 if (extract32(insn
, 31, 1)) {
3823 unallocated_encoding(s
);
3826 if (!is_postidx
&& rm
!= 0) {
3827 unallocated_encoding(s
);
3833 if (!is_load
|| S
) {
3834 unallocated_encoding(s
);
3843 if (extract32(size
, 0, 1)) {
3844 unallocated_encoding(s
);
3850 if (extract32(size
, 1, 1)) {
3851 unallocated_encoding(s
);
3854 if (!extract32(size
, 0, 1)) {
3858 unallocated_encoding(s
);
3866 g_assert_not_reached();
3869 if (!fp_access_check(s
)) {
3874 gen_check_sp_alignment(s
);
3877 total
= selem
<< scale
;
3878 tcg_rn
= cpu_reg_sp(s
, rn
);
3880 clean_addr
= gen_mte_checkN(s
, tcg_rn
, !is_load
, is_postidx
|| rn
!= 31,
3882 mop
= finalize_memop(s
, scale
);
3884 tcg_ebytes
= tcg_const_i64(1 << scale
);
3885 for (xs
= 0; xs
< selem
; xs
++) {
3887 /* Load and replicate to all elements */
3888 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
3890 tcg_gen_qemu_ld_i64(tcg_tmp
, clean_addr
, get_mem_index(s
), mop
);
3891 tcg_gen_gvec_dup_i64(scale
, vec_full_reg_offset(s
, rt
),
3892 (is_q
+ 1) * 8, vec_full_reg_size(s
),
3894 tcg_temp_free_i64(tcg_tmp
);
3896 /* Load/store one element per register */
3898 do_vec_ld(s
, rt
, index
, clean_addr
, mop
);
3900 do_vec_st(s
, rt
, index
, clean_addr
, mop
);
3903 tcg_gen_add_i64(clean_addr
, clean_addr
, tcg_ebytes
);
3906 tcg_temp_free_i64(tcg_ebytes
);
3910 tcg_gen_addi_i64(tcg_rn
, tcg_rn
, total
);
3912 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3918 * Load/Store memory tags
3920 * 31 30 29 24 22 21 12 10 5 0
3921 * +-----+-------------+-----+---+------+-----+------+------+
3922 * | 1 1 | 0 1 1 0 0 1 | op1 | 1 | imm9 | op2 | Rn | Rt |
3923 * +-----+-------------+-----+---+------+-----+------+------+
3925 static void disas_ldst_tag(DisasContext
*s
, uint32_t insn
)
3927 int rt
= extract32(insn
, 0, 5);
3928 int rn
= extract32(insn
, 5, 5);
3929 uint64_t offset
= sextract64(insn
, 12, 9) << LOG2_TAG_GRANULE
;
3930 int op2
= extract32(insn
, 10, 2);
3931 int op1
= extract32(insn
, 22, 2);
3932 bool is_load
= false, is_pair
= false, is_zero
= false, is_mult
= false;
3934 TCGv_i64 addr
, clean_addr
, tcg_rt
;
3936 /* We checked insn bits [29:24,21] in the caller. */
3937 if (extract32(insn
, 30, 2) != 3) {
3938 goto do_unallocated
;
3942 * @index is a tri-state variable which has 3 states:
3943 * < 0 : post-index, writeback
3944 * = 0 : signed offset
3945 * > 0 : pre-index, writeback
3954 if (s
->current_el
== 0 || offset
!= 0) {
3955 goto do_unallocated
;
3957 is_mult
= is_zero
= true;
3977 if (s
->current_el
== 0 || offset
!= 0) {
3978 goto do_unallocated
;
3986 is_pair
= is_zero
= true;
3990 if (s
->current_el
== 0 || offset
!= 0) {
3991 goto do_unallocated
;
3993 is_mult
= is_load
= true;
3999 unallocated_encoding(s
);
4004 ? !dc_isar_feature(aa64_mte
, s
)
4005 : !dc_isar_feature(aa64_mte_insn_reg
, s
)) {
4006 goto do_unallocated
;
4010 gen_check_sp_alignment(s
);
4013 addr
= read_cpu_reg_sp(s
, rn
, true);
4015 /* pre-index or signed offset */
4016 tcg_gen_addi_i64(addr
, addr
, offset
);
4020 tcg_rt
= cpu_reg(s
, rt
);
4023 int size
= 4 << s
->dcz_blocksize
;
4026 gen_helper_stzgm_tags(cpu_env
, addr
, tcg_rt
);
4029 * The non-tags portion of STZGM is mostly like DC_ZVA,
4030 * except the alignment happens before the access.
4032 clean_addr
= clean_data_tbi(s
, addr
);
4033 tcg_gen_andi_i64(clean_addr
, clean_addr
, -size
);
4034 gen_helper_dc_zva(cpu_env
, clean_addr
);
4035 } else if (s
->ata
) {
4037 gen_helper_ldgm(tcg_rt
, cpu_env
, addr
);
4039 gen_helper_stgm(cpu_env
, addr
, tcg_rt
);
4042 MMUAccessType acc
= is_load
? MMU_DATA_LOAD
: MMU_DATA_STORE
;
4043 int size
= 4 << GMID_EL1_BS
;
4045 clean_addr
= clean_data_tbi(s
, addr
);
4046 tcg_gen_andi_i64(clean_addr
, clean_addr
, -size
);
4047 gen_probe_access(s
, clean_addr
, acc
, size
);
4050 /* The result tags are zeros. */
4051 tcg_gen_movi_i64(tcg_rt
, 0);
4058 tcg_gen_andi_i64(addr
, addr
, -TAG_GRANULE
);
4059 tcg_rt
= cpu_reg(s
, rt
);
4061 gen_helper_ldg(tcg_rt
, cpu_env
, addr
, tcg_rt
);
4063 clean_addr
= clean_data_tbi(s
, addr
);
4064 gen_probe_access(s
, clean_addr
, MMU_DATA_LOAD
, MO_8
);
4065 gen_address_with_allocation_tag0(tcg_rt
, addr
);
4068 tcg_rt
= cpu_reg_sp(s
, rt
);
4071 * For STG and ST2G, we need to check alignment and probe memory.
4072 * TODO: For STZG and STZ2G, we could rely on the stores below,
4073 * at least for system mode; user-only won't enforce alignment.
4076 gen_helper_st2g_stub(cpu_env
, addr
);
4078 gen_helper_stg_stub(cpu_env
, addr
);
4080 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
4082 gen_helper_st2g_parallel(cpu_env
, addr
, tcg_rt
);
4084 gen_helper_stg_parallel(cpu_env
, addr
, tcg_rt
);
4088 gen_helper_st2g(cpu_env
, addr
, tcg_rt
);
4090 gen_helper_stg(cpu_env
, addr
, tcg_rt
);
4096 TCGv_i64 clean_addr
= clean_data_tbi(s
, addr
);
4097 TCGv_i64 tcg_zero
= tcg_const_i64(0);
4098 int mem_index
= get_mem_index(s
);
4099 int i
, n
= (1 + is_pair
) << LOG2_TAG_GRANULE
;
4101 tcg_gen_qemu_st_i64(tcg_zero
, clean_addr
, mem_index
,
4102 MO_UQ
| MO_ALIGN_16
);
4103 for (i
= 8; i
< n
; i
+= 8) {
4104 tcg_gen_addi_i64(clean_addr
, clean_addr
, 8);
4105 tcg_gen_qemu_st_i64(tcg_zero
, clean_addr
, mem_index
, MO_UQ
);
4107 tcg_temp_free_i64(tcg_zero
);
4111 /* pre-index or post-index */
4114 tcg_gen_addi_i64(addr
, addr
, offset
);
4116 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), addr
);
4120 /* Loads and stores */
4121 static void disas_ldst(DisasContext
*s
, uint32_t insn
)
4123 switch (extract32(insn
, 24, 6)) {
4124 case 0x08: /* Load/store exclusive */
4125 disas_ldst_excl(s
, insn
);
4127 case 0x18: case 0x1c: /* Load register (literal) */
4128 disas_ld_lit(s
, insn
);
4130 case 0x28: case 0x29:
4131 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
4132 disas_ldst_pair(s
, insn
);
4134 case 0x38: case 0x39:
4135 case 0x3c: case 0x3d: /* Load/store register (all forms) */
4136 disas_ldst_reg(s
, insn
);
4138 case 0x0c: /* AdvSIMD load/store multiple structures */
4139 disas_ldst_multiple_struct(s
, insn
);
4141 case 0x0d: /* AdvSIMD load/store single structure */
4142 disas_ldst_single_struct(s
, insn
);
4145 if (extract32(insn
, 21, 1) != 0) {
4146 disas_ldst_tag(s
, insn
);
4147 } else if (extract32(insn
, 10, 2) == 0) {
4148 disas_ldst_ldapr_stlr(s
, insn
);
4150 unallocated_encoding(s
);
4154 unallocated_encoding(s
);
4159 /* PC-rel. addressing
4160 * 31 30 29 28 24 23 5 4 0
4161 * +----+-------+-----------+-------------------+------+
4162 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
4163 * +----+-------+-----------+-------------------+------+
4165 static void disas_pc_rel_adr(DisasContext
*s
, uint32_t insn
)
4167 unsigned int page
, rd
;
4171 page
= extract32(insn
, 31, 1);
4172 /* SignExtend(immhi:immlo) -> offset */
4173 offset
= sextract64(insn
, 5, 19);
4174 offset
= offset
<< 2 | extract32(insn
, 29, 2);
4175 rd
= extract32(insn
, 0, 5);
4179 /* ADRP (page based) */
4184 tcg_gen_movi_i64(cpu_reg(s
, rd
), base
+ offset
);
4188 * Add/subtract (immediate)
4190 * 31 30 29 28 23 22 21 10 9 5 4 0
4191 * +--+--+--+-------------+--+-------------+-----+-----+
4192 * |sf|op| S| 1 0 0 0 1 0 |sh| imm12 | Rn | Rd |
4193 * +--+--+--+-------------+--+-------------+-----+-----+
4195 * sf: 0 -> 32bit, 1 -> 64bit
4196 * op: 0 -> add , 1 -> sub
4198 * sh: 1 -> LSL imm by 12
4200 static void disas_add_sub_imm(DisasContext
*s
, uint32_t insn
)
4202 int rd
= extract32(insn
, 0, 5);
4203 int rn
= extract32(insn
, 5, 5);
4204 uint64_t imm
= extract32(insn
, 10, 12);
4205 bool shift
= extract32(insn
, 22, 1);
4206 bool setflags
= extract32(insn
, 29, 1);
4207 bool sub_op
= extract32(insn
, 30, 1);
4208 bool is_64bit
= extract32(insn
, 31, 1);
4210 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
4211 TCGv_i64 tcg_rd
= setflags
? cpu_reg(s
, rd
) : cpu_reg_sp(s
, rd
);
4212 TCGv_i64 tcg_result
;
4218 tcg_result
= tcg_temp_new_i64();
4221 tcg_gen_subi_i64(tcg_result
, tcg_rn
, imm
);
4223 tcg_gen_addi_i64(tcg_result
, tcg_rn
, imm
);
4226 TCGv_i64 tcg_imm
= tcg_const_i64(imm
);
4228 gen_sub_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
4230 gen_add_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
4232 tcg_temp_free_i64(tcg_imm
);
4236 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4238 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4241 tcg_temp_free_i64(tcg_result
);
4245 * Add/subtract (immediate, with tags)
4247 * 31 30 29 28 23 22 21 16 14 10 9 5 4 0
4248 * +--+--+--+-------------+--+---------+--+-------+-----+-----+
4249 * |sf|op| S| 1 0 0 0 1 1 |o2| uimm6 |o3| uimm4 | Rn | Rd |
4250 * +--+--+--+-------------+--+---------+--+-------+-----+-----+
4252 * op: 0 -> add, 1 -> sub
4254 static void disas_add_sub_imm_with_tags(DisasContext
*s
, uint32_t insn
)
4256 int rd
= extract32(insn
, 0, 5);
4257 int rn
= extract32(insn
, 5, 5);
4258 int uimm4
= extract32(insn
, 10, 4);
4259 int uimm6
= extract32(insn
, 16, 6);
4260 bool sub_op
= extract32(insn
, 30, 1);
4261 TCGv_i64 tcg_rn
, tcg_rd
;
4264 /* Test all of sf=1, S=0, o2=0, o3=0. */
4265 if ((insn
& 0xa040c000u
) != 0x80000000u
||
4266 !dc_isar_feature(aa64_mte_insn_reg
, s
)) {
4267 unallocated_encoding(s
);
4271 imm
= uimm6
<< LOG2_TAG_GRANULE
;
4276 tcg_rn
= cpu_reg_sp(s
, rn
);
4277 tcg_rd
= cpu_reg_sp(s
, rd
);
4280 TCGv_i32 offset
= tcg_const_i32(imm
);
4281 TCGv_i32 tag_offset
= tcg_const_i32(uimm4
);
4283 gen_helper_addsubg(tcg_rd
, cpu_env
, tcg_rn
, offset
, tag_offset
);
4284 tcg_temp_free_i32(tag_offset
);
4285 tcg_temp_free_i32(offset
);
4287 tcg_gen_addi_i64(tcg_rd
, tcg_rn
, imm
);
4288 gen_address_with_allocation_tag0(tcg_rd
, tcg_rd
);
4292 /* The input should be a value in the bottom e bits (with higher
4293 * bits zero); returns that value replicated into every element
4294 * of size e in a 64 bit integer.
4296 static uint64_t bitfield_replicate(uint64_t mask
, unsigned int e
)
4306 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
4307 static inline uint64_t bitmask64(unsigned int length
)
4309 assert(length
> 0 && length
<= 64);
4310 return ~0ULL >> (64 - length
);
4313 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
4314 * only require the wmask. Returns false if the imms/immr/immn are a reserved
4315 * value (ie should cause a guest UNDEF exception), and true if they are
4316 * valid, in which case the decoded bit pattern is written to result.
4318 bool logic_imm_decode_wmask(uint64_t *result
, unsigned int immn
,
4319 unsigned int imms
, unsigned int immr
)
4322 unsigned e
, levels
, s
, r
;
4325 assert(immn
< 2 && imms
< 64 && immr
< 64);
4327 /* The bit patterns we create here are 64 bit patterns which
4328 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
4329 * 64 bits each. Each element contains the same value: a run
4330 * of between 1 and e-1 non-zero bits, rotated within the
4331 * element by between 0 and e-1 bits.
4333 * The element size and run length are encoded into immn (1 bit)
4334 * and imms (6 bits) as follows:
4335 * 64 bit elements: immn = 1, imms = <length of run - 1>
4336 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
4337 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
4338 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
4339 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
4340 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
4341 * Notice that immn = 0, imms = 11111x is the only combination
4342 * not covered by one of the above options; this is reserved.
4343 * Further, <length of run - 1> all-ones is a reserved pattern.
4345 * In all cases the rotation is by immr % e (and immr is 6 bits).
4348 /* First determine the element size */
4349 len
= 31 - clz32((immn
<< 6) | (~imms
& 0x3f));
4351 /* This is the immn == 0, imms == 0x11111x case */
4361 /* <length of run - 1> mustn't be all-ones. */
4365 /* Create the value of one element: s+1 set bits rotated
4366 * by r within the element (which is e bits wide)...
4368 mask
= bitmask64(s
+ 1);
4370 mask
= (mask
>> r
) | (mask
<< (e
- r
));
4371 mask
&= bitmask64(e
);
4373 /* ...then replicate the element over the whole 64 bit value */
4374 mask
= bitfield_replicate(mask
, e
);
4379 /* Logical (immediate)
4380 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
4381 * +----+-----+-------------+---+------+------+------+------+
4382 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
4383 * +----+-----+-------------+---+------+------+------+------+
4385 static void disas_logic_imm(DisasContext
*s
, uint32_t insn
)
4387 unsigned int sf
, opc
, is_n
, immr
, imms
, rn
, rd
;
4388 TCGv_i64 tcg_rd
, tcg_rn
;
4390 bool is_and
= false;
4392 sf
= extract32(insn
, 31, 1);
4393 opc
= extract32(insn
, 29, 2);
4394 is_n
= extract32(insn
, 22, 1);
4395 immr
= extract32(insn
, 16, 6);
4396 imms
= extract32(insn
, 10, 6);
4397 rn
= extract32(insn
, 5, 5);
4398 rd
= extract32(insn
, 0, 5);
4401 unallocated_encoding(s
);
4405 if (opc
== 0x3) { /* ANDS */
4406 tcg_rd
= cpu_reg(s
, rd
);
4408 tcg_rd
= cpu_reg_sp(s
, rd
);
4410 tcg_rn
= cpu_reg(s
, rn
);
4412 if (!logic_imm_decode_wmask(&wmask
, is_n
, imms
, immr
)) {
4413 /* some immediate field values are reserved */
4414 unallocated_encoding(s
);
4419 wmask
&= 0xffffffff;
4423 case 0x3: /* ANDS */
4425 tcg_gen_andi_i64(tcg_rd
, tcg_rn
, wmask
);
4429 tcg_gen_ori_i64(tcg_rd
, tcg_rn
, wmask
);
4432 tcg_gen_xori_i64(tcg_rd
, tcg_rn
, wmask
);
4435 assert(FALSE
); /* must handle all above */
4439 if (!sf
&& !is_and
) {
4440 /* zero extend final result; we know we can skip this for AND
4441 * since the immediate had the high 32 bits clear.
4443 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4446 if (opc
== 3) { /* ANDS */
4447 gen_logic_CC(sf
, tcg_rd
);
4452 * Move wide (immediate)
4454 * 31 30 29 28 23 22 21 20 5 4 0
4455 * +--+-----+-------------+-----+----------------+------+
4456 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
4457 * +--+-----+-------------+-----+----------------+------+
4459 * sf: 0 -> 32 bit, 1 -> 64 bit
4460 * opc: 00 -> N, 10 -> Z, 11 -> K
4461 * hw: shift/16 (0,16, and sf only 32, 48)
4463 static void disas_movw_imm(DisasContext
*s
, uint32_t insn
)
4465 int rd
= extract32(insn
, 0, 5);
4466 uint64_t imm
= extract32(insn
, 5, 16);
4467 int sf
= extract32(insn
, 31, 1);
4468 int opc
= extract32(insn
, 29, 2);
4469 int pos
= extract32(insn
, 21, 2) << 4;
4470 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4473 if (!sf
&& (pos
>= 32)) {
4474 unallocated_encoding(s
);
4488 tcg_gen_movi_i64(tcg_rd
, imm
);
4491 tcg_imm
= tcg_const_i64(imm
);
4492 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_imm
, pos
, 16);
4493 tcg_temp_free_i64(tcg_imm
);
4495 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4499 unallocated_encoding(s
);
4505 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
4506 * +----+-----+-------------+---+------+------+------+------+
4507 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
4508 * +----+-----+-------------+---+------+------+------+------+
4510 static void disas_bitfield(DisasContext
*s
, uint32_t insn
)
4512 unsigned int sf
, n
, opc
, ri
, si
, rn
, rd
, bitsize
, pos
, len
;
4513 TCGv_i64 tcg_rd
, tcg_tmp
;
4515 sf
= extract32(insn
, 31, 1);
4516 opc
= extract32(insn
, 29, 2);
4517 n
= extract32(insn
, 22, 1);
4518 ri
= extract32(insn
, 16, 6);
4519 si
= extract32(insn
, 10, 6);
4520 rn
= extract32(insn
, 5, 5);
4521 rd
= extract32(insn
, 0, 5);
4522 bitsize
= sf
? 64 : 32;
4524 if (sf
!= n
|| ri
>= bitsize
|| si
>= bitsize
|| opc
> 2) {
4525 unallocated_encoding(s
);
4529 tcg_rd
= cpu_reg(s
, rd
);
4531 /* Suppress the zero-extend for !sf. Since RI and SI are constrained
4532 to be smaller than bitsize, we'll never reference data outside the
4533 low 32-bits anyway. */
4534 tcg_tmp
= read_cpu_reg(s
, rn
, 1);
4536 /* Recognize simple(r) extractions. */
4538 /* Wd<s-r:0> = Wn<s:r> */
4539 len
= (si
- ri
) + 1;
4540 if (opc
== 0) { /* SBFM: ASR, SBFX, SXTB, SXTH, SXTW */
4541 tcg_gen_sextract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
4543 } else if (opc
== 2) { /* UBFM: UBFX, LSR, UXTB, UXTH */
4544 tcg_gen_extract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
4547 /* opc == 1, BFXIL fall through to deposit */
4548 tcg_gen_shri_i64(tcg_tmp
, tcg_tmp
, ri
);
4551 /* Handle the ri > si case with a deposit
4552 * Wd<32+s-r,32-r> = Wn<s:0>
4555 pos
= (bitsize
- ri
) & (bitsize
- 1);
4558 if (opc
== 0 && len
< ri
) {
4559 /* SBFM: sign extend the destination field from len to fill
4560 the balance of the word. Let the deposit below insert all
4561 of those sign bits. */
4562 tcg_gen_sextract_i64(tcg_tmp
, tcg_tmp
, 0, len
);
4566 if (opc
== 1) { /* BFM, BFXIL */
4567 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, pos
, len
);
4569 /* SBFM or UBFM: We start with zero, and we haven't modified
4570 any bits outside bitsize, therefore the zero-extension
4571 below is unneeded. */
4572 tcg_gen_deposit_z_i64(tcg_rd
, tcg_tmp
, pos
, len
);
4577 if (!sf
) { /* zero extend final result */
4578 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4583 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
4584 * +----+------+-------------+---+----+------+--------+------+------+
4585 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
4586 * +----+------+-------------+---+----+------+--------+------+------+
4588 static void disas_extract(DisasContext
*s
, uint32_t insn
)
4590 unsigned int sf
, n
, rm
, imm
, rn
, rd
, bitsize
, op21
, op0
;
4592 sf
= extract32(insn
, 31, 1);
4593 n
= extract32(insn
, 22, 1);
4594 rm
= extract32(insn
, 16, 5);
4595 imm
= extract32(insn
, 10, 6);
4596 rn
= extract32(insn
, 5, 5);
4597 rd
= extract32(insn
, 0, 5);
4598 op21
= extract32(insn
, 29, 2);
4599 op0
= extract32(insn
, 21, 1);
4600 bitsize
= sf
? 64 : 32;
4602 if (sf
!= n
|| op21
|| op0
|| imm
>= bitsize
) {
4603 unallocated_encoding(s
);
4605 TCGv_i64 tcg_rd
, tcg_rm
, tcg_rn
;
4607 tcg_rd
= cpu_reg(s
, rd
);
4609 if (unlikely(imm
== 0)) {
4610 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
4611 * so an extract from bit 0 is a special case.
4614 tcg_gen_mov_i64(tcg_rd
, cpu_reg(s
, rm
));
4616 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rm
));
4619 tcg_rm
= cpu_reg(s
, rm
);
4620 tcg_rn
= cpu_reg(s
, rn
);
4623 /* Specialization to ROR happens in EXTRACT2. */
4624 tcg_gen_extract2_i64(tcg_rd
, tcg_rm
, tcg_rn
, imm
);
4626 TCGv_i32 t0
= tcg_temp_new_i32();
4628 tcg_gen_extrl_i64_i32(t0
, tcg_rm
);
4630 tcg_gen_rotri_i32(t0
, t0
, imm
);
4632 TCGv_i32 t1
= tcg_temp_new_i32();
4633 tcg_gen_extrl_i64_i32(t1
, tcg_rn
);
4634 tcg_gen_extract2_i32(t0
, t0
, t1
, imm
);
4635 tcg_temp_free_i32(t1
);
4637 tcg_gen_extu_i32_i64(tcg_rd
, t0
);
4638 tcg_temp_free_i32(t0
);
4644 /* Data processing - immediate */
4645 static void disas_data_proc_imm(DisasContext
*s
, uint32_t insn
)
4647 switch (extract32(insn
, 23, 6)) {
4648 case 0x20: case 0x21: /* PC-rel. addressing */
4649 disas_pc_rel_adr(s
, insn
);
4651 case 0x22: /* Add/subtract (immediate) */
4652 disas_add_sub_imm(s
, insn
);
4654 case 0x23: /* Add/subtract (immediate, with tags) */
4655 disas_add_sub_imm_with_tags(s
, insn
);
4657 case 0x24: /* Logical (immediate) */
4658 disas_logic_imm(s
, insn
);
4660 case 0x25: /* Move wide (immediate) */
4661 disas_movw_imm(s
, insn
);
4663 case 0x26: /* Bitfield */
4664 disas_bitfield(s
, insn
);
4666 case 0x27: /* Extract */
4667 disas_extract(s
, insn
);
4670 unallocated_encoding(s
);
4675 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
4676 * Note that it is the caller's responsibility to ensure that the
4677 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
4678 * mandated semantics for out of range shifts.
4680 static void shift_reg(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
4681 enum a64_shift_type shift_type
, TCGv_i64 shift_amount
)
4683 switch (shift_type
) {
4684 case A64_SHIFT_TYPE_LSL
:
4685 tcg_gen_shl_i64(dst
, src
, shift_amount
);
4687 case A64_SHIFT_TYPE_LSR
:
4688 tcg_gen_shr_i64(dst
, src
, shift_amount
);
4690 case A64_SHIFT_TYPE_ASR
:
4692 tcg_gen_ext32s_i64(dst
, src
);
4694 tcg_gen_sar_i64(dst
, sf
? src
: dst
, shift_amount
);
4696 case A64_SHIFT_TYPE_ROR
:
4698 tcg_gen_rotr_i64(dst
, src
, shift_amount
);
4701 t0
= tcg_temp_new_i32();
4702 t1
= tcg_temp_new_i32();
4703 tcg_gen_extrl_i64_i32(t0
, src
);
4704 tcg_gen_extrl_i64_i32(t1
, shift_amount
);
4705 tcg_gen_rotr_i32(t0
, t0
, t1
);
4706 tcg_gen_extu_i32_i64(dst
, t0
);
4707 tcg_temp_free_i32(t0
);
4708 tcg_temp_free_i32(t1
);
4712 assert(FALSE
); /* all shift types should be handled */
4716 if (!sf
) { /* zero extend final result */
4717 tcg_gen_ext32u_i64(dst
, dst
);
4721 /* Shift a TCGv src by immediate, put result in dst.
4722 * The shift amount must be in range (this should always be true as the
4723 * relevant instructions will UNDEF on bad shift immediates).
4725 static void shift_reg_imm(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
4726 enum a64_shift_type shift_type
, unsigned int shift_i
)
4728 assert(shift_i
< (sf
? 64 : 32));
4731 tcg_gen_mov_i64(dst
, src
);
4733 TCGv_i64 shift_const
;
4735 shift_const
= tcg_const_i64(shift_i
);
4736 shift_reg(dst
, src
, sf
, shift_type
, shift_const
);
4737 tcg_temp_free_i64(shift_const
);
4741 /* Logical (shifted register)
4742 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
4743 * +----+-----+-----------+-------+---+------+--------+------+------+
4744 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
4745 * +----+-----+-----------+-------+---+------+--------+------+------+
4747 static void disas_logic_reg(DisasContext
*s
, uint32_t insn
)
4749 TCGv_i64 tcg_rd
, tcg_rn
, tcg_rm
;
4750 unsigned int sf
, opc
, shift_type
, invert
, rm
, shift_amount
, rn
, rd
;
4752 sf
= extract32(insn
, 31, 1);
4753 opc
= extract32(insn
, 29, 2);
4754 shift_type
= extract32(insn
, 22, 2);
4755 invert
= extract32(insn
, 21, 1);
4756 rm
= extract32(insn
, 16, 5);
4757 shift_amount
= extract32(insn
, 10, 6);
4758 rn
= extract32(insn
, 5, 5);
4759 rd
= extract32(insn
, 0, 5);
4761 if (!sf
&& (shift_amount
& (1 << 5))) {
4762 unallocated_encoding(s
);
4766 tcg_rd
= cpu_reg(s
, rd
);
4768 if (opc
== 1 && shift_amount
== 0 && shift_type
== 0 && rn
== 31) {
4769 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
4770 * register-register MOV and MVN, so it is worth special casing.
4772 tcg_rm
= cpu_reg(s
, rm
);
4774 tcg_gen_not_i64(tcg_rd
, tcg_rm
);
4776 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4780 tcg_gen_mov_i64(tcg_rd
, tcg_rm
);
4782 tcg_gen_ext32u_i64(tcg_rd
, tcg_rm
);
4788 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4791 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, shift_amount
);
4794 tcg_rn
= cpu_reg(s
, rn
);
4796 switch (opc
| (invert
<< 2)) {
4799 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4802 tcg_gen_or_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4805 tcg_gen_xor_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4809 tcg_gen_andc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4812 tcg_gen_orc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4815 tcg_gen_eqv_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4823 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4827 gen_logic_CC(sf
, tcg_rd
);
4832 * Add/subtract (extended register)
4834 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
4835 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
4836 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
4837 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
4839 * sf: 0 -> 32bit, 1 -> 64bit
4840 * op: 0 -> add , 1 -> sub
4843 * option: extension type (see DecodeRegExtend)
4844 * imm3: optional shift to Rm
4846 * Rd = Rn + LSL(extend(Rm), amount)
4848 static void disas_add_sub_ext_reg(DisasContext
*s
, uint32_t insn
)
4850 int rd
= extract32(insn
, 0, 5);
4851 int rn
= extract32(insn
, 5, 5);
4852 int imm3
= extract32(insn
, 10, 3);
4853 int option
= extract32(insn
, 13, 3);
4854 int rm
= extract32(insn
, 16, 5);
4855 int opt
= extract32(insn
, 22, 2);
4856 bool setflags
= extract32(insn
, 29, 1);
4857 bool sub_op
= extract32(insn
, 30, 1);
4858 bool sf
= extract32(insn
, 31, 1);
4860 TCGv_i64 tcg_rm
, tcg_rn
; /* temps */
4862 TCGv_i64 tcg_result
;
4864 if (imm3
> 4 || opt
!= 0) {
4865 unallocated_encoding(s
);
4869 /* non-flag setting ops may use SP */
4871 tcg_rd
= cpu_reg_sp(s
, rd
);
4873 tcg_rd
= cpu_reg(s
, rd
);
4875 tcg_rn
= read_cpu_reg_sp(s
, rn
, sf
);
4877 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4878 ext_and_shift_reg(tcg_rm
, tcg_rm
, option
, imm3
);
4880 tcg_result
= tcg_temp_new_i64();
4884 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
4886 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
4890 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4892 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4897 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4899 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4902 tcg_temp_free_i64(tcg_result
);
4906 * Add/subtract (shifted register)
4908 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
4909 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4910 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
4911 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4913 * sf: 0 -> 32bit, 1 -> 64bit
4914 * op: 0 -> add , 1 -> sub
4916 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
4917 * imm6: Shift amount to apply to Rm before the add/sub
4919 static void disas_add_sub_reg(DisasContext
*s
, uint32_t insn
)
4921 int rd
= extract32(insn
, 0, 5);
4922 int rn
= extract32(insn
, 5, 5);
4923 int imm6
= extract32(insn
, 10, 6);
4924 int rm
= extract32(insn
, 16, 5);
4925 int shift_type
= extract32(insn
, 22, 2);
4926 bool setflags
= extract32(insn
, 29, 1);
4927 bool sub_op
= extract32(insn
, 30, 1);
4928 bool sf
= extract32(insn
, 31, 1);
4930 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4931 TCGv_i64 tcg_rn
, tcg_rm
;
4932 TCGv_i64 tcg_result
;
4934 if ((shift_type
== 3) || (!sf
&& (imm6
> 31))) {
4935 unallocated_encoding(s
);
4939 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4940 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4942 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, imm6
);
4944 tcg_result
= tcg_temp_new_i64();
4948 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
4950 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
4954 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4956 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4961 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4963 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4966 tcg_temp_free_i64(tcg_result
);
4969 /* Data-processing (3 source)
4971 * 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
4972 * +--+------+-----------+------+------+----+------+------+------+
4973 * |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
4974 * +--+------+-----------+------+------+----+------+------+------+
4976 static void disas_data_proc_3src(DisasContext
*s
, uint32_t insn
)
4978 int rd
= extract32(insn
, 0, 5);
4979 int rn
= extract32(insn
, 5, 5);
4980 int ra
= extract32(insn
, 10, 5);
4981 int rm
= extract32(insn
, 16, 5);
4982 int op_id
= (extract32(insn
, 29, 3) << 4) |
4983 (extract32(insn
, 21, 3) << 1) |
4984 extract32(insn
, 15, 1);
4985 bool sf
= extract32(insn
, 31, 1);
4986 bool is_sub
= extract32(op_id
, 0, 1);
4987 bool is_high
= extract32(op_id
, 2, 1);
4988 bool is_signed
= false;
4993 /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
4995 case 0x42: /* SMADDL */
4996 case 0x43: /* SMSUBL */
4997 case 0x44: /* SMULH */
5000 case 0x0: /* MADD (32bit) */
5001 case 0x1: /* MSUB (32bit) */
5002 case 0x40: /* MADD (64bit) */
5003 case 0x41: /* MSUB (64bit) */
5004 case 0x4a: /* UMADDL */
5005 case 0x4b: /* UMSUBL */
5006 case 0x4c: /* UMULH */
5009 unallocated_encoding(s
);
5014 TCGv_i64 low_bits
= tcg_temp_new_i64(); /* low bits discarded */
5015 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5016 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
5017 TCGv_i64 tcg_rm
= cpu_reg(s
, rm
);
5020 tcg_gen_muls2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
5022 tcg_gen_mulu2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
5025 tcg_temp_free_i64(low_bits
);
5029 tcg_op1
= tcg_temp_new_i64();
5030 tcg_op2
= tcg_temp_new_i64();
5031 tcg_tmp
= tcg_temp_new_i64();
5034 tcg_gen_mov_i64(tcg_op1
, cpu_reg(s
, rn
));
5035 tcg_gen_mov_i64(tcg_op2
, cpu_reg(s
, rm
));
5038 tcg_gen_ext32s_i64(tcg_op1
, cpu_reg(s
, rn
));
5039 tcg_gen_ext32s_i64(tcg_op2
, cpu_reg(s
, rm
));
5041 tcg_gen_ext32u_i64(tcg_op1
, cpu_reg(s
, rn
));
5042 tcg_gen_ext32u_i64(tcg_op2
, cpu_reg(s
, rm
));
5046 if (ra
== 31 && !is_sub
) {
5047 /* Special-case MADD with rA == XZR; it is the standard MUL alias */
5048 tcg_gen_mul_i64(cpu_reg(s
, rd
), tcg_op1
, tcg_op2
);
5050 tcg_gen_mul_i64(tcg_tmp
, tcg_op1
, tcg_op2
);
5052 tcg_gen_sub_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
5054 tcg_gen_add_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
5059 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), cpu_reg(s
, rd
));
5062 tcg_temp_free_i64(tcg_op1
);
5063 tcg_temp_free_i64(tcg_op2
);
5064 tcg_temp_free_i64(tcg_tmp
);
5067 /* Add/subtract (with carry)
5068 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
5069 * +--+--+--+------------------------+------+-------------+------+-----+
5070 * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | 0 0 0 0 0 0 | Rn | Rd |
5071 * +--+--+--+------------------------+------+-------------+------+-----+
5074 static void disas_adc_sbc(DisasContext
*s
, uint32_t insn
)
5076 unsigned int sf
, op
, setflags
, rm
, rn
, rd
;
5077 TCGv_i64 tcg_y
, tcg_rn
, tcg_rd
;
5079 sf
= extract32(insn
, 31, 1);
5080 op
= extract32(insn
, 30, 1);
5081 setflags
= extract32(insn
, 29, 1);
5082 rm
= extract32(insn
, 16, 5);
5083 rn
= extract32(insn
, 5, 5);
5084 rd
= extract32(insn
, 0, 5);
5086 tcg_rd
= cpu_reg(s
, rd
);
5087 tcg_rn
= cpu_reg(s
, rn
);
5090 tcg_y
= new_tmp_a64(s
);
5091 tcg_gen_not_i64(tcg_y
, cpu_reg(s
, rm
));
5093 tcg_y
= cpu_reg(s
, rm
);
5097 gen_adc_CC(sf
, tcg_rd
, tcg_rn
, tcg_y
);
5099 gen_adc(sf
, tcg_rd
, tcg_rn
, tcg_y
);
5104 * Rotate right into flags
5105 * 31 30 29 21 15 10 5 4 0
5106 * +--+--+--+-----------------+--------+-----------+------+--+------+
5107 * |sf|op| S| 1 1 0 1 0 0 0 0 | imm6 | 0 0 0 0 1 | Rn |o2| mask |
5108 * +--+--+--+-----------------+--------+-----------+------+--+------+
5110 static void disas_rotate_right_into_flags(DisasContext
*s
, uint32_t insn
)
5112 int mask
= extract32(insn
, 0, 4);
5113 int o2
= extract32(insn
, 4, 1);
5114 int rn
= extract32(insn
, 5, 5);
5115 int imm6
= extract32(insn
, 15, 6);
5116 int sf_op_s
= extract32(insn
, 29, 3);
5120 if (sf_op_s
!= 5 || o2
!= 0 || !dc_isar_feature(aa64_condm_4
, s
)) {
5121 unallocated_encoding(s
);
5125 tcg_rn
= read_cpu_reg(s
, rn
, 1);
5126 tcg_gen_rotri_i64(tcg_rn
, tcg_rn
, imm6
);
5128 nzcv
= tcg_temp_new_i32();
5129 tcg_gen_extrl_i64_i32(nzcv
, tcg_rn
);
5131 if (mask
& 8) { /* N */
5132 tcg_gen_shli_i32(cpu_NF
, nzcv
, 31 - 3);
5134 if (mask
& 4) { /* Z */
5135 tcg_gen_not_i32(cpu_ZF
, nzcv
);
5136 tcg_gen_andi_i32(cpu_ZF
, cpu_ZF
, 4);
5138 if (mask
& 2) { /* C */
5139 tcg_gen_extract_i32(cpu_CF
, nzcv
, 1, 1);
5141 if (mask
& 1) { /* V */
5142 tcg_gen_shli_i32(cpu_VF
, nzcv
, 31 - 0);
5145 tcg_temp_free_i32(nzcv
);
5149 * Evaluate into flags
5150 * 31 30 29 21 15 14 10 5 4 0
5151 * +--+--+--+-----------------+---------+----+---------+------+--+------+
5152 * |sf|op| S| 1 1 0 1 0 0 0 0 | opcode2 | sz | 0 0 1 0 | Rn |o3| mask |
5153 * +--+--+--+-----------------+---------+----+---------+------+--+------+
5155 static void disas_evaluate_into_flags(DisasContext
*s
, uint32_t insn
)
5157 int o3_mask
= extract32(insn
, 0, 5);
5158 int rn
= extract32(insn
, 5, 5);
5159 int o2
= extract32(insn
, 15, 6);
5160 int sz
= extract32(insn
, 14, 1);
5161 int sf_op_s
= extract32(insn
, 29, 3);
5165 if (sf_op_s
!= 1 || o2
!= 0 || o3_mask
!= 0xd ||
5166 !dc_isar_feature(aa64_condm_4
, s
)) {
5167 unallocated_encoding(s
);
5170 shift
= sz
? 16 : 24; /* SETF16 or SETF8 */
5172 tmp
= tcg_temp_new_i32();
5173 tcg_gen_extrl_i64_i32(tmp
, cpu_reg(s
, rn
));
5174 tcg_gen_shli_i32(cpu_NF
, tmp
, shift
);
5175 tcg_gen_shli_i32(cpu_VF
, tmp
, shift
- 1);
5176 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
5177 tcg_gen_xor_i32(cpu_VF
, cpu_VF
, cpu_NF
);
5178 tcg_temp_free_i32(tmp
);
5181 /* Conditional compare (immediate / register)
5182 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
5183 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
5184 * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
5185 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
5188 static void disas_cc(DisasContext
*s
, uint32_t insn
)
5190 unsigned int sf
, op
, y
, cond
, rn
, nzcv
, is_imm
;
5191 TCGv_i32 tcg_t0
, tcg_t1
, tcg_t2
;
5192 TCGv_i64 tcg_tmp
, tcg_y
, tcg_rn
;
5195 if (!extract32(insn
, 29, 1)) {
5196 unallocated_encoding(s
);
5199 if (insn
& (1 << 10 | 1 << 4)) {
5200 unallocated_encoding(s
);
5203 sf
= extract32(insn
, 31, 1);
5204 op
= extract32(insn
, 30, 1);
5205 is_imm
= extract32(insn
, 11, 1);
5206 y
= extract32(insn
, 16, 5); /* y = rm (reg) or imm5 (imm) */
5207 cond
= extract32(insn
, 12, 4);
5208 rn
= extract32(insn
, 5, 5);
5209 nzcv
= extract32(insn
, 0, 4);
5211 /* Set T0 = !COND. */
5212 tcg_t0
= tcg_temp_new_i32();
5213 arm_test_cc(&c
, cond
);
5214 tcg_gen_setcondi_i32(tcg_invert_cond(c
.cond
), tcg_t0
, c
.value
, 0);
5217 /* Load the arguments for the new comparison. */
5219 tcg_y
= new_tmp_a64(s
);
5220 tcg_gen_movi_i64(tcg_y
, y
);
5222 tcg_y
= cpu_reg(s
, y
);
5224 tcg_rn
= cpu_reg(s
, rn
);
5226 /* Set the flags for the new comparison. */
5227 tcg_tmp
= tcg_temp_new_i64();
5229 gen_sub_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
5231 gen_add_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
5233 tcg_temp_free_i64(tcg_tmp
);
5235 /* If COND was false, force the flags to #nzcv. Compute two masks
5236 * to help with this: T1 = (COND ? 0 : -1), T2 = (COND ? -1 : 0).
5237 * For tcg hosts that support ANDC, we can make do with just T1.
5238 * In either case, allow the tcg optimizer to delete any unused mask.
5240 tcg_t1
= tcg_temp_new_i32();
5241 tcg_t2
= tcg_temp_new_i32();
5242 tcg_gen_neg_i32(tcg_t1
, tcg_t0
);
5243 tcg_gen_subi_i32(tcg_t2
, tcg_t0
, 1);
5245 if (nzcv
& 8) { /* N */
5246 tcg_gen_or_i32(cpu_NF
, cpu_NF
, tcg_t1
);
5248 if (TCG_TARGET_HAS_andc_i32
) {
5249 tcg_gen_andc_i32(cpu_NF
, cpu_NF
, tcg_t1
);
5251 tcg_gen_and_i32(cpu_NF
, cpu_NF
, tcg_t2
);
5254 if (nzcv
& 4) { /* Z */
5255 if (TCG_TARGET_HAS_andc_i32
) {
5256 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, tcg_t1
);
5258 tcg_gen_and_i32(cpu_ZF
, cpu_ZF
, tcg_t2
);
5261 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, tcg_t0
);
5263 if (nzcv
& 2) { /* C */
5264 tcg_gen_or_i32(cpu_CF
, cpu_CF
, tcg_t0
);
5266 if (TCG_TARGET_HAS_andc_i32
) {
5267 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, tcg_t1
);
5269 tcg_gen_and_i32(cpu_CF
, cpu_CF
, tcg_t2
);
5272 if (nzcv
& 1) { /* V */
5273 tcg_gen_or_i32(cpu_VF
, cpu_VF
, tcg_t1
);
5275 if (TCG_TARGET_HAS_andc_i32
) {
5276 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tcg_t1
);
5278 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tcg_t2
);
5281 tcg_temp_free_i32(tcg_t0
);
5282 tcg_temp_free_i32(tcg_t1
);
5283 tcg_temp_free_i32(tcg_t2
);
5286 /* Conditional select
5287 * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
5288 * +----+----+---+-----------------+------+------+-----+------+------+
5289 * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
5290 * +----+----+---+-----------------+------+------+-----+------+------+
5292 static void disas_cond_select(DisasContext
*s
, uint32_t insn
)
5294 unsigned int sf
, else_inv
, rm
, cond
, else_inc
, rn
, rd
;
5295 TCGv_i64 tcg_rd
, zero
;
5298 if (extract32(insn
, 29, 1) || extract32(insn
, 11, 1)) {
5299 /* S == 1 or op2<1> == 1 */
5300 unallocated_encoding(s
);
5303 sf
= extract32(insn
, 31, 1);
5304 else_inv
= extract32(insn
, 30, 1);
5305 rm
= extract32(insn
, 16, 5);
5306 cond
= extract32(insn
, 12, 4);
5307 else_inc
= extract32(insn
, 10, 1);
5308 rn
= extract32(insn
, 5, 5);
5309 rd
= extract32(insn
, 0, 5);
5311 tcg_rd
= cpu_reg(s
, rd
);
5313 a64_test_cc(&c
, cond
);
5314 zero
= tcg_const_i64(0);
5316 if (rn
== 31 && rm
== 31 && (else_inc
^ else_inv
)) {
5318 tcg_gen_setcond_i64(tcg_invert_cond(c
.cond
), tcg_rd
, c
.value
, zero
);
5320 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
5323 TCGv_i64 t_true
= cpu_reg(s
, rn
);
5324 TCGv_i64 t_false
= read_cpu_reg(s
, rm
, 1);
5325 if (else_inv
&& else_inc
) {
5326 tcg_gen_neg_i64(t_false
, t_false
);
5327 } else if (else_inv
) {
5328 tcg_gen_not_i64(t_false
, t_false
);
5329 } else if (else_inc
) {
5330 tcg_gen_addi_i64(t_false
, t_false
, 1);
5332 tcg_gen_movcond_i64(c
.cond
, tcg_rd
, c
.value
, zero
, t_true
, t_false
);
5335 tcg_temp_free_i64(zero
);
5339 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
5343 static void handle_clz(DisasContext
*s
, unsigned int sf
,
5344 unsigned int rn
, unsigned int rd
)
5346 TCGv_i64 tcg_rd
, tcg_rn
;
5347 tcg_rd
= cpu_reg(s
, rd
);
5348 tcg_rn
= cpu_reg(s
, rn
);
5351 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
5353 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
5354 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
5355 tcg_gen_clzi_i32(tcg_tmp32
, tcg_tmp32
, 32);
5356 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
5357 tcg_temp_free_i32(tcg_tmp32
);
5361 static void handle_cls(DisasContext
*s
, unsigned int sf
,
5362 unsigned int rn
, unsigned int rd
)
5364 TCGv_i64 tcg_rd
, tcg_rn
;
5365 tcg_rd
= cpu_reg(s
, rd
);
5366 tcg_rn
= cpu_reg(s
, rn
);
5369 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
5371 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
5372 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
5373 tcg_gen_clrsb_i32(tcg_tmp32
, tcg_tmp32
);
5374 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
5375 tcg_temp_free_i32(tcg_tmp32
);
5379 static void handle_rbit(DisasContext
*s
, unsigned int sf
,
5380 unsigned int rn
, unsigned int rd
)
5382 TCGv_i64 tcg_rd
, tcg_rn
;
5383 tcg_rd
= cpu_reg(s
, rd
);
5384 tcg_rn
= cpu_reg(s
, rn
);
5387 gen_helper_rbit64(tcg_rd
, tcg_rn
);
5389 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
5390 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
5391 gen_helper_rbit(tcg_tmp32
, tcg_tmp32
);
5392 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
5393 tcg_temp_free_i32(tcg_tmp32
);
5397 /* REV with sf==1, opcode==3 ("REV64") */
5398 static void handle_rev64(DisasContext
*s
, unsigned int sf
,
5399 unsigned int rn
, unsigned int rd
)
5402 unallocated_encoding(s
);
5405 tcg_gen_bswap64_i64(cpu_reg(s
, rd
), cpu_reg(s
, rn
));
5408 /* REV with sf==0, opcode==2
5409 * REV32 (sf==1, opcode==2)
5411 static void handle_rev32(DisasContext
*s
, unsigned int sf
,
5412 unsigned int rn
, unsigned int rd
)
5414 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5415 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
5418 tcg_gen_bswap64_i64(tcg_rd
, tcg_rn
);
5419 tcg_gen_rotri_i64(tcg_rd
, tcg_rd
, 32);
5421 tcg_gen_bswap32_i64(tcg_rd
, tcg_rn
, TCG_BSWAP_OZ
);
5425 /* REV16 (opcode==1) */
5426 static void handle_rev16(DisasContext
*s
, unsigned int sf
,
5427 unsigned int rn
, unsigned int rd
)
5429 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5430 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
5431 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
5432 TCGv_i64 mask
= tcg_const_i64(sf
? 0x00ff00ff00ff00ffull
: 0x00ff00ff);
5434 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 8);
5435 tcg_gen_and_i64(tcg_rd
, tcg_rn
, mask
);
5436 tcg_gen_and_i64(tcg_tmp
, tcg_tmp
, mask
);
5437 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, 8);
5438 tcg_gen_or_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
5440 tcg_temp_free_i64(mask
);
5441 tcg_temp_free_i64(tcg_tmp
);
5444 /* Data-processing (1 source)
5445 * 31 30 29 28 21 20 16 15 10 9 5 4 0
5446 * +----+---+---+-----------------+---------+--------+------+------+
5447 * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
5448 * +----+---+---+-----------------+---------+--------+------+------+
5450 static void disas_data_proc_1src(DisasContext
*s
, uint32_t insn
)
5452 unsigned int sf
, opcode
, opcode2
, rn
, rd
;
5455 if (extract32(insn
, 29, 1)) {
5456 unallocated_encoding(s
);
5460 sf
= extract32(insn
, 31, 1);
5461 opcode
= extract32(insn
, 10, 6);
5462 opcode2
= extract32(insn
, 16, 5);
5463 rn
= extract32(insn
, 5, 5);
5464 rd
= extract32(insn
, 0, 5);
5466 #define MAP(SF, O2, O1) ((SF) | (O1 << 1) | (O2 << 7))
5468 switch (MAP(sf
, opcode2
, opcode
)) {
5469 case MAP(0, 0x00, 0x00): /* RBIT */
5470 case MAP(1, 0x00, 0x00):
5471 handle_rbit(s
, sf
, rn
, rd
);
5473 case MAP(0, 0x00, 0x01): /* REV16 */
5474 case MAP(1, 0x00, 0x01):
5475 handle_rev16(s
, sf
, rn
, rd
);
5477 case MAP(0, 0x00, 0x02): /* REV/REV32 */
5478 case MAP(1, 0x00, 0x02):
5479 handle_rev32(s
, sf
, rn
, rd
);
5481 case MAP(1, 0x00, 0x03): /* REV64 */
5482 handle_rev64(s
, sf
, rn
, rd
);
5484 case MAP(0, 0x00, 0x04): /* CLZ */
5485 case MAP(1, 0x00, 0x04):
5486 handle_clz(s
, sf
, rn
, rd
);
5488 case MAP(0, 0x00, 0x05): /* CLS */
5489 case MAP(1, 0x00, 0x05):
5490 handle_cls(s
, sf
, rn
, rd
);
5492 case MAP(1, 0x01, 0x00): /* PACIA */
5493 if (s
->pauth_active
) {
5494 tcg_rd
= cpu_reg(s
, rd
);
5495 gen_helper_pacia(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5496 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5497 goto do_unallocated
;
5500 case MAP(1, 0x01, 0x01): /* PACIB */
5501 if (s
->pauth_active
) {
5502 tcg_rd
= cpu_reg(s
, rd
);
5503 gen_helper_pacib(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5504 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5505 goto do_unallocated
;
5508 case MAP(1, 0x01, 0x02): /* PACDA */
5509 if (s
->pauth_active
) {
5510 tcg_rd
= cpu_reg(s
, rd
);
5511 gen_helper_pacda(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5512 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5513 goto do_unallocated
;
5516 case MAP(1, 0x01, 0x03): /* PACDB */
5517 if (s
->pauth_active
) {
5518 tcg_rd
= cpu_reg(s
, rd
);
5519 gen_helper_pacdb(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5520 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5521 goto do_unallocated
;
5524 case MAP(1, 0x01, 0x04): /* AUTIA */
5525 if (s
->pauth_active
) {
5526 tcg_rd
= cpu_reg(s
, rd
);
5527 gen_helper_autia(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5528 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5529 goto do_unallocated
;
5532 case MAP(1, 0x01, 0x05): /* AUTIB */
5533 if (s
->pauth_active
) {
5534 tcg_rd
= cpu_reg(s
, rd
);
5535 gen_helper_autib(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5536 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5537 goto do_unallocated
;
5540 case MAP(1, 0x01, 0x06): /* AUTDA */
5541 if (s
->pauth_active
) {
5542 tcg_rd
= cpu_reg(s
, rd
);
5543 gen_helper_autda(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5544 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5545 goto do_unallocated
;
5548 case MAP(1, 0x01, 0x07): /* AUTDB */
5549 if (s
->pauth_active
) {
5550 tcg_rd
= cpu_reg(s
, rd
);
5551 gen_helper_autdb(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5552 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5553 goto do_unallocated
;
5556 case MAP(1, 0x01, 0x08): /* PACIZA */
5557 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5558 goto do_unallocated
;
5559 } else if (s
->pauth_active
) {
5560 tcg_rd
= cpu_reg(s
, rd
);
5561 gen_helper_pacia(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5564 case MAP(1, 0x01, 0x09): /* PACIZB */
5565 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5566 goto do_unallocated
;
5567 } else if (s
->pauth_active
) {
5568 tcg_rd
= cpu_reg(s
, rd
);
5569 gen_helper_pacib(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5572 case MAP(1, 0x01, 0x0a): /* PACDZA */
5573 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5574 goto do_unallocated
;
5575 } else if (s
->pauth_active
) {
5576 tcg_rd
= cpu_reg(s
, rd
);
5577 gen_helper_pacda(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5580 case MAP(1, 0x01, 0x0b): /* PACDZB */
5581 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5582 goto do_unallocated
;
5583 } else if (s
->pauth_active
) {
5584 tcg_rd
= cpu_reg(s
, rd
);
5585 gen_helper_pacdb(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5588 case MAP(1, 0x01, 0x0c): /* AUTIZA */
5589 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5590 goto do_unallocated
;
5591 } else if (s
->pauth_active
) {
5592 tcg_rd
= cpu_reg(s
, rd
);
5593 gen_helper_autia(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5596 case MAP(1, 0x01, 0x0d): /* AUTIZB */
5597 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5598 goto do_unallocated
;
5599 } else if (s
->pauth_active
) {
5600 tcg_rd
= cpu_reg(s
, rd
);
5601 gen_helper_autib(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5604 case MAP(1, 0x01, 0x0e): /* AUTDZA */
5605 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5606 goto do_unallocated
;
5607 } else if (s
->pauth_active
) {
5608 tcg_rd
= cpu_reg(s
, rd
);
5609 gen_helper_autda(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5612 case MAP(1, 0x01, 0x0f): /* AUTDZB */
5613 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5614 goto do_unallocated
;
5615 } else if (s
->pauth_active
) {
5616 tcg_rd
= cpu_reg(s
, rd
);
5617 gen_helper_autdb(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5620 case MAP(1, 0x01, 0x10): /* XPACI */
5621 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5622 goto do_unallocated
;
5623 } else if (s
->pauth_active
) {
5624 tcg_rd
= cpu_reg(s
, rd
);
5625 gen_helper_xpaci(tcg_rd
, cpu_env
, tcg_rd
);
5628 case MAP(1, 0x01, 0x11): /* XPACD */
5629 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5630 goto do_unallocated
;
5631 } else if (s
->pauth_active
) {
5632 tcg_rd
= cpu_reg(s
, rd
);
5633 gen_helper_xpacd(tcg_rd
, cpu_env
, tcg_rd
);
5638 unallocated_encoding(s
);
5645 static void handle_div(DisasContext
*s
, bool is_signed
, unsigned int sf
,
5646 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5648 TCGv_i64 tcg_n
, tcg_m
, tcg_rd
;
5649 tcg_rd
= cpu_reg(s
, rd
);
5651 if (!sf
&& is_signed
) {
5652 tcg_n
= new_tmp_a64(s
);
5653 tcg_m
= new_tmp_a64(s
);
5654 tcg_gen_ext32s_i64(tcg_n
, cpu_reg(s
, rn
));
5655 tcg_gen_ext32s_i64(tcg_m
, cpu_reg(s
, rm
));
5657 tcg_n
= read_cpu_reg(s
, rn
, sf
);
5658 tcg_m
= read_cpu_reg(s
, rm
, sf
);
5662 gen_helper_sdiv64(tcg_rd
, tcg_n
, tcg_m
);
5664 gen_helper_udiv64(tcg_rd
, tcg_n
, tcg_m
);
5667 if (!sf
) { /* zero extend final result */
5668 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
5672 /* LSLV, LSRV, ASRV, RORV */
5673 static void handle_shift_reg(DisasContext
*s
,
5674 enum a64_shift_type shift_type
, unsigned int sf
,
5675 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5677 TCGv_i64 tcg_shift
= tcg_temp_new_i64();
5678 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5679 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
5681 tcg_gen_andi_i64(tcg_shift
, cpu_reg(s
, rm
), sf
? 63 : 31);
5682 shift_reg(tcg_rd
, tcg_rn
, sf
, shift_type
, tcg_shift
);
5683 tcg_temp_free_i64(tcg_shift
);
5686 /* CRC32[BHWX], CRC32C[BHWX] */
5687 static void handle_crc32(DisasContext
*s
,
5688 unsigned int sf
, unsigned int sz
, bool crc32c
,
5689 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5691 TCGv_i64 tcg_acc
, tcg_val
;
5694 if (!dc_isar_feature(aa64_crc32
, s
)
5695 || (sf
== 1 && sz
!= 3)
5696 || (sf
== 0 && sz
== 3)) {
5697 unallocated_encoding(s
);
5702 tcg_val
= cpu_reg(s
, rm
);
5716 g_assert_not_reached();
5718 tcg_val
= new_tmp_a64(s
);
5719 tcg_gen_andi_i64(tcg_val
, cpu_reg(s
, rm
), mask
);
5722 tcg_acc
= cpu_reg(s
, rn
);
5723 tcg_bytes
= tcg_const_i32(1 << sz
);
5726 gen_helper_crc32c_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
5728 gen_helper_crc32_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
5731 tcg_temp_free_i32(tcg_bytes
);
5734 /* Data-processing (2 source)
5735 * 31 30 29 28 21 20 16 15 10 9 5 4 0
5736 * +----+---+---+-----------------+------+--------+------+------+
5737 * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
5738 * +----+---+---+-----------------+------+--------+------+------+
5740 static void disas_data_proc_2src(DisasContext
*s
, uint32_t insn
)
5742 unsigned int sf
, rm
, opcode
, rn
, rd
, setflag
;
5743 sf
= extract32(insn
, 31, 1);
5744 setflag
= extract32(insn
, 29, 1);
5745 rm
= extract32(insn
, 16, 5);
5746 opcode
= extract32(insn
, 10, 6);
5747 rn
= extract32(insn
, 5, 5);
5748 rd
= extract32(insn
, 0, 5);
5750 if (setflag
&& opcode
!= 0) {
5751 unallocated_encoding(s
);
5756 case 0: /* SUBP(S) */
5757 if (sf
== 0 || !dc_isar_feature(aa64_mte_insn_reg
, s
)) {
5758 goto do_unallocated
;
5760 TCGv_i64 tcg_n
, tcg_m
, tcg_d
;
5762 tcg_n
= read_cpu_reg_sp(s
, rn
, true);
5763 tcg_m
= read_cpu_reg_sp(s
, rm
, true);
5764 tcg_gen_sextract_i64(tcg_n
, tcg_n
, 0, 56);
5765 tcg_gen_sextract_i64(tcg_m
, tcg_m
, 0, 56);
5766 tcg_d
= cpu_reg(s
, rd
);
5769 gen_sub_CC(true, tcg_d
, tcg_n
, tcg_m
);
5771 tcg_gen_sub_i64(tcg_d
, tcg_n
, tcg_m
);
5776 handle_div(s
, false, sf
, rm
, rn
, rd
);
5779 handle_div(s
, true, sf
, rm
, rn
, rd
);
5782 if (sf
== 0 || !dc_isar_feature(aa64_mte_insn_reg
, s
)) {
5783 goto do_unallocated
;
5786 gen_helper_irg(cpu_reg_sp(s
, rd
), cpu_env
,
5787 cpu_reg_sp(s
, rn
), cpu_reg(s
, rm
));
5789 gen_address_with_allocation_tag0(cpu_reg_sp(s
, rd
),
5794 if (sf
== 0 || !dc_isar_feature(aa64_mte_insn_reg
, s
)) {
5795 goto do_unallocated
;
5797 TCGv_i64 t1
= tcg_const_i64(1);
5798 TCGv_i64 t2
= tcg_temp_new_i64();
5800 tcg_gen_extract_i64(t2
, cpu_reg_sp(s
, rn
), 56, 4);
5801 tcg_gen_shl_i64(t1
, t1
, t2
);
5802 tcg_gen_or_i64(cpu_reg(s
, rd
), cpu_reg(s
, rm
), t1
);
5804 tcg_temp_free_i64(t1
);
5805 tcg_temp_free_i64(t2
);
5809 handle_shift_reg(s
, A64_SHIFT_TYPE_LSL
, sf
, rm
, rn
, rd
);
5812 handle_shift_reg(s
, A64_SHIFT_TYPE_LSR
, sf
, rm
, rn
, rd
);
5815 handle_shift_reg(s
, A64_SHIFT_TYPE_ASR
, sf
, rm
, rn
, rd
);
5818 handle_shift_reg(s
, A64_SHIFT_TYPE_ROR
, sf
, rm
, rn
, rd
);
5820 case 12: /* PACGA */
5821 if (sf
== 0 || !dc_isar_feature(aa64_pauth
, s
)) {
5822 goto do_unallocated
;
5824 gen_helper_pacga(cpu_reg(s
, rd
), cpu_env
,
5825 cpu_reg(s
, rn
), cpu_reg_sp(s
, rm
));
5834 case 23: /* CRC32 */
5836 int sz
= extract32(opcode
, 0, 2);
5837 bool crc32c
= extract32(opcode
, 2, 1);
5838 handle_crc32(s
, sf
, sz
, crc32c
, rm
, rn
, rd
);
5843 unallocated_encoding(s
);
5849 * Data processing - register
5850 * 31 30 29 28 25 21 20 16 10 0
5851 * +--+---+--+---+-------+-----+-------+-------+---------+
5852 * | |op0| |op1| 1 0 1 | op2 | | op3 | |
5853 * +--+---+--+---+-------+-----+-------+-------+---------+
5855 static void disas_data_proc_reg(DisasContext
*s
, uint32_t insn
)
5857 int op0
= extract32(insn
, 30, 1);
5858 int op1
= extract32(insn
, 28, 1);
5859 int op2
= extract32(insn
, 21, 4);
5860 int op3
= extract32(insn
, 10, 6);
5865 /* Add/sub (extended register) */
5866 disas_add_sub_ext_reg(s
, insn
);
5868 /* Add/sub (shifted register) */
5869 disas_add_sub_reg(s
, insn
);
5872 /* Logical (shifted register) */
5873 disas_logic_reg(s
, insn
);
5881 case 0x00: /* Add/subtract (with carry) */
5882 disas_adc_sbc(s
, insn
);
5885 case 0x01: /* Rotate right into flags */
5887 disas_rotate_right_into_flags(s
, insn
);
5890 case 0x02: /* Evaluate into flags */
5894 disas_evaluate_into_flags(s
, insn
);
5898 goto do_unallocated
;
5902 case 0x2: /* Conditional compare */
5903 disas_cc(s
, insn
); /* both imm and reg forms */
5906 case 0x4: /* Conditional select */
5907 disas_cond_select(s
, insn
);
5910 case 0x6: /* Data-processing */
5911 if (op0
) { /* (1 source) */
5912 disas_data_proc_1src(s
, insn
);
5913 } else { /* (2 source) */
5914 disas_data_proc_2src(s
, insn
);
5917 case 0x8 ... 0xf: /* (3 source) */
5918 disas_data_proc_3src(s
, insn
);
5923 unallocated_encoding(s
);
5928 static void handle_fp_compare(DisasContext
*s
, int size
,
5929 unsigned int rn
, unsigned int rm
,
5930 bool cmp_with_zero
, bool signal_all_nans
)
5932 TCGv_i64 tcg_flags
= tcg_temp_new_i64();
5933 TCGv_ptr fpst
= fpstatus_ptr(size
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
5935 if (size
== MO_64
) {
5936 TCGv_i64 tcg_vn
, tcg_vm
;
5938 tcg_vn
= read_fp_dreg(s
, rn
);
5939 if (cmp_with_zero
) {
5940 tcg_vm
= tcg_const_i64(0);
5942 tcg_vm
= read_fp_dreg(s
, rm
);
5944 if (signal_all_nans
) {
5945 gen_helper_vfp_cmped_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5947 gen_helper_vfp_cmpd_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5949 tcg_temp_free_i64(tcg_vn
);
5950 tcg_temp_free_i64(tcg_vm
);
5952 TCGv_i32 tcg_vn
= tcg_temp_new_i32();
5953 TCGv_i32 tcg_vm
= tcg_temp_new_i32();
5955 read_vec_element_i32(s
, tcg_vn
, rn
, 0, size
);
5956 if (cmp_with_zero
) {
5957 tcg_gen_movi_i32(tcg_vm
, 0);
5959 read_vec_element_i32(s
, tcg_vm
, rm
, 0, size
);
5964 if (signal_all_nans
) {
5965 gen_helper_vfp_cmpes_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5967 gen_helper_vfp_cmps_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5971 if (signal_all_nans
) {
5972 gen_helper_vfp_cmpeh_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5974 gen_helper_vfp_cmph_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5978 g_assert_not_reached();
5981 tcg_temp_free_i32(tcg_vn
);
5982 tcg_temp_free_i32(tcg_vm
);
5985 tcg_temp_free_ptr(fpst
);
5987 gen_set_nzcv(tcg_flags
);
5989 tcg_temp_free_i64(tcg_flags
);
5992 /* Floating point compare
5993 * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
5994 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
5995 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
5996 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
5998 static void disas_fp_compare(DisasContext
*s
, uint32_t insn
)
6000 unsigned int mos
, type
, rm
, op
, rn
, opc
, op2r
;
6003 mos
= extract32(insn
, 29, 3);
6004 type
= extract32(insn
, 22, 2);
6005 rm
= extract32(insn
, 16, 5);
6006 op
= extract32(insn
, 14, 2);
6007 rn
= extract32(insn
, 5, 5);
6008 opc
= extract32(insn
, 3, 2);
6009 op2r
= extract32(insn
, 0, 3);
6011 if (mos
|| op
|| op2r
) {
6012 unallocated_encoding(s
);
6025 if (dc_isar_feature(aa64_fp16
, s
)) {
6030 unallocated_encoding(s
);
6034 if (!fp_access_check(s
)) {
6038 handle_fp_compare(s
, size
, rn
, rm
, opc
& 1, opc
& 2);
6041 /* Floating point conditional compare
6042 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
6043 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
6044 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
6045 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
6047 static void disas_fp_ccomp(DisasContext
*s
, uint32_t insn
)
6049 unsigned int mos
, type
, rm
, cond
, rn
, op
, nzcv
;
6051 TCGLabel
*label_continue
= NULL
;
6054 mos
= extract32(insn
, 29, 3);
6055 type
= extract32(insn
, 22, 2);
6056 rm
= extract32(insn
, 16, 5);
6057 cond
= extract32(insn
, 12, 4);
6058 rn
= extract32(insn
, 5, 5);
6059 op
= extract32(insn
, 4, 1);
6060 nzcv
= extract32(insn
, 0, 4);
6063 unallocated_encoding(s
);
6076 if (dc_isar_feature(aa64_fp16
, s
)) {
6081 unallocated_encoding(s
);
6085 if (!fp_access_check(s
)) {
6089 if (cond
< 0x0e) { /* not always */
6090 TCGLabel
*label_match
= gen_new_label();
6091 label_continue
= gen_new_label();
6092 arm_gen_test_cc(cond
, label_match
);
6094 tcg_flags
= tcg_const_i64(nzcv
<< 28);
6095 gen_set_nzcv(tcg_flags
);
6096 tcg_temp_free_i64(tcg_flags
);
6097 tcg_gen_br(label_continue
);
6098 gen_set_label(label_match
);
6101 handle_fp_compare(s
, size
, rn
, rm
, false, op
);
6104 gen_set_label(label_continue
);
6108 /* Floating point conditional select
6109 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
6110 * +---+---+---+-----------+------+---+------+------+-----+------+------+
6111 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
6112 * +---+---+---+-----------+------+---+------+------+-----+------+------+
6114 static void disas_fp_csel(DisasContext
*s
, uint32_t insn
)
6116 unsigned int mos
, type
, rm
, cond
, rn
, rd
;
6117 TCGv_i64 t_true
, t_false
, t_zero
;
6121 mos
= extract32(insn
, 29, 3);
6122 type
= extract32(insn
, 22, 2);
6123 rm
= extract32(insn
, 16, 5);
6124 cond
= extract32(insn
, 12, 4);
6125 rn
= extract32(insn
, 5, 5);
6126 rd
= extract32(insn
, 0, 5);
6129 unallocated_encoding(s
);
6142 if (dc_isar_feature(aa64_fp16
, s
)) {
6147 unallocated_encoding(s
);
6151 if (!fp_access_check(s
)) {
6155 /* Zero extend sreg & hreg inputs to 64 bits now. */
6156 t_true
= tcg_temp_new_i64();
6157 t_false
= tcg_temp_new_i64();
6158 read_vec_element(s
, t_true
, rn
, 0, sz
);
6159 read_vec_element(s
, t_false
, rm
, 0, sz
);
6161 a64_test_cc(&c
, cond
);
6162 t_zero
= tcg_const_i64(0);
6163 tcg_gen_movcond_i64(c
.cond
, t_true
, c
.value
, t_zero
, t_true
, t_false
);
6164 tcg_temp_free_i64(t_zero
);
6165 tcg_temp_free_i64(t_false
);
6168 /* Note that sregs & hregs write back zeros to the high bits,
6169 and we've already done the zero-extension. */
6170 write_fp_dreg(s
, rd
, t_true
);
6171 tcg_temp_free_i64(t_true
);
6174 /* Floating-point data-processing (1 source) - half precision */
6175 static void handle_fp_1src_half(DisasContext
*s
, int opcode
, int rd
, int rn
)
6177 TCGv_ptr fpst
= NULL
;
6178 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
6179 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6182 case 0x0: /* FMOV */
6183 tcg_gen_mov_i32(tcg_res
, tcg_op
);
6185 case 0x1: /* FABS */
6186 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
6188 case 0x2: /* FNEG */
6189 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
6191 case 0x3: /* FSQRT */
6192 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
6193 gen_helper_sqrt_f16(tcg_res
, tcg_op
, fpst
);
6195 case 0x8: /* FRINTN */
6196 case 0x9: /* FRINTP */
6197 case 0xa: /* FRINTM */
6198 case 0xb: /* FRINTZ */
6199 case 0xc: /* FRINTA */
6201 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
6202 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
6204 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
6205 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
6207 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
6208 tcg_temp_free_i32(tcg_rmode
);
6211 case 0xe: /* FRINTX */
6212 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
6213 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, fpst
);
6215 case 0xf: /* FRINTI */
6216 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
6217 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
6223 write_fp_sreg(s
, rd
, tcg_res
);
6226 tcg_temp_free_ptr(fpst
);
6228 tcg_temp_free_i32(tcg_op
);
6229 tcg_temp_free_i32(tcg_res
);
6232 /* Floating-point data-processing (1 source) - single precision */
6233 static void handle_fp_1src_single(DisasContext
*s
, int opcode
, int rd
, int rn
)
6235 void (*gen_fpst
)(TCGv_i32
, TCGv_i32
, TCGv_ptr
);
6236 TCGv_i32 tcg_op
, tcg_res
;
6240 tcg_op
= read_fp_sreg(s
, rn
);
6241 tcg_res
= tcg_temp_new_i32();
6244 case 0x0: /* FMOV */
6245 tcg_gen_mov_i32(tcg_res
, tcg_op
);
6247 case 0x1: /* FABS */
6248 gen_helper_vfp_abss(tcg_res
, tcg_op
);
6250 case 0x2: /* FNEG */
6251 gen_helper_vfp_negs(tcg_res
, tcg_op
);
6253 case 0x3: /* FSQRT */
6254 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
6256 case 0x6: /* BFCVT */
6257 gen_fpst
= gen_helper_bfcvt
;
6259 case 0x8: /* FRINTN */
6260 case 0x9: /* FRINTP */
6261 case 0xa: /* FRINTM */
6262 case 0xb: /* FRINTZ */
6263 case 0xc: /* FRINTA */
6264 rmode
= arm_rmode_to_sf(opcode
& 7);
6265 gen_fpst
= gen_helper_rints
;
6267 case 0xe: /* FRINTX */
6268 gen_fpst
= gen_helper_rints_exact
;
6270 case 0xf: /* FRINTI */
6271 gen_fpst
= gen_helper_rints
;
6273 case 0x10: /* FRINT32Z */
6274 rmode
= float_round_to_zero
;
6275 gen_fpst
= gen_helper_frint32_s
;
6277 case 0x11: /* FRINT32X */
6278 gen_fpst
= gen_helper_frint32_s
;
6280 case 0x12: /* FRINT64Z */
6281 rmode
= float_round_to_zero
;
6282 gen_fpst
= gen_helper_frint64_s
;
6284 case 0x13: /* FRINT64X */
6285 gen_fpst
= gen_helper_frint64_s
;
6288 g_assert_not_reached();
6291 fpst
= fpstatus_ptr(FPST_FPCR
);
6293 TCGv_i32 tcg_rmode
= tcg_const_i32(rmode
);
6294 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
6295 gen_fpst(tcg_res
, tcg_op
, fpst
);
6296 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
6297 tcg_temp_free_i32(tcg_rmode
);
6299 gen_fpst(tcg_res
, tcg_op
, fpst
);
6301 tcg_temp_free_ptr(fpst
);
6304 write_fp_sreg(s
, rd
, tcg_res
);
6305 tcg_temp_free_i32(tcg_op
);
6306 tcg_temp_free_i32(tcg_res
);
6309 /* Floating-point data-processing (1 source) - double precision */
6310 static void handle_fp_1src_double(DisasContext
*s
, int opcode
, int rd
, int rn
)
6312 void (*gen_fpst
)(TCGv_i64
, TCGv_i64
, TCGv_ptr
);
6313 TCGv_i64 tcg_op
, tcg_res
;
6318 case 0x0: /* FMOV */
6319 gen_gvec_fn2(s
, false, rd
, rn
, tcg_gen_gvec_mov
, 0);
6323 tcg_op
= read_fp_dreg(s
, rn
);
6324 tcg_res
= tcg_temp_new_i64();
6327 case 0x1: /* FABS */
6328 gen_helper_vfp_absd(tcg_res
, tcg_op
);
6330 case 0x2: /* FNEG */
6331 gen_helper_vfp_negd(tcg_res
, tcg_op
);
6333 case 0x3: /* FSQRT */
6334 gen_helper_vfp_sqrtd(tcg_res
, tcg_op
, cpu_env
);
6336 case 0x8: /* FRINTN */
6337 case 0x9: /* FRINTP */
6338 case 0xa: /* FRINTM */
6339 case 0xb: /* FRINTZ */
6340 case 0xc: /* FRINTA */
6341 rmode
= arm_rmode_to_sf(opcode
& 7);
6342 gen_fpst
= gen_helper_rintd
;
6344 case 0xe: /* FRINTX */
6345 gen_fpst
= gen_helper_rintd_exact
;
6347 case 0xf: /* FRINTI */
6348 gen_fpst
= gen_helper_rintd
;
6350 case 0x10: /* FRINT32Z */
6351 rmode
= float_round_to_zero
;
6352 gen_fpst
= gen_helper_frint32_d
;
6354 case 0x11: /* FRINT32X */
6355 gen_fpst
= gen_helper_frint32_d
;
6357 case 0x12: /* FRINT64Z */
6358 rmode
= float_round_to_zero
;
6359 gen_fpst
= gen_helper_frint64_d
;
6361 case 0x13: /* FRINT64X */
6362 gen_fpst
= gen_helper_frint64_d
;
6365 g_assert_not_reached();
6368 fpst
= fpstatus_ptr(FPST_FPCR
);
6370 TCGv_i32 tcg_rmode
= tcg_const_i32(rmode
);
6371 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
6372 gen_fpst(tcg_res
, tcg_op
, fpst
);
6373 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
6374 tcg_temp_free_i32(tcg_rmode
);
6376 gen_fpst(tcg_res
, tcg_op
, fpst
);
6378 tcg_temp_free_ptr(fpst
);
6381 write_fp_dreg(s
, rd
, tcg_res
);
6382 tcg_temp_free_i64(tcg_op
);
6383 tcg_temp_free_i64(tcg_res
);
6386 static void handle_fp_fcvt(DisasContext
*s
, int opcode
,
6387 int rd
, int rn
, int dtype
, int ntype
)
6392 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
6394 /* Single to double */
6395 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
6396 gen_helper_vfp_fcvtds(tcg_rd
, tcg_rn
, cpu_env
);
6397 write_fp_dreg(s
, rd
, tcg_rd
);
6398 tcg_temp_free_i64(tcg_rd
);
6400 /* Single to half */
6401 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
6402 TCGv_i32 ahp
= get_ahp_flag();
6403 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
6405 gen_helper_vfp_fcvt_f32_to_f16(tcg_rd
, tcg_rn
, fpst
, ahp
);
6406 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
6407 write_fp_sreg(s
, rd
, tcg_rd
);
6408 tcg_temp_free_i32(tcg_rd
);
6409 tcg_temp_free_i32(ahp
);
6410 tcg_temp_free_ptr(fpst
);
6412 tcg_temp_free_i32(tcg_rn
);
6417 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
6418 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
6420 /* Double to single */
6421 gen_helper_vfp_fcvtsd(tcg_rd
, tcg_rn
, cpu_env
);
6423 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
6424 TCGv_i32 ahp
= get_ahp_flag();
6425 /* Double to half */
6426 gen_helper_vfp_fcvt_f64_to_f16(tcg_rd
, tcg_rn
, fpst
, ahp
);
6427 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
6428 tcg_temp_free_ptr(fpst
);
6429 tcg_temp_free_i32(ahp
);
6431 write_fp_sreg(s
, rd
, tcg_rd
);
6432 tcg_temp_free_i32(tcg_rd
);
6433 tcg_temp_free_i64(tcg_rn
);
6438 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
6439 TCGv_ptr tcg_fpst
= fpstatus_ptr(FPST_FPCR
);
6440 TCGv_i32 tcg_ahp
= get_ahp_flag();
6441 tcg_gen_ext16u_i32(tcg_rn
, tcg_rn
);
6443 /* Half to single */
6444 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
6445 gen_helper_vfp_fcvt_f16_to_f32(tcg_rd
, tcg_rn
, tcg_fpst
, tcg_ahp
);
6446 write_fp_sreg(s
, rd
, tcg_rd
);
6447 tcg_temp_free_i32(tcg_rd
);
6449 /* Half to double */
6450 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
6451 gen_helper_vfp_fcvt_f16_to_f64(tcg_rd
, tcg_rn
, tcg_fpst
, tcg_ahp
);
6452 write_fp_dreg(s
, rd
, tcg_rd
);
6453 tcg_temp_free_i64(tcg_rd
);
6455 tcg_temp_free_i32(tcg_rn
);
6456 tcg_temp_free_ptr(tcg_fpst
);
6457 tcg_temp_free_i32(tcg_ahp
);
6465 /* Floating point data-processing (1 source)
6466 * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
6467 * +---+---+---+-----------+------+---+--------+-----------+------+------+
6468 * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
6469 * +---+---+---+-----------+------+---+--------+-----------+------+------+
6471 static void disas_fp_1src(DisasContext
*s
, uint32_t insn
)
6473 int mos
= extract32(insn
, 29, 3);
6474 int type
= extract32(insn
, 22, 2);
6475 int opcode
= extract32(insn
, 15, 6);
6476 int rn
= extract32(insn
, 5, 5);
6477 int rd
= extract32(insn
, 0, 5);
6480 goto do_unallocated
;
6484 case 0x4: case 0x5: case 0x7:
6486 /* FCVT between half, single and double precision */
6487 int dtype
= extract32(opcode
, 0, 2);
6488 if (type
== 2 || dtype
== type
) {
6489 goto do_unallocated
;
6491 if (!fp_access_check(s
)) {
6495 handle_fp_fcvt(s
, opcode
, rd
, rn
, dtype
, type
);
6499 case 0x10 ... 0x13: /* FRINT{32,64}{X,Z} */
6500 if (type
> 1 || !dc_isar_feature(aa64_frint
, s
)) {
6501 goto do_unallocated
;
6507 /* 32-to-32 and 64-to-64 ops */
6510 if (!fp_access_check(s
)) {
6513 handle_fp_1src_single(s
, opcode
, rd
, rn
);
6516 if (!fp_access_check(s
)) {
6519 handle_fp_1src_double(s
, opcode
, rd
, rn
);
6522 if (!dc_isar_feature(aa64_fp16
, s
)) {
6523 goto do_unallocated
;
6526 if (!fp_access_check(s
)) {
6529 handle_fp_1src_half(s
, opcode
, rd
, rn
);
6532 goto do_unallocated
;
6539 if (!dc_isar_feature(aa64_bf16
, s
)) {
6540 goto do_unallocated
;
6542 if (!fp_access_check(s
)) {
6545 handle_fp_1src_single(s
, opcode
, rd
, rn
);
6548 goto do_unallocated
;
6554 unallocated_encoding(s
);
6559 /* Floating-point data-processing (2 source) - single precision */
6560 static void handle_fp_2src_single(DisasContext
*s
, int opcode
,
6561 int rd
, int rn
, int rm
)
6568 tcg_res
= tcg_temp_new_i32();
6569 fpst
= fpstatus_ptr(FPST_FPCR
);
6570 tcg_op1
= read_fp_sreg(s
, rn
);
6571 tcg_op2
= read_fp_sreg(s
, rm
);
6574 case 0x0: /* FMUL */
6575 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6577 case 0x1: /* FDIV */
6578 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6580 case 0x2: /* FADD */
6581 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6583 case 0x3: /* FSUB */
6584 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6586 case 0x4: /* FMAX */
6587 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6589 case 0x5: /* FMIN */
6590 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6592 case 0x6: /* FMAXNM */
6593 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6595 case 0x7: /* FMINNM */
6596 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6598 case 0x8: /* FNMUL */
6599 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6600 gen_helper_vfp_negs(tcg_res
, tcg_res
);
6604 write_fp_sreg(s
, rd
, tcg_res
);
6606 tcg_temp_free_ptr(fpst
);
6607 tcg_temp_free_i32(tcg_op1
);
6608 tcg_temp_free_i32(tcg_op2
);
6609 tcg_temp_free_i32(tcg_res
);
6612 /* Floating-point data-processing (2 source) - double precision */
6613 static void handle_fp_2src_double(DisasContext
*s
, int opcode
,
6614 int rd
, int rn
, int rm
)
6621 tcg_res
= tcg_temp_new_i64();
6622 fpst
= fpstatus_ptr(FPST_FPCR
);
6623 tcg_op1
= read_fp_dreg(s
, rn
);
6624 tcg_op2
= read_fp_dreg(s
, rm
);
6627 case 0x0: /* FMUL */
6628 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6630 case 0x1: /* FDIV */
6631 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6633 case 0x2: /* FADD */
6634 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6636 case 0x3: /* FSUB */
6637 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6639 case 0x4: /* FMAX */
6640 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6642 case 0x5: /* FMIN */
6643 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6645 case 0x6: /* FMAXNM */
6646 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6648 case 0x7: /* FMINNM */
6649 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6651 case 0x8: /* FNMUL */
6652 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6653 gen_helper_vfp_negd(tcg_res
, tcg_res
);
6657 write_fp_dreg(s
, rd
, tcg_res
);
6659 tcg_temp_free_ptr(fpst
);
6660 tcg_temp_free_i64(tcg_op1
);
6661 tcg_temp_free_i64(tcg_op2
);
6662 tcg_temp_free_i64(tcg_res
);
6665 /* Floating-point data-processing (2 source) - half precision */
6666 static void handle_fp_2src_half(DisasContext
*s
, int opcode
,
6667 int rd
, int rn
, int rm
)
6674 tcg_res
= tcg_temp_new_i32();
6675 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
6676 tcg_op1
= read_fp_hreg(s
, rn
);
6677 tcg_op2
= read_fp_hreg(s
, rm
);
6680 case 0x0: /* FMUL */
6681 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6683 case 0x1: /* FDIV */
6684 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6686 case 0x2: /* FADD */
6687 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6689 case 0x3: /* FSUB */
6690 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6692 case 0x4: /* FMAX */
6693 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6695 case 0x5: /* FMIN */
6696 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6698 case 0x6: /* FMAXNM */
6699 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6701 case 0x7: /* FMINNM */
6702 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6704 case 0x8: /* FNMUL */
6705 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6706 tcg_gen_xori_i32(tcg_res
, tcg_res
, 0x8000);
6709 g_assert_not_reached();
6712 write_fp_sreg(s
, rd
, tcg_res
);
6714 tcg_temp_free_ptr(fpst
);
6715 tcg_temp_free_i32(tcg_op1
);
6716 tcg_temp_free_i32(tcg_op2
);
6717 tcg_temp_free_i32(tcg_res
);
6720 /* Floating point data-processing (2 source)
6721 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
6722 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
6723 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
6724 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
6726 static void disas_fp_2src(DisasContext
*s
, uint32_t insn
)
6728 int mos
= extract32(insn
, 29, 3);
6729 int type
= extract32(insn
, 22, 2);
6730 int rd
= extract32(insn
, 0, 5);
6731 int rn
= extract32(insn
, 5, 5);
6732 int rm
= extract32(insn
, 16, 5);
6733 int opcode
= extract32(insn
, 12, 4);
6735 if (opcode
> 8 || mos
) {
6736 unallocated_encoding(s
);
6742 if (!fp_access_check(s
)) {
6745 handle_fp_2src_single(s
, opcode
, rd
, rn
, rm
);
6748 if (!fp_access_check(s
)) {
6751 handle_fp_2src_double(s
, opcode
, rd
, rn
, rm
);
6754 if (!dc_isar_feature(aa64_fp16
, s
)) {
6755 unallocated_encoding(s
);
6758 if (!fp_access_check(s
)) {
6761 handle_fp_2src_half(s
, opcode
, rd
, rn
, rm
);
6764 unallocated_encoding(s
);
6768 /* Floating-point data-processing (3 source) - single precision */
6769 static void handle_fp_3src_single(DisasContext
*s
, bool o0
, bool o1
,
6770 int rd
, int rn
, int rm
, int ra
)
6772 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
6773 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6774 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
6776 tcg_op1
= read_fp_sreg(s
, rn
);
6777 tcg_op2
= read_fp_sreg(s
, rm
);
6778 tcg_op3
= read_fp_sreg(s
, ra
);
6780 /* These are fused multiply-add, and must be done as one
6781 * floating point operation with no rounding between the
6782 * multiplication and addition steps.
6783 * NB that doing the negations here as separate steps is
6784 * correct : an input NaN should come out with its sign bit
6785 * flipped if it is a negated-input.
6788 gen_helper_vfp_negs(tcg_op3
, tcg_op3
);
6792 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
6795 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6797 write_fp_sreg(s
, rd
, tcg_res
);
6799 tcg_temp_free_ptr(fpst
);
6800 tcg_temp_free_i32(tcg_op1
);
6801 tcg_temp_free_i32(tcg_op2
);
6802 tcg_temp_free_i32(tcg_op3
);
6803 tcg_temp_free_i32(tcg_res
);
6806 /* Floating-point data-processing (3 source) - double precision */
6807 static void handle_fp_3src_double(DisasContext
*s
, bool o0
, bool o1
,
6808 int rd
, int rn
, int rm
, int ra
)
6810 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
;
6811 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6812 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
6814 tcg_op1
= read_fp_dreg(s
, rn
);
6815 tcg_op2
= read_fp_dreg(s
, rm
);
6816 tcg_op3
= read_fp_dreg(s
, ra
);
6818 /* These are fused multiply-add, and must be done as one
6819 * floating point operation with no rounding between the
6820 * multiplication and addition steps.
6821 * NB that doing the negations here as separate steps is
6822 * correct : an input NaN should come out with its sign bit
6823 * flipped if it is a negated-input.
6826 gen_helper_vfp_negd(tcg_op3
, tcg_op3
);
6830 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
6833 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6835 write_fp_dreg(s
, rd
, tcg_res
);
6837 tcg_temp_free_ptr(fpst
);
6838 tcg_temp_free_i64(tcg_op1
);
6839 tcg_temp_free_i64(tcg_op2
);
6840 tcg_temp_free_i64(tcg_op3
);
6841 tcg_temp_free_i64(tcg_res
);
6844 /* Floating-point data-processing (3 source) - half precision */
6845 static void handle_fp_3src_half(DisasContext
*s
, bool o0
, bool o1
,
6846 int rd
, int rn
, int rm
, int ra
)
6848 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
6849 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6850 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR_F16
);
6852 tcg_op1
= read_fp_hreg(s
, rn
);
6853 tcg_op2
= read_fp_hreg(s
, rm
);
6854 tcg_op3
= read_fp_hreg(s
, ra
);
6856 /* These are fused multiply-add, and must be done as one
6857 * floating point operation with no rounding between the
6858 * multiplication and addition steps.
6859 * NB that doing the negations here as separate steps is
6860 * correct : an input NaN should come out with its sign bit
6861 * flipped if it is a negated-input.
6864 tcg_gen_xori_i32(tcg_op3
, tcg_op3
, 0x8000);
6868 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
6871 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6873 write_fp_sreg(s
, rd
, tcg_res
);
6875 tcg_temp_free_ptr(fpst
);
6876 tcg_temp_free_i32(tcg_op1
);
6877 tcg_temp_free_i32(tcg_op2
);
6878 tcg_temp_free_i32(tcg_op3
);
6879 tcg_temp_free_i32(tcg_res
);
6882 /* Floating point data-processing (3 source)
6883 * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
6884 * +---+---+---+-----------+------+----+------+----+------+------+------+
6885 * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
6886 * +---+---+---+-----------+------+----+------+----+------+------+------+
6888 static void disas_fp_3src(DisasContext
*s
, uint32_t insn
)
6890 int mos
= extract32(insn
, 29, 3);
6891 int type
= extract32(insn
, 22, 2);
6892 int rd
= extract32(insn
, 0, 5);
6893 int rn
= extract32(insn
, 5, 5);
6894 int ra
= extract32(insn
, 10, 5);
6895 int rm
= extract32(insn
, 16, 5);
6896 bool o0
= extract32(insn
, 15, 1);
6897 bool o1
= extract32(insn
, 21, 1);
6900 unallocated_encoding(s
);
6906 if (!fp_access_check(s
)) {
6909 handle_fp_3src_single(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6912 if (!fp_access_check(s
)) {
6915 handle_fp_3src_double(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6918 if (!dc_isar_feature(aa64_fp16
, s
)) {
6919 unallocated_encoding(s
);
6922 if (!fp_access_check(s
)) {
6925 handle_fp_3src_half(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6928 unallocated_encoding(s
);
6932 /* Floating point immediate
6933 * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
6934 * +---+---+---+-----------+------+---+------------+-------+------+------+
6935 * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
6936 * +---+---+---+-----------+------+---+------------+-------+------+------+
6938 static void disas_fp_imm(DisasContext
*s
, uint32_t insn
)
6940 int rd
= extract32(insn
, 0, 5);
6941 int imm5
= extract32(insn
, 5, 5);
6942 int imm8
= extract32(insn
, 13, 8);
6943 int type
= extract32(insn
, 22, 2);
6944 int mos
= extract32(insn
, 29, 3);
6950 unallocated_encoding(s
);
6963 if (dc_isar_feature(aa64_fp16
, s
)) {
6968 unallocated_encoding(s
);
6972 if (!fp_access_check(s
)) {
6976 imm
= vfp_expand_imm(sz
, imm8
);
6978 tcg_res
= tcg_const_i64(imm
);
6979 write_fp_dreg(s
, rd
, tcg_res
);
6980 tcg_temp_free_i64(tcg_res
);
6983 /* Handle floating point <=> fixed point conversions. Note that we can
6984 * also deal with fp <=> integer conversions as a special case (scale == 64)
6985 * OPTME: consider handling that special case specially or at least skipping
6986 * the call to scalbn in the helpers for zero shifts.
6988 static void handle_fpfpcvt(DisasContext
*s
, int rd
, int rn
, int opcode
,
6989 bool itof
, int rmode
, int scale
, int sf
, int type
)
6991 bool is_signed
= !(opcode
& 1);
6992 TCGv_ptr tcg_fpstatus
;
6993 TCGv_i32 tcg_shift
, tcg_single
;
6994 TCGv_i64 tcg_double
;
6996 tcg_fpstatus
= fpstatus_ptr(type
== 3 ? FPST_FPCR_F16
: FPST_FPCR
);
6998 tcg_shift
= tcg_const_i32(64 - scale
);
7001 TCGv_i64 tcg_int
= cpu_reg(s
, rn
);
7003 TCGv_i64 tcg_extend
= new_tmp_a64(s
);
7006 tcg_gen_ext32s_i64(tcg_extend
, tcg_int
);
7008 tcg_gen_ext32u_i64(tcg_extend
, tcg_int
);
7011 tcg_int
= tcg_extend
;
7015 case 1: /* float64 */
7016 tcg_double
= tcg_temp_new_i64();
7018 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
7019 tcg_shift
, tcg_fpstatus
);
7021 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
7022 tcg_shift
, tcg_fpstatus
);
7024 write_fp_dreg(s
, rd
, tcg_double
);
7025 tcg_temp_free_i64(tcg_double
);
7028 case 0: /* float32 */
7029 tcg_single
= tcg_temp_new_i32();
7031 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
7032 tcg_shift
, tcg_fpstatus
);
7034 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
7035 tcg_shift
, tcg_fpstatus
);
7037 write_fp_sreg(s
, rd
, tcg_single
);
7038 tcg_temp_free_i32(tcg_single
);
7041 case 3: /* float16 */
7042 tcg_single
= tcg_temp_new_i32();
7044 gen_helper_vfp_sqtoh(tcg_single
, tcg_int
,
7045 tcg_shift
, tcg_fpstatus
);
7047 gen_helper_vfp_uqtoh(tcg_single
, tcg_int
,
7048 tcg_shift
, tcg_fpstatus
);
7050 write_fp_sreg(s
, rd
, tcg_single
);
7051 tcg_temp_free_i32(tcg_single
);
7055 g_assert_not_reached();
7058 TCGv_i64 tcg_int
= cpu_reg(s
, rd
);
7061 if (extract32(opcode
, 2, 1)) {
7062 /* There are too many rounding modes to all fit into rmode,
7063 * so FCVTA[US] is a special case.
7065 rmode
= FPROUNDING_TIEAWAY
;
7068 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
7070 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
7073 case 1: /* float64 */
7074 tcg_double
= read_fp_dreg(s
, rn
);
7077 gen_helper_vfp_tosld(tcg_int
, tcg_double
,
7078 tcg_shift
, tcg_fpstatus
);
7080 gen_helper_vfp_tosqd(tcg_int
, tcg_double
,
7081 tcg_shift
, tcg_fpstatus
);
7085 gen_helper_vfp_tould(tcg_int
, tcg_double
,
7086 tcg_shift
, tcg_fpstatus
);
7088 gen_helper_vfp_touqd(tcg_int
, tcg_double
,
7089 tcg_shift
, tcg_fpstatus
);
7093 tcg_gen_ext32u_i64(tcg_int
, tcg_int
);
7095 tcg_temp_free_i64(tcg_double
);
7098 case 0: /* float32 */
7099 tcg_single
= read_fp_sreg(s
, rn
);
7102 gen_helper_vfp_tosqs(tcg_int
, tcg_single
,
7103 tcg_shift
, tcg_fpstatus
);
7105 gen_helper_vfp_touqs(tcg_int
, tcg_single
,
7106 tcg_shift
, tcg_fpstatus
);
7109 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
7111 gen_helper_vfp_tosls(tcg_dest
, tcg_single
,
7112 tcg_shift
, tcg_fpstatus
);
7114 gen_helper_vfp_touls(tcg_dest
, tcg_single
,
7115 tcg_shift
, tcg_fpstatus
);
7117 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
7118 tcg_temp_free_i32(tcg_dest
);
7120 tcg_temp_free_i32(tcg_single
);
7123 case 3: /* float16 */
7124 tcg_single
= read_fp_sreg(s
, rn
);
7127 gen_helper_vfp_tosqh(tcg_int
, tcg_single
,
7128 tcg_shift
, tcg_fpstatus
);
7130 gen_helper_vfp_touqh(tcg_int
, tcg_single
,
7131 tcg_shift
, tcg_fpstatus
);
7134 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
7136 gen_helper_vfp_toslh(tcg_dest
, tcg_single
,
7137 tcg_shift
, tcg_fpstatus
);
7139 gen_helper_vfp_toulh(tcg_dest
, tcg_single
,
7140 tcg_shift
, tcg_fpstatus
);
7142 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
7143 tcg_temp_free_i32(tcg_dest
);
7145 tcg_temp_free_i32(tcg_single
);
7149 g_assert_not_reached();
7152 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
7153 tcg_temp_free_i32(tcg_rmode
);
7156 tcg_temp_free_ptr(tcg_fpstatus
);
7157 tcg_temp_free_i32(tcg_shift
);
7160 /* Floating point <-> fixed point conversions
7161 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
7162 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
7163 * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
7164 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
7166 static void disas_fp_fixed_conv(DisasContext
*s
, uint32_t insn
)
7168 int rd
= extract32(insn
, 0, 5);
7169 int rn
= extract32(insn
, 5, 5);
7170 int scale
= extract32(insn
, 10, 6);
7171 int opcode
= extract32(insn
, 16, 3);
7172 int rmode
= extract32(insn
, 19, 2);
7173 int type
= extract32(insn
, 22, 2);
7174 bool sbit
= extract32(insn
, 29, 1);
7175 bool sf
= extract32(insn
, 31, 1);
7178 if (sbit
|| (!sf
&& scale
< 32)) {
7179 unallocated_encoding(s
);
7184 case 0: /* float32 */
7185 case 1: /* float64 */
7187 case 3: /* float16 */
7188 if (dc_isar_feature(aa64_fp16
, s
)) {
7193 unallocated_encoding(s
);
7197 switch ((rmode
<< 3) | opcode
) {
7198 case 0x2: /* SCVTF */
7199 case 0x3: /* UCVTF */
7202 case 0x18: /* FCVTZS */
7203 case 0x19: /* FCVTZU */
7207 unallocated_encoding(s
);
7211 if (!fp_access_check(s
)) {
7215 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, FPROUNDING_ZERO
, scale
, sf
, type
);
7218 static void handle_fmov(DisasContext
*s
, int rd
, int rn
, int type
, bool itof
)
7220 /* FMOV: gpr to or from float, double, or top half of quad fp reg,
7221 * without conversion.
7225 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
7231 tmp
= tcg_temp_new_i64();
7232 tcg_gen_ext32u_i64(tmp
, tcg_rn
);
7233 write_fp_dreg(s
, rd
, tmp
);
7234 tcg_temp_free_i64(tmp
);
7238 write_fp_dreg(s
, rd
, tcg_rn
);
7241 /* 64 bit to top half. */
7242 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_hi_offset(s
, rd
));
7243 clear_vec_high(s
, true, rd
);
7247 tmp
= tcg_temp_new_i64();
7248 tcg_gen_ext16u_i64(tmp
, tcg_rn
);
7249 write_fp_dreg(s
, rd
, tmp
);
7250 tcg_temp_free_i64(tmp
);
7253 g_assert_not_reached();
7256 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
7261 tcg_gen_ld32u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_32
));
7265 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_64
));
7268 /* 64 bits from top half */
7269 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_hi_offset(s
, rn
));
7273 tcg_gen_ld16u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_16
));
7276 g_assert_not_reached();
7281 static void handle_fjcvtzs(DisasContext
*s
, int rd
, int rn
)
7283 TCGv_i64 t
= read_fp_dreg(s
, rn
);
7284 TCGv_ptr fpstatus
= fpstatus_ptr(FPST_FPCR
);
7286 gen_helper_fjcvtzs(t
, t
, fpstatus
);
7288 tcg_temp_free_ptr(fpstatus
);
7290 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), t
);
7291 tcg_gen_extrh_i64_i32(cpu_ZF
, t
);
7292 tcg_gen_movi_i32(cpu_CF
, 0);
7293 tcg_gen_movi_i32(cpu_NF
, 0);
7294 tcg_gen_movi_i32(cpu_VF
, 0);
7296 tcg_temp_free_i64(t
);
7299 /* Floating point <-> integer conversions
7300 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
7301 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
7302 * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
7303 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
7305 static void disas_fp_int_conv(DisasContext
*s
, uint32_t insn
)
7307 int rd
= extract32(insn
, 0, 5);
7308 int rn
= extract32(insn
, 5, 5);
7309 int opcode
= extract32(insn
, 16, 3);
7310 int rmode
= extract32(insn
, 19, 2);
7311 int type
= extract32(insn
, 22, 2);
7312 bool sbit
= extract32(insn
, 29, 1);
7313 bool sf
= extract32(insn
, 31, 1);
7317 goto do_unallocated
;
7325 case 4: /* FCVTAS */
7326 case 5: /* FCVTAU */
7328 goto do_unallocated
;
7331 case 0: /* FCVT[NPMZ]S */
7332 case 1: /* FCVT[NPMZ]U */
7334 case 0: /* float32 */
7335 case 1: /* float64 */
7337 case 3: /* float16 */
7338 if (!dc_isar_feature(aa64_fp16
, s
)) {
7339 goto do_unallocated
;
7343 goto do_unallocated
;
7345 if (!fp_access_check(s
)) {
7348 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, rmode
, 64, sf
, type
);
7352 switch (sf
<< 7 | type
<< 5 | rmode
<< 3 | opcode
) {
7353 case 0b01100110: /* FMOV half <-> 32-bit int */
7355 case 0b11100110: /* FMOV half <-> 64-bit int */
7357 if (!dc_isar_feature(aa64_fp16
, s
)) {
7358 goto do_unallocated
;
7361 case 0b00000110: /* FMOV 32-bit */
7363 case 0b10100110: /* FMOV 64-bit */
7365 case 0b11001110: /* FMOV top half of 128-bit */
7367 if (!fp_access_check(s
)) {
7371 handle_fmov(s
, rd
, rn
, type
, itof
);
7374 case 0b00111110: /* FJCVTZS */
7375 if (!dc_isar_feature(aa64_jscvt
, s
)) {
7376 goto do_unallocated
;
7377 } else if (fp_access_check(s
)) {
7378 handle_fjcvtzs(s
, rd
, rn
);
7384 unallocated_encoding(s
);
7391 /* FP-specific subcases of table C3-6 (SIMD and FP data processing)
7392 * 31 30 29 28 25 24 0
7393 * +---+---+---+---------+-----------------------------+
7394 * | | 0 | | 1 1 1 1 | |
7395 * +---+---+---+---------+-----------------------------+
7397 static void disas_data_proc_fp(DisasContext
*s
, uint32_t insn
)
7399 if (extract32(insn
, 24, 1)) {
7400 /* Floating point data-processing (3 source) */
7401 disas_fp_3src(s
, insn
);
7402 } else if (extract32(insn
, 21, 1) == 0) {
7403 /* Floating point to fixed point conversions */
7404 disas_fp_fixed_conv(s
, insn
);
7406 switch (extract32(insn
, 10, 2)) {
7408 /* Floating point conditional compare */
7409 disas_fp_ccomp(s
, insn
);
7412 /* Floating point data-processing (2 source) */
7413 disas_fp_2src(s
, insn
);
7416 /* Floating point conditional select */
7417 disas_fp_csel(s
, insn
);
7420 switch (ctz32(extract32(insn
, 12, 4))) {
7421 case 0: /* [15:12] == xxx1 */
7422 /* Floating point immediate */
7423 disas_fp_imm(s
, insn
);
7425 case 1: /* [15:12] == xx10 */
7426 /* Floating point compare */
7427 disas_fp_compare(s
, insn
);
7429 case 2: /* [15:12] == x100 */
7430 /* Floating point data-processing (1 source) */
7431 disas_fp_1src(s
, insn
);
7433 case 3: /* [15:12] == 1000 */
7434 unallocated_encoding(s
);
7436 default: /* [15:12] == 0000 */
7437 /* Floating point <-> integer conversions */
7438 disas_fp_int_conv(s
, insn
);
7446 static void do_ext64(DisasContext
*s
, TCGv_i64 tcg_left
, TCGv_i64 tcg_right
,
7449 /* Extract 64 bits from the middle of two concatenated 64 bit
7450 * vector register slices left:right. The extracted bits start
7451 * at 'pos' bits into the right (least significant) side.
7452 * We return the result in tcg_right, and guarantee not to
7455 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
7456 assert(pos
> 0 && pos
< 64);
7458 tcg_gen_shri_i64(tcg_right
, tcg_right
, pos
);
7459 tcg_gen_shli_i64(tcg_tmp
, tcg_left
, 64 - pos
);
7460 tcg_gen_or_i64(tcg_right
, tcg_right
, tcg_tmp
);
7462 tcg_temp_free_i64(tcg_tmp
);
7466 * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
7467 * +---+---+-------------+-----+---+------+---+------+---+------+------+
7468 * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
7469 * +---+---+-------------+-----+---+------+---+------+---+------+------+
7471 static void disas_simd_ext(DisasContext
*s
, uint32_t insn
)
7473 int is_q
= extract32(insn
, 30, 1);
7474 int op2
= extract32(insn
, 22, 2);
7475 int imm4
= extract32(insn
, 11, 4);
7476 int rm
= extract32(insn
, 16, 5);
7477 int rn
= extract32(insn
, 5, 5);
7478 int rd
= extract32(insn
, 0, 5);
7479 int pos
= imm4
<< 3;
7480 TCGv_i64 tcg_resl
, tcg_resh
;
7482 if (op2
!= 0 || (!is_q
&& extract32(imm4
, 3, 1))) {
7483 unallocated_encoding(s
);
7487 if (!fp_access_check(s
)) {
7491 tcg_resh
= tcg_temp_new_i64();
7492 tcg_resl
= tcg_temp_new_i64();
7494 /* Vd gets bits starting at pos bits into Vm:Vn. This is
7495 * either extracting 128 bits from a 128:128 concatenation, or
7496 * extracting 64 bits from a 64:64 concatenation.
7499 read_vec_element(s
, tcg_resl
, rn
, 0, MO_64
);
7501 read_vec_element(s
, tcg_resh
, rm
, 0, MO_64
);
7502 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
7510 EltPosns eltposns
[] = { {rn
, 0}, {rn
, 1}, {rm
, 0}, {rm
, 1} };
7511 EltPosns
*elt
= eltposns
;
7518 read_vec_element(s
, tcg_resl
, elt
->reg
, elt
->elt
, MO_64
);
7520 read_vec_element(s
, tcg_resh
, elt
->reg
, elt
->elt
, MO_64
);
7523 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
7524 tcg_hh
= tcg_temp_new_i64();
7525 read_vec_element(s
, tcg_hh
, elt
->reg
, elt
->elt
, MO_64
);
7526 do_ext64(s
, tcg_hh
, tcg_resh
, pos
);
7527 tcg_temp_free_i64(tcg_hh
);
7531 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
7532 tcg_temp_free_i64(tcg_resl
);
7534 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
7536 tcg_temp_free_i64(tcg_resh
);
7537 clear_vec_high(s
, is_q
, rd
);
7541 * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
7542 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
7543 * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
7544 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
7546 static void disas_simd_tb(DisasContext
*s
, uint32_t insn
)
7548 int op2
= extract32(insn
, 22, 2);
7549 int is_q
= extract32(insn
, 30, 1);
7550 int rm
= extract32(insn
, 16, 5);
7551 int rn
= extract32(insn
, 5, 5);
7552 int rd
= extract32(insn
, 0, 5);
7553 int is_tbx
= extract32(insn
, 12, 1);
7554 int len
= (extract32(insn
, 13, 2) + 1) * 16;
7557 unallocated_encoding(s
);
7561 if (!fp_access_check(s
)) {
7565 tcg_gen_gvec_2_ptr(vec_full_reg_offset(s
, rd
),
7566 vec_full_reg_offset(s
, rm
), cpu_env
,
7567 is_q
? 16 : 8, vec_full_reg_size(s
),
7568 (len
<< 6) | (is_tbx
<< 5) | rn
,
7569 gen_helper_simd_tblx
);
7573 * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
7574 * +---+---+-------------+------+---+------+---+------------------+------+
7575 * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
7576 * +---+---+-------------+------+---+------+---+------------------+------+
7578 static void disas_simd_zip_trn(DisasContext
*s
, uint32_t insn
)
7580 int rd
= extract32(insn
, 0, 5);
7581 int rn
= extract32(insn
, 5, 5);
7582 int rm
= extract32(insn
, 16, 5);
7583 int size
= extract32(insn
, 22, 2);
7584 /* opc field bits [1:0] indicate ZIP/UZP/TRN;
7585 * bit 2 indicates 1 vs 2 variant of the insn.
7587 int opcode
= extract32(insn
, 12, 2);
7588 bool part
= extract32(insn
, 14, 1);
7589 bool is_q
= extract32(insn
, 30, 1);
7590 int esize
= 8 << size
;
7592 int datasize
= is_q
? 128 : 64;
7593 int elements
= datasize
/ esize
;
7594 TCGv_i64 tcg_res
, tcg_resl
, tcg_resh
;
7596 if (opcode
== 0 || (size
== 3 && !is_q
)) {
7597 unallocated_encoding(s
);
7601 if (!fp_access_check(s
)) {
7605 tcg_resl
= tcg_const_i64(0);
7606 tcg_resh
= is_q
? tcg_const_i64(0) : NULL
;
7607 tcg_res
= tcg_temp_new_i64();
7609 for (i
= 0; i
< elements
; i
++) {
7611 case 1: /* UZP1/2 */
7613 int midpoint
= elements
/ 2;
7615 read_vec_element(s
, tcg_res
, rn
, 2 * i
+ part
, size
);
7617 read_vec_element(s
, tcg_res
, rm
,
7618 2 * (i
- midpoint
) + part
, size
);
7622 case 2: /* TRN1/2 */
7624 read_vec_element(s
, tcg_res
, rm
, (i
& ~1) + part
, size
);
7626 read_vec_element(s
, tcg_res
, rn
, (i
& ~1) + part
, size
);
7629 case 3: /* ZIP1/2 */
7631 int base
= part
* elements
/ 2;
7633 read_vec_element(s
, tcg_res
, rm
, base
+ (i
>> 1), size
);
7635 read_vec_element(s
, tcg_res
, rn
, base
+ (i
>> 1), size
);
7640 g_assert_not_reached();
7645 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
);
7646 tcg_gen_or_i64(tcg_resl
, tcg_resl
, tcg_res
);
7648 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
- 64);
7649 tcg_gen_or_i64(tcg_resh
, tcg_resh
, tcg_res
);
7653 tcg_temp_free_i64(tcg_res
);
7655 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
7656 tcg_temp_free_i64(tcg_resl
);
7659 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
7660 tcg_temp_free_i64(tcg_resh
);
7662 clear_vec_high(s
, is_q
, rd
);
7666 * do_reduction_op helper
7668 * This mirrors the Reduce() pseudocode in the ARM ARM. It is
7669 * important for correct NaN propagation that we do these
7670 * operations in exactly the order specified by the pseudocode.
7672 * This is a recursive function, TCG temps should be freed by the
7673 * calling function once it is done with the values.
7675 static TCGv_i32
do_reduction_op(DisasContext
*s
, int fpopcode
, int rn
,
7676 int esize
, int size
, int vmap
, TCGv_ptr fpst
)
7678 if (esize
== size
) {
7680 MemOp msize
= esize
== 16 ? MO_16
: MO_32
;
7683 /* We should have one register left here */
7684 assert(ctpop8(vmap
) == 1);
7685 element
= ctz32(vmap
);
7686 assert(element
< 8);
7688 tcg_elem
= tcg_temp_new_i32();
7689 read_vec_element_i32(s
, tcg_elem
, rn
, element
, msize
);
7692 int bits
= size
/ 2;
7693 int shift
= ctpop8(vmap
) / 2;
7694 int vmap_lo
= (vmap
>> shift
) & vmap
;
7695 int vmap_hi
= (vmap
& ~vmap_lo
);
7696 TCGv_i32 tcg_hi
, tcg_lo
, tcg_res
;
7698 tcg_hi
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_hi
, fpst
);
7699 tcg_lo
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_lo
, fpst
);
7700 tcg_res
= tcg_temp_new_i32();
7703 case 0x0c: /* fmaxnmv half-precision */
7704 gen_helper_advsimd_maxnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7706 case 0x0f: /* fmaxv half-precision */
7707 gen_helper_advsimd_maxh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7709 case 0x1c: /* fminnmv half-precision */
7710 gen_helper_advsimd_minnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7712 case 0x1f: /* fminv half-precision */
7713 gen_helper_advsimd_minh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7715 case 0x2c: /* fmaxnmv */
7716 gen_helper_vfp_maxnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7718 case 0x2f: /* fmaxv */
7719 gen_helper_vfp_maxs(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7721 case 0x3c: /* fminnmv */
7722 gen_helper_vfp_minnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7724 case 0x3f: /* fminv */
7725 gen_helper_vfp_mins(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7728 g_assert_not_reached();
7731 tcg_temp_free_i32(tcg_hi
);
7732 tcg_temp_free_i32(tcg_lo
);
7737 /* AdvSIMD across lanes
7738 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
7739 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
7740 * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
7741 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
7743 static void disas_simd_across_lanes(DisasContext
*s
, uint32_t insn
)
7745 int rd
= extract32(insn
, 0, 5);
7746 int rn
= extract32(insn
, 5, 5);
7747 int size
= extract32(insn
, 22, 2);
7748 int opcode
= extract32(insn
, 12, 5);
7749 bool is_q
= extract32(insn
, 30, 1);
7750 bool is_u
= extract32(insn
, 29, 1);
7752 bool is_min
= false;
7756 TCGv_i64 tcg_res
, tcg_elt
;
7759 case 0x1b: /* ADDV */
7761 unallocated_encoding(s
);
7765 case 0x3: /* SADDLV, UADDLV */
7766 case 0xa: /* SMAXV, UMAXV */
7767 case 0x1a: /* SMINV, UMINV */
7768 if (size
== 3 || (size
== 2 && !is_q
)) {
7769 unallocated_encoding(s
);
7773 case 0xc: /* FMAXNMV, FMINNMV */
7774 case 0xf: /* FMAXV, FMINV */
7775 /* Bit 1 of size field encodes min vs max and the actual size
7776 * depends on the encoding of the U bit. If not set (and FP16
7777 * enabled) then we do half-precision float instead of single
7780 is_min
= extract32(size
, 1, 1);
7782 if (!is_u
&& dc_isar_feature(aa64_fp16
, s
)) {
7784 } else if (!is_u
|| !is_q
|| extract32(size
, 0, 1)) {
7785 unallocated_encoding(s
);
7792 unallocated_encoding(s
);
7796 if (!fp_access_check(s
)) {
7801 elements
= (is_q
? 128 : 64) / esize
;
7803 tcg_res
= tcg_temp_new_i64();
7804 tcg_elt
= tcg_temp_new_i64();
7806 /* These instructions operate across all lanes of a vector
7807 * to produce a single result. We can guarantee that a 64
7808 * bit intermediate is sufficient:
7809 * + for [US]ADDLV the maximum element size is 32 bits, and
7810 * the result type is 64 bits
7811 * + for FMAX*V, FMIN*V, ADDV the intermediate type is the
7812 * same as the element size, which is 32 bits at most
7813 * For the integer operations we can choose to work at 64
7814 * or 32 bits and truncate at the end; for simplicity
7815 * we use 64 bits always. The floating point
7816 * ops do require 32 bit intermediates, though.
7819 read_vec_element(s
, tcg_res
, rn
, 0, size
| (is_u
? 0 : MO_SIGN
));
7821 for (i
= 1; i
< elements
; i
++) {
7822 read_vec_element(s
, tcg_elt
, rn
, i
, size
| (is_u
? 0 : MO_SIGN
));
7825 case 0x03: /* SADDLV / UADDLV */
7826 case 0x1b: /* ADDV */
7827 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_elt
);
7829 case 0x0a: /* SMAXV / UMAXV */
7831 tcg_gen_umax_i64(tcg_res
, tcg_res
, tcg_elt
);
7833 tcg_gen_smax_i64(tcg_res
, tcg_res
, tcg_elt
);
7836 case 0x1a: /* SMINV / UMINV */
7838 tcg_gen_umin_i64(tcg_res
, tcg_res
, tcg_elt
);
7840 tcg_gen_smin_i64(tcg_res
, tcg_res
, tcg_elt
);
7844 g_assert_not_reached();
7849 /* Floating point vector reduction ops which work across 32
7850 * bit (single) or 16 bit (half-precision) intermediates.
7851 * Note that correct NaN propagation requires that we do these
7852 * operations in exactly the order specified by the pseudocode.
7854 TCGv_ptr fpst
= fpstatus_ptr(size
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
7855 int fpopcode
= opcode
| is_min
<< 4 | is_u
<< 5;
7856 int vmap
= (1 << elements
) - 1;
7857 TCGv_i32 tcg_res32
= do_reduction_op(s
, fpopcode
, rn
, esize
,
7858 (is_q
? 128 : 64), vmap
, fpst
);
7859 tcg_gen_extu_i32_i64(tcg_res
, tcg_res32
);
7860 tcg_temp_free_i32(tcg_res32
);
7861 tcg_temp_free_ptr(fpst
);
7864 tcg_temp_free_i64(tcg_elt
);
7866 /* Now truncate the result to the width required for the final output */
7867 if (opcode
== 0x03) {
7868 /* SADDLV, UADDLV: result is 2*esize */
7874 tcg_gen_ext8u_i64(tcg_res
, tcg_res
);
7877 tcg_gen_ext16u_i64(tcg_res
, tcg_res
);
7880 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
7885 g_assert_not_reached();
7888 write_fp_dreg(s
, rd
, tcg_res
);
7889 tcg_temp_free_i64(tcg_res
);
7892 /* DUP (Element, Vector)
7894 * 31 30 29 21 20 16 15 10 9 5 4 0
7895 * +---+---+-------------------+--------+-------------+------+------+
7896 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
7897 * +---+---+-------------------+--------+-------------+------+------+
7899 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7901 static void handle_simd_dupe(DisasContext
*s
, int is_q
, int rd
, int rn
,
7904 int size
= ctz32(imm5
);
7907 if (size
> 3 || (size
== 3 && !is_q
)) {
7908 unallocated_encoding(s
);
7912 if (!fp_access_check(s
)) {
7916 index
= imm5
>> (size
+ 1);
7917 tcg_gen_gvec_dup_mem(size
, vec_full_reg_offset(s
, rd
),
7918 vec_reg_offset(s
, rn
, index
, size
),
7919 is_q
? 16 : 8, vec_full_reg_size(s
));
7922 /* DUP (element, scalar)
7923 * 31 21 20 16 15 10 9 5 4 0
7924 * +-----------------------+--------+-------------+------+------+
7925 * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
7926 * +-----------------------+--------+-------------+------+------+
7928 static void handle_simd_dupes(DisasContext
*s
, int rd
, int rn
,
7931 int size
= ctz32(imm5
);
7936 unallocated_encoding(s
);
7940 if (!fp_access_check(s
)) {
7944 index
= imm5
>> (size
+ 1);
7946 /* This instruction just extracts the specified element and
7947 * zero-extends it into the bottom of the destination register.
7949 tmp
= tcg_temp_new_i64();
7950 read_vec_element(s
, tmp
, rn
, index
, size
);
7951 write_fp_dreg(s
, rd
, tmp
);
7952 tcg_temp_free_i64(tmp
);
7957 * 31 30 29 21 20 16 15 10 9 5 4 0
7958 * +---+---+-------------------+--------+-------------+------+------+
7959 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd |
7960 * +---+---+-------------------+--------+-------------+------+------+
7962 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7964 static void handle_simd_dupg(DisasContext
*s
, int is_q
, int rd
, int rn
,
7967 int size
= ctz32(imm5
);
7968 uint32_t dofs
, oprsz
, maxsz
;
7970 if (size
> 3 || ((size
== 3) && !is_q
)) {
7971 unallocated_encoding(s
);
7975 if (!fp_access_check(s
)) {
7979 dofs
= vec_full_reg_offset(s
, rd
);
7980 oprsz
= is_q
? 16 : 8;
7981 maxsz
= vec_full_reg_size(s
);
7983 tcg_gen_gvec_dup_i64(size
, dofs
, oprsz
, maxsz
, cpu_reg(s
, rn
));
7988 * 31 21 20 16 15 14 11 10 9 5 4 0
7989 * +-----------------------+--------+------------+---+------+------+
7990 * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7991 * +-----------------------+--------+------------+---+------+------+
7993 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7994 * index: encoded in imm5<4:size+1>
7996 static void handle_simd_inse(DisasContext
*s
, int rd
, int rn
,
7999 int size
= ctz32(imm5
);
8000 int src_index
, dst_index
;
8004 unallocated_encoding(s
);
8008 if (!fp_access_check(s
)) {
8012 dst_index
= extract32(imm5
, 1+size
, 5);
8013 src_index
= extract32(imm4
, size
, 4);
8015 tmp
= tcg_temp_new_i64();
8017 read_vec_element(s
, tmp
, rn
, src_index
, size
);
8018 write_vec_element(s
, tmp
, rd
, dst_index
, size
);
8020 tcg_temp_free_i64(tmp
);
8022 /* INS is considered a 128-bit write for SVE. */
8023 clear_vec_high(s
, true, rd
);
8029 * 31 21 20 16 15 10 9 5 4 0
8030 * +-----------------------+--------+-------------+------+------+
8031 * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd |
8032 * +-----------------------+--------+-------------+------+------+
8034 * size: encoded in imm5 (see ARM ARM LowestSetBit())
8035 * index: encoded in imm5<4:size+1>
8037 static void handle_simd_insg(DisasContext
*s
, int rd
, int rn
, int imm5
)
8039 int size
= ctz32(imm5
);
8043 unallocated_encoding(s
);
8047 if (!fp_access_check(s
)) {
8051 idx
= extract32(imm5
, 1 + size
, 4 - size
);
8052 write_vec_element(s
, cpu_reg(s
, rn
), rd
, idx
, size
);
8054 /* INS is considered a 128-bit write for SVE. */
8055 clear_vec_high(s
, true, rd
);
8062 * 31 30 29 21 20 16 15 12 10 9 5 4 0
8063 * +---+---+-------------------+--------+-------------+------+------+
8064 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd |
8065 * +---+---+-------------------+--------+-------------+------+------+
8067 * U: unsigned when set
8068 * size: encoded in imm5 (see ARM ARM LowestSetBit())
8070 static void handle_simd_umov_smov(DisasContext
*s
, int is_q
, int is_signed
,
8071 int rn
, int rd
, int imm5
)
8073 int size
= ctz32(imm5
);
8077 /* Check for UnallocatedEncodings */
8079 if (size
> 2 || (size
== 2 && !is_q
)) {
8080 unallocated_encoding(s
);
8085 || (size
< 3 && is_q
)
8086 || (size
== 3 && !is_q
)) {
8087 unallocated_encoding(s
);
8092 if (!fp_access_check(s
)) {
8096 element
= extract32(imm5
, 1+size
, 4);
8098 tcg_rd
= cpu_reg(s
, rd
);
8099 read_vec_element(s
, tcg_rd
, rn
, element
, size
| (is_signed
? MO_SIGN
: 0));
8100 if (is_signed
&& !is_q
) {
8101 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
8106 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
8107 * +---+---+----+-----------------+------+---+------+---+------+------+
8108 * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
8109 * +---+---+----+-----------------+------+---+------+---+------+------+
8111 static void disas_simd_copy(DisasContext
*s
, uint32_t insn
)
8113 int rd
= extract32(insn
, 0, 5);
8114 int rn
= extract32(insn
, 5, 5);
8115 int imm4
= extract32(insn
, 11, 4);
8116 int op
= extract32(insn
, 29, 1);
8117 int is_q
= extract32(insn
, 30, 1);
8118 int imm5
= extract32(insn
, 16, 5);
8123 handle_simd_inse(s
, rd
, rn
, imm4
, imm5
);
8125 unallocated_encoding(s
);
8130 /* DUP (element - vector) */
8131 handle_simd_dupe(s
, is_q
, rd
, rn
, imm5
);
8135 handle_simd_dupg(s
, is_q
, rd
, rn
, imm5
);
8140 handle_simd_insg(s
, rd
, rn
, imm5
);
8142 unallocated_encoding(s
);
8147 /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */
8148 handle_simd_umov_smov(s
, is_q
, (imm4
== 5), rn
, rd
, imm5
);
8151 unallocated_encoding(s
);
8157 /* AdvSIMD modified immediate
8158 * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
8159 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
8160 * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
8161 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
8163 * There are a number of operations that can be carried out here:
8164 * MOVI - move (shifted) imm into register
8165 * MVNI - move inverted (shifted) imm into register
8166 * ORR - bitwise OR of (shifted) imm with register
8167 * BIC - bitwise clear of (shifted) imm with register
8168 * With ARMv8.2 we also have:
8169 * FMOV half-precision
8171 static void disas_simd_mod_imm(DisasContext
*s
, uint32_t insn
)
8173 int rd
= extract32(insn
, 0, 5);
8174 int cmode
= extract32(insn
, 12, 4);
8175 int o2
= extract32(insn
, 11, 1);
8176 uint64_t abcdefgh
= extract32(insn
, 5, 5) | (extract32(insn
, 16, 3) << 5);
8177 bool is_neg
= extract32(insn
, 29, 1);
8178 bool is_q
= extract32(insn
, 30, 1);
8181 if (o2
!= 0 || ((cmode
== 0xf) && is_neg
&& !is_q
)) {
8182 /* Check for FMOV (vector, immediate) - half-precision */
8183 if (!(dc_isar_feature(aa64_fp16
, s
) && o2
&& cmode
== 0xf)) {
8184 unallocated_encoding(s
);
8189 if (!fp_access_check(s
)) {
8193 if (cmode
== 15 && o2
&& !is_neg
) {
8194 /* FMOV (vector, immediate) - half-precision */
8195 imm
= vfp_expand_imm(MO_16
, abcdefgh
);
8196 /* now duplicate across the lanes */
8197 imm
= dup_const(MO_16
, imm
);
8199 imm
= asimd_imm_const(abcdefgh
, cmode
, is_neg
);
8202 if (!((cmode
& 0x9) == 0x1 || (cmode
& 0xd) == 0x9)) {
8203 /* MOVI or MVNI, with MVNI negation handled above. */
8204 tcg_gen_gvec_dup_imm(MO_64
, vec_full_reg_offset(s
, rd
), is_q
? 16 : 8,
8205 vec_full_reg_size(s
), imm
);
8207 /* ORR or BIC, with BIC negation to AND handled above. */
8209 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_andi
, MO_64
);
8211 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_ori
, MO_64
);
8216 /* AdvSIMD scalar copy
8217 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
8218 * +-----+----+-----------------+------+---+------+---+------+------+
8219 * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
8220 * +-----+----+-----------------+------+---+------+---+------+------+
8222 static void disas_simd_scalar_copy(DisasContext
*s
, uint32_t insn
)
8224 int rd
= extract32(insn
, 0, 5);
8225 int rn
= extract32(insn
, 5, 5);
8226 int imm4
= extract32(insn
, 11, 4);
8227 int imm5
= extract32(insn
, 16, 5);
8228 int op
= extract32(insn
, 29, 1);
8230 if (op
!= 0 || imm4
!= 0) {
8231 unallocated_encoding(s
);
8235 /* DUP (element, scalar) */
8236 handle_simd_dupes(s
, rd
, rn
, imm5
);
8239 /* AdvSIMD scalar pairwise
8240 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
8241 * +-----+---+-----------+------+-----------+--------+-----+------+------+
8242 * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
8243 * +-----+---+-----------+------+-----------+--------+-----+------+------+
8245 static void disas_simd_scalar_pairwise(DisasContext
*s
, uint32_t insn
)
8247 int u
= extract32(insn
, 29, 1);
8248 int size
= extract32(insn
, 22, 2);
8249 int opcode
= extract32(insn
, 12, 5);
8250 int rn
= extract32(insn
, 5, 5);
8251 int rd
= extract32(insn
, 0, 5);
8254 /* For some ops (the FP ones), size[1] is part of the encoding.
8255 * For ADDP strictly it is not but size[1] is always 1 for valid
8258 opcode
|= (extract32(size
, 1, 1) << 5);
8261 case 0x3b: /* ADDP */
8262 if (u
|| size
!= 3) {
8263 unallocated_encoding(s
);
8266 if (!fp_access_check(s
)) {
8272 case 0xc: /* FMAXNMP */
8273 case 0xd: /* FADDP */
8274 case 0xf: /* FMAXP */
8275 case 0x2c: /* FMINNMP */
8276 case 0x2f: /* FMINP */
8277 /* FP op, size[0] is 32 or 64 bit*/
8279 if (!dc_isar_feature(aa64_fp16
, s
)) {
8280 unallocated_encoding(s
);
8286 size
= extract32(size
, 0, 1) ? MO_64
: MO_32
;
8289 if (!fp_access_check(s
)) {
8293 fpst
= fpstatus_ptr(size
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
8296 unallocated_encoding(s
);
8300 if (size
== MO_64
) {
8301 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8302 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8303 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8305 read_vec_element(s
, tcg_op1
, rn
, 0, MO_64
);
8306 read_vec_element(s
, tcg_op2
, rn
, 1, MO_64
);
8309 case 0x3b: /* ADDP */
8310 tcg_gen_add_i64(tcg_res
, tcg_op1
, tcg_op2
);
8312 case 0xc: /* FMAXNMP */
8313 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8315 case 0xd: /* FADDP */
8316 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8318 case 0xf: /* FMAXP */
8319 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8321 case 0x2c: /* FMINNMP */
8322 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8324 case 0x2f: /* FMINP */
8325 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8328 g_assert_not_reached();
8331 write_fp_dreg(s
, rd
, tcg_res
);
8333 tcg_temp_free_i64(tcg_op1
);
8334 tcg_temp_free_i64(tcg_op2
);
8335 tcg_temp_free_i64(tcg_res
);
8337 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
8338 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
8339 TCGv_i32 tcg_res
= tcg_temp_new_i32();
8341 read_vec_element_i32(s
, tcg_op1
, rn
, 0, size
);
8342 read_vec_element_i32(s
, tcg_op2
, rn
, 1, size
);
8344 if (size
== MO_16
) {
8346 case 0xc: /* FMAXNMP */
8347 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8349 case 0xd: /* FADDP */
8350 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8352 case 0xf: /* FMAXP */
8353 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8355 case 0x2c: /* FMINNMP */
8356 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8358 case 0x2f: /* FMINP */
8359 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8362 g_assert_not_reached();
8366 case 0xc: /* FMAXNMP */
8367 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8369 case 0xd: /* FADDP */
8370 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8372 case 0xf: /* FMAXP */
8373 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8375 case 0x2c: /* FMINNMP */
8376 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8378 case 0x2f: /* FMINP */
8379 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8382 g_assert_not_reached();
8386 write_fp_sreg(s
, rd
, tcg_res
);
8388 tcg_temp_free_i32(tcg_op1
);
8389 tcg_temp_free_i32(tcg_op2
);
8390 tcg_temp_free_i32(tcg_res
);
8394 tcg_temp_free_ptr(fpst
);
8399 * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate)
8401 * This code is handles the common shifting code and is used by both
8402 * the vector and scalar code.
8404 static void handle_shri_with_rndacc(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
8405 TCGv_i64 tcg_rnd
, bool accumulate
,
8406 bool is_u
, int size
, int shift
)
8408 bool extended_result
= false;
8409 bool round
= tcg_rnd
!= NULL
;
8411 TCGv_i64 tcg_src_hi
;
8413 if (round
&& size
== 3) {
8414 extended_result
= true;
8415 ext_lshift
= 64 - shift
;
8416 tcg_src_hi
= tcg_temp_new_i64();
8417 } else if (shift
== 64) {
8418 if (!accumulate
&& is_u
) {
8419 /* result is zero */
8420 tcg_gen_movi_i64(tcg_res
, 0);
8425 /* Deal with the rounding step */
8427 if (extended_result
) {
8428 TCGv_i64 tcg_zero
= tcg_const_i64(0);
8430 /* take care of sign extending tcg_res */
8431 tcg_gen_sari_i64(tcg_src_hi
, tcg_src
, 63);
8432 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
8433 tcg_src
, tcg_src_hi
,
8436 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
8440 tcg_temp_free_i64(tcg_zero
);
8442 tcg_gen_add_i64(tcg_src
, tcg_src
, tcg_rnd
);
8446 /* Now do the shift right */
8447 if (round
&& extended_result
) {
8448 /* extended case, >64 bit precision required */
8449 if (ext_lshift
== 0) {
8450 /* special case, only high bits matter */
8451 tcg_gen_mov_i64(tcg_src
, tcg_src_hi
);
8453 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
8454 tcg_gen_shli_i64(tcg_src_hi
, tcg_src_hi
, ext_lshift
);
8455 tcg_gen_or_i64(tcg_src
, tcg_src
, tcg_src_hi
);
8460 /* essentially shifting in 64 zeros */
8461 tcg_gen_movi_i64(tcg_src
, 0);
8463 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
8467 /* effectively extending the sign-bit */
8468 tcg_gen_sari_i64(tcg_src
, tcg_src
, 63);
8470 tcg_gen_sari_i64(tcg_src
, tcg_src
, shift
);
8476 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_src
);
8478 tcg_gen_mov_i64(tcg_res
, tcg_src
);
8481 if (extended_result
) {
8482 tcg_temp_free_i64(tcg_src_hi
);
8486 /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */
8487 static void handle_scalar_simd_shri(DisasContext
*s
,
8488 bool is_u
, int immh
, int immb
,
8489 int opcode
, int rn
, int rd
)
8492 int immhb
= immh
<< 3 | immb
;
8493 int shift
= 2 * (8 << size
) - immhb
;
8494 bool accumulate
= false;
8496 bool insert
= false;
8501 if (!extract32(immh
, 3, 1)) {
8502 unallocated_encoding(s
);
8506 if (!fp_access_check(s
)) {
8511 case 0x02: /* SSRA / USRA (accumulate) */
8514 case 0x04: /* SRSHR / URSHR (rounding) */
8517 case 0x06: /* SRSRA / URSRA (accum + rounding) */
8518 accumulate
= round
= true;
8520 case 0x08: /* SRI */
8526 uint64_t round_const
= 1ULL << (shift
- 1);
8527 tcg_round
= tcg_const_i64(round_const
);
8532 tcg_rn
= read_fp_dreg(s
, rn
);
8533 tcg_rd
= (accumulate
|| insert
) ? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
8536 /* shift count same as element size is valid but does nothing;
8537 * special case to avoid potential shift by 64.
8539 int esize
= 8 << size
;
8540 if (shift
!= esize
) {
8541 tcg_gen_shri_i64(tcg_rn
, tcg_rn
, shift
);
8542 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, 0, esize
- shift
);
8545 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8546 accumulate
, is_u
, size
, shift
);
8549 write_fp_dreg(s
, rd
, tcg_rd
);
8551 tcg_temp_free_i64(tcg_rn
);
8552 tcg_temp_free_i64(tcg_rd
);
8554 tcg_temp_free_i64(tcg_round
);
8558 /* SHL/SLI - Scalar shift left */
8559 static void handle_scalar_simd_shli(DisasContext
*s
, bool insert
,
8560 int immh
, int immb
, int opcode
,
8563 int size
= 32 - clz32(immh
) - 1;
8564 int immhb
= immh
<< 3 | immb
;
8565 int shift
= immhb
- (8 << size
);
8569 if (!extract32(immh
, 3, 1)) {
8570 unallocated_encoding(s
);
8574 if (!fp_access_check(s
)) {
8578 tcg_rn
= read_fp_dreg(s
, rn
);
8579 tcg_rd
= insert
? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
8582 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, shift
, 64 - shift
);
8584 tcg_gen_shli_i64(tcg_rd
, tcg_rn
, shift
);
8587 write_fp_dreg(s
, rd
, tcg_rd
);
8589 tcg_temp_free_i64(tcg_rn
);
8590 tcg_temp_free_i64(tcg_rd
);
8593 /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with
8594 * (signed/unsigned) narrowing */
8595 static void handle_vec_simd_sqshrn(DisasContext
*s
, bool is_scalar
, bool is_q
,
8596 bool is_u_shift
, bool is_u_narrow
,
8597 int immh
, int immb
, int opcode
,
8600 int immhb
= immh
<< 3 | immb
;
8601 int size
= 32 - clz32(immh
) - 1;
8602 int esize
= 8 << size
;
8603 int shift
= (2 * esize
) - immhb
;
8604 int elements
= is_scalar
? 1 : (64 / esize
);
8605 bool round
= extract32(opcode
, 0, 1);
8606 MemOp ldop
= (size
+ 1) | (is_u_shift
? 0 : MO_SIGN
);
8607 TCGv_i64 tcg_rn
, tcg_rd
, tcg_round
;
8608 TCGv_i32 tcg_rd_narrowed
;
8611 static NeonGenNarrowEnvFn
* const signed_narrow_fns
[4][2] = {
8612 { gen_helper_neon_narrow_sat_s8
,
8613 gen_helper_neon_unarrow_sat8
},
8614 { gen_helper_neon_narrow_sat_s16
,
8615 gen_helper_neon_unarrow_sat16
},
8616 { gen_helper_neon_narrow_sat_s32
,
8617 gen_helper_neon_unarrow_sat32
},
8620 static NeonGenNarrowEnvFn
* const unsigned_narrow_fns
[4] = {
8621 gen_helper_neon_narrow_sat_u8
,
8622 gen_helper_neon_narrow_sat_u16
,
8623 gen_helper_neon_narrow_sat_u32
,
8626 NeonGenNarrowEnvFn
*narrowfn
;
8632 if (extract32(immh
, 3, 1)) {
8633 unallocated_encoding(s
);
8637 if (!fp_access_check(s
)) {
8642 narrowfn
= unsigned_narrow_fns
[size
];
8644 narrowfn
= signed_narrow_fns
[size
][is_u_narrow
? 1 : 0];
8647 tcg_rn
= tcg_temp_new_i64();
8648 tcg_rd
= tcg_temp_new_i64();
8649 tcg_rd_narrowed
= tcg_temp_new_i32();
8650 tcg_final
= tcg_const_i64(0);
8653 uint64_t round_const
= 1ULL << (shift
- 1);
8654 tcg_round
= tcg_const_i64(round_const
);
8659 for (i
= 0; i
< elements
; i
++) {
8660 read_vec_element(s
, tcg_rn
, rn
, i
, ldop
);
8661 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8662 false, is_u_shift
, size
+1, shift
);
8663 narrowfn(tcg_rd_narrowed
, cpu_env
, tcg_rd
);
8664 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd_narrowed
);
8665 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
8669 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
8671 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
8675 tcg_temp_free_i64(tcg_round
);
8677 tcg_temp_free_i64(tcg_rn
);
8678 tcg_temp_free_i64(tcg_rd
);
8679 tcg_temp_free_i32(tcg_rd_narrowed
);
8680 tcg_temp_free_i64(tcg_final
);
8682 clear_vec_high(s
, is_q
, rd
);
8685 /* SQSHLU, UQSHL, SQSHL: saturating left shifts */
8686 static void handle_simd_qshl(DisasContext
*s
, bool scalar
, bool is_q
,
8687 bool src_unsigned
, bool dst_unsigned
,
8688 int immh
, int immb
, int rn
, int rd
)
8690 int immhb
= immh
<< 3 | immb
;
8691 int size
= 32 - clz32(immh
) - 1;
8692 int shift
= immhb
- (8 << size
);
8696 assert(!(scalar
&& is_q
));
8699 if (!is_q
&& extract32(immh
, 3, 1)) {
8700 unallocated_encoding(s
);
8704 /* Since we use the variable-shift helpers we must
8705 * replicate the shift count into each element of
8706 * the tcg_shift value.
8710 shift
|= shift
<< 8;
8713 shift
|= shift
<< 16;
8719 g_assert_not_reached();
8723 if (!fp_access_check(s
)) {
8728 TCGv_i64 tcg_shift
= tcg_const_i64(shift
);
8729 static NeonGenTwo64OpEnvFn
* const fns
[2][2] = {
8730 { gen_helper_neon_qshl_s64
, gen_helper_neon_qshlu_s64
},
8731 { NULL
, gen_helper_neon_qshl_u64
},
8733 NeonGenTwo64OpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
];
8734 int maxpass
= is_q
? 2 : 1;
8736 for (pass
= 0; pass
< maxpass
; pass
++) {
8737 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8739 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
8740 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
8741 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
8743 tcg_temp_free_i64(tcg_op
);
8745 tcg_temp_free_i64(tcg_shift
);
8746 clear_vec_high(s
, is_q
, rd
);
8748 TCGv_i32 tcg_shift
= tcg_const_i32(shift
);
8749 static NeonGenTwoOpEnvFn
* const fns
[2][2][3] = {
8751 { gen_helper_neon_qshl_s8
,
8752 gen_helper_neon_qshl_s16
,
8753 gen_helper_neon_qshl_s32
},
8754 { gen_helper_neon_qshlu_s8
,
8755 gen_helper_neon_qshlu_s16
,
8756 gen_helper_neon_qshlu_s32
}
8758 { NULL
, NULL
, NULL
},
8759 { gen_helper_neon_qshl_u8
,
8760 gen_helper_neon_qshl_u16
,
8761 gen_helper_neon_qshl_u32
}
8764 NeonGenTwoOpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
][size
];
8765 MemOp memop
= scalar
? size
: MO_32
;
8766 int maxpass
= scalar
? 1 : is_q
? 4 : 2;
8768 for (pass
= 0; pass
< maxpass
; pass
++) {
8769 TCGv_i32 tcg_op
= tcg_temp_new_i32();
8771 read_vec_element_i32(s
, tcg_op
, rn
, pass
, memop
);
8772 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
8776 tcg_gen_ext8u_i32(tcg_op
, tcg_op
);
8779 tcg_gen_ext16u_i32(tcg_op
, tcg_op
);
8784 g_assert_not_reached();
8786 write_fp_sreg(s
, rd
, tcg_op
);
8788 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
8791 tcg_temp_free_i32(tcg_op
);
8793 tcg_temp_free_i32(tcg_shift
);
8796 clear_vec_high(s
, is_q
, rd
);
8801 /* Common vector code for handling integer to FP conversion */
8802 static void handle_simd_intfp_conv(DisasContext
*s
, int rd
, int rn
,
8803 int elements
, int is_signed
,
8804 int fracbits
, int size
)
8806 TCGv_ptr tcg_fpst
= fpstatus_ptr(size
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
8807 TCGv_i32 tcg_shift
= NULL
;
8809 MemOp mop
= size
| (is_signed
? MO_SIGN
: 0);
8812 if (fracbits
|| size
== MO_64
) {
8813 tcg_shift
= tcg_const_i32(fracbits
);
8816 if (size
== MO_64
) {
8817 TCGv_i64 tcg_int64
= tcg_temp_new_i64();
8818 TCGv_i64 tcg_double
= tcg_temp_new_i64();
8820 for (pass
= 0; pass
< elements
; pass
++) {
8821 read_vec_element(s
, tcg_int64
, rn
, pass
, mop
);
8824 gen_helper_vfp_sqtod(tcg_double
, tcg_int64
,
8825 tcg_shift
, tcg_fpst
);
8827 gen_helper_vfp_uqtod(tcg_double
, tcg_int64
,
8828 tcg_shift
, tcg_fpst
);
8830 if (elements
== 1) {
8831 write_fp_dreg(s
, rd
, tcg_double
);
8833 write_vec_element(s
, tcg_double
, rd
, pass
, MO_64
);
8837 tcg_temp_free_i64(tcg_int64
);
8838 tcg_temp_free_i64(tcg_double
);
8841 TCGv_i32 tcg_int32
= tcg_temp_new_i32();
8842 TCGv_i32 tcg_float
= tcg_temp_new_i32();
8844 for (pass
= 0; pass
< elements
; pass
++) {
8845 read_vec_element_i32(s
, tcg_int32
, rn
, pass
, mop
);
8851 gen_helper_vfp_sltos(tcg_float
, tcg_int32
,
8852 tcg_shift
, tcg_fpst
);
8854 gen_helper_vfp_ultos(tcg_float
, tcg_int32
,
8855 tcg_shift
, tcg_fpst
);
8859 gen_helper_vfp_sitos(tcg_float
, tcg_int32
, tcg_fpst
);
8861 gen_helper_vfp_uitos(tcg_float
, tcg_int32
, tcg_fpst
);
8868 gen_helper_vfp_sltoh(tcg_float
, tcg_int32
,
8869 tcg_shift
, tcg_fpst
);
8871 gen_helper_vfp_ultoh(tcg_float
, tcg_int32
,
8872 tcg_shift
, tcg_fpst
);
8876 gen_helper_vfp_sitoh(tcg_float
, tcg_int32
, tcg_fpst
);
8878 gen_helper_vfp_uitoh(tcg_float
, tcg_int32
, tcg_fpst
);
8883 g_assert_not_reached();
8886 if (elements
== 1) {
8887 write_fp_sreg(s
, rd
, tcg_float
);
8889 write_vec_element_i32(s
, tcg_float
, rd
, pass
, size
);
8893 tcg_temp_free_i32(tcg_int32
);
8894 tcg_temp_free_i32(tcg_float
);
8897 tcg_temp_free_ptr(tcg_fpst
);
8899 tcg_temp_free_i32(tcg_shift
);
8902 clear_vec_high(s
, elements
<< size
== 16, rd
);
8905 /* UCVTF/SCVTF - Integer to FP conversion */
8906 static void handle_simd_shift_intfp_conv(DisasContext
*s
, bool is_scalar
,
8907 bool is_q
, bool is_u
,
8908 int immh
, int immb
, int opcode
,
8911 int size
, elements
, fracbits
;
8912 int immhb
= immh
<< 3 | immb
;
8916 if (!is_scalar
&& !is_q
) {
8917 unallocated_encoding(s
);
8920 } else if (immh
& 4) {
8922 } else if (immh
& 2) {
8924 if (!dc_isar_feature(aa64_fp16
, s
)) {
8925 unallocated_encoding(s
);
8929 /* immh == 0 would be a failure of the decode logic */
8930 g_assert(immh
== 1);
8931 unallocated_encoding(s
);
8938 elements
= (8 << is_q
) >> size
;
8940 fracbits
= (16 << size
) - immhb
;
8942 if (!fp_access_check(s
)) {
8946 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !is_u
, fracbits
, size
);
8949 /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */
8950 static void handle_simd_shift_fpint_conv(DisasContext
*s
, bool is_scalar
,
8951 bool is_q
, bool is_u
,
8952 int immh
, int immb
, int rn
, int rd
)
8954 int immhb
= immh
<< 3 | immb
;
8955 int pass
, size
, fracbits
;
8956 TCGv_ptr tcg_fpstatus
;
8957 TCGv_i32 tcg_rmode
, tcg_shift
;
8961 if (!is_scalar
&& !is_q
) {
8962 unallocated_encoding(s
);
8965 } else if (immh
& 0x4) {
8967 } else if (immh
& 0x2) {
8969 if (!dc_isar_feature(aa64_fp16
, s
)) {
8970 unallocated_encoding(s
);
8974 /* Should have split out AdvSIMD modified immediate earlier. */
8976 unallocated_encoding(s
);
8980 if (!fp_access_check(s
)) {
8984 assert(!(is_scalar
&& is_q
));
8986 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO
));
8987 tcg_fpstatus
= fpstatus_ptr(size
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
8988 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
8989 fracbits
= (16 << size
) - immhb
;
8990 tcg_shift
= tcg_const_i32(fracbits
);
8992 if (size
== MO_64
) {
8993 int maxpass
= is_scalar
? 1 : 2;
8995 for (pass
= 0; pass
< maxpass
; pass
++) {
8996 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8998 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9000 gen_helper_vfp_touqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
9002 gen_helper_vfp_tosqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
9004 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
9005 tcg_temp_free_i64(tcg_op
);
9007 clear_vec_high(s
, is_q
, rd
);
9009 void (*fn
)(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
9010 int maxpass
= is_scalar
? 1 : ((8 << is_q
) >> size
);
9015 fn
= gen_helper_vfp_touhh
;
9017 fn
= gen_helper_vfp_toshh
;
9022 fn
= gen_helper_vfp_touls
;
9024 fn
= gen_helper_vfp_tosls
;
9028 g_assert_not_reached();
9031 for (pass
= 0; pass
< maxpass
; pass
++) {
9032 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9034 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
9035 fn(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
9037 write_fp_sreg(s
, rd
, tcg_op
);
9039 write_vec_element_i32(s
, tcg_op
, rd
, pass
, size
);
9041 tcg_temp_free_i32(tcg_op
);
9044 clear_vec_high(s
, is_q
, rd
);
9048 tcg_temp_free_i32(tcg_shift
);
9049 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
9050 tcg_temp_free_ptr(tcg_fpstatus
);
9051 tcg_temp_free_i32(tcg_rmode
);
9054 /* AdvSIMD scalar shift by immediate
9055 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
9056 * +-----+---+-------------+------+------+--------+---+------+------+
9057 * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
9058 * +-----+---+-------------+------+------+--------+---+------+------+
9060 * This is the scalar version so it works on a fixed sized registers
9062 static void disas_simd_scalar_shift_imm(DisasContext
*s
, uint32_t insn
)
9064 int rd
= extract32(insn
, 0, 5);
9065 int rn
= extract32(insn
, 5, 5);
9066 int opcode
= extract32(insn
, 11, 5);
9067 int immb
= extract32(insn
, 16, 3);
9068 int immh
= extract32(insn
, 19, 4);
9069 bool is_u
= extract32(insn
, 29, 1);
9072 unallocated_encoding(s
);
9077 case 0x08: /* SRI */
9079 unallocated_encoding(s
);
9083 case 0x00: /* SSHR / USHR */
9084 case 0x02: /* SSRA / USRA */
9085 case 0x04: /* SRSHR / URSHR */
9086 case 0x06: /* SRSRA / URSRA */
9087 handle_scalar_simd_shri(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
9089 case 0x0a: /* SHL / SLI */
9090 handle_scalar_simd_shli(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
9092 case 0x1c: /* SCVTF, UCVTF */
9093 handle_simd_shift_intfp_conv(s
, true, false, is_u
, immh
, immb
,
9096 case 0x10: /* SQSHRUN, SQSHRUN2 */
9097 case 0x11: /* SQRSHRUN, SQRSHRUN2 */
9099 unallocated_encoding(s
);
9102 handle_vec_simd_sqshrn(s
, true, false, false, true,
9103 immh
, immb
, opcode
, rn
, rd
);
9105 case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */
9106 case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */
9107 handle_vec_simd_sqshrn(s
, true, false, is_u
, is_u
,
9108 immh
, immb
, opcode
, rn
, rd
);
9110 case 0xc: /* SQSHLU */
9112 unallocated_encoding(s
);
9115 handle_simd_qshl(s
, true, false, false, true, immh
, immb
, rn
, rd
);
9117 case 0xe: /* SQSHL, UQSHL */
9118 handle_simd_qshl(s
, true, false, is_u
, is_u
, immh
, immb
, rn
, rd
);
9120 case 0x1f: /* FCVTZS, FCVTZU */
9121 handle_simd_shift_fpint_conv(s
, true, false, is_u
, immh
, immb
, rn
, rd
);
9124 unallocated_encoding(s
);
9129 /* AdvSIMD scalar three different
9130 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
9131 * +-----+---+-----------+------+---+------+--------+-----+------+------+
9132 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
9133 * +-----+---+-----------+------+---+------+--------+-----+------+------+
9135 static void disas_simd_scalar_three_reg_diff(DisasContext
*s
, uint32_t insn
)
9137 bool is_u
= extract32(insn
, 29, 1);
9138 int size
= extract32(insn
, 22, 2);
9139 int opcode
= extract32(insn
, 12, 4);
9140 int rm
= extract32(insn
, 16, 5);
9141 int rn
= extract32(insn
, 5, 5);
9142 int rd
= extract32(insn
, 0, 5);
9145 unallocated_encoding(s
);
9150 case 0x9: /* SQDMLAL, SQDMLAL2 */
9151 case 0xb: /* SQDMLSL, SQDMLSL2 */
9152 case 0xd: /* SQDMULL, SQDMULL2 */
9153 if (size
== 0 || size
== 3) {
9154 unallocated_encoding(s
);
9159 unallocated_encoding(s
);
9163 if (!fp_access_check(s
)) {
9168 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9169 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9170 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9172 read_vec_element(s
, tcg_op1
, rn
, 0, MO_32
| MO_SIGN
);
9173 read_vec_element(s
, tcg_op2
, rm
, 0, MO_32
| MO_SIGN
);
9175 tcg_gen_mul_i64(tcg_res
, tcg_op1
, tcg_op2
);
9176 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
9179 case 0xd: /* SQDMULL, SQDMULL2 */
9181 case 0xb: /* SQDMLSL, SQDMLSL2 */
9182 tcg_gen_neg_i64(tcg_res
, tcg_res
);
9184 case 0x9: /* SQDMLAL, SQDMLAL2 */
9185 read_vec_element(s
, tcg_op1
, rd
, 0, MO_64
);
9186 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
,
9190 g_assert_not_reached();
9193 write_fp_dreg(s
, rd
, tcg_res
);
9195 tcg_temp_free_i64(tcg_op1
);
9196 tcg_temp_free_i64(tcg_op2
);
9197 tcg_temp_free_i64(tcg_res
);
9199 TCGv_i32 tcg_op1
= read_fp_hreg(s
, rn
);
9200 TCGv_i32 tcg_op2
= read_fp_hreg(s
, rm
);
9201 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9203 gen_helper_neon_mull_s16(tcg_res
, tcg_op1
, tcg_op2
);
9204 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
9207 case 0xd: /* SQDMULL, SQDMULL2 */
9209 case 0xb: /* SQDMLSL, SQDMLSL2 */
9210 gen_helper_neon_negl_u32(tcg_res
, tcg_res
);
9212 case 0x9: /* SQDMLAL, SQDMLAL2 */
9214 TCGv_i64 tcg_op3
= tcg_temp_new_i64();
9215 read_vec_element(s
, tcg_op3
, rd
, 0, MO_32
);
9216 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
,
9218 tcg_temp_free_i64(tcg_op3
);
9222 g_assert_not_reached();
9225 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
9226 write_fp_dreg(s
, rd
, tcg_res
);
9228 tcg_temp_free_i32(tcg_op1
);
9229 tcg_temp_free_i32(tcg_op2
);
9230 tcg_temp_free_i64(tcg_res
);
9234 static void handle_3same_64(DisasContext
*s
, int opcode
, bool u
,
9235 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
, TCGv_i64 tcg_rm
)
9237 /* Handle 64x64->64 opcodes which are shared between the scalar
9238 * and vector 3-same groups. We cover every opcode where size == 3
9239 * is valid in either the three-reg-same (integer, not pairwise)
9240 * or scalar-three-reg-same groups.
9245 case 0x1: /* SQADD */
9247 gen_helper_neon_qadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9249 gen_helper_neon_qadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9252 case 0x5: /* SQSUB */
9254 gen_helper_neon_qsub_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9256 gen_helper_neon_qsub_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9259 case 0x6: /* CMGT, CMHI */
9260 /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0.
9261 * We implement this using setcond (test) and then negating.
9263 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
9265 tcg_gen_setcond_i64(cond
, tcg_rd
, tcg_rn
, tcg_rm
);
9266 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
9268 case 0x7: /* CMGE, CMHS */
9269 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
9271 case 0x11: /* CMTST, CMEQ */
9276 gen_cmtst_i64(tcg_rd
, tcg_rn
, tcg_rm
);
9278 case 0x8: /* SSHL, USHL */
9280 gen_ushl_i64(tcg_rd
, tcg_rn
, tcg_rm
);
9282 gen_sshl_i64(tcg_rd
, tcg_rn
, tcg_rm
);
9285 case 0x9: /* SQSHL, UQSHL */
9287 gen_helper_neon_qshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9289 gen_helper_neon_qshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9292 case 0xa: /* SRSHL, URSHL */
9294 gen_helper_neon_rshl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
9296 gen_helper_neon_rshl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
9299 case 0xb: /* SQRSHL, UQRSHL */
9301 gen_helper_neon_qrshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9303 gen_helper_neon_qrshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
9306 case 0x10: /* ADD, SUB */
9308 tcg_gen_sub_i64(tcg_rd
, tcg_rn
, tcg_rm
);
9310 tcg_gen_add_i64(tcg_rd
, tcg_rn
, tcg_rm
);
9314 g_assert_not_reached();
9318 /* Handle the 3-same-operands float operations; shared by the scalar
9319 * and vector encodings. The caller must filter out any encodings
9320 * not allocated for the encoding it is dealing with.
9322 static void handle_3same_float(DisasContext
*s
, int size
, int elements
,
9323 int fpopcode
, int rd
, int rn
, int rm
)
9326 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
9328 for (pass
= 0; pass
< elements
; pass
++) {
9331 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
9332 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
9333 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9335 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
9336 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
9339 case 0x39: /* FMLS */
9340 /* As usual for ARM, separate negation for fused multiply-add */
9341 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
9343 case 0x19: /* FMLA */
9344 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9345 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
,
9348 case 0x18: /* FMAXNM */
9349 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9351 case 0x1a: /* FADD */
9352 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9354 case 0x1b: /* FMULX */
9355 gen_helper_vfp_mulxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9357 case 0x1c: /* FCMEQ */
9358 gen_helper_neon_ceq_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9360 case 0x1e: /* FMAX */
9361 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9363 case 0x1f: /* FRECPS */
9364 gen_helper_recpsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9366 case 0x38: /* FMINNM */
9367 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9369 case 0x3a: /* FSUB */
9370 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9372 case 0x3e: /* FMIN */
9373 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9375 case 0x3f: /* FRSQRTS */
9376 gen_helper_rsqrtsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9378 case 0x5b: /* FMUL */
9379 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9381 case 0x5c: /* FCMGE */
9382 gen_helper_neon_cge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9384 case 0x5d: /* FACGE */
9385 gen_helper_neon_acge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9387 case 0x5f: /* FDIV */
9388 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9390 case 0x7a: /* FABD */
9391 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9392 gen_helper_vfp_absd(tcg_res
, tcg_res
);
9394 case 0x7c: /* FCMGT */
9395 gen_helper_neon_cgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9397 case 0x7d: /* FACGT */
9398 gen_helper_neon_acgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9401 g_assert_not_reached();
9404 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9406 tcg_temp_free_i64(tcg_res
);
9407 tcg_temp_free_i64(tcg_op1
);
9408 tcg_temp_free_i64(tcg_op2
);
9411 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
9412 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
9413 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9415 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
9416 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
9419 case 0x39: /* FMLS */
9420 /* As usual for ARM, separate negation for fused multiply-add */
9421 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
9423 case 0x19: /* FMLA */
9424 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9425 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
,
9428 case 0x1a: /* FADD */
9429 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9431 case 0x1b: /* FMULX */
9432 gen_helper_vfp_mulxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9434 case 0x1c: /* FCMEQ */
9435 gen_helper_neon_ceq_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9437 case 0x1e: /* FMAX */
9438 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9440 case 0x1f: /* FRECPS */
9441 gen_helper_recpsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9443 case 0x18: /* FMAXNM */
9444 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9446 case 0x38: /* FMINNM */
9447 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9449 case 0x3a: /* FSUB */
9450 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9452 case 0x3e: /* FMIN */
9453 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9455 case 0x3f: /* FRSQRTS */
9456 gen_helper_rsqrtsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9458 case 0x5b: /* FMUL */
9459 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9461 case 0x5c: /* FCMGE */
9462 gen_helper_neon_cge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9464 case 0x5d: /* FACGE */
9465 gen_helper_neon_acge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9467 case 0x5f: /* FDIV */
9468 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9470 case 0x7a: /* FABD */
9471 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9472 gen_helper_vfp_abss(tcg_res
, tcg_res
);
9474 case 0x7c: /* FCMGT */
9475 gen_helper_neon_cgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9477 case 0x7d: /* FACGT */
9478 gen_helper_neon_acgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9481 g_assert_not_reached();
9484 if (elements
== 1) {
9485 /* scalar single so clear high part */
9486 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
9488 tcg_gen_extu_i32_i64(tcg_tmp
, tcg_res
);
9489 write_vec_element(s
, tcg_tmp
, rd
, pass
, MO_64
);
9490 tcg_temp_free_i64(tcg_tmp
);
9492 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9495 tcg_temp_free_i32(tcg_res
);
9496 tcg_temp_free_i32(tcg_op1
);
9497 tcg_temp_free_i32(tcg_op2
);
9501 tcg_temp_free_ptr(fpst
);
9503 clear_vec_high(s
, elements
* (size
? 8 : 4) > 8, rd
);
9506 /* AdvSIMD scalar three same
9507 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
9508 * +-----+---+-----------+------+---+------+--------+---+------+------+
9509 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
9510 * +-----+---+-----------+------+---+------+--------+---+------+------+
9512 static void disas_simd_scalar_three_reg_same(DisasContext
*s
, uint32_t insn
)
9514 int rd
= extract32(insn
, 0, 5);
9515 int rn
= extract32(insn
, 5, 5);
9516 int opcode
= extract32(insn
, 11, 5);
9517 int rm
= extract32(insn
, 16, 5);
9518 int size
= extract32(insn
, 22, 2);
9519 bool u
= extract32(insn
, 29, 1);
9522 if (opcode
>= 0x18) {
9523 /* Floating point: U, size[1] and opcode indicate operation */
9524 int fpopcode
= opcode
| (extract32(size
, 1, 1) << 5) | (u
<< 6);
9526 case 0x1b: /* FMULX */
9527 case 0x1f: /* FRECPS */
9528 case 0x3f: /* FRSQRTS */
9529 case 0x5d: /* FACGE */
9530 case 0x7d: /* FACGT */
9531 case 0x1c: /* FCMEQ */
9532 case 0x5c: /* FCMGE */
9533 case 0x7c: /* FCMGT */
9534 case 0x7a: /* FABD */
9537 unallocated_encoding(s
);
9541 if (!fp_access_check(s
)) {
9545 handle_3same_float(s
, extract32(size
, 0, 1), 1, fpopcode
, rd
, rn
, rm
);
9550 case 0x1: /* SQADD, UQADD */
9551 case 0x5: /* SQSUB, UQSUB */
9552 case 0x9: /* SQSHL, UQSHL */
9553 case 0xb: /* SQRSHL, UQRSHL */
9555 case 0x8: /* SSHL, USHL */
9556 case 0xa: /* SRSHL, URSHL */
9557 case 0x6: /* CMGT, CMHI */
9558 case 0x7: /* CMGE, CMHS */
9559 case 0x11: /* CMTST, CMEQ */
9560 case 0x10: /* ADD, SUB (vector) */
9562 unallocated_encoding(s
);
9566 case 0x16: /* SQDMULH, SQRDMULH (vector) */
9567 if (size
!= 1 && size
!= 2) {
9568 unallocated_encoding(s
);
9573 unallocated_encoding(s
);
9577 if (!fp_access_check(s
)) {
9581 tcg_rd
= tcg_temp_new_i64();
9584 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
9585 TCGv_i64 tcg_rm
= read_fp_dreg(s
, rm
);
9587 handle_3same_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rm
);
9588 tcg_temp_free_i64(tcg_rn
);
9589 tcg_temp_free_i64(tcg_rm
);
9591 /* Do a single operation on the lowest element in the vector.
9592 * We use the standard Neon helpers and rely on 0 OP 0 == 0 with
9593 * no side effects for all these operations.
9594 * OPTME: special-purpose helpers would avoid doing some
9595 * unnecessary work in the helper for the 8 and 16 bit cases.
9597 NeonGenTwoOpEnvFn
*genenvfn
;
9598 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
9599 TCGv_i32 tcg_rm
= tcg_temp_new_i32();
9600 TCGv_i32 tcg_rd32
= tcg_temp_new_i32();
9602 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
9603 read_vec_element_i32(s
, tcg_rm
, rm
, 0, size
);
9606 case 0x1: /* SQADD, UQADD */
9608 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9609 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
9610 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
9611 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
9613 genenvfn
= fns
[size
][u
];
9616 case 0x5: /* SQSUB, UQSUB */
9618 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9619 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
9620 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
9621 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
9623 genenvfn
= fns
[size
][u
];
9626 case 0x9: /* SQSHL, UQSHL */
9628 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9629 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
9630 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
9631 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
9633 genenvfn
= fns
[size
][u
];
9636 case 0xb: /* SQRSHL, UQRSHL */
9638 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9639 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
9640 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
9641 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
9643 genenvfn
= fns
[size
][u
];
9646 case 0x16: /* SQDMULH, SQRDMULH */
9648 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
9649 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
9650 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
9652 assert(size
== 1 || size
== 2);
9653 genenvfn
= fns
[size
- 1][u
];
9657 g_assert_not_reached();
9660 genenvfn(tcg_rd32
, cpu_env
, tcg_rn
, tcg_rm
);
9661 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd32
);
9662 tcg_temp_free_i32(tcg_rd32
);
9663 tcg_temp_free_i32(tcg_rn
);
9664 tcg_temp_free_i32(tcg_rm
);
9667 write_fp_dreg(s
, rd
, tcg_rd
);
9669 tcg_temp_free_i64(tcg_rd
);
9672 /* AdvSIMD scalar three same FP16
9673 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
9674 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
9675 * | 0 1 | U | 1 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
9676 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
9677 * v: 0101 1110 0100 0000 0000 0100 0000 0000 => 5e400400
9678 * m: 1101 1111 0110 0000 1100 0100 0000 0000 => df60c400
9680 static void disas_simd_scalar_three_reg_same_fp16(DisasContext
*s
,
9683 int rd
= extract32(insn
, 0, 5);
9684 int rn
= extract32(insn
, 5, 5);
9685 int opcode
= extract32(insn
, 11, 3);
9686 int rm
= extract32(insn
, 16, 5);
9687 bool u
= extract32(insn
, 29, 1);
9688 bool a
= extract32(insn
, 23, 1);
9689 int fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
9696 case 0x03: /* FMULX */
9697 case 0x04: /* FCMEQ (reg) */
9698 case 0x07: /* FRECPS */
9699 case 0x0f: /* FRSQRTS */
9700 case 0x14: /* FCMGE (reg) */
9701 case 0x15: /* FACGE */
9702 case 0x1a: /* FABD */
9703 case 0x1c: /* FCMGT (reg) */
9704 case 0x1d: /* FACGT */
9707 unallocated_encoding(s
);
9711 if (!dc_isar_feature(aa64_fp16
, s
)) {
9712 unallocated_encoding(s
);
9715 if (!fp_access_check(s
)) {
9719 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
9721 tcg_op1
= read_fp_hreg(s
, rn
);
9722 tcg_op2
= read_fp_hreg(s
, rm
);
9723 tcg_res
= tcg_temp_new_i32();
9726 case 0x03: /* FMULX */
9727 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9729 case 0x04: /* FCMEQ (reg) */
9730 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9732 case 0x07: /* FRECPS */
9733 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9735 case 0x0f: /* FRSQRTS */
9736 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9738 case 0x14: /* FCMGE (reg) */
9739 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9741 case 0x15: /* FACGE */
9742 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9744 case 0x1a: /* FABD */
9745 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9746 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
9748 case 0x1c: /* FCMGT (reg) */
9749 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9751 case 0x1d: /* FACGT */
9752 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9755 g_assert_not_reached();
9758 write_fp_sreg(s
, rd
, tcg_res
);
9761 tcg_temp_free_i32(tcg_res
);
9762 tcg_temp_free_i32(tcg_op1
);
9763 tcg_temp_free_i32(tcg_op2
);
9764 tcg_temp_free_ptr(fpst
);
9767 /* AdvSIMD scalar three same extra
9768 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
9769 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
9770 * | 0 1 | U | 1 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
9771 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
9773 static void disas_simd_scalar_three_reg_same_extra(DisasContext
*s
,
9776 int rd
= extract32(insn
, 0, 5);
9777 int rn
= extract32(insn
, 5, 5);
9778 int opcode
= extract32(insn
, 11, 4);
9779 int rm
= extract32(insn
, 16, 5);
9780 int size
= extract32(insn
, 22, 2);
9781 bool u
= extract32(insn
, 29, 1);
9782 TCGv_i32 ele1
, ele2
, ele3
;
9786 switch (u
* 16 + opcode
) {
9787 case 0x10: /* SQRDMLAH (vector) */
9788 case 0x11: /* SQRDMLSH (vector) */
9789 if (size
!= 1 && size
!= 2) {
9790 unallocated_encoding(s
);
9793 feature
= dc_isar_feature(aa64_rdm
, s
);
9796 unallocated_encoding(s
);
9800 unallocated_encoding(s
);
9803 if (!fp_access_check(s
)) {
9807 /* Do a single operation on the lowest element in the vector.
9808 * We use the standard Neon helpers and rely on 0 OP 0 == 0
9809 * with no side effects for all these operations.
9810 * OPTME: special-purpose helpers would avoid doing some
9811 * unnecessary work in the helper for the 16 bit cases.
9813 ele1
= tcg_temp_new_i32();
9814 ele2
= tcg_temp_new_i32();
9815 ele3
= tcg_temp_new_i32();
9817 read_vec_element_i32(s
, ele1
, rn
, 0, size
);
9818 read_vec_element_i32(s
, ele2
, rm
, 0, size
);
9819 read_vec_element_i32(s
, ele3
, rd
, 0, size
);
9822 case 0x0: /* SQRDMLAH */
9824 gen_helper_neon_qrdmlah_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9826 gen_helper_neon_qrdmlah_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9829 case 0x1: /* SQRDMLSH */
9831 gen_helper_neon_qrdmlsh_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9833 gen_helper_neon_qrdmlsh_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9837 g_assert_not_reached();
9839 tcg_temp_free_i32(ele1
);
9840 tcg_temp_free_i32(ele2
);
9842 res
= tcg_temp_new_i64();
9843 tcg_gen_extu_i32_i64(res
, ele3
);
9844 tcg_temp_free_i32(ele3
);
9846 write_fp_dreg(s
, rd
, res
);
9847 tcg_temp_free_i64(res
);
9850 static void handle_2misc_64(DisasContext
*s
, int opcode
, bool u
,
9851 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
,
9852 TCGv_i32 tcg_rmode
, TCGv_ptr tcg_fpstatus
)
9854 /* Handle 64->64 opcodes which are shared between the scalar and
9855 * vector 2-reg-misc groups. We cover every integer opcode where size == 3
9856 * is valid in either group and also the double-precision fp ops.
9857 * The caller only need provide tcg_rmode and tcg_fpstatus if the op
9863 case 0x4: /* CLS, CLZ */
9865 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
9867 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
9871 /* This opcode is shared with CNT and RBIT but we have earlier
9872 * enforced that size == 3 if and only if this is the NOT insn.
9874 tcg_gen_not_i64(tcg_rd
, tcg_rn
);
9876 case 0x7: /* SQABS, SQNEG */
9878 gen_helper_neon_qneg_s64(tcg_rd
, cpu_env
, tcg_rn
);
9880 gen_helper_neon_qabs_s64(tcg_rd
, cpu_env
, tcg_rn
);
9883 case 0xa: /* CMLT */
9884 /* 64 bit integer comparison against zero, result is
9885 * test ? (2^64 - 1) : 0. We implement via setcond(!test) and
9890 tcg_gen_setcondi_i64(cond
, tcg_rd
, tcg_rn
, 0);
9891 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
9893 case 0x8: /* CMGT, CMGE */
9894 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
9896 case 0x9: /* CMEQ, CMLE */
9897 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
9899 case 0xb: /* ABS, NEG */
9901 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
9903 tcg_gen_abs_i64(tcg_rd
, tcg_rn
);
9906 case 0x2f: /* FABS */
9907 gen_helper_vfp_absd(tcg_rd
, tcg_rn
);
9909 case 0x6f: /* FNEG */
9910 gen_helper_vfp_negd(tcg_rd
, tcg_rn
);
9912 case 0x7f: /* FSQRT */
9913 gen_helper_vfp_sqrtd(tcg_rd
, tcg_rn
, cpu_env
);
9915 case 0x1a: /* FCVTNS */
9916 case 0x1b: /* FCVTMS */
9917 case 0x1c: /* FCVTAS */
9918 case 0x3a: /* FCVTPS */
9919 case 0x3b: /* FCVTZS */
9921 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9922 gen_helper_vfp_tosqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9923 tcg_temp_free_i32(tcg_shift
);
9926 case 0x5a: /* FCVTNU */
9927 case 0x5b: /* FCVTMU */
9928 case 0x5c: /* FCVTAU */
9929 case 0x7a: /* FCVTPU */
9930 case 0x7b: /* FCVTZU */
9932 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9933 gen_helper_vfp_touqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9934 tcg_temp_free_i32(tcg_shift
);
9937 case 0x18: /* FRINTN */
9938 case 0x19: /* FRINTM */
9939 case 0x38: /* FRINTP */
9940 case 0x39: /* FRINTZ */
9941 case 0x58: /* FRINTA */
9942 case 0x79: /* FRINTI */
9943 gen_helper_rintd(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9945 case 0x59: /* FRINTX */
9946 gen_helper_rintd_exact(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9948 case 0x1e: /* FRINT32Z */
9949 case 0x5e: /* FRINT32X */
9950 gen_helper_frint32_d(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9952 case 0x1f: /* FRINT64Z */
9953 case 0x5f: /* FRINT64X */
9954 gen_helper_frint64_d(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9957 g_assert_not_reached();
9961 static void handle_2misc_fcmp_zero(DisasContext
*s
, int opcode
,
9962 bool is_scalar
, bool is_u
, bool is_q
,
9963 int size
, int rn
, int rd
)
9965 bool is_double
= (size
== MO_64
);
9968 if (!fp_access_check(s
)) {
9972 fpst
= fpstatus_ptr(size
== MO_16
? FPST_FPCR_F16
: FPST_FPCR
);
9975 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9976 TCGv_i64 tcg_zero
= tcg_const_i64(0);
9977 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9978 NeonGenTwoDoubleOpFn
*genfn
;
9983 case 0x2e: /* FCMLT (zero) */
9986 case 0x2c: /* FCMGT (zero) */
9987 genfn
= gen_helper_neon_cgt_f64
;
9989 case 0x2d: /* FCMEQ (zero) */
9990 genfn
= gen_helper_neon_ceq_f64
;
9992 case 0x6d: /* FCMLE (zero) */
9995 case 0x6c: /* FCMGE (zero) */
9996 genfn
= gen_helper_neon_cge_f64
;
9999 g_assert_not_reached();
10002 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10003 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
10005 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
10007 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
10009 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10011 tcg_temp_free_i64(tcg_res
);
10012 tcg_temp_free_i64(tcg_zero
);
10013 tcg_temp_free_i64(tcg_op
);
10015 clear_vec_high(s
, !is_scalar
, rd
);
10017 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10018 TCGv_i32 tcg_zero
= tcg_const_i32(0);
10019 TCGv_i32 tcg_res
= tcg_temp_new_i32();
10020 NeonGenTwoSingleOpFn
*genfn
;
10022 int pass
, maxpasses
;
10024 if (size
== MO_16
) {
10026 case 0x2e: /* FCMLT (zero) */
10029 case 0x2c: /* FCMGT (zero) */
10030 genfn
= gen_helper_advsimd_cgt_f16
;
10032 case 0x2d: /* FCMEQ (zero) */
10033 genfn
= gen_helper_advsimd_ceq_f16
;
10035 case 0x6d: /* FCMLE (zero) */
10038 case 0x6c: /* FCMGE (zero) */
10039 genfn
= gen_helper_advsimd_cge_f16
;
10042 g_assert_not_reached();
10046 case 0x2e: /* FCMLT (zero) */
10049 case 0x2c: /* FCMGT (zero) */
10050 genfn
= gen_helper_neon_cgt_f32
;
10052 case 0x2d: /* FCMEQ (zero) */
10053 genfn
= gen_helper_neon_ceq_f32
;
10055 case 0x6d: /* FCMLE (zero) */
10058 case 0x6c: /* FCMGE (zero) */
10059 genfn
= gen_helper_neon_cge_f32
;
10062 g_assert_not_reached();
10069 int vector_size
= 8 << is_q
;
10070 maxpasses
= vector_size
>> size
;
10073 for (pass
= 0; pass
< maxpasses
; pass
++) {
10074 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
10076 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
10078 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
10081 write_fp_sreg(s
, rd
, tcg_res
);
10083 write_vec_element_i32(s
, tcg_res
, rd
, pass
, size
);
10086 tcg_temp_free_i32(tcg_res
);
10087 tcg_temp_free_i32(tcg_zero
);
10088 tcg_temp_free_i32(tcg_op
);
10090 clear_vec_high(s
, is_q
, rd
);
10094 tcg_temp_free_ptr(fpst
);
10097 static void handle_2misc_reciprocal(DisasContext
*s
, int opcode
,
10098 bool is_scalar
, bool is_u
, bool is_q
,
10099 int size
, int rn
, int rd
)
10101 bool is_double
= (size
== 3);
10102 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
10105 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10106 TCGv_i64 tcg_res
= tcg_temp_new_i64();
10109 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10110 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
10112 case 0x3d: /* FRECPE */
10113 gen_helper_recpe_f64(tcg_res
, tcg_op
, fpst
);
10115 case 0x3f: /* FRECPX */
10116 gen_helper_frecpx_f64(tcg_res
, tcg_op
, fpst
);
10118 case 0x7d: /* FRSQRTE */
10119 gen_helper_rsqrte_f64(tcg_res
, tcg_op
, fpst
);
10122 g_assert_not_reached();
10124 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
10126 tcg_temp_free_i64(tcg_res
);
10127 tcg_temp_free_i64(tcg_op
);
10128 clear_vec_high(s
, !is_scalar
, rd
);
10130 TCGv_i32 tcg_op
= tcg_temp_new_i32();
10131 TCGv_i32 tcg_res
= tcg_temp_new_i32();
10132 int pass
, maxpasses
;
10137 maxpasses
= is_q
? 4 : 2;
10140 for (pass
= 0; pass
< maxpasses
; pass
++) {
10141 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
10144 case 0x3c: /* URECPE */
10145 gen_helper_recpe_u32(tcg_res
, tcg_op
);
10147 case 0x3d: /* FRECPE */
10148 gen_helper_recpe_f32(tcg_res
, tcg_op
, fpst
);
10150 case 0x3f: /* FRECPX */
10151 gen_helper_frecpx_f32(tcg_res
, tcg_op
, fpst
);
10153 case 0x7d: /* FRSQRTE */
10154 gen_helper_rsqrte_f32(tcg_res
, tcg_op
, fpst
);
10157 g_assert_not_reached();
10161 write_fp_sreg(s
, rd
, tcg_res
);
10163 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
10166 tcg_temp_free_i32(tcg_res
);
10167 tcg_temp_free_i32(tcg_op
);
10169 clear_vec_high(s
, is_q
, rd
);
10172 tcg_temp_free_ptr(fpst
);
10175 static void handle_2misc_narrow(DisasContext
*s
, bool scalar
,
10176 int opcode
, bool u
, bool is_q
,
10177 int size
, int rn
, int rd
)
10179 /* Handle 2-reg-misc ops which are narrowing (so each 2*size element
10180 * in the source becomes a size element in the destination).
10183 TCGv_i32 tcg_res
[2];
10184 int destelt
= is_q
? 2 : 0;
10185 int passes
= scalar
? 1 : 2;
10188 tcg_res
[1] = tcg_const_i32(0);
10191 for (pass
= 0; pass
< passes
; pass
++) {
10192 TCGv_i64 tcg_op
= tcg_temp_new_i64();
10193 NeonGenNarrowFn
*genfn
= NULL
;
10194 NeonGenNarrowEnvFn
*genenvfn
= NULL
;
10197 read_vec_element(s
, tcg_op
, rn
, pass
, size
+ 1);
10199 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
10201 tcg_res
[pass
] = tcg_temp_new_i32();
10204 case 0x12: /* XTN, SQXTUN */
10206 static NeonGenNarrowFn
* const xtnfns
[3] = {
10207 gen_helper_neon_narrow_u8
,
10208 gen_helper_neon_narrow_u16
,
10209 tcg_gen_extrl_i64_i32
,
10211 static NeonGenNarrowEnvFn
* const sqxtunfns
[3] = {
10212 gen_helper_neon_unarrow_sat8
,
10213 gen_helper_neon_unarrow_sat16
,
10214 gen_helper_neon_unarrow_sat32
,
10217 genenvfn
= sqxtunfns
[size
];
10219 genfn
= xtnfns
[size
];
10223 case 0x14: /* SQXTN, UQXTN */
10225 static NeonGenNarrowEnvFn
* const fns
[3][2] = {
10226 { gen_helper_neon_narrow_sat_s8
,
10227 gen_helper_neon_narrow_sat_u8
},
10228 { gen_helper_neon_narrow_sat_s16
,
10229 gen_helper_neon_narrow_sat_u16
},
10230 { gen_helper_neon_narrow_sat_s32
,
10231 gen_helper_neon_narrow_sat_u32
},
10233 genenvfn
= fns
[size
][u
];
10236 case 0x16: /* FCVTN, FCVTN2 */
10237 /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
10239 gen_helper_vfp_fcvtsd(tcg_res
[pass
], tcg_op
, cpu_env
);
10241 TCGv_i32 tcg_lo
= tcg_temp_new_i32();
10242 TCGv_i32 tcg_hi
= tcg_temp_new_i32();
10243 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
10244 TCGv_i32 ahp
= get_ahp_flag();
10246 tcg_gen_extr_i64_i32(tcg_lo
, tcg_hi
, tcg_op
);
10247 gen_helper_vfp_fcvt_f32_to_f16(tcg_lo
, tcg_lo
, fpst
, ahp
);
10248 gen_helper_vfp_fcvt_f32_to_f16(tcg_hi
, tcg_hi
, fpst
, ahp
);
10249 tcg_gen_deposit_i32(tcg_res
[pass
], tcg_lo
, tcg_hi
, 16, 16);
10250 tcg_temp_free_i32(tcg_lo
);
10251 tcg_temp_free_i32(tcg_hi
);
10252 tcg_temp_free_ptr(fpst
);
10253 tcg_temp_free_i32(ahp
);
10256 case 0x36: /* BFCVTN, BFCVTN2 */
10258 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
10259 gen_helper_bfcvt_pair(tcg_res
[pass
], tcg_op
, fpst
);
10260 tcg_temp_free_ptr(fpst
);
10263 case 0x56: /* FCVTXN, FCVTXN2 */
10264 /* 64 bit to 32 bit float conversion
10265 * with von Neumann rounding (round to odd)
10268 gen_helper_fcvtx_f64_to_f32(tcg_res
[pass
], tcg_op
, cpu_env
);
10271 g_assert_not_reached();
10275 genfn(tcg_res
[pass
], tcg_op
);
10276 } else if (genenvfn
) {
10277 genenvfn(tcg_res
[pass
], cpu_env
, tcg_op
);
10280 tcg_temp_free_i64(tcg_op
);
10283 for (pass
= 0; pass
< 2; pass
++) {
10284 write_vec_element_i32(s
, tcg_res
[pass
], rd
, destelt
+ pass
, MO_32
);
10285 tcg_temp_free_i32(tcg_res
[pass
]);
10287 clear_vec_high(s
, is_q
, rd
);
10290 /* Remaining saturating accumulating ops */
10291 static void handle_2misc_satacc(DisasContext
*s
, bool is_scalar
, bool is_u
,
10292 bool is_q
, int size
, int rn
, int rd
)
10294 bool is_double
= (size
== 3);
10297 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
10298 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
10301 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
10302 read_vec_element(s
, tcg_rn
, rn
, pass
, MO_64
);
10303 read_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
10305 if (is_u
) { /* USQADD */
10306 gen_helper_neon_uqadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10307 } else { /* SUQADD */
10308 gen_helper_neon_sqadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10310 write_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
10312 tcg_temp_free_i64(tcg_rd
);
10313 tcg_temp_free_i64(tcg_rn
);
10314 clear_vec_high(s
, !is_scalar
, rd
);
10316 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
10317 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
10318 int pass
, maxpasses
;
10323 maxpasses
= is_q
? 4 : 2;
10326 for (pass
= 0; pass
< maxpasses
; pass
++) {
10328 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, size
);
10329 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, size
);
10331 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, MO_32
);
10332 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
10335 if (is_u
) { /* USQADD */
10338 gen_helper_neon_uqadd_s8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10341 gen_helper_neon_uqadd_s16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10344 gen_helper_neon_uqadd_s32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10347 g_assert_not_reached();
10349 } else { /* SUQADD */
10352 gen_helper_neon_sqadd_u8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10355 gen_helper_neon_sqadd_u16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10358 gen_helper_neon_sqadd_u32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10361 g_assert_not_reached();
10366 TCGv_i64 tcg_zero
= tcg_const_i64(0);
10367 write_vec_element(s
, tcg_zero
, rd
, 0, MO_64
);
10368 tcg_temp_free_i64(tcg_zero
);
10370 write_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
10372 tcg_temp_free_i32(tcg_rd
);
10373 tcg_temp_free_i32(tcg_rn
);
10374 clear_vec_high(s
, is_q
, rd
);
10378 /* AdvSIMD scalar two reg misc
10379 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
10380 * +-----+---+-----------+------+-----------+--------+-----+------+------+
10381 * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
10382 * +-----+---+-----------+------+-----------+--------+-----+------+------+
10384 static void disas_simd_scalar_two_reg_misc(DisasContext
*s
, uint32_t insn
)
10386 int rd
= extract32(insn
, 0, 5);
10387 int rn
= extract32(insn
, 5, 5);
10388 int opcode
= extract32(insn
, 12, 5);
10389 int size
= extract32(insn
, 22, 2);
10390 bool u
= extract32(insn
, 29, 1);
10391 bool is_fcvt
= false;
10393 TCGv_i32 tcg_rmode
;
10394 TCGv_ptr tcg_fpstatus
;
10397 case 0x3: /* USQADD / SUQADD*/
10398 if (!fp_access_check(s
)) {
10401 handle_2misc_satacc(s
, true, u
, false, size
, rn
, rd
);
10403 case 0x7: /* SQABS / SQNEG */
10405 case 0xa: /* CMLT */
10407 unallocated_encoding(s
);
10411 case 0x8: /* CMGT, CMGE */
10412 case 0x9: /* CMEQ, CMLE */
10413 case 0xb: /* ABS, NEG */
10415 unallocated_encoding(s
);
10419 case 0x12: /* SQXTUN */
10421 unallocated_encoding(s
);
10425 case 0x14: /* SQXTN, UQXTN */
10427 unallocated_encoding(s
);
10430 if (!fp_access_check(s
)) {
10433 handle_2misc_narrow(s
, true, opcode
, u
, false, size
, rn
, rd
);
10436 case 0x16 ... 0x1d:
10438 /* Floating point: U, size[1] and opcode indicate operation;
10439 * size[0] indicates single or double precision.
10441 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
10442 size
= extract32(size
, 0, 1) ? 3 : 2;
10444 case 0x2c: /* FCMGT (zero) */
10445 case 0x2d: /* FCMEQ (zero) */
10446 case 0x2e: /* FCMLT (zero) */
10447 case 0x6c: /* FCMGE (zero) */
10448 case 0x6d: /* FCMLE (zero) */
10449 handle_2misc_fcmp_zero(s
, opcode
, true, u
, true, size
, rn
, rd
);
10451 case 0x1d: /* SCVTF */
10452 case 0x5d: /* UCVTF */
10454 bool is_signed
= (opcode
== 0x1d);
10455 if (!fp_access_check(s
)) {
10458 handle_simd_intfp_conv(s
, rd
, rn
, 1, is_signed
, 0, size
);
10461 case 0x3d: /* FRECPE */
10462 case 0x3f: /* FRECPX */
10463 case 0x7d: /* FRSQRTE */
10464 if (!fp_access_check(s
)) {
10467 handle_2misc_reciprocal(s
, opcode
, true, u
, true, size
, rn
, rd
);
10469 case 0x1a: /* FCVTNS */
10470 case 0x1b: /* FCVTMS */
10471 case 0x3a: /* FCVTPS */
10472 case 0x3b: /* FCVTZS */
10473 case 0x5a: /* FCVTNU */
10474 case 0x5b: /* FCVTMU */
10475 case 0x7a: /* FCVTPU */
10476 case 0x7b: /* FCVTZU */
10478 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
10480 case 0x1c: /* FCVTAS */
10481 case 0x5c: /* FCVTAU */
10482 /* TIEAWAY doesn't fit in the usual rounding mode encoding */
10484 rmode
= FPROUNDING_TIEAWAY
;
10486 case 0x56: /* FCVTXN, FCVTXN2 */
10488 unallocated_encoding(s
);
10491 if (!fp_access_check(s
)) {
10494 handle_2misc_narrow(s
, true, opcode
, u
, false, size
- 1, rn
, rd
);
10497 unallocated_encoding(s
);
10502 unallocated_encoding(s
);
10506 if (!fp_access_check(s
)) {
10511 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
10512 tcg_fpstatus
= fpstatus_ptr(FPST_FPCR
);
10513 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
10516 tcg_fpstatus
= NULL
;
10520 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
10521 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
10523 handle_2misc_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rmode
, tcg_fpstatus
);
10524 write_fp_dreg(s
, rd
, tcg_rd
);
10525 tcg_temp_free_i64(tcg_rd
);
10526 tcg_temp_free_i64(tcg_rn
);
10528 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
10529 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
10531 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
10534 case 0x7: /* SQABS, SQNEG */
10536 NeonGenOneOpEnvFn
*genfn
;
10537 static NeonGenOneOpEnvFn
* const fns
[3][2] = {
10538 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
10539 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
10540 { gen_helper_neon_qabs_s32
, gen_helper_neon_qneg_s32
},
10542 genfn
= fns
[size
][u
];
10543 genfn(tcg_rd
, cpu_env
, tcg_rn
);
10546 case 0x1a: /* FCVTNS */
10547 case 0x1b: /* FCVTMS */
10548 case 0x1c: /* FCVTAS */
10549 case 0x3a: /* FCVTPS */
10550 case 0x3b: /* FCVTZS */
10552 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10553 gen_helper_vfp_tosls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
10554 tcg_temp_free_i32(tcg_shift
);
10557 case 0x5a: /* FCVTNU */
10558 case 0x5b: /* FCVTMU */
10559 case 0x5c: /* FCVTAU */
10560 case 0x7a: /* FCVTPU */
10561 case 0x7b: /* FCVTZU */
10563 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10564 gen_helper_vfp_touls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
10565 tcg_temp_free_i32(tcg_shift
);
10569 g_assert_not_reached();
10572 write_fp_sreg(s
, rd
, tcg_rd
);
10573 tcg_temp_free_i32(tcg_rd
);
10574 tcg_temp_free_i32(tcg_rn
);
10578 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
10579 tcg_temp_free_i32(tcg_rmode
);
10580 tcg_temp_free_ptr(tcg_fpstatus
);
10584 /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
10585 static void handle_vec_simd_shri(DisasContext
*s
, bool is_q
, bool is_u
,
10586 int immh
, int immb
, int opcode
, int rn
, int rd
)
10588 int size
= 32 - clz32(immh
) - 1;
10589 int immhb
= immh
<< 3 | immb
;
10590 int shift
= 2 * (8 << size
) - immhb
;
10591 GVecGen2iFn
*gvec_fn
;
10593 if (extract32(immh
, 3, 1) && !is_q
) {
10594 unallocated_encoding(s
);
10597 tcg_debug_assert(size
<= 3);
10599 if (!fp_access_check(s
)) {
10604 case 0x02: /* SSRA / USRA (accumulate) */
10605 gvec_fn
= is_u
? gen_gvec_usra
: gen_gvec_ssra
;
10608 case 0x08: /* SRI */
10609 gvec_fn
= gen_gvec_sri
;
10612 case 0x00: /* SSHR / USHR */
10614 if (shift
== 8 << size
) {
10615 /* Shift count the same size as element size produces zero. */
10616 tcg_gen_gvec_dup_imm(size
, vec_full_reg_offset(s
, rd
),
10617 is_q
? 16 : 8, vec_full_reg_size(s
), 0);
10620 gvec_fn
= tcg_gen_gvec_shri
;
10622 /* Shift count the same size as element size produces all sign. */
10623 if (shift
== 8 << size
) {
10626 gvec_fn
= tcg_gen_gvec_sari
;
10630 case 0x04: /* SRSHR / URSHR (rounding) */
10631 gvec_fn
= is_u
? gen_gvec_urshr
: gen_gvec_srshr
;
10634 case 0x06: /* SRSRA / URSRA (accum + rounding) */
10635 gvec_fn
= is_u
? gen_gvec_ursra
: gen_gvec_srsra
;
10639 g_assert_not_reached();
10642 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, gvec_fn
, size
);
10645 /* SHL/SLI - Vector shift left */
10646 static void handle_vec_simd_shli(DisasContext
*s
, bool is_q
, bool insert
,
10647 int immh
, int immb
, int opcode
, int rn
, int rd
)
10649 int size
= 32 - clz32(immh
) - 1;
10650 int immhb
= immh
<< 3 | immb
;
10651 int shift
= immhb
- (8 << size
);
10653 /* Range of size is limited by decode: immh is a non-zero 4 bit field */
10654 assert(size
>= 0 && size
<= 3);
10656 if (extract32(immh
, 3, 1) && !is_q
) {
10657 unallocated_encoding(s
);
10661 if (!fp_access_check(s
)) {
10666 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, gen_gvec_sli
, size
);
10668 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_shli
, size
);
10672 /* USHLL/SHLL - Vector shift left with widening */
10673 static void handle_vec_simd_wshli(DisasContext
*s
, bool is_q
, bool is_u
,
10674 int immh
, int immb
, int opcode
, int rn
, int rd
)
10676 int size
= 32 - clz32(immh
) - 1;
10677 int immhb
= immh
<< 3 | immb
;
10678 int shift
= immhb
- (8 << size
);
10680 int esize
= 8 << size
;
10681 int elements
= dsize
/esize
;
10682 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
10683 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
10687 unallocated_encoding(s
);
10691 if (!fp_access_check(s
)) {
10695 /* For the LL variants the store is larger than the load,
10696 * so if rd == rn we would overwrite parts of our input.
10697 * So load everything right now and use shifts in the main loop.
10699 read_vec_element(s
, tcg_rn
, rn
, is_q
? 1 : 0, MO_64
);
10701 for (i
= 0; i
< elements
; i
++) {
10702 tcg_gen_shri_i64(tcg_rd
, tcg_rn
, i
* esize
);
10703 ext_and_shift_reg(tcg_rd
, tcg_rd
, size
| (!is_u
<< 2), 0);
10704 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, shift
);
10705 write_vec_element(s
, tcg_rd
, rd
, i
, size
+ 1);
10709 /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */
10710 static void handle_vec_simd_shrn(DisasContext
*s
, bool is_q
,
10711 int immh
, int immb
, int opcode
, int rn
, int rd
)
10713 int immhb
= immh
<< 3 | immb
;
10714 int size
= 32 - clz32(immh
) - 1;
10716 int esize
= 8 << size
;
10717 int elements
= dsize
/esize
;
10718 int shift
= (2 * esize
) - immhb
;
10719 bool round
= extract32(opcode
, 0, 1);
10720 TCGv_i64 tcg_rn
, tcg_rd
, tcg_final
;
10721 TCGv_i64 tcg_round
;
10724 if (extract32(immh
, 3, 1)) {
10725 unallocated_encoding(s
);
10729 if (!fp_access_check(s
)) {
10733 tcg_rn
= tcg_temp_new_i64();
10734 tcg_rd
= tcg_temp_new_i64();
10735 tcg_final
= tcg_temp_new_i64();
10736 read_vec_element(s
, tcg_final
, rd
, is_q
? 1 : 0, MO_64
);
10739 uint64_t round_const
= 1ULL << (shift
- 1);
10740 tcg_round
= tcg_const_i64(round_const
);
10745 for (i
= 0; i
< elements
; i
++) {
10746 read_vec_element(s
, tcg_rn
, rn
, i
, size
+1);
10747 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
10748 false, true, size
+1, shift
);
10750 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
10754 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
10756 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
10759 tcg_temp_free_i64(tcg_round
);
10761 tcg_temp_free_i64(tcg_rn
);
10762 tcg_temp_free_i64(tcg_rd
);
10763 tcg_temp_free_i64(tcg_final
);
10765 clear_vec_high(s
, is_q
, rd
);
10769 /* AdvSIMD shift by immediate
10770 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
10771 * +---+---+---+-------------+------+------+--------+---+------+------+
10772 * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
10773 * +---+---+---+-------------+------+------+--------+---+------+------+
10775 static void disas_simd_shift_imm(DisasContext
*s
, uint32_t insn
)
10777 int rd
= extract32(insn
, 0, 5);
10778 int rn
= extract32(insn
, 5, 5);
10779 int opcode
= extract32(insn
, 11, 5);
10780 int immb
= extract32(insn
, 16, 3);
10781 int immh
= extract32(insn
, 19, 4);
10782 bool is_u
= extract32(insn
, 29, 1);
10783 bool is_q
= extract32(insn
, 30, 1);
10785 /* data_proc_simd[] has sent immh == 0 to disas_simd_mod_imm. */
10789 case 0x08: /* SRI */
10791 unallocated_encoding(s
);
10795 case 0x00: /* SSHR / USHR */
10796 case 0x02: /* SSRA / USRA (accumulate) */
10797 case 0x04: /* SRSHR / URSHR (rounding) */
10798 case 0x06: /* SRSRA / URSRA (accum + rounding) */
10799 handle_vec_simd_shri(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10801 case 0x0a: /* SHL / SLI */
10802 handle_vec_simd_shli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10804 case 0x10: /* SHRN */
10805 case 0x11: /* RSHRN / SQRSHRUN */
10807 handle_vec_simd_sqshrn(s
, false, is_q
, false, true, immh
, immb
,
10810 handle_vec_simd_shrn(s
, is_q
, immh
, immb
, opcode
, rn
, rd
);
10813 case 0x12: /* SQSHRN / UQSHRN */
10814 case 0x13: /* SQRSHRN / UQRSHRN */
10815 handle_vec_simd_sqshrn(s
, false, is_q
, is_u
, is_u
, immh
, immb
,
10818 case 0x14: /* SSHLL / USHLL */
10819 handle_vec_simd_wshli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10821 case 0x1c: /* SCVTF / UCVTF */
10822 handle_simd_shift_intfp_conv(s
, false, is_q
, is_u
, immh
, immb
,
10825 case 0xc: /* SQSHLU */
10827 unallocated_encoding(s
);
10830 handle_simd_qshl(s
, false, is_q
, false, true, immh
, immb
, rn
, rd
);
10832 case 0xe: /* SQSHL, UQSHL */
10833 handle_simd_qshl(s
, false, is_q
, is_u
, is_u
, immh
, immb
, rn
, rd
);
10835 case 0x1f: /* FCVTZS/ FCVTZU */
10836 handle_simd_shift_fpint_conv(s
, false, is_q
, is_u
, immh
, immb
, rn
, rd
);
10839 unallocated_encoding(s
);
10844 /* Generate code to do a "long" addition or subtraction, ie one done in
10845 * TCGv_i64 on vector lanes twice the width specified by size.
10847 static void gen_neon_addl(int size
, bool is_sub
, TCGv_i64 tcg_res
,
10848 TCGv_i64 tcg_op1
, TCGv_i64 tcg_op2
)
10850 static NeonGenTwo64OpFn
* const fns
[3][2] = {
10851 { gen_helper_neon_addl_u16
, gen_helper_neon_subl_u16
},
10852 { gen_helper_neon_addl_u32
, gen_helper_neon_subl_u32
},
10853 { tcg_gen_add_i64
, tcg_gen_sub_i64
},
10855 NeonGenTwo64OpFn
*genfn
;
10858 genfn
= fns
[size
][is_sub
];
10859 genfn(tcg_res
, tcg_op1
, tcg_op2
);
10862 static void handle_3rd_widening(DisasContext
*s
, int is_q
, int is_u
, int size
,
10863 int opcode
, int rd
, int rn
, int rm
)
10865 /* 3-reg-different widening insns: 64 x 64 -> 128 */
10866 TCGv_i64 tcg_res
[2];
10869 tcg_res
[0] = tcg_temp_new_i64();
10870 tcg_res
[1] = tcg_temp_new_i64();
10872 /* Does this op do an adding accumulate, a subtracting accumulate,
10873 * or no accumulate at all?
10891 read_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
10892 read_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
10895 /* size == 2 means two 32x32->64 operations; this is worth special
10896 * casing because we can generally handle it inline.
10899 for (pass
= 0; pass
< 2; pass
++) {
10900 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10901 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10902 TCGv_i64 tcg_passres
;
10903 MemOp memop
= MO_32
| (is_u
? 0 : MO_SIGN
);
10905 int elt
= pass
+ is_q
* 2;
10907 read_vec_element(s
, tcg_op1
, rn
, elt
, memop
);
10908 read_vec_element(s
, tcg_op2
, rm
, elt
, memop
);
10911 tcg_passres
= tcg_res
[pass
];
10913 tcg_passres
= tcg_temp_new_i64();
10917 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10918 tcg_gen_add_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10920 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10921 tcg_gen_sub_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10923 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10924 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10926 TCGv_i64 tcg_tmp1
= tcg_temp_new_i64();
10927 TCGv_i64 tcg_tmp2
= tcg_temp_new_i64();
10929 tcg_gen_sub_i64(tcg_tmp1
, tcg_op1
, tcg_op2
);
10930 tcg_gen_sub_i64(tcg_tmp2
, tcg_op2
, tcg_op1
);
10931 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
10933 tcg_op1
, tcg_op2
, tcg_tmp1
, tcg_tmp2
);
10934 tcg_temp_free_i64(tcg_tmp1
);
10935 tcg_temp_free_i64(tcg_tmp2
);
10938 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10939 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10940 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
10941 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10943 case 9: /* SQDMLAL, SQDMLAL2 */
10944 case 11: /* SQDMLSL, SQDMLSL2 */
10945 case 13: /* SQDMULL, SQDMULL2 */
10946 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10947 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
10948 tcg_passres
, tcg_passres
);
10951 g_assert_not_reached();
10954 if (opcode
== 9 || opcode
== 11) {
10955 /* saturating accumulate ops */
10957 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
10959 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
10960 tcg_res
[pass
], tcg_passres
);
10961 } else if (accop
> 0) {
10962 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10963 } else if (accop
< 0) {
10964 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10968 tcg_temp_free_i64(tcg_passres
);
10971 tcg_temp_free_i64(tcg_op1
);
10972 tcg_temp_free_i64(tcg_op2
);
10975 /* size 0 or 1, generally helper functions */
10976 for (pass
= 0; pass
< 2; pass
++) {
10977 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
10978 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10979 TCGv_i64 tcg_passres
;
10980 int elt
= pass
+ is_q
* 2;
10982 read_vec_element_i32(s
, tcg_op1
, rn
, elt
, MO_32
);
10983 read_vec_element_i32(s
, tcg_op2
, rm
, elt
, MO_32
);
10986 tcg_passres
= tcg_res
[pass
];
10988 tcg_passres
= tcg_temp_new_i64();
10992 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10993 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10995 TCGv_i64 tcg_op2_64
= tcg_temp_new_i64();
10996 static NeonGenWidenFn
* const widenfns
[2][2] = {
10997 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
10998 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
11000 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
11002 widenfn(tcg_op2_64
, tcg_op2
);
11003 widenfn(tcg_passres
, tcg_op1
);
11004 gen_neon_addl(size
, (opcode
== 2), tcg_passres
,
11005 tcg_passres
, tcg_op2_64
);
11006 tcg_temp_free_i64(tcg_op2_64
);
11009 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
11010 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
11013 gen_helper_neon_abdl_u16(tcg_passres
, tcg_op1
, tcg_op2
);
11015 gen_helper_neon_abdl_s16(tcg_passres
, tcg_op1
, tcg_op2
);
11019 gen_helper_neon_abdl_u32(tcg_passres
, tcg_op1
, tcg_op2
);
11021 gen_helper_neon_abdl_s32(tcg_passres
, tcg_op1
, tcg_op2
);
11025 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
11026 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
11027 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
11030 gen_helper_neon_mull_u8(tcg_passres
, tcg_op1
, tcg_op2
);
11032 gen_helper_neon_mull_s8(tcg_passres
, tcg_op1
, tcg_op2
);
11036 gen_helper_neon_mull_u16(tcg_passres
, tcg_op1
, tcg_op2
);
11038 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
11042 case 9: /* SQDMLAL, SQDMLAL2 */
11043 case 11: /* SQDMLSL, SQDMLSL2 */
11044 case 13: /* SQDMULL, SQDMULL2 */
11046 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
11047 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
11048 tcg_passres
, tcg_passres
);
11051 g_assert_not_reached();
11053 tcg_temp_free_i32(tcg_op1
);
11054 tcg_temp_free_i32(tcg_op2
);
11057 if (opcode
== 9 || opcode
== 11) {
11058 /* saturating accumulate ops */
11060 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
11062 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
11066 gen_neon_addl(size
, (accop
< 0), tcg_res
[pass
],
11067 tcg_res
[pass
], tcg_passres
);
11069 tcg_temp_free_i64(tcg_passres
);
11074 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
11075 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
11076 tcg_temp_free_i64(tcg_res
[0]);
11077 tcg_temp_free_i64(tcg_res
[1]);
11080 static void handle_3rd_wide(DisasContext
*s
, int is_q
, int is_u
, int size
,
11081 int opcode
, int rd
, int rn
, int rm
)
11083 TCGv_i64 tcg_res
[2];
11084 int part
= is_q
? 2 : 0;
11087 for (pass
= 0; pass
< 2; pass
++) {
11088 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11089 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11090 TCGv_i64 tcg_op2_wide
= tcg_temp_new_i64();
11091 static NeonGenWidenFn
* const widenfns
[3][2] = {
11092 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
11093 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
11094 { tcg_gen_ext_i32_i64
, tcg_gen_extu_i32_i64
},
11096 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
11098 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
11099 read_vec_element_i32(s
, tcg_op2
, rm
, part
+ pass
, MO_32
);
11100 widenfn(tcg_op2_wide
, tcg_op2
);
11101 tcg_temp_free_i32(tcg_op2
);
11102 tcg_res
[pass
] = tcg_temp_new_i64();
11103 gen_neon_addl(size
, (opcode
== 3),
11104 tcg_res
[pass
], tcg_op1
, tcg_op2_wide
);
11105 tcg_temp_free_i64(tcg_op1
);
11106 tcg_temp_free_i64(tcg_op2_wide
);
11109 for (pass
= 0; pass
< 2; pass
++) {
11110 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11111 tcg_temp_free_i64(tcg_res
[pass
]);
11115 static void do_narrow_round_high_u32(TCGv_i32 res
, TCGv_i64 in
)
11117 tcg_gen_addi_i64(in
, in
, 1U << 31);
11118 tcg_gen_extrh_i64_i32(res
, in
);
11121 static void handle_3rd_narrowing(DisasContext
*s
, int is_q
, int is_u
, int size
,
11122 int opcode
, int rd
, int rn
, int rm
)
11124 TCGv_i32 tcg_res
[2];
11125 int part
= is_q
? 2 : 0;
11128 for (pass
= 0; pass
< 2; pass
++) {
11129 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11130 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11131 TCGv_i64 tcg_wideres
= tcg_temp_new_i64();
11132 static NeonGenNarrowFn
* const narrowfns
[3][2] = {
11133 { gen_helper_neon_narrow_high_u8
,
11134 gen_helper_neon_narrow_round_high_u8
},
11135 { gen_helper_neon_narrow_high_u16
,
11136 gen_helper_neon_narrow_round_high_u16
},
11137 { tcg_gen_extrh_i64_i32
, do_narrow_round_high_u32
},
11139 NeonGenNarrowFn
*gennarrow
= narrowfns
[size
][is_u
];
11141 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
11142 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
11144 gen_neon_addl(size
, (opcode
== 6), tcg_wideres
, tcg_op1
, tcg_op2
);
11146 tcg_temp_free_i64(tcg_op1
);
11147 tcg_temp_free_i64(tcg_op2
);
11149 tcg_res
[pass
] = tcg_temp_new_i32();
11150 gennarrow(tcg_res
[pass
], tcg_wideres
);
11151 tcg_temp_free_i64(tcg_wideres
);
11154 for (pass
= 0; pass
< 2; pass
++) {
11155 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
+ part
, MO_32
);
11156 tcg_temp_free_i32(tcg_res
[pass
]);
11158 clear_vec_high(s
, is_q
, rd
);
11161 /* AdvSIMD three different
11162 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
11163 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
11164 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
11165 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
11167 static void disas_simd_three_reg_diff(DisasContext
*s
, uint32_t insn
)
11169 /* Instructions in this group fall into three basic classes
11170 * (in each case with the operation working on each element in
11171 * the input vectors):
11172 * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
11174 * (2) wide 64 x 128 -> 128
11175 * (3) narrowing 128 x 128 -> 64
11176 * Here we do initial decode, catch unallocated cases and
11177 * dispatch to separate functions for each class.
11179 int is_q
= extract32(insn
, 30, 1);
11180 int is_u
= extract32(insn
, 29, 1);
11181 int size
= extract32(insn
, 22, 2);
11182 int opcode
= extract32(insn
, 12, 4);
11183 int rm
= extract32(insn
, 16, 5);
11184 int rn
= extract32(insn
, 5, 5);
11185 int rd
= extract32(insn
, 0, 5);
11188 case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
11189 case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
11190 /* 64 x 128 -> 128 */
11192 unallocated_encoding(s
);
11195 if (!fp_access_check(s
)) {
11198 handle_3rd_wide(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
11200 case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
11201 case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
11202 /* 128 x 128 -> 64 */
11204 unallocated_encoding(s
);
11207 if (!fp_access_check(s
)) {
11210 handle_3rd_narrowing(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
11212 case 14: /* PMULL, PMULL2 */
11214 unallocated_encoding(s
);
11218 case 0: /* PMULL.P8 */
11219 if (!fp_access_check(s
)) {
11222 /* The Q field specifies lo/hi half input for this insn. */
11223 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, is_q
,
11224 gen_helper_neon_pmull_h
);
11227 case 3: /* PMULL.P64 */
11228 if (!dc_isar_feature(aa64_pmull
, s
)) {
11229 unallocated_encoding(s
);
11232 if (!fp_access_check(s
)) {
11235 /* The Q field specifies lo/hi half input for this insn. */
11236 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, is_q
,
11237 gen_helper_gvec_pmull_q
);
11241 unallocated_encoding(s
);
11245 case 9: /* SQDMLAL, SQDMLAL2 */
11246 case 11: /* SQDMLSL, SQDMLSL2 */
11247 case 13: /* SQDMULL, SQDMULL2 */
11248 if (is_u
|| size
== 0) {
11249 unallocated_encoding(s
);
11253 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
11254 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
11255 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
11256 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
11257 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
11258 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
11259 case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
11260 /* 64 x 64 -> 128 */
11262 unallocated_encoding(s
);
11265 if (!fp_access_check(s
)) {
11269 handle_3rd_widening(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
11272 /* opcode 15 not allocated */
11273 unallocated_encoding(s
);
11278 /* Logic op (opcode == 3) subgroup of C3.6.16. */
11279 static void disas_simd_3same_logic(DisasContext
*s
, uint32_t insn
)
11281 int rd
= extract32(insn
, 0, 5);
11282 int rn
= extract32(insn
, 5, 5);
11283 int rm
= extract32(insn
, 16, 5);
11284 int size
= extract32(insn
, 22, 2);
11285 bool is_u
= extract32(insn
, 29, 1);
11286 bool is_q
= extract32(insn
, 30, 1);
11288 if (!fp_access_check(s
)) {
11292 switch (size
+ 4 * is_u
) {
11294 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_and
, 0);
11297 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_andc
, 0);
11300 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_or
, 0);
11303 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_orc
, 0);
11306 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_xor
, 0);
11309 case 5: /* BSL bitwise select */
11310 gen_gvec_fn4(s
, is_q
, rd
, rd
, rn
, rm
, tcg_gen_gvec_bitsel
, 0);
11312 case 6: /* BIT, bitwise insert if true */
11313 gen_gvec_fn4(s
, is_q
, rd
, rm
, rn
, rd
, tcg_gen_gvec_bitsel
, 0);
11315 case 7: /* BIF, bitwise insert if false */
11316 gen_gvec_fn4(s
, is_q
, rd
, rm
, rd
, rn
, tcg_gen_gvec_bitsel
, 0);
11320 g_assert_not_reached();
11324 /* Pairwise op subgroup of C3.6.16.
11326 * This is called directly or via the handle_3same_float for float pairwise
11327 * operations where the opcode and size are calculated differently.
11329 static void handle_simd_3same_pair(DisasContext
*s
, int is_q
, int u
, int opcode
,
11330 int size
, int rn
, int rm
, int rd
)
11335 /* Floating point operations need fpst */
11336 if (opcode
>= 0x58) {
11337 fpst
= fpstatus_ptr(FPST_FPCR
);
11342 if (!fp_access_check(s
)) {
11346 /* These operations work on the concatenated rm:rn, with each pair of
11347 * adjacent elements being operated on to produce an element in the result.
11350 TCGv_i64 tcg_res
[2];
11352 for (pass
= 0; pass
< 2; pass
++) {
11353 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11354 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11355 int passreg
= (pass
== 0) ? rn
: rm
;
11357 read_vec_element(s
, tcg_op1
, passreg
, 0, MO_64
);
11358 read_vec_element(s
, tcg_op2
, passreg
, 1, MO_64
);
11359 tcg_res
[pass
] = tcg_temp_new_i64();
11362 case 0x17: /* ADDP */
11363 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
11365 case 0x58: /* FMAXNMP */
11366 gen_helper_vfp_maxnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11368 case 0x5a: /* FADDP */
11369 gen_helper_vfp_addd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11371 case 0x5e: /* FMAXP */
11372 gen_helper_vfp_maxd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11374 case 0x78: /* FMINNMP */
11375 gen_helper_vfp_minnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11377 case 0x7e: /* FMINP */
11378 gen_helper_vfp_mind(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11381 g_assert_not_reached();
11384 tcg_temp_free_i64(tcg_op1
);
11385 tcg_temp_free_i64(tcg_op2
);
11388 for (pass
= 0; pass
< 2; pass
++) {
11389 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11390 tcg_temp_free_i64(tcg_res
[pass
]);
11393 int maxpass
= is_q
? 4 : 2;
11394 TCGv_i32 tcg_res
[4];
11396 for (pass
= 0; pass
< maxpass
; pass
++) {
11397 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11398 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11399 NeonGenTwoOpFn
*genfn
= NULL
;
11400 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
11401 int passelt
= (is_q
&& (pass
& 1)) ? 2 : 0;
11403 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_32
);
11404 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_32
);
11405 tcg_res
[pass
] = tcg_temp_new_i32();
11408 case 0x17: /* ADDP */
11410 static NeonGenTwoOpFn
* const fns
[3] = {
11411 gen_helper_neon_padd_u8
,
11412 gen_helper_neon_padd_u16
,
11418 case 0x14: /* SMAXP, UMAXP */
11420 static NeonGenTwoOpFn
* const fns
[3][2] = {
11421 { gen_helper_neon_pmax_s8
, gen_helper_neon_pmax_u8
},
11422 { gen_helper_neon_pmax_s16
, gen_helper_neon_pmax_u16
},
11423 { tcg_gen_smax_i32
, tcg_gen_umax_i32
},
11425 genfn
= fns
[size
][u
];
11428 case 0x15: /* SMINP, UMINP */
11430 static NeonGenTwoOpFn
* const fns
[3][2] = {
11431 { gen_helper_neon_pmin_s8
, gen_helper_neon_pmin_u8
},
11432 { gen_helper_neon_pmin_s16
, gen_helper_neon_pmin_u16
},
11433 { tcg_gen_smin_i32
, tcg_gen_umin_i32
},
11435 genfn
= fns
[size
][u
];
11438 /* The FP operations are all on single floats (32 bit) */
11439 case 0x58: /* FMAXNMP */
11440 gen_helper_vfp_maxnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11442 case 0x5a: /* FADDP */
11443 gen_helper_vfp_adds(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11445 case 0x5e: /* FMAXP */
11446 gen_helper_vfp_maxs(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11448 case 0x78: /* FMINNMP */
11449 gen_helper_vfp_minnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11451 case 0x7e: /* FMINP */
11452 gen_helper_vfp_mins(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11455 g_assert_not_reached();
11458 /* FP ops called directly, otherwise call now */
11460 genfn(tcg_res
[pass
], tcg_op1
, tcg_op2
);
11463 tcg_temp_free_i32(tcg_op1
);
11464 tcg_temp_free_i32(tcg_op2
);
11467 for (pass
= 0; pass
< maxpass
; pass
++) {
11468 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
11469 tcg_temp_free_i32(tcg_res
[pass
]);
11471 clear_vec_high(s
, is_q
, rd
);
11475 tcg_temp_free_ptr(fpst
);
11479 /* Floating point op subgroup of C3.6.16. */
11480 static void disas_simd_3same_float(DisasContext
*s
, uint32_t insn
)
11482 /* For floating point ops, the U, size[1] and opcode bits
11483 * together indicate the operation. size[0] indicates single
11486 int fpopcode
= extract32(insn
, 11, 5)
11487 | (extract32(insn
, 23, 1) << 5)
11488 | (extract32(insn
, 29, 1) << 6);
11489 int is_q
= extract32(insn
, 30, 1);
11490 int size
= extract32(insn
, 22, 1);
11491 int rm
= extract32(insn
, 16, 5);
11492 int rn
= extract32(insn
, 5, 5);
11493 int rd
= extract32(insn
, 0, 5);
11495 int datasize
= is_q
? 128 : 64;
11496 int esize
= 32 << size
;
11497 int elements
= datasize
/ esize
;
11499 if (size
== 1 && !is_q
) {
11500 unallocated_encoding(s
);
11504 switch (fpopcode
) {
11505 case 0x58: /* FMAXNMP */
11506 case 0x5a: /* FADDP */
11507 case 0x5e: /* FMAXP */
11508 case 0x78: /* FMINNMP */
11509 case 0x7e: /* FMINP */
11510 if (size
&& !is_q
) {
11511 unallocated_encoding(s
);
11514 handle_simd_3same_pair(s
, is_q
, 0, fpopcode
, size
? MO_64
: MO_32
,
11517 case 0x1b: /* FMULX */
11518 case 0x1f: /* FRECPS */
11519 case 0x3f: /* FRSQRTS */
11520 case 0x5d: /* FACGE */
11521 case 0x7d: /* FACGT */
11522 case 0x19: /* FMLA */
11523 case 0x39: /* FMLS */
11524 case 0x18: /* FMAXNM */
11525 case 0x1a: /* FADD */
11526 case 0x1c: /* FCMEQ */
11527 case 0x1e: /* FMAX */
11528 case 0x38: /* FMINNM */
11529 case 0x3a: /* FSUB */
11530 case 0x3e: /* FMIN */
11531 case 0x5b: /* FMUL */
11532 case 0x5c: /* FCMGE */
11533 case 0x5f: /* FDIV */
11534 case 0x7a: /* FABD */
11535 case 0x7c: /* FCMGT */
11536 if (!fp_access_check(s
)) {
11539 handle_3same_float(s
, size
, elements
, fpopcode
, rd
, rn
, rm
);
11542 case 0x1d: /* FMLAL */
11543 case 0x3d: /* FMLSL */
11544 case 0x59: /* FMLAL2 */
11545 case 0x79: /* FMLSL2 */
11546 if (size
& 1 || !dc_isar_feature(aa64_fhm
, s
)) {
11547 unallocated_encoding(s
);
11550 if (fp_access_check(s
)) {
11551 int is_s
= extract32(insn
, 23, 1);
11552 int is_2
= extract32(insn
, 29, 1);
11553 int data
= (is_2
<< 1) | is_s
;
11554 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
11555 vec_full_reg_offset(s
, rn
),
11556 vec_full_reg_offset(s
, rm
), cpu_env
,
11557 is_q
? 16 : 8, vec_full_reg_size(s
),
11558 data
, gen_helper_gvec_fmlal_a64
);
11563 unallocated_encoding(s
);
11568 /* Integer op subgroup of C3.6.16. */
11569 static void disas_simd_3same_int(DisasContext
*s
, uint32_t insn
)
11571 int is_q
= extract32(insn
, 30, 1);
11572 int u
= extract32(insn
, 29, 1);
11573 int size
= extract32(insn
, 22, 2);
11574 int opcode
= extract32(insn
, 11, 5);
11575 int rm
= extract32(insn
, 16, 5);
11576 int rn
= extract32(insn
, 5, 5);
11577 int rd
= extract32(insn
, 0, 5);
11582 case 0x13: /* MUL, PMUL */
11583 if (u
&& size
!= 0) {
11584 unallocated_encoding(s
);
11588 case 0x0: /* SHADD, UHADD */
11589 case 0x2: /* SRHADD, URHADD */
11590 case 0x4: /* SHSUB, UHSUB */
11591 case 0xc: /* SMAX, UMAX */
11592 case 0xd: /* SMIN, UMIN */
11593 case 0xe: /* SABD, UABD */
11594 case 0xf: /* SABA, UABA */
11595 case 0x12: /* MLA, MLS */
11597 unallocated_encoding(s
);
11601 case 0x16: /* SQDMULH, SQRDMULH */
11602 if (size
== 0 || size
== 3) {
11603 unallocated_encoding(s
);
11608 if (size
== 3 && !is_q
) {
11609 unallocated_encoding(s
);
11615 if (!fp_access_check(s
)) {
11620 case 0x01: /* SQADD, UQADD */
11622 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_uqadd_qc
, size
);
11624 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sqadd_qc
, size
);
11627 case 0x05: /* SQSUB, UQSUB */
11629 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_uqsub_qc
, size
);
11631 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sqsub_qc
, size
);
11634 case 0x08: /* SSHL, USHL */
11636 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_ushl
, size
);
11638 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sshl
, size
);
11641 case 0x0c: /* SMAX, UMAX */
11643 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_umax
, size
);
11645 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_smax
, size
);
11648 case 0x0d: /* SMIN, UMIN */
11650 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_umin
, size
);
11652 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_smin
, size
);
11655 case 0xe: /* SABD, UABD */
11657 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_uabd
, size
);
11659 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sabd
, size
);
11662 case 0xf: /* SABA, UABA */
11664 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_uaba
, size
);
11666 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_saba
, size
);
11669 case 0x10: /* ADD, SUB */
11671 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_sub
, size
);
11673 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_add
, size
);
11676 case 0x13: /* MUL, PMUL */
11677 if (!u
) { /* MUL */
11678 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_mul
, size
);
11679 } else { /* PMUL */
11680 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, 0, gen_helper_gvec_pmul_b
);
11683 case 0x12: /* MLA, MLS */
11685 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_mls
, size
);
11687 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_mla
, size
);
11690 case 0x16: /* SQDMULH, SQRDMULH */
11692 static gen_helper_gvec_3_ptr
* const fns
[2][2] = {
11693 { gen_helper_neon_sqdmulh_h
, gen_helper_neon_sqrdmulh_h
},
11694 { gen_helper_neon_sqdmulh_s
, gen_helper_neon_sqrdmulh_s
},
11696 gen_gvec_op3_qc(s
, is_q
, rd
, rn
, rm
, fns
[size
- 1][u
]);
11700 if (!u
) { /* CMTST */
11701 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_cmtst
, size
);
11705 cond
= TCG_COND_EQ
;
11707 case 0x06: /* CMGT, CMHI */
11708 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
11710 case 0x07: /* CMGE, CMHS */
11711 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
11713 tcg_gen_gvec_cmp(cond
, size
, vec_full_reg_offset(s
, rd
),
11714 vec_full_reg_offset(s
, rn
),
11715 vec_full_reg_offset(s
, rm
),
11716 is_q
? 16 : 8, vec_full_reg_size(s
));
11722 for (pass
= 0; pass
< 2; pass
++) {
11723 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11724 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11725 TCGv_i64 tcg_res
= tcg_temp_new_i64();
11727 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
11728 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
11730 handle_3same_64(s
, opcode
, u
, tcg_res
, tcg_op1
, tcg_op2
);
11732 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
11734 tcg_temp_free_i64(tcg_res
);
11735 tcg_temp_free_i64(tcg_op1
);
11736 tcg_temp_free_i64(tcg_op2
);
11739 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
11740 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11741 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11742 TCGv_i32 tcg_res
= tcg_temp_new_i32();
11743 NeonGenTwoOpFn
*genfn
= NULL
;
11744 NeonGenTwoOpEnvFn
*genenvfn
= NULL
;
11746 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
11747 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
11750 case 0x0: /* SHADD, UHADD */
11752 static NeonGenTwoOpFn
* const fns
[3][2] = {
11753 { gen_helper_neon_hadd_s8
, gen_helper_neon_hadd_u8
},
11754 { gen_helper_neon_hadd_s16
, gen_helper_neon_hadd_u16
},
11755 { gen_helper_neon_hadd_s32
, gen_helper_neon_hadd_u32
},
11757 genfn
= fns
[size
][u
];
11760 case 0x2: /* SRHADD, URHADD */
11762 static NeonGenTwoOpFn
* const fns
[3][2] = {
11763 { gen_helper_neon_rhadd_s8
, gen_helper_neon_rhadd_u8
},
11764 { gen_helper_neon_rhadd_s16
, gen_helper_neon_rhadd_u16
},
11765 { gen_helper_neon_rhadd_s32
, gen_helper_neon_rhadd_u32
},
11767 genfn
= fns
[size
][u
];
11770 case 0x4: /* SHSUB, UHSUB */
11772 static NeonGenTwoOpFn
* const fns
[3][2] = {
11773 { gen_helper_neon_hsub_s8
, gen_helper_neon_hsub_u8
},
11774 { gen_helper_neon_hsub_s16
, gen_helper_neon_hsub_u16
},
11775 { gen_helper_neon_hsub_s32
, gen_helper_neon_hsub_u32
},
11777 genfn
= fns
[size
][u
];
11780 case 0x9: /* SQSHL, UQSHL */
11782 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11783 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
11784 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
11785 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
11787 genenvfn
= fns
[size
][u
];
11790 case 0xa: /* SRSHL, URSHL */
11792 static NeonGenTwoOpFn
* const fns
[3][2] = {
11793 { gen_helper_neon_rshl_s8
, gen_helper_neon_rshl_u8
},
11794 { gen_helper_neon_rshl_s16
, gen_helper_neon_rshl_u16
},
11795 { gen_helper_neon_rshl_s32
, gen_helper_neon_rshl_u32
},
11797 genfn
= fns
[size
][u
];
11800 case 0xb: /* SQRSHL, UQRSHL */
11802 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11803 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
11804 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
11805 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
11807 genenvfn
= fns
[size
][u
];
11811 g_assert_not_reached();
11815 genenvfn(tcg_res
, cpu_env
, tcg_op1
, tcg_op2
);
11817 genfn(tcg_res
, tcg_op1
, tcg_op2
);
11820 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
11822 tcg_temp_free_i32(tcg_res
);
11823 tcg_temp_free_i32(tcg_op1
);
11824 tcg_temp_free_i32(tcg_op2
);
11827 clear_vec_high(s
, is_q
, rd
);
11830 /* AdvSIMD three same
11831 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
11832 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11833 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
11834 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11836 static void disas_simd_three_reg_same(DisasContext
*s
, uint32_t insn
)
11838 int opcode
= extract32(insn
, 11, 5);
11841 case 0x3: /* logic ops */
11842 disas_simd_3same_logic(s
, insn
);
11844 case 0x17: /* ADDP */
11845 case 0x14: /* SMAXP, UMAXP */
11846 case 0x15: /* SMINP, UMINP */
11848 /* Pairwise operations */
11849 int is_q
= extract32(insn
, 30, 1);
11850 int u
= extract32(insn
, 29, 1);
11851 int size
= extract32(insn
, 22, 2);
11852 int rm
= extract32(insn
, 16, 5);
11853 int rn
= extract32(insn
, 5, 5);
11854 int rd
= extract32(insn
, 0, 5);
11855 if (opcode
== 0x17) {
11856 if (u
|| (size
== 3 && !is_q
)) {
11857 unallocated_encoding(s
);
11862 unallocated_encoding(s
);
11866 handle_simd_3same_pair(s
, is_q
, u
, opcode
, size
, rn
, rm
, rd
);
11869 case 0x18 ... 0x31:
11870 /* floating point ops, sz[1] and U are part of opcode */
11871 disas_simd_3same_float(s
, insn
);
11874 disas_simd_3same_int(s
, insn
);
11880 * Advanced SIMD three same (ARMv8.2 FP16 variants)
11882 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
11883 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11884 * | 0 | Q | U | 0 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
11885 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11887 * This includes FMULX, FCMEQ (register), FRECPS, FRSQRTS, FCMGE
11888 * (register), FACGE, FABD, FCMGT (register) and FACGT.
11891 static void disas_simd_three_reg_same_fp16(DisasContext
*s
, uint32_t insn
)
11893 int opcode
= extract32(insn
, 11, 3);
11894 int u
= extract32(insn
, 29, 1);
11895 int a
= extract32(insn
, 23, 1);
11896 int is_q
= extract32(insn
, 30, 1);
11897 int rm
= extract32(insn
, 16, 5);
11898 int rn
= extract32(insn
, 5, 5);
11899 int rd
= extract32(insn
, 0, 5);
11901 * For these floating point ops, the U, a and opcode bits
11902 * together indicate the operation.
11904 int fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
11905 int datasize
= is_q
? 128 : 64;
11906 int elements
= datasize
/ 16;
11911 switch (fpopcode
) {
11912 case 0x0: /* FMAXNM */
11913 case 0x1: /* FMLA */
11914 case 0x2: /* FADD */
11915 case 0x3: /* FMULX */
11916 case 0x4: /* FCMEQ */
11917 case 0x6: /* FMAX */
11918 case 0x7: /* FRECPS */
11919 case 0x8: /* FMINNM */
11920 case 0x9: /* FMLS */
11921 case 0xa: /* FSUB */
11922 case 0xe: /* FMIN */
11923 case 0xf: /* FRSQRTS */
11924 case 0x13: /* FMUL */
11925 case 0x14: /* FCMGE */
11926 case 0x15: /* FACGE */
11927 case 0x17: /* FDIV */
11928 case 0x1a: /* FABD */
11929 case 0x1c: /* FCMGT */
11930 case 0x1d: /* FACGT */
11933 case 0x10: /* FMAXNMP */
11934 case 0x12: /* FADDP */
11935 case 0x16: /* FMAXP */
11936 case 0x18: /* FMINNMP */
11937 case 0x1e: /* FMINP */
11941 unallocated_encoding(s
);
11945 if (!dc_isar_feature(aa64_fp16
, s
)) {
11946 unallocated_encoding(s
);
11950 if (!fp_access_check(s
)) {
11954 fpst
= fpstatus_ptr(FPST_FPCR_F16
);
11957 int maxpass
= is_q
? 8 : 4;
11958 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11959 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11960 TCGv_i32 tcg_res
[8];
11962 for (pass
= 0; pass
< maxpass
; pass
++) {
11963 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
11964 int passelt
= (pass
<< 1) & (maxpass
- 1);
11966 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_16
);
11967 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_16
);
11968 tcg_res
[pass
] = tcg_temp_new_i32();
11970 switch (fpopcode
) {
11971 case 0x10: /* FMAXNMP */
11972 gen_helper_advsimd_maxnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
11975 case 0x12: /* FADDP */
11976 gen_helper_advsimd_addh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11978 case 0x16: /* FMAXP */
11979 gen_helper_advsimd_maxh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11981 case 0x18: /* FMINNMP */
11982 gen_helper_advsimd_minnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
11985 case 0x1e: /* FMINP */
11986 gen_helper_advsimd_minh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11989 g_assert_not_reached();
11993 for (pass
= 0; pass
< maxpass
; pass
++) {
11994 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_16
);
11995 tcg_temp_free_i32(tcg_res
[pass
]);
11998 tcg_temp_free_i32(tcg_op1
);
11999 tcg_temp_free_i32(tcg_op2
);
12002 for (pass
= 0; pass
< elements
; pass
++) {
12003 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
12004 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
12005 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12007 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_16
);
12008 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_16
);
12010 switch (fpopcode
) {
12011 case 0x0: /* FMAXNM */
12012 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12014 case 0x1: /* FMLA */
12015 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
12016 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
12019 case 0x2: /* FADD */
12020 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12022 case 0x3: /* FMULX */
12023 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12025 case 0x4: /* FCMEQ */
12026 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12028 case 0x6: /* FMAX */
12029 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12031 case 0x7: /* FRECPS */
12032 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12034 case 0x8: /* FMINNM */
12035 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12037 case 0x9: /* FMLS */
12038 /* As usual for ARM, separate negation for fused multiply-add */
12039 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
12040 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
12041 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
12044 case 0xa: /* FSUB */
12045 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12047 case 0xe: /* FMIN */
12048 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12050 case 0xf: /* FRSQRTS */
12051 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12053 case 0x13: /* FMUL */
12054 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12056 case 0x14: /* FCMGE */
12057 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12059 case 0x15: /* FACGE */
12060 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12062 case 0x17: /* FDIV */
12063 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12065 case 0x1a: /* FABD */
12066 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12067 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
12069 case 0x1c: /* FCMGT */
12070 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12072 case 0x1d: /* FACGT */
12073 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
12076 g_assert_not_reached();
12079 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
12080 tcg_temp_free_i32(tcg_res
);
12081 tcg_temp_free_i32(tcg_op1
);
12082 tcg_temp_free_i32(tcg_op2
);
12086 tcg_temp_free_ptr(fpst
);
12088 clear_vec_high(s
, is_q
, rd
);
12091 /* AdvSIMD three same extra
12092 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
12093 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
12094 * | 0 | Q | U | 0 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
12095 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
12097 static void disas_simd_three_reg_same_extra(DisasContext
*s
, uint32_t insn
)
12099 int rd
= extract32(insn
, 0, 5);
12100 int rn
= extract32(insn
, 5, 5);
12101 int opcode
= extract32(insn
, 11, 4);
12102 int rm
= extract32(insn
, 16, 5);
12103 int size
= extract32(insn
, 22, 2);
12104 bool u
= extract32(insn
, 29, 1);
12105 bool is_q
= extract32(insn
, 30, 1);
12109 switch (u
* 16 + opcode
) {
12110 case 0x10: /* SQRDMLAH (vector) */
12111 case 0x11: /* SQRDMLSH (vector) */
12112 if (size
!= 1 && size
!= 2) {
12113 unallocated_encoding(s
);
12116 feature
= dc_isar_feature(aa64_rdm
, s
);
12118 case 0x02: /* SDOT (vector) */
12119 case 0x12: /* UDOT (vector) */
12120 if (size
!= MO_32
) {
12121 unallocated_encoding(s
);
12124 feature
= dc_isar_feature(aa64_dp
, s
);
12126 case 0x03: /* USDOT */
12127 if (size
!= MO_32
) {
12128 unallocated_encoding(s
);
12131 feature
= dc_isar_feature(aa64_i8mm
, s
);
12133 case 0x04: /* SMMLA */
12134 case 0x14: /* UMMLA */
12135 case 0x05: /* USMMLA */
12136 if (!is_q
|| size
!= MO_32
) {
12137 unallocated_encoding(s
);
12140 feature
= dc_isar_feature(aa64_i8mm
, s
);
12142 case 0x18: /* FCMLA, #0 */
12143 case 0x19: /* FCMLA, #90 */
12144 case 0x1a: /* FCMLA, #180 */
12145 case 0x1b: /* FCMLA, #270 */
12146 case 0x1c: /* FCADD, #90 */
12147 case 0x1e: /* FCADD, #270 */
12149 || (size
== 1 && !dc_isar_feature(aa64_fp16
, s
))
12150 || (size
== 3 && !is_q
)) {
12151 unallocated_encoding(s
);
12154 feature
= dc_isar_feature(aa64_fcma
, s
);
12156 case 0x1d: /* BFMMLA */
12157 if (size
!= MO_16
|| !is_q
) {
12158 unallocated_encoding(s
);
12161 feature
= dc_isar_feature(aa64_bf16
, s
);
12165 case 1: /* BFDOT */
12166 case 3: /* BFMLAL{B,T} */
12167 feature
= dc_isar_feature(aa64_bf16
, s
);
12170 unallocated_encoding(s
);
12175 unallocated_encoding(s
);
12179 unallocated_encoding(s
);
12182 if (!fp_access_check(s
)) {
12187 case 0x0: /* SQRDMLAH (vector) */
12188 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sqrdmlah_qc
, size
);
12191 case 0x1: /* SQRDMLSH (vector) */
12192 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sqrdmlsh_qc
, size
);
12195 case 0x2: /* SDOT / UDOT */
12196 gen_gvec_op4_ool(s
, is_q
, rd
, rn
, rm
, rd
, 0,
12197 u
? gen_helper_gvec_udot_b
: gen_helper_gvec_sdot_b
);
12200 case 0x3: /* USDOT */
12201 gen_gvec_op4_ool(s
, is_q
, rd
, rn
, rm
, rd
, 0, gen_helper_gvec_usdot_b
);
12204 case 0x04: /* SMMLA, UMMLA */
12205 gen_gvec_op4_ool(s
, 1, rd
, rn
, rm
, rd
, 0,
12206 u
? gen_helper_gvec_ummla_b
12207 : gen_helper_gvec_smmla_b
);
12209 case 0x05: /* USMMLA */
12210 gen_gvec_op4_ool(s
, 1, rd
, rn
, rm
, rd
, 0, gen_helper_gvec_usmmla_b
);
12213 case 0x8: /* FCMLA, #0 */
12214 case 0x9: /* FCMLA, #90 */
12215 case 0xa: /* FCMLA, #180 */
12216 case 0xb: /* FCMLA, #270 */
12217 rot
= extract32(opcode
, 0, 2);
12220 gen_gvec_op4_fpst(s
, is_q
, rd
, rn
, rm
, rd
, true, rot
,
12221 gen_helper_gvec_fcmlah
);
12224 gen_gvec_op4_fpst(s
, is_q
, rd
, rn
, rm
, rd
, false, rot
,
12225 gen_helper_gvec_fcmlas
);
12228 gen_gvec_op4_fpst(s
, is_q
, rd
, rn
, rm
, rd
, false, rot
,
12229 gen_helper_gvec_fcmlad
);
12232 g_assert_not_reached();
12236 case 0xc: /* FCADD, #90 */
12237 case 0xe: /* FCADD, #270 */
12238 rot
= extract32(opcode
, 1, 1);
12241 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
12242 gen_helper_gvec_fcaddh
);
12245 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
12246 gen_helper_gvec_fcadds
);
12249 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
12250 gen_helper_gvec_fcaddd
);
12253 g_assert_not_reached();
12257 case 0xd: /* BFMMLA */
12258 gen_gvec_op4_ool(s
, is_q
, rd
, rn
, rm
, rd
, 0, gen_helper_gvec_bfmmla
);
12262 case 1: /* BFDOT */
12263 gen_gvec_op4_ool(s
, is_q
, rd
, rn
, rm
, rd
, 0, gen_helper_gvec_bfdot
);
12265 case 3: /* BFMLAL{B,T} */
12266 gen_gvec_op4_fpst(s
, 1, rd
, rn
, rm
, rd
, false, is_q
,
12267 gen_helper_gvec_bfmlal
);
12270 g_assert_not_reached();
12275 g_assert_not_reached();
12279 static void handle_2misc_widening(DisasContext
*s
, int opcode
, bool is_q
,
12280 int size
, int rn
, int rd
)
12282 /* Handle 2-reg-misc ops which are widening (so each size element
12283 * in the source becomes a 2*size element in the destination.
12284 * The only instruction like this is FCVTL.
12289 /* 32 -> 64 bit fp conversion */
12290 TCGv_i64 tcg_res
[2];
12291 int srcelt
= is_q
? 2 : 0;
12293 for (pass
= 0; pass
< 2; pass
++) {
12294 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12295 tcg_res
[pass
] = tcg_temp_new_i64();
12297 read_vec_element_i32(s
, tcg_op
, rn
, srcelt
+ pass
, MO_32
);
12298 gen_helper_vfp_fcvtds(tcg_res
[pass
], tcg_op
, cpu_env
);
12299 tcg_temp_free_i32(tcg_op
);
12301 for (pass
= 0; pass
< 2; pass
++) {
12302 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
12303 tcg_temp_free_i64(tcg_res
[pass
]);
12306 /* 16 -> 32 bit fp conversion */
12307 int srcelt
= is_q
? 4 : 0;
12308 TCGv_i32 tcg_res
[4];
12309 TCGv_ptr fpst
= fpstatus_ptr(FPST_FPCR
);
12310 TCGv_i32 ahp
= get_ahp_flag();
12312 for (pass
= 0; pass
< 4; pass
++) {
12313 tcg_res
[pass
] = tcg_temp_new_i32();
12315 read_vec_element_i32(s
, tcg_res
[pass
], rn
, srcelt
+ pass
, MO_16
);
12316 gen_helper_vfp_fcvt_f16_to_f32(tcg_res
[pass
], tcg_res
[pass
],
12319 for (pass
= 0; pass
< 4; pass
++) {
12320 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
12321 tcg_temp_free_i32(tcg_res
[pass
]);
12324 tcg_temp_free_ptr(fpst
);
12325 tcg_temp_free_i32(ahp
);
12329 static void handle_rev(DisasContext
*s
, int opcode
, bool u
,
12330 bool is_q
, int size
, int rn
, int rd
)
12332 int op
= (opcode
<< 1) | u
;
12333 int opsz
= op
+ size
;
12334 int grp_size
= 3 - opsz
;
12335 int dsize
= is_q
? 128 : 64;
12339 unallocated_encoding(s
);
12343 if (!fp_access_check(s
)) {
12348 /* Special case bytes, use bswap op on each group of elements */
12349 int groups
= dsize
/ (8 << grp_size
);
12351 for (i
= 0; i
< groups
; i
++) {
12352 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
12354 read_vec_element(s
, tcg_tmp
, rn
, i
, grp_size
);
12355 switch (grp_size
) {
12357 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
, TCG_BSWAP_IZ
);
12360 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
, TCG_BSWAP_IZ
);
12363 tcg_gen_bswap64_i64(tcg_tmp
, tcg_tmp
);
12366 g_assert_not_reached();
12368 write_vec_element(s
, tcg_tmp
, rd
, i
, grp_size
);
12369 tcg_temp_free_i64(tcg_tmp
);
12371 clear_vec_high(s
, is_q
, rd
);
12373 int revmask
= (1 << grp_size
) - 1;
12374 int esize
= 8 << size
;
12375 int elements
= dsize
/ esize
;
12376 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
12377 TCGv_i64 tcg_rd
= tcg_const_i64(0);
12378 TCGv_i64 tcg_rd_hi
= tcg_const_i64(0);
12380 for (i
= 0; i
< elements
; i
++) {
12381 int e_rev
= (i
& 0xf) ^ revmask
;
12382 int off
= e_rev
* esize
;
12383 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
12385 tcg_gen_deposit_i64(tcg_rd_hi
, tcg_rd_hi
,
12386 tcg_rn
, off
- 64, esize
);
12388 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, off
, esize
);
12391 write_vec_element(s
, tcg_rd
, rd
, 0, MO_64
);
12392 write_vec_element(s
, tcg_rd_hi
, rd
, 1, MO_64
);
12394 tcg_temp_free_i64(tcg_rd_hi
);
12395 tcg_temp_free_i64(tcg_rd
);
12396 tcg_temp_free_i64(tcg_rn
);
12400 static void handle_2misc_pairwise(DisasContext
*s
, int opcode
, bool u
,
12401 bool is_q
, int size
, int rn
, int rd
)
12403 /* Implement the pairwise operations from 2-misc:
12404 * SADDLP, UADDLP, SADALP, UADALP.
12405 * These all add pairs of elements in the input to produce a
12406 * double-width result element in the output (possibly accumulating).
12408 bool accum
= (opcode
== 0x6);
12409 int maxpass
= is_q
? 2 : 1;
12411 TCGv_i64 tcg_res
[2];
12414 /* 32 + 32 -> 64 op */
12415 MemOp memop
= size
+ (u
? 0 : MO_SIGN
);
12417 for (pass
= 0; pass
< maxpass
; pass
++) {
12418 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
12419 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
12421 tcg_res
[pass
] = tcg_temp_new_i64();
12423 read_vec_element(s
, tcg_op1
, rn
, pass
* 2, memop
);
12424 read_vec_element(s
, tcg_op2
, rn
, pass
* 2 + 1, memop
);
12425 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
12427 read_vec_element(s
, tcg_op1
, rd
, pass
, MO_64
);
12428 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
12431 tcg_temp_free_i64(tcg_op1
);
12432 tcg_temp_free_i64(tcg_op2
);
12435 for (pass
= 0; pass
< maxpass
; pass
++) {
12436 TCGv_i64 tcg_op
= tcg_temp_new_i64();
12437 NeonGenOne64OpFn
*genfn
;
12438 static NeonGenOne64OpFn
* const fns
[2][2] = {
12439 { gen_helper_neon_addlp_s8
, gen_helper_neon_addlp_u8
},
12440 { gen_helper_neon_addlp_s16
, gen_helper_neon_addlp_u16
},
12443 genfn
= fns
[size
][u
];
12445 tcg_res
[pass
] = tcg_temp_new_i64();
12447 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
12448 genfn(tcg_res
[pass
], tcg_op
);
12451 read_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
12453 gen_helper_neon_addl_u16(tcg_res
[pass
],
12454 tcg_res
[pass
], tcg_op
);
12456 gen_helper_neon_addl_u32(tcg_res
[pass
],
12457 tcg_res
[pass
], tcg_op
);
12460 tcg_temp_free_i64(tcg_op
);
12464 tcg_res
[1] = tcg_const_i64(0);
12466 for (pass
= 0; pass
< 2; pass
++) {
12467 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
12468 tcg_temp_free_i64(tcg_res
[pass
]);
12472 static void handle_shll(DisasContext
*s
, bool is_q
, int size
, int rn
, int rd
)
12474 /* Implement SHLL and SHLL2 */
12476 int part
= is_q
? 2 : 0;
12477 TCGv_i64 tcg_res
[2];
12479 for (pass
= 0; pass
< 2; pass
++) {
12480 static NeonGenWidenFn
* const widenfns
[3] = {
12481 gen_helper_neon_widen_u8
,
12482 gen_helper_neon_widen_u16
,
12483 tcg_gen_extu_i32_i64
,
12485 NeonGenWidenFn
*widenfn
= widenfns
[size
];
12486 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12488 read_vec_element_i32(s
, tcg_op
, rn
, part
+ pass
, MO_32
);
12489 tcg_res
[pass
] = tcg_temp_new_i64();
12490 widenfn(tcg_res
[pass
], tcg_op
);
12491 tcg_gen_shli_i64(tcg_res
[pass
], tcg_res
[pass
], 8 << size
);
12493 tcg_temp_free_i32(tcg_op
);
12496 for (pass
= 0; pass
< 2; pass
++) {
12497 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
12498 tcg_temp_free_i64(tcg_res
[pass
]);
12502 /* AdvSIMD two reg misc
12503 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
12504 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
12505 * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
12506 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
12508 static void disas_simd_two_reg_misc(DisasContext
*s
, uint32_t insn
)
12510 int size
= extract32(insn
, 22, 2);
12511 int opcode
= extract32(insn
, 12, 5);
12512 bool u
= extract32(insn
, 29, 1);
12513 bool is_q
= extract32(insn
, 30, 1);
12514 int rn
= extract32(insn
, 5, 5);
12515 int rd
= extract32(insn
, 0, 5);
12516 bool need_fpstatus
= false;
12517 bool need_rmode
= false;
12519 TCGv_i32 tcg_rmode
;
12520 TCGv_ptr tcg_fpstatus
;
12523 case 0x0: /* REV64, REV32 */
12524 case 0x1: /* REV16 */
12525 handle_rev(s
, opcode
, u
, is_q
, size
, rn
, rd
);
12527 case 0x5: /* CNT, NOT, RBIT */
12528 if (u
&& size
== 0) {
12531 } else if (u
&& size
== 1) {
12534 } else if (!u
&& size
== 0) {
12538 unallocated_encoding(s
);
12540 case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
12541 case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
12543 unallocated_encoding(s
);
12546 if (!fp_access_check(s
)) {
12550 handle_2misc_narrow(s
, false, opcode
, u
, is_q
, size
, rn
, rd
);
12552 case 0x4: /* CLS, CLZ */
12554 unallocated_encoding(s
);
12558 case 0x2: /* SADDLP, UADDLP */
12559 case 0x6: /* SADALP, UADALP */
12561 unallocated_encoding(s
);
12564 if (!fp_access_check(s
)) {
12567 handle_2misc_pairwise(s
, opcode
, u
, is_q
, size
, rn
, rd
);
12569 case 0x13: /* SHLL, SHLL2 */
12570 if (u
== 0 || size
== 3) {
12571 unallocated_encoding(s
);
12574 if (!fp_access_check(s
)) {
12577 handle_shll(s
, is_q
, size
, rn
, rd
);
12579 case 0xa: /* CMLT */
12581 unallocated_encoding(s
);
12585 case 0x8: /* CMGT, CMGE */
12586 case 0x9: /* CMEQ, CMLE */
12587 case 0xb: /* ABS, NEG */
12588 if (size
== 3 && !is_q
) {
12589 unallocated_encoding(s
);
12593 case 0x3: /* SUQADD, USQADD */
12594 if (size
== 3 && !is_q
) {
12595 unallocated_encoding(s
);
12598 if (!fp_access_check(s
)) {
12601 handle_2misc_satacc(s
, false, u
, is_q
, size
, rn
, rd
);
12603 case 0x7: /* SQABS, SQNEG */
12604 if (size
== 3 && !is_q
) {
12605 unallocated_encoding(s
);
12610 case 0x16 ... 0x1f:
12612 /* Floating point: U, size[1] and opcode indicate operation;
12613 * size[0] indicates single or double precision.
12615 int is_double
= extract32(size
, 0, 1);
12616 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
12617 size
= is_double
? 3 : 2;
12619 case 0x2f: /* FABS */
12620 case 0x6f: /* FNEG */
12621 if (size
== 3 && !is_q
) {
12622 unallocated_encoding(s
);
12626 case 0x1d: /* SCVTF */
12627 case 0x5d: /* UCVTF */
12629 bool is_signed
= (opcode
== 0x1d) ? true : false;
12630 int elements
= is_double
? 2 : is_q
? 4 : 2;
12631 if (is_double
&& !is_q
) {
12632 unallocated_encoding(s
);
12635 if (!fp_access_check(s
)) {
12638 handle_simd_intfp_conv(s
, rd
, rn
, elements
, is_signed
, 0, size
);
12641 case 0x2c: /* FCMGT (zero) */
12642 case 0x2d: /* FCMEQ (zero) */
12643 case 0x2e: /* FCMLT (zero) */
12644 case 0x6c: /* FCMGE (zero) */
12645 case 0x6d: /* FCMLE (zero) */
12646 if (size
== 3 && !is_q
) {
12647 unallocated_encoding(s
);
12650 handle_2misc_fcmp_zero(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
12652 case 0x7f: /* FSQRT */
12653 if (size
== 3 && !is_q
) {
12654 unallocated_encoding(s
);
12658 case 0x1a: /* FCVTNS */
12659 case 0x1b: /* FCVTMS */
12660 case 0x3a: /* FCVTPS */
12661 case 0x3b: /* FCVTZS */
12662 case 0x5a: /* FCVTNU */
12663 case 0x5b: /* FCVTMU */
12664 case 0x7a: /* FCVTPU */
12665 case 0x7b: /* FCVTZU */
12666 need_fpstatus
= true;
12668 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
12669 if (size
== 3 && !is_q
) {
12670 unallocated_encoding(s
);
12674 case 0x5c: /* FCVTAU */
12675 case 0x1c: /* FCVTAS */
12676 need_fpstatus
= true;
12678 rmode
= FPROUNDING_TIEAWAY
;
12679 if (size
== 3 && !is_q
) {
12680 unallocated_encoding(s
);
12684 case 0x3c: /* URECPE */
12686 unallocated_encoding(s
);
12690 case 0x3d: /* FRECPE */
12691 case 0x7d: /* FRSQRTE */
12692 if (size
== 3 && !is_q
) {
12693 unallocated_encoding(s
);
12696 if (!fp_access_check(s
)) {
12699 handle_2misc_reciprocal(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
12701 case 0x56: /* FCVTXN, FCVTXN2 */
12703 unallocated_encoding(s
);
12707 case 0x16: /* FCVTN, FCVTN2 */
12708 /* handle_2misc_narrow does a 2*size -> size operation, but these
12709 * instructions encode the source size rather than dest size.
12711 if (!fp_access_check(s
)) {
12714 handle_2misc_narrow(s
, false, opcode
, 0, is_q
, size
- 1, rn
, rd
);
12716 case 0x36: /* BFCVTN, BFCVTN2 */
12717 if (!dc_isar_feature(aa64_bf16
, s
) || size
!= 2) {
12718 unallocated_encoding(s
);
12721 if (!fp_access_check(s
)) {
12724 handle_2misc_narrow(s
, false, opcode
, 0, is_q
, size
- 1, rn
, rd
);
12726 case 0x17: /* FCVTL, FCVTL2 */
12727 if (!fp_access_check(s
)) {
12730 handle_2misc_widening(s
, opcode
, is_q
, size
, rn
, rd
);
12732 case 0x18: /* FRINTN */
12733 case 0x19: /* FRINTM */
12734 case 0x38: /* FRINTP */
12735 case 0x39: /* FRINTZ */
12737 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
12739 case 0x59: /* FRINTX */
12740 case 0x79: /* FRINTI */
12741 need_fpstatus
= true;
12742 if (size
== 3 && !is_q
) {
12743 unallocated_encoding(s
);
12747 case 0x58: /* FRINTA */
12749 rmode
= FPROUNDING_TIEAWAY
;
12750 need_fpstatus
= true;
12751 if (size
== 3 && !is_q
) {
12752 unallocated_encoding(s
);
12756 case 0x7c: /* URSQRTE */
12758 unallocated_encoding(s
);
12762 case 0x1e: /* FRINT32Z */
12763 case 0x1f: /* FRINT64Z */
12765 rmode
= FPROUNDING_ZERO
;
12767 case 0x5e: /* FRINT32X */
12768 case 0x5f: /* FRINT64X */
12769 need_fpstatus
= true;
12770 if ((size
== 3 && !is_q
) || !dc_isar_feature(aa64_frint
, s
)) {
12771 unallocated_encoding(s
);
12776 unallocated_encoding(s
);
12782 unallocated_encoding(s
);
12786 if (!fp_access_check(s
)) {
12790 if (need_fpstatus
|| need_rmode
) {
12791 tcg_fpstatus
= fpstatus_ptr(FPST_FPCR
);
12793 tcg_fpstatus
= NULL
;
12796 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
12797 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12804 if (u
&& size
== 0) { /* NOT */
12805 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_not
, 0);
12809 case 0x8: /* CMGT, CMGE */
12811 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_cge0
, size
);
12813 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_cgt0
, size
);
12816 case 0x9: /* CMEQ, CMLE */
12818 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_cle0
, size
);
12820 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_ceq0
, size
);
12823 case 0xa: /* CMLT */
12824 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_clt0
, size
);
12827 if (u
) { /* ABS, NEG */
12828 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_neg
, size
);
12830 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_abs
, size
);
12836 /* All 64-bit element operations can be shared with scalar 2misc */
12839 /* Coverity claims (size == 3 && !is_q) has been eliminated
12840 * from all paths leading to here.
12842 tcg_debug_assert(is_q
);
12843 for (pass
= 0; pass
< 2; pass
++) {
12844 TCGv_i64 tcg_op
= tcg_temp_new_i64();
12845 TCGv_i64 tcg_res
= tcg_temp_new_i64();
12847 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
12849 handle_2misc_64(s
, opcode
, u
, tcg_res
, tcg_op
,
12850 tcg_rmode
, tcg_fpstatus
);
12852 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
12854 tcg_temp_free_i64(tcg_res
);
12855 tcg_temp_free_i64(tcg_op
);
12860 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
12861 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12862 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12864 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
12867 /* Special cases for 32 bit elements */
12869 case 0x4: /* CLS */
12871 tcg_gen_clzi_i32(tcg_res
, tcg_op
, 32);
12873 tcg_gen_clrsb_i32(tcg_res
, tcg_op
);
12876 case 0x7: /* SQABS, SQNEG */
12878 gen_helper_neon_qneg_s32(tcg_res
, cpu_env
, tcg_op
);
12880 gen_helper_neon_qabs_s32(tcg_res
, cpu_env
, tcg_op
);
12883 case 0x2f: /* FABS */
12884 gen_helper_vfp_abss(tcg_res
, tcg_op
);
12886 case 0x6f: /* FNEG */
12887 gen_helper_vfp_negs(tcg_res
, tcg_op
);
12889 case 0x7f: /* FSQRT */
12890 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
12892 case 0x1a: /* FCVTNS */
12893 case 0x1b: /* FCVTMS */
12894 case 0x1c: /* FCVTAS */
12895 case 0x3a: /* FCVTPS */
12896 case 0x3b: /* FCVTZS */
12898 TCGv_i32 tcg_shift
= tcg_const_i32(0);
12899 gen_helper_vfp_tosls(tcg_res
, tcg_op
,
12900 tcg_shift
, tcg_fpstatus
);
12901 tcg_temp_free_i32(tcg_shift
);
12904 case 0x5a: /* FCVTNU */
12905 case 0x5b: /* FCVTMU */
12906 case 0x5c: /* FCVTAU */
12907 case 0x7a: /* FCVTPU */
12908 case 0x7b: /* FCVTZU */
12910 TCGv_i32 tcg_shift
= tcg_const_i32(0);
12911 gen_helper_vfp_touls(tcg_res
, tcg_op
,
12912 tcg_shift
, tcg_fpstatus
);
12913 tcg_temp_free_i32(tcg_shift
);
12916 case 0x18: /* FRINTN */
12917 case 0x19: /* FRINTM */
12918 case 0x38: /* FRINTP */
12919 case 0x39: /* FRINTZ */
12920 case 0x58: /* FRINTA */
12921 case 0x79: /* FRINTI */
12922 gen_helper_rints(tcg_res
, tcg_op
, tcg_fpstatus
);
12924 case 0x59: /* FRINTX */
12925 gen_helper_rints_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
12927 case 0x7c: /* URSQRTE */
12928 gen_helper_rsqrte_u32(tcg_res
, tcg_op
);
12930 case 0x1e: /* FRINT32Z */
12931 case 0x5e: /* FRINT32X */
12932 gen_helper_frint32_s(tcg_res
, tcg_op
, tcg_fpstatus
);
12934 case 0x1f: /* FRINT64Z */
12935 case 0x5f: /* FRINT64X */
12936 gen_helper_frint64_s(tcg_res
, tcg_op
, tcg_fpstatus
);
12939 g_assert_not_reached();
12942 /* Use helpers for 8 and 16 bit elements */
12944 case 0x5: /* CNT, RBIT */
12945 /* For these two insns size is part of the opcode specifier
12946 * (handled earlier); they always operate on byte elements.
12949 gen_helper_neon_rbit_u8(tcg_res
, tcg_op
);
12951 gen_helper_neon_cnt_u8(tcg_res
, tcg_op
);
12954 case 0x7: /* SQABS, SQNEG */
12956 NeonGenOneOpEnvFn
*genfn
;
12957 static NeonGenOneOpEnvFn
* const fns
[2][2] = {
12958 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
12959 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
12961 genfn
= fns
[size
][u
];
12962 genfn(tcg_res
, cpu_env
, tcg_op
);
12965 case 0x4: /* CLS, CLZ */
12968 gen_helper_neon_clz_u8(tcg_res
, tcg_op
);
12970 gen_helper_neon_clz_u16(tcg_res
, tcg_op
);
12974 gen_helper_neon_cls_s8(tcg_res
, tcg_op
);
12976 gen_helper_neon_cls_s16(tcg_res
, tcg_op
);
12981 g_assert_not_reached();
12985 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
12987 tcg_temp_free_i32(tcg_res
);
12988 tcg_temp_free_i32(tcg_op
);
12991 clear_vec_high(s
, is_q
, rd
);
12994 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12995 tcg_temp_free_i32(tcg_rmode
);
12997 if (need_fpstatus
) {
12998 tcg_temp_free_ptr(tcg_fpstatus
);
13002 /* AdvSIMD [scalar] two register miscellaneous (FP16)
13004 * 31 30 29 28 27 24 23 22 21 17 16 12 11 10 9 5 4 0
13005 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
13006 * | 0 | Q | U | S | 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 | Rn | Rd |
13007 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
13008 * mask: 1000 1111 0111 1110 0000 1100 0000 0000 0x8f7e 0c00
13009 * val: 0000 1110 0111 1000 0000 1000 0000 0000 0x0e78 0800
13011 * This actually covers two groups where scalar access is governed by
13012 * bit 28. A bunch of the instructions (float to integral) only exist
13013 * in the vector form and are un-allocated for the scalar decode. Also
13014 * in the scalar decode Q is always 1.
13016 static void disas_simd_two_reg_misc_fp16(DisasContext
*s
, uint32_t insn
)
13018 int fpop
, opcode
, a
, u
;
13022 bool only_in_vector
= false;
13025 TCGv_i32 tcg_rmode
= NULL
;
13026 TCGv_ptr tcg_fpstatus
= NULL
;
13027 bool need_rmode
= false;
13028 bool need_fpst
= true;
13031 if (!dc_isar_feature(aa64_fp16
, s
)) {
13032 unallocated_encoding(s
);
13036 rd
= extract32(insn
, 0, 5);
13037 rn
= extract32(insn
, 5, 5);
13039 a
= extract32(insn
, 23, 1);
13040 u
= extract32(insn
, 29, 1);
13041 is_scalar
= extract32(insn
, 28, 1);
13042 is_q
= extract32(insn
, 30, 1);
13044 opcode
= extract32(insn
, 12, 5);
13045 fpop
= deposit32(opcode
, 5, 1, a
);
13046 fpop
= deposit32(fpop
, 6, 1, u
);
13049 case 0x1d: /* SCVTF */
13050 case 0x5d: /* UCVTF */
13057 elements
= (is_q
? 8 : 4);
13060 if (!fp_access_check(s
)) {
13063 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !u
, 0, MO_16
);
13067 case 0x2c: /* FCMGT (zero) */
13068 case 0x2d: /* FCMEQ (zero) */
13069 case 0x2e: /* FCMLT (zero) */
13070 case 0x6c: /* FCMGE (zero) */
13071 case 0x6d: /* FCMLE (zero) */
13072 handle_2misc_fcmp_zero(s
, fpop
, is_scalar
, 0, is_q
, MO_16
, rn
, rd
);
13074 case 0x3d: /* FRECPE */
13075 case 0x3f: /* FRECPX */
13077 case 0x18: /* FRINTN */
13079 only_in_vector
= true;
13080 rmode
= FPROUNDING_TIEEVEN
;
13082 case 0x19: /* FRINTM */
13084 only_in_vector
= true;
13085 rmode
= FPROUNDING_NEGINF
;
13087 case 0x38: /* FRINTP */
13089 only_in_vector
= true;
13090 rmode
= FPROUNDING_POSINF
;
13092 case 0x39: /* FRINTZ */
13094 only_in_vector
= true;
13095 rmode
= FPROUNDING_ZERO
;
13097 case 0x58: /* FRINTA */
13099 only_in_vector
= true;
13100 rmode
= FPROUNDING_TIEAWAY
;
13102 case 0x59: /* FRINTX */
13103 case 0x79: /* FRINTI */
13104 only_in_vector
= true;
13105 /* current rounding mode */
13107 case 0x1a: /* FCVTNS */
13109 rmode
= FPROUNDING_TIEEVEN
;
13111 case 0x1b: /* FCVTMS */
13113 rmode
= FPROUNDING_NEGINF
;
13115 case 0x1c: /* FCVTAS */
13117 rmode
= FPROUNDING_TIEAWAY
;
13119 case 0x3a: /* FCVTPS */
13121 rmode
= FPROUNDING_POSINF
;
13123 case 0x3b: /* FCVTZS */
13125 rmode
= FPROUNDING_ZERO
;
13127 case 0x5a: /* FCVTNU */
13129 rmode
= FPROUNDING_TIEEVEN
;
13131 case 0x5b: /* FCVTMU */
13133 rmode
= FPROUNDING_NEGINF
;
13135 case 0x5c: /* FCVTAU */
13137 rmode
= FPROUNDING_TIEAWAY
;
13139 case 0x7a: /* FCVTPU */
13141 rmode
= FPROUNDING_POSINF
;
13143 case 0x7b: /* FCVTZU */
13145 rmode
= FPROUNDING_ZERO
;
13147 case 0x2f: /* FABS */
13148 case 0x6f: /* FNEG */
13151 case 0x7d: /* FRSQRTE */
13152 case 0x7f: /* FSQRT (vector) */
13155 unallocated_encoding(s
);
13160 /* Check additional constraints for the scalar encoding */
13163 unallocated_encoding(s
);
13166 /* FRINTxx is only in the vector form */
13167 if (only_in_vector
) {
13168 unallocated_encoding(s
);
13173 if (!fp_access_check(s
)) {
13177 if (need_rmode
|| need_fpst
) {
13178 tcg_fpstatus
= fpstatus_ptr(FPST_FPCR_F16
);
13182 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
13183 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
13187 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
13188 TCGv_i32 tcg_res
= tcg_temp_new_i32();
13191 case 0x1a: /* FCVTNS */
13192 case 0x1b: /* FCVTMS */
13193 case 0x1c: /* FCVTAS */
13194 case 0x3a: /* FCVTPS */
13195 case 0x3b: /* FCVTZS */
13196 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
13198 case 0x3d: /* FRECPE */
13199 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
13201 case 0x3f: /* FRECPX */
13202 gen_helper_frecpx_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
13204 case 0x5a: /* FCVTNU */
13205 case 0x5b: /* FCVTMU */
13206 case 0x5c: /* FCVTAU */
13207 case 0x7a: /* FCVTPU */
13208 case 0x7b: /* FCVTZU */
13209 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
13211 case 0x6f: /* FNEG */
13212 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
13214 case 0x7d: /* FRSQRTE */
13215 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
13218 g_assert_not_reached();
13221 /* limit any sign extension going on */
13222 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0xffff);
13223 write_fp_sreg(s
, rd
, tcg_res
);
13225 tcg_temp_free_i32(tcg_res
);
13226 tcg_temp_free_i32(tcg_op
);
13228 for (pass
= 0; pass
< (is_q
? 8 : 4); pass
++) {
13229 TCGv_i32 tcg_op
= tcg_temp_new_i32();
13230 TCGv_i32 tcg_res
= tcg_temp_new_i32();
13232 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_16
);
13235 case 0x1a: /* FCVTNS */
13236 case 0x1b: /* FCVTMS */
13237 case 0x1c: /* FCVTAS */
13238 case 0x3a: /* FCVTPS */
13239 case 0x3b: /* FCVTZS */
13240 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
13242 case 0x3d: /* FRECPE */
13243 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
13245 case 0x5a: /* FCVTNU */
13246 case 0x5b: /* FCVTMU */
13247 case 0x5c: /* FCVTAU */
13248 case 0x7a: /* FCVTPU */
13249 case 0x7b: /* FCVTZU */
13250 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
13252 case 0x18: /* FRINTN */
13253 case 0x19: /* FRINTM */
13254 case 0x38: /* FRINTP */
13255 case 0x39: /* FRINTZ */
13256 case 0x58: /* FRINTA */
13257 case 0x79: /* FRINTI */
13258 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, tcg_fpstatus
);
13260 case 0x59: /* FRINTX */
13261 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
13263 case 0x2f: /* FABS */
13264 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
13266 case 0x6f: /* FNEG */
13267 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
13269 case 0x7d: /* FRSQRTE */
13270 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
13272 case 0x7f: /* FSQRT */
13273 gen_helper_sqrt_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
13276 g_assert_not_reached();
13279 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
13281 tcg_temp_free_i32(tcg_res
);
13282 tcg_temp_free_i32(tcg_op
);
13285 clear_vec_high(s
, is_q
, rd
);
13289 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
13290 tcg_temp_free_i32(tcg_rmode
);
13293 if (tcg_fpstatus
) {
13294 tcg_temp_free_ptr(tcg_fpstatus
);
13298 /* AdvSIMD scalar x indexed element
13299 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
13300 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
13301 * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
13302 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
13303 * AdvSIMD vector x indexed element
13304 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
13305 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
13306 * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
13307 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
13309 static void disas_simd_indexed(DisasContext
*s
, uint32_t insn
)
13311 /* This encoding has two kinds of instruction:
13312 * normal, where we perform elt x idxelt => elt for each
13313 * element in the vector
13314 * long, where we perform elt x idxelt and generate a result of
13315 * double the width of the input element
13316 * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
13318 bool is_scalar
= extract32(insn
, 28, 1);
13319 bool is_q
= extract32(insn
, 30, 1);
13320 bool u
= extract32(insn
, 29, 1);
13321 int size
= extract32(insn
, 22, 2);
13322 int l
= extract32(insn
, 21, 1);
13323 int m
= extract32(insn
, 20, 1);
13324 /* Note that the Rm field here is only 4 bits, not 5 as it usually is */
13325 int rm
= extract32(insn
, 16, 4);
13326 int opcode
= extract32(insn
, 12, 4);
13327 int h
= extract32(insn
, 11, 1);
13328 int rn
= extract32(insn
, 5, 5);
13329 int rd
= extract32(insn
, 0, 5);
13330 bool is_long
= false;
13332 bool is_fp16
= false;
13336 switch (16 * u
+ opcode
) {
13337 case 0x08: /* MUL */
13338 case 0x10: /* MLA */
13339 case 0x14: /* MLS */
13341 unallocated_encoding(s
);
13345 case 0x02: /* SMLAL, SMLAL2 */
13346 case 0x12: /* UMLAL, UMLAL2 */
13347 case 0x06: /* SMLSL, SMLSL2 */
13348 case 0x16: /* UMLSL, UMLSL2 */
13349 case 0x0a: /* SMULL, SMULL2 */
13350 case 0x1a: /* UMULL, UMULL2 */
13352 unallocated_encoding(s
);
13357 case 0x03: /* SQDMLAL, SQDMLAL2 */
13358 case 0x07: /* SQDMLSL, SQDMLSL2 */
13359 case 0x0b: /* SQDMULL, SQDMULL2 */
13362 case 0x0c: /* SQDMULH */
13363 case 0x0d: /* SQRDMULH */
13365 case 0x01: /* FMLA */
13366 case 0x05: /* FMLS */
13367 case 0x09: /* FMUL */
13368 case 0x19: /* FMULX */
13371 case 0x1d: /* SQRDMLAH */
13372 case 0x1f: /* SQRDMLSH */
13373 if (!dc_isar_feature(aa64_rdm
, s
)) {
13374 unallocated_encoding(s
);
13378 case 0x0e: /* SDOT */
13379 case 0x1e: /* UDOT */
13380 if (is_scalar
|| size
!= MO_32
|| !dc_isar_feature(aa64_dp
, s
)) {
13381 unallocated_encoding(s
);
13387 case 0: /* SUDOT */
13388 case 2: /* USDOT */
13389 if (is_scalar
|| !dc_isar_feature(aa64_i8mm
, s
)) {
13390 unallocated_encoding(s
);
13395 case 1: /* BFDOT */
13396 if (is_scalar
|| !dc_isar_feature(aa64_bf16
, s
)) {
13397 unallocated_encoding(s
);
13402 case 3: /* BFMLAL{B,T} */
13403 if (is_scalar
|| !dc_isar_feature(aa64_bf16
, s
)) {
13404 unallocated_encoding(s
);
13407 /* can't set is_fp without other incorrect size checks */
13411 unallocated_encoding(s
);
13415 case 0x11: /* FCMLA #0 */
13416 case 0x13: /* FCMLA #90 */
13417 case 0x15: /* FCMLA #180 */
13418 case 0x17: /* FCMLA #270 */
13419 if (is_scalar
|| !dc_isar_feature(aa64_fcma
, s
)) {
13420 unallocated_encoding(s
);
13425 case 0x00: /* FMLAL */
13426 case 0x04: /* FMLSL */
13427 case 0x18: /* FMLAL2 */
13428 case 0x1c: /* FMLSL2 */
13429 if (is_scalar
|| size
!= MO_32
|| !dc_isar_feature(aa64_fhm
, s
)) {
13430 unallocated_encoding(s
);
13434 /* is_fp, but we pass cpu_env not fp_status. */
13437 unallocated_encoding(s
);
13442 case 1: /* normal fp */
13443 /* convert insn encoded size to MemOp size */
13445 case 0: /* half-precision */
13449 case MO_32
: /* single precision */
13450 case MO_64
: /* double precision */
13453 unallocated_encoding(s
);
13458 case 2: /* complex fp */
13459 /* Each indexable element is a complex pair. */
13464 unallocated_encoding(s
);
13472 unallocated_encoding(s
);
13477 default: /* integer */
13481 unallocated_encoding(s
);
13486 if (is_fp16
&& !dc_isar_feature(aa64_fp16
, s
)) {
13487 unallocated_encoding(s
);
13491 /* Given MemOp size, adjust register and indexing. */
13494 index
= h
<< 2 | l
<< 1 | m
;
13497 index
= h
<< 1 | l
;
13502 unallocated_encoding(s
);
13509 g_assert_not_reached();
13512 if (!fp_access_check(s
)) {
13517 fpst
= fpstatus_ptr(is_fp16
? FPST_FPCR_F16
: FPST_FPCR
);
13522 switch (16 * u
+ opcode
) {
13523 case 0x0e: /* SDOT */
13524 case 0x1e: /* UDOT */
13525 gen_gvec_op4_ool(s
, is_q
, rd
, rn
, rm
, rd
, index
,
13526 u
? gen_helper_gvec_udot_idx_b
13527 : gen_helper_gvec_sdot_idx_b
);
13530 switch (extract32(insn
, 22, 2)) {
13531 case 0: /* SUDOT */
13532 gen_gvec_op4_ool(s
, is_q
, rd
, rn
, rm
, rd
, index
,
13533 gen_helper_gvec_sudot_idx_b
);
13535 case 1: /* BFDOT */
13536 gen_gvec_op4_ool(s
, is_q
, rd
, rn
, rm
, rd
, index
,
13537 gen_helper_gvec_bfdot_idx
);
13539 case 2: /* USDOT */
13540 gen_gvec_op4_ool(s
, is_q
, rd
, rn
, rm
, rd
, index
,
13541 gen_helper_gvec_usdot_idx_b
);
13543 case 3: /* BFMLAL{B,T} */
13544 gen_gvec_op4_fpst(s
, 1, rd
, rn
, rm
, rd
, 0, (index
<< 1) | is_q
,
13545 gen_helper_gvec_bfmlal_idx
);
13548 g_assert_not_reached();
13549 case 0x11: /* FCMLA #0 */
13550 case 0x13: /* FCMLA #90 */
13551 case 0x15: /* FCMLA #180 */
13552 case 0x17: /* FCMLA #270 */
13554 int rot
= extract32(insn
, 13, 2);
13555 int data
= (index
<< 2) | rot
;
13556 tcg_gen_gvec_4_ptr(vec_full_reg_offset(s
, rd
),
13557 vec_full_reg_offset(s
, rn
),
13558 vec_full_reg_offset(s
, rm
),
13559 vec_full_reg_offset(s
, rd
), fpst
,
13560 is_q
? 16 : 8, vec_full_reg_size(s
), data
,
13562 ? gen_helper_gvec_fcmlas_idx
13563 : gen_helper_gvec_fcmlah_idx
);
13564 tcg_temp_free_ptr(fpst
);
13568 case 0x00: /* FMLAL */
13569 case 0x04: /* FMLSL */
13570 case 0x18: /* FMLAL2 */
13571 case 0x1c: /* FMLSL2 */
13573 int is_s
= extract32(opcode
, 2, 1);
13575 int data
= (index
<< 2) | (is_2
<< 1) | is_s
;
13576 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
13577 vec_full_reg_offset(s
, rn
),
13578 vec_full_reg_offset(s
, rm
), cpu_env
,
13579 is_q
? 16 : 8, vec_full_reg_size(s
),
13580 data
, gen_helper_gvec_fmlal_idx_a64
);
13584 case 0x08: /* MUL */
13585 if (!is_long
&& !is_scalar
) {
13586 static gen_helper_gvec_3
* const fns
[3] = {
13587 gen_helper_gvec_mul_idx_h
,
13588 gen_helper_gvec_mul_idx_s
,
13589 gen_helper_gvec_mul_idx_d
,
13591 tcg_gen_gvec_3_ool(vec_full_reg_offset(s
, rd
),
13592 vec_full_reg_offset(s
, rn
),
13593 vec_full_reg_offset(s
, rm
),
13594 is_q
? 16 : 8, vec_full_reg_size(s
),
13595 index
, fns
[size
- 1]);
13600 case 0x10: /* MLA */
13601 if (!is_long
&& !is_scalar
) {
13602 static gen_helper_gvec_4
* const fns
[3] = {
13603 gen_helper_gvec_mla_idx_h
,
13604 gen_helper_gvec_mla_idx_s
,
13605 gen_helper_gvec_mla_idx_d
,
13607 tcg_gen_gvec_4_ool(vec_full_reg_offset(s
, rd
),
13608 vec_full_reg_offset(s
, rn
),
13609 vec_full_reg_offset(s
, rm
),
13610 vec_full_reg_offset(s
, rd
),
13611 is_q
? 16 : 8, vec_full_reg_size(s
),
13612 index
, fns
[size
- 1]);
13617 case 0x14: /* MLS */
13618 if (!is_long
&& !is_scalar
) {
13619 static gen_helper_gvec_4
* const fns
[3] = {
13620 gen_helper_gvec_mls_idx_h
,
13621 gen_helper_gvec_mls_idx_s
,
13622 gen_helper_gvec_mls_idx_d
,
13624 tcg_gen_gvec_4_ool(vec_full_reg_offset(s
, rd
),
13625 vec_full_reg_offset(s
, rn
),
13626 vec_full_reg_offset(s
, rm
),
13627 vec_full_reg_offset(s
, rd
),
13628 is_q
? 16 : 8, vec_full_reg_size(s
),
13629 index
, fns
[size
- 1]);
13636 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
13639 assert(is_fp
&& is_q
&& !is_long
);
13641 read_vec_element(s
, tcg_idx
, rm
, index
, MO_64
);
13643 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13644 TCGv_i64 tcg_op
= tcg_temp_new_i64();
13645 TCGv_i64 tcg_res
= tcg_temp_new_i64();
13647 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
13649 switch (16 * u
+ opcode
) {
13650 case 0x05: /* FMLS */
13651 /* As usual for ARM, separate negation for fused multiply-add */
13652 gen_helper_vfp_negd(tcg_op
, tcg_op
);
13654 case 0x01: /* FMLA */
13655 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
13656 gen_helper_vfp_muladdd(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
13658 case 0x09: /* FMUL */
13659 gen_helper_vfp_muld(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13661 case 0x19: /* FMULX */
13662 gen_helper_vfp_mulxd(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13665 g_assert_not_reached();
13668 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
13669 tcg_temp_free_i64(tcg_op
);
13670 tcg_temp_free_i64(tcg_res
);
13673 tcg_temp_free_i64(tcg_idx
);
13674 clear_vec_high(s
, !is_scalar
, rd
);
13675 } else if (!is_long
) {
13676 /* 32 bit floating point, or 16 or 32 bit integer.
13677 * For the 16 bit scalar case we use the usual Neon helpers and
13678 * rely on the fact that 0 op 0 == 0 with no side effects.
13680 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
13681 int pass
, maxpasses
;
13686 maxpasses
= is_q
? 4 : 2;
13689 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
13691 if (size
== 1 && !is_scalar
) {
13692 /* The simplest way to handle the 16x16 indexed ops is to duplicate
13693 * the index into both halves of the 32 bit tcg_idx and then use
13694 * the usual Neon helpers.
13696 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
13699 for (pass
= 0; pass
< maxpasses
; pass
++) {
13700 TCGv_i32 tcg_op
= tcg_temp_new_i32();
13701 TCGv_i32 tcg_res
= tcg_temp_new_i32();
13703 read_vec_element_i32(s
, tcg_op
, rn
, pass
, is_scalar
? size
: MO_32
);
13705 switch (16 * u
+ opcode
) {
13706 case 0x08: /* MUL */
13707 case 0x10: /* MLA */
13708 case 0x14: /* MLS */
13710 static NeonGenTwoOpFn
* const fns
[2][2] = {
13711 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
13712 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
13714 NeonGenTwoOpFn
*genfn
;
13715 bool is_sub
= opcode
== 0x4;
13718 gen_helper_neon_mul_u16(tcg_res
, tcg_op
, tcg_idx
);
13720 tcg_gen_mul_i32(tcg_res
, tcg_op
, tcg_idx
);
13722 if (opcode
== 0x8) {
13725 read_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
13726 genfn
= fns
[size
- 1][is_sub
];
13727 genfn(tcg_res
, tcg_op
, tcg_res
);
13730 case 0x05: /* FMLS */
13731 case 0x01: /* FMLA */
13732 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13733 is_scalar
? size
: MO_32
);
13736 if (opcode
== 0x5) {
13737 /* As usual for ARM, separate negation for fused
13739 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80008000);
13742 gen_helper_advsimd_muladdh(tcg_res
, tcg_op
, tcg_idx
,
13745 gen_helper_advsimd_muladd2h(tcg_res
, tcg_op
, tcg_idx
,
13750 if (opcode
== 0x5) {
13751 /* As usual for ARM, separate negation for
13752 * fused multiply-add */
13753 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80000000);
13755 gen_helper_vfp_muladds(tcg_res
, tcg_op
, tcg_idx
,
13759 g_assert_not_reached();
13762 case 0x09: /* FMUL */
13766 gen_helper_advsimd_mulh(tcg_res
, tcg_op
,
13769 gen_helper_advsimd_mul2h(tcg_res
, tcg_op
,
13774 gen_helper_vfp_muls(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13777 g_assert_not_reached();
13780 case 0x19: /* FMULX */
13784 gen_helper_advsimd_mulxh(tcg_res
, tcg_op
,
13787 gen_helper_advsimd_mulx2h(tcg_res
, tcg_op
,
13792 gen_helper_vfp_mulxs(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13795 g_assert_not_reached();
13798 case 0x0c: /* SQDMULH */
13800 gen_helper_neon_qdmulh_s16(tcg_res
, cpu_env
,
13803 gen_helper_neon_qdmulh_s32(tcg_res
, cpu_env
,
13807 case 0x0d: /* SQRDMULH */
13809 gen_helper_neon_qrdmulh_s16(tcg_res
, cpu_env
,
13812 gen_helper_neon_qrdmulh_s32(tcg_res
, cpu_env
,
13816 case 0x1d: /* SQRDMLAH */
13817 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13818 is_scalar
? size
: MO_32
);
13820 gen_helper_neon_qrdmlah_s16(tcg_res
, cpu_env
,
13821 tcg_op
, tcg_idx
, tcg_res
);
13823 gen_helper_neon_qrdmlah_s32(tcg_res
, cpu_env
,
13824 tcg_op
, tcg_idx
, tcg_res
);
13827 case 0x1f: /* SQRDMLSH */
13828 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13829 is_scalar
? size
: MO_32
);
13831 gen_helper_neon_qrdmlsh_s16(tcg_res
, cpu_env
,
13832 tcg_op
, tcg_idx
, tcg_res
);
13834 gen_helper_neon_qrdmlsh_s32(tcg_res
, cpu_env
,
13835 tcg_op
, tcg_idx
, tcg_res
);
13839 g_assert_not_reached();
13843 write_fp_sreg(s
, rd
, tcg_res
);
13845 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
13848 tcg_temp_free_i32(tcg_op
);
13849 tcg_temp_free_i32(tcg_res
);
13852 tcg_temp_free_i32(tcg_idx
);
13853 clear_vec_high(s
, is_q
, rd
);
13855 /* long ops: 16x16->32 or 32x32->64 */
13856 TCGv_i64 tcg_res
[2];
13858 bool satop
= extract32(opcode
, 0, 1);
13859 MemOp memop
= MO_32
;
13866 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
13868 read_vec_element(s
, tcg_idx
, rm
, index
, memop
);
13870 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13871 TCGv_i64 tcg_op
= tcg_temp_new_i64();
13872 TCGv_i64 tcg_passres
;
13878 passelt
= pass
+ (is_q
* 2);
13881 read_vec_element(s
, tcg_op
, rn
, passelt
, memop
);
13883 tcg_res
[pass
] = tcg_temp_new_i64();
13885 if (opcode
== 0xa || opcode
== 0xb) {
13886 /* Non-accumulating ops */
13887 tcg_passres
= tcg_res
[pass
];
13889 tcg_passres
= tcg_temp_new_i64();
13892 tcg_gen_mul_i64(tcg_passres
, tcg_op
, tcg_idx
);
13893 tcg_temp_free_i64(tcg_op
);
13896 /* saturating, doubling */
13897 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
13898 tcg_passres
, tcg_passres
);
13901 if (opcode
== 0xa || opcode
== 0xb) {
13905 /* Accumulating op: handle accumulate step */
13906 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13909 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13910 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
13912 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13913 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
13915 case 0x7: /* SQDMLSL, SQDMLSL2 */
13916 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
13918 case 0x3: /* SQDMLAL, SQDMLAL2 */
13919 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
13924 g_assert_not_reached();
13926 tcg_temp_free_i64(tcg_passres
);
13928 tcg_temp_free_i64(tcg_idx
);
13930 clear_vec_high(s
, !is_scalar
, rd
);
13932 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
13935 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
13938 /* The simplest way to handle the 16x16 indexed ops is to
13939 * duplicate the index into both halves of the 32 bit tcg_idx
13940 * and then use the usual Neon helpers.
13942 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
13945 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13946 TCGv_i32 tcg_op
= tcg_temp_new_i32();
13947 TCGv_i64 tcg_passres
;
13950 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
13952 read_vec_element_i32(s
, tcg_op
, rn
,
13953 pass
+ (is_q
* 2), MO_32
);
13956 tcg_res
[pass
] = tcg_temp_new_i64();
13958 if (opcode
== 0xa || opcode
== 0xb) {
13959 /* Non-accumulating ops */
13960 tcg_passres
= tcg_res
[pass
];
13962 tcg_passres
= tcg_temp_new_i64();
13965 if (memop
& MO_SIGN
) {
13966 gen_helper_neon_mull_s16(tcg_passres
, tcg_op
, tcg_idx
);
13968 gen_helper_neon_mull_u16(tcg_passres
, tcg_op
, tcg_idx
);
13971 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
13972 tcg_passres
, tcg_passres
);
13974 tcg_temp_free_i32(tcg_op
);
13976 if (opcode
== 0xa || opcode
== 0xb) {
13980 /* Accumulating op: handle accumulate step */
13981 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13984 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13985 gen_helper_neon_addl_u32(tcg_res
[pass
], tcg_res
[pass
],
13988 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13989 gen_helper_neon_subl_u32(tcg_res
[pass
], tcg_res
[pass
],
13992 case 0x7: /* SQDMLSL, SQDMLSL2 */
13993 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
13995 case 0x3: /* SQDMLAL, SQDMLAL2 */
13996 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
14001 g_assert_not_reached();
14003 tcg_temp_free_i64(tcg_passres
);
14005 tcg_temp_free_i32(tcg_idx
);
14008 tcg_gen_ext32u_i64(tcg_res
[0], tcg_res
[0]);
14013 tcg_res
[1] = tcg_const_i64(0);
14016 for (pass
= 0; pass
< 2; pass
++) {
14017 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
14018 tcg_temp_free_i64(tcg_res
[pass
]);
14023 tcg_temp_free_ptr(fpst
);
14028 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
14029 * +-----------------+------+-----------+--------+-----+------+------+
14030 * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
14031 * +-----------------+------+-----------+--------+-----+------+------+
14033 static void disas_crypto_aes(DisasContext
*s
, uint32_t insn
)
14035 int size
= extract32(insn
, 22, 2);
14036 int opcode
= extract32(insn
, 12, 5);
14037 int rn
= extract32(insn
, 5, 5);
14038 int rd
= extract32(insn
, 0, 5);
14040 gen_helper_gvec_2
*genfn2
= NULL
;
14041 gen_helper_gvec_3
*genfn3
= NULL
;
14043 if (!dc_isar_feature(aa64_aes
, s
) || size
!= 0) {
14044 unallocated_encoding(s
);
14049 case 0x4: /* AESE */
14051 genfn3
= gen_helper_crypto_aese
;
14053 case 0x6: /* AESMC */
14055 genfn2
= gen_helper_crypto_aesmc
;
14057 case 0x5: /* AESD */
14059 genfn3
= gen_helper_crypto_aese
;
14061 case 0x7: /* AESIMC */
14063 genfn2
= gen_helper_crypto_aesmc
;
14066 unallocated_encoding(s
);
14070 if (!fp_access_check(s
)) {
14074 gen_gvec_op2_ool(s
, true, rd
, rn
, decrypt
, genfn2
);
14076 gen_gvec_op3_ool(s
, true, rd
, rd
, rn
, decrypt
, genfn3
);
14080 /* Crypto three-reg SHA
14081 * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
14082 * +-----------------+------+---+------+---+--------+-----+------+------+
14083 * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
14084 * +-----------------+------+---+------+---+--------+-----+------+------+
14086 static void disas_crypto_three_reg_sha(DisasContext
*s
, uint32_t insn
)
14088 int size
= extract32(insn
, 22, 2);
14089 int opcode
= extract32(insn
, 12, 3);
14090 int rm
= extract32(insn
, 16, 5);
14091 int rn
= extract32(insn
, 5, 5);
14092 int rd
= extract32(insn
, 0, 5);
14093 gen_helper_gvec_3
*genfn
;
14097 unallocated_encoding(s
);
14102 case 0: /* SHA1C */
14103 genfn
= gen_helper_crypto_sha1c
;
14104 feature
= dc_isar_feature(aa64_sha1
, s
);
14106 case 1: /* SHA1P */
14107 genfn
= gen_helper_crypto_sha1p
;
14108 feature
= dc_isar_feature(aa64_sha1
, s
);
14110 case 2: /* SHA1M */
14111 genfn
= gen_helper_crypto_sha1m
;
14112 feature
= dc_isar_feature(aa64_sha1
, s
);
14114 case 3: /* SHA1SU0 */
14115 genfn
= gen_helper_crypto_sha1su0
;
14116 feature
= dc_isar_feature(aa64_sha1
, s
);
14118 case 4: /* SHA256H */
14119 genfn
= gen_helper_crypto_sha256h
;
14120 feature
= dc_isar_feature(aa64_sha256
, s
);
14122 case 5: /* SHA256H2 */
14123 genfn
= gen_helper_crypto_sha256h2
;
14124 feature
= dc_isar_feature(aa64_sha256
, s
);
14126 case 6: /* SHA256SU1 */
14127 genfn
= gen_helper_crypto_sha256su1
;
14128 feature
= dc_isar_feature(aa64_sha256
, s
);
14131 unallocated_encoding(s
);
14136 unallocated_encoding(s
);
14140 if (!fp_access_check(s
)) {
14143 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, 0, genfn
);
14146 /* Crypto two-reg SHA
14147 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
14148 * +-----------------+------+-----------+--------+-----+------+------+
14149 * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
14150 * +-----------------+------+-----------+--------+-----+------+------+
14152 static void disas_crypto_two_reg_sha(DisasContext
*s
, uint32_t insn
)
14154 int size
= extract32(insn
, 22, 2);
14155 int opcode
= extract32(insn
, 12, 5);
14156 int rn
= extract32(insn
, 5, 5);
14157 int rd
= extract32(insn
, 0, 5);
14158 gen_helper_gvec_2
*genfn
;
14162 unallocated_encoding(s
);
14167 case 0: /* SHA1H */
14168 feature
= dc_isar_feature(aa64_sha1
, s
);
14169 genfn
= gen_helper_crypto_sha1h
;
14171 case 1: /* SHA1SU1 */
14172 feature
= dc_isar_feature(aa64_sha1
, s
);
14173 genfn
= gen_helper_crypto_sha1su1
;
14175 case 2: /* SHA256SU0 */
14176 feature
= dc_isar_feature(aa64_sha256
, s
);
14177 genfn
= gen_helper_crypto_sha256su0
;
14180 unallocated_encoding(s
);
14185 unallocated_encoding(s
);
14189 if (!fp_access_check(s
)) {
14192 gen_gvec_op2_ool(s
, true, rd
, rn
, 0, genfn
);
14195 static void gen_rax1_i64(TCGv_i64 d
, TCGv_i64 n
, TCGv_i64 m
)
14197 tcg_gen_rotli_i64(d
, m
, 1);
14198 tcg_gen_xor_i64(d
, d
, n
);
14201 static void gen_rax1_vec(unsigned vece
, TCGv_vec d
, TCGv_vec n
, TCGv_vec m
)
14203 tcg_gen_rotli_vec(vece
, d
, m
, 1);
14204 tcg_gen_xor_vec(vece
, d
, d
, n
);
14207 void gen_gvec_rax1(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
14208 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
)
14210 static const TCGOpcode vecop_list
[] = { INDEX_op_rotli_vec
, 0 };
14211 static const GVecGen3 op
= {
14212 .fni8
= gen_rax1_i64
,
14213 .fniv
= gen_rax1_vec
,
14214 .opt_opc
= vecop_list
,
14215 .fno
= gen_helper_crypto_rax1
,
14218 tcg_gen_gvec_3(rd_ofs
, rn_ofs
, rm_ofs
, opr_sz
, max_sz
, &op
);
14221 /* Crypto three-reg SHA512
14222 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
14223 * +-----------------------+------+---+---+-----+--------+------+------+
14224 * | 1 1 0 0 1 1 1 0 0 1 1 | Rm | 1 | O | 0 0 | opcode | Rn | Rd |
14225 * +-----------------------+------+---+---+-----+--------+------+------+
14227 static void disas_crypto_three_reg_sha512(DisasContext
*s
, uint32_t insn
)
14229 int opcode
= extract32(insn
, 10, 2);
14230 int o
= extract32(insn
, 14, 1);
14231 int rm
= extract32(insn
, 16, 5);
14232 int rn
= extract32(insn
, 5, 5);
14233 int rd
= extract32(insn
, 0, 5);
14235 gen_helper_gvec_3
*oolfn
= NULL
;
14236 GVecGen3Fn
*gvecfn
= NULL
;
14240 case 0: /* SHA512H */
14241 feature
= dc_isar_feature(aa64_sha512
, s
);
14242 oolfn
= gen_helper_crypto_sha512h
;
14244 case 1: /* SHA512H2 */
14245 feature
= dc_isar_feature(aa64_sha512
, s
);
14246 oolfn
= gen_helper_crypto_sha512h2
;
14248 case 2: /* SHA512SU1 */
14249 feature
= dc_isar_feature(aa64_sha512
, s
);
14250 oolfn
= gen_helper_crypto_sha512su1
;
14253 feature
= dc_isar_feature(aa64_sha3
, s
);
14254 gvecfn
= gen_gvec_rax1
;
14257 g_assert_not_reached();
14261 case 0: /* SM3PARTW1 */
14262 feature
= dc_isar_feature(aa64_sm3
, s
);
14263 oolfn
= gen_helper_crypto_sm3partw1
;
14265 case 1: /* SM3PARTW2 */
14266 feature
= dc_isar_feature(aa64_sm3
, s
);
14267 oolfn
= gen_helper_crypto_sm3partw2
;
14269 case 2: /* SM4EKEY */
14270 feature
= dc_isar_feature(aa64_sm4
, s
);
14271 oolfn
= gen_helper_crypto_sm4ekey
;
14274 unallocated_encoding(s
);
14280 unallocated_encoding(s
);
14284 if (!fp_access_check(s
)) {
14289 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, 0, oolfn
);
14291 gen_gvec_fn3(s
, true, rd
, rn
, rm
, gvecfn
, MO_64
);
14295 /* Crypto two-reg SHA512
14296 * 31 12 11 10 9 5 4 0
14297 * +-----------------------------------------+--------+------+------+
14298 * | 1 1 0 0 1 1 1 0 1 1 0 0 0 0 0 0 1 0 0 0 | opcode | Rn | Rd |
14299 * +-----------------------------------------+--------+------+------+
14301 static void disas_crypto_two_reg_sha512(DisasContext
*s
, uint32_t insn
)
14303 int opcode
= extract32(insn
, 10, 2);
14304 int rn
= extract32(insn
, 5, 5);
14305 int rd
= extract32(insn
, 0, 5);
14309 case 0: /* SHA512SU0 */
14310 feature
= dc_isar_feature(aa64_sha512
, s
);
14313 feature
= dc_isar_feature(aa64_sm4
, s
);
14316 unallocated_encoding(s
);
14321 unallocated_encoding(s
);
14325 if (!fp_access_check(s
)) {
14330 case 0: /* SHA512SU0 */
14331 gen_gvec_op2_ool(s
, true, rd
, rn
, 0, gen_helper_crypto_sha512su0
);
14334 gen_gvec_op3_ool(s
, true, rd
, rd
, rn
, 0, gen_helper_crypto_sm4e
);
14337 g_assert_not_reached();
14341 /* Crypto four-register
14342 * 31 23 22 21 20 16 15 14 10 9 5 4 0
14343 * +-------------------+-----+------+---+------+------+------+
14344 * | 1 1 0 0 1 1 1 0 0 | Op0 | Rm | 0 | Ra | Rn | Rd |
14345 * +-------------------+-----+------+---+------+------+------+
14347 static void disas_crypto_four_reg(DisasContext
*s
, uint32_t insn
)
14349 int op0
= extract32(insn
, 21, 2);
14350 int rm
= extract32(insn
, 16, 5);
14351 int ra
= extract32(insn
, 10, 5);
14352 int rn
= extract32(insn
, 5, 5);
14353 int rd
= extract32(insn
, 0, 5);
14359 feature
= dc_isar_feature(aa64_sha3
, s
);
14361 case 2: /* SM3SS1 */
14362 feature
= dc_isar_feature(aa64_sm3
, s
);
14365 unallocated_encoding(s
);
14370 unallocated_encoding(s
);
14374 if (!fp_access_check(s
)) {
14379 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
[2];
14382 tcg_op1
= tcg_temp_new_i64();
14383 tcg_op2
= tcg_temp_new_i64();
14384 tcg_op3
= tcg_temp_new_i64();
14385 tcg_res
[0] = tcg_temp_new_i64();
14386 tcg_res
[1] = tcg_temp_new_i64();
14388 for (pass
= 0; pass
< 2; pass
++) {
14389 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
14390 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
14391 read_vec_element(s
, tcg_op3
, ra
, pass
, MO_64
);
14395 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
14398 tcg_gen_andc_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
14400 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
14402 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
14403 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
14405 tcg_temp_free_i64(tcg_op1
);
14406 tcg_temp_free_i64(tcg_op2
);
14407 tcg_temp_free_i64(tcg_op3
);
14408 tcg_temp_free_i64(tcg_res
[0]);
14409 tcg_temp_free_i64(tcg_res
[1]);
14411 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
, tcg_zero
;
14413 tcg_op1
= tcg_temp_new_i32();
14414 tcg_op2
= tcg_temp_new_i32();
14415 tcg_op3
= tcg_temp_new_i32();
14416 tcg_res
= tcg_temp_new_i32();
14417 tcg_zero
= tcg_const_i32(0);
14419 read_vec_element_i32(s
, tcg_op1
, rn
, 3, MO_32
);
14420 read_vec_element_i32(s
, tcg_op2
, rm
, 3, MO_32
);
14421 read_vec_element_i32(s
, tcg_op3
, ra
, 3, MO_32
);
14423 tcg_gen_rotri_i32(tcg_res
, tcg_op1
, 20);
14424 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op2
);
14425 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op3
);
14426 tcg_gen_rotri_i32(tcg_res
, tcg_res
, 25);
14428 write_vec_element_i32(s
, tcg_zero
, rd
, 0, MO_32
);
14429 write_vec_element_i32(s
, tcg_zero
, rd
, 1, MO_32
);
14430 write_vec_element_i32(s
, tcg_zero
, rd
, 2, MO_32
);
14431 write_vec_element_i32(s
, tcg_res
, rd
, 3, MO_32
);
14433 tcg_temp_free_i32(tcg_op1
);
14434 tcg_temp_free_i32(tcg_op2
);
14435 tcg_temp_free_i32(tcg_op3
);
14436 tcg_temp_free_i32(tcg_res
);
14437 tcg_temp_free_i32(tcg_zero
);
14442 * 31 21 20 16 15 10 9 5 4 0
14443 * +-----------------------+------+--------+------+------+
14444 * | 1 1 0 0 1 1 1 0 1 0 0 | Rm | imm6 | Rn | Rd |
14445 * +-----------------------+------+--------+------+------+
14447 static void disas_crypto_xar(DisasContext
*s
, uint32_t insn
)
14449 int rm
= extract32(insn
, 16, 5);
14450 int imm6
= extract32(insn
, 10, 6);
14451 int rn
= extract32(insn
, 5, 5);
14452 int rd
= extract32(insn
, 0, 5);
14454 if (!dc_isar_feature(aa64_sha3
, s
)) {
14455 unallocated_encoding(s
);
14459 if (!fp_access_check(s
)) {
14463 gen_gvec_xar(MO_64
, vec_full_reg_offset(s
, rd
),
14464 vec_full_reg_offset(s
, rn
),
14465 vec_full_reg_offset(s
, rm
), imm6
, 16,
14466 vec_full_reg_size(s
));
14469 /* Crypto three-reg imm2
14470 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
14471 * +-----------------------+------+-----+------+--------+------+------+
14472 * | 1 1 0 0 1 1 1 0 0 1 0 | Rm | 1 0 | imm2 | opcode | Rn | Rd |
14473 * +-----------------------+------+-----+------+--------+------+------+
14475 static void disas_crypto_three_reg_imm2(DisasContext
*s
, uint32_t insn
)
14477 static gen_helper_gvec_3
* const fns
[4] = {
14478 gen_helper_crypto_sm3tt1a
, gen_helper_crypto_sm3tt1b
,
14479 gen_helper_crypto_sm3tt2a
, gen_helper_crypto_sm3tt2b
,
14481 int opcode
= extract32(insn
, 10, 2);
14482 int imm2
= extract32(insn
, 12, 2);
14483 int rm
= extract32(insn
, 16, 5);
14484 int rn
= extract32(insn
, 5, 5);
14485 int rd
= extract32(insn
, 0, 5);
14487 if (!dc_isar_feature(aa64_sm3
, s
)) {
14488 unallocated_encoding(s
);
14492 if (!fp_access_check(s
)) {
14496 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, imm2
, fns
[opcode
]);
14499 /* C3.6 Data processing - SIMD, inc Crypto
14501 * As the decode gets a little complex we are using a table based
14502 * approach for this part of the decode.
14504 static const AArch64DecodeTable data_proc_simd
[] = {
14505 /* pattern , mask , fn */
14506 { 0x0e200400, 0x9f200400, disas_simd_three_reg_same
},
14507 { 0x0e008400, 0x9f208400, disas_simd_three_reg_same_extra
},
14508 { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff
},
14509 { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc
},
14510 { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes
},
14511 { 0x0e000400, 0x9fe08400, disas_simd_copy
},
14512 { 0x0f000000, 0x9f000400, disas_simd_indexed
}, /* vector indexed */
14513 /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
14514 { 0x0f000400, 0x9ff80400, disas_simd_mod_imm
},
14515 { 0x0f000400, 0x9f800400, disas_simd_shift_imm
},
14516 { 0x0e000000, 0xbf208c00, disas_simd_tb
},
14517 { 0x0e000800, 0xbf208c00, disas_simd_zip_trn
},
14518 { 0x2e000000, 0xbf208400, disas_simd_ext
},
14519 { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same
},
14520 { 0x5e008400, 0xdf208400, disas_simd_scalar_three_reg_same_extra
},
14521 { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff
},
14522 { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc
},
14523 { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise
},
14524 { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy
},
14525 { 0x5f000000, 0xdf000400, disas_simd_indexed
}, /* scalar indexed */
14526 { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm
},
14527 { 0x4e280800, 0xff3e0c00, disas_crypto_aes
},
14528 { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha
},
14529 { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha
},
14530 { 0xce608000, 0xffe0b000, disas_crypto_three_reg_sha512
},
14531 { 0xcec08000, 0xfffff000, disas_crypto_two_reg_sha512
},
14532 { 0xce000000, 0xff808000, disas_crypto_four_reg
},
14533 { 0xce800000, 0xffe00000, disas_crypto_xar
},
14534 { 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2
},
14535 { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16
},
14536 { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16
},
14537 { 0x5e400400, 0xdf60c400, disas_simd_scalar_three_reg_same_fp16
},
14538 { 0x00000000, 0x00000000, NULL
}
14541 static void disas_data_proc_simd(DisasContext
*s
, uint32_t insn
)
14543 /* Note that this is called with all non-FP cases from
14544 * table C3-6 so it must UNDEF for entries not specifically
14545 * allocated to instructions in that table.
14547 AArch64DecodeFn
*fn
= lookup_disas_fn(&data_proc_simd
[0], insn
);
14551 unallocated_encoding(s
);
14555 /* C3.6 Data processing - SIMD and floating point */
14556 static void disas_data_proc_simd_fp(DisasContext
*s
, uint32_t insn
)
14558 if (extract32(insn
, 28, 1) == 1 && extract32(insn
, 30, 1) == 0) {
14559 disas_data_proc_fp(s
, insn
);
14561 /* SIMD, including crypto */
14562 disas_data_proc_simd(s
, insn
);
14568 * @env: The cpu environment
14569 * @s: The DisasContext
14571 * Return true if the page is guarded.
14573 static bool is_guarded_page(CPUARMState
*env
, DisasContext
*s
)
14575 uint64_t addr
= s
->base
.pc_first
;
14576 #ifdef CONFIG_USER_ONLY
14577 return page_get_flags(addr
) & PAGE_BTI
;
14579 int mmu_idx
= arm_to_core_mmu_idx(s
->mmu_idx
);
14580 unsigned int index
= tlb_index(env
, mmu_idx
, addr
);
14581 CPUTLBEntry
*entry
= tlb_entry(env
, mmu_idx
, addr
);
14584 * We test this immediately after reading an insn, which means
14585 * that any normal page must be in the TLB. The only exception
14586 * would be for executing from flash or device memory, which
14587 * does not retain the TLB entry.
14589 * FIXME: Assume false for those, for now. We could use
14590 * arm_cpu_get_phys_page_attrs_debug to re-read the page
14591 * table entry even for that case.
14593 return (tlb_hit(entry
->addr_code
, addr
) &&
14594 arm_tlb_bti_gp(&env_tlb(env
)->d
[mmu_idx
].iotlb
[index
].attrs
));
14599 * btype_destination_ok:
14600 * @insn: The instruction at the branch destination
14601 * @bt: SCTLR_ELx.BT
14602 * @btype: PSTATE.BTYPE, and is non-zero
14604 * On a guarded page, there are a limited number of insns
14605 * that may be present at the branch target:
14606 * - branch target identifiers,
14607 * - paciasp, pacibsp,
14610 * Anything else causes a Branch Target Exception.
14612 * Return true if the branch is compatible, false to raise BTITRAP.
14614 static bool btype_destination_ok(uint32_t insn
, bool bt
, int btype
)
14616 if ((insn
& 0xfffff01fu
) == 0xd503201fu
) {
14618 switch (extract32(insn
, 5, 7)) {
14619 case 0b011001: /* PACIASP */
14620 case 0b011011: /* PACIBSP */
14622 * If SCTLR_ELx.BT, then PACI*SP are not compatible
14623 * with btype == 3. Otherwise all btype are ok.
14625 return !bt
|| btype
!= 3;
14626 case 0b100000: /* BTI */
14627 /* Not compatible with any btype. */
14629 case 0b100010: /* BTI c */
14630 /* Not compatible with btype == 3 */
14632 case 0b100100: /* BTI j */
14633 /* Not compatible with btype == 2 */
14635 case 0b100110: /* BTI jc */
14636 /* Compatible with any btype. */
14640 switch (insn
& 0xffe0001fu
) {
14641 case 0xd4200000u
: /* BRK */
14642 case 0xd4400000u
: /* HLT */
14643 /* Give priority to the breakpoint exception. */
14650 static void aarch64_tr_init_disas_context(DisasContextBase
*dcbase
,
14653 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14654 CPUARMState
*env
= cpu
->env_ptr
;
14655 ARMCPU
*arm_cpu
= env_archcpu(env
);
14656 CPUARMTBFlags tb_flags
= arm_tbflags_from_tb(dc
->base
.tb
);
14657 int bound
, core_mmu_idx
;
14659 dc
->isar
= &arm_cpu
->isar
;
14663 /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
14664 * there is no secure EL1, so we route exceptions to EL3.
14666 dc
->secure_routed_to_el3
= arm_feature(env
, ARM_FEATURE_EL3
) &&
14667 !arm_el_is_aa64(env
, 3);
14670 dc
->be_data
= EX_TBFLAG_ANY(tb_flags
, BE_DATA
) ? MO_BE
: MO_LE
;
14671 dc
->condexec_mask
= 0;
14672 dc
->condexec_cond
= 0;
14673 core_mmu_idx
= EX_TBFLAG_ANY(tb_flags
, MMUIDX
);
14674 dc
->mmu_idx
= core_to_aa64_mmu_idx(core_mmu_idx
);
14675 dc
->tbii
= EX_TBFLAG_A64(tb_flags
, TBII
);
14676 dc
->tbid
= EX_TBFLAG_A64(tb_flags
, TBID
);
14677 dc
->tcma
= EX_TBFLAG_A64(tb_flags
, TCMA
);
14678 dc
->current_el
= arm_mmu_idx_to_el(dc
->mmu_idx
);
14679 #if !defined(CONFIG_USER_ONLY)
14680 dc
->user
= (dc
->current_el
== 0);
14682 dc
->fp_excp_el
= EX_TBFLAG_ANY(tb_flags
, FPEXC_EL
);
14683 dc
->align_mem
= EX_TBFLAG_ANY(tb_flags
, ALIGN_MEM
);
14684 dc
->pstate_il
= EX_TBFLAG_ANY(tb_flags
, PSTATE__IL
);
14685 dc
->sve_excp_el
= EX_TBFLAG_A64(tb_flags
, SVEEXC_EL
);
14686 dc
->sve_len
= (EX_TBFLAG_A64(tb_flags
, ZCR_LEN
) + 1) * 16;
14687 dc
->pauth_active
= EX_TBFLAG_A64(tb_flags
, PAUTH_ACTIVE
);
14688 dc
->bt
= EX_TBFLAG_A64(tb_flags
, BT
);
14689 dc
->btype
= EX_TBFLAG_A64(tb_flags
, BTYPE
);
14690 dc
->unpriv
= EX_TBFLAG_A64(tb_flags
, UNPRIV
);
14691 dc
->ata
= EX_TBFLAG_A64(tb_flags
, ATA
);
14692 dc
->mte_active
[0] = EX_TBFLAG_A64(tb_flags
, MTE_ACTIVE
);
14693 dc
->mte_active
[1] = EX_TBFLAG_A64(tb_flags
, MTE0_ACTIVE
);
14695 dc
->vec_stride
= 0;
14696 dc
->cp_regs
= arm_cpu
->cp_regs
;
14697 dc
->features
= env
->features
;
14698 dc
->dcz_blocksize
= arm_cpu
->dcz_blocksize
;
14700 #ifdef CONFIG_USER_ONLY
14701 /* In sve_probe_page, we assume TBI is enabled. */
14702 tcg_debug_assert(dc
->tbid
& 1);
14705 /* Single step state. The code-generation logic here is:
14707 * generate code with no special handling for single-stepping (except
14708 * that anything that can make us go to SS_ACTIVE == 1 must end the TB;
14709 * this happens anyway because those changes are all system register or
14711 * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending)
14712 * emit code for one insn
14713 * emit code to clear PSTATE.SS
14714 * emit code to generate software step exception for completed step
14715 * end TB (as usual for having generated an exception)
14716 * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending)
14717 * emit code to generate a software step exception
14720 dc
->ss_active
= EX_TBFLAG_ANY(tb_flags
, SS_ACTIVE
);
14721 dc
->pstate_ss
= EX_TBFLAG_ANY(tb_flags
, PSTATE__SS
);
14722 dc
->is_ldex
= false;
14723 dc
->debug_target_el
= EX_TBFLAG_ANY(tb_flags
, DEBUG_TARGET_EL
);
14725 /* Bound the number of insns to execute to those left on the page. */
14726 bound
= -(dc
->base
.pc_first
| TARGET_PAGE_MASK
) / 4;
14728 /* If architectural single step active, limit to 1. */
14729 if (dc
->ss_active
) {
14732 dc
->base
.max_insns
= MIN(dc
->base
.max_insns
, bound
);
14734 init_tmp_a64_array(dc
);
14737 static void aarch64_tr_tb_start(DisasContextBase
*db
, CPUState
*cpu
)
14741 static void aarch64_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
14743 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14745 tcg_gen_insn_start(dc
->base
.pc_next
, 0, 0);
14746 dc
->insn_start
= tcg_last_op();
14749 static void aarch64_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
14751 DisasContext
*s
= container_of(dcbase
, DisasContext
, base
);
14752 CPUARMState
*env
= cpu
->env_ptr
;
14753 uint64_t pc
= s
->base
.pc_next
;
14756 /* Singlestep exceptions have the highest priority. */
14757 if (s
->ss_active
&& !s
->pstate_ss
) {
14758 /* Singlestep state is Active-pending.
14759 * If we're in this state at the start of a TB then either
14760 * a) we just took an exception to an EL which is being debugged
14761 * and this is the first insn in the exception handler
14762 * b) debug exceptions were masked and we just unmasked them
14763 * without changing EL (eg by clearing PSTATE.D)
14764 * In either case we're going to take a swstep exception in the
14765 * "did not step an insn" case, and so the syndrome ISV and EX
14766 * bits should be zero.
14768 assert(s
->base
.num_insns
== 1);
14769 gen_swstep_exception(s
, 0, 0);
14770 s
->base
.is_jmp
= DISAS_NORETURN
;
14771 s
->base
.pc_next
= pc
+ 4;
14777 * PC alignment fault. This has priority over the instruction abort
14778 * that we would receive from a translation fault via arm_ldl_code.
14779 * This should only be possible after an indirect branch, at the
14782 assert(s
->base
.num_insns
== 1);
14783 gen_helper_exception_pc_alignment(cpu_env
, tcg_constant_tl(pc
));
14784 s
->base
.is_jmp
= DISAS_NORETURN
;
14785 s
->base
.pc_next
= QEMU_ALIGN_UP(pc
, 4);
14790 insn
= arm_ldl_code(env
, &s
->base
, pc
, s
->sctlr_b
);
14792 s
->base
.pc_next
= pc
+ 4;
14794 s
->fp_access_checked
= false;
14795 s
->sve_access_checked
= false;
14797 if (s
->pstate_il
) {
14799 * Illegal execution state. This has priority over BTI
14800 * exceptions, but comes after instruction abort exceptions.
14802 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
,
14803 syn_illegalstate(), default_exception_el(s
));
14807 if (dc_isar_feature(aa64_bti
, s
)) {
14808 if (s
->base
.num_insns
== 1) {
14810 * At the first insn of the TB, compute s->guarded_page.
14811 * We delayed computing this until successfully reading
14812 * the first insn of the TB, above. This (mostly) ensures
14813 * that the softmmu tlb entry has been populated, and the
14814 * page table GP bit is available.
14816 * Note that we need to compute this even if btype == 0,
14817 * because this value is used for BR instructions later
14818 * where ENV is not available.
14820 s
->guarded_page
= is_guarded_page(env
, s
);
14822 /* First insn can have btype set to non-zero. */
14823 tcg_debug_assert(s
->btype
>= 0);
14826 * Note that the Branch Target Exception has fairly high
14827 * priority -- below debugging exceptions but above most
14828 * everything else. This allows us to handle this now
14829 * instead of waiting until the insn is otherwise decoded.
14833 && !btype_destination_ok(insn
, s
->bt
, s
->btype
)) {
14834 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
,
14835 syn_btitrap(s
->btype
),
14836 default_exception_el(s
));
14840 /* Not the first insn: btype must be 0. */
14841 tcg_debug_assert(s
->btype
== 0);
14845 switch (extract32(insn
, 25, 4)) {
14846 case 0x0: case 0x1: case 0x3: /* UNALLOCATED */
14847 unallocated_encoding(s
);
14850 if (!dc_isar_feature(aa64_sve
, s
) || !disas_sve(s
, insn
)) {
14851 unallocated_encoding(s
);
14854 case 0x8: case 0x9: /* Data processing - immediate */
14855 disas_data_proc_imm(s
, insn
);
14857 case 0xa: case 0xb: /* Branch, exception generation and system insns */
14858 disas_b_exc_sys(s
, insn
);
14863 case 0xe: /* Loads and stores */
14864 disas_ldst(s
, insn
);
14867 case 0xd: /* Data processing - register */
14868 disas_data_proc_reg(s
, insn
);
14871 case 0xf: /* Data processing - SIMD and floating point */
14872 disas_data_proc_simd_fp(s
, insn
);
14875 assert(FALSE
); /* all 15 cases should be handled above */
14879 /* if we allocated any temporaries, free them here */
14883 * After execution of most insns, btype is reset to 0.
14884 * Note that we set btype == -1 when the insn sets btype.
14886 if (s
->btype
> 0 && s
->base
.is_jmp
!= DISAS_NORETURN
) {
14890 translator_loop_temp_check(&s
->base
);
14893 static void aarch64_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
14895 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14897 if (unlikely(dc
->ss_active
)) {
14898 /* Note that this means single stepping WFI doesn't halt the CPU.
14899 * For conditional branch insns this is harmless unreachable code as
14900 * gen_goto_tb() has already handled emitting the debug exception
14901 * (and thus a tb-jump is not possible when singlestepping).
14903 switch (dc
->base
.is_jmp
) {
14905 gen_a64_set_pc_im(dc
->base
.pc_next
);
14909 gen_step_complete_exception(dc
);
14911 case DISAS_NORETURN
:
14915 switch (dc
->base
.is_jmp
) {
14917 case DISAS_TOO_MANY
:
14918 gen_goto_tb(dc
, 1, dc
->base
.pc_next
);
14921 case DISAS_UPDATE_EXIT
:
14922 gen_a64_set_pc_im(dc
->base
.pc_next
);
14925 tcg_gen_exit_tb(NULL
, 0);
14927 case DISAS_UPDATE_NOCHAIN
:
14928 gen_a64_set_pc_im(dc
->base
.pc_next
);
14931 tcg_gen_lookup_and_goto_ptr();
14933 case DISAS_NORETURN
:
14937 gen_a64_set_pc_im(dc
->base
.pc_next
);
14938 gen_helper_wfe(cpu_env
);
14941 gen_a64_set_pc_im(dc
->base
.pc_next
);
14942 gen_helper_yield(cpu_env
);
14946 /* This is a special case because we don't want to just halt the CPU
14947 * if trying to debug across a WFI.
14949 TCGv_i32 tmp
= tcg_const_i32(4);
14951 gen_a64_set_pc_im(dc
->base
.pc_next
);
14952 gen_helper_wfi(cpu_env
, tmp
);
14953 tcg_temp_free_i32(tmp
);
14954 /* The helper doesn't necessarily throw an exception, but we
14955 * must go back to the main loop to check for interrupts anyway.
14957 tcg_gen_exit_tb(NULL
, 0);
14964 static void aarch64_tr_disas_log(const DisasContextBase
*dcbase
,
14967 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14969 qemu_log("IN: %s\n", lookup_symbol(dc
->base
.pc_first
));
14970 log_target_disas(cpu
, dc
->base
.pc_first
, dc
->base
.tb
->size
);
14973 const TranslatorOps aarch64_translator_ops
= {
14974 .init_disas_context
= aarch64_tr_init_disas_context
,
14975 .tb_start
= aarch64_tr_tb_start
,
14976 .insn_start
= aarch64_tr_insn_start
,
14977 .translate_insn
= aarch64_tr_translate_insn
,
14978 .tb_stop
= aarch64_tr_tb_stop
,
14979 .disas_log
= aarch64_tr_disas_log
,