?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
boot-serial-test: fallback to kvm accelerator
[qemu.git] / target / mips / cpu.h
blob74f6a5b0980605457994c0b17c84c57042d60ac1
1 #ifndef MIPS_CPU_H
2 #define MIPS_CPU_H
3
4 //#define DEBUG_OP
5
6 #define ALIGNED_ONLY
7
8 #define CPUArchState struct CPUMIPSState
9
10 #include "qemu-common.h"
11 #include "cpu-qom.h"
12 #include "mips-defs.h"
13 #include "exec/cpu-defs.h"
14 #include "fpu/softfloat.h"
15
16 struct CPUMIPSState;
17
18 typedef struct r4k_tlb_t r4k_tlb_t;
19 struct r4k_tlb_t {
20 target_ulong VPN;
21 uint32_t PageMask;
22 uint16_t ASID;
23 unsigned int G:1;
24 unsigned int C0:3;
25 unsigned int C1:3;
26 unsigned int V0:1;
27 unsigned int V1:1;
28 unsigned int D0:1;
29 unsigned int D1:1;
30 unsigned int XI0:1;
31 unsigned int XI1:1;
32 unsigned int RI0:1;
33 unsigned int RI1:1;
34 unsigned int EHINV:1;
35 uint64_t PFN[2];
36 };
37
38 #if !defined(CONFIG_USER_ONLY)
39 typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
40 struct CPUMIPSTLBContext {
41 uint32_t nb_tlb;
42 uint32_t tlb_in_use;
43 int (*map_address) (struct CPUMIPSState *env, hwaddr *physical, int *prot, target_ulong address, int rw, int access_type);
44 void (*helper_tlbwi)(struct CPUMIPSState *env);
45 void (*helper_tlbwr)(struct CPUMIPSState *env);
46 void (*helper_tlbp)(struct CPUMIPSState *env);
47 void (*helper_tlbr)(struct CPUMIPSState *env);
48 void (*helper_tlbinv)(struct CPUMIPSState *env);
49 void (*helper_tlbinvf)(struct CPUMIPSState *env);
50 union {
51 struct {
52 r4k_tlb_t tlb[MIPS_TLB_MAX];
53 } r4k;
54 } mmu;
55 };
56 #endif
57
58 /* MSA Context */
59 #define MSA_WRLEN (128)
60
61 enum CPUMIPSMSADataFormat {
62 DF_BYTE = 0,
63 DF_HALF,
64 DF_WORD,
65 DF_DOUBLE
66 };
67
68 typedef union wr_t wr_t;
69 union wr_t {
70 int8_t b[MSA_WRLEN/8];
71 int16_t h[MSA_WRLEN/16];
72 int32_t w[MSA_WRLEN/32];
73 int64_t d[MSA_WRLEN/64];
74 };
75
76 typedef union fpr_t fpr_t;
77 union fpr_t {
78 float64 fd; /* ieee double precision */
79 float32 fs[2];/* ieee single precision */
80 uint64_t d; /* binary double fixed-point */
81 uint32_t w[2]; /* binary single fixed-point */
82 /* FPU/MSA register mapping is not tested on big-endian hosts. */
83 wr_t wr; /* vector data */
84 };
85 /* define FP_ENDIAN_IDX to access the same location
86 * in the fpr_t union regardless of the host endianness
87 */
88 #if defined(HOST_WORDS_BIGENDIAN)
89 # define FP_ENDIAN_IDX 1
90 #else
91 # define FP_ENDIAN_IDX 0
92 #endif
93
94 typedef struct CPUMIPSFPUContext CPUMIPSFPUContext;
95 struct CPUMIPSFPUContext {
96 /* Floating point registers */
97 fpr_t fpr[32];
98 float_status fp_status;
99 /* fpu implementation/revision register (fir) */
100 uint32_t fcr0;
101 #define FCR0_FREP 29
102 #define FCR0_UFRP 28
103 #define FCR0_HAS2008 23
104 #define FCR0_F64 22
105 #define FCR0_L 21
106 #define FCR0_W 20
107 #define FCR0_3D 19
108 #define FCR0_PS 18
109 #define FCR0_D 17
110 #define FCR0_S 16
111 #define FCR0_PRID 8
112 #define FCR0_REV 0
113 /* fcsr */
114 uint32_t fcr31_rw_bitmask;
115 uint32_t fcr31;
116 #define FCR31_FS 24
117 #define FCR31_ABS2008 19
118 #define FCR31_NAN2008 18
119 #define SET_FP_COND(num,env) do { ((env).fcr31) |= ((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
120 #define CLEAR_FP_COND(num,env) do { ((env).fcr31) &= ~((num) ? (1 << ((num) + 24)) : (1 << 23)); } while(0)
121 #define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | (((env).fcr31 >> 23) & 0x1))
122 #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f)
123 #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f)
124 #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f)
125 #define SET_FP_CAUSE(reg,v) do { (reg) = ((reg) & ~(0x3f << 12)) | ((v & 0x3f) << 12); } while(0)
126 #define SET_FP_ENABLE(reg,v) do { (reg) = ((reg) & ~(0x1f << 7)) | ((v & 0x1f) << 7); } while(0)
127 #define SET_FP_FLAGS(reg,v) do { (reg) = ((reg) & ~(0x1f << 2)) | ((v & 0x1f) << 2); } while(0)
128 #define UPDATE_FP_FLAGS(reg,v) do { (reg) |= ((v & 0x1f) << 2); } while(0)
129 #define FP_INEXACT 1
130 #define FP_UNDERFLOW 2
131 #define FP_OVERFLOW 4
132 #define FP_DIV0 8
133 #define FP_INVALID 16
134 #define FP_UNIMPLEMENTED 32
135 };
136
137 #define NB_MMU_MODES 4
138 #define TARGET_INSN_START_EXTRA_WORDS 2
139
140 typedef struct CPUMIPSMVPContext CPUMIPSMVPContext;
141 struct CPUMIPSMVPContext {
142 int32_t CP0_MVPControl;
143 #define CP0MVPCo_CPA 3
144 #define CP0MVPCo_STLB 2
145 #define CP0MVPCo_VPC 1
146 #define CP0MVPCo_EVP 0
147 int32_t CP0_MVPConf0;
148 #define CP0MVPC0_M 31
149 #define CP0MVPC0_TLBS 29
150 #define CP0MVPC0_GS 28
151 #define CP0MVPC0_PCP 27
152 #define CP0MVPC0_PTLBE 16
153 #define CP0MVPC0_TCA 15
154 #define CP0MVPC0_PVPE 10
155 #define CP0MVPC0_PTC 0
156 int32_t CP0_MVPConf1;
157 #define CP0MVPC1_CIM 31
158 #define CP0MVPC1_CIF 30
159 #define CP0MVPC1_PCX 20
160 #define CP0MVPC1_PCP2 10
161 #define CP0MVPC1_PCP1 0
162 };
163
164 typedef struct mips_def_t mips_def_t;
165
166 #define MIPS_SHADOW_SET_MAX 16
167 #define MIPS_TC_MAX 5
168 #define MIPS_FPU_MAX 1
169 #define MIPS_DSP_ACC 4
170 #define MIPS_KSCRATCH_NUM 6
171 #define MIPS_MAAR_MAX 16 /* Must be an even number. */
172
173 typedef struct TCState TCState;
174 struct TCState {
175 target_ulong gpr[32];
176 target_ulong PC;
177 target_ulong HI[MIPS_DSP_ACC];
178 target_ulong LO[MIPS_DSP_ACC];
179 target_ulong ACX[MIPS_DSP_ACC];
180 target_ulong DSPControl;
181 int32_t CP0_TCStatus;
182 #define CP0TCSt_TCU3 31
183 #define CP0TCSt_TCU2 30
184 #define CP0TCSt_TCU1 29
185 #define CP0TCSt_TCU0 28
186 #define CP0TCSt_TMX 27
187 #define CP0TCSt_RNST 23
188 #define CP0TCSt_TDS 21
189 #define CP0TCSt_DT 20
190 #define CP0TCSt_DA 15
191 #define CP0TCSt_A 13
192 #define CP0TCSt_TKSU 11
193 #define CP0TCSt_IXMT 10
194 #define CP0TCSt_TASID 0
195 int32_t CP0_TCBind;
196 #define CP0TCBd_CurTC 21
197 #define CP0TCBd_TBE 17
198 #define CP0TCBd_CurVPE 0
199 target_ulong CP0_TCHalt;
200 target_ulong CP0_TCContext;
201 target_ulong CP0_TCSchedule;
202 target_ulong CP0_TCScheFBack;
203 int32_t CP0_Debug_tcstatus;
204 target_ulong CP0_UserLocal;
205
206 int32_t msacsr;
207
208 #define MSACSR_FS 24
209 #define MSACSR_FS_MASK (1 << MSACSR_FS)
210 #define MSACSR_NX 18
211 #define MSACSR_NX_MASK (1 << MSACSR_NX)
212 #define MSACSR_CEF 2
213 #define MSACSR_CEF_MASK (0xffff << MSACSR_CEF)
214 #define MSACSR_RM 0
215 #define MSACSR_RM_MASK (0x3 << MSACSR_RM)
216 #define MSACSR_MASK (MSACSR_RM_MASK | MSACSR_CEF_MASK | MSACSR_NX_MASK | \
217 MSACSR_FS_MASK)
218
219 float_status msa_fp_status;
220 };
221
222 typedef struct CPUMIPSState CPUMIPSState;
223 struct CPUMIPSState {
224 TCState active_tc;
225 CPUMIPSFPUContext active_fpu;
226
227 uint32_t current_tc;
228 uint32_t current_fpu;
229
230 uint32_t SEGBITS;
231 uint32_t PABITS;
232 #if defined(TARGET_MIPS64)
233 # define PABITS_BASE 36
234 #else
235 # define PABITS_BASE 32
236 #endif
237 target_ulong SEGMask;
238 uint64_t PAMask;
239 #define PAMASK_BASE ((1ULL << PABITS_BASE) - 1)
240
241 int32_t msair;
242 #define MSAIR_ProcID 8
243 #define MSAIR_Rev 0
244
245 int32_t CP0_Index;
246 /* CP0_MVP* are per MVP registers. */
247 int32_t CP0_VPControl;
248 #define CP0VPCtl_DIS 0
249 int32_t CP0_Random;
250 int32_t CP0_VPEControl;
251 #define CP0VPECo_YSI 21
252 #define CP0VPECo_GSI 20
253 #define CP0VPECo_EXCPT 16
254 #define CP0VPECo_TE 15
255 #define CP0VPECo_TargTC 0
256 int32_t CP0_VPEConf0;
257 #define CP0VPEC0_M 31
258 #define CP0VPEC0_XTC 21
259 #define CP0VPEC0_TCS 19
260 #define CP0VPEC0_SCS 18
261 #define CP0VPEC0_DSC 17
262 #define CP0VPEC0_ICS 16
263 #define CP0VPEC0_MVP 1
264 #define CP0VPEC0_VPA 0
265 int32_t CP0_VPEConf1;
266 #define CP0VPEC1_NCX 20
267 #define CP0VPEC1_NCP2 10
268 #define CP0VPEC1_NCP1 0
269 target_ulong CP0_YQMask;
270 target_ulong CP0_VPESchedule;
271 target_ulong CP0_VPEScheFBack;
272 int32_t CP0_VPEOpt;
273 #define CP0VPEOpt_IWX7 15
274 #define CP0VPEOpt_IWX6 14
275 #define CP0VPEOpt_IWX5 13
276 #define CP0VPEOpt_IWX4 12
277 #define CP0VPEOpt_IWX3 11
278 #define CP0VPEOpt_IWX2 10
279 #define CP0VPEOpt_IWX1 9
280 #define CP0VPEOpt_IWX0 8
281 #define CP0VPEOpt_DWX7 7
282 #define CP0VPEOpt_DWX6 6
283 #define CP0VPEOpt_DWX5 5
284 #define CP0VPEOpt_DWX4 4
285 #define CP0VPEOpt_DWX3 3
286 #define CP0VPEOpt_DWX2 2
287 #define CP0VPEOpt_DWX1 1
288 #define CP0VPEOpt_DWX0 0
289 uint64_t CP0_EntryLo0;
290 uint64_t CP0_EntryLo1;
291 #if defined(TARGET_MIPS64)
292 # define CP0EnLo_RI 63
293 # define CP0EnLo_XI 62
294 #else
295 # define CP0EnLo_RI 31
296 # define CP0EnLo_XI 30
297 #endif
298 int32_t CP0_GlobalNumber;
299 #define CP0GN_VPId 0
300 target_ulong CP0_Context;
301 target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM];
302 int32_t CP0_PageMask;
303 int32_t CP0_PageGrain_rw_bitmask;
304 int32_t CP0_PageGrain;
305 #define CP0PG_RIE 31
306 #define CP0PG_XIE 30
307 #define CP0PG_ELPA 29
308 #define CP0PG_IEC 27
309 target_ulong CP0_SegCtl0;
310 target_ulong CP0_SegCtl1;
311 target_ulong CP0_SegCtl2;
312 #define CP0SC_PA 9
313 #define CP0SC_PA_MASK (0x7FULL << CP0SC_PA)
314 #define CP0SC_PA_1GMASK (0x7EULL << CP0SC_PA)
315 #define CP0SC_AM 4
316 #define CP0SC_AM_MASK (0x7ULL << CP0SC_AM)
317 #define CP0SC_AM_UK 0ULL
318 #define CP0SC_AM_MK 1ULL
319 #define CP0SC_AM_MSK 2ULL
320 #define CP0SC_AM_MUSK 3ULL
321 #define CP0SC_AM_MUSUK 4ULL
322 #define CP0SC_AM_USK 5ULL
323 #define CP0SC_AM_UUSK 7ULL
324 #define CP0SC_EU 3
325 #define CP0SC_EU_MASK (1ULL << CP0SC_EU)
326 #define CP0SC_C 0
327 #define CP0SC_C_MASK (0x7ULL << CP0SC_C)
328 #define CP0SC_MASK (CP0SC_C_MASK | CP0SC_EU_MASK | CP0SC_AM_MASK | \
329 CP0SC_PA_MASK)
330 #define CP0SC_1GMASK (CP0SC_C_MASK | CP0SC_EU_MASK | CP0SC_AM_MASK | \
331 CP0SC_PA_1GMASK)
332 #define CP0SC0_MASK (CP0SC_MASK | (CP0SC_MASK << 16))
333 #define CP0SC1_XAM 59
334 #define CP0SC1_XAM_MASK (0x7ULL << CP0SC1_XAM)
335 #define CP0SC1_MASK (CP0SC_MASK | (CP0SC_MASK << 16) | CP0SC1_XAM_MASK)
336 #define CP0SC2_XR 56
337 #define CP0SC2_XR_MASK (0xFFULL << CP0SC2_XR)
338 #define CP0SC2_MASK (CP0SC_1GMASK | (CP0SC_1GMASK << 16) | CP0SC2_XR_MASK)
339 int32_t CP0_Wired;
340 int32_t CP0_SRSConf0_rw_bitmask;
341 int32_t CP0_SRSConf0;
342 #define CP0SRSC0_M 31
343 #define CP0SRSC0_SRS3 20
344 #define CP0SRSC0_SRS2 10
345 #define CP0SRSC0_SRS1 0
346 int32_t CP0_SRSConf1_rw_bitmask;
347 int32_t CP0_SRSConf1;
348 #define CP0SRSC1_M 31
349 #define CP0SRSC1_SRS6 20
350 #define CP0SRSC1_SRS5 10
351 #define CP0SRSC1_SRS4 0
352 int32_t CP0_SRSConf2_rw_bitmask;
353 int32_t CP0_SRSConf2;
354 #define CP0SRSC2_M 31
355 #define CP0SRSC2_SRS9 20
356 #define CP0SRSC2_SRS8 10
357 #define CP0SRSC2_SRS7 0
358 int32_t CP0_SRSConf3_rw_bitmask;
359 int32_t CP0_SRSConf3;
360 #define CP0SRSC3_M 31
361 #define CP0SRSC3_SRS12 20
362 #define CP0SRSC3_SRS11 10
363 #define CP0SRSC3_SRS10 0
364 int32_t CP0_SRSConf4_rw_bitmask;
365 int32_t CP0_SRSConf4;
366 #define CP0SRSC4_SRS15 20
367 #define CP0SRSC4_SRS14 10
368 #define CP0SRSC4_SRS13 0
369 int32_t CP0_HWREna;
370 target_ulong CP0_BadVAddr;
371 uint32_t CP0_BadInstr;
372 uint32_t CP0_BadInstrP;
373 int32_t CP0_Count;
374 target_ulong CP0_EntryHi;
375 #define CP0EnHi_EHINV 10
376 target_ulong CP0_EntryHi_ASID_mask;
377 int32_t CP0_Compare;
378 int32_t CP0_Status;
379 #define CP0St_CU3 31
380 #define CP0St_CU2 30
381 #define CP0St_CU1 29
382 #define CP0St_CU0 28
383 #define CP0St_RP 27
384 #define CP0St_FR 26
385 #define CP0St_RE 25
386 #define CP0St_MX 24
387 #define CP0St_PX 23
388 #define CP0St_BEV 22
389 #define CP0St_TS 21
390 #define CP0St_SR 20
391 #define CP0St_NMI 19
392 #define CP0St_IM 8
393 #define CP0St_KX 7
394 #define CP0St_SX 6
395 #define CP0St_UX 5
396 #define CP0St_KSU 3
397 #define CP0St_ERL 2
398 #define CP0St_EXL 1
399 #define CP0St_IE 0
400 int32_t CP0_IntCtl;
401 #define CP0IntCtl_IPTI 29
402 #define CP0IntCtl_IPPCI 26
403 #define CP0IntCtl_VS 5
404 int32_t CP0_SRSCtl;
405 #define CP0SRSCtl_HSS 26
406 #define CP0SRSCtl_EICSS 18
407 #define CP0SRSCtl_ESS 12
408 #define CP0SRSCtl_PSS 6
409 #define CP0SRSCtl_CSS 0
410 int32_t CP0_SRSMap;
411 #define CP0SRSMap_SSV7 28
412 #define CP0SRSMap_SSV6 24
413 #define CP0SRSMap_SSV5 20
414 #define CP0SRSMap_SSV4 16
415 #define CP0SRSMap_SSV3 12
416 #define CP0SRSMap_SSV2 8
417 #define CP0SRSMap_SSV1 4
418 #define CP0SRSMap_SSV0 0
419 int32_t CP0_Cause;
420 #define CP0Ca_BD 31
421 #define CP0Ca_TI 30
422 #define CP0Ca_CE 28
423 #define CP0Ca_DC 27
424 #define CP0Ca_PCI 26
425 #define CP0Ca_IV 23
426 #define CP0Ca_WP 22
427 #define CP0Ca_IP 8
428 #define CP0Ca_IP_mask 0x0000FF00
429 #define CP0Ca_EC 2
430 target_ulong CP0_EPC;
431 int32_t CP0_PRid;
432 target_ulong CP0_EBase;
433 target_ulong CP0_EBaseWG_rw_bitmask;
434 #define CP0EBase_WG 11
435 target_ulong CP0_CMGCRBase;
436 int32_t CP0_Config0;
437 #define CP0C0_M 31
438 #define CP0C0_K23 28
439 #define CP0C0_KU 25
440 #define CP0C0_MDU 20
441 #define CP0C0_MM 18
442 #define CP0C0_BM 16
443 #define CP0C0_BE 15
444 #define CP0C0_AT 13
445 #define CP0C0_AR 10
446 #define CP0C0_MT 7
447 #define CP0C0_VI 3
448 #define CP0C0_K0 0
449 int32_t CP0_Config1;
450 #define CP0C1_M 31
451 #define CP0C1_MMU 25
452 #define CP0C1_IS 22
453 #define CP0C1_IL 19
454 #define CP0C1_IA 16
455 #define CP0C1_DS 13
456 #define CP0C1_DL 10
457 #define CP0C1_DA 7
458 #define CP0C1_C2 6
459 #define CP0C1_MD 5
460 #define CP0C1_PC 4
461 #define CP0C1_WR 3
462 #define CP0C1_CA 2
463 #define CP0C1_EP 1
464 #define CP0C1_FP 0
465 int32_t CP0_Config2;
466 #define CP0C2_M 31
467 #define CP0C2_TU 28
468 #define CP0C2_TS 24
469 #define CP0C2_TL 20
470 #define CP0C2_TA 16
471 #define CP0C2_SU 12
472 #define CP0C2_SS 8
473 #define CP0C2_SL 4
474 #define CP0C2_SA 0
475 int32_t CP0_Config3;
476 #define CP0C3_M 31
477 #define CP0C3_BPG 30
478 #define CP0C3_CMGCR 29
479 #define CP0C3_MSAP 28
480 #define CP0C3_BP 27
481 #define CP0C3_BI 26
482 #define CP0C3_SC 25
483 #define CP0C3_IPLW 21
484 #define CP0C3_MMAR 18
485 #define CP0C3_MCU 17
486 #define CP0C3_ISA_ON_EXC 16
487 #define CP0C3_ISA 14
488 #define CP0C3_ULRI 13
489 #define CP0C3_RXI 12
490 #define CP0C3_DSP2P 11
491 #define CP0C3_DSPP 10
492 #define CP0C3_LPA 7
493 #define CP0C3_VEIC 6
494 #define CP0C3_VInt 5
495 #define CP0C3_SP 4
496 #define CP0C3_CDMM 3
497 #define CP0C3_MT 2
498 #define CP0C3_SM 1
499 #define CP0C3_TL 0
500 int32_t CP0_Config4;
501 int32_t CP0_Config4_rw_bitmask;
502 #define CP0C4_M 31
503 #define CP0C4_IE 29
504 #define CP0C4_AE 28
505 #define CP0C4_KScrExist 16
506 #define CP0C4_MMUExtDef 14
507 #define CP0C4_FTLBPageSize 8
508 #define CP0C4_FTLBWays 4
509 #define CP0C4_FTLBSets 0
510 #define CP0C4_MMUSizeExt 0
511 int32_t CP0_Config5;
512 int32_t CP0_Config5_rw_bitmask;
513 #define CP0C5_M 31
514 #define CP0C5_K 30
515 #define CP0C5_CV 29
516 #define CP0C5_EVA 28
517 #define CP0C5_MSAEn 27
518 #define CP0C5_XNP 13
519 #define CP0C5_UFE 9
520 #define CP0C5_FRE 8
521 #define CP0C5_VP 7
522 #define CP0C5_SBRI 6
523 #define CP0C5_MVH 5
524 #define CP0C5_LLB 4
525 #define CP0C5_MRP 3
526 #define CP0C5_UFR 2
527 #define CP0C5_NFExists 0
528 int32_t CP0_Config6;
529 int32_t CP0_Config7;
530 uint64_t CP0_MAAR[MIPS_MAAR_MAX];
531 int32_t CP0_MAARI;
532 /* XXX: Maybe make LLAddr per-TC? */
533 uint64_t lladdr;
534 target_ulong llval;
535 target_ulong llnewval;
536 target_ulong llreg;
537 uint64_t CP0_LLAddr_rw_bitmask;
538 int CP0_LLAddr_shift;
539 target_ulong CP0_WatchLo[8];
540 int32_t CP0_WatchHi[8];
541 #define CP0WH_ASID 16
542 target_ulong CP0_XContext;
543 int32_t CP0_Framemask;
544 int32_t CP0_Debug;
545 #define CP0DB_DBD 31
546 #define CP0DB_DM 30
547 #define CP0DB_LSNM 28
548 #define CP0DB_Doze 27
549 #define CP0DB_Halt 26
550 #define CP0DB_CNT 25
551 #define CP0DB_IBEP 24
552 #define CP0DB_DBEP 21
553 #define CP0DB_IEXI 20
554 #define CP0DB_VER 15
555 #define CP0DB_DEC 10
556 #define CP0DB_SSt 8
557 #define CP0DB_DINT 5
558 #define CP0DB_DIB 4
559 #define CP0DB_DDBS 3
560 #define CP0DB_DDBL 2
561 #define CP0DB_DBp 1
562 #define CP0DB_DSS 0
563 target_ulong CP0_DEPC;
564 int32_t CP0_Performance0;
565 int32_t CP0_ErrCtl;
566 #define CP0EC_WST 29
567 #define CP0EC_SPR 28
568 #define CP0EC_ITC 26
569 uint64_t CP0_TagLo;
570 int32_t CP0_DataLo;
571 int32_t CP0_TagHi;
572 int32_t CP0_DataHi;
573 target_ulong CP0_ErrorEPC;
574 int32_t CP0_DESAVE;
575 /* We waste some space so we can handle shadow registers like TCs. */
576 TCState tcs[MIPS_SHADOW_SET_MAX];
577 CPUMIPSFPUContext fpus[MIPS_FPU_MAX];
578 /* QEMU */
579 int error_code;
580 #define EXCP_TLB_NOMATCH 0x1
581 #define EXCP_INST_NOTAVAIL 0x2 /* No valid instruction word for BadInstr */
582 uint32_t hflags; /* CPU State */
583 /* TMASK defines different execution modes */
584 #define MIPS_HFLAG_TMASK 0x1F5807FF
585 #define MIPS_HFLAG_MODE 0x00007 /* execution modes */
586 /* The KSU flags must be the lowest bits in hflags. The flag order
587 must be the same as defined for CP0 Status. This allows to use
588 the bits as the value of mmu_idx. */
589 #define MIPS_HFLAG_KSU 0x00003 /* kernel/supervisor/user mode mask */
590 #define MIPS_HFLAG_UM 0x00002 /* user mode flag */
591 #define MIPS_HFLAG_SM 0x00001 /* supervisor mode flag */
592 #define MIPS_HFLAG_KM 0x00000 /* kernel mode flag */
593 #define MIPS_HFLAG_DM 0x00004 /* Debug mode */
594 #define MIPS_HFLAG_64 0x00008 /* 64-bit instructions enabled */
595 #define MIPS_HFLAG_CP0 0x00010 /* CP0 enabled */
596 #define MIPS_HFLAG_FPU 0x00020 /* FPU enabled */
597 #define MIPS_HFLAG_F64 0x00040 /* 64-bit FPU enabled */
598 /* True if the MIPS IV COP1X instructions can be used. This also
599 controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S
600 and RSQRT.D. */
601 #define MIPS_HFLAG_COP1X 0x00080 /* COP1X instructions enabled */
602 #define MIPS_HFLAG_RE 0x00100 /* Reversed endianness */
603 #define MIPS_HFLAG_AWRAP 0x00200 /* 32-bit compatibility address wrapping */
604 #define MIPS_HFLAG_M16 0x00400 /* MIPS16 mode flag */
605 #define MIPS_HFLAG_M16_SHIFT 10
606 /* If translation is interrupted between the branch instruction and
607 * the delay slot, record what type of branch it is so that we can
608 * resume translation properly. It might be possible to reduce
609 * this from three bits to two. */
610 #define MIPS_HFLAG_BMASK_BASE 0x803800
611 #define MIPS_HFLAG_B 0x00800 /* Unconditional branch */
612 #define MIPS_HFLAG_BC 0x01000 /* Conditional branch */
613 #define MIPS_HFLAG_BL 0x01800 /* Likely branch */
614 #define MIPS_HFLAG_BR 0x02000 /* branch to register (can't link TB) */
615 /* Extra flags about the current pending branch. */
616 #define MIPS_HFLAG_BMASK_EXT 0x7C000
617 #define MIPS_HFLAG_B16 0x04000 /* branch instruction was 16 bits */
618 #define MIPS_HFLAG_BDS16 0x08000 /* branch requires 16-bit delay slot */
619 #define MIPS_HFLAG_BDS32 0x10000 /* branch requires 32-bit delay slot */
620 #define MIPS_HFLAG_BDS_STRICT 0x20000 /* Strict delay slot size */
621 #define MIPS_HFLAG_BX 0x40000 /* branch exchanges execution mode */
622 #define MIPS_HFLAG_BMASK (MIPS_HFLAG_BMASK_BASE | MIPS_HFLAG_BMASK_EXT)
623 /* MIPS DSP resources access. */
624 #define MIPS_HFLAG_DSP 0x080000 /* Enable access to MIPS DSP resources. */
625 #define MIPS_HFLAG_DSPR2 0x100000 /* Enable access to MIPS DSPR2 resources. */
626 /* Extra flag about HWREna register. */
627 #define MIPS_HFLAG_HWRENA_ULR 0x200000 /* ULR bit from HWREna is set. */
628 #define MIPS_HFLAG_SBRI 0x400000 /* R6 SDBBP causes RI excpt. in user mode */
629 #define MIPS_HFLAG_FBNSLOT 0x800000 /* Forbidden slot */
630 #define MIPS_HFLAG_MSA 0x1000000
631 #define MIPS_HFLAG_FRE 0x2000000 /* FRE enabled */
632 #define MIPS_HFLAG_ELPA 0x4000000
633 #define MIPS_HFLAG_ITC_CACHE 0x8000000 /* CACHE instr. operates on ITC tag */
634 #define MIPS_HFLAG_ERL 0x10000000 /* error level flag */
635 target_ulong btarget; /* Jump / branch target */
636 target_ulong bcond; /* Branch condition (if needed) */
637
638 int SYNCI_Step; /* Address step size for SYNCI */
639 int CCRes; /* Cycle count resolution/divisor */
640 uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
641 uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
642 int insn_flags; /* Supported instruction set */
643
644 /* Fields up to this point are cleared by a CPU reset */
645 struct {} end_reset_fields;
646
647 CPU_COMMON
648
649 /* Fields from here on are preserved across CPU reset. */
650 CPUMIPSMVPContext *mvp;
651 #if !defined(CONFIG_USER_ONLY)
652 CPUMIPSTLBContext *tlb;
653 #endif
654
655 const mips_def_t *cpu_model;
656 void *irq[8];
657 QEMUTimer *timer; /* Internal timer */
658 MemoryRegion *itc_tag; /* ITC Configuration Tags */
659 target_ulong exception_base; /* ExceptionBase input to the core */
660 };
661
662 /**
663 * MIPSCPU:
664 * @env: #CPUMIPSState
665 *
666 * A MIPS CPU.
667 */
668 struct MIPSCPU {
669 /*< private >*/
670 CPUState parent_obj;
671 /*< public >*/
672
673 CPUMIPSState env;
674 };
675
676 static inline MIPSCPU *mips_env_get_cpu(CPUMIPSState *env)
677 {
678 return container_of(env, MIPSCPU, env);
679 }
680
681 #define ENV_GET_CPU(e) CPU(mips_env_get_cpu(e))
682
683 #define ENV_OFFSET offsetof(MIPSCPU, env)
684
685 #ifndef CONFIG_USER_ONLY
686 extern const struct VMStateDescription vmstate_mips_cpu;
687 #endif
688
689 void mips_cpu_do_interrupt(CPUState *cpu);
690 bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);
691 void mips_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
692 int flags);
693 hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
694 int mips_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
695 int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
696 void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
697 MMUAccessType access_type,
698 int mmu_idx, uintptr_t retaddr);
699
700 #if !defined(CONFIG_USER_ONLY)
701 int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
702 target_ulong address, int rw, int access_type);
703 int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
704 target_ulong address, int rw, int access_type);
705 int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
706 target_ulong address, int rw, int access_type);
707 void r4k_helper_tlbwi(CPUMIPSState *env);
708 void r4k_helper_tlbwr(CPUMIPSState *env);
709 void r4k_helper_tlbp(CPUMIPSState *env);
710 void r4k_helper_tlbr(CPUMIPSState *env);
711 void r4k_helper_tlbinv(CPUMIPSState *env);
712 void r4k_helper_tlbinvf(CPUMIPSState *env);
713
714 void mips_cpu_unassigned_access(CPUState *cpu, hwaddr addr,
715 bool is_write, bool is_exec, int unused,
716 unsigned size);
717 #endif
718
719 void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf);
720
721 #define cpu_signal_handler cpu_mips_signal_handler
722 #define cpu_list mips_cpu_list
723
724 extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env);
725 extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env);
726
727 /* MMU modes definitions. We carefully match the indices with our
728 hflags layout. */
729 #define MMU_MODE0_SUFFIX _kernel
730 #define MMU_MODE1_SUFFIX _super
731 #define MMU_MODE2_SUFFIX _user
732 #define MMU_MODE3_SUFFIX _error
733 #define MMU_USER_IDX 2
734
735 static inline int hflags_mmu_index(uint32_t hflags)
736 {
737 if (hflags & MIPS_HFLAG_ERL) {
738 return 3; /* ERL */
739 } else {
740 return hflags & MIPS_HFLAG_KSU;
741 }
742 }
743
744 static inline int cpu_mmu_index (CPUMIPSState *env, bool ifetch)
745 {
746 return hflags_mmu_index(env->hflags);
747 }
748
749 static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env)
750 {
751 return (env->CP0_Status & (1 << CP0St_IE)) &&
752 !(env->CP0_Status & (1 << CP0St_EXL)) &&
753 !(env->CP0_Status & (1 << CP0St_ERL)) &&
754 !(env->hflags & MIPS_HFLAG_DM) &&
755 /* Note that the TCStatus IXMT field is initialized to zero,
756 and only MT capable cores can set it to one. So we don't
757 need to check for MT capabilities here. */
758 !(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT));
759 }
760
761 /* Check if there is pending and not masked out interrupt */
762 static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
763 {
764 int32_t pending;
765 int32_t status;
766 bool r;
767
768 pending = env->CP0_Cause & CP0Ca_IP_mask;
769 status = env->CP0_Status & CP0Ca_IP_mask;
770
771 if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
772 /* A MIPS configured with a vectorizing external interrupt controller
773 will feed a vector into the Cause pending lines. The core treats
774 the status lines as a vector level, not as indiviual masks. */
775 r = pending > status;
776 } else {
777 /* A MIPS configured with compatibility or VInt (Vectored Interrupts)
778 treats the pending lines as individual interrupt lines, the status
779 lines are individual masks. */
780 r = (pending & status) != 0;
781 }
782 return r;
783 }
784
785 #include "exec/cpu-all.h"
786
787 /* Memory access type :
788 * may be needed for precise access rights control and precise exceptions.
789 */
790 enum {
791 /* 1 bit to define user level / supervisor access */
792 ACCESS_USER = 0x00,
793 ACCESS_SUPER = 0x01,
794 /* 1 bit to indicate direction */
795 ACCESS_STORE = 0x02,
796 /* Type of instruction that generated the access */
797 ACCESS_CODE = 0x10, /* Code fetch access */
798 ACCESS_INT = 0x20, /* Integer load/store access */
799 ACCESS_FLOAT = 0x30, /* floating point load/store access */
800 };
801
802 /* Exceptions */
803 enum {
804 EXCP_NONE = -1,
805 EXCP_RESET = 0,
806 EXCP_SRESET,
807 EXCP_DSS,
808 EXCP_DINT,
809 EXCP_DDBL,
810 EXCP_DDBS,
811 EXCP_NMI,
812 EXCP_MCHECK,
813 EXCP_EXT_INTERRUPT, /* 8 */
814 EXCP_DFWATCH,
815 EXCP_DIB,
816 EXCP_IWATCH,
817 EXCP_AdEL,
818 EXCP_AdES,
819 EXCP_TLBF,
820 EXCP_IBE,
821 EXCP_DBp, /* 16 */
822 EXCP_SYSCALL,
823 EXCP_BREAK,
824 EXCP_CpU,
825 EXCP_RI,
826 EXCP_OVERFLOW,
827 EXCP_TRAP,
828 EXCP_FPE,
829 EXCP_DWATCH, /* 24 */
830 EXCP_LTLBL,
831 EXCP_TLBL,
832 EXCP_TLBS,
833 EXCP_DBE,
834 EXCP_THREAD,
835 EXCP_MDMX,
836 EXCP_C2E,
837 EXCP_CACHE, /* 32 */
838 EXCP_DSPDIS,
839 EXCP_MSADIS,
840 EXCP_MSAFPE,
841 EXCP_TLBXI,
842 EXCP_TLBRI,
843
844 EXCP_LAST = EXCP_TLBRI,
845 };
846 /* Dummy exception for conditional stores. */
847 #define EXCP_SC 0x100
848
849 /*
850 * This is an interrnally generated WAKE request line.
851 * It is driven by the CPU itself. Raised when the MT
852 * block wants to wake a VPE from an inactive state and
853 * cleared when VPE goes from active to inactive.
854 */
855 #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0
856
857 void mips_tcg_init(void);
858 MIPSCPU *cpu_mips_init(const char *cpu_model);
859 int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
860
861 #define cpu_init(cpu_model) CPU(cpu_mips_init(cpu_model))
862 bool cpu_supports_cps_smp(const char *cpu_model);
863 bool cpu_supports_isa(const char *cpu_model, unsigned int isa);
864 void cpu_set_exception_base(int vp_index, target_ulong address);
865
866 /* TODO QOM'ify CPU reset and remove */
867 void cpu_state_reset(CPUMIPSState *s);
868
869 /* mips_timer.c */
870 uint32_t cpu_mips_get_random (CPUMIPSState *env);
871 uint32_t cpu_mips_get_count (CPUMIPSState *env);
872 void cpu_mips_store_count (CPUMIPSState *env, uint32_t value);
873 void cpu_mips_store_compare (CPUMIPSState *env, uint32_t value);
874 void cpu_mips_start_count(CPUMIPSState *env);
875 void cpu_mips_stop_count(CPUMIPSState *env);
876
877 /* mips_int.c */
878 void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level);
879
880 /* helper.c */
881 int mips_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
882 int mmu_idx);
883
884 /* op_helper.c */
885 uint32_t float_class_s(uint32_t arg, float_status *fst);
886 uint64_t float_class_d(uint64_t arg, float_status *fst);
887
888 #if !defined(CONFIG_USER_ONLY)
889 void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra);
890 hwaddr cpu_mips_translate_address (CPUMIPSState *env, target_ulong address,
891 int rw);
892 #endif
893 target_ulong exception_resume_pc (CPUMIPSState *env);
894
895 /* op_helper.c */
896 extern unsigned int ieee_rm[];
897 int ieee_ex_to_mips(int xcpt);
898
899 static inline void restore_rounding_mode(CPUMIPSState *env)
900 {
901 set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3],
902 &env->active_fpu.fp_status);
903 }
904
905 static inline void restore_flush_mode(CPUMIPSState *env)
906 {
907 set_flush_to_zero((env->active_fpu.fcr31 & (1 << FCR31_FS)) != 0,
908 &env->active_fpu.fp_status);
909 }
910
911 static inline void restore_snan_bit_mode(CPUMIPSState *env)
912 {
913 set_snan_bit_is_one((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) == 0,
914 &env->active_fpu.fp_status);
915 }
916
917 static inline void restore_fp_status(CPUMIPSState *env)
918 {
919 restore_rounding_mode(env);
920 restore_flush_mode(env);
921 restore_snan_bit_mode(env);
922 }
923
924 static inline void restore_msa_fp_status(CPUMIPSState *env)
925 {
926 float_status *status = &env->active_tc.msa_fp_status;
927 int rounding_mode = (env->active_tc.msacsr & MSACSR_RM_MASK) >> MSACSR_RM;
928 bool flush_to_zero = (env->active_tc.msacsr & MSACSR_FS_MASK) != 0;
929
930 set_float_rounding_mode(ieee_rm[rounding_mode], status);
931 set_flush_to_zero(flush_to_zero, status);
932 set_flush_inputs_to_zero(flush_to_zero, status);
933 }
934
935 static inline void restore_pamask(CPUMIPSState *env)
936 {
937 if (env->hflags & MIPS_HFLAG_ELPA) {
938 env->PAMask = (1ULL << env->PABITS) - 1;
939 } else {
940 env->PAMask = PAMASK_BASE;
941 }
942 }
943
944 static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc,
945 target_ulong *cs_base, uint32_t *flags)
946 {
947 *pc = env->active_tc.PC;
948 *cs_base = 0;
949 *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK |
950 MIPS_HFLAG_HWRENA_ULR);
951 }
952
953 static inline int mips_vpe_active(CPUMIPSState *env)
954 {
955 int active = 1;
956
957 /* Check that the VPE is enabled. */
958 if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) {
959 active = 0;
960 }
961 /* Check that the VPE is activated. */
962 if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))) {
963 active = 0;
964 }
965
966 /* Now verify that there are active thread contexts in the VPE.
967
968 This assumes the CPU model will internally reschedule threads
969 if the active one goes to sleep. If there are no threads available
970 the active one will be in a sleeping state, and we can turn off
971 the entire VPE. */
972 if (!(env->active_tc.CP0_TCStatus & (1 << CP0TCSt_A))) {
973 /* TC is not activated. */
974 active = 0;
975 }
976 if (env->active_tc.CP0_TCHalt & 1) {
977 /* TC is in halt state. */
978 active = 0;
979 }
980
981 return active;
982 }
983
984 static inline int mips_vp_active(CPUMIPSState *env)
985 {
986 CPUState *other_cs = first_cpu;
987
988 /* Check if the VP disabled other VPs (which means the VP is enabled) */
989 if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {
990 return 1;
991 }
992
993 /* Check if the virtual processor is disabled due to a DVP */
994 CPU_FOREACH(other_cs) {
995 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
996 if ((&other_cpu->env != env) &&
997 ((other_cpu->env.CP0_VPControl >> CP0VPCtl_DIS) & 1)) {
998 return 0;
999 }
1000 }
1001 return 1;
1002 }
1003
1004 static inline void compute_hflags(CPUMIPSState *env)
1005 {
1006 env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
1007 MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
1008 MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2 |
1009 MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA | MIPS_HFLAG_FRE |
1010 MIPS_HFLAG_ELPA | MIPS_HFLAG_ERL);
1011 if (env->CP0_Status & (1 << CP0St_ERL)) {
1012 env->hflags |= MIPS_HFLAG_ERL;
1013 }
1014 if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
1015 !(env->CP0_Status & (1 << CP0St_ERL)) &&
1016 !(env->hflags & MIPS_HFLAG_DM)) {
1017 env->hflags |= (env->CP0_Status >> CP0St_KSU) & MIPS_HFLAG_KSU;
1018 }
1019 #if defined(TARGET_MIPS64)
1020 if ((env->insn_flags & ISA_MIPS3) &&
1021 (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_UM) ||
1022 (env->CP0_Status & (1 << CP0St_PX)) ||
1023 (env->CP0_Status & (1 << CP0St_UX)))) {
1024 env->hflags |= MIPS_HFLAG_64;
1025 }
1026
1027 if (!(env->insn_flags & ISA_MIPS3)) {
1028 env->hflags |= MIPS_HFLAG_AWRAP;
1029 } else if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) &&
1030 !(env->CP0_Status & (1 << CP0St_UX))) {
1031 env->hflags |= MIPS_HFLAG_AWRAP;
1032 } else if (env->insn_flags & ISA_MIPS64R6) {
1033 /* Address wrapping for Supervisor and Kernel is specified in R6 */
1034 if ((((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_SM) &&
1035 !(env->CP0_Status & (1 << CP0St_SX))) ||
1036 (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_KM) &&
1037 !(env->CP0_Status & (1 << CP0St_KX)))) {
1038 env->hflags |= MIPS_HFLAG_AWRAP;
1039 }
1040 }
1041 #endif
1042 if (((env->CP0_Status & (1 << CP0St_CU0)) &&
1043 !(env->insn_flags & ISA_MIPS32R6)) ||
1044 !(env->hflags & MIPS_HFLAG_KSU)) {
1045 env->hflags |= MIPS_HFLAG_CP0;
1046 }
1047 if (env->CP0_Status & (1 << CP0St_CU1)) {
1048 env->hflags |= MIPS_HFLAG_FPU;
1049 }
1050 if (env->CP0_Status & (1 << CP0St_FR)) {
1051 env->hflags |= MIPS_HFLAG_F64;
1052 }
1053 if (((env->hflags & MIPS_HFLAG_KSU) != MIPS_HFLAG_KM) &&
1054 (env->CP0_Config5 & (1 << CP0C5_SBRI))) {
1055 env->hflags |= MIPS_HFLAG_SBRI;
1056 }
1057 if (env->insn_flags & ASE_DSPR2) {
1058 /* Enables access MIPS DSP resources, now our cpu is DSP ASER2,
1059 so enable to access DSPR2 resources. */
1060 if (env->CP0_Status & (1 << CP0St_MX)) {
1061 env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2;
1062 }
1063
1064 } else if (env->insn_flags & ASE_DSP) {
1065 /* Enables access MIPS DSP resources, now our cpu is DSP ASE,
1066 so enable to access DSP resources. */
1067 if (env->CP0_Status & (1 << CP0St_MX)) {
1068 env->hflags |= MIPS_HFLAG_DSP;
1069 }
1070
1071 }
1072 if (env->insn_flags & ISA_MIPS32R2) {
1073 if (env->active_fpu.fcr0 & (1 << FCR0_F64)) {
1074 env->hflags |= MIPS_HFLAG_COP1X;
1075 }
1076 } else if (env->insn_flags & ISA_MIPS32) {
1077 if (env->hflags & MIPS_HFLAG_64) {
1078 env->hflags |= MIPS_HFLAG_COP1X;
1079 }
1080 } else if (env->insn_flags & ISA_MIPS4) {
1081 /* All supported MIPS IV CPUs use the XX (CU3) to enable
1082 and disable the MIPS IV extensions to the MIPS III ISA.
1083 Some other MIPS IV CPUs ignore the bit, so the check here
1084 would be too restrictive for them. */
1085 if (env->CP0_Status & (1U << CP0St_CU3)) {
1086 env->hflags |= MIPS_HFLAG_COP1X;
1087 }
1088 }
1089 if (env->insn_flags & ASE_MSA) {
1090 if (env->CP0_Config5 & (1 << CP0C5_MSAEn)) {
1091 env->hflags |= MIPS_HFLAG_MSA;
1092 }
1093 }
1094 if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
1095 if (env->CP0_Config5 & (1 << CP0C5_FRE)) {
1096 env->hflags |= MIPS_HFLAG_FRE;
1097 }
1098 }
1099 if (env->CP0_Config3 & (1 << CP0C3_LPA)) {
1100 if (env->CP0_PageGrain & (1 << CP0PG_ELPA)) {
1101 env->hflags |= MIPS_HFLAG_ELPA;
1102 }
1103 }
1104 }
1105
1106 void cpu_mips_tlb_flush(CPUMIPSState *env);
1107 void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc);
1108 void cpu_mips_store_status(CPUMIPSState *env, target_ulong val);
1109 void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val);
1110
1111 void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t exception,
1112 int error_code, uintptr_t pc);
1113
1114 static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,
1115 uint32_t exception,
1116 uintptr_t pc)
1117 {
1118 do_raise_exception_err(env, exception, 0, pc);
1119 }
1120
1121 #endif /* MIPS_CPU_H */
QEmu