target-ppc/cpu-qom.h

   1 /*
   2  * QEMU PowerPC CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see
  18  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  19  */
  20 #ifndef QEMU_PPC_CPU_QOM_H
  21 #define QEMU_PPC_CPU_QOM_H
  22
  23 #include "qom/cpu.h"
  24
  25 #ifdef TARGET_PPC64
  26 #define TYPE_POWERPC_CPU "powerpc64-cpu"
  27 #elif defined(TARGET_PPCEMB)
  28 #define TYPE_POWERPC_CPU "embedded-powerpc-cpu"
  29 #else
  30 #define TYPE_POWERPC_CPU "powerpc-cpu"
  31 #endif
  32
  33 #define POWERPC_CPU_CLASS(klass) \
  34     OBJECT_CLASS_CHECK(PowerPCCPUClass, (klass), TYPE_POWERPC_CPU)
  35 #define POWERPC_CPU(obj) \
  36     OBJECT_CHECK(PowerPCCPU, (obj), TYPE_POWERPC_CPU)
  37 #define POWERPC_CPU_GET_CLASS(obj) \
  38     OBJECT_GET_CLASS(PowerPCCPUClass, (obj), TYPE_POWERPC_CPU)
  39
  40 typedef struct PowerPCCPU PowerPCCPU;
  41 typedef struct CPUPPCState CPUPPCState;
  42 typedef struct ppc_tb_t ppc_tb_t;
  43 typedef struct ppc_dcr_t ppc_dcr_t;
  44
  45 /*****************************************************************************/
  46 /* MMU model                                                                 */
  47 typedef enum powerpc_mmu_t powerpc_mmu_t;
  48 enum powerpc_mmu_t {
  49     POWERPC_MMU_UNKNOWN    = 0x00000000,
  50     /* Standard 32 bits PowerPC MMU                            */
  51     POWERPC_MMU_32B        = 0x00000001,
  52     /* PowerPC 6xx MMU with software TLB                       */
  53     POWERPC_MMU_SOFT_6xx   = 0x00000002,
  54     /* PowerPC 74xx MMU with software TLB                      */
  55     POWERPC_MMU_SOFT_74xx  = 0x00000003,
  56     /* PowerPC 4xx MMU with software TLB                       */
  57     POWERPC_MMU_SOFT_4xx   = 0x00000004,
  58     /* PowerPC 4xx MMU with software TLB and zones protections */
  59     POWERPC_MMU_SOFT_4xx_Z = 0x00000005,
  60     /* PowerPC MMU in real mode only                           */
  61     POWERPC_MMU_REAL       = 0x00000006,
  62     /* Freescale MPC8xx MMU model                              */
  63     POWERPC_MMU_MPC8xx     = 0x00000007,
  64     /* BookE MMU model                                         */
  65     POWERPC_MMU_BOOKE      = 0x00000008,
  66     /* BookE 2.06 MMU model                                    */
  67     POWERPC_MMU_BOOKE206   = 0x00000009,
  68     /* PowerPC 601 MMU model (specific BATs format)            */
  69     POWERPC_MMU_601        = 0x0000000A,
  70 #define POWERPC_MMU_64       0x00010000
  71 #define POWERPC_MMU_1TSEG    0x00020000
  72 #define POWERPC_MMU_AMR      0x00040000
  73 #define POWERPC_MMU_64K      0x00080000
  74     /* 64 bits PowerPC MMU                                     */
  75     POWERPC_MMU_64B        = POWERPC_MMU_64 | 0x00000001,
  76     /* Architecture 2.03 and later (has LPCR) */
  77     POWERPC_MMU_2_03       = POWERPC_MMU_64 | 0x00000002,
  78     /* Architecture 2.06 variant                               */
  79     POWERPC_MMU_2_06       = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
  80                              | POWERPC_MMU_64K
  81                              | POWERPC_MMU_AMR | 0x00000003,
  82     /* Architecture 2.06 "degraded" (no 1T segments)           */
  83     POWERPC_MMU_2_06a      = POWERPC_MMU_64 | POWERPC_MMU_AMR
  84                              | 0x00000003,
  85     /* Architecture 2.07 variant                               */
  86     POWERPC_MMU_2_07       = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
  87                              | POWERPC_MMU_64K
  88                              | POWERPC_MMU_AMR | 0x00000004,
  89     /* FIXME Add POWERPC_MMU_3_OO defines */
  90     /* Architecture 2.07 "degraded" (no 1T segments)           */
  91     POWERPC_MMU_2_07a      = POWERPC_MMU_64 | POWERPC_MMU_AMR
  92                              | 0x00000004,
  93 };
  94
  95 /*****************************************************************************/
  96 /* Exception model                                                           */
  97 typedef enum powerpc_excp_t powerpc_excp_t;
  98 enum powerpc_excp_t {
  99     POWERPC_EXCP_UNKNOWN   = 0,
 100     /* Standard PowerPC exception model */
 101     POWERPC_EXCP_STD,
 102     /* PowerPC 40x exception model      */
 103     POWERPC_EXCP_40x,
 104     /* PowerPC 601 exception model      */
 105     POWERPC_EXCP_601,
 106     /* PowerPC 602 exception model      */
 107     POWERPC_EXCP_602,
 108     /* PowerPC 603 exception model      */
 109     POWERPC_EXCP_603,
 110     /* PowerPC 603e exception model     */
 111     POWERPC_EXCP_603E,
 112     /* PowerPC G2 exception model       */
 113     POWERPC_EXCP_G2,
 114     /* PowerPC 604 exception model      */
 115     POWERPC_EXCP_604,
 116     /* PowerPC 7x0 exception model      */
 117     POWERPC_EXCP_7x0,
 118     /* PowerPC 7x5 exception model      */
 119     POWERPC_EXCP_7x5,
 120     /* PowerPC 74xx exception model     */
 121     POWERPC_EXCP_74xx,
 122     /* BookE exception model            */
 123     POWERPC_EXCP_BOOKE,
 124     /* PowerPC 970 exception model      */
 125     POWERPC_EXCP_970,
 126     /* POWER7 exception model           */
 127     POWERPC_EXCP_POWER7,
 128     /* POWER8 exception model           */
 129     POWERPC_EXCP_POWER8,
 130 };
 131
 132 /*****************************************************************************/
 133 /* PM instructions */
 134 typedef enum {
 135     PPC_PM_DOZE,
 136     PPC_PM_NAP,
 137     PPC_PM_SLEEP,
 138     PPC_PM_RVWINKLE,
 139 } powerpc_pm_insn_t;
 140
 141 /*****************************************************************************/
 142 /* Input pins model                                                          */
 143 typedef enum powerpc_input_t powerpc_input_t;
 144 enum powerpc_input_t {
 145     PPC_FLAGS_INPUT_UNKNOWN = 0,
 146     /* PowerPC 6xx bus                  */
 147     PPC_FLAGS_INPUT_6xx,
 148     /* BookE bus                        */
 149     PPC_FLAGS_INPUT_BookE,
 150     /* PowerPC 405 bus                  */
 151     PPC_FLAGS_INPUT_405,
 152     /* PowerPC 970 bus                  */
 153     PPC_FLAGS_INPUT_970,
 154     /* PowerPC POWER7 bus               */
 155     PPC_FLAGS_INPUT_POWER7,
 156     /* PowerPC 401 bus                  */
 157     PPC_FLAGS_INPUT_401,
 158     /* Freescale RCPU bus               */
 159     PPC_FLAGS_INPUT_RCPU,
 160 };
 161
 162 struct ppc_segment_page_sizes;
 163
 164 /**
 165  * PowerPCCPUClass:
 166  * @parent_realize: The parent class' realize handler.
 167  * @parent_reset: The parent class' reset handler.
 168  *
 169  * A PowerPC CPU model.
 170  */
 171 typedef struct PowerPCCPUClass {
 172     /*< private >*/
 173     CPUClass parent_class;
 174     /*< public >*/
 175
 176     DeviceRealize parent_realize;
 177     void (*parent_reset)(CPUState *cpu);
 178
 179     uint32_t pvr;
 180     bool (*pvr_match)(struct PowerPCCPUClass *pcc, uint32_t pvr);
 181     uint64_t pcr_mask;          /* Available bits in PCR register */
 182     uint64_t pcr_supported;     /* Bits for supported PowerISA versions */
 183     uint32_t svr;
 184     uint64_t insns_flags;
 185     uint64_t insns_flags2;
 186     uint64_t msr_mask;
 187     powerpc_mmu_t   mmu_model;
 188     powerpc_excp_t  excp_model;
 189     powerpc_input_t bus_model;
 190     uint32_t flags;
 191     int bfd_mach;
 192     uint32_t l1_dcache_size, l1_icache_size;
 193     const struct ppc_segment_page_sizes *sps;
 194     void (*init_proc)(CPUPPCState *env);
 195     int  (*check_pow)(CPUPPCState *env);
 196     int (*handle_mmu_fault)(PowerPCCPU *cpu, vaddr eaddr, int rwx, int mmu_idx);
 197     bool (*interrupts_big_endian)(PowerPCCPU *cpu);
 198 } PowerPCCPUClass;
 199
 200 #ifndef CONFIG_USER_ONLY
 201 typedef struct PPCTimebase {
 202     uint64_t guest_timebase;
 203     int64_t time_of_the_day_ns;
 204 } PPCTimebase;
 205
 206 extern const struct VMStateDescription vmstate_ppc_timebase;
 207
 208 #define VMSTATE_PPC_TIMEBASE_V(_field, _state, _version) {            \
 209     .name       = (stringify(_field)),                                \
 210     .version_id = (_version),                                         \
 211     .size       = sizeof(PPCTimebase),                                \
 212     .vmsd       = &vmstate_ppc_timebase,                              \
 213     .flags      = VMS_STRUCT,                                         \
 214     .offset     = vmstate_offset_value(_state, _field, PPCTimebase),  \
 215 }
 216 #endif
 217
 218 #endif