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Introduce VCPU self-signaling service
[qemu.git] / hw / usb-musb.c
blob782cfa22821f65b2635018658584ac04a0c18972
1 /*
2 * "Inventra" High-speed Dual-Role Controller (MUSB-HDRC), Mentor Graphics,
3 * USB2.0 OTG compliant core used in various chips.
4 *
5 * Copyright (C) 2008 Nokia Corporation
6 * Written by Andrzej Zaborowski <andrew@openedhand.com>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 or
11 * (at your option) version 3 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, see <http://www.gnu.org/licenses/>.
20 *
21 * Only host-mode and non-DMA accesses are currently supported.
22 */
23 #include "qemu-common.h"
24 #include "qemu-timer.h"
25 #include "usb.h"
26 #include "irq.h"
27 #include "hw.h"
28
29 /* Common USB registers */
30 #define MUSB_HDRC_FADDR 0x00 /* 8-bit */
31 #define MUSB_HDRC_POWER 0x01 /* 8-bit */
32
33 #define MUSB_HDRC_INTRTX 0x02 /* 16-bit */
34 #define MUSB_HDRC_INTRRX 0x04
35 #define MUSB_HDRC_INTRTXE 0x06
36 #define MUSB_HDRC_INTRRXE 0x08
37 #define MUSB_HDRC_INTRUSB 0x0a /* 8 bit */
38 #define MUSB_HDRC_INTRUSBE 0x0b /* 8 bit */
39 #define MUSB_HDRC_FRAME 0x0c /* 16-bit */
40 #define MUSB_HDRC_INDEX 0x0e /* 8 bit */
41 #define MUSB_HDRC_TESTMODE 0x0f /* 8 bit */
42
43 /* Per-EP registers in indexed mode */
44 #define MUSB_HDRC_EP_IDX 0x10 /* 8-bit */
45
46 /* EP FIFOs */
47 #define MUSB_HDRC_FIFO 0x20
48
49 /* Additional Control Registers */
50 #define MUSB_HDRC_DEVCTL 0x60 /* 8 bit */
51
52 /* These are indexed */
53 #define MUSB_HDRC_TXFIFOSZ 0x62 /* 8 bit (see masks) */
54 #define MUSB_HDRC_RXFIFOSZ 0x63 /* 8 bit (see masks) */
55 #define MUSB_HDRC_TXFIFOADDR 0x64 /* 16 bit offset shifted right 3 */
56 #define MUSB_HDRC_RXFIFOADDR 0x66 /* 16 bit offset shifted right 3 */
57
58 /* Some more registers */
59 #define MUSB_HDRC_VCTRL 0x68 /* 8 bit */
60 #define MUSB_HDRC_HWVERS 0x6c /* 8 bit */
61
62 /* Added in HDRC 1.9(?) & MHDRC 1.4 */
63 /* ULPI pass-through */
64 #define MUSB_HDRC_ULPI_VBUSCTL 0x70
65 #define MUSB_HDRC_ULPI_REGDATA 0x74
66 #define MUSB_HDRC_ULPI_REGADDR 0x75
67 #define MUSB_HDRC_ULPI_REGCTL 0x76
68
69 /* Extended config & PHY control */
70 #define MUSB_HDRC_ENDCOUNT 0x78 /* 8 bit */
71 #define MUSB_HDRC_DMARAMCFG 0x79 /* 8 bit */
72 #define MUSB_HDRC_PHYWAIT 0x7a /* 8 bit */
73 #define MUSB_HDRC_PHYVPLEN 0x7b /* 8 bit */
74 #define MUSB_HDRC_HS_EOF1 0x7c /* 8 bit, units of 546.1 us */
75 #define MUSB_HDRC_FS_EOF1 0x7d /* 8 bit, units of 533.3 ns */
76 #define MUSB_HDRC_LS_EOF1 0x7e /* 8 bit, units of 1.067 us */
77
78 /* Per-EP BUSCTL registers */
79 #define MUSB_HDRC_BUSCTL 0x80
80
81 /* Per-EP registers in flat mode */
82 #define MUSB_HDRC_EP 0x100
83
84 /* offsets to registers in flat model */
85 #define MUSB_HDRC_TXMAXP 0x00 /* 16 bit apparently */
86 #define MUSB_HDRC_TXCSR 0x02 /* 16 bit apparently */
87 #define MUSB_HDRC_CSR0 MUSB_HDRC_TXCSR /* re-used for EP0 */
88 #define MUSB_HDRC_RXMAXP 0x04 /* 16 bit apparently */
89 #define MUSB_HDRC_RXCSR 0x06 /* 16 bit apparently */
90 #define MUSB_HDRC_RXCOUNT 0x08 /* 16 bit apparently */
91 #define MUSB_HDRC_COUNT0 MUSB_HDRC_RXCOUNT /* re-used for EP0 */
92 #define MUSB_HDRC_TXTYPE 0x0a /* 8 bit apparently */
93 #define MUSB_HDRC_TYPE0 MUSB_HDRC_TXTYPE /* re-used for EP0 */
94 #define MUSB_HDRC_TXINTERVAL 0x0b /* 8 bit apparently */
95 #define MUSB_HDRC_NAKLIMIT0 MUSB_HDRC_TXINTERVAL /* re-used for EP0 */
96 #define MUSB_HDRC_RXTYPE 0x0c /* 8 bit apparently */
97 #define MUSB_HDRC_RXINTERVAL 0x0d /* 8 bit apparently */
98 #define MUSB_HDRC_FIFOSIZE 0x0f /* 8 bit apparently */
99 #define MUSB_HDRC_CONFIGDATA MGC_O_HDRC_FIFOSIZE /* re-used for EP0 */
100
101 /* "Bus control" registers */
102 #define MUSB_HDRC_TXFUNCADDR 0x00
103 #define MUSB_HDRC_TXHUBADDR 0x02
104 #define MUSB_HDRC_TXHUBPORT 0x03
105
106 #define MUSB_HDRC_RXFUNCADDR 0x04
107 #define MUSB_HDRC_RXHUBADDR 0x06
108 #define MUSB_HDRC_RXHUBPORT 0x07
109
110 /*
111 * MUSBHDRC Register bit masks
112 */
113
114 /* POWER */
115 #define MGC_M_POWER_ISOUPDATE 0x80
116 #define MGC_M_POWER_SOFTCONN 0x40
117 #define MGC_M_POWER_HSENAB 0x20
118 #define MGC_M_POWER_HSMODE 0x10
119 #define MGC_M_POWER_RESET 0x08
120 #define MGC_M_POWER_RESUME 0x04
121 #define MGC_M_POWER_SUSPENDM 0x02
122 #define MGC_M_POWER_ENSUSPEND 0x01
123
124 /* INTRUSB */
125 #define MGC_M_INTR_SUSPEND 0x01
126 #define MGC_M_INTR_RESUME 0x02
127 #define MGC_M_INTR_RESET 0x04
128 #define MGC_M_INTR_BABBLE 0x04
129 #define MGC_M_INTR_SOF 0x08
130 #define MGC_M_INTR_CONNECT 0x10
131 #define MGC_M_INTR_DISCONNECT 0x20
132 #define MGC_M_INTR_SESSREQ 0x40
133 #define MGC_M_INTR_VBUSERROR 0x80 /* FOR SESSION END */
134 #define MGC_M_INTR_EP0 0x01 /* FOR EP0 INTERRUPT */
135
136 /* DEVCTL */
137 #define MGC_M_DEVCTL_BDEVICE 0x80
138 #define MGC_M_DEVCTL_FSDEV 0x40
139 #define MGC_M_DEVCTL_LSDEV 0x20
140 #define MGC_M_DEVCTL_VBUS 0x18
141 #define MGC_S_DEVCTL_VBUS 3
142 #define MGC_M_DEVCTL_HM 0x04
143 #define MGC_M_DEVCTL_HR 0x02
144 #define MGC_M_DEVCTL_SESSION 0x01
145
146 /* TESTMODE */
147 #define MGC_M_TEST_FORCE_HOST 0x80
148 #define MGC_M_TEST_FIFO_ACCESS 0x40
149 #define MGC_M_TEST_FORCE_FS 0x20
150 #define MGC_M_TEST_FORCE_HS 0x10
151 #define MGC_M_TEST_PACKET 0x08
152 #define MGC_M_TEST_K 0x04
153 #define MGC_M_TEST_J 0x02
154 #define MGC_M_TEST_SE0_NAK 0x01
155
156 /* CSR0 */
157 #define MGC_M_CSR0_FLUSHFIFO 0x0100
158 #define MGC_M_CSR0_TXPKTRDY 0x0002
159 #define MGC_M_CSR0_RXPKTRDY 0x0001
160
161 /* CSR0 in Peripheral mode */
162 #define MGC_M_CSR0_P_SVDSETUPEND 0x0080
163 #define MGC_M_CSR0_P_SVDRXPKTRDY 0x0040
164 #define MGC_M_CSR0_P_SENDSTALL 0x0020
165 #define MGC_M_CSR0_P_SETUPEND 0x0010
166 #define MGC_M_CSR0_P_DATAEND 0x0008
167 #define MGC_M_CSR0_P_SENTSTALL 0x0004
168
169 /* CSR0 in Host mode */
170 #define MGC_M_CSR0_H_NO_PING 0x0800
171 #define MGC_M_CSR0_H_WR_DATATOGGLE 0x0400 /* set to allow setting: */
172 #define MGC_M_CSR0_H_DATATOGGLE 0x0200 /* data toggle control */
173 #define MGC_M_CSR0_H_NAKTIMEOUT 0x0080
174 #define MGC_M_CSR0_H_STATUSPKT 0x0040
175 #define MGC_M_CSR0_H_REQPKT 0x0020
176 #define MGC_M_CSR0_H_ERROR 0x0010
177 #define MGC_M_CSR0_H_SETUPPKT 0x0008
178 #define MGC_M_CSR0_H_RXSTALL 0x0004
179
180 /* CONFIGDATA */
181 #define MGC_M_CONFIGDATA_MPRXE 0x80 /* auto bulk pkt combining */
182 #define MGC_M_CONFIGDATA_MPTXE 0x40 /* auto bulk pkt splitting */
183 #define MGC_M_CONFIGDATA_BIGENDIAN 0x20
184 #define MGC_M_CONFIGDATA_HBRXE 0x10 /* HB-ISO for RX */
185 #define MGC_M_CONFIGDATA_HBTXE 0x08 /* HB-ISO for TX */
186 #define MGC_M_CONFIGDATA_DYNFIFO 0x04 /* dynamic FIFO sizing */
187 #define MGC_M_CONFIGDATA_SOFTCONE 0x02 /* SoftConnect */
188 #define MGC_M_CONFIGDATA_UTMIDW 0x01 /* Width, 0 => 8b, 1 => 16b */
189
190 /* TXCSR in Peripheral and Host mode */
191 #define MGC_M_TXCSR_AUTOSET 0x8000
192 #define MGC_M_TXCSR_ISO 0x4000
193 #define MGC_M_TXCSR_MODE 0x2000
194 #define MGC_M_TXCSR_DMAENAB 0x1000
195 #define MGC_M_TXCSR_FRCDATATOG 0x0800
196 #define MGC_M_TXCSR_DMAMODE 0x0400
197 #define MGC_M_TXCSR_CLRDATATOG 0x0040
198 #define MGC_M_TXCSR_FLUSHFIFO 0x0008
199 #define MGC_M_TXCSR_FIFONOTEMPTY 0x0002
200 #define MGC_M_TXCSR_TXPKTRDY 0x0001
201
202 /* TXCSR in Peripheral mode */
203 #define MGC_M_TXCSR_P_INCOMPTX 0x0080
204 #define MGC_M_TXCSR_P_SENTSTALL 0x0020
205 #define MGC_M_TXCSR_P_SENDSTALL 0x0010
206 #define MGC_M_TXCSR_P_UNDERRUN 0x0004
207
208 /* TXCSR in Host mode */
209 #define MGC_M_TXCSR_H_WR_DATATOGGLE 0x0200
210 #define MGC_M_TXCSR_H_DATATOGGLE 0x0100
211 #define MGC_M_TXCSR_H_NAKTIMEOUT 0x0080
212 #define MGC_M_TXCSR_H_RXSTALL 0x0020
213 #define MGC_M_TXCSR_H_ERROR 0x0004
214
215 /* RXCSR in Peripheral and Host mode */
216 #define MGC_M_RXCSR_AUTOCLEAR 0x8000
217 #define MGC_M_RXCSR_DMAENAB 0x2000
218 #define MGC_M_RXCSR_DISNYET 0x1000
219 #define MGC_M_RXCSR_DMAMODE 0x0800
220 #define MGC_M_RXCSR_INCOMPRX 0x0100
221 #define MGC_M_RXCSR_CLRDATATOG 0x0080
222 #define MGC_M_RXCSR_FLUSHFIFO 0x0010
223 #define MGC_M_RXCSR_DATAERROR 0x0008
224 #define MGC_M_RXCSR_FIFOFULL 0x0002
225 #define MGC_M_RXCSR_RXPKTRDY 0x0001
226
227 /* RXCSR in Peripheral mode */
228 #define MGC_M_RXCSR_P_ISO 0x4000
229 #define MGC_M_RXCSR_P_SENTSTALL 0x0040
230 #define MGC_M_RXCSR_P_SENDSTALL 0x0020
231 #define MGC_M_RXCSR_P_OVERRUN 0x0004
232
233 /* RXCSR in Host mode */
234 #define MGC_M_RXCSR_H_AUTOREQ 0x4000
235 #define MGC_M_RXCSR_H_WR_DATATOGGLE 0x0400
236 #define MGC_M_RXCSR_H_DATATOGGLE 0x0200
237 #define MGC_M_RXCSR_H_RXSTALL 0x0040
238 #define MGC_M_RXCSR_H_REQPKT 0x0020
239 #define MGC_M_RXCSR_H_ERROR 0x0004
240
241 /* HUBADDR */
242 #define MGC_M_HUBADDR_MULTI_TT 0x80
243
244 /* ULPI: Added in HDRC 1.9(?) & MHDRC 1.4 */
245 #define MGC_M_ULPI_VBCTL_USEEXTVBUSIND 0x02
246 #define MGC_M_ULPI_VBCTL_USEEXTVBUS 0x01
247 #define MGC_M_ULPI_REGCTL_INT_ENABLE 0x08
248 #define MGC_M_ULPI_REGCTL_READNOTWRITE 0x04
249 #define MGC_M_ULPI_REGCTL_COMPLETE 0x02
250 #define MGC_M_ULPI_REGCTL_REG 0x01
251
252 /* #define MUSB_DEBUG */
253
254 #ifdef MUSB_DEBUG
255 #define TRACE(fmt,...) fprintf(stderr, "%s@%d: " fmt "\n", __FUNCTION__, \
256 __LINE__, ##__VA_ARGS__)
257 #else
258 #define TRACE(...)
259 #endif
260
261
262 static void musb_attach(USBPort *port);
263 static void musb_detach(USBPort *port);
264
265 static USBPortOps musb_port_ops = {
266 .attach = musb_attach,
267 .detach = musb_detach,
268 };
269
270 typedef struct {
271 uint16_t faddr[2];
272 uint8_t haddr[2];
273 uint8_t hport[2];
274 uint16_t csr[2];
275 uint16_t maxp[2];
276 uint16_t rxcount;
277 uint8_t type[2];
278 uint8_t interval[2];
279 uint8_t config;
280 uint8_t fifosize;
281 int timeout[2]; /* Always in microframes */
282
283 uint8_t *buf[2];
284 int fifolen[2];
285 int fifostart[2];
286 int fifoaddr[2];
287 USBPacket packey[2];
288 int status[2];
289 int ext_size[2];
290
291 /* For callbacks' use */
292 int epnum;
293 int interrupt[2];
294 MUSBState *musb;
295 USBCallback *delayed_cb[2];
296 QEMUTimer *intv_timer[2];
297 } MUSBEndPoint;
298
299 struct MUSBState {
300 qemu_irq *irqs;
301 USBBus bus;
302 USBPort port;
303
304 int idx;
305 uint8_t devctl;
306 uint8_t power;
307 uint8_t faddr;
308
309 uint8_t intr;
310 uint8_t mask;
311 uint16_t tx_intr;
312 uint16_t tx_mask;
313 uint16_t rx_intr;
314 uint16_t rx_mask;
315
316 int setup_len;
317 int session;
318
319 uint8_t buf[0x8000];
320
321 /* Duplicating the world since 2008!... probably we should have 32
322 * logical, single endpoints instead. */
323 MUSBEndPoint ep[16];
324 } *musb_init(qemu_irq *irqs)
325 {
326 MUSBState *s = qemu_mallocz(sizeof(*s));
327 int i;
328
329 s->irqs = irqs;
330
331 s->faddr = 0x00;
332 s->power = MGC_M_POWER_HSENAB;
333 s->tx_intr = 0x0000;
334 s->rx_intr = 0x0000;
335 s->tx_mask = 0xffff;
336 s->rx_mask = 0xffff;
337 s->intr = 0x00;
338 s->mask = 0x06;
339 s->idx = 0;
340
341 /* TODO: _DW */
342 s->ep[0].config = MGC_M_CONFIGDATA_SOFTCONE | MGC_M_CONFIGDATA_DYNFIFO;
343 for (i = 0; i < 16; i ++) {
344 s->ep[i].fifosize = 64;
345 s->ep[i].maxp[0] = 0x40;
346 s->ep[i].maxp[1] = 0x40;
347 s->ep[i].musb = s;
348 s->ep[i].epnum = i;
349 }
350
351 usb_bus_new(&s->bus, NULL /* FIXME */);
352 usb_register_port(&s->bus, &s->port, s, 0, &musb_port_ops,
353 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL);
354 usb_port_location(&s->port, NULL, 1);
355
356 return s;
357 }
358
359 static void musb_vbus_set(MUSBState *s, int level)
360 {
361 if (level)
362 s->devctl |= 3 << MGC_S_DEVCTL_VBUS;
363 else
364 s->devctl &= ~MGC_M_DEVCTL_VBUS;
365
366 qemu_set_irq(s->irqs[musb_set_vbus], level);
367 }
368
369 static void musb_intr_set(MUSBState *s, int line, int level)
370 {
371 if (!level) {
372 s->intr &= ~(1 << line);
373 qemu_irq_lower(s->irqs[line]);
374 } else if (s->mask & (1 << line)) {
375 s->intr |= 1 << line;
376 qemu_irq_raise(s->irqs[line]);
377 }
378 }
379
380 static void musb_tx_intr_set(MUSBState *s, int line, int level)
381 {
382 if (!level) {
383 s->tx_intr &= ~(1 << line);
384 if (!s->tx_intr)
385 qemu_irq_lower(s->irqs[musb_irq_tx]);
386 } else if (s->tx_mask & (1 << line)) {
387 s->tx_intr |= 1 << line;
388 qemu_irq_raise(s->irqs[musb_irq_tx]);
389 }
390 }
391
392 static void musb_rx_intr_set(MUSBState *s, int line, int level)
393 {
394 if (line) {
395 if (!level) {
396 s->rx_intr &= ~(1 << line);
397 if (!s->rx_intr)
398 qemu_irq_lower(s->irqs[musb_irq_rx]);
399 } else if (s->rx_mask & (1 << line)) {
400 s->rx_intr |= 1 << line;
401 qemu_irq_raise(s->irqs[musb_irq_rx]);
402 }
403 } else
404 musb_tx_intr_set(s, line, level);
405 }
406
407 uint32_t musb_core_intr_get(MUSBState *s)
408 {
409 return (s->rx_intr << 15) | s->tx_intr;
410 }
411
412 void musb_core_intr_clear(MUSBState *s, uint32_t mask)
413 {
414 if (s->rx_intr) {
415 s->rx_intr &= mask >> 15;
416 if (!s->rx_intr)
417 qemu_irq_lower(s->irqs[musb_irq_rx]);
418 }
419
420 if (s->tx_intr) {
421 s->tx_intr &= mask & 0xffff;
422 if (!s->tx_intr)
423 qemu_irq_lower(s->irqs[musb_irq_tx]);
424 }
425 }
426
427 void musb_set_size(MUSBState *s, int epnum, int size, int is_tx)
428 {
429 s->ep[epnum].ext_size[!is_tx] = size;
430 s->ep[epnum].fifostart[0] = 0;
431 s->ep[epnum].fifostart[1] = 0;
432 s->ep[epnum].fifolen[0] = 0;
433 s->ep[epnum].fifolen[1] = 0;
434 }
435
436 static void musb_session_update(MUSBState *s, int prev_dev, int prev_sess)
437 {
438 int detect_prev = prev_dev && prev_sess;
439 int detect = !!s->port.dev && s->session;
440
441 if (detect && !detect_prev) {
442 /* Let's skip the ID pin sense and VBUS sense formalities and
443 * and signal a successful SRP directly. This should work at least
444 * for the Linux driver stack. */
445 musb_intr_set(s, musb_irq_connect, 1);
446
447 if (s->port.dev->speed == USB_SPEED_LOW) {
448 s->devctl &= ~MGC_M_DEVCTL_FSDEV;
449 s->devctl |= MGC_M_DEVCTL_LSDEV;
450 } else {
451 s->devctl |= MGC_M_DEVCTL_FSDEV;
452 s->devctl &= ~MGC_M_DEVCTL_LSDEV;
453 }
454
455 /* A-mode? */
456 s->devctl &= ~MGC_M_DEVCTL_BDEVICE;
457
458 /* Host-mode bit? */
459 s->devctl |= MGC_M_DEVCTL_HM;
460 #if 1
461 musb_vbus_set(s, 1);
462 #endif
463 } else if (!detect && detect_prev) {
464 #if 1
465 musb_vbus_set(s, 0);
466 #endif
467 }
468 }
469
470 /* Attach or detach a device on our only port. */
471 static void musb_attach(USBPort *port)
472 {
473 MUSBState *s = (MUSBState *) port->opaque;
474
475 musb_intr_set(s, musb_irq_vbus_request, 1);
476 musb_session_update(s, 0, s->session);
477 }
478
479 static void musb_detach(USBPort *port)
480 {
481 MUSBState *s = (MUSBState *) port->opaque;
482
483 musb_intr_set(s, musb_irq_disconnect, 1);
484 musb_session_update(s, 1, s->session);
485 }
486
487 static inline void musb_cb_tick0(void *opaque)
488 {
489 MUSBEndPoint *ep = (MUSBEndPoint *) opaque;
490
491 ep->delayed_cb[0](&ep->packey[0], opaque);
492 }
493
494 static inline void musb_cb_tick1(void *opaque)
495 {
496 MUSBEndPoint *ep = (MUSBEndPoint *) opaque;
497
498 ep->delayed_cb[1](&ep->packey[1], opaque);
499 }
500
501 #define musb_cb_tick (dir ? musb_cb_tick1 : musb_cb_tick0)
502
503 static inline void musb_schedule_cb(USBPacket *packey, void *opaque, int dir)
504 {
505 MUSBEndPoint *ep = (MUSBEndPoint *) opaque;
506 int timeout = 0;
507
508 if (ep->status[dir] == USB_RET_NAK)
509 timeout = ep->timeout[dir];
510 else if (ep->interrupt[dir])
511 timeout = 8;
512 else
513 return musb_cb_tick(opaque);
514
515 if (!ep->intv_timer[dir])
516 ep->intv_timer[dir] = qemu_new_timer(vm_clock, musb_cb_tick, opaque);
517
518 qemu_mod_timer(ep->intv_timer[dir], qemu_get_clock(vm_clock) +
519 muldiv64(timeout, get_ticks_per_sec(), 8000));
520 }
521
522 static void musb_schedule0_cb(USBPacket *packey, void *opaque)
523 {
524 return musb_schedule_cb(packey, opaque, 0);
525 }
526
527 static void musb_schedule1_cb(USBPacket *packey, void *opaque)
528 {
529 return musb_schedule_cb(packey, opaque, 1);
530 }
531
532 static int musb_timeout(int ttype, int speed, int val)
533 {
534 #if 1
535 return val << 3;
536 #endif
537
538 switch (ttype) {
539 case USB_ENDPOINT_XFER_CONTROL:
540 if (val < 2)
541 return 0;
542 else if (speed == USB_SPEED_HIGH)
543 return 1 << (val - 1);
544 else
545 return 8 << (val - 1);
546
547 case USB_ENDPOINT_XFER_INT:
548 if (speed == USB_SPEED_HIGH)
549 if (val < 2)
550 return 0;
551 else
552 return 1 << (val - 1);
553 else
554 return val << 3;
555
556 case USB_ENDPOINT_XFER_BULK:
557 case USB_ENDPOINT_XFER_ISOC:
558 if (val < 2)
559 return 0;
560 else if (speed == USB_SPEED_HIGH)
561 return 1 << (val - 1);
562 else
563 return 8 << (val - 1);
564 /* TODO: what with low-speed Bulk and Isochronous? */
565 }
566
567 hw_error("bad interval\n");
568 }
569
570 static inline void musb_packet(MUSBState *s, MUSBEndPoint *ep,
571 int epnum, int pid, int len, USBCallback cb, int dir)
572 {
573 int ret;
574 int idx = epnum && dir;
575 int ttype;
576
577 /* ep->type[0,1] contains:
578 * in bits 7:6 the speed (0 - invalid, 1 - high, 2 - full, 3 - slow)
579 * in bits 5:4 the transfer type (BULK / INT)
580 * in bits 3:0 the EP num
581 */
582 ttype = epnum ? (ep->type[idx] >> 4) & 3 : 0;
583
584 ep->timeout[dir] = musb_timeout(ttype,
585 ep->type[idx] >> 6, ep->interval[idx]);
586 ep->interrupt[dir] = ttype == USB_ENDPOINT_XFER_INT;
587 ep->delayed_cb[dir] = cb;
588 cb = dir ? musb_schedule1_cb : musb_schedule0_cb;
589
590 ep->packey[dir].pid = pid;
591 /* A wild guess on the FADDR semantics... */
592 ep->packey[dir].devaddr = ep->faddr[idx];
593 ep->packey[dir].devep = ep->type[idx] & 0xf;
594 ep->packey[dir].data = (void *) ep->buf[idx];
595 ep->packey[dir].len = len;
596 ep->packey[dir].complete_cb = cb;
597 ep->packey[dir].complete_opaque = ep;
598
599 if (s->port.dev)
600 ret = s->port.dev->info->handle_packet(s->port.dev, &ep->packey[dir]);
601 else
602 ret = USB_RET_NODEV;
603
604 if (ret == USB_RET_ASYNC) {
605 ep->status[dir] = len;
606 return;
607 }
608
609 ep->status[dir] = ret;
610 usb_packet_complete(&ep->packey[dir]);
611 }
612
613 static void musb_tx_packet_complete(USBPacket *packey, void *opaque)
614 {
615 /* Unfortunately we can't use packey->devep because that's the remote
616 * endpoint number and may be different than our local. */
617 MUSBEndPoint *ep = (MUSBEndPoint *) opaque;
618 int epnum = ep->epnum;
619 MUSBState *s = ep->musb;
620
621 ep->fifostart[0] = 0;
622 ep->fifolen[0] = 0;
623 #ifdef CLEAR_NAK
624 if (ep->status[0] != USB_RET_NAK) {
625 #endif
626 if (epnum)
627 ep->csr[0] &= ~(MGC_M_TXCSR_FIFONOTEMPTY | MGC_M_TXCSR_TXPKTRDY);
628 else
629 ep->csr[0] &= ~MGC_M_CSR0_TXPKTRDY;
630 #ifdef CLEAR_NAK
631 }
632 #endif
633
634 /* Clear all of the error bits first */
635 if (epnum)
636 ep->csr[0] &= ~(MGC_M_TXCSR_H_ERROR | MGC_M_TXCSR_H_RXSTALL |
637 MGC_M_TXCSR_H_NAKTIMEOUT);
638 else
639 ep->csr[0] &= ~(MGC_M_CSR0_H_ERROR | MGC_M_CSR0_H_RXSTALL |
640 MGC_M_CSR0_H_NAKTIMEOUT | MGC_M_CSR0_H_NO_PING);
641
642 if (ep->status[0] == USB_RET_STALL) {
643 /* Command not supported by target! */
644 ep->status[0] = 0;
645
646 if (epnum)
647 ep->csr[0] |= MGC_M_TXCSR_H_RXSTALL;
648 else
649 ep->csr[0] |= MGC_M_CSR0_H_RXSTALL;
650 }
651
652 if (ep->status[0] == USB_RET_NAK) {
653 ep->status[0] = 0;
654
655 /* NAK timeouts are only generated in Bulk transfers and
656 * Data-errors in Isochronous. */
657 if (ep->interrupt[0]) {
658 return;
659 }
660
661 if (epnum)
662 ep->csr[0] |= MGC_M_TXCSR_H_NAKTIMEOUT;
663 else
664 ep->csr[0] |= MGC_M_CSR0_H_NAKTIMEOUT;
665 }
666
667 if (ep->status[0] < 0) {
668 if (ep->status[0] == USB_RET_BABBLE)
669 musb_intr_set(s, musb_irq_rst_babble, 1);
670
671 /* Pretend we've tried three times already and failed (in
672 * case of USB_TOKEN_SETUP). */
673 if (epnum)
674 ep->csr[0] |= MGC_M_TXCSR_H_ERROR;
675 else
676 ep->csr[0] |= MGC_M_CSR0_H_ERROR;
677
678 musb_tx_intr_set(s, epnum, 1);
679 return;
680 }
681 /* TODO: check len for over/underruns of an OUT packet? */
682
683 #ifdef SETUPLEN_HACK
684 if (!epnum && ep->packey[0].pid == USB_TOKEN_SETUP)
685 s->setup_len = ep->packey[0].data[6];
686 #endif
687
688 /* In DMA mode: if no error, assert DMA request for this EP,
689 * and skip the interrupt. */
690 musb_tx_intr_set(s, epnum, 1);
691 }
692
693 static void musb_rx_packet_complete(USBPacket *packey, void *opaque)
694 {
695 /* Unfortunately we can't use packey->devep because that's the remote
696 * endpoint number and may be different than our local. */
697 MUSBEndPoint *ep = (MUSBEndPoint *) opaque;
698 int epnum = ep->epnum;
699 MUSBState *s = ep->musb;
700
701 ep->fifostart[1] = 0;
702 ep->fifolen[1] = 0;
703
704 #ifdef CLEAR_NAK
705 if (ep->status[1] != USB_RET_NAK) {
706 #endif
707 ep->csr[1] &= ~MGC_M_RXCSR_H_REQPKT;
708 if (!epnum)
709 ep->csr[0] &= ~MGC_M_CSR0_H_REQPKT;
710 #ifdef CLEAR_NAK
711 }
712 #endif
713
714 /* Clear all of the imaginable error bits first */
715 ep->csr[1] &= ~(MGC_M_RXCSR_H_ERROR | MGC_M_RXCSR_H_RXSTALL |
716 MGC_M_RXCSR_DATAERROR);
717 if (!epnum)
718 ep->csr[0] &= ~(MGC_M_CSR0_H_ERROR | MGC_M_CSR0_H_RXSTALL |
719 MGC_M_CSR0_H_NAKTIMEOUT | MGC_M_CSR0_H_NO_PING);
720
721 if (ep->status[1] == USB_RET_STALL) {
722 ep->status[1] = 0;
723 packey->len = 0;
724
725 ep->csr[1] |= MGC_M_RXCSR_H_RXSTALL;
726 if (!epnum)
727 ep->csr[0] |= MGC_M_CSR0_H_RXSTALL;
728 }
729
730 if (ep->status[1] == USB_RET_NAK) {
731 ep->status[1] = 0;
732
733 /* NAK timeouts are only generated in Bulk transfers and
734 * Data-errors in Isochronous. */
735 if (ep->interrupt[1])
736 return musb_packet(s, ep, epnum, USB_TOKEN_IN,
737 packey->len, musb_rx_packet_complete, 1);
738
739 ep->csr[1] |= MGC_M_RXCSR_DATAERROR;
740 if (!epnum)
741 ep->csr[0] |= MGC_M_CSR0_H_NAKTIMEOUT;
742 }
743
744 if (ep->status[1] < 0) {
745 if (ep->status[1] == USB_RET_BABBLE) {
746 musb_intr_set(s, musb_irq_rst_babble, 1);
747 return;
748 }
749
750 /* Pretend we've tried three times already and failed (in
751 * case of a control transfer). */
752 ep->csr[1] |= MGC_M_RXCSR_H_ERROR;
753 if (!epnum)
754 ep->csr[0] |= MGC_M_CSR0_H_ERROR;
755
756 musb_rx_intr_set(s, epnum, 1);
757 return;
758 }
759 /* TODO: check len for over/underruns of an OUT packet? */
760 /* TODO: perhaps make use of e->ext_size[1] here. */
761
762 packey->len = ep->status[1];
763
764 if (!(ep->csr[1] & (MGC_M_RXCSR_H_RXSTALL | MGC_M_RXCSR_DATAERROR))) {
765 ep->csr[1] |= MGC_M_RXCSR_FIFOFULL | MGC_M_RXCSR_RXPKTRDY;
766 if (!epnum)
767 ep->csr[0] |= MGC_M_CSR0_RXPKTRDY;
768
769 ep->rxcount = packey->len; /* XXX: MIN(packey->len, ep->maxp[1]); */
770 /* In DMA mode: assert DMA request for this EP */
771 }
772
773 /* Only if DMA has not been asserted */
774 musb_rx_intr_set(s, epnum, 1);
775 }
776
777 static void musb_tx_rdy(MUSBState *s, int epnum)
778 {
779 MUSBEndPoint *ep = s->ep + epnum;
780 int pid;
781 int total, valid = 0;
782 TRACE("start %d, len %d", ep->fifostart[0], ep->fifolen[0] );
783 ep->fifostart[0] += ep->fifolen[0];
784 ep->fifolen[0] = 0;
785
786 /* XXX: how's the total size of the packet retrieved exactly in
787 * the generic case? */
788 total = ep->maxp[0] & 0x3ff;
789
790 if (ep->ext_size[0]) {
791 total = ep->ext_size[0];
792 ep->ext_size[0] = 0;
793 valid = 1;
794 }
795
796 /* If the packet is not fully ready yet, wait for a next segment. */
797 if (epnum && (ep->fifostart[0]) < total)
798 return;
799
800 if (!valid)
801 total = ep->fifostart[0];
802
803 pid = USB_TOKEN_OUT;
804 if (!epnum && (ep->csr[0] & MGC_M_CSR0_H_SETUPPKT)) {
805 pid = USB_TOKEN_SETUP;
806 if (total != 8) {
807 TRACE("illegal SETUPPKT length of %i bytes", total);
808 }
809 /* Controller should retry SETUP packets three times on errors
810 * but it doesn't make sense for us to do that. */
811 }
812
813 return musb_packet(s, ep, epnum, pid,
814 total, musb_tx_packet_complete, 0);
815 }
816
817 static void musb_rx_req(MUSBState *s, int epnum)
818 {
819 MUSBEndPoint *ep = s->ep + epnum;
820 int total;
821
822 /* If we already have a packet, which didn't fit into the
823 * 64 bytes of the FIFO, only move the FIFO start and return. (Obsolete) */
824 if (ep->packey[1].pid == USB_TOKEN_IN && ep->status[1] >= 0 &&
825 (ep->fifostart[1]) + ep->rxcount <
826 ep->packey[1].len) {
827 TRACE("0x%08x, %d", ep->fifostart[1], ep->rxcount );
828 ep->fifostart[1] += ep->rxcount;
829 ep->fifolen[1] = 0;
830
831 ep->rxcount = MIN(ep->packey[0].len - (ep->fifostart[1]),
832 ep->maxp[1]);
833
834 ep->csr[1] &= ~MGC_M_RXCSR_H_REQPKT;
835 if (!epnum)
836 ep->csr[0] &= ~MGC_M_CSR0_H_REQPKT;
837
838 /* Clear all of the error bits first */
839 ep->csr[1] &= ~(MGC_M_RXCSR_H_ERROR | MGC_M_RXCSR_H_RXSTALL |
840 MGC_M_RXCSR_DATAERROR);
841 if (!epnum)
842 ep->csr[0] &= ~(MGC_M_CSR0_H_ERROR | MGC_M_CSR0_H_RXSTALL |
843 MGC_M_CSR0_H_NAKTIMEOUT | MGC_M_CSR0_H_NO_PING);
844
845 ep->csr[1] |= MGC_M_RXCSR_FIFOFULL | MGC_M_RXCSR_RXPKTRDY;
846 if (!epnum)
847 ep->csr[0] |= MGC_M_CSR0_RXPKTRDY;
848 musb_rx_intr_set(s, epnum, 1);
849 return;
850 }
851
852 /* The driver sets maxp[1] to 64 or less because it knows the hardware
853 * FIFO is this deep. Bigger packets get split in
854 * usb_generic_handle_packet but we can also do the splitting locally
855 * for performance. It turns out we can also have a bigger FIFO and
856 * ignore the limit set in ep->maxp[1]. The Linux MUSB driver deals
857 * OK with single packets of even 32KB and we avoid splitting, however
858 * usb_msd.c sometimes sends a packet bigger than what Linux expects
859 * (e.g. 8192 bytes instead of 4096) and we get an OVERRUN. Splitting
860 * hides this overrun from Linux. Up to 4096 everything is fine
861 * though. Currently this is disabled.
862 *
863 * XXX: mind ep->fifosize. */
864 total = MIN(ep->maxp[1] & 0x3ff, sizeof(s->buf));
865
866 #ifdef SETUPLEN_HACK
867 /* Why should *we* do that instead of Linux? */
868 if (!epnum) {
869 if (ep->packey[0].devaddr == 2)
870 total = MIN(s->setup_len, 8);
871 else
872 total = MIN(s->setup_len, 64);
873 s->setup_len -= total;
874 }
875 #endif
876
877 return musb_packet(s, ep, epnum, USB_TOKEN_IN,
878 total, musb_rx_packet_complete, 1);
879 }
880
881 static uint8_t musb_read_fifo(MUSBEndPoint *ep)
882 {
883 uint8_t value;
884 if (ep->fifolen[1] >= 64) {
885 /* We have a FIFO underrun */
886 TRACE("EP%d FIFO is now empty, stop reading", ep->epnum);
887 return 0x00000000;
888 }
889 /* In DMA mode clear RXPKTRDY and set REQPKT automatically
890 * (if AUTOREQ is set) */
891
892 ep->csr[1] &= ~MGC_M_RXCSR_FIFOFULL;
893 value=ep->buf[1][ep->fifostart[1] + ep->fifolen[1] ++];
894 TRACE("EP%d 0x%02x, %d", ep->epnum, value, ep->fifolen[1] );
895 return value;
896 }
897
898 static void musb_write_fifo(MUSBEndPoint *ep, uint8_t value)
899 {
900 TRACE("EP%d = %02x", ep->epnum, value);
901 if (ep->fifolen[0] >= 64) {
902 /* We have a FIFO overrun */
903 TRACE("EP%d FIFO exceeded 64 bytes, stop feeding data", ep->epnum);
904 return;
905 }
906
907 ep->buf[0][ep->fifostart[0] + ep->fifolen[0] ++] = value;
908 ep->csr[0] |= MGC_M_TXCSR_FIFONOTEMPTY;
909 }
910
911 static void musb_ep_frame_cancel(MUSBEndPoint *ep, int dir)
912 {
913 if (ep->intv_timer[dir])
914 qemu_del_timer(ep->intv_timer[dir]);
915 }
916
917 /* Bus control */
918 static uint8_t musb_busctl_readb(void *opaque, int ep, int addr)
919 {
920 MUSBState *s = (MUSBState *) opaque;
921
922 switch (addr) {
923 /* For USB2.0 HS hubs only */
924 case MUSB_HDRC_TXHUBADDR:
925 return s->ep[ep].haddr[0];
926 case MUSB_HDRC_TXHUBPORT:
927 return s->ep[ep].hport[0];
928 case MUSB_HDRC_RXHUBADDR:
929 return s->ep[ep].haddr[1];
930 case MUSB_HDRC_RXHUBPORT:
931 return s->ep[ep].hport[1];
932
933 default:
934 TRACE("unknown register 0x%02x", addr);
935 return 0x00;
936 };
937 }
938
939 static void musb_busctl_writeb(void *opaque, int ep, int addr, uint8_t value)
940 {
941 MUSBState *s = (MUSBState *) opaque;
942
943 switch (addr) {
944 case MUSB_HDRC_TXFUNCADDR:
945 s->ep[ep].faddr[0] = value;
946 break;
947 case MUSB_HDRC_RXFUNCADDR:
948 s->ep[ep].faddr[1] = value;
949 break;
950 case MUSB_HDRC_TXHUBADDR:
951 s->ep[ep].haddr[0] = value;
952 break;
953 case MUSB_HDRC_TXHUBPORT:
954 s->ep[ep].hport[0] = value;
955 break;
956 case MUSB_HDRC_RXHUBADDR:
957 s->ep[ep].haddr[1] = value;
958 break;
959 case MUSB_HDRC_RXHUBPORT:
960 s->ep[ep].hport[1] = value;
961 break;
962
963 default:
964 TRACE("unknown register 0x%02x", addr);
965 break;
966 };
967 }
968
969 static uint16_t musb_busctl_readh(void *opaque, int ep, int addr)
970 {
971 MUSBState *s = (MUSBState *) opaque;
972
973 switch (addr) {
974 case MUSB_HDRC_TXFUNCADDR:
975 return s->ep[ep].faddr[0];
976 case MUSB_HDRC_RXFUNCADDR:
977 return s->ep[ep].faddr[1];
978
979 default:
980 return musb_busctl_readb(s, ep, addr) |
981 (musb_busctl_readb(s, ep, addr | 1) << 8);
982 };
983 }
984
985 static void musb_busctl_writeh(void *opaque, int ep, int addr, uint16_t value)
986 {
987 MUSBState *s = (MUSBState *) opaque;
988
989 switch (addr) {
990 case MUSB_HDRC_TXFUNCADDR:
991 s->ep[ep].faddr[0] = value;
992 break;
993 case MUSB_HDRC_RXFUNCADDR:
994 s->ep[ep].faddr[1] = value;
995 break;
996
997 default:
998 musb_busctl_writeb(s, ep, addr, value & 0xff);
999 musb_busctl_writeb(s, ep, addr | 1, value >> 8);
1000 };
1001 }
1002
1003 /* Endpoint control */
1004 static uint8_t musb_ep_readb(void *opaque, int ep, int addr)
1005 {
1006 MUSBState *s = (MUSBState *) opaque;
1007
1008 switch (addr) {
1009 case MUSB_HDRC_TXTYPE:
1010 return s->ep[ep].type[0];
1011 case MUSB_HDRC_TXINTERVAL:
1012 return s->ep[ep].interval[0];
1013 case MUSB_HDRC_RXTYPE:
1014 return s->ep[ep].type[1];
1015 case MUSB_HDRC_RXINTERVAL:
1016 return s->ep[ep].interval[1];
1017 case (MUSB_HDRC_FIFOSIZE & ~1):
1018 return 0x00;
1019 case MUSB_HDRC_FIFOSIZE:
1020 return ep ? s->ep[ep].fifosize : s->ep[ep].config;
1021 case MUSB_HDRC_RXCOUNT:
1022 return s->ep[ep].rxcount;
1023
1024 default:
1025 TRACE("unknown register 0x%02x", addr);
1026 return 0x00;
1027 };
1028 }
1029
1030 static void musb_ep_writeb(void *opaque, int ep, int addr, uint8_t value)
1031 {
1032 MUSBState *s = (MUSBState *) opaque;
1033
1034 switch (addr) {
1035 case MUSB_HDRC_TXTYPE:
1036 s->ep[ep].type[0] = value;
1037 break;
1038 case MUSB_HDRC_TXINTERVAL:
1039 s->ep[ep].interval[0] = value;
1040 musb_ep_frame_cancel(&s->ep[ep], 0);
1041 break;
1042 case MUSB_HDRC_RXTYPE:
1043 s->ep[ep].type[1] = value;
1044 break;
1045 case MUSB_HDRC_RXINTERVAL:
1046 s->ep[ep].interval[1] = value;
1047 musb_ep_frame_cancel(&s->ep[ep], 1);
1048 break;
1049 case (MUSB_HDRC_FIFOSIZE & ~1):
1050 break;
1051 case MUSB_HDRC_FIFOSIZE:
1052 TRACE("somebody messes with fifosize (now %i bytes)", value);
1053 s->ep[ep].fifosize = value;
1054 break;
1055 default:
1056 TRACE("unknown register 0x%02x", addr);
1057 break;
1058 };
1059 }
1060
1061 static uint16_t musb_ep_readh(void *opaque, int ep, int addr)
1062 {
1063 MUSBState *s = (MUSBState *) opaque;
1064 uint16_t ret;
1065
1066 switch (addr) {
1067 case MUSB_HDRC_TXMAXP:
1068 return s->ep[ep].maxp[0];
1069 case MUSB_HDRC_TXCSR:
1070 return s->ep[ep].csr[0];
1071 case MUSB_HDRC_RXMAXP:
1072 return s->ep[ep].maxp[1];
1073 case MUSB_HDRC_RXCSR:
1074 ret = s->ep[ep].csr[1];
1075
1076 /* TODO: This and other bits probably depend on
1077 * ep->csr[1] & MGC_M_RXCSR_AUTOCLEAR. */
1078 if (s->ep[ep].csr[1] & MGC_M_RXCSR_AUTOCLEAR)
1079 s->ep[ep].csr[1] &= ~MGC_M_RXCSR_RXPKTRDY;
1080
1081 return ret;
1082 case MUSB_HDRC_RXCOUNT:
1083 return s->ep[ep].rxcount;
1084
1085 default:
1086 return musb_ep_readb(s, ep, addr) |
1087 (musb_ep_readb(s, ep, addr | 1) << 8);
1088 };
1089 }
1090
1091 static void musb_ep_writeh(void *opaque, int ep, int addr, uint16_t value)
1092 {
1093 MUSBState *s = (MUSBState *) opaque;
1094
1095 switch (addr) {
1096 case MUSB_HDRC_TXMAXP:
1097 s->ep[ep].maxp[0] = value;
1098 break;
1099 case MUSB_HDRC_TXCSR:
1100 if (ep) {
1101 s->ep[ep].csr[0] &= value & 0xa6;
1102 s->ep[ep].csr[0] |= value & 0xff59;
1103 } else {
1104 s->ep[ep].csr[0] &= value & 0x85;
1105 s->ep[ep].csr[0] |= value & 0xf7a;
1106 }
1107
1108 musb_ep_frame_cancel(&s->ep[ep], 0);
1109
1110 if ((ep && (value & MGC_M_TXCSR_FLUSHFIFO)) ||
1111 (!ep && (value & MGC_M_CSR0_FLUSHFIFO))) {
1112 s->ep[ep].fifolen[0] = 0;
1113 s->ep[ep].fifostart[0] = 0;
1114 if (ep)
1115 s->ep[ep].csr[0] &=
1116 ~(MGC_M_TXCSR_FIFONOTEMPTY | MGC_M_TXCSR_TXPKTRDY);
1117 else
1118 s->ep[ep].csr[0] &=
1119 ~(MGC_M_CSR0_TXPKTRDY | MGC_M_CSR0_RXPKTRDY);
1120 }
1121 if (
1122 (ep &&
1123 #ifdef CLEAR_NAK
1124 (value & MGC_M_TXCSR_TXPKTRDY) &&
1125 !(value & MGC_M_TXCSR_H_NAKTIMEOUT)) ||
1126 #else
1127 (value & MGC_M_TXCSR_TXPKTRDY)) ||
1128 #endif
1129 (!ep &&
1130 #ifdef CLEAR_NAK
1131 (value & MGC_M_CSR0_TXPKTRDY) &&
1132 !(value & MGC_M_CSR0_H_NAKTIMEOUT)))
1133 #else
1134 (value & MGC_M_CSR0_TXPKTRDY)))
1135 #endif
1136 musb_tx_rdy(s, ep);
1137 if (!ep &&
1138 (value & MGC_M_CSR0_H_REQPKT) &&
1139 #ifdef CLEAR_NAK
1140 !(value & (MGC_M_CSR0_H_NAKTIMEOUT |
1141 MGC_M_CSR0_RXPKTRDY)))
1142 #else
1143 !(value & MGC_M_CSR0_RXPKTRDY))
1144 #endif
1145 musb_rx_req(s, ep);
1146 break;
1147
1148 case MUSB_HDRC_RXMAXP:
1149 s->ep[ep].maxp[1] = value;
1150 break;
1151 case MUSB_HDRC_RXCSR:
1152 /* (DMA mode only) */
1153 if (
1154 (value & MGC_M_RXCSR_H_AUTOREQ) &&
1155 !(value & MGC_M_RXCSR_RXPKTRDY) &&
1156 (s->ep[ep].csr[1] & MGC_M_RXCSR_RXPKTRDY))
1157 value |= MGC_M_RXCSR_H_REQPKT;
1158
1159 s->ep[ep].csr[1] &= 0x102 | (value & 0x4d);
1160 s->ep[ep].csr[1] |= value & 0xfeb0;
1161
1162 musb_ep_frame_cancel(&s->ep[ep], 1);
1163
1164 if (value & MGC_M_RXCSR_FLUSHFIFO) {
1165 s->ep[ep].fifolen[1] = 0;
1166 s->ep[ep].fifostart[1] = 0;
1167 s->ep[ep].csr[1] &= ~(MGC_M_RXCSR_FIFOFULL | MGC_M_RXCSR_RXPKTRDY);
1168 /* If double buffering and we have two packets ready, flush
1169 * only the first one and set up the fifo at the second packet. */
1170 }
1171 #ifdef CLEAR_NAK
1172 if ((value & MGC_M_RXCSR_H_REQPKT) && !(value & MGC_M_RXCSR_DATAERROR))
1173 #else
1174 if (value & MGC_M_RXCSR_H_REQPKT)
1175 #endif
1176 musb_rx_req(s, ep);
1177 break;
1178 case MUSB_HDRC_RXCOUNT:
1179 s->ep[ep].rxcount = value;
1180 break;
1181
1182 default:
1183 musb_ep_writeb(s, ep, addr, value & 0xff);
1184 musb_ep_writeb(s, ep, addr | 1, value >> 8);
1185 };
1186 }
1187
1188 /* Generic control */
1189 static uint32_t musb_readb(void *opaque, target_phys_addr_t addr)
1190 {
1191 MUSBState *s = (MUSBState *) opaque;
1192 int ep, i;
1193 uint8_t ret;
1194
1195 switch (addr) {
1196 case MUSB_HDRC_FADDR:
1197 return s->faddr;
1198 case MUSB_HDRC_POWER:
1199 return s->power;
1200 case MUSB_HDRC_INTRUSB:
1201 ret = s->intr;
1202 for (i = 0; i < sizeof(ret) * 8; i ++)
1203 if (ret & (1 << i))
1204 musb_intr_set(s, i, 0);
1205 return ret;
1206 case MUSB_HDRC_INTRUSBE:
1207 return s->mask;
1208 case MUSB_HDRC_INDEX:
1209 return s->idx;
1210 case MUSB_HDRC_TESTMODE:
1211 return 0x00;
1212
1213 case MUSB_HDRC_EP_IDX ... (MUSB_HDRC_EP_IDX + 0xf):
1214 return musb_ep_readb(s, s->idx, addr & 0xf);
1215
1216 case MUSB_HDRC_DEVCTL:
1217 return s->devctl;
1218
1219 case MUSB_HDRC_TXFIFOSZ:
1220 case MUSB_HDRC_RXFIFOSZ:
1221 case MUSB_HDRC_VCTRL:
1222 /* TODO */
1223 return 0x00;
1224
1225 case MUSB_HDRC_HWVERS:
1226 return (1 << 10) | 400;
1227
1228 case (MUSB_HDRC_VCTRL | 1):
1229 case (MUSB_HDRC_HWVERS | 1):
1230 case (MUSB_HDRC_DEVCTL | 1):
1231 return 0x00;
1232
1233 case MUSB_HDRC_BUSCTL ... (MUSB_HDRC_BUSCTL + 0x7f):
1234 ep = (addr >> 3) & 0xf;
1235 return musb_busctl_readb(s, ep, addr & 0x7);
1236
1237 case MUSB_HDRC_EP ... (MUSB_HDRC_EP + 0xff):
1238 ep = (addr >> 4) & 0xf;
1239 return musb_ep_readb(s, ep, addr & 0xf);
1240
1241 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
1242 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1243 return musb_read_fifo(s->ep + ep);
1244
1245 default:
1246 TRACE("unknown register 0x%02x", (int) addr);
1247 return 0x00;
1248 };
1249 }
1250
1251 static void musb_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
1252 {
1253 MUSBState *s = (MUSBState *) opaque;
1254 int ep;
1255
1256 switch (addr) {
1257 case MUSB_HDRC_FADDR:
1258 s->faddr = value & 0x7f;
1259 break;
1260 case MUSB_HDRC_POWER:
1261 s->power = (value & 0xef) | (s->power & 0x10);
1262 /* MGC_M_POWER_RESET is also read-only in Peripheral Mode */
1263 if ((value & MGC_M_POWER_RESET) && s->port.dev) {
1264 usb_send_msg(s->port.dev, USB_MSG_RESET);
1265 /* Negotiate high-speed operation if MGC_M_POWER_HSENAB is set. */
1266 if ((value & MGC_M_POWER_HSENAB) &&
1267 s->port.dev->speed == USB_SPEED_HIGH)
1268 s->power |= MGC_M_POWER_HSMODE; /* Success */
1269 /* Restart frame counting. */
1270 }
1271 if (value & MGC_M_POWER_SUSPENDM) {
1272 /* When all transfers finish, suspend and if MGC_M_POWER_ENSUSPEND
1273 * is set, also go into low power mode. Frame counting stops. */
1274 /* XXX: Cleared when the interrupt register is read */
1275 }
1276 if (value & MGC_M_POWER_RESUME) {
1277 /* Wait 20ms and signal resuming on the bus. Frame counting
1278 * restarts. */
1279 }
1280 break;
1281 case MUSB_HDRC_INTRUSB:
1282 break;
1283 case MUSB_HDRC_INTRUSBE:
1284 s->mask = value & 0xff;
1285 break;
1286 case MUSB_HDRC_INDEX:
1287 s->idx = value & 0xf;
1288 break;
1289 case MUSB_HDRC_TESTMODE:
1290 break;
1291
1292 case MUSB_HDRC_EP_IDX ... (MUSB_HDRC_EP_IDX + 0xf):
1293 musb_ep_writeb(s, s->idx, addr & 0xf, value);
1294 break;
1295
1296 case MUSB_HDRC_DEVCTL:
1297 s->session = !!(value & MGC_M_DEVCTL_SESSION);
1298 musb_session_update(s,
1299 !!s->port.dev,
1300 !!(s->devctl & MGC_M_DEVCTL_SESSION));
1301
1302 /* It seems this is the only R/W bit in this register? */
1303 s->devctl &= ~MGC_M_DEVCTL_SESSION;
1304 s->devctl |= value & MGC_M_DEVCTL_SESSION;
1305 break;
1306
1307 case MUSB_HDRC_TXFIFOSZ:
1308 case MUSB_HDRC_RXFIFOSZ:
1309 case MUSB_HDRC_VCTRL:
1310 /* TODO */
1311 break;
1312
1313 case (MUSB_HDRC_VCTRL | 1):
1314 case (MUSB_HDRC_DEVCTL | 1):
1315 break;
1316
1317 case MUSB_HDRC_BUSCTL ... (MUSB_HDRC_BUSCTL + 0x7f):
1318 ep = (addr >> 3) & 0xf;
1319 musb_busctl_writeb(s, ep, addr & 0x7, value);
1320 break;
1321
1322 case MUSB_HDRC_EP ... (MUSB_HDRC_EP + 0xff):
1323 ep = (addr >> 4) & 0xf;
1324 musb_ep_writeb(s, ep, addr & 0xf, value);
1325 break;
1326
1327 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
1328 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1329 musb_write_fifo(s->ep + ep, value & 0xff);
1330 break;
1331
1332 default:
1333 TRACE("unknown register 0x%02x", (int) addr);
1334 break;
1335 };
1336 }
1337
1338 static uint32_t musb_readh(void *opaque, target_phys_addr_t addr)
1339 {
1340 MUSBState *s = (MUSBState *) opaque;
1341 int ep, i;
1342 uint16_t ret;
1343
1344 switch (addr) {
1345 case MUSB_HDRC_INTRTX:
1346 ret = s->tx_intr;
1347 /* Auto clear */
1348 for (i = 0; i < sizeof(ret) * 8; i ++)
1349 if (ret & (1 << i))
1350 musb_tx_intr_set(s, i, 0);
1351 return ret;
1352 case MUSB_HDRC_INTRRX:
1353 ret = s->rx_intr;
1354 /* Auto clear */
1355 for (i = 0; i < sizeof(ret) * 8; i ++)
1356 if (ret & (1 << i))
1357 musb_rx_intr_set(s, i, 0);
1358 return ret;
1359 case MUSB_HDRC_INTRTXE:
1360 return s->tx_mask;
1361 case MUSB_HDRC_INTRRXE:
1362 return s->rx_mask;
1363
1364 case MUSB_HDRC_FRAME:
1365 /* TODO */
1366 return 0x0000;
1367 case MUSB_HDRC_TXFIFOADDR:
1368 return s->ep[s->idx].fifoaddr[0];
1369 case MUSB_HDRC_RXFIFOADDR:
1370 return s->ep[s->idx].fifoaddr[1];
1371
1372 case MUSB_HDRC_EP_IDX ... (MUSB_HDRC_EP_IDX + 0xf):
1373 return musb_ep_readh(s, s->idx, addr & 0xf);
1374
1375 case MUSB_HDRC_BUSCTL ... (MUSB_HDRC_BUSCTL + 0x7f):
1376 ep = (addr >> 3) & 0xf;
1377 return musb_busctl_readh(s, ep, addr & 0x7);
1378
1379 case MUSB_HDRC_EP ... (MUSB_HDRC_EP + 0xff):
1380 ep = (addr >> 4) & 0xf;
1381 return musb_ep_readh(s, ep, addr & 0xf);
1382
1383 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
1384 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1385 return (musb_read_fifo(s->ep + ep) | musb_read_fifo(s->ep + ep) << 8);
1386
1387 default:
1388 return musb_readb(s, addr) | (musb_readb(s, addr | 1) << 8);
1389 };
1390 }
1391
1392 static void musb_writeh(void *opaque, target_phys_addr_t addr, uint32_t value)
1393 {
1394 MUSBState *s = (MUSBState *) opaque;
1395 int ep;
1396
1397 switch (addr) {
1398 case MUSB_HDRC_INTRTXE:
1399 s->tx_mask = value;
1400 /* XXX: the masks seem to apply on the raising edge like with
1401 * edge-triggered interrupts, thus no need to update. I may be
1402 * wrong though. */
1403 break;
1404 case MUSB_HDRC_INTRRXE:
1405 s->rx_mask = value;
1406 break;
1407
1408 case MUSB_HDRC_FRAME:
1409 /* TODO */
1410 break;
1411 case MUSB_HDRC_TXFIFOADDR:
1412 s->ep[s->idx].fifoaddr[0] = value;
1413 s->ep[s->idx].buf[0] =
1414 s->buf + ((value << 3) & 0x7ff );
1415 break;
1416 case MUSB_HDRC_RXFIFOADDR:
1417 s->ep[s->idx].fifoaddr[1] = value;
1418 s->ep[s->idx].buf[1] =
1419 s->buf + ((value << 3) & 0x7ff);
1420 break;
1421
1422 case MUSB_HDRC_EP_IDX ... (MUSB_HDRC_EP_IDX + 0xf):
1423 musb_ep_writeh(s, s->idx, addr & 0xf, value);
1424 break;
1425
1426 case MUSB_HDRC_BUSCTL ... (MUSB_HDRC_BUSCTL + 0x7f):
1427 ep = (addr >> 3) & 0xf;
1428 musb_busctl_writeh(s, ep, addr & 0x7, value);
1429 break;
1430
1431 case MUSB_HDRC_EP ... (MUSB_HDRC_EP + 0xff):
1432 ep = (addr >> 4) & 0xf;
1433 musb_ep_writeh(s, ep, addr & 0xf, value);
1434 break;
1435
1436 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
1437 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1438 musb_write_fifo(s->ep + ep, value & 0xff);
1439 musb_write_fifo(s->ep + ep, (value >> 8) & 0xff);
1440 break;
1441
1442 default:
1443 musb_writeb(s, addr, value & 0xff);
1444 musb_writeb(s, addr | 1, value >> 8);
1445 };
1446 }
1447
1448 static uint32_t musb_readw(void *opaque, target_phys_addr_t addr)
1449 {
1450 MUSBState *s = (MUSBState *) opaque;
1451 int ep;
1452
1453 switch (addr) {
1454 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
1455 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1456 return ( musb_read_fifo(s->ep + ep) |
1457 musb_read_fifo(s->ep + ep) << 8 |
1458 musb_read_fifo(s->ep + ep) << 16 |
1459 musb_read_fifo(s->ep + ep) << 24 );
1460 default:
1461 TRACE("unknown register 0x%02x", (int) addr);
1462 return 0x00000000;
1463 };
1464 }
1465
1466 static void musb_writew(void *opaque, target_phys_addr_t addr, uint32_t value)
1467 {
1468 MUSBState *s = (MUSBState *) opaque;
1469 int ep;
1470
1471 switch (addr) {
1472 case MUSB_HDRC_FIFO ... (MUSB_HDRC_FIFO + 0x3f):
1473 ep = ((addr - MUSB_HDRC_FIFO) >> 2) & 0xf;
1474 musb_write_fifo(s->ep + ep, value & 0xff);
1475 musb_write_fifo(s->ep + ep, (value >> 8 ) & 0xff);
1476 musb_write_fifo(s->ep + ep, (value >> 16) & 0xff);
1477 musb_write_fifo(s->ep + ep, (value >> 24) & 0xff);
1478 break;
1479 default:
1480 TRACE("unknown register 0x%02x", (int) addr);
1481 break;
1482 };
1483 }
1484
1485 CPUReadMemoryFunc * const musb_read[] = {
1486 musb_readb,
1487 musb_readh,
1488 musb_readw,
1489 };
1490
1491 CPUWriteMemoryFunc * const musb_write[] = {
1492 musb_writeb,
1493 musb_writeh,
1494 musb_writew,
1495 };
QEmu