hw/i2c/ppc4xx_i2c.c

   1 /*
   2  * PPC4xx I2C controller emulation
   3  *
   4  * Copyright (c) 2007 Jocelyn Mayer
   5  * Copyright (c) 2012 François Revol
   6  * Copyright (c) 2016-2018 BALATON Zoltan
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  */
  26
  27 #include "qemu/osdep.h"
  28 #include "qemu-common.h"
  29 #include "qemu/log.h"
  30 #include "cpu.h"
  31 #include "hw/hw.h"
  32 #include "hw/i2c/ppc4xx_i2c.h"
  33 #include "bitbang_i2c.h"
  34
  35 #define PPC4xx_I2C_MEM_SIZE 18
  36
  37 #define IIC_CNTL_PT         (1 << 0)
  38 #define IIC_CNTL_READ       (1 << 1)
  39 #define IIC_CNTL_CHT        (1 << 2)
  40 #define IIC_CNTL_RPST       (1 << 3)
  41
  42 #define IIC_STS_PT          (1 << 0)
  43 #define IIC_STS_ERR         (1 << 2)
  44 #define IIC_STS_MDBS        (1 << 5)
  45
  46 #define IIC_EXTSTS_XFRA     (1 << 0)
  47
  48 #define IIC_XTCNTLSS_SRST   (1 << 0)
  49
  50 #define IIC_DIRECTCNTL_SDAC (1 << 3)
  51 #define IIC_DIRECTCNTL_SCLC (1 << 2)
  52 #define IIC_DIRECTCNTL_MSDA (1 << 1)
  53 #define IIC_DIRECTCNTL_MSCL (1 << 0)
  54
  55 static void ppc4xx_i2c_reset(DeviceState *s)
  56 {
  57     PPC4xxI2CState *i2c = PPC4xx_I2C(s);
  58
  59     /* FIXME: Should also reset bus?
  60      *if (s->address != ADDR_RESET) {
  61      *    i2c_end_transfer(s->bus);
  62      *}
  63      */
  64
  65     i2c->mdata = 0;
  66     i2c->lmadr = 0;
  67     i2c->hmadr = 0;
  68     i2c->cntl = 0;
  69     i2c->mdcntl = 0;
  70     i2c->sts = 0;
  71     i2c->extsts = 0x8f;
  72     i2c->lsadr = 0;
  73     i2c->hsadr = 0;
  74     i2c->clkdiv = 0;
  75     i2c->intrmsk = 0;
  76     i2c->xfrcnt = 0;
  77     i2c->xtcntlss = 0;
  78     i2c->directcntl = 0xf;
  79 }
  80
  81 static inline bool ppc4xx_i2c_is_master(PPC4xxI2CState *i2c)
  82 {
  83     return true;
  84 }
  85
  86 static uint64_t ppc4xx_i2c_readb(void *opaque, hwaddr addr, unsigned int size)
  87 {
  88     PPC4xxI2CState *i2c = PPC4xx_I2C(opaque);
  89     uint64_t ret;
  90
  91     switch (addr) {
  92     case 0:
  93         ret = i2c->mdata;
  94         if (ppc4xx_i2c_is_master(i2c)) {
  95             ret = 0xff;
  96
  97             if (!(i2c->sts & IIC_STS_MDBS)) {
  98                 qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read "
  99                               "without starting transfer\n",
 100                               TYPE_PPC4xx_I2C, __func__);
 101             } else {
 102                 int pending = (i2c->cntl >> 4) & 3;
 103
 104                 /* get the next byte */
 105                 int byte = i2c_recv(i2c->bus);
 106
 107                 if (byte < 0) {
 108                     qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: read failed "
 109                                   "for device 0x%02x\n", TYPE_PPC4xx_I2C,
 110                                   __func__, i2c->lmadr);
 111                     ret = 0xff;
 112                 } else {
 113                     ret = byte;
 114                     /* Raise interrupt if enabled */
 115                     /*ppc4xx_i2c_raise_interrupt(i2c)*/;
 116                 }
 117
 118                 if (!pending) {
 119                     i2c->sts &= ~IIC_STS_MDBS;
 120                     /*i2c_end_transfer(i2c->bus);*/
 121                 /*} else if (i2c->cntl & (IIC_CNTL_RPST | IIC_CNTL_CHT)) {*/
 122                 } else if (pending) {
 123                     /* current smbus implementation doesn't like
 124                        multibyte xfer repeated start */
 125                     i2c_end_transfer(i2c->bus);
 126                     if (i2c_start_transfer(i2c->bus, i2c->lmadr >> 1, 1)) {
 127                         /* if non zero is returned, the adress is not valid */
 128                         i2c->sts &= ~IIC_STS_PT;
 129                         i2c->sts |= IIC_STS_ERR;
 130                         i2c->extsts |= IIC_EXTSTS_XFRA;
 131                     } else {
 132                         /*i2c->sts |= IIC_STS_PT;*/
 133                         i2c->sts |= IIC_STS_MDBS;
 134                         i2c->sts &= ~IIC_STS_ERR;
 135                         i2c->extsts = 0;
 136                     }
 137                 }
 138                 pending--;
 139                 i2c->cntl = (i2c->cntl & 0xcf) | (pending << 4);
 140             }
 141         } else {
 142             qemu_log_mask(LOG_UNIMP, "[%s]%s: slave mode not implemented\n",
 143                           TYPE_PPC4xx_I2C, __func__);
 144         }
 145         break;
 146     case 4:
 147         ret = i2c->lmadr;
 148         break;
 149     case 5:
 150         ret = i2c->hmadr;
 151         break;
 152     case 6:
 153         ret = i2c->cntl;
 154         break;
 155     case 7:
 156         ret = i2c->mdcntl;
 157         break;
 158     case 8:
 159         ret = i2c->sts;
 160         break;
 161     case 9:
 162         ret = i2c->extsts;
 163         break;
 164     case 10:
 165         ret = i2c->lsadr;
 166         break;
 167     case 11:
 168         ret = i2c->hsadr;
 169         break;
 170     case 12:
 171         ret = i2c->clkdiv;
 172         break;
 173     case 13:
 174         ret = i2c->intrmsk;
 175         break;
 176     case 14:
 177         ret = i2c->xfrcnt;
 178         break;
 179     case 15:
 180         ret = i2c->xtcntlss;
 181         break;
 182     case 16:
 183         ret = i2c->directcntl;
 184         break;
 185     default:
 186         if (addr < PPC4xx_I2C_MEM_SIZE) {
 187             qemu_log_mask(LOG_UNIMP, "%s: Unimplemented register 0x%"
 188                           HWADDR_PRIx "\n", __func__, addr);
 189         } else {
 190             qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address 0x%"
 191                           HWADDR_PRIx "\n", __func__, addr);
 192         }
 193         ret = 0;
 194         break;
 195     }
 196     return ret;
 197 }
 198
 199 static void ppc4xx_i2c_writeb(void *opaque, hwaddr addr, uint64_t value,
 200                               unsigned int size)
 201 {
 202     PPC4xxI2CState *i2c = opaque;
 203
 204     switch (addr) {
 205     case 0:
 206         i2c->mdata = value;
 207         if (!i2c_bus_busy(i2c->bus)) {
 208             /* assume we start a write transfer */
 209             if (i2c_start_transfer(i2c->bus, i2c->lmadr >> 1, 0)) {
 210                 /* if non zero is returned, the adress is not valid */
 211                 i2c->sts &= ~IIC_STS_PT;
 212                 i2c->sts |= IIC_STS_ERR;
 213                 i2c->extsts |= IIC_EXTSTS_XFRA;
 214             } else {
 215                 i2c->sts |= IIC_STS_PT;
 216                 i2c->sts &= ~IIC_STS_ERR;
 217                 i2c->extsts = 0;
 218             }
 219         }
 220         if (i2c_bus_busy(i2c->bus)) {
 221             if (i2c_send(i2c->bus, i2c->mdata)) {
 222                 /* if the target return non zero then end the transfer */
 223                 i2c->sts &= ~IIC_STS_PT;
 224                 i2c->sts |= IIC_STS_ERR;
 225                 i2c->extsts |= IIC_EXTSTS_XFRA;
 226                 i2c_end_transfer(i2c->bus);
 227             }
 228         }
 229         break;
 230     case 4:
 231         i2c->lmadr = value;
 232         if (i2c_bus_busy(i2c->bus)) {
 233             i2c_end_transfer(i2c->bus);
 234         }
 235         break;
 236     case 5:
 237         i2c->hmadr = value;
 238         break;
 239     case 6:
 240         i2c->cntl = value;
 241         if (i2c->cntl & IIC_CNTL_PT) {
 242             if (i2c->cntl & IIC_CNTL_READ) {
 243                 if (i2c_bus_busy(i2c->bus)) {
 244                     /* end previous transfer */
 245                     i2c->sts &= ~IIC_STS_PT;
 246                     i2c_end_transfer(i2c->bus);
 247                 }
 248                 if (i2c_start_transfer(i2c->bus, i2c->lmadr >> 1, 1)) {
 249                     /* if non zero is returned, the adress is not valid */
 250                     i2c->sts &= ~IIC_STS_PT;
 251                     i2c->sts |= IIC_STS_ERR;
 252                     i2c->extsts |= IIC_EXTSTS_XFRA;
 253                 } else {
 254                     /*i2c->sts |= IIC_STS_PT;*/
 255                     i2c->sts |= IIC_STS_MDBS;
 256                     i2c->sts &= ~IIC_STS_ERR;
 257                     i2c->extsts = 0;
 258                 }
 259             } else {
 260                 /* we actually already did the write transfer... */
 261                 i2c->sts &= ~IIC_STS_PT;
 262             }
 263         }
 264         break;
 265     case 7:
 266         i2c->mdcntl = value & 0xdf;
 267         break;
 268     case 8:
 269         i2c->sts &= ~(value & 0xa);
 270         break;
 271     case 9:
 272         i2c->extsts &= ~(value & 0x8f);
 273         break;
 274     case 10:
 275         i2c->lsadr = value;
 276         break;
 277     case 11:
 278         i2c->hsadr = value;
 279         break;
 280     case 12:
 281         i2c->clkdiv = value;
 282         break;
 283     case 13:
 284         i2c->intrmsk = value;
 285         break;
 286     case 14:
 287         i2c->xfrcnt = value & 0x77;
 288         break;
 289     case 15:
 290         if (value & IIC_XTCNTLSS_SRST) {
 291             /* Is it actually a full reset? U-Boot sets some regs before */
 292             ppc4xx_i2c_reset(DEVICE(i2c));
 293             break;
 294         }
 295         i2c->xtcntlss = value;
 296         break;
 297     case 16:
 298         i2c->directcntl = value & (IIC_DIRECTCNTL_SDAC & IIC_DIRECTCNTL_SCLC);
 299         i2c->directcntl |= (value & IIC_DIRECTCNTL_SCLC ? 1 : 0);
 300         bitbang_i2c_set(i2c->bitbang, BITBANG_I2C_SCL,
 301                         i2c->directcntl & IIC_DIRECTCNTL_MSCL);
 302         i2c->directcntl |= bitbang_i2c_set(i2c->bitbang, BITBANG_I2C_SDA,
 303                                (value & IIC_DIRECTCNTL_SDAC) != 0) << 1;
 304         break;
 305     default:
 306         if (addr < PPC4xx_I2C_MEM_SIZE) {
 307             qemu_log_mask(LOG_UNIMP, "%s: Unimplemented register 0x%"
 308                           HWADDR_PRIx "\n", __func__, addr);
 309         } else {
 310             qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address 0x%"
 311                           HWADDR_PRIx "\n", __func__, addr);
 312         }
 313         break;
 314     }
 315 }
 316
 317 static const MemoryRegionOps ppc4xx_i2c_ops = {
 318     .read = ppc4xx_i2c_readb,
 319     .write = ppc4xx_i2c_writeb,
 320     .valid.min_access_size = 1,
 321     .valid.max_access_size = 4,
 322     .impl.min_access_size = 1,
 323     .impl.max_access_size = 1,
 324     .endianness = DEVICE_NATIVE_ENDIAN,
 325 };
 326
 327 static void ppc4xx_i2c_init(Object *o)
 328 {
 329     PPC4xxI2CState *s = PPC4xx_I2C(o);
 330
 331     memory_region_init_io(&s->iomem, OBJECT(s), &ppc4xx_i2c_ops, s,
 332                           TYPE_PPC4xx_I2C, PPC4xx_I2C_MEM_SIZE);
 333     sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
 334     sysbus_init_irq(SYS_BUS_DEVICE(s), &s->irq);
 335     s->bus = i2c_init_bus(DEVICE(s), "i2c");
 336     s->bitbang = bitbang_i2c_init(s->bus);
 337 }
 338
 339 static void ppc4xx_i2c_class_init(ObjectClass *klass, void *data)
 340 {
 341     DeviceClass *dc = DEVICE_CLASS(klass);
 342
 343     dc->reset = ppc4xx_i2c_reset;
 344 }
 345
 346 static const TypeInfo ppc4xx_i2c_type_info = {
 347     .name = TYPE_PPC4xx_I2C,
 348     .parent = TYPE_SYS_BUS_DEVICE,
 349     .instance_size = sizeof(PPC4xxI2CState),
 350     .instance_init = ppc4xx_i2c_init,
 351     .class_init = ppc4xx_i2c_class_init,
 352 };
 353
 354 static void ppc4xx_i2c_register_types(void)
 355 {
 356     type_register_static(&ppc4xx_i2c_type_info);
 357 }
 358
 359 type_init(ppc4xx_i2c_register_types)