hw/net/lan9118.c

   1 /*
   2  * SMSC LAN9118 Ethernet interface emulation
   3  *
   4  * Copyright (c) 2009 CodeSourcery, LLC.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GNU GPL v2
   8  *
   9  * Contributions after 2012-01-13 are licensed under the terms of the
  10  * GNU GPL, version 2 or (at your option) any later version.
  11  */
  12
  13 #include "qemu/osdep.h"
  14 #include "hw/sysbus.h"
  15 #include "net/net.h"
  16 #include "net/eth.h"
  17 #include "hw/devices.h"
  18 #include "sysemu/sysemu.h"
  19 #include "hw/ptimer.h"
  20 #include "qemu/log.h"
  21 /* For crc32 */
  22 #include <zlib.h>
  23
  24 //#define DEBUG_LAN9118
  25
  26 #ifdef DEBUG_LAN9118
  27 #define DPRINTF(fmt, ...) \
  28 do { printf("lan9118: " fmt , ## __VA_ARGS__); } while (0)
  29 #define BADF(fmt, ...) \
  30 do { hw_error("lan9118: error: " fmt , ## __VA_ARGS__);} while (0)
  31 #else
  32 #define DPRINTF(fmt, ...) do {} while(0)
  33 #define BADF(fmt, ...) \
  34 do { fprintf(stderr, "lan9118: error: " fmt , ## __VA_ARGS__);} while (0)
  35 #endif
  36
  37 #define CSR_ID_REV      0x50
  38 #define CSR_IRQ_CFG     0x54
  39 #define CSR_INT_STS     0x58
  40 #define CSR_INT_EN      0x5c
  41 #define CSR_BYTE_TEST   0x64
  42 #define CSR_FIFO_INT    0x68
  43 #define CSR_RX_CFG      0x6c
  44 #define CSR_TX_CFG      0x70
  45 #define CSR_HW_CFG      0x74
  46 #define CSR_RX_DP_CTRL  0x78
  47 #define CSR_RX_FIFO_INF 0x7c
  48 #define CSR_TX_FIFO_INF 0x80
  49 #define CSR_PMT_CTRL    0x84
  50 #define CSR_GPIO_CFG    0x88
  51 #define CSR_GPT_CFG     0x8c
  52 #define CSR_GPT_CNT     0x90
  53 #define CSR_WORD_SWAP   0x98
  54 #define CSR_FREE_RUN    0x9c
  55 #define CSR_RX_DROP     0xa0
  56 #define CSR_MAC_CSR_CMD 0xa4
  57 #define CSR_MAC_CSR_DATA 0xa8
  58 #define CSR_AFC_CFG     0xac
  59 #define CSR_E2P_CMD     0xb0
  60 #define CSR_E2P_DATA    0xb4
  61
  62 #define E2P_CMD_MAC_ADDR_LOADED 0x100
  63
  64 /* IRQ_CFG */
  65 #define IRQ_INT         0x00001000
  66 #define IRQ_EN          0x00000100
  67 #define IRQ_POL         0x00000010
  68 #define IRQ_TYPE        0x00000001
  69
  70 /* INT_STS/INT_EN */
  71 #define SW_INT          0x80000000
  72 #define TXSTOP_INT      0x02000000
  73 #define RXSTOP_INT      0x01000000
  74 #define RXDFH_INT       0x00800000
  75 #define TX_IOC_INT      0x00200000
  76 #define RXD_INT         0x00100000
  77 #define GPT_INT         0x00080000
  78 #define PHY_INT         0x00040000
  79 #define PME_INT         0x00020000
  80 #define TXSO_INT        0x00010000
  81 #define RWT_INT         0x00008000
  82 #define RXE_INT         0x00004000
  83 #define TXE_INT         0x00002000
  84 #define TDFU_INT        0x00000800
  85 #define TDFO_INT        0x00000400
  86 #define TDFA_INT        0x00000200
  87 #define TSFF_INT        0x00000100
  88 #define TSFL_INT        0x00000080
  89 #define RXDF_INT        0x00000040
  90 #define RDFL_INT        0x00000020
  91 #define RSFF_INT        0x00000010
  92 #define RSFL_INT        0x00000008
  93 #define GPIO2_INT       0x00000004
  94 #define GPIO1_INT       0x00000002
  95 #define GPIO0_INT       0x00000001
  96 #define RESERVED_INT    0x7c001000
  97
  98 #define MAC_CR          1
  99 #define MAC_ADDRH       2
 100 #define MAC_ADDRL       3
 101 #define MAC_HASHH       4
 102 #define MAC_HASHL       5
 103 #define MAC_MII_ACC     6
 104 #define MAC_MII_DATA    7
 105 #define MAC_FLOW        8
 106 #define MAC_VLAN1       9 /* TODO */
 107 #define MAC_VLAN2       10 /* TODO */
 108 #define MAC_WUFF        11 /* TODO */
 109 #define MAC_WUCSR       12 /* TODO */
 110
 111 #define MAC_CR_RXALL    0x80000000
 112 #define MAC_CR_RCVOWN   0x00800000
 113 #define MAC_CR_LOOPBK   0x00200000
 114 #define MAC_CR_FDPX     0x00100000
 115 #define MAC_CR_MCPAS    0x00080000
 116 #define MAC_CR_PRMS     0x00040000
 117 #define MAC_CR_INVFILT  0x00020000
 118 #define MAC_CR_PASSBAD  0x00010000
 119 #define MAC_CR_HO       0x00008000
 120 #define MAC_CR_HPFILT   0x00002000
 121 #define MAC_CR_LCOLL    0x00001000
 122 #define MAC_CR_BCAST    0x00000800
 123 #define MAC_CR_DISRTY   0x00000400
 124 #define MAC_CR_PADSTR   0x00000100
 125 #define MAC_CR_BOLMT    0x000000c0
 126 #define MAC_CR_DFCHK    0x00000020
 127 #define MAC_CR_TXEN     0x00000008
 128 #define MAC_CR_RXEN     0x00000004
 129 #define MAC_CR_RESERVED 0x7f404213
 130
 131 #define PHY_INT_ENERGYON            0x80
 132 #define PHY_INT_AUTONEG_COMPLETE    0x40
 133 #define PHY_INT_FAULT               0x20
 134 #define PHY_INT_DOWN                0x10
 135 #define PHY_INT_AUTONEG_LP          0x08
 136 #define PHY_INT_PARFAULT            0x04
 137 #define PHY_INT_AUTONEG_PAGE        0x02
 138
 139 #define GPT_TIMER_EN    0x20000000
 140
 141 enum tx_state {
 142     TX_IDLE,
 143     TX_B,
 144     TX_DATA
 145 };
 146
 147 typedef struct {
 148     /* state is a tx_state but we can't put enums in VMStateDescriptions. */
 149     uint32_t state;
 150     uint32_t cmd_a;
 151     uint32_t cmd_b;
 152     int32_t buffer_size;
 153     int32_t offset;
 154     int32_t pad;
 155     int32_t fifo_used;
 156     int32_t len;
 157     uint8_t data[2048];
 158 } LAN9118Packet;
 159
 160 static const VMStateDescription vmstate_lan9118_packet = {
 161     .name = "lan9118_packet",
 162     .version_id = 1,
 163     .minimum_version_id = 1,
 164     .fields = (VMStateField[]) {
 165         VMSTATE_UINT32(state, LAN9118Packet),
 166         VMSTATE_UINT32(cmd_a, LAN9118Packet),
 167         VMSTATE_UINT32(cmd_b, LAN9118Packet),
 168         VMSTATE_INT32(buffer_size, LAN9118Packet),
 169         VMSTATE_INT32(offset, LAN9118Packet),
 170         VMSTATE_INT32(pad, LAN9118Packet),
 171         VMSTATE_INT32(fifo_used, LAN9118Packet),
 172         VMSTATE_INT32(len, LAN9118Packet),
 173         VMSTATE_UINT8_ARRAY(data, LAN9118Packet, 2048),
 174         VMSTATE_END_OF_LIST()
 175     }
 176 };
 177
 178 #define TYPE_LAN9118 "lan9118"
 179 #define LAN9118(obj) OBJECT_CHECK(lan9118_state, (obj), TYPE_LAN9118)
 180
 181 typedef struct {
 182     SysBusDevice parent_obj;
 183
 184     NICState *nic;
 185     NICConf conf;
 186     qemu_irq irq;
 187     MemoryRegion mmio;
 188     ptimer_state *timer;
 189
 190     uint32_t irq_cfg;
 191     uint32_t int_sts;
 192     uint32_t int_en;
 193     uint32_t fifo_int;
 194     uint32_t rx_cfg;
 195     uint32_t tx_cfg;
 196     uint32_t hw_cfg;
 197     uint32_t pmt_ctrl;
 198     uint32_t gpio_cfg;
 199     uint32_t gpt_cfg;
 200     uint32_t word_swap;
 201     uint32_t free_timer_start;
 202     uint32_t mac_cmd;
 203     uint32_t mac_data;
 204     uint32_t afc_cfg;
 205     uint32_t e2p_cmd;
 206     uint32_t e2p_data;
 207
 208     uint32_t mac_cr;
 209     uint32_t mac_hashh;
 210     uint32_t mac_hashl;
 211     uint32_t mac_mii_acc;
 212     uint32_t mac_mii_data;
 213     uint32_t mac_flow;
 214
 215     uint32_t phy_status;
 216     uint32_t phy_control;
 217     uint32_t phy_advertise;
 218     uint32_t phy_int;
 219     uint32_t phy_int_mask;
 220
 221     int32_t eeprom_writable;
 222     uint8_t eeprom[128];
 223
 224     int32_t tx_fifo_size;
 225     LAN9118Packet *txp;
 226     LAN9118Packet tx_packet;
 227
 228     int32_t tx_status_fifo_used;
 229     int32_t tx_status_fifo_head;
 230     uint32_t tx_status_fifo[512];
 231
 232     int32_t rx_status_fifo_size;
 233     int32_t rx_status_fifo_used;
 234     int32_t rx_status_fifo_head;
 235     uint32_t rx_status_fifo[896];
 236     int32_t rx_fifo_size;
 237     int32_t rx_fifo_used;
 238     int32_t rx_fifo_head;
 239     uint32_t rx_fifo[3360];
 240     int32_t rx_packet_size_head;
 241     int32_t rx_packet_size_tail;
 242     int32_t rx_packet_size[1024];
 243
 244     int32_t rxp_offset;
 245     int32_t rxp_size;
 246     int32_t rxp_pad;
 247
 248     uint32_t write_word_prev_offset;
 249     uint32_t write_word_n;
 250     uint16_t write_word_l;
 251     uint16_t write_word_h;
 252     uint32_t read_word_prev_offset;
 253     uint32_t read_word_n;
 254     uint32_t read_long;
 255
 256     uint32_t mode_16bit;
 257 } lan9118_state;
 258
 259 static const VMStateDescription vmstate_lan9118 = {
 260     .name = "lan9118",
 261     .version_id = 2,
 262     .minimum_version_id = 1,
 263     .fields = (VMStateField[]) {
 264         VMSTATE_PTIMER(timer, lan9118_state),
 265         VMSTATE_UINT32(irq_cfg, lan9118_state),
 266         VMSTATE_UINT32(int_sts, lan9118_state),
 267         VMSTATE_UINT32(int_en, lan9118_state),
 268         VMSTATE_UINT32(fifo_int, lan9118_state),
 269         VMSTATE_UINT32(rx_cfg, lan9118_state),
 270         VMSTATE_UINT32(tx_cfg, lan9118_state),
 271         VMSTATE_UINT32(hw_cfg, lan9118_state),
 272         VMSTATE_UINT32(pmt_ctrl, lan9118_state),
 273         VMSTATE_UINT32(gpio_cfg, lan9118_state),
 274         VMSTATE_UINT32(gpt_cfg, lan9118_state),
 275         VMSTATE_UINT32(word_swap, lan9118_state),
 276         VMSTATE_UINT32(free_timer_start, lan9118_state),
 277         VMSTATE_UINT32(mac_cmd, lan9118_state),
 278         VMSTATE_UINT32(mac_data, lan9118_state),
 279         VMSTATE_UINT32(afc_cfg, lan9118_state),
 280         VMSTATE_UINT32(e2p_cmd, lan9118_state),
 281         VMSTATE_UINT32(e2p_data, lan9118_state),
 282         VMSTATE_UINT32(mac_cr, lan9118_state),
 283         VMSTATE_UINT32(mac_hashh, lan9118_state),
 284         VMSTATE_UINT32(mac_hashl, lan9118_state),
 285         VMSTATE_UINT32(mac_mii_acc, lan9118_state),
 286         VMSTATE_UINT32(mac_mii_data, lan9118_state),
 287         VMSTATE_UINT32(mac_flow, lan9118_state),
 288         VMSTATE_UINT32(phy_status, lan9118_state),
 289         VMSTATE_UINT32(phy_control, lan9118_state),
 290         VMSTATE_UINT32(phy_advertise, lan9118_state),
 291         VMSTATE_UINT32(phy_int, lan9118_state),
 292         VMSTATE_UINT32(phy_int_mask, lan9118_state),
 293         VMSTATE_INT32(eeprom_writable, lan9118_state),
 294         VMSTATE_UINT8_ARRAY(eeprom, lan9118_state, 128),
 295         VMSTATE_INT32(tx_fifo_size, lan9118_state),
 296         /* txp always points at tx_packet so need not be saved */
 297         VMSTATE_STRUCT(tx_packet, lan9118_state, 0,
 298                        vmstate_lan9118_packet, LAN9118Packet),
 299         VMSTATE_INT32(tx_status_fifo_used, lan9118_state),
 300         VMSTATE_INT32(tx_status_fifo_head, lan9118_state),
 301         VMSTATE_UINT32_ARRAY(tx_status_fifo, lan9118_state, 512),
 302         VMSTATE_INT32(rx_status_fifo_size, lan9118_state),
 303         VMSTATE_INT32(rx_status_fifo_used, lan9118_state),
 304         VMSTATE_INT32(rx_status_fifo_head, lan9118_state),
 305         VMSTATE_UINT32_ARRAY(rx_status_fifo, lan9118_state, 896),
 306         VMSTATE_INT32(rx_fifo_size, lan9118_state),
 307         VMSTATE_INT32(rx_fifo_used, lan9118_state),
 308         VMSTATE_INT32(rx_fifo_head, lan9118_state),
 309         VMSTATE_UINT32_ARRAY(rx_fifo, lan9118_state, 3360),
 310         VMSTATE_INT32(rx_packet_size_head, lan9118_state),
 311         VMSTATE_INT32(rx_packet_size_tail, lan9118_state),
 312         VMSTATE_INT32_ARRAY(rx_packet_size, lan9118_state, 1024),
 313         VMSTATE_INT32(rxp_offset, lan9118_state),
 314         VMSTATE_INT32(rxp_size, lan9118_state),
 315         VMSTATE_INT32(rxp_pad, lan9118_state),
 316         VMSTATE_UINT32_V(write_word_prev_offset, lan9118_state, 2),
 317         VMSTATE_UINT32_V(write_word_n, lan9118_state, 2),
 318         VMSTATE_UINT16_V(write_word_l, lan9118_state, 2),
 319         VMSTATE_UINT16_V(write_word_h, lan9118_state, 2),
 320         VMSTATE_UINT32_V(read_word_prev_offset, lan9118_state, 2),
 321         VMSTATE_UINT32_V(read_word_n, lan9118_state, 2),
 322         VMSTATE_UINT32_V(read_long, lan9118_state, 2),
 323         VMSTATE_UINT32_V(mode_16bit, lan9118_state, 2),
 324         VMSTATE_END_OF_LIST()
 325     }
 326 };
 327
 328 static void lan9118_update(lan9118_state *s)
 329 {
 330     int level;
 331
 332     /* TODO: Implement FIFO level IRQs.  */
 333     level = (s->int_sts & s->int_en) != 0;
 334     if (level) {
 335         s->irq_cfg |= IRQ_INT;
 336     } else {
 337         s->irq_cfg &= ~IRQ_INT;
 338     }
 339     if ((s->irq_cfg & IRQ_EN) == 0) {
 340         level = 0;
 341     }
 342     if ((s->irq_cfg & (IRQ_TYPE | IRQ_POL)) != (IRQ_TYPE | IRQ_POL)) {
 343         /* Interrupt is active low unless we're configured as
 344          * active-high polarity, push-pull type.
 345          */
 346         level = !level;
 347     }
 348     qemu_set_irq(s->irq, level);
 349 }
 350
 351 static void lan9118_mac_changed(lan9118_state *s)
 352 {
 353     qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
 354 }
 355
 356 static void lan9118_reload_eeprom(lan9118_state *s)
 357 {
 358     int i;
 359     if (s->eeprom[0] != 0xa5) {
 360         s->e2p_cmd &= ~E2P_CMD_MAC_ADDR_LOADED;
 361         DPRINTF("MACADDR load failed\n");
 362         return;
 363     }
 364     for (i = 0; i < 6; i++) {
 365         s->conf.macaddr.a[i] = s->eeprom[i + 1];
 366     }
 367     s->e2p_cmd |= E2P_CMD_MAC_ADDR_LOADED;
 368     DPRINTF("MACADDR loaded from eeprom\n");
 369     lan9118_mac_changed(s);
 370 }
 371
 372 static void phy_update_irq(lan9118_state *s)
 373 {
 374     if (s->phy_int & s->phy_int_mask) {
 375         s->int_sts |= PHY_INT;
 376     } else {
 377         s->int_sts &= ~PHY_INT;
 378     }
 379     lan9118_update(s);
 380 }
 381
 382 static void phy_update_link(lan9118_state *s)
 383 {
 384     /* Autonegotiation status mirrors link status.  */
 385     if (qemu_get_queue(s->nic)->link_down) {
 386         s->phy_status &= ~0x0024;
 387         s->phy_int |= PHY_INT_DOWN;
 388     } else {
 389         s->phy_status |= 0x0024;
 390         s->phy_int |= PHY_INT_ENERGYON;
 391         s->phy_int |= PHY_INT_AUTONEG_COMPLETE;
 392     }
 393     phy_update_irq(s);
 394 }
 395
 396 static void lan9118_set_link(NetClientState *nc)
 397 {
 398     phy_update_link(qemu_get_nic_opaque(nc));
 399 }
 400
 401 static void phy_reset(lan9118_state *s)
 402 {
 403     s->phy_status = 0x7809;
 404     s->phy_control = 0x3000;
 405     s->phy_advertise = 0x01e1;
 406     s->phy_int_mask = 0;
 407     s->phy_int = 0;
 408     phy_update_link(s);
 409 }
 410
 411 static void lan9118_reset(DeviceState *d)
 412 {
 413     lan9118_state *s = LAN9118(d);
 414
 415     s->irq_cfg &= (IRQ_TYPE | IRQ_POL);
 416     s->int_sts = 0;
 417     s->int_en = 0;
 418     s->fifo_int = 0x48000000;
 419     s->rx_cfg = 0;
 420     s->tx_cfg = 0;
 421     s->hw_cfg = s->mode_16bit ? 0x00050000 : 0x00050004;
 422     s->pmt_ctrl &= 0x45;
 423     s->gpio_cfg = 0;
 424     s->txp->fifo_used = 0;
 425     s->txp->state = TX_IDLE;
 426     s->txp->cmd_a = 0xffffffffu;
 427     s->txp->cmd_b = 0xffffffffu;
 428     s->txp->len = 0;
 429     s->txp->fifo_used = 0;
 430     s->tx_fifo_size = 4608;
 431     s->tx_status_fifo_used = 0;
 432     s->rx_status_fifo_size = 704;
 433     s->rx_fifo_size = 2640;
 434     s->rx_fifo_used = 0;
 435     s->rx_status_fifo_size = 176;
 436     s->rx_status_fifo_used = 0;
 437     s->rxp_offset = 0;
 438     s->rxp_size = 0;
 439     s->rxp_pad = 0;
 440     s->rx_packet_size_tail = s->rx_packet_size_head;
 441     s->rx_packet_size[s->rx_packet_size_head] = 0;
 442     s->mac_cmd = 0;
 443     s->mac_data = 0;
 444     s->afc_cfg = 0;
 445     s->e2p_cmd = 0;
 446     s->e2p_data = 0;
 447     s->free_timer_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / 40;
 448
 449     ptimer_stop(s->timer);
 450     ptimer_set_count(s->timer, 0xffff);
 451     s->gpt_cfg = 0xffff;
 452
 453     s->mac_cr = MAC_CR_PRMS;
 454     s->mac_hashh = 0;
 455     s->mac_hashl = 0;
 456     s->mac_mii_acc = 0;
 457     s->mac_mii_data = 0;
 458     s->mac_flow = 0;
 459
 460     s->read_word_n = 0;
 461     s->write_word_n = 0;
 462
 463     phy_reset(s);
 464
 465     s->eeprom_writable = 0;
 466     lan9118_reload_eeprom(s);
 467 }
 468
 469 static void rx_fifo_push(lan9118_state *s, uint32_t val)
 470 {
 471     int fifo_pos;
 472     fifo_pos = s->rx_fifo_head + s->rx_fifo_used;
 473     if (fifo_pos >= s->rx_fifo_size)
 474       fifo_pos -= s->rx_fifo_size;
 475     s->rx_fifo[fifo_pos] = val;
 476     s->rx_fifo_used++;
 477 }
 478
 479 /* Return nonzero if the packet is accepted by the filter.  */
 480 static int lan9118_filter(lan9118_state *s, const uint8_t *addr)
 481 {
 482     int multicast;
 483     uint32_t hash;
 484
 485     if (s->mac_cr & MAC_CR_PRMS) {
 486         return 1;
 487     }
 488     if (addr[0] == 0xff && addr[1] == 0xff && addr[2] == 0xff &&
 489         addr[3] == 0xff && addr[4] == 0xff && addr[5] == 0xff) {
 490         return (s->mac_cr & MAC_CR_BCAST) == 0;
 491     }
 492
 493     multicast = addr[0] & 1;
 494     if (multicast &&s->mac_cr & MAC_CR_MCPAS) {
 495         return 1;
 496     }
 497     if (multicast ? (s->mac_cr & MAC_CR_HPFILT) == 0
 498                   : (s->mac_cr & MAC_CR_HO) == 0) {
 499         /* Exact matching.  */
 500         hash = memcmp(addr, s->conf.macaddr.a, 6);
 501         if (s->mac_cr & MAC_CR_INVFILT) {
 502             return hash != 0;
 503         } else {
 504             return hash == 0;
 505         }
 506     } else {
 507         /* Hash matching  */
 508         hash = net_crc32(addr, ETH_ALEN) >> 26;
 509         if (hash & 0x20) {
 510             return (s->mac_hashh >> (hash & 0x1f)) & 1;
 511         } else {
 512             return (s->mac_hashl >> (hash & 0x1f)) & 1;
 513         }
 514     }
 515 }
 516
 517 static ssize_t lan9118_receive(NetClientState *nc, const uint8_t *buf,
 518                                size_t size)
 519 {
 520     lan9118_state *s = qemu_get_nic_opaque(nc);
 521     int fifo_len;
 522     int offset;
 523     int src_pos;
 524     int n;
 525     int filter;
 526     uint32_t val;
 527     uint32_t crc;
 528     uint32_t status;
 529
 530     if ((s->mac_cr & MAC_CR_RXEN) == 0) {
 531         return -1;
 532     }
 533
 534     if (size >= 2048 || size < 14) {
 535         return -1;
 536     }
 537
 538     /* TODO: Implement FIFO overflow notification.  */
 539     if (s->rx_status_fifo_used == s->rx_status_fifo_size) {
 540         return -1;
 541     }
 542
 543     filter = lan9118_filter(s, buf);
 544     if (!filter && (s->mac_cr & MAC_CR_RXALL) == 0) {
 545         return size;
 546     }
 547
 548     offset = (s->rx_cfg >> 8) & 0x1f;
 549     n = offset & 3;
 550     fifo_len = (size + n + 3) >> 2;
 551     /* Add a word for the CRC.  */
 552     fifo_len++;
 553     if (s->rx_fifo_size - s->rx_fifo_used < fifo_len) {
 554         return -1;
 555     }
 556
 557     DPRINTF("Got packet len:%d fifo:%d filter:%s\n",
 558             (int)size, fifo_len, filter ? "pass" : "fail");
 559     val = 0;
 560     crc = bswap32(crc32(~0, buf, size));
 561     for (src_pos = 0; src_pos < size; src_pos++) {
 562         val = (val >> 8) | ((uint32_t)buf[src_pos] << 24);
 563         n++;
 564         if (n == 4) {
 565             n = 0;
 566             rx_fifo_push(s, val);
 567             val = 0;
 568         }
 569     }
 570     if (n) {
 571         val >>= ((4 - n) * 8);
 572         val |= crc << (n * 8);
 573         rx_fifo_push(s, val);
 574         val = crc >> ((4 - n) * 8);
 575         rx_fifo_push(s, val);
 576     } else {
 577         rx_fifo_push(s, crc);
 578     }
 579     n = s->rx_status_fifo_head + s->rx_status_fifo_used;
 580     if (n >= s->rx_status_fifo_size) {
 581         n -= s->rx_status_fifo_size;
 582     }
 583     s->rx_packet_size[s->rx_packet_size_tail] = fifo_len;
 584     s->rx_packet_size_tail = (s->rx_packet_size_tail + 1023) & 1023;
 585     s->rx_status_fifo_used++;
 586
 587     status = (size + 4) << 16;
 588     if (buf[0] == 0xff && buf[1] == 0xff && buf[2] == 0xff &&
 589         buf[3] == 0xff && buf[4] == 0xff && buf[5] == 0xff) {
 590         status |= 0x00002000;
 591     } else if (buf[0] & 1) {
 592         status |= 0x00000400;
 593     }
 594     if (!filter) {
 595         status |= 0x40000000;
 596     }
 597     s->rx_status_fifo[n] = status;
 598
 599     if (s->rx_status_fifo_used > (s->fifo_int & 0xff)) {
 600         s->int_sts |= RSFL_INT;
 601     }
 602     lan9118_update(s);
 603
 604     return size;
 605 }
 606
 607 static uint32_t rx_fifo_pop(lan9118_state *s)
 608 {
 609     int n;
 610     uint32_t val;
 611
 612     if (s->rxp_size == 0 && s->rxp_pad == 0) {
 613         s->rxp_size = s->rx_packet_size[s->rx_packet_size_head];
 614         s->rx_packet_size[s->rx_packet_size_head] = 0;
 615         if (s->rxp_size != 0) {
 616             s->rx_packet_size_head = (s->rx_packet_size_head + 1023) & 1023;
 617             s->rxp_offset = (s->rx_cfg >> 10) & 7;
 618             n = s->rxp_offset + s->rxp_size;
 619             switch (s->rx_cfg >> 30) {
 620             case 1:
 621                 n = (-n) & 3;
 622                 break;
 623             case 2:
 624                 n = (-n) & 7;
 625                 break;
 626             default:
 627                 n = 0;
 628                 break;
 629             }
 630             s->rxp_pad = n;
 631             DPRINTF("Pop packet size:%d offset:%d pad: %d\n",
 632                     s->rxp_size, s->rxp_offset, s->rxp_pad);
 633         }
 634     }
 635     if (s->rxp_offset > 0) {
 636         s->rxp_offset--;
 637         val = 0;
 638     } else if (s->rxp_size > 0) {
 639         s->rxp_size--;
 640         val = s->rx_fifo[s->rx_fifo_head++];
 641         if (s->rx_fifo_head >= s->rx_fifo_size) {
 642             s->rx_fifo_head -= s->rx_fifo_size;
 643         }
 644         s->rx_fifo_used--;
 645     } else if (s->rxp_pad > 0) {
 646         s->rxp_pad--;
 647         val =  0;
 648     } else {
 649         DPRINTF("RX underflow\n");
 650         s->int_sts |= RXE_INT;
 651         val =  0;
 652     }
 653     lan9118_update(s);
 654     return val;
 655 }
 656
 657 static void do_tx_packet(lan9118_state *s)
 658 {
 659     int n;
 660     uint32_t status;
 661
 662     /* FIXME: Honor TX disable, and allow queueing of packets.  */
 663     if (s->phy_control & 0x4000)  {
 664         /* This assumes the receive routine doesn't touch the VLANClient.  */
 665         lan9118_receive(qemu_get_queue(s->nic), s->txp->data, s->txp->len);
 666     } else {
 667         qemu_send_packet(qemu_get_queue(s->nic), s->txp->data, s->txp->len);
 668     }
 669     s->txp->fifo_used = 0;
 670
 671     if (s->tx_status_fifo_used == 512) {
 672         /* Status FIFO full */
 673         return;
 674     }
 675     /* Add entry to status FIFO.  */
 676     status = s->txp->cmd_b & 0xffff0000u;
 677     DPRINTF("Sent packet tag:%04x len %d\n", status >> 16, s->txp->len);
 678     n = (s->tx_status_fifo_head + s->tx_status_fifo_used) & 511;
 679     s->tx_status_fifo[n] = status;
 680     s->tx_status_fifo_used++;
 681     if (s->tx_status_fifo_used == 512) {
 682         s->int_sts |= TSFF_INT;
 683         /* TODO: Stop transmission.  */
 684     }
 685 }
 686
 687 static uint32_t rx_status_fifo_pop(lan9118_state *s)
 688 {
 689     uint32_t val;
 690
 691     val = s->rx_status_fifo[s->rx_status_fifo_head];
 692     if (s->rx_status_fifo_used != 0) {
 693         s->rx_status_fifo_used--;
 694         s->rx_status_fifo_head++;
 695         if (s->rx_status_fifo_head >= s->rx_status_fifo_size) {
 696             s->rx_status_fifo_head -= s->rx_status_fifo_size;
 697         }
 698         /* ??? What value should be returned when the FIFO is empty?  */
 699         DPRINTF("RX status pop 0x%08x\n", val);
 700     }
 701     return val;
 702 }
 703
 704 static uint32_t tx_status_fifo_pop(lan9118_state *s)
 705 {
 706     uint32_t val;
 707
 708     val = s->tx_status_fifo[s->tx_status_fifo_head];
 709     if (s->tx_status_fifo_used != 0) {
 710         s->tx_status_fifo_used--;
 711         s->tx_status_fifo_head = (s->tx_status_fifo_head + 1) & 511;
 712         /* ??? What value should be returned when the FIFO is empty?  */
 713     }
 714     return val;
 715 }
 716
 717 static void tx_fifo_push(lan9118_state *s, uint32_t val)
 718 {
 719     int n;
 720
 721     if (s->txp->fifo_used == s->tx_fifo_size) {
 722         s->int_sts |= TDFO_INT;
 723         return;
 724     }
 725     switch (s->txp->state) {
 726     case TX_IDLE:
 727         s->txp->cmd_a = val & 0x831f37ff;
 728         s->txp->fifo_used++;
 729         s->txp->state = TX_B;
 730         s->txp->buffer_size = extract32(s->txp->cmd_a, 0, 11);
 731         s->txp->offset = extract32(s->txp->cmd_a, 16, 5);
 732         break;
 733     case TX_B:
 734         if (s->txp->cmd_a & 0x2000) {
 735             /* First segment */
 736             s->txp->cmd_b = val;
 737             s->txp->fifo_used++;
 738             /* End alignment does not include command words.  */
 739             n = (s->txp->buffer_size + s->txp->offset + 3) >> 2;
 740             switch ((n >> 24) & 3) {
 741             case 1:
 742                 n = (-n) & 3;
 743                 break;
 744             case 2:
 745                 n = (-n) & 7;
 746                 break;
 747             default:
 748                 n = 0;
 749             }
 750             s->txp->pad = n;
 751             s->txp->len = 0;
 752         }
 753         DPRINTF("Block len:%d offset:%d pad:%d cmd %08x\n",
 754                 s->txp->buffer_size, s->txp->offset, s->txp->pad,
 755                 s->txp->cmd_a);
 756         s->txp->state = TX_DATA;
 757         break;
 758     case TX_DATA:
 759         if (s->txp->offset >= 4) {
 760             s->txp->offset -= 4;
 761             break;
 762         }
 763         if (s->txp->buffer_size <= 0 && s->txp->pad != 0) {
 764             s->txp->pad--;
 765         } else {
 766             n = MIN(4, s->txp->buffer_size + s->txp->offset);
 767             while (s->txp->offset) {
 768                 val >>= 8;
 769                 n--;
 770                 s->txp->offset--;
 771             }
 772             /* Documentation is somewhat unclear on the ordering of bytes
 773                in FIFO words.  Empirical results show it to be little-endian.
 774                */
 775             /* TODO: FIFO overflow checking.  */
 776             while (n--) {
 777                 s->txp->data[s->txp->len] = val & 0xff;
 778                 s->txp->len++;
 779                 val >>= 8;
 780                 s->txp->buffer_size--;
 781             }
 782             s->txp->fifo_used++;
 783         }
 784         if (s->txp->buffer_size <= 0 && s->txp->pad == 0) {
 785             if (s->txp->cmd_a & 0x1000) {
 786                 do_tx_packet(s);
 787             }
 788             if (s->txp->cmd_a & 0x80000000) {
 789                 s->int_sts |= TX_IOC_INT;
 790             }
 791             s->txp->state = TX_IDLE;
 792         }
 793         break;
 794     }
 795 }
 796
 797 static uint32_t do_phy_read(lan9118_state *s, int reg)
 798 {
 799     uint32_t val;
 800
 801     switch (reg) {
 802     case 0: /* Basic Control */
 803         return s->phy_control;
 804     case 1: /* Basic Status */
 805         return s->phy_status;
 806     case 2: /* ID1 */
 807         return 0x0007;
 808     case 3: /* ID2 */
 809         return 0xc0d1;
 810     case 4: /* Auto-neg advertisement */
 811         return s->phy_advertise;
 812     case 5: /* Auto-neg Link Partner Ability */
 813         return 0x0f71;
 814     case 6: /* Auto-neg Expansion */
 815         return 1;
 816         /* TODO 17, 18, 27, 29, 30, 31 */
 817     case 29: /* Interrupt source.  */
 818         val = s->phy_int;
 819         s->phy_int = 0;
 820         phy_update_irq(s);
 821         return val;
 822     case 30: /* Interrupt mask */
 823         return s->phy_int_mask;
 824     default:
 825         BADF("PHY read reg %d\n", reg);
 826         return 0;
 827     }
 828 }
 829
 830 static void do_phy_write(lan9118_state *s, int reg, uint32_t val)
 831 {
 832     switch (reg) {
 833     case 0: /* Basic Control */
 834         if (val & 0x8000) {
 835             phy_reset(s);
 836             break;
 837         }
 838         s->phy_control = val & 0x7980;
 839         /* Complete autonegotiation immediately.  */
 840         if (val & 0x1000) {
 841             s->phy_status |= 0x0020;
 842         }
 843         break;
 844     case 4: /* Auto-neg advertisement */
 845         s->phy_advertise = (val & 0x2d7f) | 0x80;
 846         break;
 847         /* TODO 17, 18, 27, 31 */
 848     case 30: /* Interrupt mask */
 849         s->phy_int_mask = val & 0xff;
 850         phy_update_irq(s);
 851         break;
 852     default:
 853         BADF("PHY write reg %d = 0x%04x\n", reg, val);
 854     }
 855 }
 856
 857 static void do_mac_write(lan9118_state *s, int reg, uint32_t val)
 858 {
 859     switch (reg) {
 860     case MAC_CR:
 861         if ((s->mac_cr & MAC_CR_RXEN) != 0 && (val & MAC_CR_RXEN) == 0) {
 862             s->int_sts |= RXSTOP_INT;
 863         }
 864         s->mac_cr = val & ~MAC_CR_RESERVED;
 865         DPRINTF("MAC_CR: %08x\n", val);
 866         break;
 867     case MAC_ADDRH:
 868         s->conf.macaddr.a[4] = val & 0xff;
 869         s->conf.macaddr.a[5] = (val >> 8) & 0xff;
 870         lan9118_mac_changed(s);
 871         break;
 872     case MAC_ADDRL:
 873         s->conf.macaddr.a[0] = val & 0xff;
 874         s->conf.macaddr.a[1] = (val >> 8) & 0xff;
 875         s->conf.macaddr.a[2] = (val >> 16) & 0xff;
 876         s->conf.macaddr.a[3] = (val >> 24) & 0xff;
 877         lan9118_mac_changed(s);
 878         break;
 879     case MAC_HASHH:
 880         s->mac_hashh = val;
 881         break;
 882     case MAC_HASHL:
 883         s->mac_hashl = val;
 884         break;
 885     case MAC_MII_ACC:
 886         s->mac_mii_acc = val & 0xffc2;
 887         if (val & 2) {
 888             DPRINTF("PHY write %d = 0x%04x\n",
 889                     (val >> 6) & 0x1f, s->mac_mii_data);
 890             do_phy_write(s, (val >> 6) & 0x1f, s->mac_mii_data);
 891         } else {
 892             s->mac_mii_data = do_phy_read(s, (val >> 6) & 0x1f);
 893             DPRINTF("PHY read %d = 0x%04x\n",
 894                     (val >> 6) & 0x1f, s->mac_mii_data);
 895         }
 896         break;
 897     case MAC_MII_DATA:
 898         s->mac_mii_data = val & 0xffff;
 899         break;
 900     case MAC_FLOW:
 901         s->mac_flow = val & 0xffff0000;
 902         break;
 903     case MAC_VLAN1:
 904         /* Writing to this register changes a condition for
 905          * FrameTooLong bit in rx_status.  Since we do not set
 906          * FrameTooLong anyway, just ignore write to this.
 907          */
 908         break;
 909     default:
 910         qemu_log_mask(LOG_GUEST_ERROR,
 911                       "lan9118: Unimplemented MAC register write: %d = 0x%x\n",
 912                  s->mac_cmd & 0xf, val);
 913     }
 914 }
 915
 916 static uint32_t do_mac_read(lan9118_state *s, int reg)
 917 {
 918     switch (reg) {
 919     case MAC_CR:
 920         return s->mac_cr;
 921     case MAC_ADDRH:
 922         return s->conf.macaddr.a[4] | (s->conf.macaddr.a[5] << 8);
 923     case MAC_ADDRL:
 924         return s->conf.macaddr.a[0] | (s->conf.macaddr.a[1] << 8)
 925                | (s->conf.macaddr.a[2] << 16) | (s->conf.macaddr.a[3] << 24);
 926     case MAC_HASHH:
 927         return s->mac_hashh;
 928         break;
 929     case MAC_HASHL:
 930         return s->mac_hashl;
 931         break;
 932     case MAC_MII_ACC:
 933         return s->mac_mii_acc;
 934     case MAC_MII_DATA:
 935         return s->mac_mii_data;
 936     case MAC_FLOW:
 937         return s->mac_flow;
 938     default:
 939         qemu_log_mask(LOG_GUEST_ERROR,
 940                       "lan9118: Unimplemented MAC register read: %d\n",
 941                  s->mac_cmd & 0xf);
 942         return 0;
 943     }
 944 }
 945
 946 static void lan9118_eeprom_cmd(lan9118_state *s, int cmd, int addr)
 947 {
 948     s->e2p_cmd = (s->e2p_cmd & E2P_CMD_MAC_ADDR_LOADED) | (cmd << 28) | addr;
 949     switch (cmd) {
 950     case 0:
 951         s->e2p_data = s->eeprom[addr];
 952         DPRINTF("EEPROM Read %d = 0x%02x\n", addr, s->e2p_data);
 953         break;
 954     case 1:
 955         s->eeprom_writable = 0;
 956         DPRINTF("EEPROM Write Disable\n");
 957         break;
 958     case 2: /* EWEN */
 959         s->eeprom_writable = 1;
 960         DPRINTF("EEPROM Write Enable\n");
 961         break;
 962     case 3: /* WRITE */
 963         if (s->eeprom_writable) {
 964             s->eeprom[addr] &= s->e2p_data;
 965             DPRINTF("EEPROM Write %d = 0x%02x\n", addr, s->e2p_data);
 966         } else {
 967             DPRINTF("EEPROM Write %d (ignored)\n", addr);
 968         }
 969         break;
 970     case 4: /* WRAL */
 971         if (s->eeprom_writable) {
 972             for (addr = 0; addr < 128; addr++) {
 973                 s->eeprom[addr] &= s->e2p_data;
 974             }
 975             DPRINTF("EEPROM Write All 0x%02x\n", s->e2p_data);
 976         } else {
 977             DPRINTF("EEPROM Write All (ignored)\n");
 978         }
 979         break;
 980     case 5: /* ERASE */
 981         if (s->eeprom_writable) {
 982             s->eeprom[addr] = 0xff;
 983             DPRINTF("EEPROM Erase %d\n", addr);
 984         } else {
 985             DPRINTF("EEPROM Erase %d (ignored)\n", addr);
 986         }
 987         break;
 988     case 6: /* ERAL */
 989         if (s->eeprom_writable) {
 990             memset(s->eeprom, 0xff, 128);
 991             DPRINTF("EEPROM Erase All\n");
 992         } else {
 993             DPRINTF("EEPROM Erase All (ignored)\n");
 994         }
 995         break;
 996     case 7: /* RELOAD */
 997         lan9118_reload_eeprom(s);
 998         break;
 999     }
1000 }
1001
1002 static void lan9118_tick(void *opaque)
1003 {
1004     lan9118_state *s = (lan9118_state *)opaque;
1005     if (s->int_en & GPT_INT) {
1006         s->int_sts |= GPT_INT;
1007     }
1008     lan9118_update(s);
1009 }
1010
1011 static void lan9118_writel(void *opaque, hwaddr offset,
1012                            uint64_t val, unsigned size)
1013 {
1014     lan9118_state *s = (lan9118_state *)opaque;
1015     offset &= 0xff;
1016
1017     //DPRINTF("Write reg 0x%02x = 0x%08x\n", (int)offset, val);
1018     if (offset >= 0x20 && offset < 0x40) {
1019         /* TX FIFO */
1020         tx_fifo_push(s, val);
1021         return;
1022     }
1023     switch (offset) {
1024     case CSR_IRQ_CFG:
1025         /* TODO: Implement interrupt deassertion intervals.  */
1026         val &= (IRQ_EN | IRQ_POL | IRQ_TYPE);
1027         s->irq_cfg = (s->irq_cfg & IRQ_INT) | val;
1028         break;
1029     case CSR_INT_STS:
1030         s->int_sts &= ~val;
1031         break;
1032     case CSR_INT_EN:
1033         s->int_en = val & ~RESERVED_INT;
1034         s->int_sts |= val & SW_INT;
1035         break;
1036     case CSR_FIFO_INT:
1037         DPRINTF("FIFO INT levels %08x\n", val);
1038         s->fifo_int = val;
1039         break;
1040     case CSR_RX_CFG:
1041         if (val & 0x8000) {
1042             /* RX_DUMP */
1043             s->rx_fifo_used = 0;
1044             s->rx_status_fifo_used = 0;
1045             s->rx_packet_size_tail = s->rx_packet_size_head;
1046             s->rx_packet_size[s->rx_packet_size_head] = 0;
1047         }
1048         s->rx_cfg = val & 0xcfff1ff0;
1049         break;
1050     case CSR_TX_CFG:
1051         if (val & 0x8000) {
1052             s->tx_status_fifo_used = 0;
1053         }
1054         if (val & 0x4000) {
1055             s->txp->state = TX_IDLE;
1056             s->txp->fifo_used = 0;
1057             s->txp->cmd_a = 0xffffffff;
1058         }
1059         s->tx_cfg = val & 6;
1060         break;
1061     case CSR_HW_CFG:
1062         if (val & 1) {
1063             /* SRST */
1064             lan9118_reset(DEVICE(s));
1065         } else {
1066             s->hw_cfg = (val & 0x003f300) | (s->hw_cfg & 0x4);
1067         }
1068         break;
1069     case CSR_RX_DP_CTRL:
1070         if (val & 0x80000000) {
1071             /* Skip forward to next packet.  */
1072             s->rxp_pad = 0;
1073             s->rxp_offset = 0;
1074             if (s->rxp_size == 0) {
1075                 /* Pop a word to start the next packet.  */
1076                 rx_fifo_pop(s);
1077                 s->rxp_pad = 0;
1078                 s->rxp_offset = 0;
1079             }
1080             s->rx_fifo_head += s->rxp_size;
1081             if (s->rx_fifo_head >= s->rx_fifo_size) {
1082                 s->rx_fifo_head -= s->rx_fifo_size;
1083             }
1084         }
1085         break;
1086     case CSR_PMT_CTRL:
1087         if (val & 0x400) {
1088             phy_reset(s);
1089         }
1090         s->pmt_ctrl &= ~0x34e;
1091         s->pmt_ctrl |= (val & 0x34e);
1092         break;
1093     case CSR_GPIO_CFG:
1094         /* Probably just enabling LEDs.  */
1095         s->gpio_cfg = val & 0x7777071f;
1096         break;
1097     case CSR_GPT_CFG:
1098         if ((s->gpt_cfg ^ val) & GPT_TIMER_EN) {
1099             if (val & GPT_TIMER_EN) {
1100                 ptimer_set_count(s->timer, val & 0xffff);
1101                 ptimer_run(s->timer, 0);
1102             } else {
1103                 ptimer_stop(s->timer);
1104                 ptimer_set_count(s->timer, 0xffff);
1105             }
1106         }
1107         s->gpt_cfg = val & (GPT_TIMER_EN | 0xffff);
1108         break;
1109     case CSR_WORD_SWAP:
1110         /* Ignored because we're in 32-bit mode.  */
1111         s->word_swap = val;
1112         break;
1113     case CSR_MAC_CSR_CMD:
1114         s->mac_cmd = val & 0x4000000f;
1115         if (val & 0x80000000) {
1116             if (val & 0x40000000) {
1117                 s->mac_data = do_mac_read(s, val & 0xf);
1118                 DPRINTF("MAC read %d = 0x%08x\n", val & 0xf, s->mac_data);
1119             } else {
1120                 DPRINTF("MAC write %d = 0x%08x\n", val & 0xf, s->mac_data);
1121                 do_mac_write(s, val & 0xf, s->mac_data);
1122             }
1123         }
1124         break;
1125     case CSR_MAC_CSR_DATA:
1126         s->mac_data = val;
1127         break;
1128     case CSR_AFC_CFG:
1129         s->afc_cfg = val & 0x00ffffff;
1130         break;
1131     case CSR_E2P_CMD:
1132         lan9118_eeprom_cmd(s, (val >> 28) & 7, val & 0x7f);
1133         break;
1134     case CSR_E2P_DATA:
1135         s->e2p_data = val & 0xff;
1136         break;
1137
1138     default:
1139         qemu_log_mask(LOG_GUEST_ERROR, "lan9118_write: Bad reg 0x%x = %x\n",
1140                       (int)offset, (int)val);
1141         break;
1142     }
1143     lan9118_update(s);
1144 }
1145
1146 static void lan9118_writew(void *opaque, hwaddr offset,
1147                            uint32_t val)
1148 {
1149     lan9118_state *s = (lan9118_state *)opaque;
1150     offset &= 0xff;
1151
1152     if (s->write_word_prev_offset != (offset & ~0x3)) {
1153         /* New offset, reset word counter */
1154         s->write_word_n = 0;
1155         s->write_word_prev_offset = offset & ~0x3;
1156     }
1157
1158     if (offset & 0x2) {
1159         s->write_word_h = val;
1160     } else {
1161         s->write_word_l = val;
1162     }
1163
1164     //DPRINTF("Writew reg 0x%02x = 0x%08x\n", (int)offset, val);
1165     s->write_word_n++;
1166     if (s->write_word_n == 2) {
1167         s->write_word_n = 0;
1168         lan9118_writel(s, offset & ~3, s->write_word_l +
1169                 (s->write_word_h << 16), 4);
1170     }
1171 }
1172
1173 static void lan9118_16bit_mode_write(void *opaque, hwaddr offset,
1174                                      uint64_t val, unsigned size)
1175 {
1176     switch (size) {
1177     case 2:
1178         lan9118_writew(opaque, offset, (uint32_t)val);
1179         return;
1180     case 4:
1181         lan9118_writel(opaque, offset, val, size);
1182         return;
1183     }
1184
1185     hw_error("lan9118_write: Bad size 0x%x\n", size);
1186 }
1187
1188 static uint64_t lan9118_readl(void *opaque, hwaddr offset,
1189                               unsigned size)
1190 {
1191     lan9118_state *s = (lan9118_state *)opaque;
1192
1193     //DPRINTF("Read reg 0x%02x\n", (int)offset);
1194     if (offset < 0x20) {
1195         /* RX FIFO */
1196         return rx_fifo_pop(s);
1197     }
1198     switch (offset) {
1199     case 0x40:
1200         return rx_status_fifo_pop(s);
1201     case 0x44:
1202         return s->rx_status_fifo[s->tx_status_fifo_head];
1203     case 0x48:
1204         return tx_status_fifo_pop(s);
1205     case 0x4c:
1206         return s->tx_status_fifo[s->tx_status_fifo_head];
1207     case CSR_ID_REV:
1208         return 0x01180001;
1209     case CSR_IRQ_CFG:
1210         return s->irq_cfg;
1211     case CSR_INT_STS:
1212         return s->int_sts;
1213     case CSR_INT_EN:
1214         return s->int_en;
1215     case CSR_BYTE_TEST:
1216         return 0x87654321;
1217     case CSR_FIFO_INT:
1218         return s->fifo_int;
1219     case CSR_RX_CFG:
1220         return s->rx_cfg;
1221     case CSR_TX_CFG:
1222         return s->tx_cfg;
1223     case CSR_HW_CFG:
1224         return s->hw_cfg;
1225     case CSR_RX_DP_CTRL:
1226         return 0;
1227     case CSR_RX_FIFO_INF:
1228         return (s->rx_status_fifo_used << 16) | (s->rx_fifo_used << 2);
1229     case CSR_TX_FIFO_INF:
1230         return (s->tx_status_fifo_used << 16)
1231                | (s->tx_fifo_size - s->txp->fifo_used);
1232     case CSR_PMT_CTRL:
1233         return s->pmt_ctrl;
1234     case CSR_GPIO_CFG:
1235         return s->gpio_cfg;
1236     case CSR_GPT_CFG:
1237         return s->gpt_cfg;
1238     case CSR_GPT_CNT:
1239         return ptimer_get_count(s->timer);
1240     case CSR_WORD_SWAP:
1241         return s->word_swap;
1242     case CSR_FREE_RUN:
1243         return (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / 40) - s->free_timer_start;
1244     case CSR_RX_DROP:
1245         /* TODO: Implement dropped frames counter.  */
1246         return 0;
1247     case CSR_MAC_CSR_CMD:
1248         return s->mac_cmd;
1249     case CSR_MAC_CSR_DATA:
1250         return s->mac_data;
1251     case CSR_AFC_CFG:
1252         return s->afc_cfg;
1253     case CSR_E2P_CMD:
1254         return s->e2p_cmd;
1255     case CSR_E2P_DATA:
1256         return s->e2p_data;
1257     }
1258     qemu_log_mask(LOG_GUEST_ERROR, "lan9118_read: Bad reg 0x%x\n", (int)offset);
1259     return 0;
1260 }
1261
1262 static uint32_t lan9118_readw(void *opaque, hwaddr offset)
1263 {
1264     lan9118_state *s = (lan9118_state *)opaque;
1265     uint32_t val;
1266
1267     if (s->read_word_prev_offset != (offset & ~0x3)) {
1268         /* New offset, reset word counter */
1269         s->read_word_n = 0;
1270         s->read_word_prev_offset = offset & ~0x3;
1271     }
1272
1273     s->read_word_n++;
1274     if (s->read_word_n == 1) {
1275         s->read_long = lan9118_readl(s, offset & ~3, 4);
1276     } else {
1277         s->read_word_n = 0;
1278     }
1279
1280     if (offset & 2) {
1281         val = s->read_long >> 16;
1282     } else {
1283         val = s->read_long & 0xFFFF;
1284     }
1285
1286     //DPRINTF("Readw reg 0x%02x, val 0x%x\n", (int)offset, val);
1287     return val;
1288 }
1289
1290 static uint64_t lan9118_16bit_mode_read(void *opaque, hwaddr offset,
1291                                         unsigned size)
1292 {
1293     switch (size) {
1294     case 2:
1295         return lan9118_readw(opaque, offset);
1296     case 4:
1297         return lan9118_readl(opaque, offset, size);
1298     }
1299
1300     hw_error("lan9118_read: Bad size 0x%x\n", size);
1301     return 0;
1302 }
1303
1304 static const MemoryRegionOps lan9118_mem_ops = {
1305     .read = lan9118_readl,
1306     .write = lan9118_writel,
1307     .endianness = DEVICE_NATIVE_ENDIAN,
1308 };
1309
1310 static const MemoryRegionOps lan9118_16bit_mem_ops = {
1311     .read = lan9118_16bit_mode_read,
1312     .write = lan9118_16bit_mode_write,
1313     .endianness = DEVICE_NATIVE_ENDIAN,
1314 };
1315
1316 static NetClientInfo net_lan9118_info = {
1317     .type = NET_CLIENT_DRIVER_NIC,
1318     .size = sizeof(NICState),
1319     .receive = lan9118_receive,
1320     .link_status_changed = lan9118_set_link,
1321 };
1322
1323 static int lan9118_init1(SysBusDevice *sbd)
1324 {
1325     DeviceState *dev = DEVICE(sbd);
1326     lan9118_state *s = LAN9118(dev);
1327     QEMUBH *bh;
1328     int i;
1329     const MemoryRegionOps *mem_ops =
1330             s->mode_16bit ? &lan9118_16bit_mem_ops : &lan9118_mem_ops;
1331
1332     memory_region_init_io(&s->mmio, OBJECT(dev), mem_ops, s,
1333                           "lan9118-mmio", 0x100);
1334     sysbus_init_mmio(sbd, &s->mmio);
1335     sysbus_init_irq(sbd, &s->irq);
1336     qemu_macaddr_default_if_unset(&s->conf.macaddr);
1337
1338     s->nic = qemu_new_nic(&net_lan9118_info, &s->conf,
1339                           object_get_typename(OBJECT(dev)), dev->id, s);
1340     qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
1341     s->eeprom[0] = 0xa5;
1342     for (i = 0; i < 6; i++) {
1343         s->eeprom[i + 1] = s->conf.macaddr.a[i];
1344     }
1345     s->pmt_ctrl = 1;
1346     s->txp = &s->tx_packet;
1347
1348     bh = qemu_bh_new(lan9118_tick, s);
1349     s->timer = ptimer_init(bh, PTIMER_POLICY_DEFAULT);
1350     ptimer_set_freq(s->timer, 10000);
1351     ptimer_set_limit(s->timer, 0xffff, 1);
1352
1353     return 0;
1354 }
1355
1356 static Property lan9118_properties[] = {
1357     DEFINE_NIC_PROPERTIES(lan9118_state, conf),
1358     DEFINE_PROP_UINT32("mode_16bit", lan9118_state, mode_16bit, 0),
1359     DEFINE_PROP_END_OF_LIST(),
1360 };
1361
1362 static void lan9118_class_init(ObjectClass *klass, void *data)
1363 {
1364     DeviceClass *dc = DEVICE_CLASS(klass);
1365     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
1366
1367     k->init = lan9118_init1;
1368     dc->reset = lan9118_reset;
1369     dc->props = lan9118_properties;
1370     dc->vmsd = &vmstate_lan9118;
1371 }
1372
1373 static const TypeInfo lan9118_info = {
1374     .name          = TYPE_LAN9118,
1375     .parent        = TYPE_SYS_BUS_DEVICE,
1376     .instance_size = sizeof(lan9118_state),
1377     .class_init    = lan9118_class_init,
1378 };
1379
1380 static void lan9118_register_types(void)
1381 {
1382     type_register_static(&lan9118_info);
1383 }
1384
1385 /* Legacy helper function.  Should go away when machine config files are
1386    implemented.  */
1387 void lan9118_init(NICInfo *nd, uint32_t base, qemu_irq irq)
1388 {
1389     DeviceState *dev;
1390     SysBusDevice *s;
1391
1392     qemu_check_nic_model(nd, "lan9118");
1393     dev = qdev_create(NULL, TYPE_LAN9118);
1394     qdev_set_nic_properties(dev, nd);
1395     qdev_init_nofail(dev);
1396     s = SYS_BUS_DEVICE(dev);
1397     sysbus_mmio_map(s, 0, base);
1398     sysbus_connect_irq(s, 0, irq);
1399 }
1400
1401 type_init(lan9118_register_types)