hw/pxa2xx_timer.c

   1 /*
   2  * Intel XScale PXA255/270 OS Timers.
   3  *
   4  * Copyright (c) 2006 Openedhand Ltd.
   5  * Copyright (c) 2006 Thorsten Zitterell
   6  *
   7  * This code is licenced under the GPL.
   8  */
   9
  10 #include "hw.h"
  11 #include "qemu-timer.h"
  12 #include "sysemu.h"
  13 #include "pxa.h"
  14 #include "sysbus.h"
  15
  16 #define OSMR0   0x00
  17 #define OSMR1   0x04
  18 #define OSMR2   0x08
  19 #define OSMR3   0x0c
  20 #define OSMR4   0x80
  21 #define OSMR5   0x84
  22 #define OSMR6   0x88
  23 #define OSMR7   0x8c
  24 #define OSMR8   0x90
  25 #define OSMR9   0x94
  26 #define OSMR10  0x98
  27 #define OSMR11  0x9c
  28 #define OSCR    0x10    /* OS Timer Count */
  29 #define OSCR4   0x40
  30 #define OSCR5   0x44
  31 #define OSCR6   0x48
  32 #define OSCR7   0x4c
  33 #define OSCR8   0x50
  34 #define OSCR9   0x54
  35 #define OSCR10  0x58
  36 #define OSCR11  0x5c
  37 #define OSSR    0x14    /* Timer status register */
  38 #define OWER    0x18
  39 #define OIER    0x1c    /* Interrupt enable register  3-0 to E3-E0 */
  40 #define OMCR4   0xc0    /* OS Match Control registers */
  41 #define OMCR5   0xc4
  42 #define OMCR6   0xc8
  43 #define OMCR7   0xcc
  44 #define OMCR8   0xd0
  45 #define OMCR9   0xd4
  46 #define OMCR10  0xd8
  47 #define OMCR11  0xdc
  48 #define OSNR    0x20
  49
  50 #define PXA25X_FREQ     3686400 /* 3.6864 MHz */
  51 #define PXA27X_FREQ     3250000 /* 3.25 MHz */
  52
  53 static int pxa2xx_timer4_freq[8] = {
  54     [0] = 0,
  55     [1] = 32768,
  56     [2] = 1000,
  57     [3] = 1,
  58     [4] = 1000000,
  59     /* [5] is the "Externally supplied clock".  Assign if necessary.  */
  60     [5 ... 7] = 0,
  61 };
  62
  63 typedef struct PXA2xxTimerInfo PXA2xxTimerInfo;
  64
  65 typedef struct {
  66     uint32_t value;
  67     int level;
  68     qemu_irq irq;
  69     QEMUTimer *qtimer;
  70     int num;
  71     PXA2xxTimerInfo *info;
  72 } PXA2xxTimer0;
  73
  74 typedef struct {
  75     PXA2xxTimer0 tm;
  76     int32_t oldclock;
  77     int32_t clock;
  78     uint64_t lastload;
  79     uint32_t freq;
  80     uint32_t control;
  81 } PXA2xxTimer4;
  82
  83 struct PXA2xxTimerInfo {
  84     SysBusDevice busdev;
  85     uint32_t flags;
  86
  87     int32_t clock;
  88     int32_t oldclock;
  89     uint64_t lastload;
  90     uint32_t freq;
  91     PXA2xxTimer0 timer[4];
  92     uint32_t events;
  93     uint32_t irq_enabled;
  94     uint32_t reset3;
  95     uint32_t snapshot;
  96
  97     PXA2xxTimer4 tm4[8];
  98 };
  99
 100 #define PXA2XX_TIMER_HAVE_TM4   0
 101
 102 static inline int pxa2xx_timer_has_tm4(PXA2xxTimerInfo *s)
 103 {
 104     return s->flags & (1 << PXA2XX_TIMER_HAVE_TM4);
 105 }
 106
 107 static void pxa2xx_timer_update(void *opaque, uint64_t now_qemu)
 108 {
 109     PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
 110     int i;
 111     uint32_t now_vm;
 112     uint64_t new_qemu;
 113
 114     now_vm = s->clock +
 115             muldiv64(now_qemu - s->lastload, s->freq, get_ticks_per_sec());
 116
 117     for (i = 0; i < 4; i ++) {
 118         new_qemu = now_qemu + muldiv64((uint32_t) (s->timer[i].value - now_vm),
 119                         get_ticks_per_sec(), s->freq);
 120         qemu_mod_timer(s->timer[i].qtimer, new_qemu);
 121     }
 122 }
 123
 124 static void pxa2xx_timer_update4(void *opaque, uint64_t now_qemu, int n)
 125 {
 126     PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
 127     uint32_t now_vm;
 128     uint64_t new_qemu;
 129     static const int counters[8] = { 0, 0, 0, 0, 4, 4, 6, 6 };
 130     int counter;
 131
 132     if (s->tm4[n].control & (1 << 7))
 133         counter = n;
 134     else
 135         counter = counters[n];
 136
 137     if (!s->tm4[counter].freq) {
 138         qemu_del_timer(s->tm4[n].tm.qtimer);
 139         return;
 140     }
 141
 142     now_vm = s->tm4[counter].clock + muldiv64(now_qemu -
 143                     s->tm4[counter].lastload,
 144                     s->tm4[counter].freq, get_ticks_per_sec());
 145
 146     new_qemu = now_qemu + muldiv64((uint32_t) (s->tm4[n].tm.value - now_vm),
 147                     get_ticks_per_sec(), s->tm4[counter].freq);
 148     qemu_mod_timer(s->tm4[n].tm.qtimer, new_qemu);
 149 }
 150
 151 static uint32_t pxa2xx_timer_read(void *opaque, target_phys_addr_t offset)
 152 {
 153     PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
 154     int tm = 0;
 155
 156     switch (offset) {
 157     case OSMR3:  tm ++;
 158     case OSMR2:  tm ++;
 159     case OSMR1:  tm ++;
 160     case OSMR0:
 161         return s->timer[tm].value;
 162     case OSMR11: tm ++;
 163     case OSMR10: tm ++;
 164     case OSMR9:  tm ++;
 165     case OSMR8:  tm ++;
 166     case OSMR7:  tm ++;
 167     case OSMR6:  tm ++;
 168     case OSMR5:  tm ++;
 169     case OSMR4:
 170         if (!pxa2xx_timer_has_tm4(s))
 171             goto badreg;
 172         return s->tm4[tm].tm.value;
 173     case OSCR:
 174         return s->clock + muldiv64(qemu_get_clock(vm_clock) -
 175                         s->lastload, s->freq, get_ticks_per_sec());
 176     case OSCR11: tm ++;
 177     case OSCR10: tm ++;
 178     case OSCR9:  tm ++;
 179     case OSCR8:  tm ++;
 180     case OSCR7:  tm ++;
 181     case OSCR6:  tm ++;
 182     case OSCR5:  tm ++;
 183     case OSCR4:
 184         if (!pxa2xx_timer_has_tm4(s))
 185             goto badreg;
 186
 187         if ((tm == 9 - 4 || tm == 11 - 4) && (s->tm4[tm].control & (1 << 9))) {
 188             if (s->tm4[tm - 1].freq)
 189                 s->snapshot = s->tm4[tm - 1].clock + muldiv64(
 190                                 qemu_get_clock(vm_clock) -
 191                                 s->tm4[tm - 1].lastload,
 192                                 s->tm4[tm - 1].freq, get_ticks_per_sec());
 193             else
 194                 s->snapshot = s->tm4[tm - 1].clock;
 195         }
 196
 197         if (!s->tm4[tm].freq)
 198             return s->tm4[tm].clock;
 199         return s->tm4[tm].clock + muldiv64(qemu_get_clock(vm_clock) -
 200                         s->tm4[tm].lastload, s->tm4[tm].freq, get_ticks_per_sec());
 201     case OIER:
 202         return s->irq_enabled;
 203     case OSSR:  /* Status register */
 204         return s->events;
 205     case OWER:
 206         return s->reset3;
 207     case OMCR11: tm ++;
 208     case OMCR10: tm ++;
 209     case OMCR9:  tm ++;
 210     case OMCR8:  tm ++;
 211     case OMCR7:  tm ++;
 212     case OMCR6:  tm ++;
 213     case OMCR5:  tm ++;
 214     case OMCR4:
 215         if (!pxa2xx_timer_has_tm4(s))
 216             goto badreg;
 217         return s->tm4[tm].control;
 218     case OSNR:
 219         return s->snapshot;
 220     default:
 221     badreg:
 222         hw_error("pxa2xx_timer_read: Bad offset " REG_FMT "\n", offset);
 223     }
 224
 225     return 0;
 226 }
 227
 228 static void pxa2xx_timer_write(void *opaque, target_phys_addr_t offset,
 229                 uint32_t value)
 230 {
 231     int i, tm = 0;
 232     PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
 233
 234     switch (offset) {
 235     case OSMR3:  tm ++;
 236     case OSMR2:  tm ++;
 237     case OSMR1:  tm ++;
 238     case OSMR0:
 239         s->timer[tm].value = value;
 240         pxa2xx_timer_update(s, qemu_get_clock(vm_clock));
 241         break;
 242     case OSMR11: tm ++;
 243     case OSMR10: tm ++;
 244     case OSMR9:  tm ++;
 245     case OSMR8:  tm ++;
 246     case OSMR7:  tm ++;
 247     case OSMR6:  tm ++;
 248     case OSMR5:  tm ++;
 249     case OSMR4:
 250         if (!pxa2xx_timer_has_tm4(s))
 251             goto badreg;
 252         s->tm4[tm].tm.value = value;
 253         pxa2xx_timer_update4(s, qemu_get_clock(vm_clock), tm);
 254         break;
 255     case OSCR:
 256         s->oldclock = s->clock;
 257         s->lastload = qemu_get_clock(vm_clock);
 258         s->clock = value;
 259         pxa2xx_timer_update(s, s->lastload);
 260         break;
 261     case OSCR11: tm ++;
 262     case OSCR10: tm ++;
 263     case OSCR9:  tm ++;
 264     case OSCR8:  tm ++;
 265     case OSCR7:  tm ++;
 266     case OSCR6:  tm ++;
 267     case OSCR5:  tm ++;
 268     case OSCR4:
 269         if (!pxa2xx_timer_has_tm4(s))
 270             goto badreg;
 271         s->tm4[tm].oldclock = s->tm4[tm].clock;
 272         s->tm4[tm].lastload = qemu_get_clock(vm_clock);
 273         s->tm4[tm].clock = value;
 274         pxa2xx_timer_update4(s, s->tm4[tm].lastload, tm);
 275         break;
 276     case OIER:
 277         s->irq_enabled = value & 0xfff;
 278         break;
 279     case OSSR:  /* Status register */
 280         s->events &= ~value;
 281         for (i = 0; i < 4; i ++, value >>= 1) {
 282             if (s->timer[i].level && (value & 1)) {
 283                 s->timer[i].level = 0;
 284                 qemu_irq_lower(s->timer[i].irq);
 285             }
 286         }
 287         if (pxa2xx_timer_has_tm4(s)) {
 288             for (i = 0; i < 8; i ++, value >>= 1)
 289                 if (s->tm4[i].tm.level && (value & 1))
 290                     s->tm4[i].tm.level = 0;
 291             if (!(s->events & 0xff0))
 292                 qemu_irq_lower(s->tm4->tm.irq);
 293         }
 294         break;
 295     case OWER:  /* XXX: Reset on OSMR3 match? */
 296         s->reset3 = value;
 297         break;
 298     case OMCR7:  tm ++;
 299     case OMCR6:  tm ++;
 300     case OMCR5:  tm ++;
 301     case OMCR4:
 302         if (!pxa2xx_timer_has_tm4(s))
 303             goto badreg;
 304         s->tm4[tm].control = value & 0x0ff;
 305         /* XXX Stop if running (shouldn't happen) */
 306         if ((value & (1 << 7)) || tm == 0)
 307             s->tm4[tm].freq = pxa2xx_timer4_freq[value & 7];
 308         else {
 309             s->tm4[tm].freq = 0;
 310             pxa2xx_timer_update4(s, qemu_get_clock(vm_clock), tm);
 311         }
 312         break;
 313     case OMCR11: tm ++;
 314     case OMCR10: tm ++;
 315     case OMCR9:  tm ++;
 316     case OMCR8:  tm += 4;
 317         if (!pxa2xx_timer_has_tm4(s))
 318             goto badreg;
 319         s->tm4[tm].control = value & 0x3ff;
 320         /* XXX Stop if running (shouldn't happen) */
 321         if ((value & (1 << 7)) || !(tm & 1))
 322             s->tm4[tm].freq =
 323                     pxa2xx_timer4_freq[(value & (1 << 8)) ?  0 : (value & 7)];
 324         else {
 325             s->tm4[tm].freq = 0;
 326             pxa2xx_timer_update4(s, qemu_get_clock(vm_clock), tm);
 327         }
 328         break;
 329     default:
 330     badreg:
 331         hw_error("pxa2xx_timer_write: Bad offset " REG_FMT "\n", offset);
 332     }
 333 }
 334
 335 static CPUReadMemoryFunc * const pxa2xx_timer_readfn[] = {
 336     pxa2xx_timer_read,
 337     pxa2xx_timer_read,
 338     pxa2xx_timer_read,
 339 };
 340
 341 static CPUWriteMemoryFunc * const pxa2xx_timer_writefn[] = {
 342     pxa2xx_timer_write,
 343     pxa2xx_timer_write,
 344     pxa2xx_timer_write,
 345 };
 346
 347 static void pxa2xx_timer_tick(void *opaque)
 348 {
 349     PXA2xxTimer0 *t = (PXA2xxTimer0 *) opaque;
 350     PXA2xxTimerInfo *i = t->info;
 351
 352     if (i->irq_enabled & (1 << t->num)) {
 353         t->level = 1;
 354         i->events |= 1 << t->num;
 355         qemu_irq_raise(t->irq);
 356     }
 357
 358     if (t->num == 3)
 359         if (i->reset3 & 1) {
 360             i->reset3 = 0;
 361             qemu_system_reset_request();
 362         }
 363 }
 364
 365 static void pxa2xx_timer_tick4(void *opaque)
 366 {
 367     PXA2xxTimer4 *t = (PXA2xxTimer4 *) opaque;
 368     PXA2xxTimerInfo *i = (PXA2xxTimerInfo *) t->tm.info;
 369
 370     pxa2xx_timer_tick(&t->tm);
 371     if (t->control & (1 << 3))
 372         t->clock = 0;
 373     if (t->control & (1 << 6))
 374         pxa2xx_timer_update4(i, qemu_get_clock(vm_clock), t->tm.num - 4);
 375 }
 376
 377 static int pxa25x_timer_post_load(void *opaque, int version_id)
 378 {
 379     PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
 380     int64_t now;
 381     int i;
 382
 383     now = qemu_get_clock(vm_clock);
 384     pxa2xx_timer_update(s, now);
 385
 386     if (pxa2xx_timer_has_tm4(s))
 387         for (i = 0; i < 8; i ++)
 388             pxa2xx_timer_update4(s, now, i);
 389
 390     return 0;
 391 }
 392
 393 static int pxa2xx_timer_init(SysBusDevice *dev)
 394 {
 395     int i;
 396     int iomemtype;
 397     PXA2xxTimerInfo *s;
 398     qemu_irq irq4;
 399
 400     s = FROM_SYSBUS(PXA2xxTimerInfo, dev);
 401     s->irq_enabled = 0;
 402     s->oldclock = 0;
 403     s->clock = 0;
 404     s->lastload = qemu_get_clock(vm_clock);
 405     s->reset3 = 0;
 406
 407     for (i = 0; i < 4; i ++) {
 408         s->timer[i].value = 0;
 409         sysbus_init_irq(dev, &s->timer[i].irq);
 410         s->timer[i].info = s;
 411         s->timer[i].num = i;
 412         s->timer[i].level = 0;
 413         s->timer[i].qtimer = qemu_new_timer(vm_clock,
 414                         pxa2xx_timer_tick, &s->timer[i]);
 415     }
 416     if (s->flags & (1 << PXA2XX_TIMER_HAVE_TM4)) {
 417         sysbus_init_irq(dev, &irq4);
 418
 419         for (i = 0; i < 8; i ++) {
 420             s->tm4[i].tm.value = 0;
 421             s->tm4[i].tm.info = s;
 422             s->tm4[i].tm.num = i + 4;
 423             s->tm4[i].tm.level = 0;
 424             s->tm4[i].freq = 0;
 425             s->tm4[i].control = 0x0;
 426             s->tm4[i].tm.qtimer = qemu_new_timer(vm_clock,
 427                         pxa2xx_timer_tick4, &s->tm4[i]);
 428             s->tm4[i].tm.irq = irq4;
 429         }
 430     }
 431
 432     iomemtype = cpu_register_io_memory(pxa2xx_timer_readfn,
 433                     pxa2xx_timer_writefn, s, DEVICE_NATIVE_ENDIAN);
 434     sysbus_init_mmio(dev, 0x00001000, iomemtype);
 435
 436     return 0;
 437 }
 438
 439 static const VMStateDescription vmstate_pxa2xx_timer0_regs = {
 440     .name = "pxa2xx_timer0",
 441     .version_id = 1,
 442     .minimum_version_id = 1,
 443     .minimum_version_id_old = 1,
 444     .fields = (VMStateField[]) {
 445         VMSTATE_UINT32(value, PXA2xxTimer0),
 446         VMSTATE_INT32(level, PXA2xxTimer0),
 447         VMSTATE_END_OF_LIST(),
 448     },
 449 };
 450
 451 static const VMStateDescription vmstate_pxa2xx_timer4_regs = {
 452     .name = "pxa2xx_timer4",
 453     .version_id = 1,
 454     .minimum_version_id = 1,
 455     .minimum_version_id_old = 1,
 456     .fields = (VMStateField[]) {
 457         VMSTATE_STRUCT(tm, PXA2xxTimer4, 1,
 458                         vmstate_pxa2xx_timer0_regs, PXA2xxTimer0),
 459         VMSTATE_INT32(oldclock, PXA2xxTimer4),
 460         VMSTATE_INT32(clock, PXA2xxTimer4),
 461         VMSTATE_UINT64(lastload, PXA2xxTimer4),
 462         VMSTATE_UINT32(freq, PXA2xxTimer4),
 463         VMSTATE_UINT32(control, PXA2xxTimer4),
 464         VMSTATE_END_OF_LIST(),
 465     },
 466 };
 467
 468 static bool pxa2xx_timer_has_tm4_test(void *opaque, int version_id)
 469 {
 470     return pxa2xx_timer_has_tm4(opaque);
 471 }
 472
 473 static const VMStateDescription vmstate_pxa2xx_timer_regs = {
 474     .name = "pxa2xx_timer",
 475     .version_id = 1,
 476     .minimum_version_id = 1,
 477     .minimum_version_id_old = 1,
 478     .post_load = pxa25x_timer_post_load,
 479     .fields = (VMStateField[]) {
 480         VMSTATE_INT32(clock, PXA2xxTimerInfo),
 481         VMSTATE_INT32(oldclock, PXA2xxTimerInfo),
 482         VMSTATE_UINT64(lastload, PXA2xxTimerInfo),
 483         VMSTATE_STRUCT_ARRAY(timer, PXA2xxTimerInfo, 4, 1,
 484                         vmstate_pxa2xx_timer0_regs, PXA2xxTimer0),
 485         VMSTATE_UINT32(events, PXA2xxTimerInfo),
 486         VMSTATE_UINT32(irq_enabled, PXA2xxTimerInfo),
 487         VMSTATE_UINT32(reset3, PXA2xxTimerInfo),
 488         VMSTATE_UINT32(snapshot, PXA2xxTimerInfo),
 489         VMSTATE_STRUCT_ARRAY_TEST(tm4, PXA2xxTimerInfo, 8,
 490                         pxa2xx_timer_has_tm4_test, 0,
 491                         vmstate_pxa2xx_timer4_regs, PXA2xxTimer4),
 492         VMSTATE_END_OF_LIST(),
 493     }
 494 };
 495
 496 static SysBusDeviceInfo pxa25x_timer_dev_info = {
 497     .init       = pxa2xx_timer_init,
 498     .qdev.name  = "pxa25x-timer",
 499     .qdev.desc  = "PXA25x timer",
 500     .qdev.size  = sizeof(PXA2xxTimerInfo),
 501     .qdev.vmsd  = &vmstate_pxa2xx_timer_regs,
 502     .qdev.props = (Property[]) {
 503         DEFINE_PROP_UINT32("freq", PXA2xxTimerInfo, freq, PXA25X_FREQ),
 504         DEFINE_PROP_BIT("tm4", PXA2xxTimerInfo, flags,
 505                         PXA2XX_TIMER_HAVE_TM4, false),
 506         DEFINE_PROP_END_OF_LIST(),
 507     },
 508 };
 509
 510 static SysBusDeviceInfo pxa27x_timer_dev_info = {
 511     .init       = pxa2xx_timer_init,
 512     .qdev.name  = "pxa27x-timer",
 513     .qdev.desc  = "PXA27x timer",
 514     .qdev.size  = sizeof(PXA2xxTimerInfo),
 515     .qdev.vmsd  = &vmstate_pxa2xx_timer_regs,
 516     .qdev.props = (Property[]) {
 517         DEFINE_PROP_UINT32("freq", PXA2xxTimerInfo, freq, PXA27X_FREQ),
 518         DEFINE_PROP_BIT("tm4", PXA2xxTimerInfo, flags,
 519                         PXA2XX_TIMER_HAVE_TM4, true),
 520         DEFINE_PROP_END_OF_LIST(),
 521     },
 522 };
 523
 524 static void pxa2xx_timer_register(void)
 525 {
 526     sysbus_register_withprop(&pxa25x_timer_dev_info);
 527     sysbus_register_withprop(&pxa27x_timer_dev_info);
 528 };
 529 device_init(pxa2xx_timer_register);