2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
4 * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
6 * Copyright (c) 2010,2011 David Gibson, IBM Corporation.
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
32 #include "target/ppc/cpu-qom.h"
36 #define XICS_IRQ_BASE (XICS_BUID << 12)
39 * We currently only support one BUID which is our interrupt base
40 * (the kernel implementation supports more but we don't exploit
43 typedef struct ICPStateClass ICPStateClass
;
44 typedef struct ICPState ICPState
;
45 typedef struct PnvICPState PnvICPState
;
46 typedef struct ICSStateClass ICSStateClass
;
47 typedef struct ICSState ICSState
;
48 typedef struct ICSIRQState ICSIRQState
;
49 typedef struct XICSFabric XICSFabric
;
51 #define TYPE_ICP "icp"
52 #define ICP(obj) OBJECT_CHECK(ICPState, (obj), TYPE_ICP)
54 #define TYPE_KVM_ICP "icp-kvm"
55 #define KVM_ICP(obj) OBJECT_CHECK(ICPState, (obj), TYPE_KVM_ICP)
57 #define TYPE_PNV_ICP "pnv-icp"
58 #define PNV_ICP(obj) OBJECT_CHECK(PnvICPState, (obj), TYPE_PNV_ICP)
60 #define ICP_CLASS(klass) \
61 OBJECT_CLASS_CHECK(ICPStateClass, (klass), TYPE_ICP)
62 #define ICP_GET_CLASS(obj) \
63 OBJECT_GET_CLASS(ICPStateClass, (obj), TYPE_ICP)
65 struct ICPStateClass
{
66 DeviceClass parent_class
;
68 void (*realize
)(ICPState
*icp
, Error
**errp
);
69 void (*pre_save
)(ICPState
*icp
);
70 int (*post_load
)(ICPState
*icp
, int version_id
);
71 void (*reset
)(ICPState
*icp
);
76 DeviceState parent_obj
;
81 uint8_t pending_priority
;
88 #define ICP_PROP_XICS "xics"
89 #define ICP_PROP_CPU "cpu"
98 #define TYPE_ICS_BASE "ics-base"
99 #define ICS_BASE(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS_BASE)
101 /* Retain ics for sPAPR for migration from existing sPAPR guests */
102 #define TYPE_ICS_SIMPLE "ics"
103 #define ICS_SIMPLE(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS_SIMPLE)
105 #define TYPE_ICS_KVM "icskvm"
106 #define ICS_KVM(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS_KVM)
108 #define ICS_BASE_CLASS(klass) \
109 OBJECT_CLASS_CHECK(ICSStateClass, (klass), TYPE_ICS_BASE)
110 #define ICS_BASE_GET_CLASS(obj) \
111 OBJECT_GET_CLASS(ICSStateClass, (obj), TYPE_ICS_BASE)
113 struct ICSStateClass
{
114 DeviceClass parent_class
;
116 void (*realize
)(ICSState
*s
, Error
**errp
);
117 void (*pre_save
)(ICSState
*s
);
118 int (*post_load
)(ICSState
*s
, int version_id
);
119 void (*reject
)(ICSState
*s
, uint32_t irq
);
120 void (*resend
)(ICSState
*s
);
121 void (*eoi
)(ICSState
*s
, uint32_t irq
);
126 DeviceState parent_obj
;
135 #define ICS_PROP_XICS "xics"
137 static inline bool ics_valid_irq(ICSState
*ics
, uint32_t nr
)
139 return (ics
->offset
!= 0) && (nr
>= ics
->offset
)
140 && (nr
< (ics
->offset
+ ics
->nr_irqs
));
146 uint8_t saved_priority
;
147 #define XICS_STATUS_ASSERTED 0x1
148 #define XICS_STATUS_SENT 0x2
149 #define XICS_STATUS_REJECTED 0x4
150 #define XICS_STATUS_MASKED_PENDING 0x8
151 #define XICS_STATUS_PRESENTED 0x10
152 #define XICS_STATUS_QUEUED 0x20
154 /* (flags & XICS_FLAGS_IRQ_MASK) == 0 means the interrupt is not allocated */
155 #define XICS_FLAGS_IRQ_LSI 0x1
156 #define XICS_FLAGS_IRQ_MSI 0x2
157 #define XICS_FLAGS_IRQ_MASK 0x3
165 #define TYPE_XICS_FABRIC "xics-fabric"
166 #define XICS_FABRIC(obj) \
167 OBJECT_CHECK(XICSFabric, (obj), TYPE_XICS_FABRIC)
168 #define XICS_FABRIC_CLASS(klass) \
169 OBJECT_CLASS_CHECK(XICSFabricClass, (klass), TYPE_XICS_FABRIC)
170 #define XICS_FABRIC_GET_CLASS(obj) \
171 OBJECT_GET_CLASS(XICSFabricClass, (obj), TYPE_XICS_FABRIC)
173 typedef struct XICSFabricClass
{
174 InterfaceClass parent
;
175 ICSState
*(*ics_get
)(XICSFabric
*xi
, int irq
);
176 void (*ics_resend
)(XICSFabric
*xi
);
177 ICPState
*(*icp_get
)(XICSFabric
*xi
, int server
);
180 #define XICS_IRQS_SPAPR 1024
182 int spapr_ics_alloc(ICSState
*ics
, int irq_hint
, bool lsi
, Error
**errp
);
183 int spapr_ics_alloc_block(ICSState
*ics
, int num
, bool lsi
, bool align
,
185 void spapr_ics_free(ICSState
*ics
, int irq
, int num
);
186 void spapr_dt_xics(int nr_servers
, void *fdt
, uint32_t phandle
);
188 qemu_irq
xics_get_qirq(XICSFabric
*xi
, int irq
);
189 ICPState
*xics_icp_get(XICSFabric
*xi
, int server
);
191 /* Internal XICS interfaces */
192 void icp_set_cppr(ICPState
*icp
, uint8_t cppr
);
193 void icp_set_mfrr(ICPState
*icp
, uint8_t mfrr
);
194 uint32_t icp_accept(ICPState
*ss
);
195 uint32_t icp_ipoll(ICPState
*ss
, uint32_t *mfrr
);
196 void icp_eoi(ICPState
*icp
, uint32_t xirr
);
198 void ics_simple_write_xive(ICSState
*ics
, int nr
, int server
,
199 uint8_t priority
, uint8_t saved_priority
);
201 void ics_set_irq_type(ICSState
*ics
, int srcno
, bool lsi
);
202 void icp_pic_print_info(ICPState
*icp
, Monitor
*mon
);
203 void ics_pic_print_info(ICSState
*ics
, Monitor
*mon
);
205 void ics_resend(ICSState
*ics
);
206 void icp_resend(ICPState
*ss
);
208 typedef struct sPAPRMachineState sPAPRMachineState
;
210 int xics_kvm_init(sPAPRMachineState
*spapr
, Error
**errp
);
211 void xics_spapr_init(sPAPRMachineState
*spapr
);