2 * ARM GICv3 support - internal interfaces
4 * Copyright (c) 2012 Linaro Limited
5 * Copyright (c) 2015 Huawei.
6 * Copyright (c) 2015 Samsung Electronics Co., Ltd.
7 * Written by Peter Maydell
8 * Reworked for GICv3 by Shlomo Pongratz and Pavel Fedin
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation, either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, see <http://www.gnu.org/licenses/>.
24 #ifndef QEMU_ARM_GICV3_INTERNAL_H
25 #define QEMU_ARM_GICV3_INTERNAL_H
27 #include "hw/intc/arm_gicv3_common.h"
29 /* Distributor registers, as offsets from the distributor base address */
30 #define GICD_CTLR 0x0000
31 #define GICD_TYPER 0x0004
32 #define GICD_IIDR 0x0008
33 #define GICD_STATUSR 0x0010
34 #define GICD_SETSPI_NSR 0x0040
35 #define GICD_CLRSPI_NSR 0x0048
36 #define GICD_SETSPI_SR 0x0050
37 #define GICD_CLRSPI_SR 0x0058
38 #define GICD_SEIR 0x0068
39 #define GICD_IGROUPR 0x0080
40 #define GICD_ISENABLER 0x0100
41 #define GICD_ICENABLER 0x0180
42 #define GICD_ISPENDR 0x0200
43 #define GICD_ICPENDR 0x0280
44 #define GICD_ISACTIVER 0x0300
45 #define GICD_ICACTIVER 0x0380
46 #define GICD_IPRIORITYR 0x0400
47 #define GICD_ITARGETSR 0x0800
48 #define GICD_ICFGR 0x0C00
49 #define GICD_IGRPMODR 0x0D00
50 #define GICD_NSACR 0x0E00
51 #define GICD_SGIR 0x0F00
52 #define GICD_CPENDSGIR 0x0F10
53 #define GICD_SPENDSGIR 0x0F20
54 #define GICD_IROUTER 0x6000
55 #define GICD_IDREGS 0xFFD0
57 /* GICD_CTLR fields */
58 #define GICD_CTLR_EN_GRP0 (1U << 0)
59 #define GICD_CTLR_EN_GRP1NS (1U << 1) /* GICv3 5.3.20 */
60 #define GICD_CTLR_EN_GRP1S (1U << 2)
61 #define GICD_CTLR_EN_GRP1_ALL (GICD_CTLR_EN_GRP1NS | GICD_CTLR_EN_GRP1S)
62 /* Bit 4 is ARE if the system doesn't support TrustZone, ARE_S otherwise */
63 #define GICD_CTLR_ARE (1U << 4)
64 #define GICD_CTLR_ARE_S (1U << 4)
65 #define GICD_CTLR_ARE_NS (1U << 5)
66 #define GICD_CTLR_DS (1U << 6)
67 #define GICD_CTLR_E1NWF (1U << 7)
68 #define GICD_CTLR_RWP (1U << 31)
71 * Redistributor frame offsets from RD_base
73 #define GICR_SGI_OFFSET 0x10000
76 * Redistributor registers, offsets from RD_base
78 #define GICR_CTLR 0x0000
79 #define GICR_IIDR 0x0004
80 #define GICR_TYPER 0x0008
81 #define GICR_STATUSR 0x0010
82 #define GICR_WAKER 0x0014
83 #define GICR_SETLPIR 0x0040
84 #define GICR_CLRLPIR 0x0048
85 #define GICR_PROPBASER 0x0070
86 #define GICR_PENDBASER 0x0078
87 #define GICR_INVLPIR 0x00A0
88 #define GICR_INVALLR 0x00B0
89 #define GICR_SYNCR 0x00C0
90 #define GICR_IDREGS 0xFFD0
92 /* SGI and PPI Redistributor registers, offsets from RD_base */
93 #define GICR_IGROUPR0 (GICR_SGI_OFFSET + 0x0080)
94 #define GICR_ISENABLER0 (GICR_SGI_OFFSET + 0x0100)
95 #define GICR_ICENABLER0 (GICR_SGI_OFFSET + 0x0180)
96 #define GICR_ISPENDR0 (GICR_SGI_OFFSET + 0x0200)
97 #define GICR_ICPENDR0 (GICR_SGI_OFFSET + 0x0280)
98 #define GICR_ISACTIVER0 (GICR_SGI_OFFSET + 0x0300)
99 #define GICR_ICACTIVER0 (GICR_SGI_OFFSET + 0x0380)
100 #define GICR_IPRIORITYR (GICR_SGI_OFFSET + 0x0400)
101 #define GICR_ICFGR0 (GICR_SGI_OFFSET + 0x0C00)
102 #define GICR_ICFGR1 (GICR_SGI_OFFSET + 0x0C04)
103 #define GICR_IGRPMODR0 (GICR_SGI_OFFSET + 0x0D00)
104 #define GICR_NSACR (GICR_SGI_OFFSET + 0x0E00)
106 #define GICR_CTLR_ENABLE_LPIS (1U << 0)
107 #define GICR_CTLR_RWP (1U << 3)
108 #define GICR_CTLR_DPG0 (1U << 24)
109 #define GICR_CTLR_DPG1NS (1U << 25)
110 #define GICR_CTLR_DPG1S (1U << 26)
111 #define GICR_CTLR_UWP (1U << 31)
113 #define GICR_TYPER_PLPIS (1U << 0)
114 #define GICR_TYPER_VLPIS (1U << 1)
115 #define GICR_TYPER_DIRECTLPI (1U << 3)
116 #define GICR_TYPER_LAST (1U << 4)
117 #define GICR_TYPER_DPGS (1U << 5)
118 #define GICR_TYPER_PROCNUM (0xFFFFU << 8)
119 #define GICR_TYPER_COMMONLPIAFF (0x3 << 24)
120 #define GICR_TYPER_AFFINITYVALUE (0xFFFFFFFFULL << 32)
122 #define GICR_WAKER_ProcessorSleep (1U << 1)
123 #define GICR_WAKER_ChildrenAsleep (1U << 2)
125 #define GICR_PROPBASER_OUTER_CACHEABILITY_MASK (7ULL << 56)
126 #define GICR_PROPBASER_ADDR_MASK (0xfffffffffULL << 12)
127 #define GICR_PROPBASER_SHAREABILITY_MASK (3U << 10)
128 #define GICR_PROPBASER_CACHEABILITY_MASK (7U << 7)
129 #define GICR_PROPBASER_IDBITS_MASK (0x1f)
131 #define GICR_PENDBASER_PTZ (1ULL << 62)
132 #define GICR_PENDBASER_OUTER_CACHEABILITY_MASK (7ULL << 56)
133 #define GICR_PENDBASER_ADDR_MASK (0xffffffffULL << 16)
134 #define GICR_PENDBASER_SHAREABILITY_MASK (3U << 10)
135 #define GICR_PENDBASER_CACHEABILITY_MASK (7U << 7)
137 #define ICC_CTLR_EL1_CBPR (1U << 0)
138 #define ICC_CTLR_EL1_EOIMODE (1U << 1)
139 #define ICC_CTLR_EL1_PMHE (1U << 6)
140 #define ICC_CTLR_EL1_PRIBITS_SHIFT 8
141 #define ICC_CTLR_EL1_IDBITS_SHIFT 11
142 #define ICC_CTLR_EL1_SEIS (1U << 14)
143 #define ICC_CTLR_EL1_A3V (1U << 15)
145 #define ICC_PMR_PRIORITY_MASK 0xff
146 #define ICC_BPR_BINARYPOINT_MASK 0x07
147 #define ICC_IGRPEN_ENABLE 0x01
149 #define ICC_CTLR_EL3_CBPR_EL1S (1U << 0)
150 #define ICC_CTLR_EL3_CBPR_EL1NS (1U << 1)
151 #define ICC_CTLR_EL3_EOIMODE_EL3 (1U << 2)
152 #define ICC_CTLR_EL3_EOIMODE_EL1S (1U << 3)
153 #define ICC_CTLR_EL3_EOIMODE_EL1NS (1U << 4)
154 #define ICC_CTLR_EL3_RM (1U << 5)
155 #define ICC_CTLR_EL3_PMHE (1U << 6)
156 #define ICC_CTLR_EL3_PRIBITS_SHIFT 8
157 #define ICC_CTLR_EL3_IDBITS_SHIFT 11
158 #define ICC_CTLR_EL3_SEIS (1U << 14)
159 #define ICC_CTLR_EL3_A3V (1U << 15)
160 #define ICC_CTLR_EL3_NDS (1U << 17)
162 /* Special interrupt IDs */
163 #define INTID_SECURE 1020
164 #define INTID_NONSECURE 1021
165 #define INTID_SPURIOUS 1023
167 /* Functions internal to the emulated GICv3 */
170 * gicv3_redist_update:
171 * @cs: GICv3CPUState for this redistributor
173 * Recalculate the highest priority pending interrupt after a
174 * change to redistributor state, and inform the CPU accordingly.
176 void gicv3_redist_update(GICv3CPUState
*cs
);
181 * @start: first interrupt whose state changed
182 * @len: length of the range of interrupts whose state changed
184 * Recalculate the highest priority pending interrupts after a
185 * change to the distributor state affecting @len interrupts
186 * starting at @start, and inform the CPUs accordingly.
188 void gicv3_update(GICv3State
*s
, int start
, int len
);
191 * gicv3_full_update_noirqset:
194 * Recalculate the cached information about highest priority
195 * pending interrupts, but don't inform the CPUs. This should be
196 * called after an incoming migration has loaded new state.
198 void gicv3_full_update_noirqset(GICv3State
*s
);
204 * Recalculate the highest priority pending interrupts after
205 * a change that could affect the status of all interrupts,
206 * and inform the CPUs accordingly.
208 void gicv3_full_update(GICv3State
*s
);
209 MemTxResult
gicv3_dist_read(void *opaque
, hwaddr offset
, uint64_t *data
,
210 unsigned size
, MemTxAttrs attrs
);
211 MemTxResult
gicv3_dist_write(void *opaque
, hwaddr addr
, uint64_t data
,
212 unsigned size
, MemTxAttrs attrs
);
213 MemTxResult
gicv3_redist_read(void *opaque
, hwaddr offset
, uint64_t *data
,
214 unsigned size
, MemTxAttrs attrs
);
215 MemTxResult
gicv3_redist_write(void *opaque
, hwaddr offset
, uint64_t data
,
216 unsigned size
, MemTxAttrs attrs
);
217 void gicv3_dist_set_irq(GICv3State
*s
, int irq
, int level
);
218 void gicv3_redist_set_irq(GICv3CPUState
*cs
, int irq
, int level
);
219 void gicv3_redist_send_sgi(GICv3CPUState
*cs
, int grp
, int irq
, bool ns
);
220 void gicv3_init_cpuif(GICv3State
*s
);
223 * gicv3_cpuif_update:
224 * @cs: GICv3CPUState for the CPU to update
226 * Recalculate whether to assert the IRQ or FIQ lines after a change
227 * to the current highest priority pending interrupt, the CPU's
228 * current running priority or the CPU's current exception level or
231 void gicv3_cpuif_update(GICv3CPUState
*cs
);
233 static inline uint32_t gicv3_iidr(void)
235 /* Return the Implementer Identification Register value
236 * for the emulated GICv3, as reported in GICD_IIDR and GICR_IIDR.
238 * We claim to be an ARM r0p0 with a zero ProductID.
239 * This is the same as an r0p0 GIC-500.
244 static inline uint32_t gicv3_idreg(int regoffset
)
246 /* Return the value of the CoreSight ID register at the specified
247 * offset from the first ID register (as found in the distributor
248 * and redistributor register banks).
249 * These values indicate an ARM implementation of a GICv3.
251 static const uint8_t gicd_ids
[] = {
252 0x44, 0x00, 0x00, 0x00, 0x92, 0xB4, 0x3B, 0x00, 0x0D, 0xF0, 0x05, 0xB1
254 return gicd_ids
[regoffset
/ 4];
260 * Return the group which this interrupt is configured as (GICV3_G0,
261 * GICV3_G1 or GICV3_G1NS).
263 static inline int gicv3_irq_group(GICv3State
*s
, GICv3CPUState
*cs
, int irq
)
265 bool grpbit
, grpmodbit
;
267 if (irq
< GIC_INTERNAL
) {
268 grpbit
= extract32(cs
->gicr_igroupr0
, irq
, 1);
269 grpmodbit
= extract32(cs
->gicr_igrpmodr0
, irq
, 1);
271 grpbit
= gicv3_gicd_group_test(s
, irq
);
272 grpmodbit
= gicv3_gicd_grpmod_test(s
, irq
);
277 if (s
->gicd_ctlr
& GICD_CTLR_DS
) {
280 return grpmodbit
? GICV3_G1
: GICV3_G0
;
284 * gicv3_redist_affid:
286 * Return the 32-bit affinity ID of the CPU connected to this redistributor
288 static inline uint32_t gicv3_redist_affid(GICv3CPUState
*cs
)
290 return cs
->gicr_typer
>> 32;
294 * gicv3_cache_target_cpustate:
296 * Update the cached CPU state corresponding to the target for this interrupt
297 * (which is kept in s->gicd_irouter_target[]).
299 static inline void gicv3_cache_target_cpustate(GICv3State
*s
, int irq
)
301 GICv3CPUState
*cs
= NULL
;
303 uint32_t tgtaff
= extract64(s
->gicd_irouter
[irq
], 0, 24) |
304 extract64(s
->gicd_irouter
[irq
], 32, 8) << 24;
306 for (i
= 0; i
< s
->num_cpu
; i
++) {
307 if (s
->cpu
[i
].gicr_typer
>> 32 == tgtaff
) {
313 s
->gicd_irouter_target
[irq
] = cs
;
317 * gicv3_cache_all_target_cpustates:
319 * Populate the entire cache of CPU state pointers for interrupt targets
320 * (eg after inbound migration or CPU reset)
322 static inline void gicv3_cache_all_target_cpustates(GICv3State
*s
)
326 for (irq
= GIC_INTERNAL
; irq
< GICV3_MAXIRQ
; irq
++) {
327 gicv3_cache_target_cpustate(s
, irq
);
331 #endif /* !QEMU_ARM_GIC_INTERNAL_H */