hw/ppc_prep.c

   1 /*
   2  * QEMU PPC PREP hardware System Emulator
   3  *
   4  * Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "nvram.h"
  26 #include "pc.h"
  27 #include "fdc.h"
  28 #include "net.h"
  29 #include "sysemu.h"
  30 #include "isa.h"
  31 #include "pci.h"
  32 #include "prep_pci.h"
  33 #include "usb-ohci.h"
  34 #include "ppc.h"
  35 #include "boards.h"
  36 #include "qemu-log.h"
  37 #include "ide.h"
  38 #include "loader.h"
  39 #include "mc146818rtc.h"
  40 #include "blockdev.h"
  41
  42 //#define HARD_DEBUG_PPC_IO
  43 //#define DEBUG_PPC_IO
  44
  45 /* SMP is not enabled, for now */
  46 #define MAX_CPUS 1
  47
  48 #define MAX_IDE_BUS 2
  49
  50 #define BIOS_SIZE (1024 * 1024)
  51 #define BIOS_FILENAME "ppc_rom.bin"
  52 #define KERNEL_LOAD_ADDR 0x01000000
  53 #define INITRD_LOAD_ADDR 0x01800000
  54
  55 #if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO)
  56 #define DEBUG_PPC_IO
  57 #endif
  58
  59 #if defined (HARD_DEBUG_PPC_IO)
  60 #define PPC_IO_DPRINTF(fmt, ...)                         \
  61 do {                                                     \
  62     if (qemu_loglevel_mask(CPU_LOG_IOPORT)) {            \
  63         qemu_log("%s: " fmt, __func__ , ## __VA_ARGS__); \
  64     } else {                                             \
  65         printf("%s : " fmt, __func__ , ## __VA_ARGS__);  \
  66     }                                                    \
  67 } while (0)
  68 #elif defined (DEBUG_PPC_IO)
  69 #define PPC_IO_DPRINTF(fmt, ...) \
  70 qemu_log_mask(CPU_LOG_IOPORT, fmt, ## __VA_ARGS__)
  71 #else
  72 #define PPC_IO_DPRINTF(fmt, ...) do { } while (0)
  73 #endif
  74
  75 /* Constants for devices init */
  76 static const int ide_iobase[2] = { 0x1f0, 0x170 };
  77 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
  78 static const int ide_irq[2] = { 13, 13 };
  79
  80 #define NE2000_NB_MAX 6
  81
  82 static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
  83 static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
  84
  85 //static PITState *pit;
  86
  87 /* ISA IO ports bridge */
  88 #define PPC_IO_BASE 0x80000000
  89
  90 #if 0
  91 /* Speaker port 0x61 */
  92 static int speaker_data_on;
  93 static int dummy_refresh_clock;
  94 #endif
  95
  96 static void speaker_ioport_write (void *opaque, uint32_t addr, uint32_t val)
  97 {
  98 #if 0
  99     speaker_data_on = (val >> 1) & 1;
 100     pit_set_gate(pit, 2, val & 1);
 101 #endif
 102 }
 103
 104 static uint32_t speaker_ioport_read (void *opaque, uint32_t addr)
 105 {
 106 #if 0
 107     int out;
 108     out = pit_get_out(pit, 2, qemu_get_clock(vm_clock));
 109     dummy_refresh_clock ^= 1;
 110     return (speaker_data_on << 1) | pit_get_gate(pit, 2) | (out << 5) |
 111         (dummy_refresh_clock << 4);
 112 #endif
 113     return 0;
 114 }
 115
 116 /* PCI intack register */
 117 /* Read-only register (?) */
 118 static void _PPC_intack_write (void *opaque,
 119                                target_phys_addr_t addr, uint32_t value)
 120 {
 121 #if 0
 122     printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
 123            value);
 124 #endif
 125 }
 126
 127 static inline uint32_t _PPC_intack_read(target_phys_addr_t addr)
 128 {
 129     uint32_t retval = 0;
 130
 131     if ((addr & 0xf) == 0)
 132         retval = pic_intack_read(isa_pic);
 133 #if 0
 134     printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
 135            retval);
 136 #endif
 137
 138     return retval;
 139 }
 140
 141 static uint32_t PPC_intack_readb (void *opaque, target_phys_addr_t addr)
 142 {
 143     return _PPC_intack_read(addr);
 144 }
 145
 146 static uint32_t PPC_intack_readw (void *opaque, target_phys_addr_t addr)
 147 {
 148 #ifdef TARGET_WORDS_BIGENDIAN
 149     return bswap16(_PPC_intack_read(addr));
 150 #else
 151     return _PPC_intack_read(addr);
 152 #endif
 153 }
 154
 155 static uint32_t PPC_intack_readl (void *opaque, target_phys_addr_t addr)
 156 {
 157 #ifdef TARGET_WORDS_BIGENDIAN
 158     return bswap32(_PPC_intack_read(addr));
 159 #else
 160     return _PPC_intack_read(addr);
 161 #endif
 162 }
 163
 164 static CPUWriteMemoryFunc * const PPC_intack_write[] = {
 165     &_PPC_intack_write,
 166     &_PPC_intack_write,
 167     &_PPC_intack_write,
 168 };
 169
 170 static CPUReadMemoryFunc * const PPC_intack_read[] = {
 171     &PPC_intack_readb,
 172     &PPC_intack_readw,
 173     &PPC_intack_readl,
 174 };
 175
 176 /* PowerPC control and status registers */
 177 #if 0 // Not used
 178 static struct {
 179     /* IDs */
 180     uint32_t veni_devi;
 181     uint32_t revi;
 182     /* Control and status */
 183     uint32_t gcsr;
 184     uint32_t xcfr;
 185     uint32_t ct32;
 186     uint32_t mcsr;
 187     /* General purpose registers */
 188     uint32_t gprg[6];
 189     /* Exceptions */
 190     uint32_t feen;
 191     uint32_t fest;
 192     uint32_t fema;
 193     uint32_t fecl;
 194     uint32_t eeen;
 195     uint32_t eest;
 196     uint32_t eecl;
 197     uint32_t eeint;
 198     uint32_t eemck0;
 199     uint32_t eemck1;
 200     /* Error diagnostic */
 201 } XCSR;
 202
 203 static void PPC_XCSR_writeb (void *opaque,
 204                              target_phys_addr_t addr, uint32_t value)
 205 {
 206     printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
 207            value);
 208 }
 209
 210 static void PPC_XCSR_writew (void *opaque,
 211                              target_phys_addr_t addr, uint32_t value)
 212 {
 213 #ifdef TARGET_WORDS_BIGENDIAN
 214     value = bswap16(value);
 215 #endif
 216     printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
 217            value);
 218 }
 219
 220 static void PPC_XCSR_writel (void *opaque,
 221                              target_phys_addr_t addr, uint32_t value)
 222 {
 223 #ifdef TARGET_WORDS_BIGENDIAN
 224     value = bswap32(value);
 225 #endif
 226     printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
 227            value);
 228 }
 229
 230 static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr)
 231 {
 232     uint32_t retval = 0;
 233
 234     printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
 235            retval);
 236
 237     return retval;
 238 }
 239
 240 static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr)
 241 {
 242     uint32_t retval = 0;
 243
 244     printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
 245            retval);
 246 #ifdef TARGET_WORDS_BIGENDIAN
 247     retval = bswap16(retval);
 248 #endif
 249
 250     return retval;
 251 }
 252
 253 static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr)
 254 {
 255     uint32_t retval = 0;
 256
 257     printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
 258            retval);
 259 #ifdef TARGET_WORDS_BIGENDIAN
 260     retval = bswap32(retval);
 261 #endif
 262
 263     return retval;
 264 }
 265
 266 static CPUWriteMemoryFunc * const PPC_XCSR_write[] = {
 267     &PPC_XCSR_writeb,
 268     &PPC_XCSR_writew,
 269     &PPC_XCSR_writel,
 270 };
 271
 272 static CPUReadMemoryFunc * const PPC_XCSR_read[] = {
 273     &PPC_XCSR_readb,
 274     &PPC_XCSR_readw,
 275     &PPC_XCSR_readl,
 276 };
 277 #endif
 278
 279 /* Fake super-io ports for PREP platform (Intel 82378ZB) */
 280 typedef struct sysctrl_t {
 281     qemu_irq reset_irq;
 282     M48t59State *nvram;
 283     uint8_t state;
 284     uint8_t syscontrol;
 285     uint8_t fake_io[2];
 286     int contiguous_map;
 287     int endian;
 288 } sysctrl_t;
 289
 290 enum {
 291     STATE_HARDFILE = 0x01,
 292 };
 293
 294 static sysctrl_t *sysctrl;
 295
 296 static void PREP_io_write (void *opaque, uint32_t addr, uint32_t val)
 297 {
 298     sysctrl_t *sysctrl = opaque;
 299
 300     PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n", addr - PPC_IO_BASE,
 301                    val);
 302     sysctrl->fake_io[addr - 0x0398] = val;
 303 }
 304
 305 static uint32_t PREP_io_read (void *opaque, uint32_t addr)
 306 {
 307     sysctrl_t *sysctrl = opaque;
 308
 309     PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n", addr - PPC_IO_BASE,
 310                    sysctrl->fake_io[addr - 0x0398]);
 311     return sysctrl->fake_io[addr - 0x0398];
 312 }
 313
 314 static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
 315 {
 316     sysctrl_t *sysctrl = opaque;
 317
 318     PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n",
 319                    addr - PPC_IO_BASE, val);
 320     switch (addr) {
 321     case 0x0092:
 322         /* Special port 92 */
 323         /* Check soft reset asked */
 324         if (val & 0x01) {
 325             qemu_irq_raise(sysctrl->reset_irq);
 326         } else {
 327             qemu_irq_lower(sysctrl->reset_irq);
 328         }
 329         /* Check LE mode */
 330         if (val & 0x02) {
 331             sysctrl->endian = 1;
 332         } else {
 333             sysctrl->endian = 0;
 334         }
 335         break;
 336     case 0x0800:
 337         /* Motorola CPU configuration register : read-only */
 338         break;
 339     case 0x0802:
 340         /* Motorola base module feature register : read-only */
 341         break;
 342     case 0x0803:
 343         /* Motorola base module status register : read-only */
 344         break;
 345     case 0x0808:
 346         /* Hardfile light register */
 347         if (val & 1)
 348             sysctrl->state |= STATE_HARDFILE;
 349         else
 350             sysctrl->state &= ~STATE_HARDFILE;
 351         break;
 352     case 0x0810:
 353         /* Password protect 1 register */
 354         if (sysctrl->nvram != NULL)
 355             m48t59_toggle_lock(sysctrl->nvram, 1);
 356         break;
 357     case 0x0812:
 358         /* Password protect 2 register */
 359         if (sysctrl->nvram != NULL)
 360             m48t59_toggle_lock(sysctrl->nvram, 2);
 361         break;
 362     case 0x0814:
 363         /* L2 invalidate register */
 364         //        tlb_flush(first_cpu, 1);
 365         break;
 366     case 0x081C:
 367         /* system control register */
 368         sysctrl->syscontrol = val & 0x0F;
 369         break;
 370     case 0x0850:
 371         /* I/O map type register */
 372         sysctrl->contiguous_map = val & 0x01;
 373         break;
 374     default:
 375         printf("ERROR: unaffected IO port write: %04" PRIx32
 376                " => %02" PRIx32"\n", addr, val);
 377         break;
 378     }
 379 }
 380
 381 static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
 382 {
 383     sysctrl_t *sysctrl = opaque;
 384     uint32_t retval = 0xFF;
 385
 386     switch (addr) {
 387     case 0x0092:
 388         /* Special port 92 */
 389         retval = 0x00;
 390         break;
 391     case 0x0800:
 392         /* Motorola CPU configuration register */
 393         retval = 0xEF; /* MPC750 */
 394         break;
 395     case 0x0802:
 396         /* Motorola Base module feature register */
 397         retval = 0xAD; /* No ESCC, PMC slot neither ethernet */
 398         break;
 399     case 0x0803:
 400         /* Motorola base module status register */
 401         retval = 0xE0; /* Standard MPC750 */
 402         break;
 403     case 0x080C:
 404         /* Equipment present register:
 405          *  no L2 cache
 406          *  no upgrade processor
 407          *  no cards in PCI slots
 408          *  SCSI fuse is bad
 409          */
 410         retval = 0x3C;
 411         break;
 412     case 0x0810:
 413         /* Motorola base module extended feature register */
 414         retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */
 415         break;
 416     case 0x0814:
 417         /* L2 invalidate: don't care */
 418         break;
 419     case 0x0818:
 420         /* Keylock */
 421         retval = 0x00;
 422         break;
 423     case 0x081C:
 424         /* system control register
 425          * 7 - 6 / 1 - 0: L2 cache enable
 426          */
 427         retval = sysctrl->syscontrol;
 428         break;
 429     case 0x0823:
 430         /* */
 431         retval = 0x03; /* no L2 cache */
 432         break;
 433     case 0x0850:
 434         /* I/O map type register */
 435         retval = sysctrl->contiguous_map;
 436         break;
 437     default:
 438         printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr);
 439         break;
 440     }
 441     PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n",
 442                    addr - PPC_IO_BASE, retval);
 443
 444     return retval;
 445 }
 446
 447 static inline target_phys_addr_t prep_IO_address(sysctrl_t *sysctrl,
 448                                                  target_phys_addr_t addr)
 449 {
 450     if (sysctrl->contiguous_map == 0) {
 451         /* 64 KB contiguous space for IOs */
 452         addr &= 0xFFFF;
 453     } else {
 454         /* 8 MB non-contiguous space for IOs */
 455         addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7);
 456     }
 457
 458     return addr;
 459 }
 460
 461 static void PPC_prep_io_writeb (void *opaque, target_phys_addr_t addr,
 462                                 uint32_t value)
 463 {
 464     sysctrl_t *sysctrl = opaque;
 465
 466     addr = prep_IO_address(sysctrl, addr);
 467     cpu_outb(addr, value);
 468 }
 469
 470 static uint32_t PPC_prep_io_readb (void *opaque, target_phys_addr_t addr)
 471 {
 472     sysctrl_t *sysctrl = opaque;
 473     uint32_t ret;
 474
 475     addr = prep_IO_address(sysctrl, addr);
 476     ret = cpu_inb(addr);
 477
 478     return ret;
 479 }
 480
 481 static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr,
 482                                 uint32_t value)
 483 {
 484     sysctrl_t *sysctrl = opaque;
 485
 486     addr = prep_IO_address(sysctrl, addr);
 487 #ifdef TARGET_WORDS_BIGENDIAN
 488     value = bswap16(value);
 489 #endif
 490     PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value);
 491     cpu_outw(addr, value);
 492 }
 493
 494 static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr)
 495 {
 496     sysctrl_t *sysctrl = opaque;
 497     uint32_t ret;
 498
 499     addr = prep_IO_address(sysctrl, addr);
 500     ret = cpu_inw(addr);
 501 #ifdef TARGET_WORDS_BIGENDIAN
 502     ret = bswap16(ret);
 503 #endif
 504     PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret);
 505
 506     return ret;
 507 }
 508
 509 static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr,
 510                                 uint32_t value)
 511 {
 512     sysctrl_t *sysctrl = opaque;
 513
 514     addr = prep_IO_address(sysctrl, addr);
 515 #ifdef TARGET_WORDS_BIGENDIAN
 516     value = bswap32(value);
 517 #endif
 518     PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value);
 519     cpu_outl(addr, value);
 520 }
 521
 522 static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr)
 523 {
 524     sysctrl_t *sysctrl = opaque;
 525     uint32_t ret;
 526
 527     addr = prep_IO_address(sysctrl, addr);
 528     ret = cpu_inl(addr);
 529 #ifdef TARGET_WORDS_BIGENDIAN
 530     ret = bswap32(ret);
 531 #endif
 532     PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret);
 533
 534     return ret;
 535 }
 536
 537 static CPUWriteMemoryFunc * const PPC_prep_io_write[] = {
 538     &PPC_prep_io_writeb,
 539     &PPC_prep_io_writew,
 540     &PPC_prep_io_writel,
 541 };
 542
 543 static CPUReadMemoryFunc * const PPC_prep_io_read[] = {
 544     &PPC_prep_io_readb,
 545     &PPC_prep_io_readw,
 546     &PPC_prep_io_readl,
 547 };
 548
 549 #define NVRAM_SIZE        0x2000
 550
 551 static void cpu_request_exit(void *opaque, int irq, int level)
 552 {
 553     CPUState *env = cpu_single_env;
 554
 555     if (env && level) {
 556         cpu_exit(env);
 557     }
 558 }
 559
 560 /* PowerPC PREP hardware initialisation */
 561 static void ppc_prep_init (ram_addr_t ram_size,
 562                            const char *boot_device,
 563                            const char *kernel_filename,
 564                            const char *kernel_cmdline,
 565                            const char *initrd_filename,
 566                            const char *cpu_model)
 567 {
 568     CPUState *env = NULL;
 569     char *filename;
 570     nvram_t nvram;
 571     M48t59State *m48t59;
 572     int PPC_io_memory;
 573     int linux_boot, i, nb_nics1, bios_size;
 574     ram_addr_t ram_offset, bios_offset;
 575     uint32_t kernel_base, initrd_base;
 576     long kernel_size, initrd_size;
 577     PCIBus *pci_bus;
 578     qemu_irq *i8259;
 579     qemu_irq *cpu_exit_irq;
 580     int ppc_boot_device;
 581     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 582     DriveInfo *fd[MAX_FD];
 583
 584     sysctrl = qemu_mallocz(sizeof(sysctrl_t));
 585
 586     linux_boot = (kernel_filename != NULL);
 587
 588     /* init CPUs */
 589     if (cpu_model == NULL)
 590         cpu_model = "602";
 591     for (i = 0; i < smp_cpus; i++) {
 592         env = cpu_init(cpu_model);
 593         if (!env) {
 594             fprintf(stderr, "Unable to find PowerPC CPU definition\n");
 595             exit(1);
 596         }
 597         if (env->flags & POWERPC_FLAG_RTC_CLK) {
 598             /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */
 599             cpu_ppc_tb_init(env, 7812500UL);
 600         } else {
 601             /* Set time-base frequency to 100 Mhz */
 602             cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
 603         }
 604         qemu_register_reset((QEMUResetHandler*)&cpu_reset, env);
 605     }
 606
 607     /* allocate RAM */
 608     ram_offset = qemu_ram_alloc(NULL, "ppc_prep.ram", ram_size);
 609     cpu_register_physical_memory(0, ram_size, ram_offset);
 610
 611     /* allocate and load BIOS */
 612     bios_offset = qemu_ram_alloc(NULL, "ppc_prep.bios", BIOS_SIZE);
 613     if (bios_name == NULL)
 614         bios_name = BIOS_FILENAME;
 615     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 616     if (filename) {
 617         bios_size = get_image_size(filename);
 618     } else {
 619         bios_size = -1;
 620     }
 621     if (bios_size > 0 && bios_size <= BIOS_SIZE) {
 622         target_phys_addr_t bios_addr;
 623         bios_size = (bios_size + 0xfff) & ~0xfff;
 624         bios_addr = (uint32_t)(-bios_size);
 625         cpu_register_physical_memory(bios_addr, bios_size,
 626                                      bios_offset | IO_MEM_ROM);
 627         bios_size = load_image_targphys(filename, bios_addr, bios_size);
 628     }
 629     if (bios_size < 0 || bios_size > BIOS_SIZE) {
 630         hw_error("qemu: could not load PPC PREP bios '%s'\n", bios_name);
 631     }
 632     if (filename) {
 633         qemu_free(filename);
 634     }
 635     if (env->nip < 0xFFF80000 && bios_size < 0x00100000) {
 636         hw_error("PowerPC 601 / 620 / 970 need a 1MB BIOS\n");
 637     }
 638
 639     if (linux_boot) {
 640         kernel_base = KERNEL_LOAD_ADDR;
 641         /* now we can load the kernel */
 642         kernel_size = load_image_targphys(kernel_filename, kernel_base,
 643                                           ram_size - kernel_base);
 644         if (kernel_size < 0) {
 645             hw_error("qemu: could not load kernel '%s'\n", kernel_filename);
 646             exit(1);
 647         }
 648         /* load initrd */
 649         if (initrd_filename) {
 650             initrd_base = INITRD_LOAD_ADDR;
 651             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 652                                               ram_size - initrd_base);
 653             if (initrd_size < 0) {
 654                 hw_error("qemu: could not load initial ram disk '%s'\n",
 655                           initrd_filename);
 656             }
 657         } else {
 658             initrd_base = 0;
 659             initrd_size = 0;
 660         }
 661         ppc_boot_device = 'm';
 662     } else {
 663         kernel_base = 0;
 664         kernel_size = 0;
 665         initrd_base = 0;
 666         initrd_size = 0;
 667         ppc_boot_device = '\0';
 668         /* For now, OHW cannot boot from the network. */
 669         for (i = 0; boot_device[i] != '\0'; i++) {
 670             if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
 671                 ppc_boot_device = boot_device[i];
 672                 break;
 673             }
 674         }
 675         if (ppc_boot_device == '\0') {
 676             fprintf(stderr, "No valid boot device for Mac99 machine\n");
 677             exit(1);
 678         }
 679     }
 680
 681     isa_mem_base = 0xc0000000;
 682     if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
 683         hw_error("Only 6xx bus is supported on PREP machine\n");
 684     }
 685     i8259 = i8259_init(first_cpu->irq_inputs[PPC6xx_INPUT_INT]);
 686     pci_bus = pci_prep_init(i8259);
 687     /* Hmm, prep has no pci-isa bridge ??? */
 688     isa_bus_new(NULL);
 689     isa_bus_irqs(i8259);
 690     //    pci_bus = i440fx_init();
 691     /* Register 8 MB of ISA IO space (needed for non-contiguous map) */
 692     PPC_io_memory = cpu_register_io_memory(PPC_prep_io_read,
 693                                            PPC_prep_io_write, sysctrl);
 694     cpu_register_physical_memory(0x80000000, 0x00800000, PPC_io_memory);
 695
 696     /* init basic PC hardware */
 697     pci_vga_init(pci_bus);
 698     //    openpic = openpic_init(0x00000000, 0xF0000000, 1);
 699     //    pit = pit_init(0x40, i8259[0]);
 700     rtc_init(2000, NULL);
 701
 702     if (serial_hds[0])
 703         serial_isa_init(0, serial_hds[0]);
 704     nb_nics1 = nb_nics;
 705     if (nb_nics1 > NE2000_NB_MAX)
 706         nb_nics1 = NE2000_NB_MAX;
 707     for(i = 0; i < nb_nics1; i++) {
 708         if (nd_table[i].model == NULL) {
 709             nd_table[i].model = qemu_strdup("ne2k_isa");
 710         }
 711         if (strcmp(nd_table[i].model, "ne2k_isa") == 0) {
 712             isa_ne2000_init(ne2000_io[i], ne2000_irq[i], &nd_table[i]);
 713         } else {
 714             pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL);
 715         }
 716     }
 717
 718     if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
 719         fprintf(stderr, "qemu: too many IDE bus\n");
 720         exit(1);
 721     }
 722
 723     for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
 724         hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
 725     }
 726
 727     for(i = 0; i < MAX_IDE_BUS; i++) {
 728         isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i],
 729                      hd[2 * i],
 730                      hd[2 * i + 1]);
 731     }
 732     isa_create_simple("i8042");
 733
 734     cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
 735     DMA_init(1, cpu_exit_irq);
 736
 737     //    SB16_init();
 738
 739     for(i = 0; i < MAX_FD; i++) {
 740         fd[i] = drive_get(IF_FLOPPY, 0, i);
 741     }
 742     fdctrl_init_isa(fd);
 743
 744     /* Register speaker port */
 745     register_ioport_read(0x61, 1, 1, speaker_ioport_read, NULL);
 746     register_ioport_write(0x61, 1, 1, speaker_ioport_write, NULL);
 747     /* Register fake IO ports for PREP */
 748     sysctrl->reset_irq = first_cpu->irq_inputs[PPC6xx_INPUT_HRESET];
 749     register_ioport_read(0x398, 2, 1, &PREP_io_read, sysctrl);
 750     register_ioport_write(0x398, 2, 1, &PREP_io_write, sysctrl);
 751     /* System control ports */
 752     register_ioport_read(0x0092, 0x01, 1, &PREP_io_800_readb, sysctrl);
 753     register_ioport_write(0x0092, 0x01, 1, &PREP_io_800_writeb, sysctrl);
 754     register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, sysctrl);
 755     register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl);
 756     /* PCI intack location */
 757     PPC_io_memory = cpu_register_io_memory(PPC_intack_read,
 758                                            PPC_intack_write, NULL);
 759     cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory);
 760     /* PowerPC control and status register group */
 761 #if 0
 762     PPC_io_memory = cpu_register_io_memory(PPC_XCSR_read, PPC_XCSR_write,
 763                                            NULL);
 764     cpu_register_physical_memory(0xFEFF0000, 0x1000, PPC_io_memory);
 765 #endif
 766
 767     if (usb_enabled) {
 768         usb_ohci_init_pci(pci_bus, -1);
 769     }
 770
 771     m48t59 = m48t59_init(i8259[8], 0, 0x0074, NVRAM_SIZE, 59);
 772     if (m48t59 == NULL)
 773         return;
 774     sysctrl->nvram = m48t59;
 775
 776     /* Initialise NVRAM */
 777     nvram.opaque = m48t59;
 778     nvram.read_fn = &m48t59_read;
 779     nvram.write_fn = &m48t59_write;
 780     PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "PREP", ram_size, ppc_boot_device,
 781                          kernel_base, kernel_size,
 782                          kernel_cmdline,
 783                          initrd_base, initrd_size,
 784                          /* XXX: need an option to load a NVRAM image */
 785                          0,
 786                          graphic_width, graphic_height, graphic_depth);
 787
 788     /* Special port to get debug messages from Open-Firmware */
 789     register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL);
 790 }
 791
 792 static QEMUMachine prep_machine = {
 793     .name = "prep",
 794     .desc = "PowerPC PREP platform",
 795     .init = ppc_prep_init,
 796     .max_cpus = MAX_CPUS,
 797 };
 798
 799 static void prep_machine_init(void)
 800 {
 801     qemu_register_machine(&prep_machine);
 802 }
 803
 804 machine_init(prep_machine_init);