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arm: Don't decode MRS(banked) or MSR(banked) for M profile
[qemu.git] / hw / i386 / acpi-build.c
blob207310857739a9a8510297b25234309af043e701
1 /* Support for generating ACPI tables and passing them to Guests
2 *
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
6 *
7 * Author: Michael S. Tsirkin <mst@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #include "qemu/osdep.h"
24 #include "qapi/error.h"
25 #include "acpi-build.h"
26 #include "qemu-common.h"
27 #include "qemu/bitmap.h"
28 #include "qemu/error-report.h"
29 #include "hw/pci/pci.h"
30 #include "qom/cpu.h"
31 #include "hw/i386/pc.h"
32 #include "target/i386/cpu.h"
33 #include "hw/timer/hpet.h"
34 #include "hw/acpi/acpi-defs.h"
35 #include "hw/acpi/acpi.h"
36 #include "hw/acpi/cpu.h"
37 #include "hw/nvram/fw_cfg.h"
38 #include "hw/acpi/bios-linker-loader.h"
39 #include "hw/loader.h"
40 #include "hw/isa/isa.h"
41 #include "hw/block/fdc.h"
42 #include "hw/acpi/memory_hotplug.h"
43 #include "sysemu/tpm.h"
44 #include "hw/acpi/tpm.h"
45 #include "hw/acpi/vmgenid.h"
46 #include "sysemu/tpm_backend.h"
47 #include "hw/timer/mc146818rtc_regs.h"
48 #include "sysemu/numa.h"
49
50 /* Supported chipsets: */
51 #include "hw/acpi/piix4.h"
52 #include "hw/acpi/pcihp.h"
53 #include "hw/i386/ich9.h"
54 #include "hw/pci/pci_bus.h"
55 #include "hw/pci-host/q35.h"
56 #include "hw/i386/x86-iommu.h"
57
58 #include "hw/acpi/aml-build.h"
59
60 #include "qapi/qmp/qint.h"
61 #include "qom/qom-qobject.h"
62 #include "hw/i386/amd_iommu.h"
63 #include "hw/i386/intel_iommu.h"
64
65 #include "hw/acpi/ipmi.h"
66
67 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
68 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
69 * a little bit, there should be plenty of free space since the DSDT
70 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
71 */
72 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
73 #define ACPI_BUILD_ALIGN_SIZE 0x1000
74
75 #define ACPI_BUILD_TABLE_SIZE 0x20000
76
77 /* #define DEBUG_ACPI_BUILD */
78 #ifdef DEBUG_ACPI_BUILD
79 #define ACPI_BUILD_DPRINTF(fmt, ...) \
80 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
81 #else
82 #define ACPI_BUILD_DPRINTF(fmt, ...)
83 #endif
84
85 /* Default IOAPIC ID */
86 #define ACPI_BUILD_IOAPIC_ID 0x0
87
88 typedef struct AcpiMcfgInfo {
89 uint64_t mcfg_base;
90 uint32_t mcfg_size;
91 } AcpiMcfgInfo;
92
93 typedef struct AcpiPmInfo {
94 bool s3_disabled;
95 bool s4_disabled;
96 bool pcihp_bridge_en;
97 uint8_t s4_val;
98 uint16_t sci_int;
99 uint8_t acpi_enable_cmd;
100 uint8_t acpi_disable_cmd;
101 uint32_t gpe0_blk;
102 uint32_t gpe0_blk_len;
103 uint32_t io_base;
104 uint16_t cpu_hp_io_base;
105 uint16_t pcihp_io_base;
106 uint16_t pcihp_io_len;
107 } AcpiPmInfo;
108
109 typedef struct AcpiMiscInfo {
110 bool is_piix4;
111 bool has_hpet;
112 TPMVersion tpm_version;
113 const unsigned char *dsdt_code;
114 unsigned dsdt_size;
115 uint16_t pvpanic_port;
116 uint16_t applesmc_io_base;
117 } AcpiMiscInfo;
118
119 typedef struct AcpiBuildPciBusHotplugState {
120 GArray *device_table;
121 GArray *notify_table;
122 struct AcpiBuildPciBusHotplugState *parent;
123 bool pcihp_bridge_en;
124 } AcpiBuildPciBusHotplugState;
125
126 static void acpi_get_pm_info(AcpiPmInfo *pm)
127 {
128 Object *piix = piix4_pm_find();
129 Object *lpc = ich9_lpc_find();
130 Object *obj = NULL;
131 QObject *o;
132
133 pm->cpu_hp_io_base = 0;
134 pm->pcihp_io_base = 0;
135 pm->pcihp_io_len = 0;
136 if (piix) {
137 obj = piix;
138 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
139 pm->pcihp_io_base =
140 object_property_get_int(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
141 pm->pcihp_io_len =
142 object_property_get_int(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
143 }
144 if (lpc) {
145 obj = lpc;
146 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
147 }
148 assert(obj);
149
150 /* Fill in optional s3/s4 related properties */
151 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
152 if (o) {
153 pm->s3_disabled = qint_get_int(qobject_to_qint(o));
154 } else {
155 pm->s3_disabled = false;
156 }
157 qobject_decref(o);
158 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL);
159 if (o) {
160 pm->s4_disabled = qint_get_int(qobject_to_qint(o));
161 } else {
162 pm->s4_disabled = false;
163 }
164 qobject_decref(o);
165 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL);
166 if (o) {
167 pm->s4_val = qint_get_int(qobject_to_qint(o));
168 } else {
169 pm->s4_val = false;
170 }
171 qobject_decref(o);
172
173 /* Fill in mandatory properties */
174 pm->sci_int = object_property_get_int(obj, ACPI_PM_PROP_SCI_INT, NULL);
175
176 pm->acpi_enable_cmd = object_property_get_int(obj,
177 ACPI_PM_PROP_ACPI_ENABLE_CMD,
178 NULL);
179 pm->acpi_disable_cmd = object_property_get_int(obj,
180 ACPI_PM_PROP_ACPI_DISABLE_CMD,
181 NULL);
182 pm->io_base = object_property_get_int(obj, ACPI_PM_PROP_PM_IO_BASE,
183 NULL);
184 pm->gpe0_blk = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK,
185 NULL);
186 pm->gpe0_blk_len = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK_LEN,
187 NULL);
188 pm->pcihp_bridge_en =
189 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support",
190 NULL);
191 }
192
193 static void acpi_get_misc_info(AcpiMiscInfo *info)
194 {
195 Object *piix = piix4_pm_find();
196 Object *lpc = ich9_lpc_find();
197 assert(!!piix != !!lpc);
198
199 if (piix) {
200 info->is_piix4 = true;
201 }
202 if (lpc) {
203 info->is_piix4 = false;
204 }
205
206 info->has_hpet = hpet_find();
207 info->tpm_version = tpm_get_version();
208 info->pvpanic_port = pvpanic_port();
209 info->applesmc_io_base = applesmc_port();
210 }
211
212 /*
213 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
214 * On i386 arch we only have two pci hosts, so we can look only for them.
215 */
216 static Object *acpi_get_i386_pci_host(void)
217 {
218 PCIHostState *host;
219
220 host = OBJECT_CHECK(PCIHostState,
221 object_resolve_path("/machine/i440fx", NULL),
222 TYPE_PCI_HOST_BRIDGE);
223 if (!host) {
224 host = OBJECT_CHECK(PCIHostState,
225 object_resolve_path("/machine/q35", NULL),
226 TYPE_PCI_HOST_BRIDGE);
227 }
228
229 return OBJECT(host);
230 }
231
232 static void acpi_get_pci_holes(Range *hole, Range *hole64)
233 {
234 Object *pci_host;
235
236 pci_host = acpi_get_i386_pci_host();
237 g_assert(pci_host);
238
239 range_set_bounds1(hole,
240 object_property_get_int(pci_host,
241 PCI_HOST_PROP_PCI_HOLE_START,
242 NULL),
243 object_property_get_int(pci_host,
244 PCI_HOST_PROP_PCI_HOLE_END,
245 NULL));
246 range_set_bounds1(hole64,
247 object_property_get_int(pci_host,
248 PCI_HOST_PROP_PCI_HOLE64_START,
249 NULL),
250 object_property_get_int(pci_host,
251 PCI_HOST_PROP_PCI_HOLE64_END,
252 NULL));
253 }
254
255 #define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */
256
257 static void acpi_align_size(GArray *blob, unsigned align)
258 {
259 /* Align size to multiple of given size. This reduces the chance
260 * we need to change size in the future (breaking cross version migration).
261 */
262 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
263 }
264
265 /* FACS */
266 static void
267 build_facs(GArray *table_data, BIOSLinker *linker)
268 {
269 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs);
270 memcpy(&facs->signature, "FACS", 4);
271 facs->length = cpu_to_le32(sizeof(*facs));
272 }
273
274 /* Load chipset information in FADT */
275 static void fadt_setup(AcpiFadtDescriptorRev1 *fadt, AcpiPmInfo *pm)
276 {
277 fadt->model = 1;
278 fadt->reserved1 = 0;
279 fadt->sci_int = cpu_to_le16(pm->sci_int);
280 fadt->smi_cmd = cpu_to_le32(ACPI_PORT_SMI_CMD);
281 fadt->acpi_enable = pm->acpi_enable_cmd;
282 fadt->acpi_disable = pm->acpi_disable_cmd;
283 /* EVT, CNT, TMR offset matches hw/acpi/core.c */
284 fadt->pm1a_evt_blk = cpu_to_le32(pm->io_base);
285 fadt->pm1a_cnt_blk = cpu_to_le32(pm->io_base + 0x04);
286 fadt->pm_tmr_blk = cpu_to_le32(pm->io_base + 0x08);
287 fadt->gpe0_blk = cpu_to_le32(pm->gpe0_blk);
288 /* EVT, CNT, TMR length matches hw/acpi/core.c */
289 fadt->pm1_evt_len = 4;
290 fadt->pm1_cnt_len = 2;
291 fadt->pm_tmr_len = 4;
292 fadt->gpe0_blk_len = pm->gpe0_blk_len;
293 fadt->plvl2_lat = cpu_to_le16(0xfff); /* C2 state not supported */
294 fadt->plvl3_lat = cpu_to_le16(0xfff); /* C3 state not supported */
295 fadt->flags = cpu_to_le32((1 << ACPI_FADT_F_WBINVD) |
296 (1 << ACPI_FADT_F_PROC_C1) |
297 (1 << ACPI_FADT_F_SLP_BUTTON) |
298 (1 << ACPI_FADT_F_RTC_S4));
299 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK);
300 /* APIC destination mode ("Flat Logical") has an upper limit of 8 CPUs
301 * For more than 8 CPUs, "Clustered Logical" mode has to be used
302 */
303 if (max_cpus > 8) {
304 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL);
305 }
306 fadt->century = RTC_CENTURY;
307 }
308
309
310 /* FADT */
311 static void
312 build_fadt(GArray *table_data, BIOSLinker *linker, AcpiPmInfo *pm,
313 unsigned facs_tbl_offset, unsigned dsdt_tbl_offset,
314 const char *oem_id, const char *oem_table_id)
315 {
316 AcpiFadtDescriptorRev1 *fadt = acpi_data_push(table_data, sizeof(*fadt));
317 unsigned fw_ctrl_offset = (char *)&fadt->firmware_ctrl - table_data->data;
318 unsigned dsdt_entry_offset = (char *)&fadt->dsdt - table_data->data;
319
320 /* FACS address to be filled by Guest linker */
321 bios_linker_loader_add_pointer(linker,
322 ACPI_BUILD_TABLE_FILE, fw_ctrl_offset, sizeof(fadt->firmware_ctrl),
323 ACPI_BUILD_TABLE_FILE, facs_tbl_offset);
324
325 /* DSDT address to be filled by Guest linker */
326 fadt_setup(fadt, pm);
327 bios_linker_loader_add_pointer(linker,
328 ACPI_BUILD_TABLE_FILE, dsdt_entry_offset, sizeof(fadt->dsdt),
329 ACPI_BUILD_TABLE_FILE, dsdt_tbl_offset);
330
331 build_header(linker, table_data,
332 (void *)fadt, "FACP", sizeof(*fadt), 1, oem_id, oem_table_id);
333 }
334
335 void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid,
336 const CPUArchIdList *apic_ids, GArray *entry)
337 {
338 uint32_t apic_id = apic_ids->cpus[uid].arch_id;
339
340 /* ACPI spec says that LAPIC entry for non present
341 * CPU may be omitted from MADT or it must be marked
342 * as disabled. However omitting non present CPU from
343 * MADT breaks hotplug on linux. So possible CPUs
344 * should be put in MADT but kept disabled.
345 */
346 if (apic_id < 255) {
347 AcpiMadtProcessorApic *apic = acpi_data_push(entry, sizeof *apic);
348
349 apic->type = ACPI_APIC_PROCESSOR;
350 apic->length = sizeof(*apic);
351 apic->processor_id = uid;
352 apic->local_apic_id = apic_id;
353 if (apic_ids->cpus[uid].cpu != NULL) {
354 apic->flags = cpu_to_le32(1);
355 } else {
356 apic->flags = cpu_to_le32(0);
357 }
358 } else {
359 AcpiMadtProcessorX2Apic *apic = acpi_data_push(entry, sizeof *apic);
360
361 apic->type = ACPI_APIC_LOCAL_X2APIC;
362 apic->length = sizeof(*apic);
363 apic->uid = cpu_to_le32(uid);
364 apic->x2apic_id = cpu_to_le32(apic_id);
365 if (apic_ids->cpus[uid].cpu != NULL) {
366 apic->flags = cpu_to_le32(1);
367 } else {
368 apic->flags = cpu_to_le32(0);
369 }
370 }
371 }
372
373 static void
374 build_madt(GArray *table_data, BIOSLinker *linker, PCMachineState *pcms)
375 {
376 MachineClass *mc = MACHINE_GET_CLASS(pcms);
377 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(MACHINE(pcms));
378 int madt_start = table_data->len;
379 AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_GET_CLASS(pcms->acpi_dev);
380 AcpiDeviceIf *adev = ACPI_DEVICE_IF(pcms->acpi_dev);
381 bool x2apic_mode = false;
382
383 AcpiMultipleApicTable *madt;
384 AcpiMadtIoApic *io_apic;
385 AcpiMadtIntsrcovr *intsrcovr;
386 int i;
387
388 madt = acpi_data_push(table_data, sizeof *madt);
389 madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS);
390 madt->flags = cpu_to_le32(1);
391
392 for (i = 0; i < apic_ids->len; i++) {
393 adevc->madt_cpu(adev, i, apic_ids, table_data);
394 if (apic_ids->cpus[i].arch_id > 254) {
395 x2apic_mode = true;
396 }
397 }
398
399 io_apic = acpi_data_push(table_data, sizeof *io_apic);
400 io_apic->type = ACPI_APIC_IO;
401 io_apic->length = sizeof(*io_apic);
402 io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID;
403 io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS);
404 io_apic->interrupt = cpu_to_le32(0);
405
406 if (pcms->apic_xrupt_override) {
407 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
408 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
409 intsrcovr->length = sizeof(*intsrcovr);
410 intsrcovr->source = 0;
411 intsrcovr->gsi = cpu_to_le32(2);
412 intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */
413 }
414 for (i = 1; i < 16; i++) {
415 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
416 if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) {
417 /* No need for a INT source override structure. */
418 continue;
419 }
420 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
421 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
422 intsrcovr->length = sizeof(*intsrcovr);
423 intsrcovr->source = i;
424 intsrcovr->gsi = cpu_to_le32(i);
425 intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */
426 }
427
428 if (x2apic_mode) {
429 AcpiMadtLocalX2ApicNmi *local_nmi;
430
431 local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
432 local_nmi->type = ACPI_APIC_LOCAL_X2APIC_NMI;
433 local_nmi->length = sizeof(*local_nmi);
434 local_nmi->uid = 0xFFFFFFFF; /* all processors */
435 local_nmi->flags = cpu_to_le16(0);
436 local_nmi->lint = 1; /* ACPI_LINT1 */
437 } else {
438 AcpiMadtLocalNmi *local_nmi;
439
440 local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
441 local_nmi->type = ACPI_APIC_LOCAL_NMI;
442 local_nmi->length = sizeof(*local_nmi);
443 local_nmi->processor_id = 0xff; /* all processors */
444 local_nmi->flags = cpu_to_le16(0);
445 local_nmi->lint = 1; /* ACPI_LINT1 */
446 }
447
448 build_header(linker, table_data,
449 (void *)(table_data->data + madt_start), "APIC",
450 table_data->len - madt_start, 1, NULL, NULL);
451 }
452
453 /* Assign BSEL property to all buses. In the future, this can be changed
454 * to only assign to buses that support hotplug.
455 */
456 static void *acpi_set_bsel(PCIBus *bus, void *opaque)
457 {
458 unsigned *bsel_alloc = opaque;
459 unsigned *bus_bsel;
460
461 if (qbus_is_hotpluggable(BUS(bus))) {
462 bus_bsel = g_malloc(sizeof *bus_bsel);
463
464 *bus_bsel = (*bsel_alloc)++;
465 object_property_add_uint32_ptr(OBJECT(bus), ACPI_PCIHP_PROP_BSEL,
466 bus_bsel, &error_abort);
467 }
468
469 return bsel_alloc;
470 }
471
472 static void acpi_set_pci_info(void)
473 {
474 PCIBus *bus = find_i440fx(); /* TODO: Q35 support */
475 unsigned bsel_alloc = ACPI_PCIHP_BSEL_DEFAULT;
476
477 if (bus) {
478 /* Scan all PCI buses. Set property to enable acpi based hotplug. */
479 pci_for_each_bus_depth_first(bus, acpi_set_bsel, NULL, &bsel_alloc);
480 }
481 }
482
483 static void build_append_pcihp_notify_entry(Aml *method, int slot)
484 {
485 Aml *if_ctx;
486 int32_t devfn = PCI_DEVFN(slot, 0);
487
488 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL));
489 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1)));
490 aml_append(method, if_ctx);
491 }
492
493 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus,
494 bool pcihp_bridge_en)
495 {
496 Aml *dev, *notify_method, *method;
497 QObject *bsel;
498 PCIBus *sec;
499 int i;
500
501 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
502 if (bsel) {
503 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel));
504
505 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val)));
506 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED);
507 }
508
509 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) {
510 DeviceClass *dc;
511 PCIDeviceClass *pc;
512 PCIDevice *pdev = bus->devices[i];
513 int slot = PCI_SLOT(i);
514 bool hotplug_enabled_dev;
515 bool bridge_in_acpi;
516
517 if (!pdev) {
518 if (bsel) { /* add hotplug slots for non present devices */
519 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
520 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
521 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
522 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
523 aml_append(method,
524 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
525 );
526 aml_append(dev, method);
527 aml_append(parent_scope, dev);
528
529 build_append_pcihp_notify_entry(notify_method, slot);
530 }
531 continue;
532 }
533
534 pc = PCI_DEVICE_GET_CLASS(pdev);
535 dc = DEVICE_GET_CLASS(pdev);
536
537 /* When hotplug for bridges is enabled, bridges are
538 * described in ACPI separately (see build_pci_bus_end).
539 * In this case they aren't themselves hot-pluggable.
540 * Hotplugged bridges *are* hot-pluggable.
541 */
542 bridge_in_acpi = pc->is_bridge && pcihp_bridge_en &&
543 !DEVICE(pdev)->hotplugged;
544
545 hotplug_enabled_dev = bsel && dc->hotpluggable && !bridge_in_acpi;
546
547 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) {
548 continue;
549 }
550
551 /* start to compose PCI slot descriptor */
552 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
553 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
554
555 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) {
556 /* add VGA specific AML methods */
557 int s3d;
558
559 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) {
560 s3d = 3;
561 } else {
562 s3d = 0;
563 }
564
565 method = aml_method("_S1D", 0, AML_NOTSERIALIZED);
566 aml_append(method, aml_return(aml_int(0)));
567 aml_append(dev, method);
568
569 method = aml_method("_S2D", 0, AML_NOTSERIALIZED);
570 aml_append(method, aml_return(aml_int(0)));
571 aml_append(dev, method);
572
573 method = aml_method("_S3D", 0, AML_NOTSERIALIZED);
574 aml_append(method, aml_return(aml_int(s3d)));
575 aml_append(dev, method);
576 } else if (hotplug_enabled_dev) {
577 /* add _SUN/_EJ0 to make slot hotpluggable */
578 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
579
580 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
581 aml_append(method,
582 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
583 );
584 aml_append(dev, method);
585
586 if (bsel) {
587 build_append_pcihp_notify_entry(notify_method, slot);
588 }
589 } else if (bridge_in_acpi) {
590 /*
591 * device is coldplugged bridge,
592 * add child device descriptions into its scope
593 */
594 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
595
596 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en);
597 }
598 /* slot descriptor has been composed, add it into parent context */
599 aml_append(parent_scope, dev);
600 }
601
602 if (bsel) {
603 aml_append(parent_scope, notify_method);
604 }
605
606 /* Append PCNT method to notify about events on local and child buses.
607 * Add unconditionally for root since DSDT expects it.
608 */
609 method = aml_method("PCNT", 0, AML_NOTSERIALIZED);
610
611 /* If bus supports hotplug select it and notify about local events */
612 if (bsel) {
613 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel));
614 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM")));
615 aml_append(method,
616 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */)
617 );
618 aml_append(method,
619 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */)
620 );
621 }
622
623 /* Notify about child bus events in any case */
624 if (pcihp_bridge_en) {
625 QLIST_FOREACH(sec, &bus->child, sibling) {
626 int32_t devfn = sec->parent_dev->devfn;
627
628 if (pci_bus_is_root(sec) || pci_bus_is_express(sec)) {
629 continue;
630 }
631
632 aml_append(method, aml_name("^S%.02X.PCNT", devfn));
633 }
634 }
635 aml_append(parent_scope, method);
636 qobject_decref(bsel);
637 }
638
639 /**
640 * build_prt_entry:
641 * @link_name: link name for PCI route entry
642 *
643 * build AML package containing a PCI route entry for @link_name
644 */
645 static Aml *build_prt_entry(const char *link_name)
646 {
647 Aml *a_zero = aml_int(0);
648 Aml *pkg = aml_package(4);
649 aml_append(pkg, a_zero);
650 aml_append(pkg, a_zero);
651 aml_append(pkg, aml_name("%s", link_name));
652 aml_append(pkg, a_zero);
653 return pkg;
654 }
655
656 /*
657 * initialize_route - Initialize the interrupt routing rule
658 * through a specific LINK:
659 * if (lnk_idx == idx)
660 * route using link 'link_name'
661 */
662 static Aml *initialize_route(Aml *route, const char *link_name,
663 Aml *lnk_idx, int idx)
664 {
665 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx)));
666 Aml *pkg = build_prt_entry(link_name);
667
668 aml_append(if_ctx, aml_store(pkg, route));
669
670 return if_ctx;
671 }
672
673 /*
674 * build_prt - Define interrupt rounting rules
675 *
676 * Returns an array of 128 routes, one for each device,
677 * based on device location.
678 * The main goal is to equaly distribute the interrupts
679 * over the 4 existing ACPI links (works only for i440fx).
680 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]".
681 *
682 */
683 static Aml *build_prt(bool is_pci0_prt)
684 {
685 Aml *method, *while_ctx, *pin, *res;
686
687 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
688 res = aml_local(0);
689 pin = aml_local(1);
690 aml_append(method, aml_store(aml_package(128), res));
691 aml_append(method, aml_store(aml_int(0), pin));
692
693 /* while (pin < 128) */
694 while_ctx = aml_while(aml_lless(pin, aml_int(128)));
695 {
696 Aml *slot = aml_local(2);
697 Aml *lnk_idx = aml_local(3);
698 Aml *route = aml_local(4);
699
700 /* slot = pin >> 2 */
701 aml_append(while_ctx,
702 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot));
703 /* lnk_idx = (slot + pin) & 3 */
704 aml_append(while_ctx,
705 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL),
706 lnk_idx));
707
708 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */
709 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0));
710 if (is_pci0_prt) {
711 Aml *if_device_1, *if_pin_4, *else_pin_4;
712
713 /* device 1 is the power-management device, needs SCI */
714 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1)));
715 {
716 if_pin_4 = aml_if(aml_equal(pin, aml_int(4)));
717 {
718 aml_append(if_pin_4,
719 aml_store(build_prt_entry("LNKS"), route));
720 }
721 aml_append(if_device_1, if_pin_4);
722 else_pin_4 = aml_else();
723 {
724 aml_append(else_pin_4,
725 aml_store(build_prt_entry("LNKA"), route));
726 }
727 aml_append(if_device_1, else_pin_4);
728 }
729 aml_append(while_ctx, if_device_1);
730 } else {
731 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1));
732 }
733 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2));
734 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3));
735
736 /* route[0] = 0x[slot]FFFF */
737 aml_append(while_ctx,
738 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF),
739 NULL),
740 aml_index(route, aml_int(0))));
741 /* route[1] = pin & 3 */
742 aml_append(while_ctx,
743 aml_store(aml_and(pin, aml_int(3), NULL),
744 aml_index(route, aml_int(1))));
745 /* res[pin] = route */
746 aml_append(while_ctx, aml_store(route, aml_index(res, pin)));
747 /* pin++ */
748 aml_append(while_ctx, aml_increment(pin));
749 }
750 aml_append(method, while_ctx);
751 /* return res*/
752 aml_append(method, aml_return(res));
753
754 return method;
755 }
756
757 typedef struct CrsRangeEntry {
758 uint64_t base;
759 uint64_t limit;
760 } CrsRangeEntry;
761
762 static void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit)
763 {
764 CrsRangeEntry *entry;
765
766 entry = g_malloc(sizeof(*entry));
767 entry->base = base;
768 entry->limit = limit;
769
770 g_ptr_array_add(ranges, entry);
771 }
772
773 static void crs_range_free(gpointer data)
774 {
775 CrsRangeEntry *entry = (CrsRangeEntry *)data;
776 g_free(entry);
777 }
778
779 typedef struct CrsRangeSet {
780 GPtrArray *io_ranges;
781 GPtrArray *mem_ranges;
782 GPtrArray *mem_64bit_ranges;
783 } CrsRangeSet;
784
785 static void crs_range_set_init(CrsRangeSet *range_set)
786 {
787 range_set->io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
788 range_set->mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
789 range_set->mem_64bit_ranges =
790 g_ptr_array_new_with_free_func(crs_range_free);
791 }
792
793 static void crs_range_set_free(CrsRangeSet *range_set)
794 {
795 g_ptr_array_free(range_set->io_ranges, true);
796 g_ptr_array_free(range_set->mem_ranges, true);
797 g_ptr_array_free(range_set->mem_64bit_ranges, true);
798 }
799
800 static gint crs_range_compare(gconstpointer a, gconstpointer b)
801 {
802 CrsRangeEntry *entry_a = *(CrsRangeEntry **)a;
803 CrsRangeEntry *entry_b = *(CrsRangeEntry **)b;
804
805 return (int64_t)entry_a->base - (int64_t)entry_b->base;
806 }
807
808 /*
809 * crs_replace_with_free_ranges - given the 'used' ranges within [start - end]
810 * interval, computes the 'free' ranges from the same interval.
811 * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function
812 * will return { [base - a1], [a2 - b1], [b2 - limit] }.
813 */
814 static void crs_replace_with_free_ranges(GPtrArray *ranges,
815 uint64_t start, uint64_t end)
816 {
817 GPtrArray *free_ranges = g_ptr_array_new();
818 uint64_t free_base = start;
819 int i;
820
821 g_ptr_array_sort(ranges, crs_range_compare);
822 for (i = 0; i < ranges->len; i++) {
823 CrsRangeEntry *used = g_ptr_array_index(ranges, i);
824
825 if (free_base < used->base) {
826 crs_range_insert(free_ranges, free_base, used->base - 1);
827 }
828
829 free_base = used->limit + 1;
830 }
831
832 if (free_base < end) {
833 crs_range_insert(free_ranges, free_base, end);
834 }
835
836 g_ptr_array_set_size(ranges, 0);
837 for (i = 0; i < free_ranges->len; i++) {
838 g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i));
839 }
840
841 g_ptr_array_free(free_ranges, true);
842 }
843
844 /*
845 * crs_range_merge - merges adjacent ranges in the given array.
846 * Array elements are deleted and replaced with the merged ranges.
847 */
848 static void crs_range_merge(GPtrArray *range)
849 {
850 GPtrArray *tmp = g_ptr_array_new_with_free_func(crs_range_free);
851 CrsRangeEntry *entry;
852 uint64_t range_base, range_limit;
853 int i;
854
855 if (!range->len) {
856 return;
857 }
858
859 g_ptr_array_sort(range, crs_range_compare);
860
861 entry = g_ptr_array_index(range, 0);
862 range_base = entry->base;
863 range_limit = entry->limit;
864 for (i = 1; i < range->len; i++) {
865 entry = g_ptr_array_index(range, i);
866 if (entry->base - 1 == range_limit) {
867 range_limit = entry->limit;
868 } else {
869 crs_range_insert(tmp, range_base, range_limit);
870 range_base = entry->base;
871 range_limit = entry->limit;
872 }
873 }
874 crs_range_insert(tmp, range_base, range_limit);
875
876 g_ptr_array_set_size(range, 0);
877 for (i = 0; i < tmp->len; i++) {
878 entry = g_ptr_array_index(tmp, i);
879 crs_range_insert(range, entry->base, entry->limit);
880 }
881 g_ptr_array_free(tmp, true);
882 }
883
884 static Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set)
885 {
886 Aml *crs = aml_resource_template();
887 CrsRangeSet temp_range_set;
888 CrsRangeEntry *entry;
889 uint8_t max_bus = pci_bus_num(host->bus);
890 uint8_t type;
891 int devfn;
892 int i;
893
894 crs_range_set_init(&temp_range_set);
895 for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) {
896 uint64_t range_base, range_limit;
897 PCIDevice *dev = host->bus->devices[devfn];
898
899 if (!dev) {
900 continue;
901 }
902
903 for (i = 0; i < PCI_NUM_REGIONS; i++) {
904 PCIIORegion *r = &dev->io_regions[i];
905
906 range_base = r->addr;
907 range_limit = r->addr + r->size - 1;
908
909 /*
910 * Work-around for old bioses
911 * that do not support multiple root buses
912 */
913 if (!range_base || range_base > range_limit) {
914 continue;
915 }
916
917 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
918 crs_range_insert(temp_range_set.io_ranges,
919 range_base, range_limit);
920 } else { /* "memory" */
921 crs_range_insert(temp_range_set.mem_ranges,
922 range_base, range_limit);
923 }
924 }
925
926 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
927 if (type == PCI_HEADER_TYPE_BRIDGE) {
928 uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS];
929 if (subordinate > max_bus) {
930 max_bus = subordinate;
931 }
932
933 range_base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
934 range_limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
935
936 /*
937 * Work-around for old bioses
938 * that do not support multiple root buses
939 */
940 if (range_base && range_base <= range_limit) {
941 crs_range_insert(temp_range_set.io_ranges,
942 range_base, range_limit);
943 }
944
945 range_base =
946 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
947 range_limit =
948 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
949
950 /*
951 * Work-around for old bioses
952 * that do not support multiple root buses
953 */
954 if (range_base && range_base <= range_limit) {
955 uint64_t length = range_limit - range_base + 1;
956 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) {
957 crs_range_insert(temp_range_set.mem_ranges,
958 range_base, range_limit);
959 } else {
960 crs_range_insert(temp_range_set.mem_64bit_ranges,
961 range_base, range_limit);
962 }
963 }
964
965 range_base =
966 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
967 range_limit =
968 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
969
970 /*
971 * Work-around for old bioses
972 * that do not support multiple root buses
973 */
974 if (range_base && range_base <= range_limit) {
975 uint64_t length = range_limit - range_base + 1;
976 if (range_limit <= UINT32_MAX && length <= UINT32_MAX) {
977 crs_range_insert(temp_range_set.mem_ranges,
978 range_base, range_limit);
979 } else {
980 crs_range_insert(temp_range_set.mem_64bit_ranges,
981 range_base, range_limit);
982 }
983 }
984 }
985 }
986
987 crs_range_merge(temp_range_set.io_ranges);
988 for (i = 0; i < temp_range_set.io_ranges->len; i++) {
989 entry = g_ptr_array_index(temp_range_set.io_ranges, i);
990 aml_append(crs,
991 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
992 AML_POS_DECODE, AML_ENTIRE_RANGE,
993 0, entry->base, entry->limit, 0,
994 entry->limit - entry->base + 1));
995 crs_range_insert(range_set->io_ranges, entry->base, entry->limit);
996 }
997
998 crs_range_merge(temp_range_set.mem_ranges);
999 for (i = 0; i < temp_range_set.mem_ranges->len; i++) {
1000 entry = g_ptr_array_index(temp_range_set.mem_ranges, i);
1001 aml_append(crs,
1002 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED,
1003 AML_MAX_FIXED, AML_NON_CACHEABLE,
1004 AML_READ_WRITE,
1005 0, entry->base, entry->limit, 0,
1006 entry->limit - entry->base + 1));
1007 crs_range_insert(range_set->mem_ranges, entry->base, entry->limit);
1008 }
1009
1010 crs_range_merge(temp_range_set.mem_64bit_ranges);
1011 for (i = 0; i < temp_range_set.mem_64bit_ranges->len; i++) {
1012 entry = g_ptr_array_index(temp_range_set.mem_64bit_ranges, i);
1013 aml_append(crs,
1014 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
1015 AML_MAX_FIXED, AML_NON_CACHEABLE,
1016 AML_READ_WRITE,
1017 0, entry->base, entry->limit, 0,
1018 entry->limit - entry->base + 1));
1019 crs_range_insert(range_set->mem_64bit_ranges,
1020 entry->base, entry->limit);
1021 }
1022
1023 crs_range_set_free(&temp_range_set);
1024
1025 aml_append(crs,
1026 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
1027 0,
1028 pci_bus_num(host->bus),
1029 max_bus,
1030 0,
1031 max_bus - pci_bus_num(host->bus) + 1));
1032
1033 return crs;
1034 }
1035
1036 static void build_hpet_aml(Aml *table)
1037 {
1038 Aml *crs;
1039 Aml *field;
1040 Aml *method;
1041 Aml *if_ctx;
1042 Aml *scope = aml_scope("_SB");
1043 Aml *dev = aml_device("HPET");
1044 Aml *zero = aml_int(0);
1045 Aml *id = aml_local(0);
1046 Aml *period = aml_local(1);
1047
1048 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103")));
1049 aml_append(dev, aml_name_decl("_UID", zero));
1050
1051 aml_append(dev,
1052 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE),
1053 HPET_LEN));
1054 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE);
1055 aml_append(field, aml_named_field("VEND", 32));
1056 aml_append(field, aml_named_field("PRD", 32));
1057 aml_append(dev, field);
1058
1059 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1060 aml_append(method, aml_store(aml_name("VEND"), id));
1061 aml_append(method, aml_store(aml_name("PRD"), period));
1062 aml_append(method, aml_shiftright(id, aml_int(16), id));
1063 if_ctx = aml_if(aml_lor(aml_equal(id, zero),
1064 aml_equal(id, aml_int(0xffff))));
1065 {
1066 aml_append(if_ctx, aml_return(zero));
1067 }
1068 aml_append(method, if_ctx);
1069
1070 if_ctx = aml_if(aml_lor(aml_equal(period, zero),
1071 aml_lgreater(period, aml_int(100000000))));
1072 {
1073 aml_append(if_ctx, aml_return(zero));
1074 }
1075 aml_append(method, if_ctx);
1076
1077 aml_append(method, aml_return(aml_int(0x0F)));
1078 aml_append(dev, method);
1079
1080 crs = aml_resource_template();
1081 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY));
1082 aml_append(dev, aml_name_decl("_CRS", crs));
1083
1084 aml_append(scope, dev);
1085 aml_append(table, scope);
1086 }
1087
1088 static Aml *build_fdinfo_aml(int idx, FloppyDriveType type)
1089 {
1090 Aml *dev, *fdi;
1091 uint8_t maxc, maxh, maxs;
1092
1093 isa_fdc_get_drive_max_chs(type, &maxc, &maxh, &maxs);
1094
1095 dev = aml_device("FLP%c", 'A' + idx);
1096
1097 aml_append(dev, aml_name_decl("_ADR", aml_int(idx)));
1098
1099 fdi = aml_package(16);
1100 aml_append(fdi, aml_int(idx)); /* Drive Number */
1101 aml_append(fdi,
1102 aml_int(cmos_get_fd_drive_type(type))); /* Device Type */
1103 /*
1104 * the values below are the limits of the drive, and are thus independent
1105 * of the inserted media
1106 */
1107 aml_append(fdi, aml_int(maxc)); /* Maximum Cylinder Number */
1108 aml_append(fdi, aml_int(maxs)); /* Maximum Sector Number */
1109 aml_append(fdi, aml_int(maxh)); /* Maximum Head Number */
1110 /*
1111 * SeaBIOS returns the below values for int 0x13 func 0x08 regardless of
1112 * the drive type, so shall we
1113 */
1114 aml_append(fdi, aml_int(0xAF)); /* disk_specify_1 */
1115 aml_append(fdi, aml_int(0x02)); /* disk_specify_2 */
1116 aml_append(fdi, aml_int(0x25)); /* disk_motor_wait */
1117 aml_append(fdi, aml_int(0x02)); /* disk_sector_siz */
1118 aml_append(fdi, aml_int(0x12)); /* disk_eot */
1119 aml_append(fdi, aml_int(0x1B)); /* disk_rw_gap */
1120 aml_append(fdi, aml_int(0xFF)); /* disk_dtl */
1121 aml_append(fdi, aml_int(0x6C)); /* disk_formt_gap */
1122 aml_append(fdi, aml_int(0xF6)); /* disk_fill */
1123 aml_append(fdi, aml_int(0x0F)); /* disk_head_sttl */
1124 aml_append(fdi, aml_int(0x08)); /* disk_motor_strt */
1125
1126 aml_append(dev, aml_name_decl("_FDI", fdi));
1127 return dev;
1128 }
1129
1130 static Aml *build_fdc_device_aml(ISADevice *fdc)
1131 {
1132 int i;
1133 Aml *dev;
1134 Aml *crs;
1135
1136 #define ACPI_FDE_MAX_FD 4
1137 uint32_t fde_buf[5] = {
1138 0, 0, 0, 0, /* presence of floppy drives #0 - #3 */
1139 cpu_to_le32(2) /* tape presence (2 == never present) */
1140 };
1141
1142 dev = aml_device("FDC0");
1143 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0700")));
1144
1145 crs = aml_resource_template();
1146 aml_append(crs, aml_io(AML_DECODE16, 0x03F2, 0x03F2, 0x00, 0x04));
1147 aml_append(crs, aml_io(AML_DECODE16, 0x03F7, 0x03F7, 0x00, 0x01));
1148 aml_append(crs, aml_irq_no_flags(6));
1149 aml_append(crs,
1150 aml_dma(AML_COMPATIBILITY, AML_NOTBUSMASTER, AML_TRANSFER8, 2));
1151 aml_append(dev, aml_name_decl("_CRS", crs));
1152
1153 for (i = 0; i < MIN(MAX_FD, ACPI_FDE_MAX_FD); i++) {
1154 FloppyDriveType type = isa_fdc_get_drive_type(fdc, i);
1155
1156 if (type < FLOPPY_DRIVE_TYPE_NONE) {
1157 fde_buf[i] = cpu_to_le32(1); /* drive present */
1158 aml_append(dev, build_fdinfo_aml(i, type));
1159 }
1160 }
1161 aml_append(dev, aml_name_decl("_FDE",
1162 aml_buffer(sizeof(fde_buf), (uint8_t *)fde_buf)));
1163
1164 return dev;
1165 }
1166
1167 static Aml *build_rtc_device_aml(void)
1168 {
1169 Aml *dev;
1170 Aml *crs;
1171
1172 dev = aml_device("RTC");
1173 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0B00")));
1174 crs = aml_resource_template();
1175 aml_append(crs, aml_io(AML_DECODE16, 0x0070, 0x0070, 0x10, 0x02));
1176 aml_append(crs, aml_irq_no_flags(8));
1177 aml_append(crs, aml_io(AML_DECODE16, 0x0072, 0x0072, 0x02, 0x06));
1178 aml_append(dev, aml_name_decl("_CRS", crs));
1179
1180 return dev;
1181 }
1182
1183 static Aml *build_kbd_device_aml(void)
1184 {
1185 Aml *dev;
1186 Aml *crs;
1187 Aml *method;
1188
1189 dev = aml_device("KBD");
1190 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0303")));
1191
1192 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1193 aml_append(method, aml_return(aml_int(0x0f)));
1194 aml_append(dev, method);
1195
1196 crs = aml_resource_template();
1197 aml_append(crs, aml_io(AML_DECODE16, 0x0060, 0x0060, 0x01, 0x01));
1198 aml_append(crs, aml_io(AML_DECODE16, 0x0064, 0x0064, 0x01, 0x01));
1199 aml_append(crs, aml_irq_no_flags(1));
1200 aml_append(dev, aml_name_decl("_CRS", crs));
1201
1202 return dev;
1203 }
1204
1205 static Aml *build_mouse_device_aml(void)
1206 {
1207 Aml *dev;
1208 Aml *crs;
1209 Aml *method;
1210
1211 dev = aml_device("MOU");
1212 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0F13")));
1213
1214 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1215 aml_append(method, aml_return(aml_int(0x0f)));
1216 aml_append(dev, method);
1217
1218 crs = aml_resource_template();
1219 aml_append(crs, aml_irq_no_flags(12));
1220 aml_append(dev, aml_name_decl("_CRS", crs));
1221
1222 return dev;
1223 }
1224
1225 static Aml *build_lpt_device_aml(void)
1226 {
1227 Aml *dev;
1228 Aml *crs;
1229 Aml *method;
1230 Aml *if_ctx;
1231 Aml *else_ctx;
1232 Aml *zero = aml_int(0);
1233 Aml *is_present = aml_local(0);
1234
1235 dev = aml_device("LPT");
1236 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0400")));
1237
1238 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1239 aml_append(method, aml_store(aml_name("LPEN"), is_present));
1240 if_ctx = aml_if(aml_equal(is_present, zero));
1241 {
1242 aml_append(if_ctx, aml_return(aml_int(0x00)));
1243 }
1244 aml_append(method, if_ctx);
1245 else_ctx = aml_else();
1246 {
1247 aml_append(else_ctx, aml_return(aml_int(0x0f)));
1248 }
1249 aml_append(method, else_ctx);
1250 aml_append(dev, method);
1251
1252 crs = aml_resource_template();
1253 aml_append(crs, aml_io(AML_DECODE16, 0x0378, 0x0378, 0x08, 0x08));
1254 aml_append(crs, aml_irq_no_flags(7));
1255 aml_append(dev, aml_name_decl("_CRS", crs));
1256
1257 return dev;
1258 }
1259
1260 static Aml *build_com_device_aml(uint8_t uid)
1261 {
1262 Aml *dev;
1263 Aml *crs;
1264 Aml *method;
1265 Aml *if_ctx;
1266 Aml *else_ctx;
1267 Aml *zero = aml_int(0);
1268 Aml *is_present = aml_local(0);
1269 const char *enabled_field = "CAEN";
1270 uint8_t irq = 4;
1271 uint16_t io_port = 0x03F8;
1272
1273 assert(uid == 1 || uid == 2);
1274 if (uid == 2) {
1275 enabled_field = "CBEN";
1276 irq = 3;
1277 io_port = 0x02F8;
1278 }
1279
1280 dev = aml_device("COM%d", uid);
1281 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0501")));
1282 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1283
1284 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1285 aml_append(method, aml_store(aml_name("%s", enabled_field), is_present));
1286 if_ctx = aml_if(aml_equal(is_present, zero));
1287 {
1288 aml_append(if_ctx, aml_return(aml_int(0x00)));
1289 }
1290 aml_append(method, if_ctx);
1291 else_ctx = aml_else();
1292 {
1293 aml_append(else_ctx, aml_return(aml_int(0x0f)));
1294 }
1295 aml_append(method, else_ctx);
1296 aml_append(dev, method);
1297
1298 crs = aml_resource_template();
1299 aml_append(crs, aml_io(AML_DECODE16, io_port, io_port, 0x00, 0x08));
1300 aml_append(crs, aml_irq_no_flags(irq));
1301 aml_append(dev, aml_name_decl("_CRS", crs));
1302
1303 return dev;
1304 }
1305
1306 static void build_isa_devices_aml(Aml *table)
1307 {
1308 ISADevice *fdc = pc_find_fdc0();
1309 bool ambiguous;
1310
1311 Aml *scope = aml_scope("_SB.PCI0.ISA");
1312 Object *obj = object_resolve_path_type("", TYPE_ISA_BUS, &ambiguous);
1313
1314 aml_append(scope, build_rtc_device_aml());
1315 aml_append(scope, build_kbd_device_aml());
1316 aml_append(scope, build_mouse_device_aml());
1317 if (fdc) {
1318 aml_append(scope, build_fdc_device_aml(fdc));
1319 }
1320 aml_append(scope, build_lpt_device_aml());
1321 aml_append(scope, build_com_device_aml(1));
1322 aml_append(scope, build_com_device_aml(2));
1323
1324 if (ambiguous) {
1325 error_report("Multiple ISA busses, unable to define IPMI ACPI data");
1326 } else if (!obj) {
1327 error_report("No ISA bus, unable to define IPMI ACPI data");
1328 } else {
1329 build_acpi_ipmi_devices(scope, BUS(obj));
1330 }
1331
1332 aml_append(table, scope);
1333 }
1334
1335 static void build_dbg_aml(Aml *table)
1336 {
1337 Aml *field;
1338 Aml *method;
1339 Aml *while_ctx;
1340 Aml *scope = aml_scope("\\");
1341 Aml *buf = aml_local(0);
1342 Aml *len = aml_local(1);
1343 Aml *idx = aml_local(2);
1344
1345 aml_append(scope,
1346 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01));
1347 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1348 aml_append(field, aml_named_field("DBGB", 8));
1349 aml_append(scope, field);
1350
1351 method = aml_method("DBUG", 1, AML_NOTSERIALIZED);
1352
1353 aml_append(method, aml_to_hexstring(aml_arg(0), buf));
1354 aml_append(method, aml_to_buffer(buf, buf));
1355 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len));
1356 aml_append(method, aml_store(aml_int(0), idx));
1357
1358 while_ctx = aml_while(aml_lless(idx, len));
1359 aml_append(while_ctx,
1360 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB")));
1361 aml_append(while_ctx, aml_increment(idx));
1362 aml_append(method, while_ctx);
1363
1364 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB")));
1365 aml_append(scope, method);
1366
1367 aml_append(table, scope);
1368 }
1369
1370 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg)
1371 {
1372 Aml *dev;
1373 Aml *crs;
1374 Aml *method;
1375 uint32_t irqs[] = {5, 10, 11};
1376
1377 dev = aml_device("%s", name);
1378 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1379 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1380
1381 crs = aml_resource_template();
1382 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1383 AML_SHARED, irqs, ARRAY_SIZE(irqs)));
1384 aml_append(dev, aml_name_decl("_PRS", crs));
1385
1386 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1387 aml_append(method, aml_return(aml_call1("IQST", reg)));
1388 aml_append(dev, method);
1389
1390 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1391 aml_append(method, aml_or(reg, aml_int(0x80), reg));
1392 aml_append(dev, method);
1393
1394 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1395 aml_append(method, aml_return(aml_call1("IQCR", reg)));
1396 aml_append(dev, method);
1397
1398 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1399 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
1400 aml_append(method, aml_store(aml_name("PRRI"), reg));
1401 aml_append(dev, method);
1402
1403 return dev;
1404 }
1405
1406 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi)
1407 {
1408 Aml *dev;
1409 Aml *crs;
1410 Aml *method;
1411 uint32_t irqs;
1412
1413 dev = aml_device("%s", name);
1414 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1415 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1416
1417 crs = aml_resource_template();
1418 irqs = gsi;
1419 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1420 AML_SHARED, &irqs, 1));
1421 aml_append(dev, aml_name_decl("_PRS", crs));
1422
1423 aml_append(dev, aml_name_decl("_CRS", crs));
1424
1425 /*
1426 * _DIS can be no-op because the interrupt cannot be disabled.
1427 */
1428 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1429 aml_append(dev, method);
1430
1431 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1432 aml_append(dev, method);
1433
1434 return dev;
1435 }
1436
1437 /* _CRS method - get current settings */
1438 static Aml *build_iqcr_method(bool is_piix4)
1439 {
1440 Aml *if_ctx;
1441 uint32_t irqs;
1442 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED);
1443 Aml *crs = aml_resource_template();
1444
1445 irqs = 0;
1446 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1447 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1));
1448 aml_append(method, aml_name_decl("PRR0", crs));
1449
1450 aml_append(method,
1451 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
1452
1453 if (is_piix4) {
1454 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
1455 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI")));
1456 aml_append(method, if_ctx);
1457 } else {
1458 aml_append(method,
1459 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL),
1460 aml_name("PRRI")));
1461 }
1462
1463 aml_append(method, aml_return(aml_name("PRR0")));
1464 return method;
1465 }
1466
1467 /* _STA method - get status */
1468 static Aml *build_irq_status_method(void)
1469 {
1470 Aml *if_ctx;
1471 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED);
1472
1473 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL));
1474 aml_append(if_ctx, aml_return(aml_int(0x09)));
1475 aml_append(method, if_ctx);
1476 aml_append(method, aml_return(aml_int(0x0B)));
1477 return method;
1478 }
1479
1480 static void build_piix4_pci0_int(Aml *table)
1481 {
1482 Aml *dev;
1483 Aml *crs;
1484 Aml *field;
1485 Aml *method;
1486 uint32_t irqs;
1487 Aml *sb_scope = aml_scope("_SB");
1488 Aml *pci0_scope = aml_scope("PCI0");
1489
1490 aml_append(pci0_scope, build_prt(true));
1491 aml_append(sb_scope, pci0_scope);
1492
1493 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1494 aml_append(field, aml_named_field("PRQ0", 8));
1495 aml_append(field, aml_named_field("PRQ1", 8));
1496 aml_append(field, aml_named_field("PRQ2", 8));
1497 aml_append(field, aml_named_field("PRQ3", 8));
1498 aml_append(sb_scope, field);
1499
1500 aml_append(sb_scope, build_irq_status_method());
1501 aml_append(sb_scope, build_iqcr_method(true));
1502
1503 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0")));
1504 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1")));
1505 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2")));
1506 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3")));
1507
1508 dev = aml_device("LNKS");
1509 {
1510 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1511 aml_append(dev, aml_name_decl("_UID", aml_int(4)));
1512
1513 crs = aml_resource_template();
1514 irqs = 9;
1515 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1516 AML_ACTIVE_HIGH, AML_SHARED,
1517 &irqs, 1));
1518 aml_append(dev, aml_name_decl("_PRS", crs));
1519
1520 /* The SCI cannot be disabled and is always attached to GSI 9,
1521 * so these are no-ops. We only need this link to override the
1522 * polarity to active high and match the content of the MADT.
1523 */
1524 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1525 aml_append(method, aml_return(aml_int(0x0b)));
1526 aml_append(dev, method);
1527
1528 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1529 aml_append(dev, method);
1530
1531 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1532 aml_append(method, aml_return(aml_name("_PRS")));
1533 aml_append(dev, method);
1534
1535 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1536 aml_append(dev, method);
1537 }
1538 aml_append(sb_scope, dev);
1539
1540 aml_append(table, sb_scope);
1541 }
1542
1543 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name)
1544 {
1545 int i;
1546 int head;
1547 Aml *pkg;
1548 char base = name[3] < 'E' ? 'A' : 'E';
1549 char *s = g_strdup(name);
1550 Aml *a_nr = aml_int((nr << 16) | 0xffff);
1551
1552 assert(strlen(s) == 4);
1553
1554 head = name[3] - base;
1555 for (i = 0; i < 4; i++) {
1556 if (head + i > 3) {
1557 head = i * -1;
1558 }
1559 s[3] = base + head + i;
1560 pkg = aml_package(4);
1561 aml_append(pkg, a_nr);
1562 aml_append(pkg, aml_int(i));
1563 aml_append(pkg, aml_name("%s", s));
1564 aml_append(pkg, aml_int(0));
1565 aml_append(ctx, pkg);
1566 }
1567 g_free(s);
1568 }
1569
1570 static Aml *build_q35_routing_table(const char *str)
1571 {
1572 int i;
1573 Aml *pkg;
1574 char *name = g_strdup_printf("%s ", str);
1575
1576 pkg = aml_package(128);
1577 for (i = 0; i < 0x18; i++) {
1578 name[3] = 'E' + (i & 0x3);
1579 append_q35_prt_entry(pkg, i, name);
1580 }
1581
1582 name[3] = 'E';
1583 append_q35_prt_entry(pkg, 0x18, name);
1584
1585 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */
1586 for (i = 0x0019; i < 0x1e; i++) {
1587 name[3] = 'A';
1588 append_q35_prt_entry(pkg, i, name);
1589 }
1590
1591 /* PCIe->PCI bridge. use PIRQ[E-H] */
1592 name[3] = 'E';
1593 append_q35_prt_entry(pkg, 0x1e, name);
1594 name[3] = 'A';
1595 append_q35_prt_entry(pkg, 0x1f, name);
1596
1597 g_free(name);
1598 return pkg;
1599 }
1600
1601 static void build_q35_pci0_int(Aml *table)
1602 {
1603 Aml *field;
1604 Aml *method;
1605 Aml *sb_scope = aml_scope("_SB");
1606 Aml *pci0_scope = aml_scope("PCI0");
1607
1608 /* Zero => PIC mode, One => APIC Mode */
1609 aml_append(table, aml_name_decl("PICF", aml_int(0)));
1610 method = aml_method("_PIC", 1, AML_NOTSERIALIZED);
1611 {
1612 aml_append(method, aml_store(aml_arg(0), aml_name("PICF")));
1613 }
1614 aml_append(table, method);
1615
1616 aml_append(pci0_scope,
1617 aml_name_decl("PRTP", build_q35_routing_table("LNK")));
1618 aml_append(pci0_scope,
1619 aml_name_decl("PRTA", build_q35_routing_table("GSI")));
1620
1621 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
1622 {
1623 Aml *if_ctx;
1624 Aml *else_ctx;
1625
1626 /* PCI IRQ routing table, example from ACPI 2.0a specification,
1627 section 6.2.8.1 */
1628 /* Note: we provide the same info as the PCI routing
1629 table of the Bochs BIOS */
1630 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0)));
1631 aml_append(if_ctx, aml_return(aml_name("PRTP")));
1632 aml_append(method, if_ctx);
1633 else_ctx = aml_else();
1634 aml_append(else_ctx, aml_return(aml_name("PRTA")));
1635 aml_append(method, else_ctx);
1636 }
1637 aml_append(pci0_scope, method);
1638 aml_append(sb_scope, pci0_scope);
1639
1640 field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1641 aml_append(field, aml_named_field("PRQA", 8));
1642 aml_append(field, aml_named_field("PRQB", 8));
1643 aml_append(field, aml_named_field("PRQC", 8));
1644 aml_append(field, aml_named_field("PRQD", 8));
1645 aml_append(field, aml_reserved_field(0x20));
1646 aml_append(field, aml_named_field("PRQE", 8));
1647 aml_append(field, aml_named_field("PRQF", 8));
1648 aml_append(field, aml_named_field("PRQG", 8));
1649 aml_append(field, aml_named_field("PRQH", 8));
1650 aml_append(sb_scope, field);
1651
1652 aml_append(sb_scope, build_irq_status_method());
1653 aml_append(sb_scope, build_iqcr_method(false));
1654
1655 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA")));
1656 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB")));
1657 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC")));
1658 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD")));
1659 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE")));
1660 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF")));
1661 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG")));
1662 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH")));
1663
1664 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10));
1665 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11));
1666 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12));
1667 aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13));
1668 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14));
1669 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15));
1670 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16));
1671 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17));
1672
1673 aml_append(table, sb_scope);
1674 }
1675
1676 static void build_q35_isa_bridge(Aml *table)
1677 {
1678 Aml *dev;
1679 Aml *scope;
1680 Aml *field;
1681
1682 scope = aml_scope("_SB.PCI0");
1683 dev = aml_device("ISA");
1684 aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000)));
1685
1686 /* ICH9 PCI to ISA irq remapping */
1687 aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG,
1688 aml_int(0x60), 0x0C));
1689
1690 aml_append(dev, aml_operation_region("LPCD", AML_PCI_CONFIG,
1691 aml_int(0x80), 0x02));
1692 field = aml_field("LPCD", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1693 aml_append(field, aml_named_field("COMA", 3));
1694 aml_append(field, aml_reserved_field(1));
1695 aml_append(field, aml_named_field("COMB", 3));
1696 aml_append(field, aml_reserved_field(1));
1697 aml_append(field, aml_named_field("LPTD", 2));
1698 aml_append(dev, field);
1699
1700 aml_append(dev, aml_operation_region("LPCE", AML_PCI_CONFIG,
1701 aml_int(0x82), 0x02));
1702 /* enable bits */
1703 field = aml_field("LPCE", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1704 aml_append(field, aml_named_field("CAEN", 1));
1705 aml_append(field, aml_named_field("CBEN", 1));
1706 aml_append(field, aml_named_field("LPEN", 1));
1707 aml_append(dev, field);
1708
1709 aml_append(scope, dev);
1710 aml_append(table, scope);
1711 }
1712
1713 static void build_piix4_pm(Aml *table)
1714 {
1715 Aml *dev;
1716 Aml *scope;
1717
1718 scope = aml_scope("_SB.PCI0");
1719 dev = aml_device("PX13");
1720 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010003)));
1721
1722 aml_append(dev, aml_operation_region("P13C", AML_PCI_CONFIG,
1723 aml_int(0x00), 0xff));
1724 aml_append(scope, dev);
1725 aml_append(table, scope);
1726 }
1727
1728 static void build_piix4_isa_bridge(Aml *table)
1729 {
1730 Aml *dev;
1731 Aml *scope;
1732 Aml *field;
1733
1734 scope = aml_scope("_SB.PCI0");
1735 dev = aml_device("ISA");
1736 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000)));
1737
1738 /* PIIX PCI to ISA irq remapping */
1739 aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG,
1740 aml_int(0x60), 0x04));
1741 /* enable bits */
1742 field = aml_field("^PX13.P13C", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1743 /* Offset(0x5f),, 7, */
1744 aml_append(field, aml_reserved_field(0x2f8));
1745 aml_append(field, aml_reserved_field(7));
1746 aml_append(field, aml_named_field("LPEN", 1));
1747 /* Offset(0x67),, 3, */
1748 aml_append(field, aml_reserved_field(0x38));
1749 aml_append(field, aml_reserved_field(3));
1750 aml_append(field, aml_named_field("CAEN", 1));
1751 aml_append(field, aml_reserved_field(3));
1752 aml_append(field, aml_named_field("CBEN", 1));
1753 aml_append(dev, field);
1754
1755 aml_append(scope, dev);
1756 aml_append(table, scope);
1757 }
1758
1759 static void build_piix4_pci_hotplug(Aml *table)
1760 {
1761 Aml *scope;
1762 Aml *field;
1763 Aml *method;
1764
1765 scope = aml_scope("_SB.PCI0");
1766
1767 aml_append(scope,
1768 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x08));
1769 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1770 aml_append(field, aml_named_field("PCIU", 32));
1771 aml_append(field, aml_named_field("PCID", 32));
1772 aml_append(scope, field);
1773
1774 aml_append(scope,
1775 aml_operation_region("SEJ", AML_SYSTEM_IO, aml_int(0xae08), 0x04));
1776 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1777 aml_append(field, aml_named_field("B0EJ", 32));
1778 aml_append(scope, field);
1779
1780 aml_append(scope,
1781 aml_operation_region("BNMR", AML_SYSTEM_IO, aml_int(0xae10), 0x04));
1782 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1783 aml_append(field, aml_named_field("BNUM", 32));
1784 aml_append(scope, field);
1785
1786 aml_append(scope, aml_mutex("BLCK", 0));
1787
1788 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED);
1789 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF));
1790 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM")));
1791 aml_append(method,
1792 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ")));
1793 aml_append(method, aml_release(aml_name("BLCK")));
1794 aml_append(method, aml_return(aml_int(0)));
1795 aml_append(scope, method);
1796
1797 aml_append(table, scope);
1798 }
1799
1800 static Aml *build_q35_osc_method(void)
1801 {
1802 Aml *if_ctx;
1803 Aml *if_ctx2;
1804 Aml *else_ctx;
1805 Aml *method;
1806 Aml *a_cwd1 = aml_name("CDW1");
1807 Aml *a_ctrl = aml_local(0);
1808
1809 method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
1810 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
1811
1812 if_ctx = aml_if(aml_equal(
1813 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
1814 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
1815 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
1816
1817 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl));
1818
1819 /*
1820 * Always allow native PME, AER (no dependencies)
1821 * Never allow SHPC (no SHPC controller in this system)
1822 */
1823 aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1D), a_ctrl));
1824
1825 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
1826 /* Unknown revision */
1827 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1));
1828 aml_append(if_ctx, if_ctx2);
1829
1830 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl)));
1831 /* Capabilities bits were masked */
1832 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1));
1833 aml_append(if_ctx, if_ctx2);
1834
1835 /* Update DWORD3 in the buffer */
1836 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3")));
1837 aml_append(method, if_ctx);
1838
1839 else_ctx = aml_else();
1840 /* Unrecognized UUID */
1841 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1));
1842 aml_append(method, else_ctx);
1843
1844 aml_append(method, aml_return(aml_arg(3)));
1845 return method;
1846 }
1847
1848 static void
1849 build_dsdt(GArray *table_data, BIOSLinker *linker,
1850 AcpiPmInfo *pm, AcpiMiscInfo *misc,
1851 Range *pci_hole, Range *pci_hole64, MachineState *machine)
1852 {
1853 CrsRangeEntry *entry;
1854 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs;
1855 CrsRangeSet crs_range_set;
1856 PCMachineState *pcms = PC_MACHINE(machine);
1857 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine);
1858 uint32_t nr_mem = machine->ram_slots;
1859 int root_bus_limit = 0xFF;
1860 PCIBus *bus = NULL;
1861 int i;
1862
1863 dsdt = init_aml_allocator();
1864
1865 /* Reserve space for header */
1866 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader));
1867
1868 build_dbg_aml(dsdt);
1869 if (misc->is_piix4) {
1870 sb_scope = aml_scope("_SB");
1871 dev = aml_device("PCI0");
1872 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1873 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1874 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
1875 aml_append(sb_scope, dev);
1876 aml_append(dsdt, sb_scope);
1877
1878 build_hpet_aml(dsdt);
1879 build_piix4_pm(dsdt);
1880 build_piix4_isa_bridge(dsdt);
1881 build_isa_devices_aml(dsdt);
1882 build_piix4_pci_hotplug(dsdt);
1883 build_piix4_pci0_int(dsdt);
1884 } else {
1885 sb_scope = aml_scope("_SB");
1886 aml_append(sb_scope,
1887 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x0c));
1888 aml_append(sb_scope,
1889 aml_operation_region("PCSB", AML_SYSTEM_IO, aml_int(0xae0c), 0x01));
1890 field = aml_field("PCSB", AML_ANY_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1891 aml_append(field, aml_named_field("PCIB", 8));
1892 aml_append(sb_scope, field);
1893 aml_append(dsdt, sb_scope);
1894
1895 sb_scope = aml_scope("_SB");
1896 dev = aml_device("PCI0");
1897 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1898 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1899 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1900 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
1901 aml_append(dev, build_q35_osc_method());
1902 aml_append(sb_scope, dev);
1903 aml_append(dsdt, sb_scope);
1904
1905 build_hpet_aml(dsdt);
1906 build_q35_isa_bridge(dsdt);
1907 build_isa_devices_aml(dsdt);
1908 build_q35_pci0_int(dsdt);
1909 }
1910
1911 if (pcmc->legacy_cpu_hotplug) {
1912 build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base);
1913 } else {
1914 CPUHotplugFeatures opts = {
1915 .apci_1_compatible = true, .has_legacy_cphp = true
1916 };
1917 build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base,
1918 "\\_SB.PCI0", "\\_GPE._E02");
1919 }
1920 build_memory_hotplug_aml(dsdt, nr_mem, "\\_SB.PCI0", "\\_GPE._E03");
1921
1922 scope = aml_scope("_GPE");
1923 {
1924 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006")));
1925
1926 if (misc->is_piix4) {
1927 method = aml_method("_E01", 0, AML_NOTSERIALIZED);
1928 aml_append(method,
1929 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
1930 aml_append(method, aml_call0("\\_SB.PCI0.PCNT"));
1931 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK")));
1932 aml_append(scope, method);
1933 }
1934
1935 if (pcms->acpi_nvdimm_state.is_enabled) {
1936 method = aml_method("_E04", 0, AML_NOTSERIALIZED);
1937 aml_append(method, aml_notify(aml_name("\\_SB.NVDR"),
1938 aml_int(0x80)));
1939 aml_append(scope, method);
1940 }
1941 }
1942 aml_append(dsdt, scope);
1943
1944 crs_range_set_init(&crs_range_set);
1945 bus = PC_MACHINE(machine)->bus;
1946 if (bus) {
1947 QLIST_FOREACH(bus, &bus->child, sibling) {
1948 uint8_t bus_num = pci_bus_num(bus);
1949 uint8_t numa_node = pci_bus_numa_node(bus);
1950
1951 /* look only for expander root buses */
1952 if (!pci_bus_is_root(bus)) {
1953 continue;
1954 }
1955
1956 if (bus_num < root_bus_limit) {
1957 root_bus_limit = bus_num - 1;
1958 }
1959
1960 scope = aml_scope("\\_SB");
1961 dev = aml_device("PC%.02X", bus_num);
1962 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
1963 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1964 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
1965 if (pci_bus_is_express(bus)) {
1966 aml_append(dev, build_q35_osc_method());
1967 }
1968
1969 if (numa_node != NUMA_NODE_UNASSIGNED) {
1970 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node)));
1971 }
1972
1973 aml_append(dev, build_prt(false));
1974 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set);
1975 aml_append(dev, aml_name_decl("_CRS", crs));
1976 aml_append(scope, dev);
1977 aml_append(dsdt, scope);
1978 }
1979 }
1980
1981 scope = aml_scope("\\_SB.PCI0");
1982 /* build PCI0._CRS */
1983 crs = aml_resource_template();
1984 aml_append(crs,
1985 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
1986 0x0000, 0x0, root_bus_limit,
1987 0x0000, root_bus_limit + 1));
1988 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08));
1989
1990 aml_append(crs,
1991 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1992 AML_POS_DECODE, AML_ENTIRE_RANGE,
1993 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
1994
1995 crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF);
1996 for (i = 0; i < crs_range_set.io_ranges->len; i++) {
1997 entry = g_ptr_array_index(crs_range_set.io_ranges, i);
1998 aml_append(crs,
1999 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
2000 AML_POS_DECODE, AML_ENTIRE_RANGE,
2001 0x0000, entry->base, entry->limit,
2002 0x0000, entry->limit - entry->base + 1));
2003 }
2004
2005 aml_append(crs,
2006 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
2007 AML_CACHEABLE, AML_READ_WRITE,
2008 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
2009
2010 crs_replace_with_free_ranges(crs_range_set.mem_ranges,
2011 range_lob(pci_hole),
2012 range_upb(pci_hole));
2013 for (i = 0; i < crs_range_set.mem_ranges->len; i++) {
2014 entry = g_ptr_array_index(crs_range_set.mem_ranges, i);
2015 aml_append(crs,
2016 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
2017 AML_NON_CACHEABLE, AML_READ_WRITE,
2018 0, entry->base, entry->limit,
2019 0, entry->limit - entry->base + 1));
2020 }
2021
2022 if (!range_is_empty(pci_hole64)) {
2023 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges,
2024 range_lob(pci_hole64),
2025 range_upb(pci_hole64));
2026 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) {
2027 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i);
2028 aml_append(crs,
2029 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED,
2030 AML_MAX_FIXED,
2031 AML_CACHEABLE, AML_READ_WRITE,
2032 0, entry->base, entry->limit,
2033 0, entry->limit - entry->base + 1));
2034 }
2035 }
2036
2037 if (misc->tpm_version != TPM_VERSION_UNSPEC) {
2038 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
2039 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
2040 }
2041 aml_append(scope, aml_name_decl("_CRS", crs));
2042
2043 /* reserve GPE0 block resources */
2044 dev = aml_device("GPE0");
2045 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
2046 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources")));
2047 /* device present, functioning, decoding, not shown in UI */
2048 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2049 crs = aml_resource_template();
2050 aml_append(crs,
2051 aml_io(AML_DECODE16, pm->gpe0_blk, pm->gpe0_blk, 1, pm->gpe0_blk_len)
2052 );
2053 aml_append(dev, aml_name_decl("_CRS", crs));
2054 aml_append(scope, dev);
2055
2056 crs_range_set_free(&crs_range_set);
2057
2058 /* reserve PCIHP resources */
2059 if (pm->pcihp_io_len) {
2060 dev = aml_device("PHPR");
2061 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
2062 aml_append(dev,
2063 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
2064 /* device present, functioning, decoding, not shown in UI */
2065 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2066 crs = aml_resource_template();
2067 aml_append(crs,
2068 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1,
2069 pm->pcihp_io_len)
2070 );
2071 aml_append(dev, aml_name_decl("_CRS", crs));
2072 aml_append(scope, dev);
2073 }
2074 aml_append(dsdt, scope);
2075
2076 /* create S3_ / S4_ / S5_ packages if necessary */
2077 scope = aml_scope("\\");
2078 if (!pm->s3_disabled) {
2079 pkg = aml_package(4);
2080 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */
2081 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2082 aml_append(pkg, aml_int(0)); /* reserved */
2083 aml_append(pkg, aml_int(0)); /* reserved */
2084 aml_append(scope, aml_name_decl("_S3", pkg));
2085 }
2086
2087 if (!pm->s4_disabled) {
2088 pkg = aml_package(4);
2089 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */
2090 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2091 aml_append(pkg, aml_int(pm->s4_val));
2092 aml_append(pkg, aml_int(0)); /* reserved */
2093 aml_append(pkg, aml_int(0)); /* reserved */
2094 aml_append(scope, aml_name_decl("_S4", pkg));
2095 }
2096
2097 pkg = aml_package(4);
2098 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */
2099 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
2100 aml_append(pkg, aml_int(0)); /* reserved */
2101 aml_append(pkg, aml_int(0)); /* reserved */
2102 aml_append(scope, aml_name_decl("_S5", pkg));
2103 aml_append(dsdt, scope);
2104
2105 /* create fw_cfg node, unconditionally */
2106 {
2107 /* when using port i/o, the 8-bit data register *always* overlaps
2108 * with half of the 16-bit control register. Hence, the total size
2109 * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the
2110 * DMA control register is located at FW_CFG_DMA_IO_BASE + 4 */
2111 uint8_t io_size = object_property_get_bool(OBJECT(pcms->fw_cfg),
2112 "dma_enabled", NULL) ?
2113 ROUND_UP(FW_CFG_CTL_SIZE, 4) + sizeof(dma_addr_t) :
2114 FW_CFG_CTL_SIZE;
2115
2116 scope = aml_scope("\\_SB.PCI0");
2117 dev = aml_device("FWCF");
2118
2119 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
2120
2121 /* device present, functioning, decoding, not shown in UI */
2122 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2123
2124 crs = aml_resource_template();
2125 aml_append(crs,
2126 aml_io(AML_DECODE16, FW_CFG_IO_BASE, FW_CFG_IO_BASE, 0x01, io_size)
2127 );
2128 aml_append(dev, aml_name_decl("_CRS", crs));
2129
2130 aml_append(scope, dev);
2131 aml_append(dsdt, scope);
2132 }
2133
2134 if (misc->applesmc_io_base) {
2135 scope = aml_scope("\\_SB.PCI0.ISA");
2136 dev = aml_device("SMC");
2137
2138 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001")));
2139 /* device present, functioning, decoding, not shown in UI */
2140 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2141
2142 crs = aml_resource_template();
2143 aml_append(crs,
2144 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base,
2145 0x01, APPLESMC_MAX_DATA_LENGTH)
2146 );
2147 aml_append(crs, aml_irq_no_flags(6));
2148 aml_append(dev, aml_name_decl("_CRS", crs));
2149
2150 aml_append(scope, dev);
2151 aml_append(dsdt, scope);
2152 }
2153
2154 if (misc->pvpanic_port) {
2155 scope = aml_scope("\\_SB.PCI0.ISA");
2156
2157 dev = aml_device("PEVT");
2158 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001")));
2159
2160 crs = aml_resource_template();
2161 aml_append(crs,
2162 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1)
2163 );
2164 aml_append(dev, aml_name_decl("_CRS", crs));
2165
2166 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO,
2167 aml_int(misc->pvpanic_port), 1));
2168 field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
2169 aml_append(field, aml_named_field("PEPT", 8));
2170 aml_append(dev, field);
2171
2172 /* device present, functioning, decoding, shown in UI */
2173 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
2174
2175 method = aml_method("RDPT", 0, AML_NOTSERIALIZED);
2176 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0)));
2177 aml_append(method, aml_return(aml_local(0)));
2178 aml_append(dev, method);
2179
2180 method = aml_method("WRPT", 1, AML_NOTSERIALIZED);
2181 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT")));
2182 aml_append(dev, method);
2183
2184 aml_append(scope, dev);
2185 aml_append(dsdt, scope);
2186 }
2187
2188 sb_scope = aml_scope("\\_SB");
2189 {
2190 Object *pci_host;
2191 PCIBus *bus = NULL;
2192
2193 pci_host = acpi_get_i386_pci_host();
2194 if (pci_host) {
2195 bus = PCI_HOST_BRIDGE(pci_host)->bus;
2196 }
2197
2198 if (bus) {
2199 Aml *scope = aml_scope("PCI0");
2200 /* Scan all PCI buses. Generate tables to support hotplug. */
2201 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en);
2202
2203 if (misc->tpm_version != TPM_VERSION_UNSPEC) {
2204 dev = aml_device("ISA.TPM");
2205 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C31")));
2206 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
2207 crs = aml_resource_template();
2208 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
2209 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
2210 /*
2211 FIXME: TPM_TIS_IRQ=5 conflicts with PNP0C0F irqs,
2212 Rewrite to take IRQ from TPM device model and
2213 fix default IRQ value there to use some unused IRQ
2214 */
2215 /* aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ)); */
2216 aml_append(dev, aml_name_decl("_CRS", crs));
2217 aml_append(scope, dev);
2218 }
2219
2220 aml_append(sb_scope, scope);
2221 }
2222 }
2223 aml_append(dsdt, sb_scope);
2224
2225 /* copy AML table into ACPI tables blob and patch header there */
2226 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
2227 build_header(linker, table_data,
2228 (void *)(table_data->data + table_data->len - dsdt->buf->len),
2229 "DSDT", dsdt->buf->len, 1, NULL, NULL);
2230 free_aml_allocator();
2231 }
2232
2233 static void
2234 build_hpet(GArray *table_data, BIOSLinker *linker)
2235 {
2236 Acpi20Hpet *hpet;
2237
2238 hpet = acpi_data_push(table_data, sizeof(*hpet));
2239 /* Note timer_block_id value must be kept in sync with value advertised by
2240 * emulated hpet
2241 */
2242 hpet->timer_block_id = cpu_to_le32(0x8086a201);
2243 hpet->addr.address = cpu_to_le64(HPET_BASE);
2244 build_header(linker, table_data,
2245 (void *)hpet, "HPET", sizeof(*hpet), 1, NULL, NULL);
2246 }
2247
2248 static void
2249 build_tpm_tcpa(GArray *table_data, BIOSLinker *linker, GArray *tcpalog)
2250 {
2251 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa);
2252 unsigned log_addr_size = sizeof(tcpa->log_area_start_address);
2253 unsigned log_addr_offset =
2254 (char *)&tcpa->log_area_start_address - table_data->data;
2255
2256 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT);
2257 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE);
2258 acpi_data_push(tcpalog, le32_to_cpu(tcpa->log_area_minimum_length));
2259
2260 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, tcpalog, 1,
2261 false /* high memory */);
2262
2263 /* log area start address to be filled by Guest linker */
2264 bios_linker_loader_add_pointer(linker,
2265 ACPI_BUILD_TABLE_FILE, log_addr_offset, log_addr_size,
2266 ACPI_BUILD_TPMLOG_FILE, 0);
2267
2268 build_header(linker, table_data,
2269 (void *)tcpa, "TCPA", sizeof(*tcpa), 2, NULL, NULL);
2270 }
2271
2272 static void
2273 build_tpm2(GArray *table_data, BIOSLinker *linker)
2274 {
2275 Acpi20TPM2 *tpm2_ptr;
2276
2277 tpm2_ptr = acpi_data_push(table_data, sizeof *tpm2_ptr);
2278
2279 tpm2_ptr->platform_class = cpu_to_le16(TPM2_ACPI_CLASS_CLIENT);
2280 tpm2_ptr->control_area_address = cpu_to_le64(0);
2281 tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_MMIO);
2282
2283 build_header(linker, table_data,
2284 (void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4, NULL, NULL);
2285 }
2286
2287 static void
2288 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine)
2289 {
2290 AcpiSystemResourceAffinityTable *srat;
2291 AcpiSratMemoryAffinity *numamem;
2292
2293 int i;
2294 int srat_start, numa_start, slots;
2295 uint64_t mem_len, mem_base, next_base;
2296 MachineClass *mc = MACHINE_GET_CLASS(machine);
2297 const CPUArchIdList *apic_ids = mc->possible_cpu_arch_ids(machine);
2298 PCMachineState *pcms = PC_MACHINE(machine);
2299 ram_addr_t hotplugabble_address_space_size =
2300 object_property_get_int(OBJECT(pcms), PC_MACHINE_MEMHP_REGION_SIZE,
2301 NULL);
2302
2303 srat_start = table_data->len;
2304
2305 srat = acpi_data_push(table_data, sizeof *srat);
2306 srat->reserved1 = cpu_to_le32(1);
2307
2308 for (i = 0; i < apic_ids->len; i++) {
2309 int j = numa_get_node_for_cpu(i);
2310 uint32_t apic_id = apic_ids->cpus[i].arch_id;
2311
2312 if (apic_id < 255) {
2313 AcpiSratProcessorAffinity *core;
2314
2315 core = acpi_data_push(table_data, sizeof *core);
2316 core->type = ACPI_SRAT_PROCESSOR_APIC;
2317 core->length = sizeof(*core);
2318 core->local_apic_id = apic_id;
2319 if (j < nb_numa_nodes) {
2320 core->proximity_lo = j;
2321 }
2322 memset(core->proximity_hi, 0, 3);
2323 core->local_sapic_eid = 0;
2324 core->flags = cpu_to_le32(1);
2325 } else {
2326 AcpiSratProcessorX2ApicAffinity *core;
2327
2328 core = acpi_data_push(table_data, sizeof *core);
2329 core->type = ACPI_SRAT_PROCESSOR_x2APIC;
2330 core->length = sizeof(*core);
2331 core->x2apic_id = cpu_to_le32(apic_id);
2332 if (j < nb_numa_nodes) {
2333 core->proximity_domain = cpu_to_le32(j);
2334 }
2335 core->flags = cpu_to_le32(1);
2336 }
2337 }
2338
2339
2340 /* the memory map is a bit tricky, it contains at least one hole
2341 * from 640k-1M and possibly another one from 3.5G-4G.
2342 */
2343 next_base = 0;
2344 numa_start = table_data->len;
2345
2346 numamem = acpi_data_push(table_data, sizeof *numamem);
2347 build_srat_memory(numamem, 0, 640 * 1024, 0, MEM_AFFINITY_ENABLED);
2348 next_base = 1024 * 1024;
2349 for (i = 1; i < pcms->numa_nodes + 1; ++i) {
2350 mem_base = next_base;
2351 mem_len = pcms->node_mem[i - 1];
2352 if (i == 1) {
2353 mem_len -= 1024 * 1024;
2354 }
2355 next_base = mem_base + mem_len;
2356
2357 /* Cut out the ACPI_PCI hole */
2358 if (mem_base <= pcms->below_4g_mem_size &&
2359 next_base > pcms->below_4g_mem_size) {
2360 mem_len -= next_base - pcms->below_4g_mem_size;
2361 if (mem_len > 0) {
2362 numamem = acpi_data_push(table_data, sizeof *numamem);
2363 build_srat_memory(numamem, mem_base, mem_len, i - 1,
2364 MEM_AFFINITY_ENABLED);
2365 }
2366 mem_base = 1ULL << 32;
2367 mem_len = next_base - pcms->below_4g_mem_size;
2368 next_base += (1ULL << 32) - pcms->below_4g_mem_size;
2369 }
2370 numamem = acpi_data_push(table_data, sizeof *numamem);
2371 build_srat_memory(numamem, mem_base, mem_len, i - 1,
2372 MEM_AFFINITY_ENABLED);
2373 }
2374 slots = (table_data->len - numa_start) / sizeof *numamem;
2375 for (; slots < pcms->numa_nodes + 2; slots++) {
2376 numamem = acpi_data_push(table_data, sizeof *numamem);
2377 build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS);
2378 }
2379
2380 /*
2381 * Entry is required for Windows to enable memory hotplug in OS.
2382 * Memory devices may override proximity set by this entry,
2383 * providing _PXM method if necessary.
2384 */
2385 if (hotplugabble_address_space_size) {
2386 numamem = acpi_data_push(table_data, sizeof *numamem);
2387 build_srat_memory(numamem, pcms->hotplug_memory.base,
2388 hotplugabble_address_space_size, 0,
2389 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
2390 }
2391
2392 build_header(linker, table_data,
2393 (void *)(table_data->data + srat_start),
2394 "SRAT",
2395 table_data->len - srat_start, 1, NULL, NULL);
2396 }
2397
2398 static void
2399 build_mcfg_q35(GArray *table_data, BIOSLinker *linker, AcpiMcfgInfo *info)
2400 {
2401 AcpiTableMcfg *mcfg;
2402 const char *sig;
2403 int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]);
2404
2405 mcfg = acpi_data_push(table_data, len);
2406 mcfg->allocation[0].address = cpu_to_le64(info->mcfg_base);
2407 /* Only a single allocation so no need to play with segments */
2408 mcfg->allocation[0].pci_segment = cpu_to_le16(0);
2409 mcfg->allocation[0].start_bus_number = 0;
2410 mcfg->allocation[0].end_bus_number = PCIE_MMCFG_BUS(info->mcfg_size - 1);
2411
2412 /* MCFG is used for ECAM which can be enabled or disabled by guest.
2413 * To avoid table size changes (which create migration issues),
2414 * always create the table even if there are no allocations,
2415 * but set the signature to a reserved value in this case.
2416 * ACPI spec requires OSPMs to ignore such tables.
2417 */
2418 if (info->mcfg_base == PCIE_BASE_ADDR_UNMAPPED) {
2419 /* Reserved signature: ignored by OSPM */
2420 sig = "QEMU";
2421 } else {
2422 sig = "MCFG";
2423 }
2424 build_header(linker, table_data, (void *)mcfg, sig, len, 1, NULL, NULL);
2425 }
2426
2427 /*
2428 * VT-d spec 8.1 DMA Remapping Reporting Structure
2429 * (version Oct. 2014 or later)
2430 */
2431 static void
2432 build_dmar_q35(GArray *table_data, BIOSLinker *linker)
2433 {
2434 int dmar_start = table_data->len;
2435
2436 AcpiTableDmar *dmar;
2437 AcpiDmarHardwareUnit *drhd;
2438 AcpiDmarRootPortATS *atsr;
2439 uint8_t dmar_flags = 0;
2440 X86IOMMUState *iommu = x86_iommu_get_default();
2441 AcpiDmarDeviceScope *scope = NULL;
2442 /* Root complex IOAPIC use one path[0] only */
2443 size_t ioapic_scope_size = sizeof(*scope) + sizeof(scope->path[0]);
2444
2445 assert(iommu);
2446 if (iommu->intr_supported) {
2447 dmar_flags |= 0x1; /* Flags: 0x1: INT_REMAP */
2448 }
2449
2450 dmar = acpi_data_push(table_data, sizeof(*dmar));
2451 dmar->host_address_width = VTD_HOST_ADDRESS_WIDTH - 1;
2452 dmar->flags = dmar_flags;
2453
2454 /* DMAR Remapping Hardware Unit Definition structure */
2455 drhd = acpi_data_push(table_data, sizeof(*drhd) + ioapic_scope_size);
2456 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT);
2457 drhd->length = cpu_to_le16(sizeof(*drhd) + ioapic_scope_size);
2458 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL;
2459 drhd->pci_segment = cpu_to_le16(0);
2460 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR);
2461
2462 /* Scope definition for the root-complex IOAPIC. See VT-d spec
2463 * 8.3.1 (version Oct. 2014 or later). */
2464 scope = &drhd->scope[0];
2465 scope->entry_type = 0x03; /* Type: 0x03 for IOAPIC */
2466 scope->length = ioapic_scope_size;
2467 scope->enumeration_id = ACPI_BUILD_IOAPIC_ID;
2468 scope->bus = Q35_PSEUDO_BUS_PLATFORM;
2469 scope->path[0].device = PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC);
2470 scope->path[0].function = PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC);
2471
2472 if (iommu->dt_supported) {
2473 atsr = acpi_data_push(table_data, sizeof(*atsr));
2474 atsr->type = cpu_to_le16(ACPI_DMAR_TYPE_ATSR);
2475 atsr->length = cpu_to_le16(sizeof(*atsr));
2476 atsr->flags = ACPI_DMAR_ATSR_ALL_PORTS;
2477 atsr->pci_segment = cpu_to_le16(0);
2478 }
2479
2480 build_header(linker, table_data, (void *)(table_data->data + dmar_start),
2481 "DMAR", table_data->len - dmar_start, 1, NULL, NULL);
2482 }
2483 /*
2484 * IVRS table as specified in AMD IOMMU Specification v2.62, Section 5.2
2485 * accessible here http://support.amd.com/TechDocs/48882_IOMMU.pdf
2486 */
2487 static void
2488 build_amd_iommu(GArray *table_data, BIOSLinker *linker)
2489 {
2490 int iommu_start = table_data->len;
2491 AMDVIState *s = AMD_IOMMU_DEVICE(x86_iommu_get_default());
2492
2493 /* IVRS header */
2494 acpi_data_push(table_data, sizeof(AcpiTableHeader));
2495 /* IVinfo - IO virtualization information common to all
2496 * IOMMU units in a system
2497 */
2498 build_append_int_noprefix(table_data, 40UL << 8/* PASize */, 4);
2499 /* reserved */
2500 build_append_int_noprefix(table_data, 0, 8);
2501
2502 /* IVHD definition - type 10h */
2503 build_append_int_noprefix(table_data, 0x10, 1);
2504 /* virtualization flags */
2505 build_append_int_noprefix(table_data,
2506 (1UL << 0) | /* HtTunEn */
2507 (1UL << 4) | /* iotblSup */
2508 (1UL << 6) | /* PrefSup */
2509 (1UL << 7), /* PPRSup */
2510 1);
2511 /* IVHD length */
2512 build_append_int_noprefix(table_data, 0x24, 2);
2513 /* DeviceID */
2514 build_append_int_noprefix(table_data, s->devid, 2);
2515 /* Capability offset */
2516 build_append_int_noprefix(table_data, s->capab_offset, 2);
2517 /* IOMMU base address */
2518 build_append_int_noprefix(table_data, s->mmio.addr, 8);
2519 /* PCI Segment Group */
2520 build_append_int_noprefix(table_data, 0, 2);
2521 /* IOMMU info */
2522 build_append_int_noprefix(table_data, 0, 2);
2523 /* IOMMU Feature Reporting */
2524 build_append_int_noprefix(table_data,
2525 (48UL << 30) | /* HATS */
2526 (48UL << 28) | /* GATS */
2527 (1UL << 2), /* GTSup */
2528 4);
2529 /*
2530 * Type 1 device entry reporting all devices
2531 * These are 4-byte device entries currently reporting the range of
2532 * Refer to Spec - Table 95:IVHD Device Entry Type Codes(4-byte)
2533 */
2534 build_append_int_noprefix(table_data, 0x0000001, 4);
2535
2536 build_header(linker, table_data, (void *)(table_data->data + iommu_start),
2537 "IVRS", table_data->len - iommu_start, 1, NULL, NULL);
2538 }
2539
2540 static GArray *
2541 build_rsdp(GArray *rsdp_table, BIOSLinker *linker, unsigned rsdt_tbl_offset)
2542 {
2543 AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp);
2544 unsigned rsdt_pa_size = sizeof(rsdp->rsdt_physical_address);
2545 unsigned rsdt_pa_offset =
2546 (char *)&rsdp->rsdt_physical_address - rsdp_table->data;
2547
2548 bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, rsdp_table, 16,
2549 true /* fseg memory */);
2550
2551 memcpy(&rsdp->signature, "RSD PTR ", 8);
2552 memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, 6);
2553 /* Address to be filled by Guest linker */
2554 bios_linker_loader_add_pointer(linker,
2555 ACPI_BUILD_RSDP_FILE, rsdt_pa_offset, rsdt_pa_size,
2556 ACPI_BUILD_TABLE_FILE, rsdt_tbl_offset);
2557
2558 /* Checksum to be filled by Guest linker */
2559 bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE,
2560 (char *)rsdp - rsdp_table->data, sizeof *rsdp,
2561 (char *)&rsdp->checksum - rsdp_table->data);
2562
2563 return rsdp_table;
2564 }
2565
2566 typedef
2567 struct AcpiBuildState {
2568 /* Copy of table in RAM (for patching). */
2569 MemoryRegion *table_mr;
2570 /* Is table patched? */
2571 uint8_t patched;
2572 void *rsdp;
2573 MemoryRegion *rsdp_mr;
2574 MemoryRegion *linker_mr;
2575 } AcpiBuildState;
2576
2577 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg)
2578 {
2579 Object *pci_host;
2580 QObject *o;
2581
2582 pci_host = acpi_get_i386_pci_host();
2583 g_assert(pci_host);
2584
2585 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL);
2586 if (!o) {
2587 return false;
2588 }
2589 mcfg->mcfg_base = qint_get_int(qobject_to_qint(o));
2590 qobject_decref(o);
2591
2592 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
2593 assert(o);
2594 mcfg->mcfg_size = qint_get_int(qobject_to_qint(o));
2595 qobject_decref(o);
2596 return true;
2597 }
2598
2599 static
2600 void acpi_build(AcpiBuildTables *tables, MachineState *machine)
2601 {
2602 PCMachineState *pcms = PC_MACHINE(machine);
2603 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2604 GArray *table_offsets;
2605 unsigned facs, dsdt, rsdt, fadt;
2606 AcpiPmInfo pm;
2607 AcpiMiscInfo misc;
2608 AcpiMcfgInfo mcfg;
2609 Range pci_hole, pci_hole64;
2610 uint8_t *u;
2611 size_t aml_len = 0;
2612 GArray *tables_blob = tables->table_data;
2613 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL };
2614 Object *vmgenid_dev;
2615
2616 acpi_get_pm_info(&pm);
2617 acpi_get_misc_info(&misc);
2618 acpi_get_pci_holes(&pci_hole, &pci_hole64);
2619 acpi_get_slic_oem(&slic_oem);
2620
2621 table_offsets = g_array_new(false, true /* clear */,
2622 sizeof(uint32_t));
2623 ACPI_BUILD_DPRINTF("init ACPI tables\n");
2624
2625 bios_linker_loader_alloc(tables->linker,
2626 ACPI_BUILD_TABLE_FILE, tables_blob,
2627 64 /* Ensure FACS is aligned */,
2628 false /* high memory */);
2629
2630 /*
2631 * FACS is pointed to by FADT.
2632 * We place it first since it's the only table that has alignment
2633 * requirements.
2634 */
2635 facs = tables_blob->len;
2636 build_facs(tables_blob, tables->linker);
2637
2638 /* DSDT is pointed to by FADT */
2639 dsdt = tables_blob->len;
2640 build_dsdt(tables_blob, tables->linker, &pm, &misc,
2641 &pci_hole, &pci_hole64, machine);
2642
2643 /* Count the size of the DSDT and SSDT, we will need it for legacy
2644 * sizing of ACPI tables.
2645 */
2646 aml_len += tables_blob->len - dsdt;
2647
2648 /* ACPI tables pointed to by RSDT */
2649 fadt = tables_blob->len;
2650 acpi_add_table(table_offsets, tables_blob);
2651 build_fadt(tables_blob, tables->linker, &pm, facs, dsdt,
2652 slic_oem.id, slic_oem.table_id);
2653 aml_len += tables_blob->len - fadt;
2654
2655 acpi_add_table(table_offsets, tables_blob);
2656 build_madt(tables_blob, tables->linker, pcms);
2657
2658 vmgenid_dev = find_vmgenid_dev();
2659 if (vmgenid_dev) {
2660 acpi_add_table(table_offsets, tables_blob);
2661 vmgenid_build_acpi(VMGENID(vmgenid_dev), tables_blob,
2662 tables->vmgenid, tables->linker);
2663 }
2664
2665 if (misc.has_hpet) {
2666 acpi_add_table(table_offsets, tables_blob);
2667 build_hpet(tables_blob, tables->linker);
2668 }
2669 if (misc.tpm_version != TPM_VERSION_UNSPEC) {
2670 acpi_add_table(table_offsets, tables_blob);
2671 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog);
2672
2673 if (misc.tpm_version == TPM_VERSION_2_0) {
2674 acpi_add_table(table_offsets, tables_blob);
2675 build_tpm2(tables_blob, tables->linker);
2676 }
2677 }
2678 if (pcms->numa_nodes) {
2679 acpi_add_table(table_offsets, tables_blob);
2680 build_srat(tables_blob, tables->linker, machine);
2681 }
2682 if (acpi_get_mcfg(&mcfg)) {
2683 acpi_add_table(table_offsets, tables_blob);
2684 build_mcfg_q35(tables_blob, tables->linker, &mcfg);
2685 }
2686 if (x86_iommu_get_default()) {
2687 IommuType IOMMUType = x86_iommu_get_type();
2688 if (IOMMUType == TYPE_AMD) {
2689 acpi_add_table(table_offsets, tables_blob);
2690 build_amd_iommu(tables_blob, tables->linker);
2691 } else if (IOMMUType == TYPE_INTEL) {
2692 acpi_add_table(table_offsets, tables_blob);
2693 build_dmar_q35(tables_blob, tables->linker);
2694 }
2695 }
2696 if (pcms->acpi_nvdimm_state.is_enabled) {
2697 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker,
2698 &pcms->acpi_nvdimm_state, machine->ram_slots);
2699 }
2700
2701 /* Add tables supplied by user (if any) */
2702 for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
2703 unsigned len = acpi_table_len(u);
2704
2705 acpi_add_table(table_offsets, tables_blob);
2706 g_array_append_vals(tables_blob, u, len);
2707 }
2708
2709 /* RSDT is pointed to by RSDP */
2710 rsdt = tables_blob->len;
2711 build_rsdt(tables_blob, tables->linker, table_offsets,
2712 slic_oem.id, slic_oem.table_id);
2713
2714 /* RSDP is in FSEG memory, so allocate it separately */
2715 build_rsdp(tables->rsdp, tables->linker, rsdt);
2716
2717 /* We'll expose it all to Guest so we want to reduce
2718 * chance of size changes.
2719 *
2720 * We used to align the tables to 4k, but of course this would
2721 * too simple to be enough. 4k turned out to be too small an
2722 * alignment very soon, and in fact it is almost impossible to
2723 * keep the table size stable for all (max_cpus, max_memory_slots)
2724 * combinations. So the table size is always 64k for pc-i440fx-2.1
2725 * and we give an error if the table grows beyond that limit.
2726 *
2727 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
2728 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
2729 * than 2.0 and we can always pad the smaller tables with zeros. We can
2730 * then use the exact size of the 2.0 tables.
2731 *
2732 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
2733 */
2734 if (pcmc->legacy_acpi_table_size) {
2735 /* Subtracting aml_len gives the size of fixed tables. Then add the
2736 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
2737 */
2738 int legacy_aml_len =
2739 pcmc->legacy_acpi_table_size +
2740 ACPI_BUILD_LEGACY_CPU_AML_SIZE * pcms->apic_id_limit;
2741 int legacy_table_size =
2742 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len,
2743 ACPI_BUILD_ALIGN_SIZE);
2744 if (tables_blob->len > legacy_table_size) {
2745 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
2746 error_report("Warning: migration may not work.");
2747 }
2748 g_array_set_size(tables_blob, legacy_table_size);
2749 } else {
2750 /* Make sure we have a buffer in case we need to resize the tables. */
2751 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
2752 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
2753 error_report("Warning: ACPI tables are larger than 64k.");
2754 error_report("Warning: migration may not work.");
2755 error_report("Warning: please remove CPUs, NUMA nodes, "
2756 "memory slots or PCI bridges.");
2757 }
2758 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
2759 }
2760
2761 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE);
2762
2763 /* Cleanup memory that's no longer used. */
2764 g_array_free(table_offsets, true);
2765 }
2766
2767 static void acpi_ram_update(MemoryRegion *mr, GArray *data)
2768 {
2769 uint32_t size = acpi_data_len(data);
2770
2771 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
2772 memory_region_ram_resize(mr, size, &error_abort);
2773
2774 memcpy(memory_region_get_ram_ptr(mr), data->data, size);
2775 memory_region_set_dirty(mr, 0, size);
2776 }
2777
2778 static void acpi_build_update(void *build_opaque)
2779 {
2780 AcpiBuildState *build_state = build_opaque;
2781 AcpiBuildTables tables;
2782
2783 /* No state to update or already patched? Nothing to do. */
2784 if (!build_state || build_state->patched) {
2785 return;
2786 }
2787 build_state->patched = 1;
2788
2789 acpi_build_tables_init(&tables);
2790
2791 acpi_build(&tables, MACHINE(qdev_get_machine()));
2792
2793 acpi_ram_update(build_state->table_mr, tables.table_data);
2794
2795 if (build_state->rsdp) {
2796 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp));
2797 } else {
2798 acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
2799 }
2800
2801 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob);
2802 acpi_build_tables_cleanup(&tables, true);
2803 }
2804
2805 static void acpi_build_reset(void *build_opaque)
2806 {
2807 AcpiBuildState *build_state = build_opaque;
2808 build_state->patched = 0;
2809 }
2810
2811 static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state,
2812 GArray *blob, const char *name,
2813 uint64_t max_size)
2814 {
2815 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1,
2816 name, acpi_build_update, build_state, NULL, true);
2817 }
2818
2819 static const VMStateDescription vmstate_acpi_build = {
2820 .name = "acpi_build",
2821 .version_id = 1,
2822 .minimum_version_id = 1,
2823 .fields = (VMStateField[]) {
2824 VMSTATE_UINT8(patched, AcpiBuildState),
2825 VMSTATE_END_OF_LIST()
2826 },
2827 };
2828
2829 void acpi_setup(void)
2830 {
2831 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
2832 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2833 AcpiBuildTables tables;
2834 AcpiBuildState *build_state;
2835 Object *vmgenid_dev;
2836
2837 if (!pcms->fw_cfg) {
2838 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
2839 return;
2840 }
2841
2842 if (!pcms->acpi_build_enabled) {
2843 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
2844 return;
2845 }
2846
2847 if (!acpi_enabled) {
2848 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
2849 return;
2850 }
2851
2852 build_state = g_malloc0(sizeof *build_state);
2853
2854 acpi_set_pci_info();
2855
2856 acpi_build_tables_init(&tables);
2857 acpi_build(&tables, MACHINE(pcms));
2858
2859 /* Now expose it all to Guest */
2860 build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data,
2861 ACPI_BUILD_TABLE_FILE,
2862 ACPI_BUILD_TABLE_MAX_SIZE);
2863 assert(build_state->table_mr != NULL);
2864
2865 build_state->linker_mr =
2866 acpi_add_rom_blob(build_state, tables.linker->cmd_blob,
2867 "etc/table-loader", 0);
2868
2869 fw_cfg_add_file(pcms->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
2870 tables.tcpalog->data, acpi_data_len(tables.tcpalog));
2871
2872 vmgenid_dev = find_vmgenid_dev();
2873 if (vmgenid_dev) {
2874 vmgenid_add_fw_cfg(VMGENID(vmgenid_dev), pcms->fw_cfg,
2875 tables.vmgenid);
2876 }
2877
2878 if (!pcmc->rsdp_in_ram) {
2879 /*
2880 * Keep for compatibility with old machine types.
2881 * Though RSDP is small, its contents isn't immutable, so
2882 * we'll update it along with the rest of tables on guest access.
2883 */
2884 uint32_t rsdp_size = acpi_data_len(tables.rsdp);
2885
2886 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size);
2887 fw_cfg_add_file_callback(pcms->fw_cfg, ACPI_BUILD_RSDP_FILE,
2888 acpi_build_update, build_state,
2889 build_state->rsdp, rsdp_size, true);
2890 build_state->rsdp_mr = NULL;
2891 } else {
2892 build_state->rsdp = NULL;
2893 build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp,
2894 ACPI_BUILD_RSDP_FILE, 0);
2895 }
2896
2897 qemu_register_reset(acpi_build_reset, build_state);
2898 acpi_build_reset(build_state);
2899 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state);
2900
2901 /* Cleanup tables but don't free the memory: we track it
2902 * in build_state.
2903 */
2904 acpi_build_tables_cleanup(&tables, false);
2905 }
QEmu