4 * Copyright (c) 2013 Alexander Graf <agraf@suse.de>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #include "qemu/osdep.h"
22 #include "exec/exec-all.h"
23 #include "tcg/tcg-op.h"
24 #include "tcg/tcg-op-gvec.h"
27 #include "translate.h"
28 #include "internals.h"
29 #include "qemu/host-utils.h"
31 #include "hw/semihosting/semihost.h"
32 #include "exec/gen-icount.h"
34 #include "exec/helper-proto.h"
35 #include "exec/helper-gen.h"
38 #include "trace-tcg.h"
39 #include "translate-a64.h"
40 #include "qemu/atomic128.h"
42 static TCGv_i64 cpu_X
[32];
43 static TCGv_i64 cpu_pc
;
45 /* Load/store exclusive handling */
46 static TCGv_i64 cpu_exclusive_high
;
48 static const char *regnames
[] = {
49 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
50 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
51 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
52 "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp"
56 A64_SHIFT_TYPE_LSL
= 0,
57 A64_SHIFT_TYPE_LSR
= 1,
58 A64_SHIFT_TYPE_ASR
= 2,
59 A64_SHIFT_TYPE_ROR
= 3
62 /* Table based decoder typedefs - used when the relevant bits for decode
63 * are too awkwardly scattered across the instruction (eg SIMD).
65 typedef void AArch64DecodeFn(DisasContext
*s
, uint32_t insn
);
67 typedef struct AArch64DecodeTable
{
70 AArch64DecodeFn
*disas_fn
;
73 /* initialize TCG globals. */
74 void a64_translate_init(void)
78 cpu_pc
= tcg_global_mem_new_i64(cpu_env
,
79 offsetof(CPUARMState
, pc
),
81 for (i
= 0; i
< 32; i
++) {
82 cpu_X
[i
] = tcg_global_mem_new_i64(cpu_env
,
83 offsetof(CPUARMState
, xregs
[i
]),
87 cpu_exclusive_high
= tcg_global_mem_new_i64(cpu_env
,
88 offsetof(CPUARMState
, exclusive_high
), "exclusive_high");
92 * Return the core mmu_idx to use for A64 "unprivileged load/store" insns
94 static int get_a64_user_mem_index(DisasContext
*s
)
97 * If AccType_UNPRIV is not used, the insn uses AccType_NORMAL,
98 * which is the usual mmu_idx for this cpu state.
100 ARMMMUIdx useridx
= s
->mmu_idx
;
104 * We have pre-computed the condition for AccType_UNPRIV.
105 * Therefore we should never get here with a mmu_idx for
106 * which we do not know the corresponding user mmu_idx.
109 case ARMMMUIdx_E10_1
:
110 case ARMMMUIdx_E10_1_PAN
:
111 useridx
= ARMMMUIdx_E10_0
;
113 case ARMMMUIdx_E20_2
:
114 case ARMMMUIdx_E20_2_PAN
:
115 useridx
= ARMMMUIdx_E20_0
;
117 case ARMMMUIdx_SE10_1
:
118 case ARMMMUIdx_SE10_1_PAN
:
119 useridx
= ARMMMUIdx_SE10_0
;
122 g_assert_not_reached();
125 return arm_to_core_mmu_idx(useridx
);
128 static void reset_btype(DisasContext
*s
)
131 TCGv_i32 zero
= tcg_const_i32(0);
132 tcg_gen_st_i32(zero
, cpu_env
, offsetof(CPUARMState
, btype
));
133 tcg_temp_free_i32(zero
);
138 static void set_btype(DisasContext
*s
, int val
)
142 /* BTYPE is a 2-bit field, and 0 should be done with reset_btype. */
143 tcg_debug_assert(val
>= 1 && val
<= 3);
145 tcg_val
= tcg_const_i32(val
);
146 tcg_gen_st_i32(tcg_val
, cpu_env
, offsetof(CPUARMState
, btype
));
147 tcg_temp_free_i32(tcg_val
);
151 void gen_a64_set_pc_im(uint64_t val
)
153 tcg_gen_movi_i64(cpu_pc
, val
);
157 * Handle Top Byte Ignore (TBI) bits.
159 * If address tagging is enabled via the TCR TBI bits:
160 * + for EL2 and EL3 there is only one TBI bit, and if it is set
161 * then the address is zero-extended, clearing bits [63:56]
162 * + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0
163 * and TBI1 controls addressses with bit 55 == 1.
164 * If the appropriate TBI bit is set for the address then
165 * the address is sign-extended from bit 55 into bits [63:56]
167 * Here We have concatenated TBI{1,0} into tbi.
169 static void gen_top_byte_ignore(DisasContext
*s
, TCGv_i64 dst
,
170 TCGv_i64 src
, int tbi
)
173 /* Load unmodified address */
174 tcg_gen_mov_i64(dst
, src
);
175 } else if (!regime_has_2_ranges(s
->mmu_idx
)) {
176 /* Force tag byte to all zero */
177 tcg_gen_extract_i64(dst
, src
, 0, 56);
179 /* Sign-extend from bit 55. */
180 tcg_gen_sextract_i64(dst
, src
, 0, 56);
183 TCGv_i64 tcg_zero
= tcg_const_i64(0);
186 * The two TBI bits differ.
187 * If tbi0, then !tbi1: only use the extension if positive.
188 * if !tbi0, then tbi1: only use the extension if negative.
190 tcg_gen_movcond_i64(tbi
== 1 ? TCG_COND_GE
: TCG_COND_LT
,
191 dst
, dst
, tcg_zero
, dst
, src
);
192 tcg_temp_free_i64(tcg_zero
);
197 static void gen_a64_set_pc(DisasContext
*s
, TCGv_i64 src
)
200 * If address tagging is enabled for instructions via the TCR TBI bits,
201 * then loading an address into the PC will clear out any tag.
203 gen_top_byte_ignore(s
, cpu_pc
, src
, s
->tbii
);
207 * Return a "clean" address for ADDR according to TBID.
208 * This is always a fresh temporary, as we need to be able to
209 * increment this independently of a dirty write-back address.
211 static TCGv_i64
clean_data_tbi(DisasContext
*s
, TCGv_i64 addr
)
213 TCGv_i64 clean
= new_tmp_a64(s
);
215 * In order to get the correct value in the FAR_ELx register,
216 * we must present the memory subsystem with the "dirty" address
217 * including the TBI. In system mode we can make this work via
218 * the TLB, dropping the TBI during translation. But for user-only
219 * mode we don't have that option, and must remove the top byte now.
221 #ifdef CONFIG_USER_ONLY
222 gen_top_byte_ignore(s
, clean
, addr
, s
->tbid
);
224 tcg_gen_mov_i64(clean
, addr
);
229 /* Insert a zero tag into src, with the result at dst. */
230 static void gen_address_with_allocation_tag0(TCGv_i64 dst
, TCGv_i64 src
)
232 tcg_gen_andi_i64(dst
, src
, ~MAKE_64BIT_MASK(56, 4));
235 typedef struct DisasCompare64
{
240 static void a64_test_cc(DisasCompare64
*c64
, int cc
)
244 arm_test_cc(&c32
, cc
);
246 /* Sign-extend the 32-bit value so that the GE/LT comparisons work
247 * properly. The NE/EQ comparisons are also fine with this choice. */
248 c64
->cond
= c32
.cond
;
249 c64
->value
= tcg_temp_new_i64();
250 tcg_gen_ext_i32_i64(c64
->value
, c32
.value
);
255 static void a64_free_cc(DisasCompare64
*c64
)
257 tcg_temp_free_i64(c64
->value
);
260 static void gen_exception_internal(int excp
)
262 TCGv_i32 tcg_excp
= tcg_const_i32(excp
);
264 assert(excp_is_internal(excp
));
265 gen_helper_exception_internal(cpu_env
, tcg_excp
);
266 tcg_temp_free_i32(tcg_excp
);
269 static void gen_exception_internal_insn(DisasContext
*s
, uint64_t pc
, int excp
)
271 gen_a64_set_pc_im(pc
);
272 gen_exception_internal(excp
);
273 s
->base
.is_jmp
= DISAS_NORETURN
;
276 static void gen_exception_insn(DisasContext
*s
, uint64_t pc
, int excp
,
277 uint32_t syndrome
, uint32_t target_el
)
279 gen_a64_set_pc_im(pc
);
280 gen_exception(excp
, syndrome
, target_el
);
281 s
->base
.is_jmp
= DISAS_NORETURN
;
284 static void gen_exception_bkpt_insn(DisasContext
*s
, uint32_t syndrome
)
288 gen_a64_set_pc_im(s
->pc_curr
);
289 tcg_syn
= tcg_const_i32(syndrome
);
290 gen_helper_exception_bkpt_insn(cpu_env
, tcg_syn
);
291 tcg_temp_free_i32(tcg_syn
);
292 s
->base
.is_jmp
= DISAS_NORETURN
;
295 static void gen_step_complete_exception(DisasContext
*s
)
297 /* We just completed step of an insn. Move from Active-not-pending
298 * to Active-pending, and then also take the swstep exception.
299 * This corresponds to making the (IMPDEF) choice to prioritize
300 * swstep exceptions over asynchronous exceptions taken to an exception
301 * level where debug is disabled. This choice has the advantage that
302 * we do not need to maintain internal state corresponding to the
303 * ISV/EX syndrome bits between completion of the step and generation
304 * of the exception, and our syndrome information is always correct.
307 gen_swstep_exception(s
, 1, s
->is_ldex
);
308 s
->base
.is_jmp
= DISAS_NORETURN
;
311 static inline bool use_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
313 /* No direct tb linking with singlestep (either QEMU's or the ARM
314 * debug architecture kind) or deterministic io
316 if (s
->base
.singlestep_enabled
|| s
->ss_active
||
317 (tb_cflags(s
->base
.tb
) & CF_LAST_IO
)) {
321 #ifndef CONFIG_USER_ONLY
322 /* Only link tbs from inside the same guest page */
323 if ((s
->base
.tb
->pc
& TARGET_PAGE_MASK
) != (dest
& TARGET_PAGE_MASK
)) {
331 static inline void gen_goto_tb(DisasContext
*s
, int n
, uint64_t dest
)
333 TranslationBlock
*tb
;
336 if (use_goto_tb(s
, n
, dest
)) {
338 gen_a64_set_pc_im(dest
);
339 tcg_gen_exit_tb(tb
, n
);
340 s
->base
.is_jmp
= DISAS_NORETURN
;
342 gen_a64_set_pc_im(dest
);
344 gen_step_complete_exception(s
);
345 } else if (s
->base
.singlestep_enabled
) {
346 gen_exception_internal(EXCP_DEBUG
);
348 tcg_gen_lookup_and_goto_ptr();
349 s
->base
.is_jmp
= DISAS_NORETURN
;
354 void unallocated_encoding(DisasContext
*s
)
356 /* Unallocated and reserved encodings are uncategorized */
357 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
, syn_uncategorized(),
358 default_exception_el(s
));
361 static void init_tmp_a64_array(DisasContext
*s
)
363 #ifdef CONFIG_DEBUG_TCG
364 memset(s
->tmp_a64
, 0, sizeof(s
->tmp_a64
));
366 s
->tmp_a64_count
= 0;
369 static void free_tmp_a64(DisasContext
*s
)
372 for (i
= 0; i
< s
->tmp_a64_count
; i
++) {
373 tcg_temp_free_i64(s
->tmp_a64
[i
]);
375 init_tmp_a64_array(s
);
378 TCGv_i64
new_tmp_a64(DisasContext
*s
)
380 assert(s
->tmp_a64_count
< TMP_A64_MAX
);
381 return s
->tmp_a64
[s
->tmp_a64_count
++] = tcg_temp_new_i64();
384 TCGv_i64
new_tmp_a64_zero(DisasContext
*s
)
386 TCGv_i64 t
= new_tmp_a64(s
);
387 tcg_gen_movi_i64(t
, 0);
392 * Register access functions
394 * These functions are used for directly accessing a register in where
395 * changes to the final register value are likely to be made. If you
396 * need to use a register for temporary calculation (e.g. index type
397 * operations) use the read_* form.
399 * B1.2.1 Register mappings
401 * In instruction register encoding 31 can refer to ZR (zero register) or
402 * the SP (stack pointer) depending on context. In QEMU's case we map SP
403 * to cpu_X[31] and ZR accesses to a temporary which can be discarded.
404 * This is the point of the _sp forms.
406 TCGv_i64
cpu_reg(DisasContext
*s
, int reg
)
409 return new_tmp_a64_zero(s
);
415 /* register access for when 31 == SP */
416 TCGv_i64
cpu_reg_sp(DisasContext
*s
, int reg
)
421 /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64
422 * representing the register contents. This TCGv is an auto-freed
423 * temporary so it need not be explicitly freed, and may be modified.
425 TCGv_i64
read_cpu_reg(DisasContext
*s
, int reg
, int sf
)
427 TCGv_i64 v
= new_tmp_a64(s
);
430 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
432 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
435 tcg_gen_movi_i64(v
, 0);
440 TCGv_i64
read_cpu_reg_sp(DisasContext
*s
, int reg
, int sf
)
442 TCGv_i64 v
= new_tmp_a64(s
);
444 tcg_gen_mov_i64(v
, cpu_X
[reg
]);
446 tcg_gen_ext32u_i64(v
, cpu_X
[reg
]);
451 /* Return the offset into CPUARMState of a slice (from
452 * the least significant end) of FP register Qn (ie
454 * (Note that this is not the same mapping as for A32; see cpu.h)
456 static inline int fp_reg_offset(DisasContext
*s
, int regno
, MemOp size
)
458 return vec_reg_offset(s
, regno
, 0, size
);
461 /* Offset of the high half of the 128 bit vector Qn */
462 static inline int fp_reg_hi_offset(DisasContext
*s
, int regno
)
464 return vec_reg_offset(s
, regno
, 1, MO_64
);
467 /* Convenience accessors for reading and writing single and double
468 * FP registers. Writing clears the upper parts of the associated
469 * 128 bit vector register, as required by the architecture.
470 * Note that unlike the GP register accessors, the values returned
471 * by the read functions must be manually freed.
473 static TCGv_i64
read_fp_dreg(DisasContext
*s
, int reg
)
475 TCGv_i64 v
= tcg_temp_new_i64();
477 tcg_gen_ld_i64(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_64
));
481 static TCGv_i32
read_fp_sreg(DisasContext
*s
, int reg
)
483 TCGv_i32 v
= tcg_temp_new_i32();
485 tcg_gen_ld_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_32
));
489 static TCGv_i32
read_fp_hreg(DisasContext
*s
, int reg
)
491 TCGv_i32 v
= tcg_temp_new_i32();
493 tcg_gen_ld16u_i32(v
, cpu_env
, fp_reg_offset(s
, reg
, MO_16
));
497 /* Clear the bits above an N-bit vector, for N = (is_q ? 128 : 64).
498 * If SVE is not enabled, then there are only 128 bits in the vector.
500 static void clear_vec_high(DisasContext
*s
, bool is_q
, int rd
)
502 unsigned ofs
= fp_reg_offset(s
, rd
, MO_64
);
503 unsigned vsz
= vec_full_reg_size(s
);
505 /* Nop move, with side effect of clearing the tail. */
506 tcg_gen_gvec_mov(MO_64
, ofs
, ofs
, is_q
? 16 : 8, vsz
);
509 void write_fp_dreg(DisasContext
*s
, int reg
, TCGv_i64 v
)
511 unsigned ofs
= fp_reg_offset(s
, reg
, MO_64
);
513 tcg_gen_st_i64(v
, cpu_env
, ofs
);
514 clear_vec_high(s
, false, reg
);
517 static void write_fp_sreg(DisasContext
*s
, int reg
, TCGv_i32 v
)
519 TCGv_i64 tmp
= tcg_temp_new_i64();
521 tcg_gen_extu_i32_i64(tmp
, v
);
522 write_fp_dreg(s
, reg
, tmp
);
523 tcg_temp_free_i64(tmp
);
526 TCGv_ptr
get_fpstatus_ptr(bool is_f16
)
528 TCGv_ptr statusptr
= tcg_temp_new_ptr();
531 /* In A64 all instructions (both FP and Neon) use the FPCR; there
532 * is no equivalent of the A32 Neon "standard FPSCR value".
533 * However half-precision operations operate under a different
534 * FZ16 flag and use vfp.fp_status_f16 instead of vfp.fp_status.
537 offset
= offsetof(CPUARMState
, vfp
.fp_status_f16
);
539 offset
= offsetof(CPUARMState
, vfp
.fp_status
);
541 tcg_gen_addi_ptr(statusptr
, cpu_env
, offset
);
545 /* Expand a 2-operand AdvSIMD vector operation using an expander function. */
546 static void gen_gvec_fn2(DisasContext
*s
, bool is_q
, int rd
, int rn
,
547 GVecGen2Fn
*gvec_fn
, int vece
)
549 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
550 is_q
? 16 : 8, vec_full_reg_size(s
));
553 /* Expand a 2-operand + immediate AdvSIMD vector operation using
554 * an expander function.
556 static void gen_gvec_fn2i(DisasContext
*s
, bool is_q
, int rd
, int rn
,
557 int64_t imm
, GVecGen2iFn
*gvec_fn
, int vece
)
559 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
560 imm
, is_q
? 16 : 8, vec_full_reg_size(s
));
563 /* Expand a 3-operand AdvSIMD vector operation using an expander function. */
564 static void gen_gvec_fn3(DisasContext
*s
, bool is_q
, int rd
, int rn
, int rm
,
565 GVecGen3Fn
*gvec_fn
, int vece
)
567 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
568 vec_full_reg_offset(s
, rm
), is_q
? 16 : 8, vec_full_reg_size(s
));
571 /* Expand a 4-operand AdvSIMD vector operation using an expander function. */
572 static void gen_gvec_fn4(DisasContext
*s
, bool is_q
, int rd
, int rn
, int rm
,
573 int rx
, GVecGen4Fn
*gvec_fn
, int vece
)
575 gvec_fn(vece
, vec_full_reg_offset(s
, rd
), vec_full_reg_offset(s
, rn
),
576 vec_full_reg_offset(s
, rm
), vec_full_reg_offset(s
, rx
),
577 is_q
? 16 : 8, vec_full_reg_size(s
));
580 /* Expand a 2-operand operation using an out-of-line helper. */
581 static void gen_gvec_op2_ool(DisasContext
*s
, bool is_q
, int rd
,
582 int rn
, int data
, gen_helper_gvec_2
*fn
)
584 tcg_gen_gvec_2_ool(vec_full_reg_offset(s
, rd
),
585 vec_full_reg_offset(s
, rn
),
586 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
589 /* Expand a 3-operand operation using an out-of-line helper. */
590 static void gen_gvec_op3_ool(DisasContext
*s
, bool is_q
, int rd
,
591 int rn
, int rm
, int data
, gen_helper_gvec_3
*fn
)
593 tcg_gen_gvec_3_ool(vec_full_reg_offset(s
, rd
),
594 vec_full_reg_offset(s
, rn
),
595 vec_full_reg_offset(s
, rm
),
596 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
599 /* Expand a 3-operand + fpstatus pointer + simd data value operation using
600 * an out-of-line helper.
602 static void gen_gvec_op3_fpst(DisasContext
*s
, bool is_q
, int rd
, int rn
,
603 int rm
, bool is_fp16
, int data
,
604 gen_helper_gvec_3_ptr
*fn
)
606 TCGv_ptr fpst
= get_fpstatus_ptr(is_fp16
);
607 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
608 vec_full_reg_offset(s
, rn
),
609 vec_full_reg_offset(s
, rm
), fpst
,
610 is_q
? 16 : 8, vec_full_reg_size(s
), data
, fn
);
611 tcg_temp_free_ptr(fpst
);
614 /* Set ZF and NF based on a 64 bit result. This is alas fiddlier
615 * than the 32 bit equivalent.
617 static inline void gen_set_NZ64(TCGv_i64 result
)
619 tcg_gen_extr_i64_i32(cpu_ZF
, cpu_NF
, result
);
620 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, cpu_NF
);
623 /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
624 static inline void gen_logic_CC(int sf
, TCGv_i64 result
)
627 gen_set_NZ64(result
);
629 tcg_gen_extrl_i64_i32(cpu_ZF
, result
);
630 tcg_gen_mov_i32(cpu_NF
, cpu_ZF
);
632 tcg_gen_movi_i32(cpu_CF
, 0);
633 tcg_gen_movi_i32(cpu_VF
, 0);
636 /* dest = T0 + T1; compute C, N, V and Z flags */
637 static void gen_add_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
640 TCGv_i64 result
, flag
, tmp
;
641 result
= tcg_temp_new_i64();
642 flag
= tcg_temp_new_i64();
643 tmp
= tcg_temp_new_i64();
645 tcg_gen_movi_i64(tmp
, 0);
646 tcg_gen_add2_i64(result
, flag
, t0
, tmp
, t1
, tmp
);
648 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
650 gen_set_NZ64(result
);
652 tcg_gen_xor_i64(flag
, result
, t0
);
653 tcg_gen_xor_i64(tmp
, t0
, t1
);
654 tcg_gen_andc_i64(flag
, flag
, tmp
);
655 tcg_temp_free_i64(tmp
);
656 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
658 tcg_gen_mov_i64(dest
, result
);
659 tcg_temp_free_i64(result
);
660 tcg_temp_free_i64(flag
);
662 /* 32 bit arithmetic */
663 TCGv_i32 t0_32
= tcg_temp_new_i32();
664 TCGv_i32 t1_32
= tcg_temp_new_i32();
665 TCGv_i32 tmp
= tcg_temp_new_i32();
667 tcg_gen_movi_i32(tmp
, 0);
668 tcg_gen_extrl_i64_i32(t0_32
, t0
);
669 tcg_gen_extrl_i64_i32(t1_32
, t1
);
670 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, t1_32
, tmp
);
671 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
672 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
673 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
674 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
675 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
677 tcg_temp_free_i32(tmp
);
678 tcg_temp_free_i32(t0_32
);
679 tcg_temp_free_i32(t1_32
);
683 /* dest = T0 - T1; compute C, N, V and Z flags */
684 static void gen_sub_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
687 /* 64 bit arithmetic */
688 TCGv_i64 result
, flag
, tmp
;
690 result
= tcg_temp_new_i64();
691 flag
= tcg_temp_new_i64();
692 tcg_gen_sub_i64(result
, t0
, t1
);
694 gen_set_NZ64(result
);
696 tcg_gen_setcond_i64(TCG_COND_GEU
, flag
, t0
, t1
);
697 tcg_gen_extrl_i64_i32(cpu_CF
, flag
);
699 tcg_gen_xor_i64(flag
, result
, t0
);
700 tmp
= tcg_temp_new_i64();
701 tcg_gen_xor_i64(tmp
, t0
, t1
);
702 tcg_gen_and_i64(flag
, flag
, tmp
);
703 tcg_temp_free_i64(tmp
);
704 tcg_gen_extrh_i64_i32(cpu_VF
, flag
);
705 tcg_gen_mov_i64(dest
, result
);
706 tcg_temp_free_i64(flag
);
707 tcg_temp_free_i64(result
);
709 /* 32 bit arithmetic */
710 TCGv_i32 t0_32
= tcg_temp_new_i32();
711 TCGv_i32 t1_32
= tcg_temp_new_i32();
714 tcg_gen_extrl_i64_i32(t0_32
, t0
);
715 tcg_gen_extrl_i64_i32(t1_32
, t1
);
716 tcg_gen_sub_i32(cpu_NF
, t0_32
, t1_32
);
717 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
718 tcg_gen_setcond_i32(TCG_COND_GEU
, cpu_CF
, t0_32
, t1_32
);
719 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
720 tmp
= tcg_temp_new_i32();
721 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
722 tcg_temp_free_i32(t0_32
);
723 tcg_temp_free_i32(t1_32
);
724 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tmp
);
725 tcg_temp_free_i32(tmp
);
726 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
730 /* dest = T0 + T1 + CF; do not compute flags. */
731 static void gen_adc(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
733 TCGv_i64 flag
= tcg_temp_new_i64();
734 tcg_gen_extu_i32_i64(flag
, cpu_CF
);
735 tcg_gen_add_i64(dest
, t0
, t1
);
736 tcg_gen_add_i64(dest
, dest
, flag
);
737 tcg_temp_free_i64(flag
);
740 tcg_gen_ext32u_i64(dest
, dest
);
744 /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */
745 static void gen_adc_CC(int sf
, TCGv_i64 dest
, TCGv_i64 t0
, TCGv_i64 t1
)
748 TCGv_i64 result
, cf_64
, vf_64
, tmp
;
749 result
= tcg_temp_new_i64();
750 cf_64
= tcg_temp_new_i64();
751 vf_64
= tcg_temp_new_i64();
752 tmp
= tcg_const_i64(0);
754 tcg_gen_extu_i32_i64(cf_64
, cpu_CF
);
755 tcg_gen_add2_i64(result
, cf_64
, t0
, tmp
, cf_64
, tmp
);
756 tcg_gen_add2_i64(result
, cf_64
, result
, cf_64
, t1
, tmp
);
757 tcg_gen_extrl_i64_i32(cpu_CF
, cf_64
);
758 gen_set_NZ64(result
);
760 tcg_gen_xor_i64(vf_64
, result
, t0
);
761 tcg_gen_xor_i64(tmp
, t0
, t1
);
762 tcg_gen_andc_i64(vf_64
, vf_64
, tmp
);
763 tcg_gen_extrh_i64_i32(cpu_VF
, vf_64
);
765 tcg_gen_mov_i64(dest
, result
);
767 tcg_temp_free_i64(tmp
);
768 tcg_temp_free_i64(vf_64
);
769 tcg_temp_free_i64(cf_64
);
770 tcg_temp_free_i64(result
);
772 TCGv_i32 t0_32
, t1_32
, tmp
;
773 t0_32
= tcg_temp_new_i32();
774 t1_32
= tcg_temp_new_i32();
775 tmp
= tcg_const_i32(0);
777 tcg_gen_extrl_i64_i32(t0_32
, t0
);
778 tcg_gen_extrl_i64_i32(t1_32
, t1
);
779 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, t0_32
, tmp
, cpu_CF
, tmp
);
780 tcg_gen_add2_i32(cpu_NF
, cpu_CF
, cpu_NF
, cpu_CF
, t1_32
, tmp
);
782 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
783 tcg_gen_xor_i32(cpu_VF
, cpu_NF
, t0_32
);
784 tcg_gen_xor_i32(tmp
, t0_32
, t1_32
);
785 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tmp
);
786 tcg_gen_extu_i32_i64(dest
, cpu_NF
);
788 tcg_temp_free_i32(tmp
);
789 tcg_temp_free_i32(t1_32
);
790 tcg_temp_free_i32(t0_32
);
795 * Load/Store generators
799 * Store from GPR register to memory.
801 static void do_gpr_st_memidx(DisasContext
*s
, TCGv_i64 source
,
802 TCGv_i64 tcg_addr
, int size
, int memidx
,
804 unsigned int iss_srt
,
805 bool iss_sf
, bool iss_ar
)
808 tcg_gen_qemu_st_i64(source
, tcg_addr
, memidx
, s
->be_data
+ size
);
813 syn
= syn_data_abort_with_iss(0,
819 0, 0, 0, 0, 0, false);
820 disas_set_insn_syndrome(s
, syn
);
824 static void do_gpr_st(DisasContext
*s
, TCGv_i64 source
,
825 TCGv_i64 tcg_addr
, int size
,
827 unsigned int iss_srt
,
828 bool iss_sf
, bool iss_ar
)
830 do_gpr_st_memidx(s
, source
, tcg_addr
, size
, get_mem_index(s
),
831 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
835 * Load from memory to GPR register
837 static void do_gpr_ld_memidx(DisasContext
*s
,
838 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
839 int size
, bool is_signed
,
840 bool extend
, int memidx
,
841 bool iss_valid
, unsigned int iss_srt
,
842 bool iss_sf
, bool iss_ar
)
844 MemOp memop
= s
->be_data
+ size
;
852 tcg_gen_qemu_ld_i64(dest
, tcg_addr
, memidx
, memop
);
854 if (extend
&& is_signed
) {
856 tcg_gen_ext32u_i64(dest
, dest
);
862 syn
= syn_data_abort_with_iss(0,
868 0, 0, 0, 0, 0, false);
869 disas_set_insn_syndrome(s
, syn
);
873 static void do_gpr_ld(DisasContext
*s
,
874 TCGv_i64 dest
, TCGv_i64 tcg_addr
,
875 int size
, bool is_signed
, bool extend
,
876 bool iss_valid
, unsigned int iss_srt
,
877 bool iss_sf
, bool iss_ar
)
879 do_gpr_ld_memidx(s
, dest
, tcg_addr
, size
, is_signed
, extend
,
881 iss_valid
, iss_srt
, iss_sf
, iss_ar
);
885 * Store from FP register to memory
887 static void do_fp_st(DisasContext
*s
, int srcidx
, TCGv_i64 tcg_addr
, int size
)
889 /* This writes the bottom N bits of a 128 bit wide vector to memory */
890 TCGv_i64 tmp
= tcg_temp_new_i64();
891 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_offset(s
, srcidx
, MO_64
));
893 tcg_gen_qemu_st_i64(tmp
, tcg_addr
, get_mem_index(s
),
896 bool be
= s
->be_data
== MO_BE
;
897 TCGv_i64 tcg_hiaddr
= tcg_temp_new_i64();
899 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
900 tcg_gen_qemu_st_i64(tmp
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
902 tcg_gen_ld_i64(tmp
, cpu_env
, fp_reg_hi_offset(s
, srcidx
));
903 tcg_gen_qemu_st_i64(tmp
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
905 tcg_temp_free_i64(tcg_hiaddr
);
908 tcg_temp_free_i64(tmp
);
912 * Load from memory to FP register
914 static void do_fp_ld(DisasContext
*s
, int destidx
, TCGv_i64 tcg_addr
, int size
)
916 /* This always zero-extends and writes to a full 128 bit wide vector */
917 TCGv_i64 tmplo
= tcg_temp_new_i64();
918 TCGv_i64 tmphi
= NULL
;
921 MemOp memop
= s
->be_data
+ size
;
922 tcg_gen_qemu_ld_i64(tmplo
, tcg_addr
, get_mem_index(s
), memop
);
924 bool be
= s
->be_data
== MO_BE
;
927 tmphi
= tcg_temp_new_i64();
928 tcg_hiaddr
= tcg_temp_new_i64();
930 tcg_gen_addi_i64(tcg_hiaddr
, tcg_addr
, 8);
931 tcg_gen_qemu_ld_i64(tmplo
, be
? tcg_hiaddr
: tcg_addr
, get_mem_index(s
),
933 tcg_gen_qemu_ld_i64(tmphi
, be
? tcg_addr
: tcg_hiaddr
, get_mem_index(s
),
935 tcg_temp_free_i64(tcg_hiaddr
);
938 tcg_gen_st_i64(tmplo
, cpu_env
, fp_reg_offset(s
, destidx
, MO_64
));
939 tcg_temp_free_i64(tmplo
);
942 tcg_gen_st_i64(tmphi
, cpu_env
, fp_reg_hi_offset(s
, destidx
));
943 tcg_temp_free_i64(tmphi
);
945 clear_vec_high(s
, tmphi
!= NULL
, destidx
);
949 * Vector load/store helpers.
951 * The principal difference between this and a FP load is that we don't
952 * zero extend as we are filling a partial chunk of the vector register.
953 * These functions don't support 128 bit loads/stores, which would be
954 * normal load/store operations.
956 * The _i32 versions are useful when operating on 32 bit quantities
957 * (eg for floating point single or using Neon helper functions).
960 /* Get value of an element within a vector register */
961 static void read_vec_element(DisasContext
*s
, TCGv_i64 tcg_dest
, int srcidx
,
962 int element
, MemOp memop
)
964 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
967 tcg_gen_ld8u_i64(tcg_dest
, cpu_env
, vect_off
);
970 tcg_gen_ld16u_i64(tcg_dest
, cpu_env
, vect_off
);
973 tcg_gen_ld32u_i64(tcg_dest
, cpu_env
, vect_off
);
976 tcg_gen_ld8s_i64(tcg_dest
, cpu_env
, vect_off
);
979 tcg_gen_ld16s_i64(tcg_dest
, cpu_env
, vect_off
);
982 tcg_gen_ld32s_i64(tcg_dest
, cpu_env
, vect_off
);
986 tcg_gen_ld_i64(tcg_dest
, cpu_env
, vect_off
);
989 g_assert_not_reached();
993 static void read_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_dest
, int srcidx
,
994 int element
, MemOp memop
)
996 int vect_off
= vec_reg_offset(s
, srcidx
, element
, memop
& MO_SIZE
);
999 tcg_gen_ld8u_i32(tcg_dest
, cpu_env
, vect_off
);
1002 tcg_gen_ld16u_i32(tcg_dest
, cpu_env
, vect_off
);
1005 tcg_gen_ld8s_i32(tcg_dest
, cpu_env
, vect_off
);
1008 tcg_gen_ld16s_i32(tcg_dest
, cpu_env
, vect_off
);
1012 tcg_gen_ld_i32(tcg_dest
, cpu_env
, vect_off
);
1015 g_assert_not_reached();
1019 /* Set value of an element within a vector register */
1020 static void write_vec_element(DisasContext
*s
, TCGv_i64 tcg_src
, int destidx
,
1021 int element
, MemOp memop
)
1023 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1026 tcg_gen_st8_i64(tcg_src
, cpu_env
, vect_off
);
1029 tcg_gen_st16_i64(tcg_src
, cpu_env
, vect_off
);
1032 tcg_gen_st32_i64(tcg_src
, cpu_env
, vect_off
);
1035 tcg_gen_st_i64(tcg_src
, cpu_env
, vect_off
);
1038 g_assert_not_reached();
1042 static void write_vec_element_i32(DisasContext
*s
, TCGv_i32 tcg_src
,
1043 int destidx
, int element
, MemOp memop
)
1045 int vect_off
= vec_reg_offset(s
, destidx
, element
, memop
& MO_SIZE
);
1048 tcg_gen_st8_i32(tcg_src
, cpu_env
, vect_off
);
1051 tcg_gen_st16_i32(tcg_src
, cpu_env
, vect_off
);
1054 tcg_gen_st_i32(tcg_src
, cpu_env
, vect_off
);
1057 g_assert_not_reached();
1061 /* Store from vector register to memory */
1062 static void do_vec_st(DisasContext
*s
, int srcidx
, int element
,
1063 TCGv_i64 tcg_addr
, int size
, MemOp endian
)
1065 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1067 read_vec_element(s
, tcg_tmp
, srcidx
, element
, size
);
1068 tcg_gen_qemu_st_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), endian
| size
);
1070 tcg_temp_free_i64(tcg_tmp
);
1073 /* Load from memory to vector register */
1074 static void do_vec_ld(DisasContext
*s
, int destidx
, int element
,
1075 TCGv_i64 tcg_addr
, int size
, MemOp endian
)
1077 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
1079 tcg_gen_qemu_ld_i64(tcg_tmp
, tcg_addr
, get_mem_index(s
), endian
| size
);
1080 write_vec_element(s
, tcg_tmp
, destidx
, element
, size
);
1082 tcg_temp_free_i64(tcg_tmp
);
1085 /* Check that FP/Neon access is enabled. If it is, return
1086 * true. If not, emit code to generate an appropriate exception,
1087 * and return false; the caller should not emit any code for
1088 * the instruction. Note that this check must happen after all
1089 * unallocated-encoding checks (otherwise the syndrome information
1090 * for the resulting exception will be incorrect).
1092 static inline bool fp_access_check(DisasContext
*s
)
1094 assert(!s
->fp_access_checked
);
1095 s
->fp_access_checked
= true;
1097 if (!s
->fp_excp_el
) {
1101 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
,
1102 syn_fp_access_trap(1, 0xe, false), s
->fp_excp_el
);
1106 /* Check that SVE access is enabled. If it is, return true.
1107 * If not, emit code to generate an appropriate exception and return false.
1109 bool sve_access_check(DisasContext
*s
)
1111 if (s
->sve_excp_el
) {
1112 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
, syn_sve_access_trap(),
1116 return fp_access_check(s
);
1120 * This utility function is for doing register extension with an
1121 * optional shift. You will likely want to pass a temporary for the
1122 * destination register. See DecodeRegExtend() in the ARM ARM.
1124 static void ext_and_shift_reg(TCGv_i64 tcg_out
, TCGv_i64 tcg_in
,
1125 int option
, unsigned int shift
)
1127 int extsize
= extract32(option
, 0, 2);
1128 bool is_signed
= extract32(option
, 2, 1);
1133 tcg_gen_ext8s_i64(tcg_out
, tcg_in
);
1136 tcg_gen_ext16s_i64(tcg_out
, tcg_in
);
1139 tcg_gen_ext32s_i64(tcg_out
, tcg_in
);
1142 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1148 tcg_gen_ext8u_i64(tcg_out
, tcg_in
);
1151 tcg_gen_ext16u_i64(tcg_out
, tcg_in
);
1154 tcg_gen_ext32u_i64(tcg_out
, tcg_in
);
1157 tcg_gen_mov_i64(tcg_out
, tcg_in
);
1163 tcg_gen_shli_i64(tcg_out
, tcg_out
, shift
);
1167 static inline void gen_check_sp_alignment(DisasContext
*s
)
1169 /* The AArch64 architecture mandates that (if enabled via PSTATE
1170 * or SCTLR bits) there is a check that SP is 16-aligned on every
1171 * SP-relative load or store (with an exception generated if it is not).
1172 * In line with general QEMU practice regarding misaligned accesses,
1173 * we omit these checks for the sake of guest program performance.
1174 * This function is provided as a hook so we can more easily add these
1175 * checks in future (possibly as a "favour catching guest program bugs
1176 * over speed" user selectable option).
1181 * This provides a simple table based table lookup decoder. It is
1182 * intended to be used when the relevant bits for decode are too
1183 * awkwardly placed and switch/if based logic would be confusing and
1184 * deeply nested. Since it's a linear search through the table, tables
1185 * should be kept small.
1187 * It returns the first handler where insn & mask == pattern, or
1188 * NULL if there is no match.
1189 * The table is terminated by an empty mask (i.e. 0)
1191 static inline AArch64DecodeFn
*lookup_disas_fn(const AArch64DecodeTable
*table
,
1194 const AArch64DecodeTable
*tptr
= table
;
1196 while (tptr
->mask
) {
1197 if ((insn
& tptr
->mask
) == tptr
->pattern
) {
1198 return tptr
->disas_fn
;
1206 * The instruction disassembly implemented here matches
1207 * the instruction encoding classifications in chapter C4
1208 * of the ARM Architecture Reference Manual (DDI0487B_a);
1209 * classification names and decode diagrams here should generally
1210 * match up with those in the manual.
1213 /* Unconditional branch (immediate)
1215 * +----+-----------+-------------------------------------+
1216 * | op | 0 0 1 0 1 | imm26 |
1217 * +----+-----------+-------------------------------------+
1219 static void disas_uncond_b_imm(DisasContext
*s
, uint32_t insn
)
1221 uint64_t addr
= s
->pc_curr
+ sextract32(insn
, 0, 26) * 4;
1223 if (insn
& (1U << 31)) {
1224 /* BL Branch with link */
1225 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->base
.pc_next
);
1228 /* B Branch / BL Branch with link */
1230 gen_goto_tb(s
, 0, addr
);
1233 /* Compare and branch (immediate)
1234 * 31 30 25 24 23 5 4 0
1235 * +----+-------------+----+---------------------+--------+
1236 * | sf | 0 1 1 0 1 0 | op | imm19 | Rt |
1237 * +----+-------------+----+---------------------+--------+
1239 static void disas_comp_b_imm(DisasContext
*s
, uint32_t insn
)
1241 unsigned int sf
, op
, rt
;
1243 TCGLabel
*label_match
;
1246 sf
= extract32(insn
, 31, 1);
1247 op
= extract32(insn
, 24, 1); /* 0: CBZ; 1: CBNZ */
1248 rt
= extract32(insn
, 0, 5);
1249 addr
= s
->pc_curr
+ sextract32(insn
, 5, 19) * 4;
1251 tcg_cmp
= read_cpu_reg(s
, rt
, sf
);
1252 label_match
= gen_new_label();
1255 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1256 tcg_cmp
, 0, label_match
);
1258 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1259 gen_set_label(label_match
);
1260 gen_goto_tb(s
, 1, addr
);
1263 /* Test and branch (immediate)
1264 * 31 30 25 24 23 19 18 5 4 0
1265 * +----+-------------+----+-------+-------------+------+
1266 * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt |
1267 * +----+-------------+----+-------+-------------+------+
1269 static void disas_test_b_imm(DisasContext
*s
, uint32_t insn
)
1271 unsigned int bit_pos
, op
, rt
;
1273 TCGLabel
*label_match
;
1276 bit_pos
= (extract32(insn
, 31, 1) << 5) | extract32(insn
, 19, 5);
1277 op
= extract32(insn
, 24, 1); /* 0: TBZ; 1: TBNZ */
1278 addr
= s
->pc_curr
+ sextract32(insn
, 5, 14) * 4;
1279 rt
= extract32(insn
, 0, 5);
1281 tcg_cmp
= tcg_temp_new_i64();
1282 tcg_gen_andi_i64(tcg_cmp
, cpu_reg(s
, rt
), (1ULL << bit_pos
));
1283 label_match
= gen_new_label();
1286 tcg_gen_brcondi_i64(op
? TCG_COND_NE
: TCG_COND_EQ
,
1287 tcg_cmp
, 0, label_match
);
1288 tcg_temp_free_i64(tcg_cmp
);
1289 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1290 gen_set_label(label_match
);
1291 gen_goto_tb(s
, 1, addr
);
1294 /* Conditional branch (immediate)
1295 * 31 25 24 23 5 4 3 0
1296 * +---------------+----+---------------------+----+------+
1297 * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond |
1298 * +---------------+----+---------------------+----+------+
1300 static void disas_cond_b_imm(DisasContext
*s
, uint32_t insn
)
1305 if ((insn
& (1 << 4)) || (insn
& (1 << 24))) {
1306 unallocated_encoding(s
);
1309 addr
= s
->pc_curr
+ sextract32(insn
, 5, 19) * 4;
1310 cond
= extract32(insn
, 0, 4);
1314 /* genuinely conditional branches */
1315 TCGLabel
*label_match
= gen_new_label();
1316 arm_gen_test_cc(cond
, label_match
);
1317 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1318 gen_set_label(label_match
);
1319 gen_goto_tb(s
, 1, addr
);
1321 /* 0xe and 0xf are both "always" conditions */
1322 gen_goto_tb(s
, 0, addr
);
1326 /* HINT instruction group, including various allocated HINTs */
1327 static void handle_hint(DisasContext
*s
, uint32_t insn
,
1328 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1330 unsigned int selector
= crm
<< 3 | op2
;
1333 unallocated_encoding(s
);
1338 case 0b00000: /* NOP */
1340 case 0b00011: /* WFI */
1341 s
->base
.is_jmp
= DISAS_WFI
;
1343 case 0b00001: /* YIELD */
1344 /* When running in MTTCG we don't generate jumps to the yield and
1345 * WFE helpers as it won't affect the scheduling of other vCPUs.
1346 * If we wanted to more completely model WFE/SEV so we don't busy
1347 * spin unnecessarily we would need to do something more involved.
1349 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1350 s
->base
.is_jmp
= DISAS_YIELD
;
1353 case 0b00010: /* WFE */
1354 if (!(tb_cflags(s
->base
.tb
) & CF_PARALLEL
)) {
1355 s
->base
.is_jmp
= DISAS_WFE
;
1358 case 0b00100: /* SEV */
1359 case 0b00101: /* SEVL */
1360 /* we treat all as NOP at least for now */
1362 case 0b00111: /* XPACLRI */
1363 if (s
->pauth_active
) {
1364 gen_helper_xpaci(cpu_X
[30], cpu_env
, cpu_X
[30]);
1367 case 0b01000: /* PACIA1716 */
1368 if (s
->pauth_active
) {
1369 gen_helper_pacia(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1372 case 0b01010: /* PACIB1716 */
1373 if (s
->pauth_active
) {
1374 gen_helper_pacib(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1377 case 0b01100: /* AUTIA1716 */
1378 if (s
->pauth_active
) {
1379 gen_helper_autia(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1382 case 0b01110: /* AUTIB1716 */
1383 if (s
->pauth_active
) {
1384 gen_helper_autib(cpu_X
[17], cpu_env
, cpu_X
[17], cpu_X
[16]);
1387 case 0b11000: /* PACIAZ */
1388 if (s
->pauth_active
) {
1389 gen_helper_pacia(cpu_X
[30], cpu_env
, cpu_X
[30],
1390 new_tmp_a64_zero(s
));
1393 case 0b11001: /* PACIASP */
1394 if (s
->pauth_active
) {
1395 gen_helper_pacia(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1398 case 0b11010: /* PACIBZ */
1399 if (s
->pauth_active
) {
1400 gen_helper_pacib(cpu_X
[30], cpu_env
, cpu_X
[30],
1401 new_tmp_a64_zero(s
));
1404 case 0b11011: /* PACIBSP */
1405 if (s
->pauth_active
) {
1406 gen_helper_pacib(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1409 case 0b11100: /* AUTIAZ */
1410 if (s
->pauth_active
) {
1411 gen_helper_autia(cpu_X
[30], cpu_env
, cpu_X
[30],
1412 new_tmp_a64_zero(s
));
1415 case 0b11101: /* AUTIASP */
1416 if (s
->pauth_active
) {
1417 gen_helper_autia(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1420 case 0b11110: /* AUTIBZ */
1421 if (s
->pauth_active
) {
1422 gen_helper_autib(cpu_X
[30], cpu_env
, cpu_X
[30],
1423 new_tmp_a64_zero(s
));
1426 case 0b11111: /* AUTIBSP */
1427 if (s
->pauth_active
) {
1428 gen_helper_autib(cpu_X
[30], cpu_env
, cpu_X
[30], cpu_X
[31]);
1432 /* default specified as NOP equivalent */
1437 static void gen_clrex(DisasContext
*s
, uint32_t insn
)
1439 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
1442 /* CLREX, DSB, DMB, ISB */
1443 static void handle_sync(DisasContext
*s
, uint32_t insn
,
1444 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1449 unallocated_encoding(s
);
1460 case 1: /* MBReqTypes_Reads */
1461 bar
= TCG_BAR_SC
| TCG_MO_LD_LD
| TCG_MO_LD_ST
;
1463 case 2: /* MBReqTypes_Writes */
1464 bar
= TCG_BAR_SC
| TCG_MO_ST_ST
;
1466 default: /* MBReqTypes_All */
1467 bar
= TCG_BAR_SC
| TCG_MO_ALL
;
1473 /* We need to break the TB after this insn to execute
1474 * a self-modified code correctly and also to take
1475 * any pending interrupts immediately.
1478 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1482 if (crm
!= 0 || !dc_isar_feature(aa64_sb
, s
)) {
1483 goto do_unallocated
;
1486 * TODO: There is no speculation barrier opcode for TCG;
1487 * MB and end the TB instead.
1489 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_SC
);
1490 gen_goto_tb(s
, 0, s
->base
.pc_next
);
1495 unallocated_encoding(s
);
1500 static void gen_xaflag(void)
1502 TCGv_i32 z
= tcg_temp_new_i32();
1504 tcg_gen_setcondi_i32(TCG_COND_EQ
, z
, cpu_ZF
, 0);
1513 tcg_gen_or_i32(cpu_NF
, cpu_CF
, z
);
1514 tcg_gen_subi_i32(cpu_NF
, cpu_NF
, 1);
1517 tcg_gen_and_i32(cpu_ZF
, z
, cpu_CF
);
1518 tcg_gen_xori_i32(cpu_ZF
, cpu_ZF
, 1);
1520 /* (!C & Z) << 31 -> -(Z & ~C) */
1521 tcg_gen_andc_i32(cpu_VF
, z
, cpu_CF
);
1522 tcg_gen_neg_i32(cpu_VF
, cpu_VF
);
1525 tcg_gen_or_i32(cpu_CF
, cpu_CF
, z
);
1527 tcg_temp_free_i32(z
);
1530 static void gen_axflag(void)
1532 tcg_gen_sari_i32(cpu_VF
, cpu_VF
, 31); /* V ? -1 : 0 */
1533 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, cpu_VF
); /* C & !V */
1535 /* !(Z | V) -> !(!ZF | V) -> ZF & !V -> ZF & ~VF */
1536 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, cpu_VF
);
1538 tcg_gen_movi_i32(cpu_NF
, 0);
1539 tcg_gen_movi_i32(cpu_VF
, 0);
1542 /* MSR (immediate) - move immediate to processor state field */
1543 static void handle_msr_i(DisasContext
*s
, uint32_t insn
,
1544 unsigned int op1
, unsigned int op2
, unsigned int crm
)
1547 int op
= op1
<< 3 | op2
;
1549 /* End the TB by default, chaining is ok. */
1550 s
->base
.is_jmp
= DISAS_TOO_MANY
;
1553 case 0x00: /* CFINV */
1554 if (crm
!= 0 || !dc_isar_feature(aa64_condm_4
, s
)) {
1555 goto do_unallocated
;
1557 tcg_gen_xori_i32(cpu_CF
, cpu_CF
, 1);
1558 s
->base
.is_jmp
= DISAS_NEXT
;
1561 case 0x01: /* XAFlag */
1562 if (crm
!= 0 || !dc_isar_feature(aa64_condm_5
, s
)) {
1563 goto do_unallocated
;
1566 s
->base
.is_jmp
= DISAS_NEXT
;
1569 case 0x02: /* AXFlag */
1570 if (crm
!= 0 || !dc_isar_feature(aa64_condm_5
, s
)) {
1571 goto do_unallocated
;
1574 s
->base
.is_jmp
= DISAS_NEXT
;
1577 case 0x03: /* UAO */
1578 if (!dc_isar_feature(aa64_uao
, s
) || s
->current_el
== 0) {
1579 goto do_unallocated
;
1582 set_pstate_bits(PSTATE_UAO
);
1584 clear_pstate_bits(PSTATE_UAO
);
1586 t1
= tcg_const_i32(s
->current_el
);
1587 gen_helper_rebuild_hflags_a64(cpu_env
, t1
);
1588 tcg_temp_free_i32(t1
);
1591 case 0x04: /* PAN */
1592 if (!dc_isar_feature(aa64_pan
, s
) || s
->current_el
== 0) {
1593 goto do_unallocated
;
1596 set_pstate_bits(PSTATE_PAN
);
1598 clear_pstate_bits(PSTATE_PAN
);
1600 t1
= tcg_const_i32(s
->current_el
);
1601 gen_helper_rebuild_hflags_a64(cpu_env
, t1
);
1602 tcg_temp_free_i32(t1
);
1605 case 0x05: /* SPSel */
1606 if (s
->current_el
== 0) {
1607 goto do_unallocated
;
1609 t1
= tcg_const_i32(crm
& PSTATE_SP
);
1610 gen_helper_msr_i_spsel(cpu_env
, t1
);
1611 tcg_temp_free_i32(t1
);
1614 case 0x1e: /* DAIFSet */
1615 t1
= tcg_const_i32(crm
);
1616 gen_helper_msr_i_daifset(cpu_env
, t1
);
1617 tcg_temp_free_i32(t1
);
1620 case 0x1f: /* DAIFClear */
1621 t1
= tcg_const_i32(crm
);
1622 gen_helper_msr_i_daifclear(cpu_env
, t1
);
1623 tcg_temp_free_i32(t1
);
1624 /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */
1625 s
->base
.is_jmp
= DISAS_UPDATE_EXIT
;
1628 case 0x1c: /* TCO */
1629 if (dc_isar_feature(aa64_mte
, s
)) {
1630 /* Full MTE is enabled -- set the TCO bit as directed. */
1632 set_pstate_bits(PSTATE_TCO
);
1634 clear_pstate_bits(PSTATE_TCO
);
1636 t1
= tcg_const_i32(s
->current_el
);
1637 gen_helper_rebuild_hflags_a64(cpu_env
, t1
);
1638 tcg_temp_free_i32(t1
);
1639 /* Many factors, including TCO, go into MTE_ACTIVE. */
1640 s
->base
.is_jmp
= DISAS_UPDATE_NOCHAIN
;
1641 } else if (dc_isar_feature(aa64_mte_insn_reg
, s
)) {
1642 /* Only "instructions accessible at EL0" -- PSTATE.TCO is WI. */
1643 s
->base
.is_jmp
= DISAS_NEXT
;
1645 goto do_unallocated
;
1651 unallocated_encoding(s
);
1656 static void gen_get_nzcv(TCGv_i64 tcg_rt
)
1658 TCGv_i32 tmp
= tcg_temp_new_i32();
1659 TCGv_i32 nzcv
= tcg_temp_new_i32();
1661 /* build bit 31, N */
1662 tcg_gen_andi_i32(nzcv
, cpu_NF
, (1U << 31));
1663 /* build bit 30, Z */
1664 tcg_gen_setcondi_i32(TCG_COND_EQ
, tmp
, cpu_ZF
, 0);
1665 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 30, 1);
1666 /* build bit 29, C */
1667 tcg_gen_deposit_i32(nzcv
, nzcv
, cpu_CF
, 29, 1);
1668 /* build bit 28, V */
1669 tcg_gen_shri_i32(tmp
, cpu_VF
, 31);
1670 tcg_gen_deposit_i32(nzcv
, nzcv
, tmp
, 28, 1);
1671 /* generate result */
1672 tcg_gen_extu_i32_i64(tcg_rt
, nzcv
);
1674 tcg_temp_free_i32(nzcv
);
1675 tcg_temp_free_i32(tmp
);
1678 static void gen_set_nzcv(TCGv_i64 tcg_rt
)
1680 TCGv_i32 nzcv
= tcg_temp_new_i32();
1682 /* take NZCV from R[t] */
1683 tcg_gen_extrl_i64_i32(nzcv
, tcg_rt
);
1686 tcg_gen_andi_i32(cpu_NF
, nzcv
, (1U << 31));
1688 tcg_gen_andi_i32(cpu_ZF
, nzcv
, (1 << 30));
1689 tcg_gen_setcondi_i32(TCG_COND_EQ
, cpu_ZF
, cpu_ZF
, 0);
1691 tcg_gen_andi_i32(cpu_CF
, nzcv
, (1 << 29));
1692 tcg_gen_shri_i32(cpu_CF
, cpu_CF
, 29);
1694 tcg_gen_andi_i32(cpu_VF
, nzcv
, (1 << 28));
1695 tcg_gen_shli_i32(cpu_VF
, cpu_VF
, 3);
1696 tcg_temp_free_i32(nzcv
);
1699 /* MRS - move from system register
1700 * MSR (register) - move to system register
1703 * These are all essentially the same insn in 'read' and 'write'
1704 * versions, with varying op0 fields.
1706 static void handle_sys(DisasContext
*s
, uint32_t insn
, bool isread
,
1707 unsigned int op0
, unsigned int op1
, unsigned int op2
,
1708 unsigned int crn
, unsigned int crm
, unsigned int rt
)
1710 const ARMCPRegInfo
*ri
;
1713 ri
= get_arm_cp_reginfo(s
->cp_regs
,
1714 ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP
,
1715 crn
, crm
, op0
, op1
, op2
));
1718 /* Unknown register; this might be a guest error or a QEMU
1719 * unimplemented feature.
1721 qemu_log_mask(LOG_UNIMP
, "%s access to unsupported AArch64 "
1722 "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n",
1723 isread
? "read" : "write", op0
, op1
, crn
, crm
, op2
);
1724 unallocated_encoding(s
);
1728 /* Check access permissions */
1729 if (!cp_access_ok(s
->current_el
, ri
, isread
)) {
1730 unallocated_encoding(s
);
1735 /* Emit code to perform further access permissions checks at
1736 * runtime; this may result in an exception.
1739 TCGv_i32 tcg_syn
, tcg_isread
;
1742 gen_a64_set_pc_im(s
->pc_curr
);
1743 tmpptr
= tcg_const_ptr(ri
);
1744 syndrome
= syn_aa64_sysregtrap(op0
, op1
, op2
, crn
, crm
, rt
, isread
);
1745 tcg_syn
= tcg_const_i32(syndrome
);
1746 tcg_isread
= tcg_const_i32(isread
);
1747 gen_helper_access_check_cp_reg(cpu_env
, tmpptr
, tcg_syn
, tcg_isread
);
1748 tcg_temp_free_ptr(tmpptr
);
1749 tcg_temp_free_i32(tcg_syn
);
1750 tcg_temp_free_i32(tcg_isread
);
1751 } else if (ri
->type
& ARM_CP_RAISES_EXC
) {
1753 * The readfn or writefn might raise an exception;
1754 * synchronize the CPU state in case it does.
1756 gen_a64_set_pc_im(s
->pc_curr
);
1759 /* Handle special cases first */
1760 switch (ri
->type
& ~(ARM_CP_FLAG_MASK
& ~ARM_CP_SPECIAL
)) {
1764 tcg_rt
= cpu_reg(s
, rt
);
1766 gen_get_nzcv(tcg_rt
);
1768 gen_set_nzcv(tcg_rt
);
1771 case ARM_CP_CURRENTEL
:
1772 /* Reads as current EL value from pstate, which is
1773 * guaranteed to be constant by the tb flags.
1775 tcg_rt
= cpu_reg(s
, rt
);
1776 tcg_gen_movi_i64(tcg_rt
, s
->current_el
<< 2);
1779 /* Writes clear the aligned block of memory which rt points into. */
1780 tcg_rt
= clean_data_tbi(s
, cpu_reg(s
, rt
));
1781 gen_helper_dc_zva(cpu_env
, tcg_rt
);
1786 if ((ri
->type
& ARM_CP_FPU
) && !fp_access_check(s
)) {
1788 } else if ((ri
->type
& ARM_CP_SVE
) && !sve_access_check(s
)) {
1792 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1796 tcg_rt
= cpu_reg(s
, rt
);
1799 if (ri
->type
& ARM_CP_CONST
) {
1800 tcg_gen_movi_i64(tcg_rt
, ri
->resetvalue
);
1801 } else if (ri
->readfn
) {
1803 tmpptr
= tcg_const_ptr(ri
);
1804 gen_helper_get_cp_reg64(tcg_rt
, cpu_env
, tmpptr
);
1805 tcg_temp_free_ptr(tmpptr
);
1807 tcg_gen_ld_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1810 if (ri
->type
& ARM_CP_CONST
) {
1811 /* If not forbidden by access permissions, treat as WI */
1813 } else if (ri
->writefn
) {
1815 tmpptr
= tcg_const_ptr(ri
);
1816 gen_helper_set_cp_reg64(cpu_env
, tmpptr
, tcg_rt
);
1817 tcg_temp_free_ptr(tmpptr
);
1819 tcg_gen_st_i64(tcg_rt
, cpu_env
, ri
->fieldoffset
);
1823 if ((tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) && (ri
->type
& ARM_CP_IO
)) {
1824 /* I/O operations must end the TB here (whether read or write) */
1825 s
->base
.is_jmp
= DISAS_UPDATE_EXIT
;
1827 if (!isread
&& !(ri
->type
& ARM_CP_SUPPRESS_TB_END
)) {
1829 * A write to any coprocessor regiser that ends a TB
1830 * must rebuild the hflags for the next TB.
1832 TCGv_i32 tcg_el
= tcg_const_i32(s
->current_el
);
1833 gen_helper_rebuild_hflags_a64(cpu_env
, tcg_el
);
1834 tcg_temp_free_i32(tcg_el
);
1836 * We default to ending the TB on a coprocessor register write,
1837 * but allow this to be suppressed by the register definition
1838 * (usually only necessary to work around guest bugs).
1840 s
->base
.is_jmp
= DISAS_UPDATE_EXIT
;
1845 * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0
1846 * +---------------------+---+-----+-----+-------+-------+-----+------+
1847 * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt |
1848 * +---------------------+---+-----+-----+-------+-------+-----+------+
1850 static void disas_system(DisasContext
*s
, uint32_t insn
)
1852 unsigned int l
, op0
, op1
, crn
, crm
, op2
, rt
;
1853 l
= extract32(insn
, 21, 1);
1854 op0
= extract32(insn
, 19, 2);
1855 op1
= extract32(insn
, 16, 3);
1856 crn
= extract32(insn
, 12, 4);
1857 crm
= extract32(insn
, 8, 4);
1858 op2
= extract32(insn
, 5, 3);
1859 rt
= extract32(insn
, 0, 5);
1862 if (l
|| rt
!= 31) {
1863 unallocated_encoding(s
);
1867 case 2: /* HINT (including allocated hints like NOP, YIELD, etc) */
1868 handle_hint(s
, insn
, op1
, op2
, crm
);
1870 case 3: /* CLREX, DSB, DMB, ISB */
1871 handle_sync(s
, insn
, op1
, op2
, crm
);
1873 case 4: /* MSR (immediate) */
1874 handle_msr_i(s
, insn
, op1
, op2
, crm
);
1877 unallocated_encoding(s
);
1882 handle_sys(s
, insn
, l
, op0
, op1
, op2
, crn
, crm
, rt
);
1885 /* Exception generation
1887 * 31 24 23 21 20 5 4 2 1 0
1888 * +-----------------+-----+------------------------+-----+----+
1889 * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL |
1890 * +-----------------------+------------------------+----------+
1892 static void disas_exc(DisasContext
*s
, uint32_t insn
)
1894 int opc
= extract32(insn
, 21, 3);
1895 int op2_ll
= extract32(insn
, 0, 5);
1896 int imm16
= extract32(insn
, 5, 16);
1901 /* For SVC, HVC and SMC we advance the single-step state
1902 * machine before taking the exception. This is architecturally
1903 * mandated, to ensure that single-stepping a system call
1904 * instruction works properly.
1909 gen_exception_insn(s
, s
->base
.pc_next
, EXCP_SWI
,
1910 syn_aa64_svc(imm16
), default_exception_el(s
));
1913 if (s
->current_el
== 0) {
1914 unallocated_encoding(s
);
1917 /* The pre HVC helper handles cases when HVC gets trapped
1918 * as an undefined insn by runtime configuration.
1920 gen_a64_set_pc_im(s
->pc_curr
);
1921 gen_helper_pre_hvc(cpu_env
);
1923 gen_exception_insn(s
, s
->base
.pc_next
, EXCP_HVC
,
1924 syn_aa64_hvc(imm16
), 2);
1927 if (s
->current_el
== 0) {
1928 unallocated_encoding(s
);
1931 gen_a64_set_pc_im(s
->pc_curr
);
1932 tmp
= tcg_const_i32(syn_aa64_smc(imm16
));
1933 gen_helper_pre_smc(cpu_env
, tmp
);
1934 tcg_temp_free_i32(tmp
);
1936 gen_exception_insn(s
, s
->base
.pc_next
, EXCP_SMC
,
1937 syn_aa64_smc(imm16
), 3);
1940 unallocated_encoding(s
);
1946 unallocated_encoding(s
);
1950 gen_exception_bkpt_insn(s
, syn_aa64_bkpt(imm16
));
1954 unallocated_encoding(s
);
1957 /* HLT. This has two purposes.
1958 * Architecturally, it is an external halting debug instruction.
1959 * Since QEMU doesn't implement external debug, we treat this as
1960 * it is required for halting debug disabled: it will UNDEF.
1961 * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction.
1963 if (semihosting_enabled() && imm16
== 0xf000) {
1964 #ifndef CONFIG_USER_ONLY
1965 /* In system mode, don't allow userspace access to semihosting,
1966 * to provide some semblance of security (and for consistency
1967 * with our 32-bit semihosting).
1969 if (s
->current_el
== 0) {
1970 unsupported_encoding(s
, insn
);
1974 gen_exception_internal_insn(s
, s
->pc_curr
, EXCP_SEMIHOST
);
1976 unsupported_encoding(s
, insn
);
1980 if (op2_ll
< 1 || op2_ll
> 3) {
1981 unallocated_encoding(s
);
1984 /* DCPS1, DCPS2, DCPS3 */
1985 unsupported_encoding(s
, insn
);
1988 unallocated_encoding(s
);
1993 /* Unconditional branch (register)
1994 * 31 25 24 21 20 16 15 10 9 5 4 0
1995 * +---------------+-------+-------+-------+------+-------+
1996 * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 |
1997 * +---------------+-------+-------+-------+------+-------+
1999 static void disas_uncond_b_reg(DisasContext
*s
, uint32_t insn
)
2001 unsigned int opc
, op2
, op3
, rn
, op4
;
2002 unsigned btype_mod
= 2; /* 0: BR, 1: BLR, 2: other */
2006 opc
= extract32(insn
, 21, 4);
2007 op2
= extract32(insn
, 16, 5);
2008 op3
= extract32(insn
, 10, 6);
2009 rn
= extract32(insn
, 5, 5);
2010 op4
= extract32(insn
, 0, 5);
2013 goto do_unallocated
;
2025 goto do_unallocated
;
2027 dst
= cpu_reg(s
, rn
);
2032 if (!dc_isar_feature(aa64_pauth
, s
)) {
2033 goto do_unallocated
;
2037 if (rn
!= 0x1f || op4
!= 0x1f) {
2038 goto do_unallocated
;
2041 modifier
= cpu_X
[31];
2043 /* BRAAZ, BRABZ, BLRAAZ, BLRABZ */
2045 goto do_unallocated
;
2047 modifier
= new_tmp_a64_zero(s
);
2049 if (s
->pauth_active
) {
2050 dst
= new_tmp_a64(s
);
2052 gen_helper_autia(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2054 gen_helper_autib(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2057 dst
= cpu_reg(s
, rn
);
2062 goto do_unallocated
;
2064 gen_a64_set_pc(s
, dst
);
2065 /* BLR also needs to load return address */
2067 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->base
.pc_next
);
2073 if (!dc_isar_feature(aa64_pauth
, s
)) {
2074 goto do_unallocated
;
2076 if ((op3
& ~1) != 2) {
2077 goto do_unallocated
;
2079 btype_mod
= opc
& 1;
2080 if (s
->pauth_active
) {
2081 dst
= new_tmp_a64(s
);
2082 modifier
= cpu_reg_sp(s
, op4
);
2084 gen_helper_autia(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2086 gen_helper_autib(dst
, cpu_env
, cpu_reg(s
, rn
), modifier
);
2089 dst
= cpu_reg(s
, rn
);
2091 gen_a64_set_pc(s
, dst
);
2092 /* BLRAA also needs to load return address */
2094 tcg_gen_movi_i64(cpu_reg(s
, 30), s
->base
.pc_next
);
2099 if (s
->current_el
== 0) {
2100 goto do_unallocated
;
2105 goto do_unallocated
;
2107 dst
= tcg_temp_new_i64();
2108 tcg_gen_ld_i64(dst
, cpu_env
,
2109 offsetof(CPUARMState
, elr_el
[s
->current_el
]));
2112 case 2: /* ERETAA */
2113 case 3: /* ERETAB */
2114 if (!dc_isar_feature(aa64_pauth
, s
)) {
2115 goto do_unallocated
;
2117 if (rn
!= 0x1f || op4
!= 0x1f) {
2118 goto do_unallocated
;
2120 dst
= tcg_temp_new_i64();
2121 tcg_gen_ld_i64(dst
, cpu_env
,
2122 offsetof(CPUARMState
, elr_el
[s
->current_el
]));
2123 if (s
->pauth_active
) {
2124 modifier
= cpu_X
[31];
2126 gen_helper_autia(dst
, cpu_env
, dst
, modifier
);
2128 gen_helper_autib(dst
, cpu_env
, dst
, modifier
);
2134 goto do_unallocated
;
2136 if (tb_cflags(s
->base
.tb
) & CF_USE_ICOUNT
) {
2140 gen_helper_exception_return(cpu_env
, dst
);
2141 tcg_temp_free_i64(dst
);
2142 /* Must exit loop to check un-masked IRQs */
2143 s
->base
.is_jmp
= DISAS_EXIT
;
2147 if (op3
!= 0 || op4
!= 0 || rn
!= 0x1f) {
2148 goto do_unallocated
;
2150 unsupported_encoding(s
, insn
);
2156 unallocated_encoding(s
);
2160 switch (btype_mod
) {
2162 if (dc_isar_feature(aa64_bti
, s
)) {
2163 /* BR to {x16,x17} or !guard -> 1, else 3. */
2164 set_btype(s
, rn
== 16 || rn
== 17 || !s
->guarded_page
? 1 : 3);
2169 if (dc_isar_feature(aa64_bti
, s
)) {
2170 /* BLR sets BTYPE to 2, regardless of source guarded page. */
2175 default: /* RET or none of the above. */
2176 /* BTYPE will be set to 0 by normal end-of-insn processing. */
2180 s
->base
.is_jmp
= DISAS_JUMP
;
2183 /* Branches, exception generating and system instructions */
2184 static void disas_b_exc_sys(DisasContext
*s
, uint32_t insn
)
2186 switch (extract32(insn
, 25, 7)) {
2187 case 0x0a: case 0x0b:
2188 case 0x4a: case 0x4b: /* Unconditional branch (immediate) */
2189 disas_uncond_b_imm(s
, insn
);
2191 case 0x1a: case 0x5a: /* Compare & branch (immediate) */
2192 disas_comp_b_imm(s
, insn
);
2194 case 0x1b: case 0x5b: /* Test & branch (immediate) */
2195 disas_test_b_imm(s
, insn
);
2197 case 0x2a: /* Conditional branch (immediate) */
2198 disas_cond_b_imm(s
, insn
);
2200 case 0x6a: /* Exception generation / System */
2201 if (insn
& (1 << 24)) {
2202 if (extract32(insn
, 22, 2) == 0) {
2203 disas_system(s
, insn
);
2205 unallocated_encoding(s
);
2211 case 0x6b: /* Unconditional branch (register) */
2212 disas_uncond_b_reg(s
, insn
);
2215 unallocated_encoding(s
);
2221 * Load/Store exclusive instructions are implemented by remembering
2222 * the value/address loaded, and seeing if these are the same
2223 * when the store is performed. This is not actually the architecturally
2224 * mandated semantics, but it works for typical guest code sequences
2225 * and avoids having to monitor regular stores.
2227 * The store exclusive uses the atomic cmpxchg primitives to avoid
2228 * races in multi-threaded linux-user and when MTTCG softmmu is
2231 static void gen_load_exclusive(DisasContext
*s
, int rt
, int rt2
,
2232 TCGv_i64 addr
, int size
, bool is_pair
)
2234 int idx
= get_mem_index(s
);
2235 MemOp memop
= s
->be_data
;
2237 g_assert(size
<= 3);
2239 g_assert(size
>= 2);
2241 /* The pair must be single-copy atomic for the doubleword. */
2242 memop
|= MO_64
| MO_ALIGN
;
2243 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2244 if (s
->be_data
== MO_LE
) {
2245 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 0, 32);
2246 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 32, 32);
2248 tcg_gen_extract_i64(cpu_reg(s
, rt
), cpu_exclusive_val
, 32, 32);
2249 tcg_gen_extract_i64(cpu_reg(s
, rt2
), cpu_exclusive_val
, 0, 32);
2252 /* The pair must be single-copy atomic for *each* doubleword, not
2253 the entire quadword, however it must be quadword aligned. */
2255 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
,
2256 memop
| MO_ALIGN_16
);
2258 TCGv_i64 addr2
= tcg_temp_new_i64();
2259 tcg_gen_addi_i64(addr2
, addr
, 8);
2260 tcg_gen_qemu_ld_i64(cpu_exclusive_high
, addr2
, idx
, memop
);
2261 tcg_temp_free_i64(addr2
);
2263 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2264 tcg_gen_mov_i64(cpu_reg(s
, rt2
), cpu_exclusive_high
);
2267 memop
|= size
| MO_ALIGN
;
2268 tcg_gen_qemu_ld_i64(cpu_exclusive_val
, addr
, idx
, memop
);
2269 tcg_gen_mov_i64(cpu_reg(s
, rt
), cpu_exclusive_val
);
2271 tcg_gen_mov_i64(cpu_exclusive_addr
, addr
);
2274 static void gen_store_exclusive(DisasContext
*s
, int rd
, int rt
, int rt2
,
2275 TCGv_i64 addr
, int size
, int is_pair
)
2277 /* if (env->exclusive_addr == addr && env->exclusive_val == [addr]
2278 * && (!is_pair || env->exclusive_high == [addr + datasize])) {
2281 * [addr + datasize] = {Rt2};
2287 * env->exclusive_addr = -1;
2289 TCGLabel
*fail_label
= gen_new_label();
2290 TCGLabel
*done_label
= gen_new_label();
2293 tcg_gen_brcond_i64(TCG_COND_NE
, addr
, cpu_exclusive_addr
, fail_label
);
2295 tmp
= tcg_temp_new_i64();
2298 if (s
->be_data
== MO_LE
) {
2299 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2301 tcg_gen_concat32_i64(tmp
, cpu_reg(s
, rt2
), cpu_reg(s
, rt
));
2303 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
,
2304 cpu_exclusive_val
, tmp
,
2306 MO_64
| MO_ALIGN
| s
->be_data
);
2307 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2308 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2309 if (!HAVE_CMPXCHG128
) {
2310 gen_helper_exit_atomic(cpu_env
);
2311 s
->base
.is_jmp
= DISAS_NORETURN
;
2312 } else if (s
->be_data
== MO_LE
) {
2313 gen_helper_paired_cmpxchg64_le_parallel(tmp
, cpu_env
,
2318 gen_helper_paired_cmpxchg64_be_parallel(tmp
, cpu_env
,
2323 } else if (s
->be_data
== MO_LE
) {
2324 gen_helper_paired_cmpxchg64_le(tmp
, cpu_env
, cpu_exclusive_addr
,
2325 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2327 gen_helper_paired_cmpxchg64_be(tmp
, cpu_env
, cpu_exclusive_addr
,
2328 cpu_reg(s
, rt
), cpu_reg(s
, rt2
));
2331 tcg_gen_atomic_cmpxchg_i64(tmp
, cpu_exclusive_addr
, cpu_exclusive_val
,
2332 cpu_reg(s
, rt
), get_mem_index(s
),
2333 size
| MO_ALIGN
| s
->be_data
);
2334 tcg_gen_setcond_i64(TCG_COND_NE
, tmp
, tmp
, cpu_exclusive_val
);
2336 tcg_gen_mov_i64(cpu_reg(s
, rd
), tmp
);
2337 tcg_temp_free_i64(tmp
);
2338 tcg_gen_br(done_label
);
2340 gen_set_label(fail_label
);
2341 tcg_gen_movi_i64(cpu_reg(s
, rd
), 1);
2342 gen_set_label(done_label
);
2343 tcg_gen_movi_i64(cpu_exclusive_addr
, -1);
2346 static void gen_compare_and_swap(DisasContext
*s
, int rs
, int rt
,
2349 TCGv_i64 tcg_rs
= cpu_reg(s
, rs
);
2350 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2351 int memidx
= get_mem_index(s
);
2352 TCGv_i64 clean_addr
;
2355 gen_check_sp_alignment(s
);
2357 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2358 tcg_gen_atomic_cmpxchg_i64(tcg_rs
, clean_addr
, tcg_rs
, tcg_rt
, memidx
,
2359 size
| MO_ALIGN
| s
->be_data
);
2362 static void gen_compare_and_swap_pair(DisasContext
*s
, int rs
, int rt
,
2365 TCGv_i64 s1
= cpu_reg(s
, rs
);
2366 TCGv_i64 s2
= cpu_reg(s
, rs
+ 1);
2367 TCGv_i64 t1
= cpu_reg(s
, rt
);
2368 TCGv_i64 t2
= cpu_reg(s
, rt
+ 1);
2369 TCGv_i64 clean_addr
;
2370 int memidx
= get_mem_index(s
);
2373 gen_check_sp_alignment(s
);
2375 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2378 TCGv_i64 cmp
= tcg_temp_new_i64();
2379 TCGv_i64 val
= tcg_temp_new_i64();
2381 if (s
->be_data
== MO_LE
) {
2382 tcg_gen_concat32_i64(val
, t1
, t2
);
2383 tcg_gen_concat32_i64(cmp
, s1
, s2
);
2385 tcg_gen_concat32_i64(val
, t2
, t1
);
2386 tcg_gen_concat32_i64(cmp
, s2
, s1
);
2389 tcg_gen_atomic_cmpxchg_i64(cmp
, clean_addr
, cmp
, val
, memidx
,
2390 MO_64
| MO_ALIGN
| s
->be_data
);
2391 tcg_temp_free_i64(val
);
2393 if (s
->be_data
== MO_LE
) {
2394 tcg_gen_extr32_i64(s1
, s2
, cmp
);
2396 tcg_gen_extr32_i64(s2
, s1
, cmp
);
2398 tcg_temp_free_i64(cmp
);
2399 } else if (tb_cflags(s
->base
.tb
) & CF_PARALLEL
) {
2400 if (HAVE_CMPXCHG128
) {
2401 TCGv_i32 tcg_rs
= tcg_const_i32(rs
);
2402 if (s
->be_data
== MO_LE
) {
2403 gen_helper_casp_le_parallel(cpu_env
, tcg_rs
,
2404 clean_addr
, t1
, t2
);
2406 gen_helper_casp_be_parallel(cpu_env
, tcg_rs
,
2407 clean_addr
, t1
, t2
);
2409 tcg_temp_free_i32(tcg_rs
);
2411 gen_helper_exit_atomic(cpu_env
);
2412 s
->base
.is_jmp
= DISAS_NORETURN
;
2415 TCGv_i64 d1
= tcg_temp_new_i64();
2416 TCGv_i64 d2
= tcg_temp_new_i64();
2417 TCGv_i64 a2
= tcg_temp_new_i64();
2418 TCGv_i64 c1
= tcg_temp_new_i64();
2419 TCGv_i64 c2
= tcg_temp_new_i64();
2420 TCGv_i64 zero
= tcg_const_i64(0);
2422 /* Load the two words, in memory order. */
2423 tcg_gen_qemu_ld_i64(d1
, clean_addr
, memidx
,
2424 MO_64
| MO_ALIGN_16
| s
->be_data
);
2425 tcg_gen_addi_i64(a2
, clean_addr
, 8);
2426 tcg_gen_qemu_ld_i64(d2
, a2
, memidx
, MO_64
| s
->be_data
);
2428 /* Compare the two words, also in memory order. */
2429 tcg_gen_setcond_i64(TCG_COND_EQ
, c1
, d1
, s1
);
2430 tcg_gen_setcond_i64(TCG_COND_EQ
, c2
, d2
, s2
);
2431 tcg_gen_and_i64(c2
, c2
, c1
);
2433 /* If compare equal, write back new data, else write back old data. */
2434 tcg_gen_movcond_i64(TCG_COND_NE
, c1
, c2
, zero
, t1
, d1
);
2435 tcg_gen_movcond_i64(TCG_COND_NE
, c2
, c2
, zero
, t2
, d2
);
2436 tcg_gen_qemu_st_i64(c1
, clean_addr
, memidx
, MO_64
| s
->be_data
);
2437 tcg_gen_qemu_st_i64(c2
, a2
, memidx
, MO_64
| s
->be_data
);
2438 tcg_temp_free_i64(a2
);
2439 tcg_temp_free_i64(c1
);
2440 tcg_temp_free_i64(c2
);
2441 tcg_temp_free_i64(zero
);
2443 /* Write back the data from memory to Rs. */
2444 tcg_gen_mov_i64(s1
, d1
);
2445 tcg_gen_mov_i64(s2
, d2
);
2446 tcg_temp_free_i64(d1
);
2447 tcg_temp_free_i64(d2
);
2451 /* Update the Sixty-Four bit (SF) registersize. This logic is derived
2452 * from the ARMv8 specs for LDR (Shared decode for all encodings).
2454 static bool disas_ldst_compute_iss_sf(int size
, bool is_signed
, int opc
)
2456 int opc0
= extract32(opc
, 0, 1);
2460 regsize
= opc0
? 32 : 64;
2462 regsize
= size
== 3 ? 64 : 32;
2464 return regsize
== 64;
2467 /* Load/store exclusive
2469 * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0
2470 * +-----+-------------+----+---+----+------+----+-------+------+------+
2471 * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt |
2472 * +-----+-------------+----+---+----+------+----+-------+------+------+
2474 * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit
2475 * L: 0 -> store, 1 -> load
2476 * o2: 0 -> exclusive, 1 -> not
2477 * o1: 0 -> single register, 1 -> register pair
2478 * o0: 1 -> load-acquire/store-release, 0 -> not
2480 static void disas_ldst_excl(DisasContext
*s
, uint32_t insn
)
2482 int rt
= extract32(insn
, 0, 5);
2483 int rn
= extract32(insn
, 5, 5);
2484 int rt2
= extract32(insn
, 10, 5);
2485 int rs
= extract32(insn
, 16, 5);
2486 int is_lasr
= extract32(insn
, 15, 1);
2487 int o2_L_o1_o0
= extract32(insn
, 21, 3) * 2 | is_lasr
;
2488 int size
= extract32(insn
, 30, 2);
2489 TCGv_i64 clean_addr
;
2491 switch (o2_L_o1_o0
) {
2492 case 0x0: /* STXR */
2493 case 0x1: /* STLXR */
2495 gen_check_sp_alignment(s
);
2498 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2500 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2501 gen_store_exclusive(s
, rs
, rt
, rt2
, clean_addr
, size
, false);
2504 case 0x4: /* LDXR */
2505 case 0x5: /* LDAXR */
2507 gen_check_sp_alignment(s
);
2509 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2511 gen_load_exclusive(s
, rt
, rt2
, clean_addr
, size
, false);
2513 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2517 case 0x8: /* STLLR */
2518 if (!dc_isar_feature(aa64_lor
, s
)) {
2521 /* StoreLORelease is the same as Store-Release for QEMU. */
2523 case 0x9: /* STLR */
2524 /* Generate ISS for non-exclusive accesses including LASR. */
2526 gen_check_sp_alignment(s
);
2528 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2529 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2530 do_gpr_st(s
, cpu_reg(s
, rt
), clean_addr
, size
, true, rt
,
2531 disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2534 case 0xc: /* LDLAR */
2535 if (!dc_isar_feature(aa64_lor
, s
)) {
2538 /* LoadLOAcquire is the same as Load-Acquire for QEMU. */
2540 case 0xd: /* LDAR */
2541 /* Generate ISS for non-exclusive accesses including LASR. */
2543 gen_check_sp_alignment(s
);
2545 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2546 do_gpr_ld(s
, cpu_reg(s
, rt
), clean_addr
, size
, false, false, true, rt
,
2547 disas_ldst_compute_iss_sf(size
, false, 0), is_lasr
);
2548 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2551 case 0x2: case 0x3: /* CASP / STXP */
2552 if (size
& 2) { /* STXP / STLXP */
2554 gen_check_sp_alignment(s
);
2557 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
2559 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2560 gen_store_exclusive(s
, rs
, rt
, rt2
, clean_addr
, size
, true);
2564 && ((rt
| rs
) & 1) == 0
2565 && dc_isar_feature(aa64_atomics
, s
)) {
2567 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2572 case 0x6: case 0x7: /* CASPA / LDXP */
2573 if (size
& 2) { /* LDXP / LDAXP */
2575 gen_check_sp_alignment(s
);
2577 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
2579 gen_load_exclusive(s
, rt
, rt2
, clean_addr
, size
, true);
2581 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
2586 && ((rt
| rs
) & 1) == 0
2587 && dc_isar_feature(aa64_atomics
, s
)) {
2588 /* CASPA / CASPAL */
2589 gen_compare_and_swap_pair(s
, rs
, rt
, rn
, size
| 2);
2595 case 0xb: /* CASL */
2596 case 0xe: /* CASA */
2597 case 0xf: /* CASAL */
2598 if (rt2
== 31 && dc_isar_feature(aa64_atomics
, s
)) {
2599 gen_compare_and_swap(s
, rs
, rt
, rn
, size
);
2604 unallocated_encoding(s
);
2608 * Load register (literal)
2610 * 31 30 29 27 26 25 24 23 5 4 0
2611 * +-----+-------+---+-----+-------------------+-------+
2612 * | opc | 0 1 1 | V | 0 0 | imm19 | Rt |
2613 * +-----+-------+---+-----+-------------------+-------+
2615 * V: 1 -> vector (simd/fp)
2616 * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit,
2617 * 10-> 32 bit signed, 11 -> prefetch
2618 * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated)
2620 static void disas_ld_lit(DisasContext
*s
, uint32_t insn
)
2622 int rt
= extract32(insn
, 0, 5);
2623 int64_t imm
= sextract32(insn
, 5, 19) << 2;
2624 bool is_vector
= extract32(insn
, 26, 1);
2625 int opc
= extract32(insn
, 30, 2);
2626 bool is_signed
= false;
2628 TCGv_i64 tcg_rt
, clean_addr
;
2632 unallocated_encoding(s
);
2636 if (!fp_access_check(s
)) {
2641 /* PRFM (literal) : prefetch */
2644 size
= 2 + extract32(opc
, 0, 1);
2645 is_signed
= extract32(opc
, 1, 1);
2648 tcg_rt
= cpu_reg(s
, rt
);
2650 clean_addr
= tcg_const_i64(s
->pc_curr
+ imm
);
2652 do_fp_ld(s
, rt
, clean_addr
, size
);
2654 /* Only unsigned 32bit loads target 32bit registers. */
2655 bool iss_sf
= opc
!= 0;
2657 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
, is_signed
, false,
2658 true, rt
, iss_sf
, false);
2660 tcg_temp_free_i64(clean_addr
);
2664 * LDNP (Load Pair - non-temporal hint)
2665 * LDP (Load Pair - non vector)
2666 * LDPSW (Load Pair Signed Word - non vector)
2667 * STNP (Store Pair - non-temporal hint)
2668 * STP (Store Pair - non vector)
2669 * LDNP (Load Pair of SIMD&FP - non-temporal hint)
2670 * LDP (Load Pair of SIMD&FP)
2671 * STNP (Store Pair of SIMD&FP - non-temporal hint)
2672 * STP (Store Pair of SIMD&FP)
2674 * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0
2675 * +-----+-------+---+---+-------+---+-----------------------------+
2676 * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt |
2677 * +-----+-------+---+---+-------+---+-------+-------+------+------+
2679 * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit
2681 * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit
2682 * V: 0 -> GPR, 1 -> Vector
2683 * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index,
2684 * 10 -> signed offset, 11 -> pre-index
2685 * L: 0 -> Store 1 -> Load
2687 * Rt, Rt2 = GPR or SIMD registers to be stored
2688 * Rn = general purpose register containing address
2689 * imm7 = signed offset (multiple of 4 or 8 depending on size)
2691 static void disas_ldst_pair(DisasContext
*s
, uint32_t insn
)
2693 int rt
= extract32(insn
, 0, 5);
2694 int rn
= extract32(insn
, 5, 5);
2695 int rt2
= extract32(insn
, 10, 5);
2696 uint64_t offset
= sextract64(insn
, 15, 7);
2697 int index
= extract32(insn
, 23, 2);
2698 bool is_vector
= extract32(insn
, 26, 1);
2699 bool is_load
= extract32(insn
, 22, 1);
2700 int opc
= extract32(insn
, 30, 2);
2702 bool is_signed
= false;
2703 bool postindex
= false;
2706 TCGv_i64 clean_addr
, dirty_addr
;
2711 unallocated_encoding(s
);
2718 size
= 2 + extract32(opc
, 1, 1);
2719 is_signed
= extract32(opc
, 0, 1);
2720 if (!is_load
&& is_signed
) {
2721 unallocated_encoding(s
);
2727 case 1: /* post-index */
2732 /* signed offset with "non-temporal" hint. Since we don't emulate
2733 * caches we don't care about hints to the cache system about
2734 * data access patterns, and handle this identically to plain
2738 /* There is no non-temporal-hint version of LDPSW */
2739 unallocated_encoding(s
);
2744 case 2: /* signed offset, rn not updated */
2747 case 3: /* pre-index */
2753 if (is_vector
&& !fp_access_check(s
)) {
2760 gen_check_sp_alignment(s
);
2763 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
2765 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
2767 clean_addr
= clean_data_tbi(s
, dirty_addr
);
2771 do_fp_ld(s
, rt
, clean_addr
, size
);
2773 do_fp_st(s
, rt
, clean_addr
, size
);
2775 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2777 do_fp_ld(s
, rt2
, clean_addr
, size
);
2779 do_fp_st(s
, rt2
, clean_addr
, size
);
2782 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2783 TCGv_i64 tcg_rt2
= cpu_reg(s
, rt2
);
2786 TCGv_i64 tmp
= tcg_temp_new_i64();
2788 /* Do not modify tcg_rt before recognizing any exception
2789 * from the second load.
2791 do_gpr_ld(s
, tmp
, clean_addr
, size
, is_signed
, false,
2792 false, 0, false, false);
2793 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2794 do_gpr_ld(s
, tcg_rt2
, clean_addr
, size
, is_signed
, false,
2795 false, 0, false, false);
2797 tcg_gen_mov_i64(tcg_rt
, tmp
);
2798 tcg_temp_free_i64(tmp
);
2800 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
2801 false, 0, false, false);
2802 tcg_gen_addi_i64(clean_addr
, clean_addr
, 1 << size
);
2803 do_gpr_st(s
, tcg_rt2
, clean_addr
, size
,
2804 false, 0, false, false);
2810 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
2812 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), dirty_addr
);
2817 * Load/store (immediate post-indexed)
2818 * Load/store (immediate pre-indexed)
2819 * Load/store (unscaled immediate)
2821 * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0
2822 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2823 * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt |
2824 * +----+-------+---+-----+-----+---+--------+-----+------+------+
2826 * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback)
2828 * V = 0 -> non-vector
2829 * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
2830 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2832 static void disas_ldst_reg_imm9(DisasContext
*s
, uint32_t insn
,
2838 int rn
= extract32(insn
, 5, 5);
2839 int imm9
= sextract32(insn
, 12, 9);
2840 int idx
= extract32(insn
, 10, 2);
2841 bool is_signed
= false;
2842 bool is_store
= false;
2843 bool is_extended
= false;
2844 bool is_unpriv
= (idx
== 2);
2845 bool iss_valid
= !is_vector
;
2849 TCGv_i64 clean_addr
, dirty_addr
;
2852 size
|= (opc
& 2) << 1;
2853 if (size
> 4 || is_unpriv
) {
2854 unallocated_encoding(s
);
2857 is_store
= ((opc
& 1) == 0);
2858 if (!fp_access_check(s
)) {
2862 if (size
== 3 && opc
== 2) {
2863 /* PRFM - prefetch */
2865 unallocated_encoding(s
);
2870 if (opc
== 3 && size
> 1) {
2871 unallocated_encoding(s
);
2874 is_store
= (opc
== 0);
2875 is_signed
= extract32(opc
, 1, 1);
2876 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
2894 g_assert_not_reached();
2898 gen_check_sp_alignment(s
);
2901 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
2903 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, imm9
);
2905 clean_addr
= clean_data_tbi(s
, dirty_addr
);
2909 do_fp_st(s
, rt
, clean_addr
, size
);
2911 do_fp_ld(s
, rt
, clean_addr
, size
);
2914 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
2915 int memidx
= is_unpriv
? get_a64_user_mem_index(s
) : get_mem_index(s
);
2916 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
2919 do_gpr_st_memidx(s
, tcg_rt
, clean_addr
, size
, memidx
,
2920 iss_valid
, rt
, iss_sf
, false);
2922 do_gpr_ld_memidx(s
, tcg_rt
, clean_addr
, size
,
2923 is_signed
, is_extended
, memidx
,
2924 iss_valid
, rt
, iss_sf
, false);
2929 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
2931 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, imm9
);
2933 tcg_gen_mov_i64(tcg_rn
, dirty_addr
);
2938 * Load/store (register offset)
2940 * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0
2941 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2942 * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt |
2943 * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+
2946 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
2947 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
2949 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
2950 * opc<0>: 0 -> store, 1 -> load
2951 * V: 1 -> vector/simd
2952 * opt: extend encoding (see DecodeRegExtend)
2953 * S: if S=1 then scale (essentially index by sizeof(size))
2954 * Rt: register to transfer into/out of
2955 * Rn: address register or SP for base
2956 * Rm: offset register or ZR for offset
2958 static void disas_ldst_reg_roffset(DisasContext
*s
, uint32_t insn
,
2964 int rn
= extract32(insn
, 5, 5);
2965 int shift
= extract32(insn
, 12, 1);
2966 int rm
= extract32(insn
, 16, 5);
2967 int opt
= extract32(insn
, 13, 3);
2968 bool is_signed
= false;
2969 bool is_store
= false;
2970 bool is_extended
= false;
2972 TCGv_i64 tcg_rm
, clean_addr
, dirty_addr
;
2974 if (extract32(opt
, 1, 1) == 0) {
2975 unallocated_encoding(s
);
2980 size
|= (opc
& 2) << 1;
2982 unallocated_encoding(s
);
2985 is_store
= !extract32(opc
, 0, 1);
2986 if (!fp_access_check(s
)) {
2990 if (size
== 3 && opc
== 2) {
2991 /* PRFM - prefetch */
2994 if (opc
== 3 && size
> 1) {
2995 unallocated_encoding(s
);
2998 is_store
= (opc
== 0);
2999 is_signed
= extract32(opc
, 1, 1);
3000 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
3004 gen_check_sp_alignment(s
);
3006 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3008 tcg_rm
= read_cpu_reg(s
, rm
, 1);
3009 ext_and_shift_reg(tcg_rm
, tcg_rm
, opt
, shift
? size
: 0);
3011 tcg_gen_add_i64(dirty_addr
, dirty_addr
, tcg_rm
);
3012 clean_addr
= clean_data_tbi(s
, dirty_addr
);
3016 do_fp_st(s
, rt
, clean_addr
, size
);
3018 do_fp_ld(s
, rt
, clean_addr
, size
);
3021 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3022 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3024 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
3025 true, rt
, iss_sf
, false);
3027 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
,
3028 is_signed
, is_extended
,
3029 true, rt
, iss_sf
, false);
3035 * Load/store (unsigned immediate)
3037 * 31 30 29 27 26 25 24 23 22 21 10 9 5
3038 * +----+-------+---+-----+-----+------------+-------+------+
3039 * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt |
3040 * +----+-------+---+-----+-----+------------+-------+------+
3043 * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit
3044 * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
3046 * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated
3047 * opc<0>: 0 -> store, 1 -> load
3048 * Rn: base address register (inc SP)
3049 * Rt: target register
3051 static void disas_ldst_reg_unsigned_imm(DisasContext
*s
, uint32_t insn
,
3057 int rn
= extract32(insn
, 5, 5);
3058 unsigned int imm12
= extract32(insn
, 10, 12);
3059 unsigned int offset
;
3061 TCGv_i64 clean_addr
, dirty_addr
;
3064 bool is_signed
= false;
3065 bool is_extended
= false;
3068 size
|= (opc
& 2) << 1;
3070 unallocated_encoding(s
);
3073 is_store
= !extract32(opc
, 0, 1);
3074 if (!fp_access_check(s
)) {
3078 if (size
== 3 && opc
== 2) {
3079 /* PRFM - prefetch */
3082 if (opc
== 3 && size
> 1) {
3083 unallocated_encoding(s
);
3086 is_store
= (opc
== 0);
3087 is_signed
= extract32(opc
, 1, 1);
3088 is_extended
= (size
< 3) && extract32(opc
, 0, 1);
3092 gen_check_sp_alignment(s
);
3094 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3095 offset
= imm12
<< size
;
3096 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3097 clean_addr
= clean_data_tbi(s
, dirty_addr
);
3101 do_fp_st(s
, rt
, clean_addr
, size
);
3103 do_fp_ld(s
, rt
, clean_addr
, size
);
3106 TCGv_i64 tcg_rt
= cpu_reg(s
, rt
);
3107 bool iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3109 do_gpr_st(s
, tcg_rt
, clean_addr
, size
,
3110 true, rt
, iss_sf
, false);
3112 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
, is_signed
, is_extended
,
3113 true, rt
, iss_sf
, false);
3118 /* Atomic memory operations
3120 * 31 30 27 26 24 22 21 16 15 12 10 5 0
3121 * +------+-------+---+-----+-----+---+----+----+-----+-----+----+-----+
3122 * | size | 1 1 1 | V | 0 0 | A R | 1 | Rs | o3 | opc | 0 0 | Rn | Rt |
3123 * +------+-------+---+-----+-----+--------+----+-----+-----+----+-----+
3125 * Rt: the result register
3126 * Rn: base address or SP
3127 * Rs: the source register for the operation
3128 * V: vector flag (always 0 as of v8.3)
3132 static void disas_ldst_atomic(DisasContext
*s
, uint32_t insn
,
3133 int size
, int rt
, bool is_vector
)
3135 int rs
= extract32(insn
, 16, 5);
3136 int rn
= extract32(insn
, 5, 5);
3137 int o3_opc
= extract32(insn
, 12, 4);
3138 bool r
= extract32(insn
, 22, 1);
3139 bool a
= extract32(insn
, 23, 1);
3140 TCGv_i64 tcg_rs
, clean_addr
;
3141 AtomicThreeOpFn
*fn
;
3143 if (is_vector
|| !dc_isar_feature(aa64_atomics
, s
)) {
3144 unallocated_encoding(s
);
3148 case 000: /* LDADD */
3149 fn
= tcg_gen_atomic_fetch_add_i64
;
3151 case 001: /* LDCLR */
3152 fn
= tcg_gen_atomic_fetch_and_i64
;
3154 case 002: /* LDEOR */
3155 fn
= tcg_gen_atomic_fetch_xor_i64
;
3157 case 003: /* LDSET */
3158 fn
= tcg_gen_atomic_fetch_or_i64
;
3160 case 004: /* LDSMAX */
3161 fn
= tcg_gen_atomic_fetch_smax_i64
;
3163 case 005: /* LDSMIN */
3164 fn
= tcg_gen_atomic_fetch_smin_i64
;
3166 case 006: /* LDUMAX */
3167 fn
= tcg_gen_atomic_fetch_umax_i64
;
3169 case 007: /* LDUMIN */
3170 fn
= tcg_gen_atomic_fetch_umin_i64
;
3173 fn
= tcg_gen_atomic_xchg_i64
;
3175 case 014: /* LDAPR, LDAPRH, LDAPRB */
3176 if (!dc_isar_feature(aa64_rcpc_8_3
, s
) ||
3177 rs
!= 31 || a
!= 1 || r
!= 0) {
3178 unallocated_encoding(s
);
3183 unallocated_encoding(s
);
3188 gen_check_sp_alignment(s
);
3190 clean_addr
= clean_data_tbi(s
, cpu_reg_sp(s
, rn
));
3192 if (o3_opc
== 014) {
3194 * LDAPR* are a special case because they are a simple load, not a
3195 * fetch-and-do-something op.
3196 * The architectural consistency requirements here are weaker than
3197 * full load-acquire (we only need "load-acquire processor consistent"),
3198 * but we choose to implement them as full LDAQ.
3200 do_gpr_ld(s
, cpu_reg(s
, rt
), clean_addr
, size
, false, false,
3201 true, rt
, disas_ldst_compute_iss_sf(size
, false, 0), true);
3202 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
3206 tcg_rs
= read_cpu_reg(s
, rs
, true);
3208 if (o3_opc
== 1) { /* LDCLR */
3209 tcg_gen_not_i64(tcg_rs
, tcg_rs
);
3212 /* The tcg atomic primitives are all full barriers. Therefore we
3213 * can ignore the Acquire and Release bits of this instruction.
3215 fn(cpu_reg(s
, rt
), clean_addr
, tcg_rs
, get_mem_index(s
),
3216 s
->be_data
| size
| MO_ALIGN
);
3220 * PAC memory operations
3222 * 31 30 27 26 24 22 21 12 11 10 5 0
3223 * +------+-------+---+-----+-----+---+--------+---+---+----+-----+
3224 * | size | 1 1 1 | V | 0 0 | M S | 1 | imm9 | W | 1 | Rn | Rt |
3225 * +------+-------+---+-----+-----+---+--------+---+---+----+-----+
3227 * Rt: the result register
3228 * Rn: base address or SP
3229 * V: vector flag (always 0 as of v8.3)
3230 * M: clear for key DA, set for key DB
3231 * W: pre-indexing flag
3234 static void disas_ldst_pac(DisasContext
*s
, uint32_t insn
,
3235 int size
, int rt
, bool is_vector
)
3237 int rn
= extract32(insn
, 5, 5);
3238 bool is_wback
= extract32(insn
, 11, 1);
3239 bool use_key_a
= !extract32(insn
, 23, 1);
3241 TCGv_i64 clean_addr
, dirty_addr
, tcg_rt
;
3243 if (size
!= 3 || is_vector
|| !dc_isar_feature(aa64_pauth
, s
)) {
3244 unallocated_encoding(s
);
3249 gen_check_sp_alignment(s
);
3251 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3253 if (s
->pauth_active
) {
3255 gen_helper_autda(dirty_addr
, cpu_env
, dirty_addr
, cpu_X
[31]);
3257 gen_helper_autdb(dirty_addr
, cpu_env
, dirty_addr
, cpu_X
[31]);
3261 /* Form the 10-bit signed, scaled offset. */
3262 offset
= (extract32(insn
, 22, 1) << 9) | extract32(insn
, 12, 9);
3263 offset
= sextract32(offset
<< size
, 0, 10 + size
);
3264 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3266 /* Note that "clean" and "dirty" here refer to TBI not PAC. */
3267 clean_addr
= clean_data_tbi(s
, dirty_addr
);
3269 tcg_rt
= cpu_reg(s
, rt
);
3270 do_gpr_ld(s
, tcg_rt
, clean_addr
, size
, /* is_signed */ false,
3271 /* extend */ false, /* iss_valid */ !is_wback
,
3272 /* iss_srt */ rt
, /* iss_sf */ true, /* iss_ar */ false);
3275 tcg_gen_mov_i64(cpu_reg_sp(s
, rn
), dirty_addr
);
3280 * LDAPR/STLR (unscaled immediate)
3282 * 31 30 24 22 21 12 10 5 0
3283 * +------+-------------+-----+---+--------+-----+----+-----+
3284 * | size | 0 1 1 0 0 1 | opc | 0 | imm9 | 0 0 | Rn | Rt |
3285 * +------+-------------+-----+---+--------+-----+----+-----+
3287 * Rt: source or destination register
3289 * imm9: unscaled immediate offset
3290 * opc: 00: STLUR*, 01/10/11: various LDAPUR*
3291 * size: size of load/store
3293 static void disas_ldst_ldapr_stlr(DisasContext
*s
, uint32_t insn
)
3295 int rt
= extract32(insn
, 0, 5);
3296 int rn
= extract32(insn
, 5, 5);
3297 int offset
= sextract32(insn
, 12, 9);
3298 int opc
= extract32(insn
, 22, 2);
3299 int size
= extract32(insn
, 30, 2);
3300 TCGv_i64 clean_addr
, dirty_addr
;
3301 bool is_store
= false;
3302 bool is_signed
= false;
3303 bool extend
= false;
3306 if (!dc_isar_feature(aa64_rcpc_8_4
, s
)) {
3307 unallocated_encoding(s
);
3312 case 0: /* STLURB */
3315 case 1: /* LDAPUR* */
3317 case 2: /* LDAPURS* 64-bit variant */
3319 unallocated_encoding(s
);
3324 case 3: /* LDAPURS* 32-bit variant */
3326 unallocated_encoding(s
);
3330 extend
= true; /* zero-extend 32->64 after signed load */
3333 g_assert_not_reached();
3336 iss_sf
= disas_ldst_compute_iss_sf(size
, is_signed
, opc
);
3339 gen_check_sp_alignment(s
);
3342 dirty_addr
= read_cpu_reg_sp(s
, rn
, 1);
3343 tcg_gen_addi_i64(dirty_addr
, dirty_addr
, offset
);
3344 clean_addr
= clean_data_tbi(s
, dirty_addr
);
3347 /* Store-Release semantics */
3348 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
3349 do_gpr_st(s
, cpu_reg(s
, rt
), clean_addr
, size
, true, rt
, iss_sf
, true);
3352 * Load-AcquirePC semantics; we implement as the slightly more
3353 * restrictive Load-Acquire.
3355 do_gpr_ld(s
, cpu_reg(s
, rt
), clean_addr
, size
, is_signed
, extend
,
3356 true, rt
, iss_sf
, true);
3357 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
3361 /* Load/store register (all forms) */
3362 static void disas_ldst_reg(DisasContext
*s
, uint32_t insn
)
3364 int rt
= extract32(insn
, 0, 5);
3365 int opc
= extract32(insn
, 22, 2);
3366 bool is_vector
= extract32(insn
, 26, 1);
3367 int size
= extract32(insn
, 30, 2);
3369 switch (extract32(insn
, 24, 2)) {
3371 if (extract32(insn
, 21, 1) == 0) {
3372 /* Load/store register (unscaled immediate)
3373 * Load/store immediate pre/post-indexed
3374 * Load/store register unprivileged
3376 disas_ldst_reg_imm9(s
, insn
, opc
, size
, rt
, is_vector
);
3379 switch (extract32(insn
, 10, 2)) {
3381 disas_ldst_atomic(s
, insn
, size
, rt
, is_vector
);
3384 disas_ldst_reg_roffset(s
, insn
, opc
, size
, rt
, is_vector
);
3387 disas_ldst_pac(s
, insn
, size
, rt
, is_vector
);
3392 disas_ldst_reg_unsigned_imm(s
, insn
, opc
, size
, rt
, is_vector
);
3395 unallocated_encoding(s
);
3398 /* AdvSIMD load/store multiple structures
3400 * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0
3401 * +---+---+---------------+---+-------------+--------+------+------+------+
3402 * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt |
3403 * +---+---+---------------+---+-------------+--------+------+------+------+
3405 * AdvSIMD load/store multiple structures (post-indexed)
3407 * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0
3408 * +---+---+---------------+---+---+---------+--------+------+------+------+
3409 * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt |
3410 * +---+---+---------------+---+---+---------+--------+------+------+------+
3412 * Rt: first (or only) SIMD&FP register to be transferred
3413 * Rn: base address or SP
3414 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3416 static void disas_ldst_multiple_struct(DisasContext
*s
, uint32_t insn
)
3418 int rt
= extract32(insn
, 0, 5);
3419 int rn
= extract32(insn
, 5, 5);
3420 int rm
= extract32(insn
, 16, 5);
3421 int size
= extract32(insn
, 10, 2);
3422 int opcode
= extract32(insn
, 12, 4);
3423 bool is_store
= !extract32(insn
, 22, 1);
3424 bool is_postidx
= extract32(insn
, 23, 1);
3425 bool is_q
= extract32(insn
, 30, 1);
3426 TCGv_i64 clean_addr
, tcg_rn
, tcg_ebytes
;
3427 MemOp endian
= s
->be_data
;
3429 int ebytes
; /* bytes per element */
3430 int elements
; /* elements per vector */
3431 int rpt
; /* num iterations */
3432 int selem
; /* structure elements */
3435 if (extract32(insn
, 31, 1) || extract32(insn
, 21, 1)) {
3436 unallocated_encoding(s
);
3440 if (!is_postidx
&& rm
!= 0) {
3441 unallocated_encoding(s
);
3445 /* From the shared decode logic */
3476 unallocated_encoding(s
);
3480 if (size
== 3 && !is_q
&& selem
!= 1) {
3482 unallocated_encoding(s
);
3486 if (!fp_access_check(s
)) {
3491 gen_check_sp_alignment(s
);
3494 /* For our purposes, bytes are always little-endian. */
3499 /* Consecutive little-endian elements from a single register
3500 * can be promoted to a larger little-endian operation.
3502 if (selem
== 1 && endian
== MO_LE
) {
3506 elements
= (is_q
? 16 : 8) / ebytes
;
3508 tcg_rn
= cpu_reg_sp(s
, rn
);
3509 clean_addr
= clean_data_tbi(s
, tcg_rn
);
3510 tcg_ebytes
= tcg_const_i64(ebytes
);
3512 for (r
= 0; r
< rpt
; r
++) {
3514 for (e
= 0; e
< elements
; e
++) {
3516 for (xs
= 0; xs
< selem
; xs
++) {
3517 int tt
= (rt
+ r
+ xs
) % 32;
3519 do_vec_st(s
, tt
, e
, clean_addr
, size
, endian
);
3521 do_vec_ld(s
, tt
, e
, clean_addr
, size
, endian
);
3523 tcg_gen_add_i64(clean_addr
, clean_addr
, tcg_ebytes
);
3527 tcg_temp_free_i64(tcg_ebytes
);
3530 /* For non-quad operations, setting a slice of the low
3531 * 64 bits of the register clears the high 64 bits (in
3532 * the ARM ARM pseudocode this is implicit in the fact
3533 * that 'rval' is a 64 bit wide variable).
3534 * For quad operations, we might still need to zero the
3537 for (r
= 0; r
< rpt
* selem
; r
++) {
3538 int tt
= (rt
+ r
) % 32;
3539 clear_vec_high(s
, is_q
, tt
);
3545 tcg_gen_addi_i64(tcg_rn
, tcg_rn
, rpt
* elements
* selem
* ebytes
);
3547 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3552 /* AdvSIMD load/store single structure
3554 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3555 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3556 * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt |
3557 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3559 * AdvSIMD load/store single structure (post-indexed)
3561 * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0
3562 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3563 * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt |
3564 * +---+---+---------------+-----+-----------+-----+---+------+------+------+
3566 * Rt: first (or only) SIMD&FP register to be transferred
3567 * Rn: base address or SP
3568 * Rm (post-index only): post-index register (when !31) or size dependent #imm
3569 * index = encoded in Q:S:size dependent on size
3571 * lane_size = encoded in R, opc
3572 * transfer width = encoded in opc, S, size
3574 static void disas_ldst_single_struct(DisasContext
*s
, uint32_t insn
)
3576 int rt
= extract32(insn
, 0, 5);
3577 int rn
= extract32(insn
, 5, 5);
3578 int rm
= extract32(insn
, 16, 5);
3579 int size
= extract32(insn
, 10, 2);
3580 int S
= extract32(insn
, 12, 1);
3581 int opc
= extract32(insn
, 13, 3);
3582 int R
= extract32(insn
, 21, 1);
3583 int is_load
= extract32(insn
, 22, 1);
3584 int is_postidx
= extract32(insn
, 23, 1);
3585 int is_q
= extract32(insn
, 30, 1);
3587 int scale
= extract32(opc
, 1, 2);
3588 int selem
= (extract32(opc
, 0, 1) << 1 | R
) + 1;
3589 bool replicate
= false;
3590 int index
= is_q
<< 3 | S
<< 2 | size
;
3592 TCGv_i64 clean_addr
, tcg_rn
, tcg_ebytes
;
3594 if (extract32(insn
, 31, 1)) {
3595 unallocated_encoding(s
);
3598 if (!is_postidx
&& rm
!= 0) {
3599 unallocated_encoding(s
);
3605 if (!is_load
|| S
) {
3606 unallocated_encoding(s
);
3615 if (extract32(size
, 0, 1)) {
3616 unallocated_encoding(s
);
3622 if (extract32(size
, 1, 1)) {
3623 unallocated_encoding(s
);
3626 if (!extract32(size
, 0, 1)) {
3630 unallocated_encoding(s
);
3638 g_assert_not_reached();
3641 if (!fp_access_check(s
)) {
3645 ebytes
= 1 << scale
;
3648 gen_check_sp_alignment(s
);
3651 tcg_rn
= cpu_reg_sp(s
, rn
);
3652 clean_addr
= clean_data_tbi(s
, tcg_rn
);
3653 tcg_ebytes
= tcg_const_i64(ebytes
);
3655 for (xs
= 0; xs
< selem
; xs
++) {
3657 /* Load and replicate to all elements */
3658 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
3660 tcg_gen_qemu_ld_i64(tcg_tmp
, clean_addr
,
3661 get_mem_index(s
), s
->be_data
+ scale
);
3662 tcg_gen_gvec_dup_i64(scale
, vec_full_reg_offset(s
, rt
),
3663 (is_q
+ 1) * 8, vec_full_reg_size(s
),
3665 tcg_temp_free_i64(tcg_tmp
);
3667 /* Load/store one element per register */
3669 do_vec_ld(s
, rt
, index
, clean_addr
, scale
, s
->be_data
);
3671 do_vec_st(s
, rt
, index
, clean_addr
, scale
, s
->be_data
);
3674 tcg_gen_add_i64(clean_addr
, clean_addr
, tcg_ebytes
);
3677 tcg_temp_free_i64(tcg_ebytes
);
3681 tcg_gen_addi_i64(tcg_rn
, tcg_rn
, selem
* ebytes
);
3683 tcg_gen_add_i64(tcg_rn
, tcg_rn
, cpu_reg(s
, rm
));
3688 /* Loads and stores */
3689 static void disas_ldst(DisasContext
*s
, uint32_t insn
)
3691 switch (extract32(insn
, 24, 6)) {
3692 case 0x08: /* Load/store exclusive */
3693 disas_ldst_excl(s
, insn
);
3695 case 0x18: case 0x1c: /* Load register (literal) */
3696 disas_ld_lit(s
, insn
);
3698 case 0x28: case 0x29:
3699 case 0x2c: case 0x2d: /* Load/store pair (all forms) */
3700 disas_ldst_pair(s
, insn
);
3702 case 0x38: case 0x39:
3703 case 0x3c: case 0x3d: /* Load/store register (all forms) */
3704 disas_ldst_reg(s
, insn
);
3706 case 0x0c: /* AdvSIMD load/store multiple structures */
3707 disas_ldst_multiple_struct(s
, insn
);
3709 case 0x0d: /* AdvSIMD load/store single structure */
3710 disas_ldst_single_struct(s
, insn
);
3712 case 0x19: /* LDAPR/STLR (unscaled immediate) */
3713 if (extract32(insn
, 10, 2) != 0 ||
3714 extract32(insn
, 21, 1) != 0) {
3715 unallocated_encoding(s
);
3718 disas_ldst_ldapr_stlr(s
, insn
);
3721 unallocated_encoding(s
);
3726 /* PC-rel. addressing
3727 * 31 30 29 28 24 23 5 4 0
3728 * +----+-------+-----------+-------------------+------+
3729 * | op | immlo | 1 0 0 0 0 | immhi | Rd |
3730 * +----+-------+-----------+-------------------+------+
3732 static void disas_pc_rel_adr(DisasContext
*s
, uint32_t insn
)
3734 unsigned int page
, rd
;
3738 page
= extract32(insn
, 31, 1);
3739 /* SignExtend(immhi:immlo) -> offset */
3740 offset
= sextract64(insn
, 5, 19);
3741 offset
= offset
<< 2 | extract32(insn
, 29, 2);
3742 rd
= extract32(insn
, 0, 5);
3746 /* ADRP (page based) */
3751 tcg_gen_movi_i64(cpu_reg(s
, rd
), base
+ offset
);
3755 * Add/subtract (immediate)
3757 * 31 30 29 28 23 22 21 10 9 5 4 0
3758 * +--+--+--+-------------+--+-------------+-----+-----+
3759 * |sf|op| S| 1 0 0 0 1 0 |sh| imm12 | Rn | Rd |
3760 * +--+--+--+-------------+--+-------------+-----+-----+
3762 * sf: 0 -> 32bit, 1 -> 64bit
3763 * op: 0 -> add , 1 -> sub
3765 * sh: 1 -> LSL imm by 12
3767 static void disas_add_sub_imm(DisasContext
*s
, uint32_t insn
)
3769 int rd
= extract32(insn
, 0, 5);
3770 int rn
= extract32(insn
, 5, 5);
3771 uint64_t imm
= extract32(insn
, 10, 12);
3772 bool shift
= extract32(insn
, 22, 1);
3773 bool setflags
= extract32(insn
, 29, 1);
3774 bool sub_op
= extract32(insn
, 30, 1);
3775 bool is_64bit
= extract32(insn
, 31, 1);
3777 TCGv_i64 tcg_rn
= cpu_reg_sp(s
, rn
);
3778 TCGv_i64 tcg_rd
= setflags
? cpu_reg(s
, rd
) : cpu_reg_sp(s
, rd
);
3779 TCGv_i64 tcg_result
;
3785 tcg_result
= tcg_temp_new_i64();
3788 tcg_gen_subi_i64(tcg_result
, tcg_rn
, imm
);
3790 tcg_gen_addi_i64(tcg_result
, tcg_rn
, imm
);
3793 TCGv_i64 tcg_imm
= tcg_const_i64(imm
);
3795 gen_sub_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
3797 gen_add_CC(is_64bit
, tcg_result
, tcg_rn
, tcg_imm
);
3799 tcg_temp_free_i64(tcg_imm
);
3803 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
3805 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
3808 tcg_temp_free_i64(tcg_result
);
3812 * Add/subtract (immediate, with tags)
3814 * 31 30 29 28 23 22 21 16 14 10 9 5 4 0
3815 * +--+--+--+-------------+--+---------+--+-------+-----+-----+
3816 * |sf|op| S| 1 0 0 0 1 1 |o2| uimm6 |o3| uimm4 | Rn | Rd |
3817 * +--+--+--+-------------+--+---------+--+-------+-----+-----+
3819 * op: 0 -> add, 1 -> sub
3821 static void disas_add_sub_imm_with_tags(DisasContext
*s
, uint32_t insn
)
3823 int rd
= extract32(insn
, 0, 5);
3824 int rn
= extract32(insn
, 5, 5);
3825 int uimm4
= extract32(insn
, 10, 4);
3826 int uimm6
= extract32(insn
, 16, 6);
3827 bool sub_op
= extract32(insn
, 30, 1);
3828 TCGv_i64 tcg_rn
, tcg_rd
;
3831 /* Test all of sf=1, S=0, o2=0, o3=0. */
3832 if ((insn
& 0xa040c000u
) != 0x80000000u
||
3833 !dc_isar_feature(aa64_mte_insn_reg
, s
)) {
3834 unallocated_encoding(s
);
3838 imm
= uimm6
<< LOG2_TAG_GRANULE
;
3843 tcg_rn
= cpu_reg_sp(s
, rn
);
3844 tcg_rd
= cpu_reg_sp(s
, rd
);
3847 TCGv_i32 offset
= tcg_const_i32(imm
);
3848 TCGv_i32 tag_offset
= tcg_const_i32(uimm4
);
3850 gen_helper_addsubg(tcg_rd
, cpu_env
, tcg_rn
, offset
, tag_offset
);
3851 tcg_temp_free_i32(tag_offset
);
3852 tcg_temp_free_i32(offset
);
3854 tcg_gen_addi_i64(tcg_rd
, tcg_rn
, imm
);
3855 gen_address_with_allocation_tag0(tcg_rd
, tcg_rd
);
3859 /* The input should be a value in the bottom e bits (with higher
3860 * bits zero); returns that value replicated into every element
3861 * of size e in a 64 bit integer.
3863 static uint64_t bitfield_replicate(uint64_t mask
, unsigned int e
)
3873 /* Return a value with the bottom len bits set (where 0 < len <= 64) */
3874 static inline uint64_t bitmask64(unsigned int length
)
3876 assert(length
> 0 && length
<= 64);
3877 return ~0ULL >> (64 - length
);
3880 /* Simplified variant of pseudocode DecodeBitMasks() for the case where we
3881 * only require the wmask. Returns false if the imms/immr/immn are a reserved
3882 * value (ie should cause a guest UNDEF exception), and true if they are
3883 * valid, in which case the decoded bit pattern is written to result.
3885 bool logic_imm_decode_wmask(uint64_t *result
, unsigned int immn
,
3886 unsigned int imms
, unsigned int immr
)
3889 unsigned e
, levels
, s
, r
;
3892 assert(immn
< 2 && imms
< 64 && immr
< 64);
3894 /* The bit patterns we create here are 64 bit patterns which
3895 * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or
3896 * 64 bits each. Each element contains the same value: a run
3897 * of between 1 and e-1 non-zero bits, rotated within the
3898 * element by between 0 and e-1 bits.
3900 * The element size and run length are encoded into immn (1 bit)
3901 * and imms (6 bits) as follows:
3902 * 64 bit elements: immn = 1, imms = <length of run - 1>
3903 * 32 bit elements: immn = 0, imms = 0 : <length of run - 1>
3904 * 16 bit elements: immn = 0, imms = 10 : <length of run - 1>
3905 * 8 bit elements: immn = 0, imms = 110 : <length of run - 1>
3906 * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1>
3907 * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1>
3908 * Notice that immn = 0, imms = 11111x is the only combination
3909 * not covered by one of the above options; this is reserved.
3910 * Further, <length of run - 1> all-ones is a reserved pattern.
3912 * In all cases the rotation is by immr % e (and immr is 6 bits).
3915 /* First determine the element size */
3916 len
= 31 - clz32((immn
<< 6) | (~imms
& 0x3f));
3918 /* This is the immn == 0, imms == 0x11111x case */
3928 /* <length of run - 1> mustn't be all-ones. */
3932 /* Create the value of one element: s+1 set bits rotated
3933 * by r within the element (which is e bits wide)...
3935 mask
= bitmask64(s
+ 1);
3937 mask
= (mask
>> r
) | (mask
<< (e
- r
));
3938 mask
&= bitmask64(e
);
3940 /* ...then replicate the element over the whole 64 bit value */
3941 mask
= bitfield_replicate(mask
, e
);
3946 /* Logical (immediate)
3947 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
3948 * +----+-----+-------------+---+------+------+------+------+
3949 * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd |
3950 * +----+-----+-------------+---+------+------+------+------+
3952 static void disas_logic_imm(DisasContext
*s
, uint32_t insn
)
3954 unsigned int sf
, opc
, is_n
, immr
, imms
, rn
, rd
;
3955 TCGv_i64 tcg_rd
, tcg_rn
;
3957 bool is_and
= false;
3959 sf
= extract32(insn
, 31, 1);
3960 opc
= extract32(insn
, 29, 2);
3961 is_n
= extract32(insn
, 22, 1);
3962 immr
= extract32(insn
, 16, 6);
3963 imms
= extract32(insn
, 10, 6);
3964 rn
= extract32(insn
, 5, 5);
3965 rd
= extract32(insn
, 0, 5);
3968 unallocated_encoding(s
);
3972 if (opc
== 0x3) { /* ANDS */
3973 tcg_rd
= cpu_reg(s
, rd
);
3975 tcg_rd
= cpu_reg_sp(s
, rd
);
3977 tcg_rn
= cpu_reg(s
, rn
);
3979 if (!logic_imm_decode_wmask(&wmask
, is_n
, imms
, immr
)) {
3980 /* some immediate field values are reserved */
3981 unallocated_encoding(s
);
3986 wmask
&= 0xffffffff;
3990 case 0x3: /* ANDS */
3992 tcg_gen_andi_i64(tcg_rd
, tcg_rn
, wmask
);
3996 tcg_gen_ori_i64(tcg_rd
, tcg_rn
, wmask
);
3999 tcg_gen_xori_i64(tcg_rd
, tcg_rn
, wmask
);
4002 assert(FALSE
); /* must handle all above */
4006 if (!sf
&& !is_and
) {
4007 /* zero extend final result; we know we can skip this for AND
4008 * since the immediate had the high 32 bits clear.
4010 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4013 if (opc
== 3) { /* ANDS */
4014 gen_logic_CC(sf
, tcg_rd
);
4019 * Move wide (immediate)
4021 * 31 30 29 28 23 22 21 20 5 4 0
4022 * +--+-----+-------------+-----+----------------+------+
4023 * |sf| opc | 1 0 0 1 0 1 | hw | imm16 | Rd |
4024 * +--+-----+-------------+-----+----------------+------+
4026 * sf: 0 -> 32 bit, 1 -> 64 bit
4027 * opc: 00 -> N, 10 -> Z, 11 -> K
4028 * hw: shift/16 (0,16, and sf only 32, 48)
4030 static void disas_movw_imm(DisasContext
*s
, uint32_t insn
)
4032 int rd
= extract32(insn
, 0, 5);
4033 uint64_t imm
= extract32(insn
, 5, 16);
4034 int sf
= extract32(insn
, 31, 1);
4035 int opc
= extract32(insn
, 29, 2);
4036 int pos
= extract32(insn
, 21, 2) << 4;
4037 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4040 if (!sf
&& (pos
>= 32)) {
4041 unallocated_encoding(s
);
4055 tcg_gen_movi_i64(tcg_rd
, imm
);
4058 tcg_imm
= tcg_const_i64(imm
);
4059 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_imm
, pos
, 16);
4060 tcg_temp_free_i64(tcg_imm
);
4062 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4066 unallocated_encoding(s
);
4072 * 31 30 29 28 23 22 21 16 15 10 9 5 4 0
4073 * +----+-----+-------------+---+------+------+------+------+
4074 * | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
4075 * +----+-----+-------------+---+------+------+------+------+
4077 static void disas_bitfield(DisasContext
*s
, uint32_t insn
)
4079 unsigned int sf
, n
, opc
, ri
, si
, rn
, rd
, bitsize
, pos
, len
;
4080 TCGv_i64 tcg_rd
, tcg_tmp
;
4082 sf
= extract32(insn
, 31, 1);
4083 opc
= extract32(insn
, 29, 2);
4084 n
= extract32(insn
, 22, 1);
4085 ri
= extract32(insn
, 16, 6);
4086 si
= extract32(insn
, 10, 6);
4087 rn
= extract32(insn
, 5, 5);
4088 rd
= extract32(insn
, 0, 5);
4089 bitsize
= sf
? 64 : 32;
4091 if (sf
!= n
|| ri
>= bitsize
|| si
>= bitsize
|| opc
> 2) {
4092 unallocated_encoding(s
);
4096 tcg_rd
= cpu_reg(s
, rd
);
4098 /* Suppress the zero-extend for !sf. Since RI and SI are constrained
4099 to be smaller than bitsize, we'll never reference data outside the
4100 low 32-bits anyway. */
4101 tcg_tmp
= read_cpu_reg(s
, rn
, 1);
4103 /* Recognize simple(r) extractions. */
4105 /* Wd<s-r:0> = Wn<s:r> */
4106 len
= (si
- ri
) + 1;
4107 if (opc
== 0) { /* SBFM: ASR, SBFX, SXTB, SXTH, SXTW */
4108 tcg_gen_sextract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
4110 } else if (opc
== 2) { /* UBFM: UBFX, LSR, UXTB, UXTH */
4111 tcg_gen_extract_i64(tcg_rd
, tcg_tmp
, ri
, len
);
4114 /* opc == 1, BFXIL fall through to deposit */
4115 tcg_gen_shri_i64(tcg_tmp
, tcg_tmp
, ri
);
4118 /* Handle the ri > si case with a deposit
4119 * Wd<32+s-r,32-r> = Wn<s:0>
4122 pos
= (bitsize
- ri
) & (bitsize
- 1);
4125 if (opc
== 0 && len
< ri
) {
4126 /* SBFM: sign extend the destination field from len to fill
4127 the balance of the word. Let the deposit below insert all
4128 of those sign bits. */
4129 tcg_gen_sextract_i64(tcg_tmp
, tcg_tmp
, 0, len
);
4133 if (opc
== 1) { /* BFM, BFXIL */
4134 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_tmp
, pos
, len
);
4136 /* SBFM or UBFM: We start with zero, and we haven't modified
4137 any bits outside bitsize, therefore the zero-extension
4138 below is unneeded. */
4139 tcg_gen_deposit_z_i64(tcg_rd
, tcg_tmp
, pos
, len
);
4144 if (!sf
) { /* zero extend final result */
4145 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4150 * 31 30 29 28 23 22 21 20 16 15 10 9 5 4 0
4151 * +----+------+-------------+---+----+------+--------+------+------+
4152 * | sf | op21 | 1 0 0 1 1 1 | N | o0 | Rm | imms | Rn | Rd |
4153 * +----+------+-------------+---+----+------+--------+------+------+
4155 static void disas_extract(DisasContext
*s
, uint32_t insn
)
4157 unsigned int sf
, n
, rm
, imm
, rn
, rd
, bitsize
, op21
, op0
;
4159 sf
= extract32(insn
, 31, 1);
4160 n
= extract32(insn
, 22, 1);
4161 rm
= extract32(insn
, 16, 5);
4162 imm
= extract32(insn
, 10, 6);
4163 rn
= extract32(insn
, 5, 5);
4164 rd
= extract32(insn
, 0, 5);
4165 op21
= extract32(insn
, 29, 2);
4166 op0
= extract32(insn
, 21, 1);
4167 bitsize
= sf
? 64 : 32;
4169 if (sf
!= n
|| op21
|| op0
|| imm
>= bitsize
) {
4170 unallocated_encoding(s
);
4172 TCGv_i64 tcg_rd
, tcg_rm
, tcg_rn
;
4174 tcg_rd
= cpu_reg(s
, rd
);
4176 if (unlikely(imm
== 0)) {
4177 /* tcg shl_i32/shl_i64 is undefined for 32/64 bit shifts,
4178 * so an extract from bit 0 is a special case.
4181 tcg_gen_mov_i64(tcg_rd
, cpu_reg(s
, rm
));
4183 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rm
));
4186 tcg_rm
= cpu_reg(s
, rm
);
4187 tcg_rn
= cpu_reg(s
, rn
);
4190 /* Specialization to ROR happens in EXTRACT2. */
4191 tcg_gen_extract2_i64(tcg_rd
, tcg_rm
, tcg_rn
, imm
);
4193 TCGv_i32 t0
= tcg_temp_new_i32();
4195 tcg_gen_extrl_i64_i32(t0
, tcg_rm
);
4197 tcg_gen_rotri_i32(t0
, t0
, imm
);
4199 TCGv_i32 t1
= tcg_temp_new_i32();
4200 tcg_gen_extrl_i64_i32(t1
, tcg_rn
);
4201 tcg_gen_extract2_i32(t0
, t0
, t1
, imm
);
4202 tcg_temp_free_i32(t1
);
4204 tcg_gen_extu_i32_i64(tcg_rd
, t0
);
4205 tcg_temp_free_i32(t0
);
4211 /* Data processing - immediate */
4212 static void disas_data_proc_imm(DisasContext
*s
, uint32_t insn
)
4214 switch (extract32(insn
, 23, 6)) {
4215 case 0x20: case 0x21: /* PC-rel. addressing */
4216 disas_pc_rel_adr(s
, insn
);
4218 case 0x22: /* Add/subtract (immediate) */
4219 disas_add_sub_imm(s
, insn
);
4221 case 0x23: /* Add/subtract (immediate, with tags) */
4222 disas_add_sub_imm_with_tags(s
, insn
);
4224 case 0x24: /* Logical (immediate) */
4225 disas_logic_imm(s
, insn
);
4227 case 0x25: /* Move wide (immediate) */
4228 disas_movw_imm(s
, insn
);
4230 case 0x26: /* Bitfield */
4231 disas_bitfield(s
, insn
);
4233 case 0x27: /* Extract */
4234 disas_extract(s
, insn
);
4237 unallocated_encoding(s
);
4242 /* Shift a TCGv src by TCGv shift_amount, put result in dst.
4243 * Note that it is the caller's responsibility to ensure that the
4244 * shift amount is in range (ie 0..31 or 0..63) and provide the ARM
4245 * mandated semantics for out of range shifts.
4247 static void shift_reg(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
4248 enum a64_shift_type shift_type
, TCGv_i64 shift_amount
)
4250 switch (shift_type
) {
4251 case A64_SHIFT_TYPE_LSL
:
4252 tcg_gen_shl_i64(dst
, src
, shift_amount
);
4254 case A64_SHIFT_TYPE_LSR
:
4255 tcg_gen_shr_i64(dst
, src
, shift_amount
);
4257 case A64_SHIFT_TYPE_ASR
:
4259 tcg_gen_ext32s_i64(dst
, src
);
4261 tcg_gen_sar_i64(dst
, sf
? src
: dst
, shift_amount
);
4263 case A64_SHIFT_TYPE_ROR
:
4265 tcg_gen_rotr_i64(dst
, src
, shift_amount
);
4268 t0
= tcg_temp_new_i32();
4269 t1
= tcg_temp_new_i32();
4270 tcg_gen_extrl_i64_i32(t0
, src
);
4271 tcg_gen_extrl_i64_i32(t1
, shift_amount
);
4272 tcg_gen_rotr_i32(t0
, t0
, t1
);
4273 tcg_gen_extu_i32_i64(dst
, t0
);
4274 tcg_temp_free_i32(t0
);
4275 tcg_temp_free_i32(t1
);
4279 assert(FALSE
); /* all shift types should be handled */
4283 if (!sf
) { /* zero extend final result */
4284 tcg_gen_ext32u_i64(dst
, dst
);
4288 /* Shift a TCGv src by immediate, put result in dst.
4289 * The shift amount must be in range (this should always be true as the
4290 * relevant instructions will UNDEF on bad shift immediates).
4292 static void shift_reg_imm(TCGv_i64 dst
, TCGv_i64 src
, int sf
,
4293 enum a64_shift_type shift_type
, unsigned int shift_i
)
4295 assert(shift_i
< (sf
? 64 : 32));
4298 tcg_gen_mov_i64(dst
, src
);
4300 TCGv_i64 shift_const
;
4302 shift_const
= tcg_const_i64(shift_i
);
4303 shift_reg(dst
, src
, sf
, shift_type
, shift_const
);
4304 tcg_temp_free_i64(shift_const
);
4308 /* Logical (shifted register)
4309 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
4310 * +----+-----+-----------+-------+---+------+--------+------+------+
4311 * | sf | opc | 0 1 0 1 0 | shift | N | Rm | imm6 | Rn | Rd |
4312 * +----+-----+-----------+-------+---+------+--------+------+------+
4314 static void disas_logic_reg(DisasContext
*s
, uint32_t insn
)
4316 TCGv_i64 tcg_rd
, tcg_rn
, tcg_rm
;
4317 unsigned int sf
, opc
, shift_type
, invert
, rm
, shift_amount
, rn
, rd
;
4319 sf
= extract32(insn
, 31, 1);
4320 opc
= extract32(insn
, 29, 2);
4321 shift_type
= extract32(insn
, 22, 2);
4322 invert
= extract32(insn
, 21, 1);
4323 rm
= extract32(insn
, 16, 5);
4324 shift_amount
= extract32(insn
, 10, 6);
4325 rn
= extract32(insn
, 5, 5);
4326 rd
= extract32(insn
, 0, 5);
4328 if (!sf
&& (shift_amount
& (1 << 5))) {
4329 unallocated_encoding(s
);
4333 tcg_rd
= cpu_reg(s
, rd
);
4335 if (opc
== 1 && shift_amount
== 0 && shift_type
== 0 && rn
== 31) {
4336 /* Unshifted ORR and ORN with WZR/XZR is the standard encoding for
4337 * register-register MOV and MVN, so it is worth special casing.
4339 tcg_rm
= cpu_reg(s
, rm
);
4341 tcg_gen_not_i64(tcg_rd
, tcg_rm
);
4343 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4347 tcg_gen_mov_i64(tcg_rd
, tcg_rm
);
4349 tcg_gen_ext32u_i64(tcg_rd
, tcg_rm
);
4355 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4358 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, shift_amount
);
4361 tcg_rn
= cpu_reg(s
, rn
);
4363 switch (opc
| (invert
<< 2)) {
4366 tcg_gen_and_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4369 tcg_gen_or_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4372 tcg_gen_xor_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4376 tcg_gen_andc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4379 tcg_gen_orc_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4382 tcg_gen_eqv_i64(tcg_rd
, tcg_rn
, tcg_rm
);
4390 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4394 gen_logic_CC(sf
, tcg_rd
);
4399 * Add/subtract (extended register)
4401 * 31|30|29|28 24|23 22|21|20 16|15 13|12 10|9 5|4 0|
4402 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
4403 * |sf|op| S| 0 1 0 1 1 | opt | 1| Rm |option| imm3 | Rn | Rd |
4404 * +--+--+--+-----------+-----+--+-------+------+------+----+----+
4406 * sf: 0 -> 32bit, 1 -> 64bit
4407 * op: 0 -> add , 1 -> sub
4410 * option: extension type (see DecodeRegExtend)
4411 * imm3: optional shift to Rm
4413 * Rd = Rn + LSL(extend(Rm), amount)
4415 static void disas_add_sub_ext_reg(DisasContext
*s
, uint32_t insn
)
4417 int rd
= extract32(insn
, 0, 5);
4418 int rn
= extract32(insn
, 5, 5);
4419 int imm3
= extract32(insn
, 10, 3);
4420 int option
= extract32(insn
, 13, 3);
4421 int rm
= extract32(insn
, 16, 5);
4422 int opt
= extract32(insn
, 22, 2);
4423 bool setflags
= extract32(insn
, 29, 1);
4424 bool sub_op
= extract32(insn
, 30, 1);
4425 bool sf
= extract32(insn
, 31, 1);
4427 TCGv_i64 tcg_rm
, tcg_rn
; /* temps */
4429 TCGv_i64 tcg_result
;
4431 if (imm3
> 4 || opt
!= 0) {
4432 unallocated_encoding(s
);
4436 /* non-flag setting ops may use SP */
4438 tcg_rd
= cpu_reg_sp(s
, rd
);
4440 tcg_rd
= cpu_reg(s
, rd
);
4442 tcg_rn
= read_cpu_reg_sp(s
, rn
, sf
);
4444 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4445 ext_and_shift_reg(tcg_rm
, tcg_rm
, option
, imm3
);
4447 tcg_result
= tcg_temp_new_i64();
4451 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
4453 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
4457 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4459 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4464 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4466 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4469 tcg_temp_free_i64(tcg_result
);
4473 * Add/subtract (shifted register)
4475 * 31 30 29 28 24 23 22 21 20 16 15 10 9 5 4 0
4476 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4477 * |sf|op| S| 0 1 0 1 1 |shift| 0| Rm | imm6 | Rn | Rd |
4478 * +--+--+--+-----------+-----+--+-------+---------+------+------+
4480 * sf: 0 -> 32bit, 1 -> 64bit
4481 * op: 0 -> add , 1 -> sub
4483 * shift: 00 -> LSL, 01 -> LSR, 10 -> ASR, 11 -> RESERVED
4484 * imm6: Shift amount to apply to Rm before the add/sub
4486 static void disas_add_sub_reg(DisasContext
*s
, uint32_t insn
)
4488 int rd
= extract32(insn
, 0, 5);
4489 int rn
= extract32(insn
, 5, 5);
4490 int imm6
= extract32(insn
, 10, 6);
4491 int rm
= extract32(insn
, 16, 5);
4492 int shift_type
= extract32(insn
, 22, 2);
4493 bool setflags
= extract32(insn
, 29, 1);
4494 bool sub_op
= extract32(insn
, 30, 1);
4495 bool sf
= extract32(insn
, 31, 1);
4497 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4498 TCGv_i64 tcg_rn
, tcg_rm
;
4499 TCGv_i64 tcg_result
;
4501 if ((shift_type
== 3) || (!sf
&& (imm6
> 31))) {
4502 unallocated_encoding(s
);
4506 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4507 tcg_rm
= read_cpu_reg(s
, rm
, sf
);
4509 shift_reg_imm(tcg_rm
, tcg_rm
, sf
, shift_type
, imm6
);
4511 tcg_result
= tcg_temp_new_i64();
4515 tcg_gen_sub_i64(tcg_result
, tcg_rn
, tcg_rm
);
4517 tcg_gen_add_i64(tcg_result
, tcg_rn
, tcg_rm
);
4521 gen_sub_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4523 gen_add_CC(sf
, tcg_result
, tcg_rn
, tcg_rm
);
4528 tcg_gen_mov_i64(tcg_rd
, tcg_result
);
4530 tcg_gen_ext32u_i64(tcg_rd
, tcg_result
);
4533 tcg_temp_free_i64(tcg_result
);
4536 /* Data-processing (3 source)
4538 * 31 30 29 28 24 23 21 20 16 15 14 10 9 5 4 0
4539 * +--+------+-----------+------+------+----+------+------+------+
4540 * |sf| op54 | 1 1 0 1 1 | op31 | Rm | o0 | Ra | Rn | Rd |
4541 * +--+------+-----------+------+------+----+------+------+------+
4543 static void disas_data_proc_3src(DisasContext
*s
, uint32_t insn
)
4545 int rd
= extract32(insn
, 0, 5);
4546 int rn
= extract32(insn
, 5, 5);
4547 int ra
= extract32(insn
, 10, 5);
4548 int rm
= extract32(insn
, 16, 5);
4549 int op_id
= (extract32(insn
, 29, 3) << 4) |
4550 (extract32(insn
, 21, 3) << 1) |
4551 extract32(insn
, 15, 1);
4552 bool sf
= extract32(insn
, 31, 1);
4553 bool is_sub
= extract32(op_id
, 0, 1);
4554 bool is_high
= extract32(op_id
, 2, 1);
4555 bool is_signed
= false;
4560 /* Note that op_id is sf:op54:op31:o0 so it includes the 32/64 size flag */
4562 case 0x42: /* SMADDL */
4563 case 0x43: /* SMSUBL */
4564 case 0x44: /* SMULH */
4567 case 0x0: /* MADD (32bit) */
4568 case 0x1: /* MSUB (32bit) */
4569 case 0x40: /* MADD (64bit) */
4570 case 0x41: /* MSUB (64bit) */
4571 case 0x4a: /* UMADDL */
4572 case 0x4b: /* UMSUBL */
4573 case 0x4c: /* UMULH */
4576 unallocated_encoding(s
);
4581 TCGv_i64 low_bits
= tcg_temp_new_i64(); /* low bits discarded */
4582 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4583 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
4584 TCGv_i64 tcg_rm
= cpu_reg(s
, rm
);
4587 tcg_gen_muls2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
4589 tcg_gen_mulu2_i64(low_bits
, tcg_rd
, tcg_rn
, tcg_rm
);
4592 tcg_temp_free_i64(low_bits
);
4596 tcg_op1
= tcg_temp_new_i64();
4597 tcg_op2
= tcg_temp_new_i64();
4598 tcg_tmp
= tcg_temp_new_i64();
4601 tcg_gen_mov_i64(tcg_op1
, cpu_reg(s
, rn
));
4602 tcg_gen_mov_i64(tcg_op2
, cpu_reg(s
, rm
));
4605 tcg_gen_ext32s_i64(tcg_op1
, cpu_reg(s
, rn
));
4606 tcg_gen_ext32s_i64(tcg_op2
, cpu_reg(s
, rm
));
4608 tcg_gen_ext32u_i64(tcg_op1
, cpu_reg(s
, rn
));
4609 tcg_gen_ext32u_i64(tcg_op2
, cpu_reg(s
, rm
));
4613 if (ra
== 31 && !is_sub
) {
4614 /* Special-case MADD with rA == XZR; it is the standard MUL alias */
4615 tcg_gen_mul_i64(cpu_reg(s
, rd
), tcg_op1
, tcg_op2
);
4617 tcg_gen_mul_i64(tcg_tmp
, tcg_op1
, tcg_op2
);
4619 tcg_gen_sub_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
4621 tcg_gen_add_i64(cpu_reg(s
, rd
), cpu_reg(s
, ra
), tcg_tmp
);
4626 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), cpu_reg(s
, rd
));
4629 tcg_temp_free_i64(tcg_op1
);
4630 tcg_temp_free_i64(tcg_op2
);
4631 tcg_temp_free_i64(tcg_tmp
);
4634 /* Add/subtract (with carry)
4635 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
4636 * +--+--+--+------------------------+------+-------------+------+-----+
4637 * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | 0 0 0 0 0 0 | Rn | Rd |
4638 * +--+--+--+------------------------+------+-------------+------+-----+
4641 static void disas_adc_sbc(DisasContext
*s
, uint32_t insn
)
4643 unsigned int sf
, op
, setflags
, rm
, rn
, rd
;
4644 TCGv_i64 tcg_y
, tcg_rn
, tcg_rd
;
4646 sf
= extract32(insn
, 31, 1);
4647 op
= extract32(insn
, 30, 1);
4648 setflags
= extract32(insn
, 29, 1);
4649 rm
= extract32(insn
, 16, 5);
4650 rn
= extract32(insn
, 5, 5);
4651 rd
= extract32(insn
, 0, 5);
4653 tcg_rd
= cpu_reg(s
, rd
);
4654 tcg_rn
= cpu_reg(s
, rn
);
4657 tcg_y
= new_tmp_a64(s
);
4658 tcg_gen_not_i64(tcg_y
, cpu_reg(s
, rm
));
4660 tcg_y
= cpu_reg(s
, rm
);
4664 gen_adc_CC(sf
, tcg_rd
, tcg_rn
, tcg_y
);
4666 gen_adc(sf
, tcg_rd
, tcg_rn
, tcg_y
);
4671 * Rotate right into flags
4672 * 31 30 29 21 15 10 5 4 0
4673 * +--+--+--+-----------------+--------+-----------+------+--+------+
4674 * |sf|op| S| 1 1 0 1 0 0 0 0 | imm6 | 0 0 0 0 1 | Rn |o2| mask |
4675 * +--+--+--+-----------------+--------+-----------+------+--+------+
4677 static void disas_rotate_right_into_flags(DisasContext
*s
, uint32_t insn
)
4679 int mask
= extract32(insn
, 0, 4);
4680 int o2
= extract32(insn
, 4, 1);
4681 int rn
= extract32(insn
, 5, 5);
4682 int imm6
= extract32(insn
, 15, 6);
4683 int sf_op_s
= extract32(insn
, 29, 3);
4687 if (sf_op_s
!= 5 || o2
!= 0 || !dc_isar_feature(aa64_condm_4
, s
)) {
4688 unallocated_encoding(s
);
4692 tcg_rn
= read_cpu_reg(s
, rn
, 1);
4693 tcg_gen_rotri_i64(tcg_rn
, tcg_rn
, imm6
);
4695 nzcv
= tcg_temp_new_i32();
4696 tcg_gen_extrl_i64_i32(nzcv
, tcg_rn
);
4698 if (mask
& 8) { /* N */
4699 tcg_gen_shli_i32(cpu_NF
, nzcv
, 31 - 3);
4701 if (mask
& 4) { /* Z */
4702 tcg_gen_not_i32(cpu_ZF
, nzcv
);
4703 tcg_gen_andi_i32(cpu_ZF
, cpu_ZF
, 4);
4705 if (mask
& 2) { /* C */
4706 tcg_gen_extract_i32(cpu_CF
, nzcv
, 1, 1);
4708 if (mask
& 1) { /* V */
4709 tcg_gen_shli_i32(cpu_VF
, nzcv
, 31 - 0);
4712 tcg_temp_free_i32(nzcv
);
4716 * Evaluate into flags
4717 * 31 30 29 21 15 14 10 5 4 0
4718 * +--+--+--+-----------------+---------+----+---------+------+--+------+
4719 * |sf|op| S| 1 1 0 1 0 0 0 0 | opcode2 | sz | 0 0 1 0 | Rn |o3| mask |
4720 * +--+--+--+-----------------+---------+----+---------+------+--+------+
4722 static void disas_evaluate_into_flags(DisasContext
*s
, uint32_t insn
)
4724 int o3_mask
= extract32(insn
, 0, 5);
4725 int rn
= extract32(insn
, 5, 5);
4726 int o2
= extract32(insn
, 15, 6);
4727 int sz
= extract32(insn
, 14, 1);
4728 int sf_op_s
= extract32(insn
, 29, 3);
4732 if (sf_op_s
!= 1 || o2
!= 0 || o3_mask
!= 0xd ||
4733 !dc_isar_feature(aa64_condm_4
, s
)) {
4734 unallocated_encoding(s
);
4737 shift
= sz
? 16 : 24; /* SETF16 or SETF8 */
4739 tmp
= tcg_temp_new_i32();
4740 tcg_gen_extrl_i64_i32(tmp
, cpu_reg(s
, rn
));
4741 tcg_gen_shli_i32(cpu_NF
, tmp
, shift
);
4742 tcg_gen_shli_i32(cpu_VF
, tmp
, shift
- 1);
4743 tcg_gen_mov_i32(cpu_ZF
, cpu_NF
);
4744 tcg_gen_xor_i32(cpu_VF
, cpu_VF
, cpu_NF
);
4745 tcg_temp_free_i32(tmp
);
4748 /* Conditional compare (immediate / register)
4749 * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
4750 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
4751 * |sf|op| S| 1 1 0 1 0 0 1 0 |imm5/rm | cond |i/r |o2| Rn |o3|nzcv |
4752 * +--+--+--+------------------------+--------+------+----+--+------+--+-----+
4755 static void disas_cc(DisasContext
*s
, uint32_t insn
)
4757 unsigned int sf
, op
, y
, cond
, rn
, nzcv
, is_imm
;
4758 TCGv_i32 tcg_t0
, tcg_t1
, tcg_t2
;
4759 TCGv_i64 tcg_tmp
, tcg_y
, tcg_rn
;
4762 if (!extract32(insn
, 29, 1)) {
4763 unallocated_encoding(s
);
4766 if (insn
& (1 << 10 | 1 << 4)) {
4767 unallocated_encoding(s
);
4770 sf
= extract32(insn
, 31, 1);
4771 op
= extract32(insn
, 30, 1);
4772 is_imm
= extract32(insn
, 11, 1);
4773 y
= extract32(insn
, 16, 5); /* y = rm (reg) or imm5 (imm) */
4774 cond
= extract32(insn
, 12, 4);
4775 rn
= extract32(insn
, 5, 5);
4776 nzcv
= extract32(insn
, 0, 4);
4778 /* Set T0 = !COND. */
4779 tcg_t0
= tcg_temp_new_i32();
4780 arm_test_cc(&c
, cond
);
4781 tcg_gen_setcondi_i32(tcg_invert_cond(c
.cond
), tcg_t0
, c
.value
, 0);
4784 /* Load the arguments for the new comparison. */
4786 tcg_y
= new_tmp_a64(s
);
4787 tcg_gen_movi_i64(tcg_y
, y
);
4789 tcg_y
= cpu_reg(s
, y
);
4791 tcg_rn
= cpu_reg(s
, rn
);
4793 /* Set the flags for the new comparison. */
4794 tcg_tmp
= tcg_temp_new_i64();
4796 gen_sub_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
4798 gen_add_CC(sf
, tcg_tmp
, tcg_rn
, tcg_y
);
4800 tcg_temp_free_i64(tcg_tmp
);
4802 /* If COND was false, force the flags to #nzcv. Compute two masks
4803 * to help with this: T1 = (COND ? 0 : -1), T2 = (COND ? -1 : 0).
4804 * For tcg hosts that support ANDC, we can make do with just T1.
4805 * In either case, allow the tcg optimizer to delete any unused mask.
4807 tcg_t1
= tcg_temp_new_i32();
4808 tcg_t2
= tcg_temp_new_i32();
4809 tcg_gen_neg_i32(tcg_t1
, tcg_t0
);
4810 tcg_gen_subi_i32(tcg_t2
, tcg_t0
, 1);
4812 if (nzcv
& 8) { /* N */
4813 tcg_gen_or_i32(cpu_NF
, cpu_NF
, tcg_t1
);
4815 if (TCG_TARGET_HAS_andc_i32
) {
4816 tcg_gen_andc_i32(cpu_NF
, cpu_NF
, tcg_t1
);
4818 tcg_gen_and_i32(cpu_NF
, cpu_NF
, tcg_t2
);
4821 if (nzcv
& 4) { /* Z */
4822 if (TCG_TARGET_HAS_andc_i32
) {
4823 tcg_gen_andc_i32(cpu_ZF
, cpu_ZF
, tcg_t1
);
4825 tcg_gen_and_i32(cpu_ZF
, cpu_ZF
, tcg_t2
);
4828 tcg_gen_or_i32(cpu_ZF
, cpu_ZF
, tcg_t0
);
4830 if (nzcv
& 2) { /* C */
4831 tcg_gen_or_i32(cpu_CF
, cpu_CF
, tcg_t0
);
4833 if (TCG_TARGET_HAS_andc_i32
) {
4834 tcg_gen_andc_i32(cpu_CF
, cpu_CF
, tcg_t1
);
4836 tcg_gen_and_i32(cpu_CF
, cpu_CF
, tcg_t2
);
4839 if (nzcv
& 1) { /* V */
4840 tcg_gen_or_i32(cpu_VF
, cpu_VF
, tcg_t1
);
4842 if (TCG_TARGET_HAS_andc_i32
) {
4843 tcg_gen_andc_i32(cpu_VF
, cpu_VF
, tcg_t1
);
4845 tcg_gen_and_i32(cpu_VF
, cpu_VF
, tcg_t2
);
4848 tcg_temp_free_i32(tcg_t0
);
4849 tcg_temp_free_i32(tcg_t1
);
4850 tcg_temp_free_i32(tcg_t2
);
4853 /* Conditional select
4854 * 31 30 29 28 21 20 16 15 12 11 10 9 5 4 0
4855 * +----+----+---+-----------------+------+------+-----+------+------+
4856 * | sf | op | S | 1 1 0 1 0 1 0 0 | Rm | cond | op2 | Rn | Rd |
4857 * +----+----+---+-----------------+------+------+-----+------+------+
4859 static void disas_cond_select(DisasContext
*s
, uint32_t insn
)
4861 unsigned int sf
, else_inv
, rm
, cond
, else_inc
, rn
, rd
;
4862 TCGv_i64 tcg_rd
, zero
;
4865 if (extract32(insn
, 29, 1) || extract32(insn
, 11, 1)) {
4866 /* S == 1 or op2<1> == 1 */
4867 unallocated_encoding(s
);
4870 sf
= extract32(insn
, 31, 1);
4871 else_inv
= extract32(insn
, 30, 1);
4872 rm
= extract32(insn
, 16, 5);
4873 cond
= extract32(insn
, 12, 4);
4874 else_inc
= extract32(insn
, 10, 1);
4875 rn
= extract32(insn
, 5, 5);
4876 rd
= extract32(insn
, 0, 5);
4878 tcg_rd
= cpu_reg(s
, rd
);
4880 a64_test_cc(&c
, cond
);
4881 zero
= tcg_const_i64(0);
4883 if (rn
== 31 && rm
== 31 && (else_inc
^ else_inv
)) {
4885 tcg_gen_setcond_i64(tcg_invert_cond(c
.cond
), tcg_rd
, c
.value
, zero
);
4887 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
4890 TCGv_i64 t_true
= cpu_reg(s
, rn
);
4891 TCGv_i64 t_false
= read_cpu_reg(s
, rm
, 1);
4892 if (else_inv
&& else_inc
) {
4893 tcg_gen_neg_i64(t_false
, t_false
);
4894 } else if (else_inv
) {
4895 tcg_gen_not_i64(t_false
, t_false
);
4896 } else if (else_inc
) {
4897 tcg_gen_addi_i64(t_false
, t_false
, 1);
4899 tcg_gen_movcond_i64(c
.cond
, tcg_rd
, c
.value
, zero
, t_true
, t_false
);
4902 tcg_temp_free_i64(zero
);
4906 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
4910 static void handle_clz(DisasContext
*s
, unsigned int sf
,
4911 unsigned int rn
, unsigned int rd
)
4913 TCGv_i64 tcg_rd
, tcg_rn
;
4914 tcg_rd
= cpu_reg(s
, rd
);
4915 tcg_rn
= cpu_reg(s
, rn
);
4918 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
4920 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4921 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4922 tcg_gen_clzi_i32(tcg_tmp32
, tcg_tmp32
, 32);
4923 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4924 tcg_temp_free_i32(tcg_tmp32
);
4928 static void handle_cls(DisasContext
*s
, unsigned int sf
,
4929 unsigned int rn
, unsigned int rd
)
4931 TCGv_i64 tcg_rd
, tcg_rn
;
4932 tcg_rd
= cpu_reg(s
, rd
);
4933 tcg_rn
= cpu_reg(s
, rn
);
4936 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
4938 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4939 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4940 tcg_gen_clrsb_i32(tcg_tmp32
, tcg_tmp32
);
4941 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4942 tcg_temp_free_i32(tcg_tmp32
);
4946 static void handle_rbit(DisasContext
*s
, unsigned int sf
,
4947 unsigned int rn
, unsigned int rd
)
4949 TCGv_i64 tcg_rd
, tcg_rn
;
4950 tcg_rd
= cpu_reg(s
, rd
);
4951 tcg_rn
= cpu_reg(s
, rn
);
4954 gen_helper_rbit64(tcg_rd
, tcg_rn
);
4956 TCGv_i32 tcg_tmp32
= tcg_temp_new_i32();
4957 tcg_gen_extrl_i64_i32(tcg_tmp32
, tcg_rn
);
4958 gen_helper_rbit(tcg_tmp32
, tcg_tmp32
);
4959 tcg_gen_extu_i32_i64(tcg_rd
, tcg_tmp32
);
4960 tcg_temp_free_i32(tcg_tmp32
);
4964 /* REV with sf==1, opcode==3 ("REV64") */
4965 static void handle_rev64(DisasContext
*s
, unsigned int sf
,
4966 unsigned int rn
, unsigned int rd
)
4969 unallocated_encoding(s
);
4972 tcg_gen_bswap64_i64(cpu_reg(s
, rd
), cpu_reg(s
, rn
));
4975 /* REV with sf==0, opcode==2
4976 * REV32 (sf==1, opcode==2)
4978 static void handle_rev32(DisasContext
*s
, unsigned int sf
,
4979 unsigned int rn
, unsigned int rd
)
4981 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
4984 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
4985 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
4987 /* bswap32_i64 requires zero high word */
4988 tcg_gen_ext32u_i64(tcg_tmp
, tcg_rn
);
4989 tcg_gen_bswap32_i64(tcg_rd
, tcg_tmp
);
4990 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 32);
4991 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
4992 tcg_gen_concat32_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
4994 tcg_temp_free_i64(tcg_tmp
);
4996 tcg_gen_ext32u_i64(tcg_rd
, cpu_reg(s
, rn
));
4997 tcg_gen_bswap32_i64(tcg_rd
, tcg_rd
);
5001 /* REV16 (opcode==1) */
5002 static void handle_rev16(DisasContext
*s
, unsigned int sf
,
5003 unsigned int rn
, unsigned int rd
)
5005 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5006 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
5007 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
5008 TCGv_i64 mask
= tcg_const_i64(sf
? 0x00ff00ff00ff00ffull
: 0x00ff00ff);
5010 tcg_gen_shri_i64(tcg_tmp
, tcg_rn
, 8);
5011 tcg_gen_and_i64(tcg_rd
, tcg_rn
, mask
);
5012 tcg_gen_and_i64(tcg_tmp
, tcg_tmp
, mask
);
5013 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, 8);
5014 tcg_gen_or_i64(tcg_rd
, tcg_rd
, tcg_tmp
);
5016 tcg_temp_free_i64(mask
);
5017 tcg_temp_free_i64(tcg_tmp
);
5020 /* Data-processing (1 source)
5021 * 31 30 29 28 21 20 16 15 10 9 5 4 0
5022 * +----+---+---+-----------------+---------+--------+------+------+
5023 * | sf | 1 | S | 1 1 0 1 0 1 1 0 | opcode2 | opcode | Rn | Rd |
5024 * +----+---+---+-----------------+---------+--------+------+------+
5026 static void disas_data_proc_1src(DisasContext
*s
, uint32_t insn
)
5028 unsigned int sf
, opcode
, opcode2
, rn
, rd
;
5031 if (extract32(insn
, 29, 1)) {
5032 unallocated_encoding(s
);
5036 sf
= extract32(insn
, 31, 1);
5037 opcode
= extract32(insn
, 10, 6);
5038 opcode2
= extract32(insn
, 16, 5);
5039 rn
= extract32(insn
, 5, 5);
5040 rd
= extract32(insn
, 0, 5);
5042 #define MAP(SF, O2, O1) ((SF) | (O1 << 1) | (O2 << 7))
5044 switch (MAP(sf
, opcode2
, opcode
)) {
5045 case MAP(0, 0x00, 0x00): /* RBIT */
5046 case MAP(1, 0x00, 0x00):
5047 handle_rbit(s
, sf
, rn
, rd
);
5049 case MAP(0, 0x00, 0x01): /* REV16 */
5050 case MAP(1, 0x00, 0x01):
5051 handle_rev16(s
, sf
, rn
, rd
);
5053 case MAP(0, 0x00, 0x02): /* REV/REV32 */
5054 case MAP(1, 0x00, 0x02):
5055 handle_rev32(s
, sf
, rn
, rd
);
5057 case MAP(1, 0x00, 0x03): /* REV64 */
5058 handle_rev64(s
, sf
, rn
, rd
);
5060 case MAP(0, 0x00, 0x04): /* CLZ */
5061 case MAP(1, 0x00, 0x04):
5062 handle_clz(s
, sf
, rn
, rd
);
5064 case MAP(0, 0x00, 0x05): /* CLS */
5065 case MAP(1, 0x00, 0x05):
5066 handle_cls(s
, sf
, rn
, rd
);
5068 case MAP(1, 0x01, 0x00): /* PACIA */
5069 if (s
->pauth_active
) {
5070 tcg_rd
= cpu_reg(s
, rd
);
5071 gen_helper_pacia(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5072 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5073 goto do_unallocated
;
5076 case MAP(1, 0x01, 0x01): /* PACIB */
5077 if (s
->pauth_active
) {
5078 tcg_rd
= cpu_reg(s
, rd
);
5079 gen_helper_pacib(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5080 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5081 goto do_unallocated
;
5084 case MAP(1, 0x01, 0x02): /* PACDA */
5085 if (s
->pauth_active
) {
5086 tcg_rd
= cpu_reg(s
, rd
);
5087 gen_helper_pacda(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5088 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5089 goto do_unallocated
;
5092 case MAP(1, 0x01, 0x03): /* PACDB */
5093 if (s
->pauth_active
) {
5094 tcg_rd
= cpu_reg(s
, rd
);
5095 gen_helper_pacdb(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5096 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5097 goto do_unallocated
;
5100 case MAP(1, 0x01, 0x04): /* AUTIA */
5101 if (s
->pauth_active
) {
5102 tcg_rd
= cpu_reg(s
, rd
);
5103 gen_helper_autia(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5104 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5105 goto do_unallocated
;
5108 case MAP(1, 0x01, 0x05): /* AUTIB */
5109 if (s
->pauth_active
) {
5110 tcg_rd
= cpu_reg(s
, rd
);
5111 gen_helper_autib(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5112 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5113 goto do_unallocated
;
5116 case MAP(1, 0x01, 0x06): /* AUTDA */
5117 if (s
->pauth_active
) {
5118 tcg_rd
= cpu_reg(s
, rd
);
5119 gen_helper_autda(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5120 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5121 goto do_unallocated
;
5124 case MAP(1, 0x01, 0x07): /* AUTDB */
5125 if (s
->pauth_active
) {
5126 tcg_rd
= cpu_reg(s
, rd
);
5127 gen_helper_autdb(tcg_rd
, cpu_env
, tcg_rd
, cpu_reg_sp(s
, rn
));
5128 } else if (!dc_isar_feature(aa64_pauth
, s
)) {
5129 goto do_unallocated
;
5132 case MAP(1, 0x01, 0x08): /* PACIZA */
5133 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5134 goto do_unallocated
;
5135 } else if (s
->pauth_active
) {
5136 tcg_rd
= cpu_reg(s
, rd
);
5137 gen_helper_pacia(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5140 case MAP(1, 0x01, 0x09): /* PACIZB */
5141 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5142 goto do_unallocated
;
5143 } else if (s
->pauth_active
) {
5144 tcg_rd
= cpu_reg(s
, rd
);
5145 gen_helper_pacib(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5148 case MAP(1, 0x01, 0x0a): /* PACDZA */
5149 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5150 goto do_unallocated
;
5151 } else if (s
->pauth_active
) {
5152 tcg_rd
= cpu_reg(s
, rd
);
5153 gen_helper_pacda(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5156 case MAP(1, 0x01, 0x0b): /* PACDZB */
5157 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5158 goto do_unallocated
;
5159 } else if (s
->pauth_active
) {
5160 tcg_rd
= cpu_reg(s
, rd
);
5161 gen_helper_pacdb(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5164 case MAP(1, 0x01, 0x0c): /* AUTIZA */
5165 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5166 goto do_unallocated
;
5167 } else if (s
->pauth_active
) {
5168 tcg_rd
= cpu_reg(s
, rd
);
5169 gen_helper_autia(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5172 case MAP(1, 0x01, 0x0d): /* AUTIZB */
5173 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5174 goto do_unallocated
;
5175 } else if (s
->pauth_active
) {
5176 tcg_rd
= cpu_reg(s
, rd
);
5177 gen_helper_autib(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5180 case MAP(1, 0x01, 0x0e): /* AUTDZA */
5181 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5182 goto do_unallocated
;
5183 } else if (s
->pauth_active
) {
5184 tcg_rd
= cpu_reg(s
, rd
);
5185 gen_helper_autda(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5188 case MAP(1, 0x01, 0x0f): /* AUTDZB */
5189 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5190 goto do_unallocated
;
5191 } else if (s
->pauth_active
) {
5192 tcg_rd
= cpu_reg(s
, rd
);
5193 gen_helper_autdb(tcg_rd
, cpu_env
, tcg_rd
, new_tmp_a64_zero(s
));
5196 case MAP(1, 0x01, 0x10): /* XPACI */
5197 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5198 goto do_unallocated
;
5199 } else if (s
->pauth_active
) {
5200 tcg_rd
= cpu_reg(s
, rd
);
5201 gen_helper_xpaci(tcg_rd
, cpu_env
, tcg_rd
);
5204 case MAP(1, 0x01, 0x11): /* XPACD */
5205 if (!dc_isar_feature(aa64_pauth
, s
) || rn
!= 31) {
5206 goto do_unallocated
;
5207 } else if (s
->pauth_active
) {
5208 tcg_rd
= cpu_reg(s
, rd
);
5209 gen_helper_xpacd(tcg_rd
, cpu_env
, tcg_rd
);
5214 unallocated_encoding(s
);
5221 static void handle_div(DisasContext
*s
, bool is_signed
, unsigned int sf
,
5222 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5224 TCGv_i64 tcg_n
, tcg_m
, tcg_rd
;
5225 tcg_rd
= cpu_reg(s
, rd
);
5227 if (!sf
&& is_signed
) {
5228 tcg_n
= new_tmp_a64(s
);
5229 tcg_m
= new_tmp_a64(s
);
5230 tcg_gen_ext32s_i64(tcg_n
, cpu_reg(s
, rn
));
5231 tcg_gen_ext32s_i64(tcg_m
, cpu_reg(s
, rm
));
5233 tcg_n
= read_cpu_reg(s
, rn
, sf
);
5234 tcg_m
= read_cpu_reg(s
, rm
, sf
);
5238 gen_helper_sdiv64(tcg_rd
, tcg_n
, tcg_m
);
5240 gen_helper_udiv64(tcg_rd
, tcg_n
, tcg_m
);
5243 if (!sf
) { /* zero extend final result */
5244 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
5248 /* LSLV, LSRV, ASRV, RORV */
5249 static void handle_shift_reg(DisasContext
*s
,
5250 enum a64_shift_type shift_type
, unsigned int sf
,
5251 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5253 TCGv_i64 tcg_shift
= tcg_temp_new_i64();
5254 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
5255 TCGv_i64 tcg_rn
= read_cpu_reg(s
, rn
, sf
);
5257 tcg_gen_andi_i64(tcg_shift
, cpu_reg(s
, rm
), sf
? 63 : 31);
5258 shift_reg(tcg_rd
, tcg_rn
, sf
, shift_type
, tcg_shift
);
5259 tcg_temp_free_i64(tcg_shift
);
5262 /* CRC32[BHWX], CRC32C[BHWX] */
5263 static void handle_crc32(DisasContext
*s
,
5264 unsigned int sf
, unsigned int sz
, bool crc32c
,
5265 unsigned int rm
, unsigned int rn
, unsigned int rd
)
5267 TCGv_i64 tcg_acc
, tcg_val
;
5270 if (!dc_isar_feature(aa64_crc32
, s
)
5271 || (sf
== 1 && sz
!= 3)
5272 || (sf
== 0 && sz
== 3)) {
5273 unallocated_encoding(s
);
5278 tcg_val
= cpu_reg(s
, rm
);
5292 g_assert_not_reached();
5294 tcg_val
= new_tmp_a64(s
);
5295 tcg_gen_andi_i64(tcg_val
, cpu_reg(s
, rm
), mask
);
5298 tcg_acc
= cpu_reg(s
, rn
);
5299 tcg_bytes
= tcg_const_i32(1 << sz
);
5302 gen_helper_crc32c_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
5304 gen_helper_crc32_64(cpu_reg(s
, rd
), tcg_acc
, tcg_val
, tcg_bytes
);
5307 tcg_temp_free_i32(tcg_bytes
);
5310 /* Data-processing (2 source)
5311 * 31 30 29 28 21 20 16 15 10 9 5 4 0
5312 * +----+---+---+-----------------+------+--------+------+------+
5313 * | sf | 0 | S | 1 1 0 1 0 1 1 0 | Rm | opcode | Rn | Rd |
5314 * +----+---+---+-----------------+------+--------+------+------+
5316 static void disas_data_proc_2src(DisasContext
*s
, uint32_t insn
)
5318 unsigned int sf
, rm
, opcode
, rn
, rd
;
5319 sf
= extract32(insn
, 31, 1);
5320 rm
= extract32(insn
, 16, 5);
5321 opcode
= extract32(insn
, 10, 6);
5322 rn
= extract32(insn
, 5, 5);
5323 rd
= extract32(insn
, 0, 5);
5325 if (extract32(insn
, 29, 1)) {
5326 unallocated_encoding(s
);
5332 handle_div(s
, false, sf
, rm
, rn
, rd
);
5335 handle_div(s
, true, sf
, rm
, rn
, rd
);
5338 if (sf
== 0 || !dc_isar_feature(aa64_mte_insn_reg
, s
)) {
5339 goto do_unallocated
;
5342 gen_helper_irg(cpu_reg_sp(s
, rd
), cpu_env
,
5343 cpu_reg_sp(s
, rn
), cpu_reg(s
, rm
));
5345 gen_address_with_allocation_tag0(cpu_reg_sp(s
, rd
),
5350 if (sf
== 0 || !dc_isar_feature(aa64_mte_insn_reg
, s
)) {
5351 goto do_unallocated
;
5353 TCGv_i64 t1
= tcg_const_i64(1);
5354 TCGv_i64 t2
= tcg_temp_new_i64();
5356 tcg_gen_extract_i64(t2
, cpu_reg_sp(s
, rn
), 56, 4);
5357 tcg_gen_shl_i64(t1
, t1
, t2
);
5358 tcg_gen_or_i64(cpu_reg(s
, rd
), cpu_reg(s
, rm
), t1
);
5360 tcg_temp_free_i64(t1
);
5361 tcg_temp_free_i64(t2
);
5365 handle_shift_reg(s
, A64_SHIFT_TYPE_LSL
, sf
, rm
, rn
, rd
);
5368 handle_shift_reg(s
, A64_SHIFT_TYPE_LSR
, sf
, rm
, rn
, rd
);
5371 handle_shift_reg(s
, A64_SHIFT_TYPE_ASR
, sf
, rm
, rn
, rd
);
5374 handle_shift_reg(s
, A64_SHIFT_TYPE_ROR
, sf
, rm
, rn
, rd
);
5376 case 12: /* PACGA */
5377 if (sf
== 0 || !dc_isar_feature(aa64_pauth
, s
)) {
5378 goto do_unallocated
;
5380 gen_helper_pacga(cpu_reg(s
, rd
), cpu_env
,
5381 cpu_reg(s
, rn
), cpu_reg_sp(s
, rm
));
5390 case 23: /* CRC32 */
5392 int sz
= extract32(opcode
, 0, 2);
5393 bool crc32c
= extract32(opcode
, 2, 1);
5394 handle_crc32(s
, sf
, sz
, crc32c
, rm
, rn
, rd
);
5399 unallocated_encoding(s
);
5405 * Data processing - register
5406 * 31 30 29 28 25 21 20 16 10 0
5407 * +--+---+--+---+-------+-----+-------+-------+---------+
5408 * | |op0| |op1| 1 0 1 | op2 | | op3 | |
5409 * +--+---+--+---+-------+-----+-------+-------+---------+
5411 static void disas_data_proc_reg(DisasContext
*s
, uint32_t insn
)
5413 int op0
= extract32(insn
, 30, 1);
5414 int op1
= extract32(insn
, 28, 1);
5415 int op2
= extract32(insn
, 21, 4);
5416 int op3
= extract32(insn
, 10, 6);
5421 /* Add/sub (extended register) */
5422 disas_add_sub_ext_reg(s
, insn
);
5424 /* Add/sub (shifted register) */
5425 disas_add_sub_reg(s
, insn
);
5428 /* Logical (shifted register) */
5429 disas_logic_reg(s
, insn
);
5437 case 0x00: /* Add/subtract (with carry) */
5438 disas_adc_sbc(s
, insn
);
5441 case 0x01: /* Rotate right into flags */
5443 disas_rotate_right_into_flags(s
, insn
);
5446 case 0x02: /* Evaluate into flags */
5450 disas_evaluate_into_flags(s
, insn
);
5454 goto do_unallocated
;
5458 case 0x2: /* Conditional compare */
5459 disas_cc(s
, insn
); /* both imm and reg forms */
5462 case 0x4: /* Conditional select */
5463 disas_cond_select(s
, insn
);
5466 case 0x6: /* Data-processing */
5467 if (op0
) { /* (1 source) */
5468 disas_data_proc_1src(s
, insn
);
5469 } else { /* (2 source) */
5470 disas_data_proc_2src(s
, insn
);
5473 case 0x8 ... 0xf: /* (3 source) */
5474 disas_data_proc_3src(s
, insn
);
5479 unallocated_encoding(s
);
5484 static void handle_fp_compare(DisasContext
*s
, int size
,
5485 unsigned int rn
, unsigned int rm
,
5486 bool cmp_with_zero
, bool signal_all_nans
)
5488 TCGv_i64 tcg_flags
= tcg_temp_new_i64();
5489 TCGv_ptr fpst
= get_fpstatus_ptr(size
== MO_16
);
5491 if (size
== MO_64
) {
5492 TCGv_i64 tcg_vn
, tcg_vm
;
5494 tcg_vn
= read_fp_dreg(s
, rn
);
5495 if (cmp_with_zero
) {
5496 tcg_vm
= tcg_const_i64(0);
5498 tcg_vm
= read_fp_dreg(s
, rm
);
5500 if (signal_all_nans
) {
5501 gen_helper_vfp_cmped_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5503 gen_helper_vfp_cmpd_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5505 tcg_temp_free_i64(tcg_vn
);
5506 tcg_temp_free_i64(tcg_vm
);
5508 TCGv_i32 tcg_vn
= tcg_temp_new_i32();
5509 TCGv_i32 tcg_vm
= tcg_temp_new_i32();
5511 read_vec_element_i32(s
, tcg_vn
, rn
, 0, size
);
5512 if (cmp_with_zero
) {
5513 tcg_gen_movi_i32(tcg_vm
, 0);
5515 read_vec_element_i32(s
, tcg_vm
, rm
, 0, size
);
5520 if (signal_all_nans
) {
5521 gen_helper_vfp_cmpes_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5523 gen_helper_vfp_cmps_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5527 if (signal_all_nans
) {
5528 gen_helper_vfp_cmpeh_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5530 gen_helper_vfp_cmph_a64(tcg_flags
, tcg_vn
, tcg_vm
, fpst
);
5534 g_assert_not_reached();
5537 tcg_temp_free_i32(tcg_vn
);
5538 tcg_temp_free_i32(tcg_vm
);
5541 tcg_temp_free_ptr(fpst
);
5543 gen_set_nzcv(tcg_flags
);
5545 tcg_temp_free_i64(tcg_flags
);
5548 /* Floating point compare
5549 * 31 30 29 28 24 23 22 21 20 16 15 14 13 10 9 5 4 0
5550 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
5551 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | op | 1 0 0 0 | Rn | op2 |
5552 * +---+---+---+-----------+------+---+------+-----+---------+------+-------+
5554 static void disas_fp_compare(DisasContext
*s
, uint32_t insn
)
5556 unsigned int mos
, type
, rm
, op
, rn
, opc
, op2r
;
5559 mos
= extract32(insn
, 29, 3);
5560 type
= extract32(insn
, 22, 2);
5561 rm
= extract32(insn
, 16, 5);
5562 op
= extract32(insn
, 14, 2);
5563 rn
= extract32(insn
, 5, 5);
5564 opc
= extract32(insn
, 3, 2);
5565 op2r
= extract32(insn
, 0, 3);
5567 if (mos
|| op
|| op2r
) {
5568 unallocated_encoding(s
);
5581 if (dc_isar_feature(aa64_fp16
, s
)) {
5586 unallocated_encoding(s
);
5590 if (!fp_access_check(s
)) {
5594 handle_fp_compare(s
, size
, rn
, rm
, opc
& 1, opc
& 2);
5597 /* Floating point conditional compare
5598 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
5599 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
5600 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 0 1 | Rn | op | nzcv |
5601 * +---+---+---+-----------+------+---+------+------+-----+------+----+------+
5603 static void disas_fp_ccomp(DisasContext
*s
, uint32_t insn
)
5605 unsigned int mos
, type
, rm
, cond
, rn
, op
, nzcv
;
5607 TCGLabel
*label_continue
= NULL
;
5610 mos
= extract32(insn
, 29, 3);
5611 type
= extract32(insn
, 22, 2);
5612 rm
= extract32(insn
, 16, 5);
5613 cond
= extract32(insn
, 12, 4);
5614 rn
= extract32(insn
, 5, 5);
5615 op
= extract32(insn
, 4, 1);
5616 nzcv
= extract32(insn
, 0, 4);
5619 unallocated_encoding(s
);
5632 if (dc_isar_feature(aa64_fp16
, s
)) {
5637 unallocated_encoding(s
);
5641 if (!fp_access_check(s
)) {
5645 if (cond
< 0x0e) { /* not always */
5646 TCGLabel
*label_match
= gen_new_label();
5647 label_continue
= gen_new_label();
5648 arm_gen_test_cc(cond
, label_match
);
5650 tcg_flags
= tcg_const_i64(nzcv
<< 28);
5651 gen_set_nzcv(tcg_flags
);
5652 tcg_temp_free_i64(tcg_flags
);
5653 tcg_gen_br(label_continue
);
5654 gen_set_label(label_match
);
5657 handle_fp_compare(s
, size
, rn
, rm
, false, op
);
5660 gen_set_label(label_continue
);
5664 /* Floating point conditional select
5665 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
5666 * +---+---+---+-----------+------+---+------+------+-----+------+------+
5667 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | cond | 1 1 | Rn | Rd |
5668 * +---+---+---+-----------+------+---+------+------+-----+------+------+
5670 static void disas_fp_csel(DisasContext
*s
, uint32_t insn
)
5672 unsigned int mos
, type
, rm
, cond
, rn
, rd
;
5673 TCGv_i64 t_true
, t_false
, t_zero
;
5677 mos
= extract32(insn
, 29, 3);
5678 type
= extract32(insn
, 22, 2);
5679 rm
= extract32(insn
, 16, 5);
5680 cond
= extract32(insn
, 12, 4);
5681 rn
= extract32(insn
, 5, 5);
5682 rd
= extract32(insn
, 0, 5);
5685 unallocated_encoding(s
);
5698 if (dc_isar_feature(aa64_fp16
, s
)) {
5703 unallocated_encoding(s
);
5707 if (!fp_access_check(s
)) {
5711 /* Zero extend sreg & hreg inputs to 64 bits now. */
5712 t_true
= tcg_temp_new_i64();
5713 t_false
= tcg_temp_new_i64();
5714 read_vec_element(s
, t_true
, rn
, 0, sz
);
5715 read_vec_element(s
, t_false
, rm
, 0, sz
);
5717 a64_test_cc(&c
, cond
);
5718 t_zero
= tcg_const_i64(0);
5719 tcg_gen_movcond_i64(c
.cond
, t_true
, c
.value
, t_zero
, t_true
, t_false
);
5720 tcg_temp_free_i64(t_zero
);
5721 tcg_temp_free_i64(t_false
);
5724 /* Note that sregs & hregs write back zeros to the high bits,
5725 and we've already done the zero-extension. */
5726 write_fp_dreg(s
, rd
, t_true
);
5727 tcg_temp_free_i64(t_true
);
5730 /* Floating-point data-processing (1 source) - half precision */
5731 static void handle_fp_1src_half(DisasContext
*s
, int opcode
, int rd
, int rn
)
5733 TCGv_ptr fpst
= NULL
;
5734 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
5735 TCGv_i32 tcg_res
= tcg_temp_new_i32();
5738 case 0x0: /* FMOV */
5739 tcg_gen_mov_i32(tcg_res
, tcg_op
);
5741 case 0x1: /* FABS */
5742 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
5744 case 0x2: /* FNEG */
5745 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
5747 case 0x3: /* FSQRT */
5748 fpst
= get_fpstatus_ptr(true);
5749 gen_helper_sqrt_f16(tcg_res
, tcg_op
, fpst
);
5751 case 0x8: /* FRINTN */
5752 case 0x9: /* FRINTP */
5753 case 0xa: /* FRINTM */
5754 case 0xb: /* FRINTZ */
5755 case 0xc: /* FRINTA */
5757 TCGv_i32 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(opcode
& 7));
5758 fpst
= get_fpstatus_ptr(true);
5760 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5761 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
5763 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5764 tcg_temp_free_i32(tcg_rmode
);
5767 case 0xe: /* FRINTX */
5768 fpst
= get_fpstatus_ptr(true);
5769 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, fpst
);
5771 case 0xf: /* FRINTI */
5772 fpst
= get_fpstatus_ptr(true);
5773 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, fpst
);
5779 write_fp_sreg(s
, rd
, tcg_res
);
5782 tcg_temp_free_ptr(fpst
);
5784 tcg_temp_free_i32(tcg_op
);
5785 tcg_temp_free_i32(tcg_res
);
5788 /* Floating-point data-processing (1 source) - single precision */
5789 static void handle_fp_1src_single(DisasContext
*s
, int opcode
, int rd
, int rn
)
5791 void (*gen_fpst
)(TCGv_i32
, TCGv_i32
, TCGv_ptr
);
5792 TCGv_i32 tcg_op
, tcg_res
;
5796 tcg_op
= read_fp_sreg(s
, rn
);
5797 tcg_res
= tcg_temp_new_i32();
5800 case 0x0: /* FMOV */
5801 tcg_gen_mov_i32(tcg_res
, tcg_op
);
5803 case 0x1: /* FABS */
5804 gen_helper_vfp_abss(tcg_res
, tcg_op
);
5806 case 0x2: /* FNEG */
5807 gen_helper_vfp_negs(tcg_res
, tcg_op
);
5809 case 0x3: /* FSQRT */
5810 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
5812 case 0x8: /* FRINTN */
5813 case 0x9: /* FRINTP */
5814 case 0xa: /* FRINTM */
5815 case 0xb: /* FRINTZ */
5816 case 0xc: /* FRINTA */
5817 rmode
= arm_rmode_to_sf(opcode
& 7);
5818 gen_fpst
= gen_helper_rints
;
5820 case 0xe: /* FRINTX */
5821 gen_fpst
= gen_helper_rints_exact
;
5823 case 0xf: /* FRINTI */
5824 gen_fpst
= gen_helper_rints
;
5826 case 0x10: /* FRINT32Z */
5827 rmode
= float_round_to_zero
;
5828 gen_fpst
= gen_helper_frint32_s
;
5830 case 0x11: /* FRINT32X */
5831 gen_fpst
= gen_helper_frint32_s
;
5833 case 0x12: /* FRINT64Z */
5834 rmode
= float_round_to_zero
;
5835 gen_fpst
= gen_helper_frint64_s
;
5837 case 0x13: /* FRINT64X */
5838 gen_fpst
= gen_helper_frint64_s
;
5841 g_assert_not_reached();
5844 fpst
= get_fpstatus_ptr(false);
5846 TCGv_i32 tcg_rmode
= tcg_const_i32(rmode
);
5847 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5848 gen_fpst(tcg_res
, tcg_op
, fpst
);
5849 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5850 tcg_temp_free_i32(tcg_rmode
);
5852 gen_fpst(tcg_res
, tcg_op
, fpst
);
5854 tcg_temp_free_ptr(fpst
);
5857 write_fp_sreg(s
, rd
, tcg_res
);
5858 tcg_temp_free_i32(tcg_op
);
5859 tcg_temp_free_i32(tcg_res
);
5862 /* Floating-point data-processing (1 source) - double precision */
5863 static void handle_fp_1src_double(DisasContext
*s
, int opcode
, int rd
, int rn
)
5865 void (*gen_fpst
)(TCGv_i64
, TCGv_i64
, TCGv_ptr
);
5866 TCGv_i64 tcg_op
, tcg_res
;
5871 case 0x0: /* FMOV */
5872 gen_gvec_fn2(s
, false, rd
, rn
, tcg_gen_gvec_mov
, 0);
5876 tcg_op
= read_fp_dreg(s
, rn
);
5877 tcg_res
= tcg_temp_new_i64();
5880 case 0x1: /* FABS */
5881 gen_helper_vfp_absd(tcg_res
, tcg_op
);
5883 case 0x2: /* FNEG */
5884 gen_helper_vfp_negd(tcg_res
, tcg_op
);
5886 case 0x3: /* FSQRT */
5887 gen_helper_vfp_sqrtd(tcg_res
, tcg_op
, cpu_env
);
5889 case 0x8: /* FRINTN */
5890 case 0x9: /* FRINTP */
5891 case 0xa: /* FRINTM */
5892 case 0xb: /* FRINTZ */
5893 case 0xc: /* FRINTA */
5894 rmode
= arm_rmode_to_sf(opcode
& 7);
5895 gen_fpst
= gen_helper_rintd
;
5897 case 0xe: /* FRINTX */
5898 gen_fpst
= gen_helper_rintd_exact
;
5900 case 0xf: /* FRINTI */
5901 gen_fpst
= gen_helper_rintd
;
5903 case 0x10: /* FRINT32Z */
5904 rmode
= float_round_to_zero
;
5905 gen_fpst
= gen_helper_frint32_d
;
5907 case 0x11: /* FRINT32X */
5908 gen_fpst
= gen_helper_frint32_d
;
5910 case 0x12: /* FRINT64Z */
5911 rmode
= float_round_to_zero
;
5912 gen_fpst
= gen_helper_frint64_d
;
5914 case 0x13: /* FRINT64X */
5915 gen_fpst
= gen_helper_frint64_d
;
5918 g_assert_not_reached();
5921 fpst
= get_fpstatus_ptr(false);
5923 TCGv_i32 tcg_rmode
= tcg_const_i32(rmode
);
5924 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5925 gen_fpst(tcg_res
, tcg_op
, fpst
);
5926 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, fpst
);
5927 tcg_temp_free_i32(tcg_rmode
);
5929 gen_fpst(tcg_res
, tcg_op
, fpst
);
5931 tcg_temp_free_ptr(fpst
);
5934 write_fp_dreg(s
, rd
, tcg_res
);
5935 tcg_temp_free_i64(tcg_op
);
5936 tcg_temp_free_i64(tcg_res
);
5939 static void handle_fp_fcvt(DisasContext
*s
, int opcode
,
5940 int rd
, int rn
, int dtype
, int ntype
)
5945 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
5947 /* Single to double */
5948 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
5949 gen_helper_vfp_fcvtds(tcg_rd
, tcg_rn
, cpu_env
);
5950 write_fp_dreg(s
, rd
, tcg_rd
);
5951 tcg_temp_free_i64(tcg_rd
);
5953 /* Single to half */
5954 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5955 TCGv_i32 ahp
= get_ahp_flag();
5956 TCGv_ptr fpst
= get_fpstatus_ptr(false);
5958 gen_helper_vfp_fcvt_f32_to_f16(tcg_rd
, tcg_rn
, fpst
, ahp
);
5959 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
5960 write_fp_sreg(s
, rd
, tcg_rd
);
5961 tcg_temp_free_i32(tcg_rd
);
5962 tcg_temp_free_i32(ahp
);
5963 tcg_temp_free_ptr(fpst
);
5965 tcg_temp_free_i32(tcg_rn
);
5970 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
5971 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5973 /* Double to single */
5974 gen_helper_vfp_fcvtsd(tcg_rd
, tcg_rn
, cpu_env
);
5976 TCGv_ptr fpst
= get_fpstatus_ptr(false);
5977 TCGv_i32 ahp
= get_ahp_flag();
5978 /* Double to half */
5979 gen_helper_vfp_fcvt_f64_to_f16(tcg_rd
, tcg_rn
, fpst
, ahp
);
5980 /* write_fp_sreg is OK here because top half of tcg_rd is zero */
5981 tcg_temp_free_ptr(fpst
);
5982 tcg_temp_free_i32(ahp
);
5984 write_fp_sreg(s
, rd
, tcg_rd
);
5985 tcg_temp_free_i32(tcg_rd
);
5986 tcg_temp_free_i64(tcg_rn
);
5991 TCGv_i32 tcg_rn
= read_fp_sreg(s
, rn
);
5992 TCGv_ptr tcg_fpst
= get_fpstatus_ptr(false);
5993 TCGv_i32 tcg_ahp
= get_ahp_flag();
5994 tcg_gen_ext16u_i32(tcg_rn
, tcg_rn
);
5996 /* Half to single */
5997 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
5998 gen_helper_vfp_fcvt_f16_to_f32(tcg_rd
, tcg_rn
, tcg_fpst
, tcg_ahp
);
5999 write_fp_sreg(s
, rd
, tcg_rd
);
6000 tcg_temp_free_i32(tcg_rd
);
6002 /* Half to double */
6003 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
6004 gen_helper_vfp_fcvt_f16_to_f64(tcg_rd
, tcg_rn
, tcg_fpst
, tcg_ahp
);
6005 write_fp_dreg(s
, rd
, tcg_rd
);
6006 tcg_temp_free_i64(tcg_rd
);
6008 tcg_temp_free_i32(tcg_rn
);
6009 tcg_temp_free_ptr(tcg_fpst
);
6010 tcg_temp_free_i32(tcg_ahp
);
6018 /* Floating point data-processing (1 source)
6019 * 31 30 29 28 24 23 22 21 20 15 14 10 9 5 4 0
6020 * +---+---+---+-----------+------+---+--------+-----------+------+------+
6021 * | M | 0 | S | 1 1 1 1 0 | type | 1 | opcode | 1 0 0 0 0 | Rn | Rd |
6022 * +---+---+---+-----------+------+---+--------+-----------+------+------+
6024 static void disas_fp_1src(DisasContext
*s
, uint32_t insn
)
6026 int mos
= extract32(insn
, 29, 3);
6027 int type
= extract32(insn
, 22, 2);
6028 int opcode
= extract32(insn
, 15, 6);
6029 int rn
= extract32(insn
, 5, 5);
6030 int rd
= extract32(insn
, 0, 5);
6033 unallocated_encoding(s
);
6038 case 0x4: case 0x5: case 0x7:
6040 /* FCVT between half, single and double precision */
6041 int dtype
= extract32(opcode
, 0, 2);
6042 if (type
== 2 || dtype
== type
) {
6043 unallocated_encoding(s
);
6046 if (!fp_access_check(s
)) {
6050 handle_fp_fcvt(s
, opcode
, rd
, rn
, dtype
, type
);
6054 case 0x10 ... 0x13: /* FRINT{32,64}{X,Z} */
6055 if (type
> 1 || !dc_isar_feature(aa64_frint
, s
)) {
6056 unallocated_encoding(s
);
6063 /* 32-to-32 and 64-to-64 ops */
6066 if (!fp_access_check(s
)) {
6069 handle_fp_1src_single(s
, opcode
, rd
, rn
);
6072 if (!fp_access_check(s
)) {
6075 handle_fp_1src_double(s
, opcode
, rd
, rn
);
6078 if (!dc_isar_feature(aa64_fp16
, s
)) {
6079 unallocated_encoding(s
);
6083 if (!fp_access_check(s
)) {
6086 handle_fp_1src_half(s
, opcode
, rd
, rn
);
6089 unallocated_encoding(s
);
6094 unallocated_encoding(s
);
6099 /* Floating-point data-processing (2 source) - single precision */
6100 static void handle_fp_2src_single(DisasContext
*s
, int opcode
,
6101 int rd
, int rn
, int rm
)
6108 tcg_res
= tcg_temp_new_i32();
6109 fpst
= get_fpstatus_ptr(false);
6110 tcg_op1
= read_fp_sreg(s
, rn
);
6111 tcg_op2
= read_fp_sreg(s
, rm
);
6114 case 0x0: /* FMUL */
6115 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6117 case 0x1: /* FDIV */
6118 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6120 case 0x2: /* FADD */
6121 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6123 case 0x3: /* FSUB */
6124 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6126 case 0x4: /* FMAX */
6127 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6129 case 0x5: /* FMIN */
6130 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6132 case 0x6: /* FMAXNM */
6133 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6135 case 0x7: /* FMINNM */
6136 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6138 case 0x8: /* FNMUL */
6139 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6140 gen_helper_vfp_negs(tcg_res
, tcg_res
);
6144 write_fp_sreg(s
, rd
, tcg_res
);
6146 tcg_temp_free_ptr(fpst
);
6147 tcg_temp_free_i32(tcg_op1
);
6148 tcg_temp_free_i32(tcg_op2
);
6149 tcg_temp_free_i32(tcg_res
);
6152 /* Floating-point data-processing (2 source) - double precision */
6153 static void handle_fp_2src_double(DisasContext
*s
, int opcode
,
6154 int rd
, int rn
, int rm
)
6161 tcg_res
= tcg_temp_new_i64();
6162 fpst
= get_fpstatus_ptr(false);
6163 tcg_op1
= read_fp_dreg(s
, rn
);
6164 tcg_op2
= read_fp_dreg(s
, rm
);
6167 case 0x0: /* FMUL */
6168 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6170 case 0x1: /* FDIV */
6171 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6173 case 0x2: /* FADD */
6174 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6176 case 0x3: /* FSUB */
6177 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6179 case 0x4: /* FMAX */
6180 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6182 case 0x5: /* FMIN */
6183 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6185 case 0x6: /* FMAXNM */
6186 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6188 case 0x7: /* FMINNM */
6189 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6191 case 0x8: /* FNMUL */
6192 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6193 gen_helper_vfp_negd(tcg_res
, tcg_res
);
6197 write_fp_dreg(s
, rd
, tcg_res
);
6199 tcg_temp_free_ptr(fpst
);
6200 tcg_temp_free_i64(tcg_op1
);
6201 tcg_temp_free_i64(tcg_op2
);
6202 tcg_temp_free_i64(tcg_res
);
6205 /* Floating-point data-processing (2 source) - half precision */
6206 static void handle_fp_2src_half(DisasContext
*s
, int opcode
,
6207 int rd
, int rn
, int rm
)
6214 tcg_res
= tcg_temp_new_i32();
6215 fpst
= get_fpstatus_ptr(true);
6216 tcg_op1
= read_fp_hreg(s
, rn
);
6217 tcg_op2
= read_fp_hreg(s
, rm
);
6220 case 0x0: /* FMUL */
6221 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6223 case 0x1: /* FDIV */
6224 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6226 case 0x2: /* FADD */
6227 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6229 case 0x3: /* FSUB */
6230 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6232 case 0x4: /* FMAX */
6233 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6235 case 0x5: /* FMIN */
6236 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6238 case 0x6: /* FMAXNM */
6239 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6241 case 0x7: /* FMINNM */
6242 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6244 case 0x8: /* FNMUL */
6245 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
6246 tcg_gen_xori_i32(tcg_res
, tcg_res
, 0x8000);
6249 g_assert_not_reached();
6252 write_fp_sreg(s
, rd
, tcg_res
);
6254 tcg_temp_free_ptr(fpst
);
6255 tcg_temp_free_i32(tcg_op1
);
6256 tcg_temp_free_i32(tcg_op2
);
6257 tcg_temp_free_i32(tcg_res
);
6260 /* Floating point data-processing (2 source)
6261 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
6262 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
6263 * | M | 0 | S | 1 1 1 1 0 | type | 1 | Rm | opcode | 1 0 | Rn | Rd |
6264 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
6266 static void disas_fp_2src(DisasContext
*s
, uint32_t insn
)
6268 int mos
= extract32(insn
, 29, 3);
6269 int type
= extract32(insn
, 22, 2);
6270 int rd
= extract32(insn
, 0, 5);
6271 int rn
= extract32(insn
, 5, 5);
6272 int rm
= extract32(insn
, 16, 5);
6273 int opcode
= extract32(insn
, 12, 4);
6275 if (opcode
> 8 || mos
) {
6276 unallocated_encoding(s
);
6282 if (!fp_access_check(s
)) {
6285 handle_fp_2src_single(s
, opcode
, rd
, rn
, rm
);
6288 if (!fp_access_check(s
)) {
6291 handle_fp_2src_double(s
, opcode
, rd
, rn
, rm
);
6294 if (!dc_isar_feature(aa64_fp16
, s
)) {
6295 unallocated_encoding(s
);
6298 if (!fp_access_check(s
)) {
6301 handle_fp_2src_half(s
, opcode
, rd
, rn
, rm
);
6304 unallocated_encoding(s
);
6308 /* Floating-point data-processing (3 source) - single precision */
6309 static void handle_fp_3src_single(DisasContext
*s
, bool o0
, bool o1
,
6310 int rd
, int rn
, int rm
, int ra
)
6312 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
6313 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6314 TCGv_ptr fpst
= get_fpstatus_ptr(false);
6316 tcg_op1
= read_fp_sreg(s
, rn
);
6317 tcg_op2
= read_fp_sreg(s
, rm
);
6318 tcg_op3
= read_fp_sreg(s
, ra
);
6320 /* These are fused multiply-add, and must be done as one
6321 * floating point operation with no rounding between the
6322 * multiplication and addition steps.
6323 * NB that doing the negations here as separate steps is
6324 * correct : an input NaN should come out with its sign bit
6325 * flipped if it is a negated-input.
6328 gen_helper_vfp_negs(tcg_op3
, tcg_op3
);
6332 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
6335 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6337 write_fp_sreg(s
, rd
, tcg_res
);
6339 tcg_temp_free_ptr(fpst
);
6340 tcg_temp_free_i32(tcg_op1
);
6341 tcg_temp_free_i32(tcg_op2
);
6342 tcg_temp_free_i32(tcg_op3
);
6343 tcg_temp_free_i32(tcg_res
);
6346 /* Floating-point data-processing (3 source) - double precision */
6347 static void handle_fp_3src_double(DisasContext
*s
, bool o0
, bool o1
,
6348 int rd
, int rn
, int rm
, int ra
)
6350 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
;
6351 TCGv_i64 tcg_res
= tcg_temp_new_i64();
6352 TCGv_ptr fpst
= get_fpstatus_ptr(false);
6354 tcg_op1
= read_fp_dreg(s
, rn
);
6355 tcg_op2
= read_fp_dreg(s
, rm
);
6356 tcg_op3
= read_fp_dreg(s
, ra
);
6358 /* These are fused multiply-add, and must be done as one
6359 * floating point operation with no rounding between the
6360 * multiplication and addition steps.
6361 * NB that doing the negations here as separate steps is
6362 * correct : an input NaN should come out with its sign bit
6363 * flipped if it is a negated-input.
6366 gen_helper_vfp_negd(tcg_op3
, tcg_op3
);
6370 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
6373 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6375 write_fp_dreg(s
, rd
, tcg_res
);
6377 tcg_temp_free_ptr(fpst
);
6378 tcg_temp_free_i64(tcg_op1
);
6379 tcg_temp_free_i64(tcg_op2
);
6380 tcg_temp_free_i64(tcg_op3
);
6381 tcg_temp_free_i64(tcg_res
);
6384 /* Floating-point data-processing (3 source) - half precision */
6385 static void handle_fp_3src_half(DisasContext
*s
, bool o0
, bool o1
,
6386 int rd
, int rn
, int rm
, int ra
)
6388 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
;
6389 TCGv_i32 tcg_res
= tcg_temp_new_i32();
6390 TCGv_ptr fpst
= get_fpstatus_ptr(true);
6392 tcg_op1
= read_fp_hreg(s
, rn
);
6393 tcg_op2
= read_fp_hreg(s
, rm
);
6394 tcg_op3
= read_fp_hreg(s
, ra
);
6396 /* These are fused multiply-add, and must be done as one
6397 * floating point operation with no rounding between the
6398 * multiplication and addition steps.
6399 * NB that doing the negations here as separate steps is
6400 * correct : an input NaN should come out with its sign bit
6401 * flipped if it is a negated-input.
6404 tcg_gen_xori_i32(tcg_op3
, tcg_op3
, 0x8000);
6408 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
6411 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_op3
, fpst
);
6413 write_fp_sreg(s
, rd
, tcg_res
);
6415 tcg_temp_free_ptr(fpst
);
6416 tcg_temp_free_i32(tcg_op1
);
6417 tcg_temp_free_i32(tcg_op2
);
6418 tcg_temp_free_i32(tcg_op3
);
6419 tcg_temp_free_i32(tcg_res
);
6422 /* Floating point data-processing (3 source)
6423 * 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
6424 * +---+---+---+-----------+------+----+------+----+------+------+------+
6425 * | M | 0 | S | 1 1 1 1 1 | type | o1 | Rm | o0 | Ra | Rn | Rd |
6426 * +---+---+---+-----------+------+----+------+----+------+------+------+
6428 static void disas_fp_3src(DisasContext
*s
, uint32_t insn
)
6430 int mos
= extract32(insn
, 29, 3);
6431 int type
= extract32(insn
, 22, 2);
6432 int rd
= extract32(insn
, 0, 5);
6433 int rn
= extract32(insn
, 5, 5);
6434 int ra
= extract32(insn
, 10, 5);
6435 int rm
= extract32(insn
, 16, 5);
6436 bool o0
= extract32(insn
, 15, 1);
6437 bool o1
= extract32(insn
, 21, 1);
6440 unallocated_encoding(s
);
6446 if (!fp_access_check(s
)) {
6449 handle_fp_3src_single(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6452 if (!fp_access_check(s
)) {
6455 handle_fp_3src_double(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6458 if (!dc_isar_feature(aa64_fp16
, s
)) {
6459 unallocated_encoding(s
);
6462 if (!fp_access_check(s
)) {
6465 handle_fp_3src_half(s
, o0
, o1
, rd
, rn
, rm
, ra
);
6468 unallocated_encoding(s
);
6472 /* Floating point immediate
6473 * 31 30 29 28 24 23 22 21 20 13 12 10 9 5 4 0
6474 * +---+---+---+-----------+------+---+------------+-------+------+------+
6475 * | M | 0 | S | 1 1 1 1 0 | type | 1 | imm8 | 1 0 0 | imm5 | Rd |
6476 * +---+---+---+-----------+------+---+------------+-------+------+------+
6478 static void disas_fp_imm(DisasContext
*s
, uint32_t insn
)
6480 int rd
= extract32(insn
, 0, 5);
6481 int imm5
= extract32(insn
, 5, 5);
6482 int imm8
= extract32(insn
, 13, 8);
6483 int type
= extract32(insn
, 22, 2);
6484 int mos
= extract32(insn
, 29, 3);
6490 unallocated_encoding(s
);
6503 if (dc_isar_feature(aa64_fp16
, s
)) {
6508 unallocated_encoding(s
);
6512 if (!fp_access_check(s
)) {
6516 imm
= vfp_expand_imm(sz
, imm8
);
6518 tcg_res
= tcg_const_i64(imm
);
6519 write_fp_dreg(s
, rd
, tcg_res
);
6520 tcg_temp_free_i64(tcg_res
);
6523 /* Handle floating point <=> fixed point conversions. Note that we can
6524 * also deal with fp <=> integer conversions as a special case (scale == 64)
6525 * OPTME: consider handling that special case specially or at least skipping
6526 * the call to scalbn in the helpers for zero shifts.
6528 static void handle_fpfpcvt(DisasContext
*s
, int rd
, int rn
, int opcode
,
6529 bool itof
, int rmode
, int scale
, int sf
, int type
)
6531 bool is_signed
= !(opcode
& 1);
6532 TCGv_ptr tcg_fpstatus
;
6533 TCGv_i32 tcg_shift
, tcg_single
;
6534 TCGv_i64 tcg_double
;
6536 tcg_fpstatus
= get_fpstatus_ptr(type
== 3);
6538 tcg_shift
= tcg_const_i32(64 - scale
);
6541 TCGv_i64 tcg_int
= cpu_reg(s
, rn
);
6543 TCGv_i64 tcg_extend
= new_tmp_a64(s
);
6546 tcg_gen_ext32s_i64(tcg_extend
, tcg_int
);
6548 tcg_gen_ext32u_i64(tcg_extend
, tcg_int
);
6551 tcg_int
= tcg_extend
;
6555 case 1: /* float64 */
6556 tcg_double
= tcg_temp_new_i64();
6558 gen_helper_vfp_sqtod(tcg_double
, tcg_int
,
6559 tcg_shift
, tcg_fpstatus
);
6561 gen_helper_vfp_uqtod(tcg_double
, tcg_int
,
6562 tcg_shift
, tcg_fpstatus
);
6564 write_fp_dreg(s
, rd
, tcg_double
);
6565 tcg_temp_free_i64(tcg_double
);
6568 case 0: /* float32 */
6569 tcg_single
= tcg_temp_new_i32();
6571 gen_helper_vfp_sqtos(tcg_single
, tcg_int
,
6572 tcg_shift
, tcg_fpstatus
);
6574 gen_helper_vfp_uqtos(tcg_single
, tcg_int
,
6575 tcg_shift
, tcg_fpstatus
);
6577 write_fp_sreg(s
, rd
, tcg_single
);
6578 tcg_temp_free_i32(tcg_single
);
6581 case 3: /* float16 */
6582 tcg_single
= tcg_temp_new_i32();
6584 gen_helper_vfp_sqtoh(tcg_single
, tcg_int
,
6585 tcg_shift
, tcg_fpstatus
);
6587 gen_helper_vfp_uqtoh(tcg_single
, tcg_int
,
6588 tcg_shift
, tcg_fpstatus
);
6590 write_fp_sreg(s
, rd
, tcg_single
);
6591 tcg_temp_free_i32(tcg_single
);
6595 g_assert_not_reached();
6598 TCGv_i64 tcg_int
= cpu_reg(s
, rd
);
6601 if (extract32(opcode
, 2, 1)) {
6602 /* There are too many rounding modes to all fit into rmode,
6603 * so FCVTA[US] is a special case.
6605 rmode
= FPROUNDING_TIEAWAY
;
6608 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
6610 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
6613 case 1: /* float64 */
6614 tcg_double
= read_fp_dreg(s
, rn
);
6617 gen_helper_vfp_tosld(tcg_int
, tcg_double
,
6618 tcg_shift
, tcg_fpstatus
);
6620 gen_helper_vfp_tosqd(tcg_int
, tcg_double
,
6621 tcg_shift
, tcg_fpstatus
);
6625 gen_helper_vfp_tould(tcg_int
, tcg_double
,
6626 tcg_shift
, tcg_fpstatus
);
6628 gen_helper_vfp_touqd(tcg_int
, tcg_double
,
6629 tcg_shift
, tcg_fpstatus
);
6633 tcg_gen_ext32u_i64(tcg_int
, tcg_int
);
6635 tcg_temp_free_i64(tcg_double
);
6638 case 0: /* float32 */
6639 tcg_single
= read_fp_sreg(s
, rn
);
6642 gen_helper_vfp_tosqs(tcg_int
, tcg_single
,
6643 tcg_shift
, tcg_fpstatus
);
6645 gen_helper_vfp_touqs(tcg_int
, tcg_single
,
6646 tcg_shift
, tcg_fpstatus
);
6649 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
6651 gen_helper_vfp_tosls(tcg_dest
, tcg_single
,
6652 tcg_shift
, tcg_fpstatus
);
6654 gen_helper_vfp_touls(tcg_dest
, tcg_single
,
6655 tcg_shift
, tcg_fpstatus
);
6657 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
6658 tcg_temp_free_i32(tcg_dest
);
6660 tcg_temp_free_i32(tcg_single
);
6663 case 3: /* float16 */
6664 tcg_single
= read_fp_sreg(s
, rn
);
6667 gen_helper_vfp_tosqh(tcg_int
, tcg_single
,
6668 tcg_shift
, tcg_fpstatus
);
6670 gen_helper_vfp_touqh(tcg_int
, tcg_single
,
6671 tcg_shift
, tcg_fpstatus
);
6674 TCGv_i32 tcg_dest
= tcg_temp_new_i32();
6676 gen_helper_vfp_toslh(tcg_dest
, tcg_single
,
6677 tcg_shift
, tcg_fpstatus
);
6679 gen_helper_vfp_toulh(tcg_dest
, tcg_single
,
6680 tcg_shift
, tcg_fpstatus
);
6682 tcg_gen_extu_i32_i64(tcg_int
, tcg_dest
);
6683 tcg_temp_free_i32(tcg_dest
);
6685 tcg_temp_free_i32(tcg_single
);
6689 g_assert_not_reached();
6692 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
6693 tcg_temp_free_i32(tcg_rmode
);
6696 tcg_temp_free_ptr(tcg_fpstatus
);
6697 tcg_temp_free_i32(tcg_shift
);
6700 /* Floating point <-> fixed point conversions
6701 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
6702 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
6703 * | sf | 0 | S | 1 1 1 1 0 | type | 0 | rmode | opcode | scale | Rn | Rd |
6704 * +----+---+---+-----------+------+---+-------+--------+-------+------+------+
6706 static void disas_fp_fixed_conv(DisasContext
*s
, uint32_t insn
)
6708 int rd
= extract32(insn
, 0, 5);
6709 int rn
= extract32(insn
, 5, 5);
6710 int scale
= extract32(insn
, 10, 6);
6711 int opcode
= extract32(insn
, 16, 3);
6712 int rmode
= extract32(insn
, 19, 2);
6713 int type
= extract32(insn
, 22, 2);
6714 bool sbit
= extract32(insn
, 29, 1);
6715 bool sf
= extract32(insn
, 31, 1);
6718 if (sbit
|| (!sf
&& scale
< 32)) {
6719 unallocated_encoding(s
);
6724 case 0: /* float32 */
6725 case 1: /* float64 */
6727 case 3: /* float16 */
6728 if (dc_isar_feature(aa64_fp16
, s
)) {
6733 unallocated_encoding(s
);
6737 switch ((rmode
<< 3) | opcode
) {
6738 case 0x2: /* SCVTF */
6739 case 0x3: /* UCVTF */
6742 case 0x18: /* FCVTZS */
6743 case 0x19: /* FCVTZU */
6747 unallocated_encoding(s
);
6751 if (!fp_access_check(s
)) {
6755 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, FPROUNDING_ZERO
, scale
, sf
, type
);
6758 static void handle_fmov(DisasContext
*s
, int rd
, int rn
, int type
, bool itof
)
6760 /* FMOV: gpr to or from float, double, or top half of quad fp reg,
6761 * without conversion.
6765 TCGv_i64 tcg_rn
= cpu_reg(s
, rn
);
6771 tmp
= tcg_temp_new_i64();
6772 tcg_gen_ext32u_i64(tmp
, tcg_rn
);
6773 write_fp_dreg(s
, rd
, tmp
);
6774 tcg_temp_free_i64(tmp
);
6778 write_fp_dreg(s
, rd
, tcg_rn
);
6781 /* 64 bit to top half. */
6782 tcg_gen_st_i64(tcg_rn
, cpu_env
, fp_reg_hi_offset(s
, rd
));
6783 clear_vec_high(s
, true, rd
);
6787 tmp
= tcg_temp_new_i64();
6788 tcg_gen_ext16u_i64(tmp
, tcg_rn
);
6789 write_fp_dreg(s
, rd
, tmp
);
6790 tcg_temp_free_i64(tmp
);
6793 g_assert_not_reached();
6796 TCGv_i64 tcg_rd
= cpu_reg(s
, rd
);
6801 tcg_gen_ld32u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_32
));
6805 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_64
));
6808 /* 64 bits from top half */
6809 tcg_gen_ld_i64(tcg_rd
, cpu_env
, fp_reg_hi_offset(s
, rn
));
6813 tcg_gen_ld16u_i64(tcg_rd
, cpu_env
, fp_reg_offset(s
, rn
, MO_16
));
6816 g_assert_not_reached();
6821 static void handle_fjcvtzs(DisasContext
*s
, int rd
, int rn
)
6823 TCGv_i64 t
= read_fp_dreg(s
, rn
);
6824 TCGv_ptr fpstatus
= get_fpstatus_ptr(false);
6826 gen_helper_fjcvtzs(t
, t
, fpstatus
);
6828 tcg_temp_free_ptr(fpstatus
);
6830 tcg_gen_ext32u_i64(cpu_reg(s
, rd
), t
);
6831 tcg_gen_extrh_i64_i32(cpu_ZF
, t
);
6832 tcg_gen_movi_i32(cpu_CF
, 0);
6833 tcg_gen_movi_i32(cpu_NF
, 0);
6834 tcg_gen_movi_i32(cpu_VF
, 0);
6836 tcg_temp_free_i64(t
);
6839 /* Floating point <-> integer conversions
6840 * 31 30 29 28 24 23 22 21 20 19 18 16 15 10 9 5 4 0
6841 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
6842 * | sf | 0 | S | 1 1 1 1 0 | type | 1 | rmode | opc | 0 0 0 0 0 0 | Rn | Rd |
6843 * +----+---+---+-----------+------+---+-------+-----+-------------+----+----+
6845 static void disas_fp_int_conv(DisasContext
*s
, uint32_t insn
)
6847 int rd
= extract32(insn
, 0, 5);
6848 int rn
= extract32(insn
, 5, 5);
6849 int opcode
= extract32(insn
, 16, 3);
6850 int rmode
= extract32(insn
, 19, 2);
6851 int type
= extract32(insn
, 22, 2);
6852 bool sbit
= extract32(insn
, 29, 1);
6853 bool sf
= extract32(insn
, 31, 1);
6857 goto do_unallocated
;
6865 case 4: /* FCVTAS */
6866 case 5: /* FCVTAU */
6868 goto do_unallocated
;
6871 case 0: /* FCVT[NPMZ]S */
6872 case 1: /* FCVT[NPMZ]U */
6874 case 0: /* float32 */
6875 case 1: /* float64 */
6877 case 3: /* float16 */
6878 if (!dc_isar_feature(aa64_fp16
, s
)) {
6879 goto do_unallocated
;
6883 goto do_unallocated
;
6885 if (!fp_access_check(s
)) {
6888 handle_fpfpcvt(s
, rd
, rn
, opcode
, itof
, rmode
, 64, sf
, type
);
6892 switch (sf
<< 7 | type
<< 5 | rmode
<< 3 | opcode
) {
6893 case 0b01100110: /* FMOV half <-> 32-bit int */
6895 case 0b11100110: /* FMOV half <-> 64-bit int */
6897 if (!dc_isar_feature(aa64_fp16
, s
)) {
6898 goto do_unallocated
;
6901 case 0b00000110: /* FMOV 32-bit */
6903 case 0b10100110: /* FMOV 64-bit */
6905 case 0b11001110: /* FMOV top half of 128-bit */
6907 if (!fp_access_check(s
)) {
6911 handle_fmov(s
, rd
, rn
, type
, itof
);
6914 case 0b00111110: /* FJCVTZS */
6915 if (!dc_isar_feature(aa64_jscvt
, s
)) {
6916 goto do_unallocated
;
6917 } else if (fp_access_check(s
)) {
6918 handle_fjcvtzs(s
, rd
, rn
);
6924 unallocated_encoding(s
);
6931 /* FP-specific subcases of table C3-6 (SIMD and FP data processing)
6932 * 31 30 29 28 25 24 0
6933 * +---+---+---+---------+-----------------------------+
6934 * | | 0 | | 1 1 1 1 | |
6935 * +---+---+---+---------+-----------------------------+
6937 static void disas_data_proc_fp(DisasContext
*s
, uint32_t insn
)
6939 if (extract32(insn
, 24, 1)) {
6940 /* Floating point data-processing (3 source) */
6941 disas_fp_3src(s
, insn
);
6942 } else if (extract32(insn
, 21, 1) == 0) {
6943 /* Floating point to fixed point conversions */
6944 disas_fp_fixed_conv(s
, insn
);
6946 switch (extract32(insn
, 10, 2)) {
6948 /* Floating point conditional compare */
6949 disas_fp_ccomp(s
, insn
);
6952 /* Floating point data-processing (2 source) */
6953 disas_fp_2src(s
, insn
);
6956 /* Floating point conditional select */
6957 disas_fp_csel(s
, insn
);
6960 switch (ctz32(extract32(insn
, 12, 4))) {
6961 case 0: /* [15:12] == xxx1 */
6962 /* Floating point immediate */
6963 disas_fp_imm(s
, insn
);
6965 case 1: /* [15:12] == xx10 */
6966 /* Floating point compare */
6967 disas_fp_compare(s
, insn
);
6969 case 2: /* [15:12] == x100 */
6970 /* Floating point data-processing (1 source) */
6971 disas_fp_1src(s
, insn
);
6973 case 3: /* [15:12] == 1000 */
6974 unallocated_encoding(s
);
6976 default: /* [15:12] == 0000 */
6977 /* Floating point <-> integer conversions */
6978 disas_fp_int_conv(s
, insn
);
6986 static void do_ext64(DisasContext
*s
, TCGv_i64 tcg_left
, TCGv_i64 tcg_right
,
6989 /* Extract 64 bits from the middle of two concatenated 64 bit
6990 * vector register slices left:right. The extracted bits start
6991 * at 'pos' bits into the right (least significant) side.
6992 * We return the result in tcg_right, and guarantee not to
6995 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
6996 assert(pos
> 0 && pos
< 64);
6998 tcg_gen_shri_i64(tcg_right
, tcg_right
, pos
);
6999 tcg_gen_shli_i64(tcg_tmp
, tcg_left
, 64 - pos
);
7000 tcg_gen_or_i64(tcg_right
, tcg_right
, tcg_tmp
);
7002 tcg_temp_free_i64(tcg_tmp
);
7006 * 31 30 29 24 23 22 21 20 16 15 14 11 10 9 5 4 0
7007 * +---+---+-------------+-----+---+------+---+------+---+------+------+
7008 * | 0 | Q | 1 0 1 1 1 0 | op2 | 0 | Rm | 0 | imm4 | 0 | Rn | Rd |
7009 * +---+---+-------------+-----+---+------+---+------+---+------+------+
7011 static void disas_simd_ext(DisasContext
*s
, uint32_t insn
)
7013 int is_q
= extract32(insn
, 30, 1);
7014 int op2
= extract32(insn
, 22, 2);
7015 int imm4
= extract32(insn
, 11, 4);
7016 int rm
= extract32(insn
, 16, 5);
7017 int rn
= extract32(insn
, 5, 5);
7018 int rd
= extract32(insn
, 0, 5);
7019 int pos
= imm4
<< 3;
7020 TCGv_i64 tcg_resl
, tcg_resh
;
7022 if (op2
!= 0 || (!is_q
&& extract32(imm4
, 3, 1))) {
7023 unallocated_encoding(s
);
7027 if (!fp_access_check(s
)) {
7031 tcg_resh
= tcg_temp_new_i64();
7032 tcg_resl
= tcg_temp_new_i64();
7034 /* Vd gets bits starting at pos bits into Vm:Vn. This is
7035 * either extracting 128 bits from a 128:128 concatenation, or
7036 * extracting 64 bits from a 64:64 concatenation.
7039 read_vec_element(s
, tcg_resl
, rn
, 0, MO_64
);
7041 read_vec_element(s
, tcg_resh
, rm
, 0, MO_64
);
7042 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
7050 EltPosns eltposns
[] = { {rn
, 0}, {rn
, 1}, {rm
, 0}, {rm
, 1} };
7051 EltPosns
*elt
= eltposns
;
7058 read_vec_element(s
, tcg_resl
, elt
->reg
, elt
->elt
, MO_64
);
7060 read_vec_element(s
, tcg_resh
, elt
->reg
, elt
->elt
, MO_64
);
7063 do_ext64(s
, tcg_resh
, tcg_resl
, pos
);
7064 tcg_hh
= tcg_temp_new_i64();
7065 read_vec_element(s
, tcg_hh
, elt
->reg
, elt
->elt
, MO_64
);
7066 do_ext64(s
, tcg_hh
, tcg_resh
, pos
);
7067 tcg_temp_free_i64(tcg_hh
);
7071 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
7072 tcg_temp_free_i64(tcg_resl
);
7074 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
7076 tcg_temp_free_i64(tcg_resh
);
7077 clear_vec_high(s
, is_q
, rd
);
7081 * 31 30 29 24 23 22 21 20 16 15 14 13 12 11 10 9 5 4 0
7082 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
7083 * | 0 | Q | 0 0 1 1 1 0 | op2 | 0 | Rm | 0 | len | op | 0 0 | Rn | Rd |
7084 * +---+---+-------------+-----+---+------+---+-----+----+-----+------+------+
7086 static void disas_simd_tb(DisasContext
*s
, uint32_t insn
)
7088 int op2
= extract32(insn
, 22, 2);
7089 int is_q
= extract32(insn
, 30, 1);
7090 int rm
= extract32(insn
, 16, 5);
7091 int rn
= extract32(insn
, 5, 5);
7092 int rd
= extract32(insn
, 0, 5);
7093 int is_tblx
= extract32(insn
, 12, 1);
7094 int len
= extract32(insn
, 13, 2);
7095 TCGv_i64 tcg_resl
, tcg_resh
, tcg_idx
;
7096 TCGv_i32 tcg_regno
, tcg_numregs
;
7099 unallocated_encoding(s
);
7103 if (!fp_access_check(s
)) {
7107 /* This does a table lookup: for every byte element in the input
7108 * we index into a table formed from up to four vector registers,
7109 * and then the output is the result of the lookups. Our helper
7110 * function does the lookup operation for a single 64 bit part of
7113 tcg_resl
= tcg_temp_new_i64();
7117 read_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
7119 tcg_gen_movi_i64(tcg_resl
, 0);
7123 tcg_resh
= tcg_temp_new_i64();
7125 read_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
7127 tcg_gen_movi_i64(tcg_resh
, 0);
7131 tcg_idx
= tcg_temp_new_i64();
7132 tcg_regno
= tcg_const_i32(rn
);
7133 tcg_numregs
= tcg_const_i32(len
+ 1);
7134 read_vec_element(s
, tcg_idx
, rm
, 0, MO_64
);
7135 gen_helper_simd_tbl(tcg_resl
, cpu_env
, tcg_resl
, tcg_idx
,
7136 tcg_regno
, tcg_numregs
);
7138 read_vec_element(s
, tcg_idx
, rm
, 1, MO_64
);
7139 gen_helper_simd_tbl(tcg_resh
, cpu_env
, tcg_resh
, tcg_idx
,
7140 tcg_regno
, tcg_numregs
);
7142 tcg_temp_free_i64(tcg_idx
);
7143 tcg_temp_free_i32(tcg_regno
);
7144 tcg_temp_free_i32(tcg_numregs
);
7146 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
7147 tcg_temp_free_i64(tcg_resl
);
7150 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
7151 tcg_temp_free_i64(tcg_resh
);
7153 clear_vec_high(s
, is_q
, rd
);
7157 * 31 30 29 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
7158 * +---+---+-------------+------+---+------+---+------------------+------+
7159 * | 0 | Q | 0 0 1 1 1 0 | size | 0 | Rm | 0 | opc | 1 0 | Rn | Rd |
7160 * +---+---+-------------+------+---+------+---+------------------+------+
7162 static void disas_simd_zip_trn(DisasContext
*s
, uint32_t insn
)
7164 int rd
= extract32(insn
, 0, 5);
7165 int rn
= extract32(insn
, 5, 5);
7166 int rm
= extract32(insn
, 16, 5);
7167 int size
= extract32(insn
, 22, 2);
7168 /* opc field bits [1:0] indicate ZIP/UZP/TRN;
7169 * bit 2 indicates 1 vs 2 variant of the insn.
7171 int opcode
= extract32(insn
, 12, 2);
7172 bool part
= extract32(insn
, 14, 1);
7173 bool is_q
= extract32(insn
, 30, 1);
7174 int esize
= 8 << size
;
7176 int datasize
= is_q
? 128 : 64;
7177 int elements
= datasize
/ esize
;
7178 TCGv_i64 tcg_res
, tcg_resl
, tcg_resh
;
7180 if (opcode
== 0 || (size
== 3 && !is_q
)) {
7181 unallocated_encoding(s
);
7185 if (!fp_access_check(s
)) {
7189 tcg_resl
= tcg_const_i64(0);
7190 tcg_resh
= is_q
? tcg_const_i64(0) : NULL
;
7191 tcg_res
= tcg_temp_new_i64();
7193 for (i
= 0; i
< elements
; i
++) {
7195 case 1: /* UZP1/2 */
7197 int midpoint
= elements
/ 2;
7199 read_vec_element(s
, tcg_res
, rn
, 2 * i
+ part
, size
);
7201 read_vec_element(s
, tcg_res
, rm
,
7202 2 * (i
- midpoint
) + part
, size
);
7206 case 2: /* TRN1/2 */
7208 read_vec_element(s
, tcg_res
, rm
, (i
& ~1) + part
, size
);
7210 read_vec_element(s
, tcg_res
, rn
, (i
& ~1) + part
, size
);
7213 case 3: /* ZIP1/2 */
7215 int base
= part
* elements
/ 2;
7217 read_vec_element(s
, tcg_res
, rm
, base
+ (i
>> 1), size
);
7219 read_vec_element(s
, tcg_res
, rn
, base
+ (i
>> 1), size
);
7224 g_assert_not_reached();
7229 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
);
7230 tcg_gen_or_i64(tcg_resl
, tcg_resl
, tcg_res
);
7232 tcg_gen_shli_i64(tcg_res
, tcg_res
, ofs
- 64);
7233 tcg_gen_or_i64(tcg_resh
, tcg_resh
, tcg_res
);
7237 tcg_temp_free_i64(tcg_res
);
7239 write_vec_element(s
, tcg_resl
, rd
, 0, MO_64
);
7240 tcg_temp_free_i64(tcg_resl
);
7243 write_vec_element(s
, tcg_resh
, rd
, 1, MO_64
);
7244 tcg_temp_free_i64(tcg_resh
);
7246 clear_vec_high(s
, is_q
, rd
);
7250 * do_reduction_op helper
7252 * This mirrors the Reduce() pseudocode in the ARM ARM. It is
7253 * important for correct NaN propagation that we do these
7254 * operations in exactly the order specified by the pseudocode.
7256 * This is a recursive function, TCG temps should be freed by the
7257 * calling function once it is done with the values.
7259 static TCGv_i32
do_reduction_op(DisasContext
*s
, int fpopcode
, int rn
,
7260 int esize
, int size
, int vmap
, TCGv_ptr fpst
)
7262 if (esize
== size
) {
7264 MemOp msize
= esize
== 16 ? MO_16
: MO_32
;
7267 /* We should have one register left here */
7268 assert(ctpop8(vmap
) == 1);
7269 element
= ctz32(vmap
);
7270 assert(element
< 8);
7272 tcg_elem
= tcg_temp_new_i32();
7273 read_vec_element_i32(s
, tcg_elem
, rn
, element
, msize
);
7276 int bits
= size
/ 2;
7277 int shift
= ctpop8(vmap
) / 2;
7278 int vmap_lo
= (vmap
>> shift
) & vmap
;
7279 int vmap_hi
= (vmap
& ~vmap_lo
);
7280 TCGv_i32 tcg_hi
, tcg_lo
, tcg_res
;
7282 tcg_hi
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_hi
, fpst
);
7283 tcg_lo
= do_reduction_op(s
, fpopcode
, rn
, esize
, bits
, vmap_lo
, fpst
);
7284 tcg_res
= tcg_temp_new_i32();
7287 case 0x0c: /* fmaxnmv half-precision */
7288 gen_helper_advsimd_maxnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7290 case 0x0f: /* fmaxv half-precision */
7291 gen_helper_advsimd_maxh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7293 case 0x1c: /* fminnmv half-precision */
7294 gen_helper_advsimd_minnumh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7296 case 0x1f: /* fminv half-precision */
7297 gen_helper_advsimd_minh(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7299 case 0x2c: /* fmaxnmv */
7300 gen_helper_vfp_maxnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7302 case 0x2f: /* fmaxv */
7303 gen_helper_vfp_maxs(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7305 case 0x3c: /* fminnmv */
7306 gen_helper_vfp_minnums(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7308 case 0x3f: /* fminv */
7309 gen_helper_vfp_mins(tcg_res
, tcg_lo
, tcg_hi
, fpst
);
7312 g_assert_not_reached();
7315 tcg_temp_free_i32(tcg_hi
);
7316 tcg_temp_free_i32(tcg_lo
);
7321 /* AdvSIMD across lanes
7322 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
7323 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
7324 * | 0 | Q | U | 0 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
7325 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
7327 static void disas_simd_across_lanes(DisasContext
*s
, uint32_t insn
)
7329 int rd
= extract32(insn
, 0, 5);
7330 int rn
= extract32(insn
, 5, 5);
7331 int size
= extract32(insn
, 22, 2);
7332 int opcode
= extract32(insn
, 12, 5);
7333 bool is_q
= extract32(insn
, 30, 1);
7334 bool is_u
= extract32(insn
, 29, 1);
7336 bool is_min
= false;
7340 TCGv_i64 tcg_res
, tcg_elt
;
7343 case 0x1b: /* ADDV */
7345 unallocated_encoding(s
);
7349 case 0x3: /* SADDLV, UADDLV */
7350 case 0xa: /* SMAXV, UMAXV */
7351 case 0x1a: /* SMINV, UMINV */
7352 if (size
== 3 || (size
== 2 && !is_q
)) {
7353 unallocated_encoding(s
);
7357 case 0xc: /* FMAXNMV, FMINNMV */
7358 case 0xf: /* FMAXV, FMINV */
7359 /* Bit 1 of size field encodes min vs max and the actual size
7360 * depends on the encoding of the U bit. If not set (and FP16
7361 * enabled) then we do half-precision float instead of single
7364 is_min
= extract32(size
, 1, 1);
7366 if (!is_u
&& dc_isar_feature(aa64_fp16
, s
)) {
7368 } else if (!is_u
|| !is_q
|| extract32(size
, 0, 1)) {
7369 unallocated_encoding(s
);
7376 unallocated_encoding(s
);
7380 if (!fp_access_check(s
)) {
7385 elements
= (is_q
? 128 : 64) / esize
;
7387 tcg_res
= tcg_temp_new_i64();
7388 tcg_elt
= tcg_temp_new_i64();
7390 /* These instructions operate across all lanes of a vector
7391 * to produce a single result. We can guarantee that a 64
7392 * bit intermediate is sufficient:
7393 * + for [US]ADDLV the maximum element size is 32 bits, and
7394 * the result type is 64 bits
7395 * + for FMAX*V, FMIN*V, ADDV the intermediate type is the
7396 * same as the element size, which is 32 bits at most
7397 * For the integer operations we can choose to work at 64
7398 * or 32 bits and truncate at the end; for simplicity
7399 * we use 64 bits always. The floating point
7400 * ops do require 32 bit intermediates, though.
7403 read_vec_element(s
, tcg_res
, rn
, 0, size
| (is_u
? 0 : MO_SIGN
));
7405 for (i
= 1; i
< elements
; i
++) {
7406 read_vec_element(s
, tcg_elt
, rn
, i
, size
| (is_u
? 0 : MO_SIGN
));
7409 case 0x03: /* SADDLV / UADDLV */
7410 case 0x1b: /* ADDV */
7411 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_elt
);
7413 case 0x0a: /* SMAXV / UMAXV */
7415 tcg_gen_umax_i64(tcg_res
, tcg_res
, tcg_elt
);
7417 tcg_gen_smax_i64(tcg_res
, tcg_res
, tcg_elt
);
7420 case 0x1a: /* SMINV / UMINV */
7422 tcg_gen_umin_i64(tcg_res
, tcg_res
, tcg_elt
);
7424 tcg_gen_smin_i64(tcg_res
, tcg_res
, tcg_elt
);
7428 g_assert_not_reached();
7433 /* Floating point vector reduction ops which work across 32
7434 * bit (single) or 16 bit (half-precision) intermediates.
7435 * Note that correct NaN propagation requires that we do these
7436 * operations in exactly the order specified by the pseudocode.
7438 TCGv_ptr fpst
= get_fpstatus_ptr(size
== MO_16
);
7439 int fpopcode
= opcode
| is_min
<< 4 | is_u
<< 5;
7440 int vmap
= (1 << elements
) - 1;
7441 TCGv_i32 tcg_res32
= do_reduction_op(s
, fpopcode
, rn
, esize
,
7442 (is_q
? 128 : 64), vmap
, fpst
);
7443 tcg_gen_extu_i32_i64(tcg_res
, tcg_res32
);
7444 tcg_temp_free_i32(tcg_res32
);
7445 tcg_temp_free_ptr(fpst
);
7448 tcg_temp_free_i64(tcg_elt
);
7450 /* Now truncate the result to the width required for the final output */
7451 if (opcode
== 0x03) {
7452 /* SADDLV, UADDLV: result is 2*esize */
7458 tcg_gen_ext8u_i64(tcg_res
, tcg_res
);
7461 tcg_gen_ext16u_i64(tcg_res
, tcg_res
);
7464 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
7469 g_assert_not_reached();
7472 write_fp_dreg(s
, rd
, tcg_res
);
7473 tcg_temp_free_i64(tcg_res
);
7476 /* DUP (Element, Vector)
7478 * 31 30 29 21 20 16 15 10 9 5 4 0
7479 * +---+---+-------------------+--------+-------------+------+------+
7480 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
7481 * +---+---+-------------------+--------+-------------+------+------+
7483 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7485 static void handle_simd_dupe(DisasContext
*s
, int is_q
, int rd
, int rn
,
7488 int size
= ctz32(imm5
);
7491 if (size
> 3 || (size
== 3 && !is_q
)) {
7492 unallocated_encoding(s
);
7496 if (!fp_access_check(s
)) {
7500 index
= imm5
>> (size
+ 1);
7501 tcg_gen_gvec_dup_mem(size
, vec_full_reg_offset(s
, rd
),
7502 vec_reg_offset(s
, rn
, index
, size
),
7503 is_q
? 16 : 8, vec_full_reg_size(s
));
7506 /* DUP (element, scalar)
7507 * 31 21 20 16 15 10 9 5 4 0
7508 * +-----------------------+--------+-------------+------+------+
7509 * | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
7510 * +-----------------------+--------+-------------+------+------+
7512 static void handle_simd_dupes(DisasContext
*s
, int rd
, int rn
,
7515 int size
= ctz32(imm5
);
7520 unallocated_encoding(s
);
7524 if (!fp_access_check(s
)) {
7528 index
= imm5
>> (size
+ 1);
7530 /* This instruction just extracts the specified element and
7531 * zero-extends it into the bottom of the destination register.
7533 tmp
= tcg_temp_new_i64();
7534 read_vec_element(s
, tmp
, rn
, index
, size
);
7535 write_fp_dreg(s
, rd
, tmp
);
7536 tcg_temp_free_i64(tmp
);
7541 * 31 30 29 21 20 16 15 10 9 5 4 0
7542 * +---+---+-------------------+--------+-------------+------+------+
7543 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd |
7544 * +---+---+-------------------+--------+-------------+------+------+
7546 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7548 static void handle_simd_dupg(DisasContext
*s
, int is_q
, int rd
, int rn
,
7551 int size
= ctz32(imm5
);
7552 uint32_t dofs
, oprsz
, maxsz
;
7554 if (size
> 3 || ((size
== 3) && !is_q
)) {
7555 unallocated_encoding(s
);
7559 if (!fp_access_check(s
)) {
7563 dofs
= vec_full_reg_offset(s
, rd
);
7564 oprsz
= is_q
? 16 : 8;
7565 maxsz
= vec_full_reg_size(s
);
7567 tcg_gen_gvec_dup_i64(size
, dofs
, oprsz
, maxsz
, cpu_reg(s
, rn
));
7572 * 31 21 20 16 15 14 11 10 9 5 4 0
7573 * +-----------------------+--------+------------+---+------+------+
7574 * | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7575 * +-----------------------+--------+------------+---+------+------+
7577 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7578 * index: encoded in imm5<4:size+1>
7580 static void handle_simd_inse(DisasContext
*s
, int rd
, int rn
,
7583 int size
= ctz32(imm5
);
7584 int src_index
, dst_index
;
7588 unallocated_encoding(s
);
7592 if (!fp_access_check(s
)) {
7596 dst_index
= extract32(imm5
, 1+size
, 5);
7597 src_index
= extract32(imm4
, size
, 4);
7599 tmp
= tcg_temp_new_i64();
7601 read_vec_element(s
, tmp
, rn
, src_index
, size
);
7602 write_vec_element(s
, tmp
, rd
, dst_index
, size
);
7604 tcg_temp_free_i64(tmp
);
7606 /* INS is considered a 128-bit write for SVE. */
7607 clear_vec_high(s
, true, rd
);
7613 * 31 21 20 16 15 10 9 5 4 0
7614 * +-----------------------+--------+-------------+------+------+
7615 * | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd |
7616 * +-----------------------+--------+-------------+------+------+
7618 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7619 * index: encoded in imm5<4:size+1>
7621 static void handle_simd_insg(DisasContext
*s
, int rd
, int rn
, int imm5
)
7623 int size
= ctz32(imm5
);
7627 unallocated_encoding(s
);
7631 if (!fp_access_check(s
)) {
7635 idx
= extract32(imm5
, 1 + size
, 4 - size
);
7636 write_vec_element(s
, cpu_reg(s
, rn
), rd
, idx
, size
);
7638 /* INS is considered a 128-bit write for SVE. */
7639 clear_vec_high(s
, true, rd
);
7646 * 31 30 29 21 20 16 15 12 10 9 5 4 0
7647 * +---+---+-------------------+--------+-------------+------+------+
7648 * | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd |
7649 * +---+---+-------------------+--------+-------------+------+------+
7651 * U: unsigned when set
7652 * size: encoded in imm5 (see ARM ARM LowestSetBit())
7654 static void handle_simd_umov_smov(DisasContext
*s
, int is_q
, int is_signed
,
7655 int rn
, int rd
, int imm5
)
7657 int size
= ctz32(imm5
);
7661 /* Check for UnallocatedEncodings */
7663 if (size
> 2 || (size
== 2 && !is_q
)) {
7664 unallocated_encoding(s
);
7669 || (size
< 3 && is_q
)
7670 || (size
== 3 && !is_q
)) {
7671 unallocated_encoding(s
);
7676 if (!fp_access_check(s
)) {
7680 element
= extract32(imm5
, 1+size
, 4);
7682 tcg_rd
= cpu_reg(s
, rd
);
7683 read_vec_element(s
, tcg_rd
, rn
, element
, size
| (is_signed
? MO_SIGN
: 0));
7684 if (is_signed
&& !is_q
) {
7685 tcg_gen_ext32u_i64(tcg_rd
, tcg_rd
);
7690 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
7691 * +---+---+----+-----------------+------+---+------+---+------+------+
7692 * | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7693 * +---+---+----+-----------------+------+---+------+---+------+------+
7695 static void disas_simd_copy(DisasContext
*s
, uint32_t insn
)
7697 int rd
= extract32(insn
, 0, 5);
7698 int rn
= extract32(insn
, 5, 5);
7699 int imm4
= extract32(insn
, 11, 4);
7700 int op
= extract32(insn
, 29, 1);
7701 int is_q
= extract32(insn
, 30, 1);
7702 int imm5
= extract32(insn
, 16, 5);
7707 handle_simd_inse(s
, rd
, rn
, imm4
, imm5
);
7709 unallocated_encoding(s
);
7714 /* DUP (element - vector) */
7715 handle_simd_dupe(s
, is_q
, rd
, rn
, imm5
);
7719 handle_simd_dupg(s
, is_q
, rd
, rn
, imm5
);
7724 handle_simd_insg(s
, rd
, rn
, imm5
);
7726 unallocated_encoding(s
);
7731 /* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */
7732 handle_simd_umov_smov(s
, is_q
, (imm4
== 5), rn
, rd
, imm5
);
7735 unallocated_encoding(s
);
7741 /* AdvSIMD modified immediate
7742 * 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
7743 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
7744 * | 0 | Q | op | 0 1 1 1 1 0 0 0 0 0 | abc | cmode | o2 | 1 | defgh | Rd |
7745 * +---+---+----+---------------------+-----+-------+----+---+-------+------+
7747 * There are a number of operations that can be carried out here:
7748 * MOVI - move (shifted) imm into register
7749 * MVNI - move inverted (shifted) imm into register
7750 * ORR - bitwise OR of (shifted) imm with register
7751 * BIC - bitwise clear of (shifted) imm with register
7752 * With ARMv8.2 we also have:
7753 * FMOV half-precision
7755 static void disas_simd_mod_imm(DisasContext
*s
, uint32_t insn
)
7757 int rd
= extract32(insn
, 0, 5);
7758 int cmode
= extract32(insn
, 12, 4);
7759 int cmode_3_1
= extract32(cmode
, 1, 3);
7760 int cmode_0
= extract32(cmode
, 0, 1);
7761 int o2
= extract32(insn
, 11, 1);
7762 uint64_t abcdefgh
= extract32(insn
, 5, 5) | (extract32(insn
, 16, 3) << 5);
7763 bool is_neg
= extract32(insn
, 29, 1);
7764 bool is_q
= extract32(insn
, 30, 1);
7767 if (o2
!= 0 || ((cmode
== 0xf) && is_neg
&& !is_q
)) {
7768 /* Check for FMOV (vector, immediate) - half-precision */
7769 if (!(dc_isar_feature(aa64_fp16
, s
) && o2
&& cmode
== 0xf)) {
7770 unallocated_encoding(s
);
7775 if (!fp_access_check(s
)) {
7779 /* See AdvSIMDExpandImm() in ARM ARM */
7780 switch (cmode_3_1
) {
7781 case 0: /* Replicate(Zeros(24):imm8, 2) */
7782 case 1: /* Replicate(Zeros(16):imm8:Zeros(8), 2) */
7783 case 2: /* Replicate(Zeros(8):imm8:Zeros(16), 2) */
7784 case 3: /* Replicate(imm8:Zeros(24), 2) */
7786 int shift
= cmode_3_1
* 8;
7787 imm
= bitfield_replicate(abcdefgh
<< shift
, 32);
7790 case 4: /* Replicate(Zeros(8):imm8, 4) */
7791 case 5: /* Replicate(imm8:Zeros(8), 4) */
7793 int shift
= (cmode_3_1
& 0x1) * 8;
7794 imm
= bitfield_replicate(abcdefgh
<< shift
, 16);
7799 /* Replicate(Zeros(8):imm8:Ones(16), 2) */
7800 imm
= (abcdefgh
<< 16) | 0xffff;
7802 /* Replicate(Zeros(16):imm8:Ones(8), 2) */
7803 imm
= (abcdefgh
<< 8) | 0xff;
7805 imm
= bitfield_replicate(imm
, 32);
7808 if (!cmode_0
&& !is_neg
) {
7809 imm
= bitfield_replicate(abcdefgh
, 8);
7810 } else if (!cmode_0
&& is_neg
) {
7813 for (i
= 0; i
< 8; i
++) {
7814 if ((abcdefgh
) & (1 << i
)) {
7815 imm
|= 0xffULL
<< (i
* 8);
7818 } else if (cmode_0
) {
7820 imm
= (abcdefgh
& 0x3f) << 48;
7821 if (abcdefgh
& 0x80) {
7822 imm
|= 0x8000000000000000ULL
;
7824 if (abcdefgh
& 0x40) {
7825 imm
|= 0x3fc0000000000000ULL
;
7827 imm
|= 0x4000000000000000ULL
;
7831 /* FMOV (vector, immediate) - half-precision */
7832 imm
= vfp_expand_imm(MO_16
, abcdefgh
);
7833 /* now duplicate across the lanes */
7834 imm
= bitfield_replicate(imm
, 16);
7836 imm
= (abcdefgh
& 0x3f) << 19;
7837 if (abcdefgh
& 0x80) {
7840 if (abcdefgh
& 0x40) {
7851 fprintf(stderr
, "%s: cmode_3_1: %x\n", __func__
, cmode_3_1
);
7852 g_assert_not_reached();
7855 if (cmode_3_1
!= 7 && is_neg
) {
7859 if (!((cmode
& 0x9) == 0x1 || (cmode
& 0xd) == 0x9)) {
7860 /* MOVI or MVNI, with MVNI negation handled above. */
7861 tcg_gen_gvec_dup_imm(MO_64
, vec_full_reg_offset(s
, rd
), is_q
? 16 : 8,
7862 vec_full_reg_size(s
), imm
);
7864 /* ORR or BIC, with BIC negation to AND handled above. */
7866 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_andi
, MO_64
);
7868 gen_gvec_fn2i(s
, is_q
, rd
, rd
, imm
, tcg_gen_gvec_ori
, MO_64
);
7873 /* AdvSIMD scalar copy
7874 * 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
7875 * +-----+----+-----------------+------+---+------+---+------+------+
7876 * | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
7877 * +-----+----+-----------------+------+---+------+---+------+------+
7879 static void disas_simd_scalar_copy(DisasContext
*s
, uint32_t insn
)
7881 int rd
= extract32(insn
, 0, 5);
7882 int rn
= extract32(insn
, 5, 5);
7883 int imm4
= extract32(insn
, 11, 4);
7884 int imm5
= extract32(insn
, 16, 5);
7885 int op
= extract32(insn
, 29, 1);
7887 if (op
!= 0 || imm4
!= 0) {
7888 unallocated_encoding(s
);
7892 /* DUP (element, scalar) */
7893 handle_simd_dupes(s
, rd
, rn
, imm5
);
7896 /* AdvSIMD scalar pairwise
7897 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
7898 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7899 * | 0 1 | U | 1 1 1 1 0 | size | 1 1 0 0 0 | opcode | 1 0 | Rn | Rd |
7900 * +-----+---+-----------+------+-----------+--------+-----+------+------+
7902 static void disas_simd_scalar_pairwise(DisasContext
*s
, uint32_t insn
)
7904 int u
= extract32(insn
, 29, 1);
7905 int size
= extract32(insn
, 22, 2);
7906 int opcode
= extract32(insn
, 12, 5);
7907 int rn
= extract32(insn
, 5, 5);
7908 int rd
= extract32(insn
, 0, 5);
7911 /* For some ops (the FP ones), size[1] is part of the encoding.
7912 * For ADDP strictly it is not but size[1] is always 1 for valid
7915 opcode
|= (extract32(size
, 1, 1) << 5);
7918 case 0x3b: /* ADDP */
7919 if (u
|| size
!= 3) {
7920 unallocated_encoding(s
);
7923 if (!fp_access_check(s
)) {
7929 case 0xc: /* FMAXNMP */
7930 case 0xd: /* FADDP */
7931 case 0xf: /* FMAXP */
7932 case 0x2c: /* FMINNMP */
7933 case 0x2f: /* FMINP */
7934 /* FP op, size[0] is 32 or 64 bit*/
7936 if (!dc_isar_feature(aa64_fp16
, s
)) {
7937 unallocated_encoding(s
);
7943 size
= extract32(size
, 0, 1) ? MO_64
: MO_32
;
7946 if (!fp_access_check(s
)) {
7950 fpst
= get_fpstatus_ptr(size
== MO_16
);
7953 unallocated_encoding(s
);
7957 if (size
== MO_64
) {
7958 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
7959 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
7960 TCGv_i64 tcg_res
= tcg_temp_new_i64();
7962 read_vec_element(s
, tcg_op1
, rn
, 0, MO_64
);
7963 read_vec_element(s
, tcg_op2
, rn
, 1, MO_64
);
7966 case 0x3b: /* ADDP */
7967 tcg_gen_add_i64(tcg_res
, tcg_op1
, tcg_op2
);
7969 case 0xc: /* FMAXNMP */
7970 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7972 case 0xd: /* FADDP */
7973 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7975 case 0xf: /* FMAXP */
7976 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7978 case 0x2c: /* FMINNMP */
7979 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7981 case 0x2f: /* FMINP */
7982 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
7985 g_assert_not_reached();
7988 write_fp_dreg(s
, rd
, tcg_res
);
7990 tcg_temp_free_i64(tcg_op1
);
7991 tcg_temp_free_i64(tcg_op2
);
7992 tcg_temp_free_i64(tcg_res
);
7994 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
7995 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
7996 TCGv_i32 tcg_res
= tcg_temp_new_i32();
7998 read_vec_element_i32(s
, tcg_op1
, rn
, 0, size
);
7999 read_vec_element_i32(s
, tcg_op2
, rn
, 1, size
);
8001 if (size
== MO_16
) {
8003 case 0xc: /* FMAXNMP */
8004 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8006 case 0xd: /* FADDP */
8007 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8009 case 0xf: /* FMAXP */
8010 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8012 case 0x2c: /* FMINNMP */
8013 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8015 case 0x2f: /* FMINP */
8016 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8019 g_assert_not_reached();
8023 case 0xc: /* FMAXNMP */
8024 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8026 case 0xd: /* FADDP */
8027 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8029 case 0xf: /* FMAXP */
8030 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8032 case 0x2c: /* FMINNMP */
8033 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8035 case 0x2f: /* FMINP */
8036 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
8039 g_assert_not_reached();
8043 write_fp_sreg(s
, rd
, tcg_res
);
8045 tcg_temp_free_i32(tcg_op1
);
8046 tcg_temp_free_i32(tcg_op2
);
8047 tcg_temp_free_i32(tcg_res
);
8051 tcg_temp_free_ptr(fpst
);
8056 * Common SSHR[RA]/USHR[RA] - Shift right (optional rounding/accumulate)
8058 * This code is handles the common shifting code and is used by both
8059 * the vector and scalar code.
8061 static void handle_shri_with_rndacc(TCGv_i64 tcg_res
, TCGv_i64 tcg_src
,
8062 TCGv_i64 tcg_rnd
, bool accumulate
,
8063 bool is_u
, int size
, int shift
)
8065 bool extended_result
= false;
8066 bool round
= tcg_rnd
!= NULL
;
8068 TCGv_i64 tcg_src_hi
;
8070 if (round
&& size
== 3) {
8071 extended_result
= true;
8072 ext_lshift
= 64 - shift
;
8073 tcg_src_hi
= tcg_temp_new_i64();
8074 } else if (shift
== 64) {
8075 if (!accumulate
&& is_u
) {
8076 /* result is zero */
8077 tcg_gen_movi_i64(tcg_res
, 0);
8082 /* Deal with the rounding step */
8084 if (extended_result
) {
8085 TCGv_i64 tcg_zero
= tcg_const_i64(0);
8087 /* take care of sign extending tcg_res */
8088 tcg_gen_sari_i64(tcg_src_hi
, tcg_src
, 63);
8089 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
8090 tcg_src
, tcg_src_hi
,
8093 tcg_gen_add2_i64(tcg_src
, tcg_src_hi
,
8097 tcg_temp_free_i64(tcg_zero
);
8099 tcg_gen_add_i64(tcg_src
, tcg_src
, tcg_rnd
);
8103 /* Now do the shift right */
8104 if (round
&& extended_result
) {
8105 /* extended case, >64 bit precision required */
8106 if (ext_lshift
== 0) {
8107 /* special case, only high bits matter */
8108 tcg_gen_mov_i64(tcg_src
, tcg_src_hi
);
8110 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
8111 tcg_gen_shli_i64(tcg_src_hi
, tcg_src_hi
, ext_lshift
);
8112 tcg_gen_or_i64(tcg_src
, tcg_src
, tcg_src_hi
);
8117 /* essentially shifting in 64 zeros */
8118 tcg_gen_movi_i64(tcg_src
, 0);
8120 tcg_gen_shri_i64(tcg_src
, tcg_src
, shift
);
8124 /* effectively extending the sign-bit */
8125 tcg_gen_sari_i64(tcg_src
, tcg_src
, 63);
8127 tcg_gen_sari_i64(tcg_src
, tcg_src
, shift
);
8133 tcg_gen_add_i64(tcg_res
, tcg_res
, tcg_src
);
8135 tcg_gen_mov_i64(tcg_res
, tcg_src
);
8138 if (extended_result
) {
8139 tcg_temp_free_i64(tcg_src_hi
);
8143 /* SSHR[RA]/USHR[RA] - Scalar shift right (optional rounding/accumulate) */
8144 static void handle_scalar_simd_shri(DisasContext
*s
,
8145 bool is_u
, int immh
, int immb
,
8146 int opcode
, int rn
, int rd
)
8149 int immhb
= immh
<< 3 | immb
;
8150 int shift
= 2 * (8 << size
) - immhb
;
8151 bool accumulate
= false;
8153 bool insert
= false;
8158 if (!extract32(immh
, 3, 1)) {
8159 unallocated_encoding(s
);
8163 if (!fp_access_check(s
)) {
8168 case 0x02: /* SSRA / USRA (accumulate) */
8171 case 0x04: /* SRSHR / URSHR (rounding) */
8174 case 0x06: /* SRSRA / URSRA (accum + rounding) */
8175 accumulate
= round
= true;
8177 case 0x08: /* SRI */
8183 uint64_t round_const
= 1ULL << (shift
- 1);
8184 tcg_round
= tcg_const_i64(round_const
);
8189 tcg_rn
= read_fp_dreg(s
, rn
);
8190 tcg_rd
= (accumulate
|| insert
) ? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
8193 /* shift count same as element size is valid but does nothing;
8194 * special case to avoid potential shift by 64.
8196 int esize
= 8 << size
;
8197 if (shift
!= esize
) {
8198 tcg_gen_shri_i64(tcg_rn
, tcg_rn
, shift
);
8199 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, 0, esize
- shift
);
8202 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8203 accumulate
, is_u
, size
, shift
);
8206 write_fp_dreg(s
, rd
, tcg_rd
);
8208 tcg_temp_free_i64(tcg_rn
);
8209 tcg_temp_free_i64(tcg_rd
);
8211 tcg_temp_free_i64(tcg_round
);
8215 /* SHL/SLI - Scalar shift left */
8216 static void handle_scalar_simd_shli(DisasContext
*s
, bool insert
,
8217 int immh
, int immb
, int opcode
,
8220 int size
= 32 - clz32(immh
) - 1;
8221 int immhb
= immh
<< 3 | immb
;
8222 int shift
= immhb
- (8 << size
);
8223 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
8224 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
8226 if (!extract32(immh
, 3, 1)) {
8227 unallocated_encoding(s
);
8231 if (!fp_access_check(s
)) {
8235 tcg_rn
= read_fp_dreg(s
, rn
);
8236 tcg_rd
= insert
? read_fp_dreg(s
, rd
) : tcg_temp_new_i64();
8239 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, shift
, 64 - shift
);
8241 tcg_gen_shli_i64(tcg_rd
, tcg_rn
, shift
);
8244 write_fp_dreg(s
, rd
, tcg_rd
);
8246 tcg_temp_free_i64(tcg_rn
);
8247 tcg_temp_free_i64(tcg_rd
);
8250 /* SQSHRN/SQSHRUN - Saturating (signed/unsigned) shift right with
8251 * (signed/unsigned) narrowing */
8252 static void handle_vec_simd_sqshrn(DisasContext
*s
, bool is_scalar
, bool is_q
,
8253 bool is_u_shift
, bool is_u_narrow
,
8254 int immh
, int immb
, int opcode
,
8257 int immhb
= immh
<< 3 | immb
;
8258 int size
= 32 - clz32(immh
) - 1;
8259 int esize
= 8 << size
;
8260 int shift
= (2 * esize
) - immhb
;
8261 int elements
= is_scalar
? 1 : (64 / esize
);
8262 bool round
= extract32(opcode
, 0, 1);
8263 MemOp ldop
= (size
+ 1) | (is_u_shift
? 0 : MO_SIGN
);
8264 TCGv_i64 tcg_rn
, tcg_rd
, tcg_round
;
8265 TCGv_i32 tcg_rd_narrowed
;
8268 static NeonGenNarrowEnvFn
* const signed_narrow_fns
[4][2] = {
8269 { gen_helper_neon_narrow_sat_s8
,
8270 gen_helper_neon_unarrow_sat8
},
8271 { gen_helper_neon_narrow_sat_s16
,
8272 gen_helper_neon_unarrow_sat16
},
8273 { gen_helper_neon_narrow_sat_s32
,
8274 gen_helper_neon_unarrow_sat32
},
8277 static NeonGenNarrowEnvFn
* const unsigned_narrow_fns
[4] = {
8278 gen_helper_neon_narrow_sat_u8
,
8279 gen_helper_neon_narrow_sat_u16
,
8280 gen_helper_neon_narrow_sat_u32
,
8283 NeonGenNarrowEnvFn
*narrowfn
;
8289 if (extract32(immh
, 3, 1)) {
8290 unallocated_encoding(s
);
8294 if (!fp_access_check(s
)) {
8299 narrowfn
= unsigned_narrow_fns
[size
];
8301 narrowfn
= signed_narrow_fns
[size
][is_u_narrow
? 1 : 0];
8304 tcg_rn
= tcg_temp_new_i64();
8305 tcg_rd
= tcg_temp_new_i64();
8306 tcg_rd_narrowed
= tcg_temp_new_i32();
8307 tcg_final
= tcg_const_i64(0);
8310 uint64_t round_const
= 1ULL << (shift
- 1);
8311 tcg_round
= tcg_const_i64(round_const
);
8316 for (i
= 0; i
< elements
; i
++) {
8317 read_vec_element(s
, tcg_rn
, rn
, i
, ldop
);
8318 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
8319 false, is_u_shift
, size
+1, shift
);
8320 narrowfn(tcg_rd_narrowed
, cpu_env
, tcg_rd
);
8321 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd_narrowed
);
8322 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
8326 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
8328 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
8332 tcg_temp_free_i64(tcg_round
);
8334 tcg_temp_free_i64(tcg_rn
);
8335 tcg_temp_free_i64(tcg_rd
);
8336 tcg_temp_free_i32(tcg_rd_narrowed
);
8337 tcg_temp_free_i64(tcg_final
);
8339 clear_vec_high(s
, is_q
, rd
);
8342 /* SQSHLU, UQSHL, SQSHL: saturating left shifts */
8343 static void handle_simd_qshl(DisasContext
*s
, bool scalar
, bool is_q
,
8344 bool src_unsigned
, bool dst_unsigned
,
8345 int immh
, int immb
, int rn
, int rd
)
8347 int immhb
= immh
<< 3 | immb
;
8348 int size
= 32 - clz32(immh
) - 1;
8349 int shift
= immhb
- (8 << size
);
8353 assert(!(scalar
&& is_q
));
8356 if (!is_q
&& extract32(immh
, 3, 1)) {
8357 unallocated_encoding(s
);
8361 /* Since we use the variable-shift helpers we must
8362 * replicate the shift count into each element of
8363 * the tcg_shift value.
8367 shift
|= shift
<< 8;
8370 shift
|= shift
<< 16;
8376 g_assert_not_reached();
8380 if (!fp_access_check(s
)) {
8385 TCGv_i64 tcg_shift
= tcg_const_i64(shift
);
8386 static NeonGenTwo64OpEnvFn
* const fns
[2][2] = {
8387 { gen_helper_neon_qshl_s64
, gen_helper_neon_qshlu_s64
},
8388 { NULL
, gen_helper_neon_qshl_u64
},
8390 NeonGenTwo64OpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
];
8391 int maxpass
= is_q
? 2 : 1;
8393 for (pass
= 0; pass
< maxpass
; pass
++) {
8394 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8396 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
8397 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
8398 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
8400 tcg_temp_free_i64(tcg_op
);
8402 tcg_temp_free_i64(tcg_shift
);
8403 clear_vec_high(s
, is_q
, rd
);
8405 TCGv_i32 tcg_shift
= tcg_const_i32(shift
);
8406 static NeonGenTwoOpEnvFn
* const fns
[2][2][3] = {
8408 { gen_helper_neon_qshl_s8
,
8409 gen_helper_neon_qshl_s16
,
8410 gen_helper_neon_qshl_s32
},
8411 { gen_helper_neon_qshlu_s8
,
8412 gen_helper_neon_qshlu_s16
,
8413 gen_helper_neon_qshlu_s32
}
8415 { NULL
, NULL
, NULL
},
8416 { gen_helper_neon_qshl_u8
,
8417 gen_helper_neon_qshl_u16
,
8418 gen_helper_neon_qshl_u32
}
8421 NeonGenTwoOpEnvFn
*genfn
= fns
[src_unsigned
][dst_unsigned
][size
];
8422 MemOp memop
= scalar
? size
: MO_32
;
8423 int maxpass
= scalar
? 1 : is_q
? 4 : 2;
8425 for (pass
= 0; pass
< maxpass
; pass
++) {
8426 TCGv_i32 tcg_op
= tcg_temp_new_i32();
8428 read_vec_element_i32(s
, tcg_op
, rn
, pass
, memop
);
8429 genfn(tcg_op
, cpu_env
, tcg_op
, tcg_shift
);
8433 tcg_gen_ext8u_i32(tcg_op
, tcg_op
);
8436 tcg_gen_ext16u_i32(tcg_op
, tcg_op
);
8441 g_assert_not_reached();
8443 write_fp_sreg(s
, rd
, tcg_op
);
8445 write_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
8448 tcg_temp_free_i32(tcg_op
);
8450 tcg_temp_free_i32(tcg_shift
);
8453 clear_vec_high(s
, is_q
, rd
);
8458 /* Common vector code for handling integer to FP conversion */
8459 static void handle_simd_intfp_conv(DisasContext
*s
, int rd
, int rn
,
8460 int elements
, int is_signed
,
8461 int fracbits
, int size
)
8463 TCGv_ptr tcg_fpst
= get_fpstatus_ptr(size
== MO_16
);
8464 TCGv_i32 tcg_shift
= NULL
;
8466 MemOp mop
= size
| (is_signed
? MO_SIGN
: 0);
8469 if (fracbits
|| size
== MO_64
) {
8470 tcg_shift
= tcg_const_i32(fracbits
);
8473 if (size
== MO_64
) {
8474 TCGv_i64 tcg_int64
= tcg_temp_new_i64();
8475 TCGv_i64 tcg_double
= tcg_temp_new_i64();
8477 for (pass
= 0; pass
< elements
; pass
++) {
8478 read_vec_element(s
, tcg_int64
, rn
, pass
, mop
);
8481 gen_helper_vfp_sqtod(tcg_double
, tcg_int64
,
8482 tcg_shift
, tcg_fpst
);
8484 gen_helper_vfp_uqtod(tcg_double
, tcg_int64
,
8485 tcg_shift
, tcg_fpst
);
8487 if (elements
== 1) {
8488 write_fp_dreg(s
, rd
, tcg_double
);
8490 write_vec_element(s
, tcg_double
, rd
, pass
, MO_64
);
8494 tcg_temp_free_i64(tcg_int64
);
8495 tcg_temp_free_i64(tcg_double
);
8498 TCGv_i32 tcg_int32
= tcg_temp_new_i32();
8499 TCGv_i32 tcg_float
= tcg_temp_new_i32();
8501 for (pass
= 0; pass
< elements
; pass
++) {
8502 read_vec_element_i32(s
, tcg_int32
, rn
, pass
, mop
);
8508 gen_helper_vfp_sltos(tcg_float
, tcg_int32
,
8509 tcg_shift
, tcg_fpst
);
8511 gen_helper_vfp_ultos(tcg_float
, tcg_int32
,
8512 tcg_shift
, tcg_fpst
);
8516 gen_helper_vfp_sitos(tcg_float
, tcg_int32
, tcg_fpst
);
8518 gen_helper_vfp_uitos(tcg_float
, tcg_int32
, tcg_fpst
);
8525 gen_helper_vfp_sltoh(tcg_float
, tcg_int32
,
8526 tcg_shift
, tcg_fpst
);
8528 gen_helper_vfp_ultoh(tcg_float
, tcg_int32
,
8529 tcg_shift
, tcg_fpst
);
8533 gen_helper_vfp_sitoh(tcg_float
, tcg_int32
, tcg_fpst
);
8535 gen_helper_vfp_uitoh(tcg_float
, tcg_int32
, tcg_fpst
);
8540 g_assert_not_reached();
8543 if (elements
== 1) {
8544 write_fp_sreg(s
, rd
, tcg_float
);
8546 write_vec_element_i32(s
, tcg_float
, rd
, pass
, size
);
8550 tcg_temp_free_i32(tcg_int32
);
8551 tcg_temp_free_i32(tcg_float
);
8554 tcg_temp_free_ptr(tcg_fpst
);
8556 tcg_temp_free_i32(tcg_shift
);
8559 clear_vec_high(s
, elements
<< size
== 16, rd
);
8562 /* UCVTF/SCVTF - Integer to FP conversion */
8563 static void handle_simd_shift_intfp_conv(DisasContext
*s
, bool is_scalar
,
8564 bool is_q
, bool is_u
,
8565 int immh
, int immb
, int opcode
,
8568 int size
, elements
, fracbits
;
8569 int immhb
= immh
<< 3 | immb
;
8573 if (!is_scalar
&& !is_q
) {
8574 unallocated_encoding(s
);
8577 } else if (immh
& 4) {
8579 } else if (immh
& 2) {
8581 if (!dc_isar_feature(aa64_fp16
, s
)) {
8582 unallocated_encoding(s
);
8586 /* immh == 0 would be a failure of the decode logic */
8587 g_assert(immh
== 1);
8588 unallocated_encoding(s
);
8595 elements
= (8 << is_q
) >> size
;
8597 fracbits
= (16 << size
) - immhb
;
8599 if (!fp_access_check(s
)) {
8603 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !is_u
, fracbits
, size
);
8606 /* FCVTZS, FVCVTZU - FP to fixedpoint conversion */
8607 static void handle_simd_shift_fpint_conv(DisasContext
*s
, bool is_scalar
,
8608 bool is_q
, bool is_u
,
8609 int immh
, int immb
, int rn
, int rd
)
8611 int immhb
= immh
<< 3 | immb
;
8612 int pass
, size
, fracbits
;
8613 TCGv_ptr tcg_fpstatus
;
8614 TCGv_i32 tcg_rmode
, tcg_shift
;
8618 if (!is_scalar
&& !is_q
) {
8619 unallocated_encoding(s
);
8622 } else if (immh
& 0x4) {
8624 } else if (immh
& 0x2) {
8626 if (!dc_isar_feature(aa64_fp16
, s
)) {
8627 unallocated_encoding(s
);
8631 /* Should have split out AdvSIMD modified immediate earlier. */
8633 unallocated_encoding(s
);
8637 if (!fp_access_check(s
)) {
8641 assert(!(is_scalar
&& is_q
));
8643 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(FPROUNDING_ZERO
));
8644 tcg_fpstatus
= get_fpstatus_ptr(size
== MO_16
);
8645 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
8646 fracbits
= (16 << size
) - immhb
;
8647 tcg_shift
= tcg_const_i32(fracbits
);
8649 if (size
== MO_64
) {
8650 int maxpass
= is_scalar
? 1 : 2;
8652 for (pass
= 0; pass
< maxpass
; pass
++) {
8653 TCGv_i64 tcg_op
= tcg_temp_new_i64();
8655 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
8657 gen_helper_vfp_touqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
8659 gen_helper_vfp_tosqd(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
8661 write_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
8662 tcg_temp_free_i64(tcg_op
);
8664 clear_vec_high(s
, is_q
, rd
);
8666 void (*fn
)(TCGv_i32
, TCGv_i32
, TCGv_i32
, TCGv_ptr
);
8667 int maxpass
= is_scalar
? 1 : ((8 << is_q
) >> size
);
8672 fn
= gen_helper_vfp_touhh
;
8674 fn
= gen_helper_vfp_toshh
;
8679 fn
= gen_helper_vfp_touls
;
8681 fn
= gen_helper_vfp_tosls
;
8685 g_assert_not_reached();
8688 for (pass
= 0; pass
< maxpass
; pass
++) {
8689 TCGv_i32 tcg_op
= tcg_temp_new_i32();
8691 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
8692 fn(tcg_op
, tcg_op
, tcg_shift
, tcg_fpstatus
);
8694 write_fp_sreg(s
, rd
, tcg_op
);
8696 write_vec_element_i32(s
, tcg_op
, rd
, pass
, size
);
8698 tcg_temp_free_i32(tcg_op
);
8701 clear_vec_high(s
, is_q
, rd
);
8705 tcg_temp_free_ptr(tcg_fpstatus
);
8706 tcg_temp_free_i32(tcg_shift
);
8707 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
8708 tcg_temp_free_i32(tcg_rmode
);
8711 /* AdvSIMD scalar shift by immediate
8712 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
8713 * +-----+---+-------------+------+------+--------+---+------+------+
8714 * | 0 1 | U | 1 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
8715 * +-----+---+-------------+------+------+--------+---+------+------+
8717 * This is the scalar version so it works on a fixed sized registers
8719 static void disas_simd_scalar_shift_imm(DisasContext
*s
, uint32_t insn
)
8721 int rd
= extract32(insn
, 0, 5);
8722 int rn
= extract32(insn
, 5, 5);
8723 int opcode
= extract32(insn
, 11, 5);
8724 int immb
= extract32(insn
, 16, 3);
8725 int immh
= extract32(insn
, 19, 4);
8726 bool is_u
= extract32(insn
, 29, 1);
8729 unallocated_encoding(s
);
8734 case 0x08: /* SRI */
8736 unallocated_encoding(s
);
8740 case 0x00: /* SSHR / USHR */
8741 case 0x02: /* SSRA / USRA */
8742 case 0x04: /* SRSHR / URSHR */
8743 case 0x06: /* SRSRA / URSRA */
8744 handle_scalar_simd_shri(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8746 case 0x0a: /* SHL / SLI */
8747 handle_scalar_simd_shli(s
, is_u
, immh
, immb
, opcode
, rn
, rd
);
8749 case 0x1c: /* SCVTF, UCVTF */
8750 handle_simd_shift_intfp_conv(s
, true, false, is_u
, immh
, immb
,
8753 case 0x10: /* SQSHRUN, SQSHRUN2 */
8754 case 0x11: /* SQRSHRUN, SQRSHRUN2 */
8756 unallocated_encoding(s
);
8759 handle_vec_simd_sqshrn(s
, true, false, false, true,
8760 immh
, immb
, opcode
, rn
, rd
);
8762 case 0x12: /* SQSHRN, SQSHRN2, UQSHRN */
8763 case 0x13: /* SQRSHRN, SQRSHRN2, UQRSHRN, UQRSHRN2 */
8764 handle_vec_simd_sqshrn(s
, true, false, is_u
, is_u
,
8765 immh
, immb
, opcode
, rn
, rd
);
8767 case 0xc: /* SQSHLU */
8769 unallocated_encoding(s
);
8772 handle_simd_qshl(s
, true, false, false, true, immh
, immb
, rn
, rd
);
8774 case 0xe: /* SQSHL, UQSHL */
8775 handle_simd_qshl(s
, true, false, is_u
, is_u
, immh
, immb
, rn
, rd
);
8777 case 0x1f: /* FCVTZS, FCVTZU */
8778 handle_simd_shift_fpint_conv(s
, true, false, is_u
, immh
, immb
, rn
, rd
);
8781 unallocated_encoding(s
);
8786 /* AdvSIMD scalar three different
8787 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
8788 * +-----+---+-----------+------+---+------+--------+-----+------+------+
8789 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
8790 * +-----+---+-----------+------+---+------+--------+-----+------+------+
8792 static void disas_simd_scalar_three_reg_diff(DisasContext
*s
, uint32_t insn
)
8794 bool is_u
= extract32(insn
, 29, 1);
8795 int size
= extract32(insn
, 22, 2);
8796 int opcode
= extract32(insn
, 12, 4);
8797 int rm
= extract32(insn
, 16, 5);
8798 int rn
= extract32(insn
, 5, 5);
8799 int rd
= extract32(insn
, 0, 5);
8802 unallocated_encoding(s
);
8807 case 0x9: /* SQDMLAL, SQDMLAL2 */
8808 case 0xb: /* SQDMLSL, SQDMLSL2 */
8809 case 0xd: /* SQDMULL, SQDMULL2 */
8810 if (size
== 0 || size
== 3) {
8811 unallocated_encoding(s
);
8816 unallocated_encoding(s
);
8820 if (!fp_access_check(s
)) {
8825 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8826 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8827 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8829 read_vec_element(s
, tcg_op1
, rn
, 0, MO_32
| MO_SIGN
);
8830 read_vec_element(s
, tcg_op2
, rm
, 0, MO_32
| MO_SIGN
);
8832 tcg_gen_mul_i64(tcg_res
, tcg_op1
, tcg_op2
);
8833 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
8836 case 0xd: /* SQDMULL, SQDMULL2 */
8838 case 0xb: /* SQDMLSL, SQDMLSL2 */
8839 tcg_gen_neg_i64(tcg_res
, tcg_res
);
8841 case 0x9: /* SQDMLAL, SQDMLAL2 */
8842 read_vec_element(s
, tcg_op1
, rd
, 0, MO_64
);
8843 gen_helper_neon_addl_saturate_s64(tcg_res
, cpu_env
,
8847 g_assert_not_reached();
8850 write_fp_dreg(s
, rd
, tcg_res
);
8852 tcg_temp_free_i64(tcg_op1
);
8853 tcg_temp_free_i64(tcg_op2
);
8854 tcg_temp_free_i64(tcg_res
);
8856 TCGv_i32 tcg_op1
= read_fp_hreg(s
, rn
);
8857 TCGv_i32 tcg_op2
= read_fp_hreg(s
, rm
);
8858 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8860 gen_helper_neon_mull_s16(tcg_res
, tcg_op1
, tcg_op2
);
8861 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
, tcg_res
, tcg_res
);
8864 case 0xd: /* SQDMULL, SQDMULL2 */
8866 case 0xb: /* SQDMLSL, SQDMLSL2 */
8867 gen_helper_neon_negl_u32(tcg_res
, tcg_res
);
8869 case 0x9: /* SQDMLAL, SQDMLAL2 */
8871 TCGv_i64 tcg_op3
= tcg_temp_new_i64();
8872 read_vec_element(s
, tcg_op3
, rd
, 0, MO_32
);
8873 gen_helper_neon_addl_saturate_s32(tcg_res
, cpu_env
,
8875 tcg_temp_free_i64(tcg_op3
);
8879 g_assert_not_reached();
8882 tcg_gen_ext32u_i64(tcg_res
, tcg_res
);
8883 write_fp_dreg(s
, rd
, tcg_res
);
8885 tcg_temp_free_i32(tcg_op1
);
8886 tcg_temp_free_i32(tcg_op2
);
8887 tcg_temp_free_i64(tcg_res
);
8891 static void handle_3same_64(DisasContext
*s
, int opcode
, bool u
,
8892 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
, TCGv_i64 tcg_rm
)
8894 /* Handle 64x64->64 opcodes which are shared between the scalar
8895 * and vector 3-same groups. We cover every opcode where size == 3
8896 * is valid in either the three-reg-same (integer, not pairwise)
8897 * or scalar-three-reg-same groups.
8902 case 0x1: /* SQADD */
8904 gen_helper_neon_qadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8906 gen_helper_neon_qadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8909 case 0x5: /* SQSUB */
8911 gen_helper_neon_qsub_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8913 gen_helper_neon_qsub_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8916 case 0x6: /* CMGT, CMHI */
8917 /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0.
8918 * We implement this using setcond (test) and then negating.
8920 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
8922 tcg_gen_setcond_i64(cond
, tcg_rd
, tcg_rn
, tcg_rm
);
8923 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
8925 case 0x7: /* CMGE, CMHS */
8926 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
8928 case 0x11: /* CMTST, CMEQ */
8933 gen_cmtst_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8935 case 0x8: /* SSHL, USHL */
8937 gen_ushl_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8939 gen_sshl_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8942 case 0x9: /* SQSHL, UQSHL */
8944 gen_helper_neon_qshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8946 gen_helper_neon_qshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8949 case 0xa: /* SRSHL, URSHL */
8951 gen_helper_neon_rshl_u64(tcg_rd
, tcg_rn
, tcg_rm
);
8953 gen_helper_neon_rshl_s64(tcg_rd
, tcg_rn
, tcg_rm
);
8956 case 0xb: /* SQRSHL, UQRSHL */
8958 gen_helper_neon_qrshl_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8960 gen_helper_neon_qrshl_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rm
);
8963 case 0x10: /* ADD, SUB */
8965 tcg_gen_sub_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8967 tcg_gen_add_i64(tcg_rd
, tcg_rn
, tcg_rm
);
8971 g_assert_not_reached();
8975 /* Handle the 3-same-operands float operations; shared by the scalar
8976 * and vector encodings. The caller must filter out any encodings
8977 * not allocated for the encoding it is dealing with.
8979 static void handle_3same_float(DisasContext
*s
, int size
, int elements
,
8980 int fpopcode
, int rd
, int rn
, int rm
)
8983 TCGv_ptr fpst
= get_fpstatus_ptr(false);
8985 for (pass
= 0; pass
< elements
; pass
++) {
8988 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
8989 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
8990 TCGv_i64 tcg_res
= tcg_temp_new_i64();
8992 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
8993 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
8996 case 0x39: /* FMLS */
8997 /* As usual for ARM, separate negation for fused multiply-add */
8998 gen_helper_vfp_negd(tcg_op1
, tcg_op1
);
9000 case 0x19: /* FMLA */
9001 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9002 gen_helper_vfp_muladdd(tcg_res
, tcg_op1
, tcg_op2
,
9005 case 0x18: /* FMAXNM */
9006 gen_helper_vfp_maxnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9008 case 0x1a: /* FADD */
9009 gen_helper_vfp_addd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9011 case 0x1b: /* FMULX */
9012 gen_helper_vfp_mulxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9014 case 0x1c: /* FCMEQ */
9015 gen_helper_neon_ceq_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9017 case 0x1e: /* FMAX */
9018 gen_helper_vfp_maxd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9020 case 0x1f: /* FRECPS */
9021 gen_helper_recpsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9023 case 0x38: /* FMINNM */
9024 gen_helper_vfp_minnumd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9026 case 0x3a: /* FSUB */
9027 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9029 case 0x3e: /* FMIN */
9030 gen_helper_vfp_mind(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9032 case 0x3f: /* FRSQRTS */
9033 gen_helper_rsqrtsf_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9035 case 0x5b: /* FMUL */
9036 gen_helper_vfp_muld(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9038 case 0x5c: /* FCMGE */
9039 gen_helper_neon_cge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9041 case 0x5d: /* FACGE */
9042 gen_helper_neon_acge_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9044 case 0x5f: /* FDIV */
9045 gen_helper_vfp_divd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9047 case 0x7a: /* FABD */
9048 gen_helper_vfp_subd(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9049 gen_helper_vfp_absd(tcg_res
, tcg_res
);
9051 case 0x7c: /* FCMGT */
9052 gen_helper_neon_cgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9054 case 0x7d: /* FACGT */
9055 gen_helper_neon_acgt_f64(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9058 g_assert_not_reached();
9061 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9063 tcg_temp_free_i64(tcg_res
);
9064 tcg_temp_free_i64(tcg_op1
);
9065 tcg_temp_free_i64(tcg_op2
);
9068 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
9069 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
9070 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9072 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
9073 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
9076 case 0x39: /* FMLS */
9077 /* As usual for ARM, separate negation for fused multiply-add */
9078 gen_helper_vfp_negs(tcg_op1
, tcg_op1
);
9080 case 0x19: /* FMLA */
9081 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9082 gen_helper_vfp_muladds(tcg_res
, tcg_op1
, tcg_op2
,
9085 case 0x1a: /* FADD */
9086 gen_helper_vfp_adds(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9088 case 0x1b: /* FMULX */
9089 gen_helper_vfp_mulxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9091 case 0x1c: /* FCMEQ */
9092 gen_helper_neon_ceq_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9094 case 0x1e: /* FMAX */
9095 gen_helper_vfp_maxs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9097 case 0x1f: /* FRECPS */
9098 gen_helper_recpsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9100 case 0x18: /* FMAXNM */
9101 gen_helper_vfp_maxnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9103 case 0x38: /* FMINNM */
9104 gen_helper_vfp_minnums(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9106 case 0x3a: /* FSUB */
9107 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9109 case 0x3e: /* FMIN */
9110 gen_helper_vfp_mins(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9112 case 0x3f: /* FRSQRTS */
9113 gen_helper_rsqrtsf_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9115 case 0x5b: /* FMUL */
9116 gen_helper_vfp_muls(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9118 case 0x5c: /* FCMGE */
9119 gen_helper_neon_cge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9121 case 0x5d: /* FACGE */
9122 gen_helper_neon_acge_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9124 case 0x5f: /* FDIV */
9125 gen_helper_vfp_divs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9127 case 0x7a: /* FABD */
9128 gen_helper_vfp_subs(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9129 gen_helper_vfp_abss(tcg_res
, tcg_res
);
9131 case 0x7c: /* FCMGT */
9132 gen_helper_neon_cgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9134 case 0x7d: /* FACGT */
9135 gen_helper_neon_acgt_f32(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9138 g_assert_not_reached();
9141 if (elements
== 1) {
9142 /* scalar single so clear high part */
9143 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
9145 tcg_gen_extu_i32_i64(tcg_tmp
, tcg_res
);
9146 write_vec_element(s
, tcg_tmp
, rd
, pass
, MO_64
);
9147 tcg_temp_free_i64(tcg_tmp
);
9149 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9152 tcg_temp_free_i32(tcg_res
);
9153 tcg_temp_free_i32(tcg_op1
);
9154 tcg_temp_free_i32(tcg_op2
);
9158 tcg_temp_free_ptr(fpst
);
9160 clear_vec_high(s
, elements
* (size
? 8 : 4) > 8, rd
);
9163 /* AdvSIMD scalar three same
9164 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
9165 * +-----+---+-----------+------+---+------+--------+---+------+------+
9166 * | 0 1 | U | 1 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
9167 * +-----+---+-----------+------+---+------+--------+---+------+------+
9169 static void disas_simd_scalar_three_reg_same(DisasContext
*s
, uint32_t insn
)
9171 int rd
= extract32(insn
, 0, 5);
9172 int rn
= extract32(insn
, 5, 5);
9173 int opcode
= extract32(insn
, 11, 5);
9174 int rm
= extract32(insn
, 16, 5);
9175 int size
= extract32(insn
, 22, 2);
9176 bool u
= extract32(insn
, 29, 1);
9179 if (opcode
>= 0x18) {
9180 /* Floating point: U, size[1] and opcode indicate operation */
9181 int fpopcode
= opcode
| (extract32(size
, 1, 1) << 5) | (u
<< 6);
9183 case 0x1b: /* FMULX */
9184 case 0x1f: /* FRECPS */
9185 case 0x3f: /* FRSQRTS */
9186 case 0x5d: /* FACGE */
9187 case 0x7d: /* FACGT */
9188 case 0x1c: /* FCMEQ */
9189 case 0x5c: /* FCMGE */
9190 case 0x7c: /* FCMGT */
9191 case 0x7a: /* FABD */
9194 unallocated_encoding(s
);
9198 if (!fp_access_check(s
)) {
9202 handle_3same_float(s
, extract32(size
, 0, 1), 1, fpopcode
, rd
, rn
, rm
);
9207 case 0x1: /* SQADD, UQADD */
9208 case 0x5: /* SQSUB, UQSUB */
9209 case 0x9: /* SQSHL, UQSHL */
9210 case 0xb: /* SQRSHL, UQRSHL */
9212 case 0x8: /* SSHL, USHL */
9213 case 0xa: /* SRSHL, URSHL */
9214 case 0x6: /* CMGT, CMHI */
9215 case 0x7: /* CMGE, CMHS */
9216 case 0x11: /* CMTST, CMEQ */
9217 case 0x10: /* ADD, SUB (vector) */
9219 unallocated_encoding(s
);
9223 case 0x16: /* SQDMULH, SQRDMULH (vector) */
9224 if (size
!= 1 && size
!= 2) {
9225 unallocated_encoding(s
);
9230 unallocated_encoding(s
);
9234 if (!fp_access_check(s
)) {
9238 tcg_rd
= tcg_temp_new_i64();
9241 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
9242 TCGv_i64 tcg_rm
= read_fp_dreg(s
, rm
);
9244 handle_3same_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rm
);
9245 tcg_temp_free_i64(tcg_rn
);
9246 tcg_temp_free_i64(tcg_rm
);
9248 /* Do a single operation on the lowest element in the vector.
9249 * We use the standard Neon helpers and rely on 0 OP 0 == 0 with
9250 * no side effects for all these operations.
9251 * OPTME: special-purpose helpers would avoid doing some
9252 * unnecessary work in the helper for the 8 and 16 bit cases.
9254 NeonGenTwoOpEnvFn
*genenvfn
;
9255 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
9256 TCGv_i32 tcg_rm
= tcg_temp_new_i32();
9257 TCGv_i32 tcg_rd32
= tcg_temp_new_i32();
9259 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
9260 read_vec_element_i32(s
, tcg_rm
, rm
, 0, size
);
9263 case 0x1: /* SQADD, UQADD */
9265 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9266 { gen_helper_neon_qadd_s8
, gen_helper_neon_qadd_u8
},
9267 { gen_helper_neon_qadd_s16
, gen_helper_neon_qadd_u16
},
9268 { gen_helper_neon_qadd_s32
, gen_helper_neon_qadd_u32
},
9270 genenvfn
= fns
[size
][u
];
9273 case 0x5: /* SQSUB, UQSUB */
9275 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9276 { gen_helper_neon_qsub_s8
, gen_helper_neon_qsub_u8
},
9277 { gen_helper_neon_qsub_s16
, gen_helper_neon_qsub_u16
},
9278 { gen_helper_neon_qsub_s32
, gen_helper_neon_qsub_u32
},
9280 genenvfn
= fns
[size
][u
];
9283 case 0x9: /* SQSHL, UQSHL */
9285 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9286 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
9287 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
9288 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
9290 genenvfn
= fns
[size
][u
];
9293 case 0xb: /* SQRSHL, UQRSHL */
9295 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
9296 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
9297 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
9298 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
9300 genenvfn
= fns
[size
][u
];
9303 case 0x16: /* SQDMULH, SQRDMULH */
9305 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
9306 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
9307 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
9309 assert(size
== 1 || size
== 2);
9310 genenvfn
= fns
[size
- 1][u
];
9314 g_assert_not_reached();
9317 genenvfn(tcg_rd32
, cpu_env
, tcg_rn
, tcg_rm
);
9318 tcg_gen_extu_i32_i64(tcg_rd
, tcg_rd32
);
9319 tcg_temp_free_i32(tcg_rd32
);
9320 tcg_temp_free_i32(tcg_rn
);
9321 tcg_temp_free_i32(tcg_rm
);
9324 write_fp_dreg(s
, rd
, tcg_rd
);
9326 tcg_temp_free_i64(tcg_rd
);
9329 /* AdvSIMD scalar three same FP16
9330 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
9331 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
9332 * | 0 1 | U | 1 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
9333 * +-----+---+-----------+---+-----+------+-----+--------+---+----+----+
9334 * v: 0101 1110 0100 0000 0000 0100 0000 0000 => 5e400400
9335 * m: 1101 1111 0110 0000 1100 0100 0000 0000 => df60c400
9337 static void disas_simd_scalar_three_reg_same_fp16(DisasContext
*s
,
9340 int rd
= extract32(insn
, 0, 5);
9341 int rn
= extract32(insn
, 5, 5);
9342 int opcode
= extract32(insn
, 11, 3);
9343 int rm
= extract32(insn
, 16, 5);
9344 bool u
= extract32(insn
, 29, 1);
9345 bool a
= extract32(insn
, 23, 1);
9346 int fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
9353 case 0x03: /* FMULX */
9354 case 0x04: /* FCMEQ (reg) */
9355 case 0x07: /* FRECPS */
9356 case 0x0f: /* FRSQRTS */
9357 case 0x14: /* FCMGE (reg) */
9358 case 0x15: /* FACGE */
9359 case 0x1a: /* FABD */
9360 case 0x1c: /* FCMGT (reg) */
9361 case 0x1d: /* FACGT */
9364 unallocated_encoding(s
);
9368 if (!dc_isar_feature(aa64_fp16
, s
)) {
9369 unallocated_encoding(s
);
9372 if (!fp_access_check(s
)) {
9376 fpst
= get_fpstatus_ptr(true);
9378 tcg_op1
= read_fp_hreg(s
, rn
);
9379 tcg_op2
= read_fp_hreg(s
, rm
);
9380 tcg_res
= tcg_temp_new_i32();
9383 case 0x03: /* FMULX */
9384 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9386 case 0x04: /* FCMEQ (reg) */
9387 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9389 case 0x07: /* FRECPS */
9390 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9392 case 0x0f: /* FRSQRTS */
9393 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9395 case 0x14: /* FCMGE (reg) */
9396 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9398 case 0x15: /* FACGE */
9399 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9401 case 0x1a: /* FABD */
9402 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9403 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
9405 case 0x1c: /* FCMGT (reg) */
9406 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9408 case 0x1d: /* FACGT */
9409 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
9412 g_assert_not_reached();
9415 write_fp_sreg(s
, rd
, tcg_res
);
9418 tcg_temp_free_i32(tcg_res
);
9419 tcg_temp_free_i32(tcg_op1
);
9420 tcg_temp_free_i32(tcg_op2
);
9421 tcg_temp_free_ptr(fpst
);
9424 /* AdvSIMD scalar three same extra
9425 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
9426 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
9427 * | 0 1 | U | 1 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
9428 * +-----+---+-----------+------+---+------+---+--------+---+----+----+
9430 static void disas_simd_scalar_three_reg_same_extra(DisasContext
*s
,
9433 int rd
= extract32(insn
, 0, 5);
9434 int rn
= extract32(insn
, 5, 5);
9435 int opcode
= extract32(insn
, 11, 4);
9436 int rm
= extract32(insn
, 16, 5);
9437 int size
= extract32(insn
, 22, 2);
9438 bool u
= extract32(insn
, 29, 1);
9439 TCGv_i32 ele1
, ele2
, ele3
;
9443 switch (u
* 16 + opcode
) {
9444 case 0x10: /* SQRDMLAH (vector) */
9445 case 0x11: /* SQRDMLSH (vector) */
9446 if (size
!= 1 && size
!= 2) {
9447 unallocated_encoding(s
);
9450 feature
= dc_isar_feature(aa64_rdm
, s
);
9453 unallocated_encoding(s
);
9457 unallocated_encoding(s
);
9460 if (!fp_access_check(s
)) {
9464 /* Do a single operation on the lowest element in the vector.
9465 * We use the standard Neon helpers and rely on 0 OP 0 == 0
9466 * with no side effects for all these operations.
9467 * OPTME: special-purpose helpers would avoid doing some
9468 * unnecessary work in the helper for the 16 bit cases.
9470 ele1
= tcg_temp_new_i32();
9471 ele2
= tcg_temp_new_i32();
9472 ele3
= tcg_temp_new_i32();
9474 read_vec_element_i32(s
, ele1
, rn
, 0, size
);
9475 read_vec_element_i32(s
, ele2
, rm
, 0, size
);
9476 read_vec_element_i32(s
, ele3
, rd
, 0, size
);
9479 case 0x0: /* SQRDMLAH */
9481 gen_helper_neon_qrdmlah_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9483 gen_helper_neon_qrdmlah_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9486 case 0x1: /* SQRDMLSH */
9488 gen_helper_neon_qrdmlsh_s16(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9490 gen_helper_neon_qrdmlsh_s32(ele3
, cpu_env
, ele1
, ele2
, ele3
);
9494 g_assert_not_reached();
9496 tcg_temp_free_i32(ele1
);
9497 tcg_temp_free_i32(ele2
);
9499 res
= tcg_temp_new_i64();
9500 tcg_gen_extu_i32_i64(res
, ele3
);
9501 tcg_temp_free_i32(ele3
);
9503 write_fp_dreg(s
, rd
, res
);
9504 tcg_temp_free_i64(res
);
9507 static void handle_2misc_64(DisasContext
*s
, int opcode
, bool u
,
9508 TCGv_i64 tcg_rd
, TCGv_i64 tcg_rn
,
9509 TCGv_i32 tcg_rmode
, TCGv_ptr tcg_fpstatus
)
9511 /* Handle 64->64 opcodes which are shared between the scalar and
9512 * vector 2-reg-misc groups. We cover every integer opcode where size == 3
9513 * is valid in either group and also the double-precision fp ops.
9514 * The caller only need provide tcg_rmode and tcg_fpstatus if the op
9520 case 0x4: /* CLS, CLZ */
9522 tcg_gen_clzi_i64(tcg_rd
, tcg_rn
, 64);
9524 tcg_gen_clrsb_i64(tcg_rd
, tcg_rn
);
9528 /* This opcode is shared with CNT and RBIT but we have earlier
9529 * enforced that size == 3 if and only if this is the NOT insn.
9531 tcg_gen_not_i64(tcg_rd
, tcg_rn
);
9533 case 0x7: /* SQABS, SQNEG */
9535 gen_helper_neon_qneg_s64(tcg_rd
, cpu_env
, tcg_rn
);
9537 gen_helper_neon_qabs_s64(tcg_rd
, cpu_env
, tcg_rn
);
9540 case 0xa: /* CMLT */
9541 /* 64 bit integer comparison against zero, result is
9542 * test ? (2^64 - 1) : 0. We implement via setcond(!test) and
9547 tcg_gen_setcondi_i64(cond
, tcg_rd
, tcg_rn
, 0);
9548 tcg_gen_neg_i64(tcg_rd
, tcg_rd
);
9550 case 0x8: /* CMGT, CMGE */
9551 cond
= u
? TCG_COND_GE
: TCG_COND_GT
;
9553 case 0x9: /* CMEQ, CMLE */
9554 cond
= u
? TCG_COND_LE
: TCG_COND_EQ
;
9556 case 0xb: /* ABS, NEG */
9558 tcg_gen_neg_i64(tcg_rd
, tcg_rn
);
9560 tcg_gen_abs_i64(tcg_rd
, tcg_rn
);
9563 case 0x2f: /* FABS */
9564 gen_helper_vfp_absd(tcg_rd
, tcg_rn
);
9566 case 0x6f: /* FNEG */
9567 gen_helper_vfp_negd(tcg_rd
, tcg_rn
);
9569 case 0x7f: /* FSQRT */
9570 gen_helper_vfp_sqrtd(tcg_rd
, tcg_rn
, cpu_env
);
9572 case 0x1a: /* FCVTNS */
9573 case 0x1b: /* FCVTMS */
9574 case 0x1c: /* FCVTAS */
9575 case 0x3a: /* FCVTPS */
9576 case 0x3b: /* FCVTZS */
9578 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9579 gen_helper_vfp_tosqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9580 tcg_temp_free_i32(tcg_shift
);
9583 case 0x5a: /* FCVTNU */
9584 case 0x5b: /* FCVTMU */
9585 case 0x5c: /* FCVTAU */
9586 case 0x7a: /* FCVTPU */
9587 case 0x7b: /* FCVTZU */
9589 TCGv_i32 tcg_shift
= tcg_const_i32(0);
9590 gen_helper_vfp_touqd(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
9591 tcg_temp_free_i32(tcg_shift
);
9594 case 0x18: /* FRINTN */
9595 case 0x19: /* FRINTM */
9596 case 0x38: /* FRINTP */
9597 case 0x39: /* FRINTZ */
9598 case 0x58: /* FRINTA */
9599 case 0x79: /* FRINTI */
9600 gen_helper_rintd(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9602 case 0x59: /* FRINTX */
9603 gen_helper_rintd_exact(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9605 case 0x1e: /* FRINT32Z */
9606 case 0x5e: /* FRINT32X */
9607 gen_helper_frint32_d(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9609 case 0x1f: /* FRINT64Z */
9610 case 0x5f: /* FRINT64X */
9611 gen_helper_frint64_d(tcg_rd
, tcg_rn
, tcg_fpstatus
);
9614 g_assert_not_reached();
9618 static void handle_2misc_fcmp_zero(DisasContext
*s
, int opcode
,
9619 bool is_scalar
, bool is_u
, bool is_q
,
9620 int size
, int rn
, int rd
)
9622 bool is_double
= (size
== MO_64
);
9625 if (!fp_access_check(s
)) {
9629 fpst
= get_fpstatus_ptr(size
== MO_16
);
9632 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9633 TCGv_i64 tcg_zero
= tcg_const_i64(0);
9634 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9635 NeonGenTwoDoubleOpFn
*genfn
;
9640 case 0x2e: /* FCMLT (zero) */
9643 case 0x2c: /* FCMGT (zero) */
9644 genfn
= gen_helper_neon_cgt_f64
;
9646 case 0x2d: /* FCMEQ (zero) */
9647 genfn
= gen_helper_neon_ceq_f64
;
9649 case 0x6d: /* FCMLE (zero) */
9652 case 0x6c: /* FCMGE (zero) */
9653 genfn
= gen_helper_neon_cge_f64
;
9656 g_assert_not_reached();
9659 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9660 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9662 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
9664 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
9666 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9668 tcg_temp_free_i64(tcg_res
);
9669 tcg_temp_free_i64(tcg_zero
);
9670 tcg_temp_free_i64(tcg_op
);
9672 clear_vec_high(s
, !is_scalar
, rd
);
9674 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9675 TCGv_i32 tcg_zero
= tcg_const_i32(0);
9676 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9677 NeonGenTwoSingleOpFn
*genfn
;
9679 int pass
, maxpasses
;
9681 if (size
== MO_16
) {
9683 case 0x2e: /* FCMLT (zero) */
9686 case 0x2c: /* FCMGT (zero) */
9687 genfn
= gen_helper_advsimd_cgt_f16
;
9689 case 0x2d: /* FCMEQ (zero) */
9690 genfn
= gen_helper_advsimd_ceq_f16
;
9692 case 0x6d: /* FCMLE (zero) */
9695 case 0x6c: /* FCMGE (zero) */
9696 genfn
= gen_helper_advsimd_cge_f16
;
9699 g_assert_not_reached();
9703 case 0x2e: /* FCMLT (zero) */
9706 case 0x2c: /* FCMGT (zero) */
9707 genfn
= gen_helper_neon_cgt_f32
;
9709 case 0x2d: /* FCMEQ (zero) */
9710 genfn
= gen_helper_neon_ceq_f32
;
9712 case 0x6d: /* FCMLE (zero) */
9715 case 0x6c: /* FCMGE (zero) */
9716 genfn
= gen_helper_neon_cge_f32
;
9719 g_assert_not_reached();
9726 int vector_size
= 8 << is_q
;
9727 maxpasses
= vector_size
>> size
;
9730 for (pass
= 0; pass
< maxpasses
; pass
++) {
9731 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
9733 genfn(tcg_res
, tcg_zero
, tcg_op
, fpst
);
9735 genfn(tcg_res
, tcg_op
, tcg_zero
, fpst
);
9738 write_fp_sreg(s
, rd
, tcg_res
);
9740 write_vec_element_i32(s
, tcg_res
, rd
, pass
, size
);
9743 tcg_temp_free_i32(tcg_res
);
9744 tcg_temp_free_i32(tcg_zero
);
9745 tcg_temp_free_i32(tcg_op
);
9747 clear_vec_high(s
, is_q
, rd
);
9751 tcg_temp_free_ptr(fpst
);
9754 static void handle_2misc_reciprocal(DisasContext
*s
, int opcode
,
9755 bool is_scalar
, bool is_u
, bool is_q
,
9756 int size
, int rn
, int rd
)
9758 bool is_double
= (size
== 3);
9759 TCGv_ptr fpst
= get_fpstatus_ptr(false);
9762 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9763 TCGv_i64 tcg_res
= tcg_temp_new_i64();
9766 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9767 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9769 case 0x3d: /* FRECPE */
9770 gen_helper_recpe_f64(tcg_res
, tcg_op
, fpst
);
9772 case 0x3f: /* FRECPX */
9773 gen_helper_frecpx_f64(tcg_res
, tcg_op
, fpst
);
9775 case 0x7d: /* FRSQRTE */
9776 gen_helper_rsqrte_f64(tcg_res
, tcg_op
, fpst
);
9779 g_assert_not_reached();
9781 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
9783 tcg_temp_free_i64(tcg_res
);
9784 tcg_temp_free_i64(tcg_op
);
9785 clear_vec_high(s
, !is_scalar
, rd
);
9787 TCGv_i32 tcg_op
= tcg_temp_new_i32();
9788 TCGv_i32 tcg_res
= tcg_temp_new_i32();
9789 int pass
, maxpasses
;
9794 maxpasses
= is_q
? 4 : 2;
9797 for (pass
= 0; pass
< maxpasses
; pass
++) {
9798 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
9801 case 0x3c: /* URECPE */
9802 gen_helper_recpe_u32(tcg_res
, tcg_op
);
9804 case 0x3d: /* FRECPE */
9805 gen_helper_recpe_f32(tcg_res
, tcg_op
, fpst
);
9807 case 0x3f: /* FRECPX */
9808 gen_helper_frecpx_f32(tcg_res
, tcg_op
, fpst
);
9810 case 0x7d: /* FRSQRTE */
9811 gen_helper_rsqrte_f32(tcg_res
, tcg_op
, fpst
);
9814 g_assert_not_reached();
9818 write_fp_sreg(s
, rd
, tcg_res
);
9820 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
9823 tcg_temp_free_i32(tcg_res
);
9824 tcg_temp_free_i32(tcg_op
);
9826 clear_vec_high(s
, is_q
, rd
);
9829 tcg_temp_free_ptr(fpst
);
9832 static void handle_2misc_narrow(DisasContext
*s
, bool scalar
,
9833 int opcode
, bool u
, bool is_q
,
9834 int size
, int rn
, int rd
)
9836 /* Handle 2-reg-misc ops which are narrowing (so each 2*size element
9837 * in the source becomes a size element in the destination).
9840 TCGv_i32 tcg_res
[2];
9841 int destelt
= is_q
? 2 : 0;
9842 int passes
= scalar
? 1 : 2;
9845 tcg_res
[1] = tcg_const_i32(0);
9848 for (pass
= 0; pass
< passes
; pass
++) {
9849 TCGv_i64 tcg_op
= tcg_temp_new_i64();
9850 NeonGenNarrowFn
*genfn
= NULL
;
9851 NeonGenNarrowEnvFn
*genenvfn
= NULL
;
9854 read_vec_element(s
, tcg_op
, rn
, pass
, size
+ 1);
9856 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
9858 tcg_res
[pass
] = tcg_temp_new_i32();
9861 case 0x12: /* XTN, SQXTUN */
9863 static NeonGenNarrowFn
* const xtnfns
[3] = {
9864 gen_helper_neon_narrow_u8
,
9865 gen_helper_neon_narrow_u16
,
9866 tcg_gen_extrl_i64_i32
,
9868 static NeonGenNarrowEnvFn
* const sqxtunfns
[3] = {
9869 gen_helper_neon_unarrow_sat8
,
9870 gen_helper_neon_unarrow_sat16
,
9871 gen_helper_neon_unarrow_sat32
,
9874 genenvfn
= sqxtunfns
[size
];
9876 genfn
= xtnfns
[size
];
9880 case 0x14: /* SQXTN, UQXTN */
9882 static NeonGenNarrowEnvFn
* const fns
[3][2] = {
9883 { gen_helper_neon_narrow_sat_s8
,
9884 gen_helper_neon_narrow_sat_u8
},
9885 { gen_helper_neon_narrow_sat_s16
,
9886 gen_helper_neon_narrow_sat_u16
},
9887 { gen_helper_neon_narrow_sat_s32
,
9888 gen_helper_neon_narrow_sat_u32
},
9890 genenvfn
= fns
[size
][u
];
9893 case 0x16: /* FCVTN, FCVTN2 */
9894 /* 32 bit to 16 bit or 64 bit to 32 bit float conversion */
9896 gen_helper_vfp_fcvtsd(tcg_res
[pass
], tcg_op
, cpu_env
);
9898 TCGv_i32 tcg_lo
= tcg_temp_new_i32();
9899 TCGv_i32 tcg_hi
= tcg_temp_new_i32();
9900 TCGv_ptr fpst
= get_fpstatus_ptr(false);
9901 TCGv_i32 ahp
= get_ahp_flag();
9903 tcg_gen_extr_i64_i32(tcg_lo
, tcg_hi
, tcg_op
);
9904 gen_helper_vfp_fcvt_f32_to_f16(tcg_lo
, tcg_lo
, fpst
, ahp
);
9905 gen_helper_vfp_fcvt_f32_to_f16(tcg_hi
, tcg_hi
, fpst
, ahp
);
9906 tcg_gen_deposit_i32(tcg_res
[pass
], tcg_lo
, tcg_hi
, 16, 16);
9907 tcg_temp_free_i32(tcg_lo
);
9908 tcg_temp_free_i32(tcg_hi
);
9909 tcg_temp_free_ptr(fpst
);
9910 tcg_temp_free_i32(ahp
);
9913 case 0x56: /* FCVTXN, FCVTXN2 */
9914 /* 64 bit to 32 bit float conversion
9915 * with von Neumann rounding (round to odd)
9918 gen_helper_fcvtx_f64_to_f32(tcg_res
[pass
], tcg_op
, cpu_env
);
9921 g_assert_not_reached();
9925 genfn(tcg_res
[pass
], tcg_op
);
9926 } else if (genenvfn
) {
9927 genenvfn(tcg_res
[pass
], cpu_env
, tcg_op
);
9930 tcg_temp_free_i64(tcg_op
);
9933 for (pass
= 0; pass
< 2; pass
++) {
9934 write_vec_element_i32(s
, tcg_res
[pass
], rd
, destelt
+ pass
, MO_32
);
9935 tcg_temp_free_i32(tcg_res
[pass
]);
9937 clear_vec_high(s
, is_q
, rd
);
9940 /* Remaining saturating accumulating ops */
9941 static void handle_2misc_satacc(DisasContext
*s
, bool is_scalar
, bool is_u
,
9942 bool is_q
, int size
, int rn
, int rd
)
9944 bool is_double
= (size
== 3);
9947 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
9948 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
9951 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
9952 read_vec_element(s
, tcg_rn
, rn
, pass
, MO_64
);
9953 read_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
9955 if (is_u
) { /* USQADD */
9956 gen_helper_neon_uqadd_s64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9957 } else { /* SUQADD */
9958 gen_helper_neon_sqadd_u64(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9960 write_vec_element(s
, tcg_rd
, rd
, pass
, MO_64
);
9962 tcg_temp_free_i64(tcg_rd
);
9963 tcg_temp_free_i64(tcg_rn
);
9964 clear_vec_high(s
, !is_scalar
, rd
);
9966 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
9967 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
9968 int pass
, maxpasses
;
9973 maxpasses
= is_q
? 4 : 2;
9976 for (pass
= 0; pass
< maxpasses
; pass
++) {
9978 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, size
);
9979 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, size
);
9981 read_vec_element_i32(s
, tcg_rn
, rn
, pass
, MO_32
);
9982 read_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
9985 if (is_u
) { /* USQADD */
9988 gen_helper_neon_uqadd_s8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9991 gen_helper_neon_uqadd_s16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9994 gen_helper_neon_uqadd_s32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
9997 g_assert_not_reached();
9999 } else { /* SUQADD */
10002 gen_helper_neon_sqadd_u8(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10005 gen_helper_neon_sqadd_u16(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10008 gen_helper_neon_sqadd_u32(tcg_rd
, cpu_env
, tcg_rn
, tcg_rd
);
10011 g_assert_not_reached();
10016 TCGv_i64 tcg_zero
= tcg_const_i64(0);
10017 write_vec_element(s
, tcg_zero
, rd
, 0, MO_64
);
10018 tcg_temp_free_i64(tcg_zero
);
10020 write_vec_element_i32(s
, tcg_rd
, rd
, pass
, MO_32
);
10022 tcg_temp_free_i32(tcg_rd
);
10023 tcg_temp_free_i32(tcg_rn
);
10024 clear_vec_high(s
, is_q
, rd
);
10028 /* AdvSIMD scalar two reg misc
10029 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
10030 * +-----+---+-----------+------+-----------+--------+-----+------+------+
10031 * | 0 1 | U | 1 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
10032 * +-----+---+-----------+------+-----------+--------+-----+------+------+
10034 static void disas_simd_scalar_two_reg_misc(DisasContext
*s
, uint32_t insn
)
10036 int rd
= extract32(insn
, 0, 5);
10037 int rn
= extract32(insn
, 5, 5);
10038 int opcode
= extract32(insn
, 12, 5);
10039 int size
= extract32(insn
, 22, 2);
10040 bool u
= extract32(insn
, 29, 1);
10041 bool is_fcvt
= false;
10043 TCGv_i32 tcg_rmode
;
10044 TCGv_ptr tcg_fpstatus
;
10047 case 0x3: /* USQADD / SUQADD*/
10048 if (!fp_access_check(s
)) {
10051 handle_2misc_satacc(s
, true, u
, false, size
, rn
, rd
);
10053 case 0x7: /* SQABS / SQNEG */
10055 case 0xa: /* CMLT */
10057 unallocated_encoding(s
);
10061 case 0x8: /* CMGT, CMGE */
10062 case 0x9: /* CMEQ, CMLE */
10063 case 0xb: /* ABS, NEG */
10065 unallocated_encoding(s
);
10069 case 0x12: /* SQXTUN */
10071 unallocated_encoding(s
);
10075 case 0x14: /* SQXTN, UQXTN */
10077 unallocated_encoding(s
);
10080 if (!fp_access_check(s
)) {
10083 handle_2misc_narrow(s
, true, opcode
, u
, false, size
, rn
, rd
);
10086 case 0x16 ... 0x1d:
10088 /* Floating point: U, size[1] and opcode indicate operation;
10089 * size[0] indicates single or double precision.
10091 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
10092 size
= extract32(size
, 0, 1) ? 3 : 2;
10094 case 0x2c: /* FCMGT (zero) */
10095 case 0x2d: /* FCMEQ (zero) */
10096 case 0x2e: /* FCMLT (zero) */
10097 case 0x6c: /* FCMGE (zero) */
10098 case 0x6d: /* FCMLE (zero) */
10099 handle_2misc_fcmp_zero(s
, opcode
, true, u
, true, size
, rn
, rd
);
10101 case 0x1d: /* SCVTF */
10102 case 0x5d: /* UCVTF */
10104 bool is_signed
= (opcode
== 0x1d);
10105 if (!fp_access_check(s
)) {
10108 handle_simd_intfp_conv(s
, rd
, rn
, 1, is_signed
, 0, size
);
10111 case 0x3d: /* FRECPE */
10112 case 0x3f: /* FRECPX */
10113 case 0x7d: /* FRSQRTE */
10114 if (!fp_access_check(s
)) {
10117 handle_2misc_reciprocal(s
, opcode
, true, u
, true, size
, rn
, rd
);
10119 case 0x1a: /* FCVTNS */
10120 case 0x1b: /* FCVTMS */
10121 case 0x3a: /* FCVTPS */
10122 case 0x3b: /* FCVTZS */
10123 case 0x5a: /* FCVTNU */
10124 case 0x5b: /* FCVTMU */
10125 case 0x7a: /* FCVTPU */
10126 case 0x7b: /* FCVTZU */
10128 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
10130 case 0x1c: /* FCVTAS */
10131 case 0x5c: /* FCVTAU */
10132 /* TIEAWAY doesn't fit in the usual rounding mode encoding */
10134 rmode
= FPROUNDING_TIEAWAY
;
10136 case 0x56: /* FCVTXN, FCVTXN2 */
10138 unallocated_encoding(s
);
10141 if (!fp_access_check(s
)) {
10144 handle_2misc_narrow(s
, true, opcode
, u
, false, size
- 1, rn
, rd
);
10147 unallocated_encoding(s
);
10152 unallocated_encoding(s
);
10156 if (!fp_access_check(s
)) {
10161 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
10162 tcg_fpstatus
= get_fpstatus_ptr(false);
10163 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
10166 tcg_fpstatus
= NULL
;
10170 TCGv_i64 tcg_rn
= read_fp_dreg(s
, rn
);
10171 TCGv_i64 tcg_rd
= tcg_temp_new_i64();
10173 handle_2misc_64(s
, opcode
, u
, tcg_rd
, tcg_rn
, tcg_rmode
, tcg_fpstatus
);
10174 write_fp_dreg(s
, rd
, tcg_rd
);
10175 tcg_temp_free_i64(tcg_rd
);
10176 tcg_temp_free_i64(tcg_rn
);
10178 TCGv_i32 tcg_rn
= tcg_temp_new_i32();
10179 TCGv_i32 tcg_rd
= tcg_temp_new_i32();
10181 read_vec_element_i32(s
, tcg_rn
, rn
, 0, size
);
10184 case 0x7: /* SQABS, SQNEG */
10186 NeonGenOneOpEnvFn
*genfn
;
10187 static NeonGenOneOpEnvFn
* const fns
[3][2] = {
10188 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
10189 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
10190 { gen_helper_neon_qabs_s32
, gen_helper_neon_qneg_s32
},
10192 genfn
= fns
[size
][u
];
10193 genfn(tcg_rd
, cpu_env
, tcg_rn
);
10196 case 0x1a: /* FCVTNS */
10197 case 0x1b: /* FCVTMS */
10198 case 0x1c: /* FCVTAS */
10199 case 0x3a: /* FCVTPS */
10200 case 0x3b: /* FCVTZS */
10202 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10203 gen_helper_vfp_tosls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
10204 tcg_temp_free_i32(tcg_shift
);
10207 case 0x5a: /* FCVTNU */
10208 case 0x5b: /* FCVTMU */
10209 case 0x5c: /* FCVTAU */
10210 case 0x7a: /* FCVTPU */
10211 case 0x7b: /* FCVTZU */
10213 TCGv_i32 tcg_shift
= tcg_const_i32(0);
10214 gen_helper_vfp_touls(tcg_rd
, tcg_rn
, tcg_shift
, tcg_fpstatus
);
10215 tcg_temp_free_i32(tcg_shift
);
10219 g_assert_not_reached();
10222 write_fp_sreg(s
, rd
, tcg_rd
);
10223 tcg_temp_free_i32(tcg_rd
);
10224 tcg_temp_free_i32(tcg_rn
);
10228 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
10229 tcg_temp_free_i32(tcg_rmode
);
10230 tcg_temp_free_ptr(tcg_fpstatus
);
10234 /* SSHR[RA]/USHR[RA] - Vector shift right (optional rounding/accumulate) */
10235 static void handle_vec_simd_shri(DisasContext
*s
, bool is_q
, bool is_u
,
10236 int immh
, int immb
, int opcode
, int rn
, int rd
)
10238 int size
= 32 - clz32(immh
) - 1;
10239 int immhb
= immh
<< 3 | immb
;
10240 int shift
= 2 * (8 << size
) - immhb
;
10241 GVecGen2iFn
*gvec_fn
;
10243 if (extract32(immh
, 3, 1) && !is_q
) {
10244 unallocated_encoding(s
);
10247 tcg_debug_assert(size
<= 3);
10249 if (!fp_access_check(s
)) {
10254 case 0x02: /* SSRA / USRA (accumulate) */
10255 gvec_fn
= is_u
? gen_gvec_usra
: gen_gvec_ssra
;
10258 case 0x08: /* SRI */
10259 gvec_fn
= gen_gvec_sri
;
10262 case 0x00: /* SSHR / USHR */
10264 if (shift
== 8 << size
) {
10265 /* Shift count the same size as element size produces zero. */
10266 tcg_gen_gvec_dup_imm(size
, vec_full_reg_offset(s
, rd
),
10267 is_q
? 16 : 8, vec_full_reg_size(s
), 0);
10270 gvec_fn
= tcg_gen_gvec_shri
;
10272 /* Shift count the same size as element size produces all sign. */
10273 if (shift
== 8 << size
) {
10276 gvec_fn
= tcg_gen_gvec_sari
;
10280 case 0x04: /* SRSHR / URSHR (rounding) */
10281 gvec_fn
= is_u
? gen_gvec_urshr
: gen_gvec_srshr
;
10284 case 0x06: /* SRSRA / URSRA (accum + rounding) */
10285 gvec_fn
= is_u
? gen_gvec_ursra
: gen_gvec_srsra
;
10289 g_assert_not_reached();
10292 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, gvec_fn
, size
);
10295 /* SHL/SLI - Vector shift left */
10296 static void handle_vec_simd_shli(DisasContext
*s
, bool is_q
, bool insert
,
10297 int immh
, int immb
, int opcode
, int rn
, int rd
)
10299 int size
= 32 - clz32(immh
) - 1;
10300 int immhb
= immh
<< 3 | immb
;
10301 int shift
= immhb
- (8 << size
);
10303 /* Range of size is limited by decode: immh is a non-zero 4 bit field */
10304 assert(size
>= 0 && size
<= 3);
10306 if (extract32(immh
, 3, 1) && !is_q
) {
10307 unallocated_encoding(s
);
10311 if (!fp_access_check(s
)) {
10316 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, gen_gvec_sli
, size
);
10318 gen_gvec_fn2i(s
, is_q
, rd
, rn
, shift
, tcg_gen_gvec_shli
, size
);
10322 /* USHLL/SHLL - Vector shift left with widening */
10323 static void handle_vec_simd_wshli(DisasContext
*s
, bool is_q
, bool is_u
,
10324 int immh
, int immb
, int opcode
, int rn
, int rd
)
10326 int size
= 32 - clz32(immh
) - 1;
10327 int immhb
= immh
<< 3 | immb
;
10328 int shift
= immhb
- (8 << size
);
10330 int esize
= 8 << size
;
10331 int elements
= dsize
/esize
;
10332 TCGv_i64 tcg_rn
= new_tmp_a64(s
);
10333 TCGv_i64 tcg_rd
= new_tmp_a64(s
);
10337 unallocated_encoding(s
);
10341 if (!fp_access_check(s
)) {
10345 /* For the LL variants the store is larger than the load,
10346 * so if rd == rn we would overwrite parts of our input.
10347 * So load everything right now and use shifts in the main loop.
10349 read_vec_element(s
, tcg_rn
, rn
, is_q
? 1 : 0, MO_64
);
10351 for (i
= 0; i
< elements
; i
++) {
10352 tcg_gen_shri_i64(tcg_rd
, tcg_rn
, i
* esize
);
10353 ext_and_shift_reg(tcg_rd
, tcg_rd
, size
| (!is_u
<< 2), 0);
10354 tcg_gen_shli_i64(tcg_rd
, tcg_rd
, shift
);
10355 write_vec_element(s
, tcg_rd
, rd
, i
, size
+ 1);
10359 /* SHRN/RSHRN - Shift right with narrowing (and potential rounding) */
10360 static void handle_vec_simd_shrn(DisasContext
*s
, bool is_q
,
10361 int immh
, int immb
, int opcode
, int rn
, int rd
)
10363 int immhb
= immh
<< 3 | immb
;
10364 int size
= 32 - clz32(immh
) - 1;
10366 int esize
= 8 << size
;
10367 int elements
= dsize
/esize
;
10368 int shift
= (2 * esize
) - immhb
;
10369 bool round
= extract32(opcode
, 0, 1);
10370 TCGv_i64 tcg_rn
, tcg_rd
, tcg_final
;
10371 TCGv_i64 tcg_round
;
10374 if (extract32(immh
, 3, 1)) {
10375 unallocated_encoding(s
);
10379 if (!fp_access_check(s
)) {
10383 tcg_rn
= tcg_temp_new_i64();
10384 tcg_rd
= tcg_temp_new_i64();
10385 tcg_final
= tcg_temp_new_i64();
10386 read_vec_element(s
, tcg_final
, rd
, is_q
? 1 : 0, MO_64
);
10389 uint64_t round_const
= 1ULL << (shift
- 1);
10390 tcg_round
= tcg_const_i64(round_const
);
10395 for (i
= 0; i
< elements
; i
++) {
10396 read_vec_element(s
, tcg_rn
, rn
, i
, size
+1);
10397 handle_shri_with_rndacc(tcg_rd
, tcg_rn
, tcg_round
,
10398 false, true, size
+1, shift
);
10400 tcg_gen_deposit_i64(tcg_final
, tcg_final
, tcg_rd
, esize
* i
, esize
);
10404 write_vec_element(s
, tcg_final
, rd
, 0, MO_64
);
10406 write_vec_element(s
, tcg_final
, rd
, 1, MO_64
);
10409 tcg_temp_free_i64(tcg_round
);
10411 tcg_temp_free_i64(tcg_rn
);
10412 tcg_temp_free_i64(tcg_rd
);
10413 tcg_temp_free_i64(tcg_final
);
10415 clear_vec_high(s
, is_q
, rd
);
10419 /* AdvSIMD shift by immediate
10420 * 31 30 29 28 23 22 19 18 16 15 11 10 9 5 4 0
10421 * +---+---+---+-------------+------+------+--------+---+------+------+
10422 * | 0 | Q | U | 0 1 1 1 1 0 | immh | immb | opcode | 1 | Rn | Rd |
10423 * +---+---+---+-------------+------+------+--------+---+------+------+
10425 static void disas_simd_shift_imm(DisasContext
*s
, uint32_t insn
)
10427 int rd
= extract32(insn
, 0, 5);
10428 int rn
= extract32(insn
, 5, 5);
10429 int opcode
= extract32(insn
, 11, 5);
10430 int immb
= extract32(insn
, 16, 3);
10431 int immh
= extract32(insn
, 19, 4);
10432 bool is_u
= extract32(insn
, 29, 1);
10433 bool is_q
= extract32(insn
, 30, 1);
10435 /* data_proc_simd[] has sent immh == 0 to disas_simd_mod_imm. */
10439 case 0x08: /* SRI */
10441 unallocated_encoding(s
);
10445 case 0x00: /* SSHR / USHR */
10446 case 0x02: /* SSRA / USRA (accumulate) */
10447 case 0x04: /* SRSHR / URSHR (rounding) */
10448 case 0x06: /* SRSRA / URSRA (accum + rounding) */
10449 handle_vec_simd_shri(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10451 case 0x0a: /* SHL / SLI */
10452 handle_vec_simd_shli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10454 case 0x10: /* SHRN */
10455 case 0x11: /* RSHRN / SQRSHRUN */
10457 handle_vec_simd_sqshrn(s
, false, is_q
, false, true, immh
, immb
,
10460 handle_vec_simd_shrn(s
, is_q
, immh
, immb
, opcode
, rn
, rd
);
10463 case 0x12: /* SQSHRN / UQSHRN */
10464 case 0x13: /* SQRSHRN / UQRSHRN */
10465 handle_vec_simd_sqshrn(s
, false, is_q
, is_u
, is_u
, immh
, immb
,
10468 case 0x14: /* SSHLL / USHLL */
10469 handle_vec_simd_wshli(s
, is_q
, is_u
, immh
, immb
, opcode
, rn
, rd
);
10471 case 0x1c: /* SCVTF / UCVTF */
10472 handle_simd_shift_intfp_conv(s
, false, is_q
, is_u
, immh
, immb
,
10475 case 0xc: /* SQSHLU */
10477 unallocated_encoding(s
);
10480 handle_simd_qshl(s
, false, is_q
, false, true, immh
, immb
, rn
, rd
);
10482 case 0xe: /* SQSHL, UQSHL */
10483 handle_simd_qshl(s
, false, is_q
, is_u
, is_u
, immh
, immb
, rn
, rd
);
10485 case 0x1f: /* FCVTZS/ FCVTZU */
10486 handle_simd_shift_fpint_conv(s
, false, is_q
, is_u
, immh
, immb
, rn
, rd
);
10489 unallocated_encoding(s
);
10494 /* Generate code to do a "long" addition or subtraction, ie one done in
10495 * TCGv_i64 on vector lanes twice the width specified by size.
10497 static void gen_neon_addl(int size
, bool is_sub
, TCGv_i64 tcg_res
,
10498 TCGv_i64 tcg_op1
, TCGv_i64 tcg_op2
)
10500 static NeonGenTwo64OpFn
* const fns
[3][2] = {
10501 { gen_helper_neon_addl_u16
, gen_helper_neon_subl_u16
},
10502 { gen_helper_neon_addl_u32
, gen_helper_neon_subl_u32
},
10503 { tcg_gen_add_i64
, tcg_gen_sub_i64
},
10505 NeonGenTwo64OpFn
*genfn
;
10508 genfn
= fns
[size
][is_sub
];
10509 genfn(tcg_res
, tcg_op1
, tcg_op2
);
10512 static void handle_3rd_widening(DisasContext
*s
, int is_q
, int is_u
, int size
,
10513 int opcode
, int rd
, int rn
, int rm
)
10515 /* 3-reg-different widening insns: 64 x 64 -> 128 */
10516 TCGv_i64 tcg_res
[2];
10519 tcg_res
[0] = tcg_temp_new_i64();
10520 tcg_res
[1] = tcg_temp_new_i64();
10522 /* Does this op do an adding accumulate, a subtracting accumulate,
10523 * or no accumulate at all?
10541 read_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
10542 read_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
10545 /* size == 2 means two 32x32->64 operations; this is worth special
10546 * casing because we can generally handle it inline.
10549 for (pass
= 0; pass
< 2; pass
++) {
10550 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10551 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10552 TCGv_i64 tcg_passres
;
10553 MemOp memop
= MO_32
| (is_u
? 0 : MO_SIGN
);
10555 int elt
= pass
+ is_q
* 2;
10557 read_vec_element(s
, tcg_op1
, rn
, elt
, memop
);
10558 read_vec_element(s
, tcg_op2
, rm
, elt
, memop
);
10561 tcg_passres
= tcg_res
[pass
];
10563 tcg_passres
= tcg_temp_new_i64();
10567 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10568 tcg_gen_add_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10570 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10571 tcg_gen_sub_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10573 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10574 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10576 TCGv_i64 tcg_tmp1
= tcg_temp_new_i64();
10577 TCGv_i64 tcg_tmp2
= tcg_temp_new_i64();
10579 tcg_gen_sub_i64(tcg_tmp1
, tcg_op1
, tcg_op2
);
10580 tcg_gen_sub_i64(tcg_tmp2
, tcg_op2
, tcg_op1
);
10581 tcg_gen_movcond_i64(is_u
? TCG_COND_GEU
: TCG_COND_GE
,
10583 tcg_op1
, tcg_op2
, tcg_tmp1
, tcg_tmp2
);
10584 tcg_temp_free_i64(tcg_tmp1
);
10585 tcg_temp_free_i64(tcg_tmp2
);
10588 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10589 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10590 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
10591 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10593 case 9: /* SQDMLAL, SQDMLAL2 */
10594 case 11: /* SQDMLSL, SQDMLSL2 */
10595 case 13: /* SQDMULL, SQDMULL2 */
10596 tcg_gen_mul_i64(tcg_passres
, tcg_op1
, tcg_op2
);
10597 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
10598 tcg_passres
, tcg_passres
);
10601 g_assert_not_reached();
10604 if (opcode
== 9 || opcode
== 11) {
10605 /* saturating accumulate ops */
10607 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
10609 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
10610 tcg_res
[pass
], tcg_passres
);
10611 } else if (accop
> 0) {
10612 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10613 } else if (accop
< 0) {
10614 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
10618 tcg_temp_free_i64(tcg_passres
);
10621 tcg_temp_free_i64(tcg_op1
);
10622 tcg_temp_free_i64(tcg_op2
);
10625 /* size 0 or 1, generally helper functions */
10626 for (pass
= 0; pass
< 2; pass
++) {
10627 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
10628 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10629 TCGv_i64 tcg_passres
;
10630 int elt
= pass
+ is_q
* 2;
10632 read_vec_element_i32(s
, tcg_op1
, rn
, elt
, MO_32
);
10633 read_vec_element_i32(s
, tcg_op2
, rm
, elt
, MO_32
);
10636 tcg_passres
= tcg_res
[pass
];
10638 tcg_passres
= tcg_temp_new_i64();
10642 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10643 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10645 TCGv_i64 tcg_op2_64
= tcg_temp_new_i64();
10646 static NeonGenWidenFn
* const widenfns
[2][2] = {
10647 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
10648 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
10650 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
10652 widenfn(tcg_op2_64
, tcg_op2
);
10653 widenfn(tcg_passres
, tcg_op1
);
10654 gen_neon_addl(size
, (opcode
== 2), tcg_passres
,
10655 tcg_passres
, tcg_op2_64
);
10656 tcg_temp_free_i64(tcg_op2_64
);
10659 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10660 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10663 gen_helper_neon_abdl_u16(tcg_passres
, tcg_op1
, tcg_op2
);
10665 gen_helper_neon_abdl_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10669 gen_helper_neon_abdl_u32(tcg_passres
, tcg_op1
, tcg_op2
);
10671 gen_helper_neon_abdl_s32(tcg_passres
, tcg_op1
, tcg_op2
);
10675 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10676 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10677 case 12: /* UMULL, UMULL2, SMULL, SMULL2 */
10680 gen_helper_neon_mull_u8(tcg_passres
, tcg_op1
, tcg_op2
);
10682 gen_helper_neon_mull_s8(tcg_passres
, tcg_op1
, tcg_op2
);
10686 gen_helper_neon_mull_u16(tcg_passres
, tcg_op1
, tcg_op2
);
10688 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10692 case 9: /* SQDMLAL, SQDMLAL2 */
10693 case 11: /* SQDMLSL, SQDMLSL2 */
10694 case 13: /* SQDMULL, SQDMULL2 */
10696 gen_helper_neon_mull_s16(tcg_passres
, tcg_op1
, tcg_op2
);
10697 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
10698 tcg_passres
, tcg_passres
);
10701 g_assert_not_reached();
10703 tcg_temp_free_i32(tcg_op1
);
10704 tcg_temp_free_i32(tcg_op2
);
10707 if (opcode
== 9 || opcode
== 11) {
10708 /* saturating accumulate ops */
10710 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
10712 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
10716 gen_neon_addl(size
, (accop
< 0), tcg_res
[pass
],
10717 tcg_res
[pass
], tcg_passres
);
10719 tcg_temp_free_i64(tcg_passres
);
10724 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
10725 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
10726 tcg_temp_free_i64(tcg_res
[0]);
10727 tcg_temp_free_i64(tcg_res
[1]);
10730 static void handle_3rd_wide(DisasContext
*s
, int is_q
, int is_u
, int size
,
10731 int opcode
, int rd
, int rn
, int rm
)
10733 TCGv_i64 tcg_res
[2];
10734 int part
= is_q
? 2 : 0;
10737 for (pass
= 0; pass
< 2; pass
++) {
10738 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10739 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
10740 TCGv_i64 tcg_op2_wide
= tcg_temp_new_i64();
10741 static NeonGenWidenFn
* const widenfns
[3][2] = {
10742 { gen_helper_neon_widen_s8
, gen_helper_neon_widen_u8
},
10743 { gen_helper_neon_widen_s16
, gen_helper_neon_widen_u16
},
10744 { tcg_gen_ext_i32_i64
, tcg_gen_extu_i32_i64
},
10746 NeonGenWidenFn
*widenfn
= widenfns
[size
][is_u
];
10748 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
10749 read_vec_element_i32(s
, tcg_op2
, rm
, part
+ pass
, MO_32
);
10750 widenfn(tcg_op2_wide
, tcg_op2
);
10751 tcg_temp_free_i32(tcg_op2
);
10752 tcg_res
[pass
] = tcg_temp_new_i64();
10753 gen_neon_addl(size
, (opcode
== 3),
10754 tcg_res
[pass
], tcg_op1
, tcg_op2_wide
);
10755 tcg_temp_free_i64(tcg_op1
);
10756 tcg_temp_free_i64(tcg_op2_wide
);
10759 for (pass
= 0; pass
< 2; pass
++) {
10760 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
10761 tcg_temp_free_i64(tcg_res
[pass
]);
10765 static void do_narrow_round_high_u32(TCGv_i32 res
, TCGv_i64 in
)
10767 tcg_gen_addi_i64(in
, in
, 1U << 31);
10768 tcg_gen_extrh_i64_i32(res
, in
);
10771 static void handle_3rd_narrowing(DisasContext
*s
, int is_q
, int is_u
, int size
,
10772 int opcode
, int rd
, int rn
, int rm
)
10774 TCGv_i32 tcg_res
[2];
10775 int part
= is_q
? 2 : 0;
10778 for (pass
= 0; pass
< 2; pass
++) {
10779 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
10780 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
10781 TCGv_i64 tcg_wideres
= tcg_temp_new_i64();
10782 static NeonGenNarrowFn
* const narrowfns
[3][2] = {
10783 { gen_helper_neon_narrow_high_u8
,
10784 gen_helper_neon_narrow_round_high_u8
},
10785 { gen_helper_neon_narrow_high_u16
,
10786 gen_helper_neon_narrow_round_high_u16
},
10787 { tcg_gen_extrh_i64_i32
, do_narrow_round_high_u32
},
10789 NeonGenNarrowFn
*gennarrow
= narrowfns
[size
][is_u
];
10791 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
10792 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
10794 gen_neon_addl(size
, (opcode
== 6), tcg_wideres
, tcg_op1
, tcg_op2
);
10796 tcg_temp_free_i64(tcg_op1
);
10797 tcg_temp_free_i64(tcg_op2
);
10799 tcg_res
[pass
] = tcg_temp_new_i32();
10800 gennarrow(tcg_res
[pass
], tcg_wideres
);
10801 tcg_temp_free_i64(tcg_wideres
);
10804 for (pass
= 0; pass
< 2; pass
++) {
10805 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
+ part
, MO_32
);
10806 tcg_temp_free_i32(tcg_res
[pass
]);
10808 clear_vec_high(s
, is_q
, rd
);
10811 /* AdvSIMD three different
10812 * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0
10813 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
10814 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 0 0 | Rn | Rd |
10815 * +---+---+---+-----------+------+---+------+--------+-----+------+------+
10817 static void disas_simd_three_reg_diff(DisasContext
*s
, uint32_t insn
)
10819 /* Instructions in this group fall into three basic classes
10820 * (in each case with the operation working on each element in
10821 * the input vectors):
10822 * (1) widening 64 x 64 -> 128 (with possibly Vd as an extra
10824 * (2) wide 64 x 128 -> 128
10825 * (3) narrowing 128 x 128 -> 64
10826 * Here we do initial decode, catch unallocated cases and
10827 * dispatch to separate functions for each class.
10829 int is_q
= extract32(insn
, 30, 1);
10830 int is_u
= extract32(insn
, 29, 1);
10831 int size
= extract32(insn
, 22, 2);
10832 int opcode
= extract32(insn
, 12, 4);
10833 int rm
= extract32(insn
, 16, 5);
10834 int rn
= extract32(insn
, 5, 5);
10835 int rd
= extract32(insn
, 0, 5);
10838 case 1: /* SADDW, SADDW2, UADDW, UADDW2 */
10839 case 3: /* SSUBW, SSUBW2, USUBW, USUBW2 */
10840 /* 64 x 128 -> 128 */
10842 unallocated_encoding(s
);
10845 if (!fp_access_check(s
)) {
10848 handle_3rd_wide(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10850 case 4: /* ADDHN, ADDHN2, RADDHN, RADDHN2 */
10851 case 6: /* SUBHN, SUBHN2, RSUBHN, RSUBHN2 */
10852 /* 128 x 128 -> 64 */
10854 unallocated_encoding(s
);
10857 if (!fp_access_check(s
)) {
10860 handle_3rd_narrowing(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10862 case 14: /* PMULL, PMULL2 */
10864 unallocated_encoding(s
);
10868 case 0: /* PMULL.P8 */
10869 if (!fp_access_check(s
)) {
10872 /* The Q field specifies lo/hi half input for this insn. */
10873 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, is_q
,
10874 gen_helper_neon_pmull_h
);
10877 case 3: /* PMULL.P64 */
10878 if (!dc_isar_feature(aa64_pmull
, s
)) {
10879 unallocated_encoding(s
);
10882 if (!fp_access_check(s
)) {
10885 /* The Q field specifies lo/hi half input for this insn. */
10886 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, is_q
,
10887 gen_helper_gvec_pmull_q
);
10891 unallocated_encoding(s
);
10895 case 9: /* SQDMLAL, SQDMLAL2 */
10896 case 11: /* SQDMLSL, SQDMLSL2 */
10897 case 13: /* SQDMULL, SQDMULL2 */
10898 if (is_u
|| size
== 0) {
10899 unallocated_encoding(s
);
10903 case 0: /* SADDL, SADDL2, UADDL, UADDL2 */
10904 case 2: /* SSUBL, SSUBL2, USUBL, USUBL2 */
10905 case 5: /* SABAL, SABAL2, UABAL, UABAL2 */
10906 case 7: /* SABDL, SABDL2, UABDL, UABDL2 */
10907 case 8: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
10908 case 10: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
10909 case 12: /* SMULL, SMULL2, UMULL, UMULL2 */
10910 /* 64 x 64 -> 128 */
10912 unallocated_encoding(s
);
10915 if (!fp_access_check(s
)) {
10919 handle_3rd_widening(s
, is_q
, is_u
, size
, opcode
, rd
, rn
, rm
);
10922 /* opcode 15 not allocated */
10923 unallocated_encoding(s
);
10928 /* Logic op (opcode == 3) subgroup of C3.6.16. */
10929 static void disas_simd_3same_logic(DisasContext
*s
, uint32_t insn
)
10931 int rd
= extract32(insn
, 0, 5);
10932 int rn
= extract32(insn
, 5, 5);
10933 int rm
= extract32(insn
, 16, 5);
10934 int size
= extract32(insn
, 22, 2);
10935 bool is_u
= extract32(insn
, 29, 1);
10936 bool is_q
= extract32(insn
, 30, 1);
10938 if (!fp_access_check(s
)) {
10942 switch (size
+ 4 * is_u
) {
10944 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_and
, 0);
10947 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_andc
, 0);
10950 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_or
, 0);
10953 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_orc
, 0);
10956 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_xor
, 0);
10959 case 5: /* BSL bitwise select */
10960 gen_gvec_fn4(s
, is_q
, rd
, rd
, rn
, rm
, tcg_gen_gvec_bitsel
, 0);
10962 case 6: /* BIT, bitwise insert if true */
10963 gen_gvec_fn4(s
, is_q
, rd
, rm
, rn
, rd
, tcg_gen_gvec_bitsel
, 0);
10965 case 7: /* BIF, bitwise insert if false */
10966 gen_gvec_fn4(s
, is_q
, rd
, rm
, rd
, rn
, tcg_gen_gvec_bitsel
, 0);
10970 g_assert_not_reached();
10974 /* Pairwise op subgroup of C3.6.16.
10976 * This is called directly or via the handle_3same_float for float pairwise
10977 * operations where the opcode and size are calculated differently.
10979 static void handle_simd_3same_pair(DisasContext
*s
, int is_q
, int u
, int opcode
,
10980 int size
, int rn
, int rm
, int rd
)
10985 /* Floating point operations need fpst */
10986 if (opcode
>= 0x58) {
10987 fpst
= get_fpstatus_ptr(false);
10992 if (!fp_access_check(s
)) {
10996 /* These operations work on the concatenated rm:rn, with each pair of
10997 * adjacent elements being operated on to produce an element in the result.
11000 TCGv_i64 tcg_res
[2];
11002 for (pass
= 0; pass
< 2; pass
++) {
11003 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11004 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11005 int passreg
= (pass
== 0) ? rn
: rm
;
11007 read_vec_element(s
, tcg_op1
, passreg
, 0, MO_64
);
11008 read_vec_element(s
, tcg_op2
, passreg
, 1, MO_64
);
11009 tcg_res
[pass
] = tcg_temp_new_i64();
11012 case 0x17: /* ADDP */
11013 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
11015 case 0x58: /* FMAXNMP */
11016 gen_helper_vfp_maxnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11018 case 0x5a: /* FADDP */
11019 gen_helper_vfp_addd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11021 case 0x5e: /* FMAXP */
11022 gen_helper_vfp_maxd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11024 case 0x78: /* FMINNMP */
11025 gen_helper_vfp_minnumd(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11027 case 0x7e: /* FMINP */
11028 gen_helper_vfp_mind(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11031 g_assert_not_reached();
11034 tcg_temp_free_i64(tcg_op1
);
11035 tcg_temp_free_i64(tcg_op2
);
11038 for (pass
= 0; pass
< 2; pass
++) {
11039 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11040 tcg_temp_free_i64(tcg_res
[pass
]);
11043 int maxpass
= is_q
? 4 : 2;
11044 TCGv_i32 tcg_res
[4];
11046 for (pass
= 0; pass
< maxpass
; pass
++) {
11047 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11048 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11049 NeonGenTwoOpFn
*genfn
= NULL
;
11050 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
11051 int passelt
= (is_q
&& (pass
& 1)) ? 2 : 0;
11053 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_32
);
11054 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_32
);
11055 tcg_res
[pass
] = tcg_temp_new_i32();
11058 case 0x17: /* ADDP */
11060 static NeonGenTwoOpFn
* const fns
[3] = {
11061 gen_helper_neon_padd_u8
,
11062 gen_helper_neon_padd_u16
,
11068 case 0x14: /* SMAXP, UMAXP */
11070 static NeonGenTwoOpFn
* const fns
[3][2] = {
11071 { gen_helper_neon_pmax_s8
, gen_helper_neon_pmax_u8
},
11072 { gen_helper_neon_pmax_s16
, gen_helper_neon_pmax_u16
},
11073 { tcg_gen_smax_i32
, tcg_gen_umax_i32
},
11075 genfn
= fns
[size
][u
];
11078 case 0x15: /* SMINP, UMINP */
11080 static NeonGenTwoOpFn
* const fns
[3][2] = {
11081 { gen_helper_neon_pmin_s8
, gen_helper_neon_pmin_u8
},
11082 { gen_helper_neon_pmin_s16
, gen_helper_neon_pmin_u16
},
11083 { tcg_gen_smin_i32
, tcg_gen_umin_i32
},
11085 genfn
= fns
[size
][u
];
11088 /* The FP operations are all on single floats (32 bit) */
11089 case 0x58: /* FMAXNMP */
11090 gen_helper_vfp_maxnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11092 case 0x5a: /* FADDP */
11093 gen_helper_vfp_adds(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11095 case 0x5e: /* FMAXP */
11096 gen_helper_vfp_maxs(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11098 case 0x78: /* FMINNMP */
11099 gen_helper_vfp_minnums(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11101 case 0x7e: /* FMINP */
11102 gen_helper_vfp_mins(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11105 g_assert_not_reached();
11108 /* FP ops called directly, otherwise call now */
11110 genfn(tcg_res
[pass
], tcg_op1
, tcg_op2
);
11113 tcg_temp_free_i32(tcg_op1
);
11114 tcg_temp_free_i32(tcg_op2
);
11117 for (pass
= 0; pass
< maxpass
; pass
++) {
11118 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
11119 tcg_temp_free_i32(tcg_res
[pass
]);
11121 clear_vec_high(s
, is_q
, rd
);
11125 tcg_temp_free_ptr(fpst
);
11129 /* Floating point op subgroup of C3.6.16. */
11130 static void disas_simd_3same_float(DisasContext
*s
, uint32_t insn
)
11132 /* For floating point ops, the U, size[1] and opcode bits
11133 * together indicate the operation. size[0] indicates single
11136 int fpopcode
= extract32(insn
, 11, 5)
11137 | (extract32(insn
, 23, 1) << 5)
11138 | (extract32(insn
, 29, 1) << 6);
11139 int is_q
= extract32(insn
, 30, 1);
11140 int size
= extract32(insn
, 22, 1);
11141 int rm
= extract32(insn
, 16, 5);
11142 int rn
= extract32(insn
, 5, 5);
11143 int rd
= extract32(insn
, 0, 5);
11145 int datasize
= is_q
? 128 : 64;
11146 int esize
= 32 << size
;
11147 int elements
= datasize
/ esize
;
11149 if (size
== 1 && !is_q
) {
11150 unallocated_encoding(s
);
11154 switch (fpopcode
) {
11155 case 0x58: /* FMAXNMP */
11156 case 0x5a: /* FADDP */
11157 case 0x5e: /* FMAXP */
11158 case 0x78: /* FMINNMP */
11159 case 0x7e: /* FMINP */
11160 if (size
&& !is_q
) {
11161 unallocated_encoding(s
);
11164 handle_simd_3same_pair(s
, is_q
, 0, fpopcode
, size
? MO_64
: MO_32
,
11167 case 0x1b: /* FMULX */
11168 case 0x1f: /* FRECPS */
11169 case 0x3f: /* FRSQRTS */
11170 case 0x5d: /* FACGE */
11171 case 0x7d: /* FACGT */
11172 case 0x19: /* FMLA */
11173 case 0x39: /* FMLS */
11174 case 0x18: /* FMAXNM */
11175 case 0x1a: /* FADD */
11176 case 0x1c: /* FCMEQ */
11177 case 0x1e: /* FMAX */
11178 case 0x38: /* FMINNM */
11179 case 0x3a: /* FSUB */
11180 case 0x3e: /* FMIN */
11181 case 0x5b: /* FMUL */
11182 case 0x5c: /* FCMGE */
11183 case 0x5f: /* FDIV */
11184 case 0x7a: /* FABD */
11185 case 0x7c: /* FCMGT */
11186 if (!fp_access_check(s
)) {
11189 handle_3same_float(s
, size
, elements
, fpopcode
, rd
, rn
, rm
);
11192 case 0x1d: /* FMLAL */
11193 case 0x3d: /* FMLSL */
11194 case 0x59: /* FMLAL2 */
11195 case 0x79: /* FMLSL2 */
11196 if (size
& 1 || !dc_isar_feature(aa64_fhm
, s
)) {
11197 unallocated_encoding(s
);
11200 if (fp_access_check(s
)) {
11201 int is_s
= extract32(insn
, 23, 1);
11202 int is_2
= extract32(insn
, 29, 1);
11203 int data
= (is_2
<< 1) | is_s
;
11204 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
11205 vec_full_reg_offset(s
, rn
),
11206 vec_full_reg_offset(s
, rm
), cpu_env
,
11207 is_q
? 16 : 8, vec_full_reg_size(s
),
11208 data
, gen_helper_gvec_fmlal_a64
);
11213 unallocated_encoding(s
);
11218 /* Integer op subgroup of C3.6.16. */
11219 static void disas_simd_3same_int(DisasContext
*s
, uint32_t insn
)
11221 int is_q
= extract32(insn
, 30, 1);
11222 int u
= extract32(insn
, 29, 1);
11223 int size
= extract32(insn
, 22, 2);
11224 int opcode
= extract32(insn
, 11, 5);
11225 int rm
= extract32(insn
, 16, 5);
11226 int rn
= extract32(insn
, 5, 5);
11227 int rd
= extract32(insn
, 0, 5);
11232 case 0x13: /* MUL, PMUL */
11233 if (u
&& size
!= 0) {
11234 unallocated_encoding(s
);
11238 case 0x0: /* SHADD, UHADD */
11239 case 0x2: /* SRHADD, URHADD */
11240 case 0x4: /* SHSUB, UHSUB */
11241 case 0xc: /* SMAX, UMAX */
11242 case 0xd: /* SMIN, UMIN */
11243 case 0xe: /* SABD, UABD */
11244 case 0xf: /* SABA, UABA */
11245 case 0x12: /* MLA, MLS */
11247 unallocated_encoding(s
);
11251 case 0x16: /* SQDMULH, SQRDMULH */
11252 if (size
== 0 || size
== 3) {
11253 unallocated_encoding(s
);
11258 if (size
== 3 && !is_q
) {
11259 unallocated_encoding(s
);
11265 if (!fp_access_check(s
)) {
11270 case 0x01: /* SQADD, UQADD */
11272 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_uqadd_qc
, size
);
11274 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sqadd_qc
, size
);
11277 case 0x05: /* SQSUB, UQSUB */
11279 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_uqsub_qc
, size
);
11281 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sqsub_qc
, size
);
11284 case 0x08: /* SSHL, USHL */
11286 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_ushl
, size
);
11288 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sshl
, size
);
11291 case 0x0c: /* SMAX, UMAX */
11293 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_umax
, size
);
11295 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_smax
, size
);
11298 case 0x0d: /* SMIN, UMIN */
11300 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_umin
, size
);
11302 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_smin
, size
);
11305 case 0xe: /* SABD, UABD */
11307 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_uabd
, size
);
11309 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sabd
, size
);
11312 case 0xf: /* SABA, UABA */
11314 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_uaba
, size
);
11316 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_saba
, size
);
11319 case 0x10: /* ADD, SUB */
11321 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_sub
, size
);
11323 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_add
, size
);
11326 case 0x13: /* MUL, PMUL */
11327 if (!u
) { /* MUL */
11328 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, tcg_gen_gvec_mul
, size
);
11329 } else { /* PMUL */
11330 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, 0, gen_helper_gvec_pmul_b
);
11333 case 0x12: /* MLA, MLS */
11335 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_mls
, size
);
11337 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_mla
, size
);
11341 if (!u
) { /* CMTST */
11342 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_cmtst
, size
);
11346 cond
= TCG_COND_EQ
;
11348 case 0x06: /* CMGT, CMHI */
11349 cond
= u
? TCG_COND_GTU
: TCG_COND_GT
;
11351 case 0x07: /* CMGE, CMHS */
11352 cond
= u
? TCG_COND_GEU
: TCG_COND_GE
;
11354 tcg_gen_gvec_cmp(cond
, size
, vec_full_reg_offset(s
, rd
),
11355 vec_full_reg_offset(s
, rn
),
11356 vec_full_reg_offset(s
, rm
),
11357 is_q
? 16 : 8, vec_full_reg_size(s
));
11363 for (pass
= 0; pass
< 2; pass
++) {
11364 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11365 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11366 TCGv_i64 tcg_res
= tcg_temp_new_i64();
11368 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
11369 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
11371 handle_3same_64(s
, opcode
, u
, tcg_res
, tcg_op1
, tcg_op2
);
11373 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
11375 tcg_temp_free_i64(tcg_res
);
11376 tcg_temp_free_i64(tcg_op1
);
11377 tcg_temp_free_i64(tcg_op2
);
11380 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
11381 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11382 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11383 TCGv_i32 tcg_res
= tcg_temp_new_i32();
11384 NeonGenTwoOpFn
*genfn
= NULL
;
11385 NeonGenTwoOpEnvFn
*genenvfn
= NULL
;
11387 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_32
);
11388 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_32
);
11391 case 0x0: /* SHADD, UHADD */
11393 static NeonGenTwoOpFn
* const fns
[3][2] = {
11394 { gen_helper_neon_hadd_s8
, gen_helper_neon_hadd_u8
},
11395 { gen_helper_neon_hadd_s16
, gen_helper_neon_hadd_u16
},
11396 { gen_helper_neon_hadd_s32
, gen_helper_neon_hadd_u32
},
11398 genfn
= fns
[size
][u
];
11401 case 0x2: /* SRHADD, URHADD */
11403 static NeonGenTwoOpFn
* const fns
[3][2] = {
11404 { gen_helper_neon_rhadd_s8
, gen_helper_neon_rhadd_u8
},
11405 { gen_helper_neon_rhadd_s16
, gen_helper_neon_rhadd_u16
},
11406 { gen_helper_neon_rhadd_s32
, gen_helper_neon_rhadd_u32
},
11408 genfn
= fns
[size
][u
];
11411 case 0x4: /* SHSUB, UHSUB */
11413 static NeonGenTwoOpFn
* const fns
[3][2] = {
11414 { gen_helper_neon_hsub_s8
, gen_helper_neon_hsub_u8
},
11415 { gen_helper_neon_hsub_s16
, gen_helper_neon_hsub_u16
},
11416 { gen_helper_neon_hsub_s32
, gen_helper_neon_hsub_u32
},
11418 genfn
= fns
[size
][u
];
11421 case 0x9: /* SQSHL, UQSHL */
11423 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11424 { gen_helper_neon_qshl_s8
, gen_helper_neon_qshl_u8
},
11425 { gen_helper_neon_qshl_s16
, gen_helper_neon_qshl_u16
},
11426 { gen_helper_neon_qshl_s32
, gen_helper_neon_qshl_u32
},
11428 genenvfn
= fns
[size
][u
];
11431 case 0xa: /* SRSHL, URSHL */
11433 static NeonGenTwoOpFn
* const fns
[3][2] = {
11434 { gen_helper_neon_rshl_s8
, gen_helper_neon_rshl_u8
},
11435 { gen_helper_neon_rshl_s16
, gen_helper_neon_rshl_u16
},
11436 { gen_helper_neon_rshl_s32
, gen_helper_neon_rshl_u32
},
11438 genfn
= fns
[size
][u
];
11441 case 0xb: /* SQRSHL, UQRSHL */
11443 static NeonGenTwoOpEnvFn
* const fns
[3][2] = {
11444 { gen_helper_neon_qrshl_s8
, gen_helper_neon_qrshl_u8
},
11445 { gen_helper_neon_qrshl_s16
, gen_helper_neon_qrshl_u16
},
11446 { gen_helper_neon_qrshl_s32
, gen_helper_neon_qrshl_u32
},
11448 genenvfn
= fns
[size
][u
];
11451 case 0x16: /* SQDMULH, SQRDMULH */
11453 static NeonGenTwoOpEnvFn
* const fns
[2][2] = {
11454 { gen_helper_neon_qdmulh_s16
, gen_helper_neon_qrdmulh_s16
},
11455 { gen_helper_neon_qdmulh_s32
, gen_helper_neon_qrdmulh_s32
},
11457 assert(size
== 1 || size
== 2);
11458 genenvfn
= fns
[size
- 1][u
];
11462 g_assert_not_reached();
11466 genenvfn(tcg_res
, cpu_env
, tcg_op1
, tcg_op2
);
11468 genfn(tcg_res
, tcg_op1
, tcg_op2
);
11471 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
11473 tcg_temp_free_i32(tcg_res
);
11474 tcg_temp_free_i32(tcg_op1
);
11475 tcg_temp_free_i32(tcg_op2
);
11478 clear_vec_high(s
, is_q
, rd
);
11481 /* AdvSIMD three same
11482 * 31 30 29 28 24 23 22 21 20 16 15 11 10 9 5 4 0
11483 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11484 * | 0 | Q | U | 0 1 1 1 0 | size | 1 | Rm | opcode | 1 | Rn | Rd |
11485 * +---+---+---+-----------+------+---+------+--------+---+------+------+
11487 static void disas_simd_three_reg_same(DisasContext
*s
, uint32_t insn
)
11489 int opcode
= extract32(insn
, 11, 5);
11492 case 0x3: /* logic ops */
11493 disas_simd_3same_logic(s
, insn
);
11495 case 0x17: /* ADDP */
11496 case 0x14: /* SMAXP, UMAXP */
11497 case 0x15: /* SMINP, UMINP */
11499 /* Pairwise operations */
11500 int is_q
= extract32(insn
, 30, 1);
11501 int u
= extract32(insn
, 29, 1);
11502 int size
= extract32(insn
, 22, 2);
11503 int rm
= extract32(insn
, 16, 5);
11504 int rn
= extract32(insn
, 5, 5);
11505 int rd
= extract32(insn
, 0, 5);
11506 if (opcode
== 0x17) {
11507 if (u
|| (size
== 3 && !is_q
)) {
11508 unallocated_encoding(s
);
11513 unallocated_encoding(s
);
11517 handle_simd_3same_pair(s
, is_q
, u
, opcode
, size
, rn
, rm
, rd
);
11520 case 0x18 ... 0x31:
11521 /* floating point ops, sz[1] and U are part of opcode */
11522 disas_simd_3same_float(s
, insn
);
11525 disas_simd_3same_int(s
, insn
);
11531 * Advanced SIMD three same (ARMv8.2 FP16 variants)
11533 * 31 30 29 28 24 23 22 21 20 16 15 14 13 11 10 9 5 4 0
11534 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11535 * | 0 | Q | U | 0 1 1 1 0 | a | 1 0 | Rm | 0 0 | opcode | 1 | Rn | Rd |
11536 * +---+---+---+-----------+---------+------+-----+--------+---+------+------+
11538 * This includes FMULX, FCMEQ (register), FRECPS, FRSQRTS, FCMGE
11539 * (register), FACGE, FABD, FCMGT (register) and FACGT.
11542 static void disas_simd_three_reg_same_fp16(DisasContext
*s
, uint32_t insn
)
11544 int opcode
, fpopcode
;
11545 int is_q
, u
, a
, rm
, rn
, rd
;
11546 int datasize
, elements
;
11549 bool pairwise
= false;
11551 if (!dc_isar_feature(aa64_fp16
, s
)) {
11552 unallocated_encoding(s
);
11556 if (!fp_access_check(s
)) {
11560 /* For these floating point ops, the U, a and opcode bits
11561 * together indicate the operation.
11563 opcode
= extract32(insn
, 11, 3);
11564 u
= extract32(insn
, 29, 1);
11565 a
= extract32(insn
, 23, 1);
11566 is_q
= extract32(insn
, 30, 1);
11567 rm
= extract32(insn
, 16, 5);
11568 rn
= extract32(insn
, 5, 5);
11569 rd
= extract32(insn
, 0, 5);
11571 fpopcode
= opcode
| (a
<< 3) | (u
<< 4);
11572 datasize
= is_q
? 128 : 64;
11573 elements
= datasize
/ 16;
11575 switch (fpopcode
) {
11576 case 0x10: /* FMAXNMP */
11577 case 0x12: /* FADDP */
11578 case 0x16: /* FMAXP */
11579 case 0x18: /* FMINNMP */
11580 case 0x1e: /* FMINP */
11585 fpst
= get_fpstatus_ptr(true);
11588 int maxpass
= is_q
? 8 : 4;
11589 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11590 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11591 TCGv_i32 tcg_res
[8];
11593 for (pass
= 0; pass
< maxpass
; pass
++) {
11594 int passreg
= pass
< (maxpass
/ 2) ? rn
: rm
;
11595 int passelt
= (pass
<< 1) & (maxpass
- 1);
11597 read_vec_element_i32(s
, tcg_op1
, passreg
, passelt
, MO_16
);
11598 read_vec_element_i32(s
, tcg_op2
, passreg
, passelt
+ 1, MO_16
);
11599 tcg_res
[pass
] = tcg_temp_new_i32();
11601 switch (fpopcode
) {
11602 case 0x10: /* FMAXNMP */
11603 gen_helper_advsimd_maxnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
11606 case 0x12: /* FADDP */
11607 gen_helper_advsimd_addh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11609 case 0x16: /* FMAXP */
11610 gen_helper_advsimd_maxh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11612 case 0x18: /* FMINNMP */
11613 gen_helper_advsimd_minnumh(tcg_res
[pass
], tcg_op1
, tcg_op2
,
11616 case 0x1e: /* FMINP */
11617 gen_helper_advsimd_minh(tcg_res
[pass
], tcg_op1
, tcg_op2
, fpst
);
11620 g_assert_not_reached();
11624 for (pass
= 0; pass
< maxpass
; pass
++) {
11625 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_16
);
11626 tcg_temp_free_i32(tcg_res
[pass
]);
11629 tcg_temp_free_i32(tcg_op1
);
11630 tcg_temp_free_i32(tcg_op2
);
11633 for (pass
= 0; pass
< elements
; pass
++) {
11634 TCGv_i32 tcg_op1
= tcg_temp_new_i32();
11635 TCGv_i32 tcg_op2
= tcg_temp_new_i32();
11636 TCGv_i32 tcg_res
= tcg_temp_new_i32();
11638 read_vec_element_i32(s
, tcg_op1
, rn
, pass
, MO_16
);
11639 read_vec_element_i32(s
, tcg_op2
, rm
, pass
, MO_16
);
11641 switch (fpopcode
) {
11642 case 0x0: /* FMAXNM */
11643 gen_helper_advsimd_maxnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11645 case 0x1: /* FMLA */
11646 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11647 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
11650 case 0x2: /* FADD */
11651 gen_helper_advsimd_addh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11653 case 0x3: /* FMULX */
11654 gen_helper_advsimd_mulxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11656 case 0x4: /* FCMEQ */
11657 gen_helper_advsimd_ceq_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11659 case 0x6: /* FMAX */
11660 gen_helper_advsimd_maxh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11662 case 0x7: /* FRECPS */
11663 gen_helper_recpsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11665 case 0x8: /* FMINNM */
11666 gen_helper_advsimd_minnumh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11668 case 0x9: /* FMLS */
11669 /* As usual for ARM, separate negation for fused multiply-add */
11670 tcg_gen_xori_i32(tcg_op1
, tcg_op1
, 0x8000);
11671 read_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11672 gen_helper_advsimd_muladdh(tcg_res
, tcg_op1
, tcg_op2
, tcg_res
,
11675 case 0xa: /* FSUB */
11676 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11678 case 0xe: /* FMIN */
11679 gen_helper_advsimd_minh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11681 case 0xf: /* FRSQRTS */
11682 gen_helper_rsqrtsf_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11684 case 0x13: /* FMUL */
11685 gen_helper_advsimd_mulh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11687 case 0x14: /* FCMGE */
11688 gen_helper_advsimd_cge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11690 case 0x15: /* FACGE */
11691 gen_helper_advsimd_acge_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11693 case 0x17: /* FDIV */
11694 gen_helper_advsimd_divh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11696 case 0x1a: /* FABD */
11697 gen_helper_advsimd_subh(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11698 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0x7fff);
11700 case 0x1c: /* FCMGT */
11701 gen_helper_advsimd_cgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11703 case 0x1d: /* FACGT */
11704 gen_helper_advsimd_acgt_f16(tcg_res
, tcg_op1
, tcg_op2
, fpst
);
11707 fprintf(stderr
, "%s: insn %#04x, fpop %#2x @ %#" PRIx64
"\n",
11708 __func__
, insn
, fpopcode
, s
->pc_curr
);
11709 g_assert_not_reached();
11712 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
11713 tcg_temp_free_i32(tcg_res
);
11714 tcg_temp_free_i32(tcg_op1
);
11715 tcg_temp_free_i32(tcg_op2
);
11719 tcg_temp_free_ptr(fpst
);
11721 clear_vec_high(s
, is_q
, rd
);
11724 /* AdvSIMD three same extra
11725 * 31 30 29 28 24 23 22 21 20 16 15 14 11 10 9 5 4 0
11726 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
11727 * | 0 | Q | U | 0 1 1 1 0 | size | 0 | Rm | 1 | opcode | 1 | Rn | Rd |
11728 * +---+---+---+-----------+------+---+------+---+--------+---+----+----+
11730 static void disas_simd_three_reg_same_extra(DisasContext
*s
, uint32_t insn
)
11732 int rd
= extract32(insn
, 0, 5);
11733 int rn
= extract32(insn
, 5, 5);
11734 int opcode
= extract32(insn
, 11, 4);
11735 int rm
= extract32(insn
, 16, 5);
11736 int size
= extract32(insn
, 22, 2);
11737 bool u
= extract32(insn
, 29, 1);
11738 bool is_q
= extract32(insn
, 30, 1);
11742 switch (u
* 16 + opcode
) {
11743 case 0x10: /* SQRDMLAH (vector) */
11744 case 0x11: /* SQRDMLSH (vector) */
11745 if (size
!= 1 && size
!= 2) {
11746 unallocated_encoding(s
);
11749 feature
= dc_isar_feature(aa64_rdm
, s
);
11751 case 0x02: /* SDOT (vector) */
11752 case 0x12: /* UDOT (vector) */
11753 if (size
!= MO_32
) {
11754 unallocated_encoding(s
);
11757 feature
= dc_isar_feature(aa64_dp
, s
);
11759 case 0x18: /* FCMLA, #0 */
11760 case 0x19: /* FCMLA, #90 */
11761 case 0x1a: /* FCMLA, #180 */
11762 case 0x1b: /* FCMLA, #270 */
11763 case 0x1c: /* FCADD, #90 */
11764 case 0x1e: /* FCADD, #270 */
11766 || (size
== 1 && !dc_isar_feature(aa64_fp16
, s
))
11767 || (size
== 3 && !is_q
)) {
11768 unallocated_encoding(s
);
11771 feature
= dc_isar_feature(aa64_fcma
, s
);
11774 unallocated_encoding(s
);
11778 unallocated_encoding(s
);
11781 if (!fp_access_check(s
)) {
11786 case 0x0: /* SQRDMLAH (vector) */
11787 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sqrdmlah_qc
, size
);
11790 case 0x1: /* SQRDMLSH (vector) */
11791 gen_gvec_fn3(s
, is_q
, rd
, rn
, rm
, gen_gvec_sqrdmlsh_qc
, size
);
11794 case 0x2: /* SDOT / UDOT */
11795 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, 0,
11796 u
? gen_helper_gvec_udot_b
: gen_helper_gvec_sdot_b
);
11799 case 0x8: /* FCMLA, #0 */
11800 case 0x9: /* FCMLA, #90 */
11801 case 0xa: /* FCMLA, #180 */
11802 case 0xb: /* FCMLA, #270 */
11803 rot
= extract32(opcode
, 0, 2);
11806 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, true, rot
,
11807 gen_helper_gvec_fcmlah
);
11810 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, false, rot
,
11811 gen_helper_gvec_fcmlas
);
11814 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, false, rot
,
11815 gen_helper_gvec_fcmlad
);
11818 g_assert_not_reached();
11822 case 0xc: /* FCADD, #90 */
11823 case 0xe: /* FCADD, #270 */
11824 rot
= extract32(opcode
, 1, 1);
11827 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11828 gen_helper_gvec_fcaddh
);
11831 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11832 gen_helper_gvec_fcadds
);
11835 gen_gvec_op3_fpst(s
, is_q
, rd
, rn
, rm
, size
== 1, rot
,
11836 gen_helper_gvec_fcaddd
);
11839 g_assert_not_reached();
11844 g_assert_not_reached();
11848 static void handle_2misc_widening(DisasContext
*s
, int opcode
, bool is_q
,
11849 int size
, int rn
, int rd
)
11851 /* Handle 2-reg-misc ops which are widening (so each size element
11852 * in the source becomes a 2*size element in the destination.
11853 * The only instruction like this is FCVTL.
11858 /* 32 -> 64 bit fp conversion */
11859 TCGv_i64 tcg_res
[2];
11860 int srcelt
= is_q
? 2 : 0;
11862 for (pass
= 0; pass
< 2; pass
++) {
11863 TCGv_i32 tcg_op
= tcg_temp_new_i32();
11864 tcg_res
[pass
] = tcg_temp_new_i64();
11866 read_vec_element_i32(s
, tcg_op
, rn
, srcelt
+ pass
, MO_32
);
11867 gen_helper_vfp_fcvtds(tcg_res
[pass
], tcg_op
, cpu_env
);
11868 tcg_temp_free_i32(tcg_op
);
11870 for (pass
= 0; pass
< 2; pass
++) {
11871 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
11872 tcg_temp_free_i64(tcg_res
[pass
]);
11875 /* 16 -> 32 bit fp conversion */
11876 int srcelt
= is_q
? 4 : 0;
11877 TCGv_i32 tcg_res
[4];
11878 TCGv_ptr fpst
= get_fpstatus_ptr(false);
11879 TCGv_i32 ahp
= get_ahp_flag();
11881 for (pass
= 0; pass
< 4; pass
++) {
11882 tcg_res
[pass
] = tcg_temp_new_i32();
11884 read_vec_element_i32(s
, tcg_res
[pass
], rn
, srcelt
+ pass
, MO_16
);
11885 gen_helper_vfp_fcvt_f16_to_f32(tcg_res
[pass
], tcg_res
[pass
],
11888 for (pass
= 0; pass
< 4; pass
++) {
11889 write_vec_element_i32(s
, tcg_res
[pass
], rd
, pass
, MO_32
);
11890 tcg_temp_free_i32(tcg_res
[pass
]);
11893 tcg_temp_free_ptr(fpst
);
11894 tcg_temp_free_i32(ahp
);
11898 static void handle_rev(DisasContext
*s
, int opcode
, bool u
,
11899 bool is_q
, int size
, int rn
, int rd
)
11901 int op
= (opcode
<< 1) | u
;
11902 int opsz
= op
+ size
;
11903 int grp_size
= 3 - opsz
;
11904 int dsize
= is_q
? 128 : 64;
11908 unallocated_encoding(s
);
11912 if (!fp_access_check(s
)) {
11917 /* Special case bytes, use bswap op on each group of elements */
11918 int groups
= dsize
/ (8 << grp_size
);
11920 for (i
= 0; i
< groups
; i
++) {
11921 TCGv_i64 tcg_tmp
= tcg_temp_new_i64();
11923 read_vec_element(s
, tcg_tmp
, rn
, i
, grp_size
);
11924 switch (grp_size
) {
11926 tcg_gen_bswap16_i64(tcg_tmp
, tcg_tmp
);
11929 tcg_gen_bswap32_i64(tcg_tmp
, tcg_tmp
);
11932 tcg_gen_bswap64_i64(tcg_tmp
, tcg_tmp
);
11935 g_assert_not_reached();
11937 write_vec_element(s
, tcg_tmp
, rd
, i
, grp_size
);
11938 tcg_temp_free_i64(tcg_tmp
);
11940 clear_vec_high(s
, is_q
, rd
);
11942 int revmask
= (1 << grp_size
) - 1;
11943 int esize
= 8 << size
;
11944 int elements
= dsize
/ esize
;
11945 TCGv_i64 tcg_rn
= tcg_temp_new_i64();
11946 TCGv_i64 tcg_rd
= tcg_const_i64(0);
11947 TCGv_i64 tcg_rd_hi
= tcg_const_i64(0);
11949 for (i
= 0; i
< elements
; i
++) {
11950 int e_rev
= (i
& 0xf) ^ revmask
;
11951 int off
= e_rev
* esize
;
11952 read_vec_element(s
, tcg_rn
, rn
, i
, size
);
11954 tcg_gen_deposit_i64(tcg_rd_hi
, tcg_rd_hi
,
11955 tcg_rn
, off
- 64, esize
);
11957 tcg_gen_deposit_i64(tcg_rd
, tcg_rd
, tcg_rn
, off
, esize
);
11960 write_vec_element(s
, tcg_rd
, rd
, 0, MO_64
);
11961 write_vec_element(s
, tcg_rd_hi
, rd
, 1, MO_64
);
11963 tcg_temp_free_i64(tcg_rd_hi
);
11964 tcg_temp_free_i64(tcg_rd
);
11965 tcg_temp_free_i64(tcg_rn
);
11969 static void handle_2misc_pairwise(DisasContext
*s
, int opcode
, bool u
,
11970 bool is_q
, int size
, int rn
, int rd
)
11972 /* Implement the pairwise operations from 2-misc:
11973 * SADDLP, UADDLP, SADALP, UADALP.
11974 * These all add pairs of elements in the input to produce a
11975 * double-width result element in the output (possibly accumulating).
11977 bool accum
= (opcode
== 0x6);
11978 int maxpass
= is_q
? 2 : 1;
11980 TCGv_i64 tcg_res
[2];
11983 /* 32 + 32 -> 64 op */
11984 MemOp memop
= size
+ (u
? 0 : MO_SIGN
);
11986 for (pass
= 0; pass
< maxpass
; pass
++) {
11987 TCGv_i64 tcg_op1
= tcg_temp_new_i64();
11988 TCGv_i64 tcg_op2
= tcg_temp_new_i64();
11990 tcg_res
[pass
] = tcg_temp_new_i64();
11992 read_vec_element(s
, tcg_op1
, rn
, pass
* 2, memop
);
11993 read_vec_element(s
, tcg_op2
, rn
, pass
* 2 + 1, memop
);
11994 tcg_gen_add_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
11996 read_vec_element(s
, tcg_op1
, rd
, pass
, MO_64
);
11997 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
12000 tcg_temp_free_i64(tcg_op1
);
12001 tcg_temp_free_i64(tcg_op2
);
12004 for (pass
= 0; pass
< maxpass
; pass
++) {
12005 TCGv_i64 tcg_op
= tcg_temp_new_i64();
12006 NeonGenOne64OpFn
*genfn
;
12007 static NeonGenOne64OpFn
* const fns
[2][2] = {
12008 { gen_helper_neon_addlp_s8
, gen_helper_neon_addlp_u8
},
12009 { gen_helper_neon_addlp_s16
, gen_helper_neon_addlp_u16
},
12012 genfn
= fns
[size
][u
];
12014 tcg_res
[pass
] = tcg_temp_new_i64();
12016 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
12017 genfn(tcg_res
[pass
], tcg_op
);
12020 read_vec_element(s
, tcg_op
, rd
, pass
, MO_64
);
12022 gen_helper_neon_addl_u16(tcg_res
[pass
],
12023 tcg_res
[pass
], tcg_op
);
12025 gen_helper_neon_addl_u32(tcg_res
[pass
],
12026 tcg_res
[pass
], tcg_op
);
12029 tcg_temp_free_i64(tcg_op
);
12033 tcg_res
[1] = tcg_const_i64(0);
12035 for (pass
= 0; pass
< 2; pass
++) {
12036 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
12037 tcg_temp_free_i64(tcg_res
[pass
]);
12041 static void handle_shll(DisasContext
*s
, bool is_q
, int size
, int rn
, int rd
)
12043 /* Implement SHLL and SHLL2 */
12045 int part
= is_q
? 2 : 0;
12046 TCGv_i64 tcg_res
[2];
12048 for (pass
= 0; pass
< 2; pass
++) {
12049 static NeonGenWidenFn
* const widenfns
[3] = {
12050 gen_helper_neon_widen_u8
,
12051 gen_helper_neon_widen_u16
,
12052 tcg_gen_extu_i32_i64
,
12054 NeonGenWidenFn
*widenfn
= widenfns
[size
];
12055 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12057 read_vec_element_i32(s
, tcg_op
, rn
, part
+ pass
, MO_32
);
12058 tcg_res
[pass
] = tcg_temp_new_i64();
12059 widenfn(tcg_res
[pass
], tcg_op
);
12060 tcg_gen_shli_i64(tcg_res
[pass
], tcg_res
[pass
], 8 << size
);
12062 tcg_temp_free_i32(tcg_op
);
12065 for (pass
= 0; pass
< 2; pass
++) {
12066 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
12067 tcg_temp_free_i64(tcg_res
[pass
]);
12071 /* AdvSIMD two reg misc
12072 * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
12073 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
12074 * | 0 | Q | U | 0 1 1 1 0 | size | 1 0 0 0 0 | opcode | 1 0 | Rn | Rd |
12075 * +---+---+---+-----------+------+-----------+--------+-----+------+------+
12077 static void disas_simd_two_reg_misc(DisasContext
*s
, uint32_t insn
)
12079 int size
= extract32(insn
, 22, 2);
12080 int opcode
= extract32(insn
, 12, 5);
12081 bool u
= extract32(insn
, 29, 1);
12082 bool is_q
= extract32(insn
, 30, 1);
12083 int rn
= extract32(insn
, 5, 5);
12084 int rd
= extract32(insn
, 0, 5);
12085 bool need_fpstatus
= false;
12086 bool need_rmode
= false;
12088 TCGv_i32 tcg_rmode
;
12089 TCGv_ptr tcg_fpstatus
;
12092 case 0x0: /* REV64, REV32 */
12093 case 0x1: /* REV16 */
12094 handle_rev(s
, opcode
, u
, is_q
, size
, rn
, rd
);
12096 case 0x5: /* CNT, NOT, RBIT */
12097 if (u
&& size
== 0) {
12100 } else if (u
&& size
== 1) {
12103 } else if (!u
&& size
== 0) {
12107 unallocated_encoding(s
);
12109 case 0x12: /* XTN, XTN2, SQXTUN, SQXTUN2 */
12110 case 0x14: /* SQXTN, SQXTN2, UQXTN, UQXTN2 */
12112 unallocated_encoding(s
);
12115 if (!fp_access_check(s
)) {
12119 handle_2misc_narrow(s
, false, opcode
, u
, is_q
, size
, rn
, rd
);
12121 case 0x4: /* CLS, CLZ */
12123 unallocated_encoding(s
);
12127 case 0x2: /* SADDLP, UADDLP */
12128 case 0x6: /* SADALP, UADALP */
12130 unallocated_encoding(s
);
12133 if (!fp_access_check(s
)) {
12136 handle_2misc_pairwise(s
, opcode
, u
, is_q
, size
, rn
, rd
);
12138 case 0x13: /* SHLL, SHLL2 */
12139 if (u
== 0 || size
== 3) {
12140 unallocated_encoding(s
);
12143 if (!fp_access_check(s
)) {
12146 handle_shll(s
, is_q
, size
, rn
, rd
);
12148 case 0xa: /* CMLT */
12150 unallocated_encoding(s
);
12154 case 0x8: /* CMGT, CMGE */
12155 case 0x9: /* CMEQ, CMLE */
12156 case 0xb: /* ABS, NEG */
12157 if (size
== 3 && !is_q
) {
12158 unallocated_encoding(s
);
12162 case 0x3: /* SUQADD, USQADD */
12163 if (size
== 3 && !is_q
) {
12164 unallocated_encoding(s
);
12167 if (!fp_access_check(s
)) {
12170 handle_2misc_satacc(s
, false, u
, is_q
, size
, rn
, rd
);
12172 case 0x7: /* SQABS, SQNEG */
12173 if (size
== 3 && !is_q
) {
12174 unallocated_encoding(s
);
12179 case 0x16 ... 0x1f:
12181 /* Floating point: U, size[1] and opcode indicate operation;
12182 * size[0] indicates single or double precision.
12184 int is_double
= extract32(size
, 0, 1);
12185 opcode
|= (extract32(size
, 1, 1) << 5) | (u
<< 6);
12186 size
= is_double
? 3 : 2;
12188 case 0x2f: /* FABS */
12189 case 0x6f: /* FNEG */
12190 if (size
== 3 && !is_q
) {
12191 unallocated_encoding(s
);
12195 case 0x1d: /* SCVTF */
12196 case 0x5d: /* UCVTF */
12198 bool is_signed
= (opcode
== 0x1d) ? true : false;
12199 int elements
= is_double
? 2 : is_q
? 4 : 2;
12200 if (is_double
&& !is_q
) {
12201 unallocated_encoding(s
);
12204 if (!fp_access_check(s
)) {
12207 handle_simd_intfp_conv(s
, rd
, rn
, elements
, is_signed
, 0, size
);
12210 case 0x2c: /* FCMGT (zero) */
12211 case 0x2d: /* FCMEQ (zero) */
12212 case 0x2e: /* FCMLT (zero) */
12213 case 0x6c: /* FCMGE (zero) */
12214 case 0x6d: /* FCMLE (zero) */
12215 if (size
== 3 && !is_q
) {
12216 unallocated_encoding(s
);
12219 handle_2misc_fcmp_zero(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
12221 case 0x7f: /* FSQRT */
12222 if (size
== 3 && !is_q
) {
12223 unallocated_encoding(s
);
12227 case 0x1a: /* FCVTNS */
12228 case 0x1b: /* FCVTMS */
12229 case 0x3a: /* FCVTPS */
12230 case 0x3b: /* FCVTZS */
12231 case 0x5a: /* FCVTNU */
12232 case 0x5b: /* FCVTMU */
12233 case 0x7a: /* FCVTPU */
12234 case 0x7b: /* FCVTZU */
12235 need_fpstatus
= true;
12237 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
12238 if (size
== 3 && !is_q
) {
12239 unallocated_encoding(s
);
12243 case 0x5c: /* FCVTAU */
12244 case 0x1c: /* FCVTAS */
12245 need_fpstatus
= true;
12247 rmode
= FPROUNDING_TIEAWAY
;
12248 if (size
== 3 && !is_q
) {
12249 unallocated_encoding(s
);
12253 case 0x3c: /* URECPE */
12255 unallocated_encoding(s
);
12259 case 0x3d: /* FRECPE */
12260 case 0x7d: /* FRSQRTE */
12261 if (size
== 3 && !is_q
) {
12262 unallocated_encoding(s
);
12265 if (!fp_access_check(s
)) {
12268 handle_2misc_reciprocal(s
, opcode
, false, u
, is_q
, size
, rn
, rd
);
12270 case 0x56: /* FCVTXN, FCVTXN2 */
12272 unallocated_encoding(s
);
12276 case 0x16: /* FCVTN, FCVTN2 */
12277 /* handle_2misc_narrow does a 2*size -> size operation, but these
12278 * instructions encode the source size rather than dest size.
12280 if (!fp_access_check(s
)) {
12283 handle_2misc_narrow(s
, false, opcode
, 0, is_q
, size
- 1, rn
, rd
);
12285 case 0x17: /* FCVTL, FCVTL2 */
12286 if (!fp_access_check(s
)) {
12289 handle_2misc_widening(s
, opcode
, is_q
, size
, rn
, rd
);
12291 case 0x18: /* FRINTN */
12292 case 0x19: /* FRINTM */
12293 case 0x38: /* FRINTP */
12294 case 0x39: /* FRINTZ */
12296 rmode
= extract32(opcode
, 5, 1) | (extract32(opcode
, 0, 1) << 1);
12298 case 0x59: /* FRINTX */
12299 case 0x79: /* FRINTI */
12300 need_fpstatus
= true;
12301 if (size
== 3 && !is_q
) {
12302 unallocated_encoding(s
);
12306 case 0x58: /* FRINTA */
12308 rmode
= FPROUNDING_TIEAWAY
;
12309 need_fpstatus
= true;
12310 if (size
== 3 && !is_q
) {
12311 unallocated_encoding(s
);
12315 case 0x7c: /* URSQRTE */
12317 unallocated_encoding(s
);
12321 case 0x1e: /* FRINT32Z */
12322 case 0x1f: /* FRINT64Z */
12324 rmode
= FPROUNDING_ZERO
;
12326 case 0x5e: /* FRINT32X */
12327 case 0x5f: /* FRINT64X */
12328 need_fpstatus
= true;
12329 if ((size
== 3 && !is_q
) || !dc_isar_feature(aa64_frint
, s
)) {
12330 unallocated_encoding(s
);
12335 unallocated_encoding(s
);
12341 unallocated_encoding(s
);
12345 if (!fp_access_check(s
)) {
12349 if (need_fpstatus
|| need_rmode
) {
12350 tcg_fpstatus
= get_fpstatus_ptr(false);
12352 tcg_fpstatus
= NULL
;
12355 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
12356 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12363 if (u
&& size
== 0) { /* NOT */
12364 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_not
, 0);
12368 case 0x8: /* CMGT, CMGE */
12370 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_cge0
, size
);
12372 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_cgt0
, size
);
12375 case 0x9: /* CMEQ, CMLE */
12377 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_cle0
, size
);
12379 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_ceq0
, size
);
12382 case 0xa: /* CMLT */
12383 gen_gvec_fn2(s
, is_q
, rd
, rn
, gen_gvec_clt0
, size
);
12386 if (u
) { /* ABS, NEG */
12387 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_neg
, size
);
12389 gen_gvec_fn2(s
, is_q
, rd
, rn
, tcg_gen_gvec_abs
, size
);
12395 /* All 64-bit element operations can be shared with scalar 2misc */
12398 /* Coverity claims (size == 3 && !is_q) has been eliminated
12399 * from all paths leading to here.
12401 tcg_debug_assert(is_q
);
12402 for (pass
= 0; pass
< 2; pass
++) {
12403 TCGv_i64 tcg_op
= tcg_temp_new_i64();
12404 TCGv_i64 tcg_res
= tcg_temp_new_i64();
12406 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
12408 handle_2misc_64(s
, opcode
, u
, tcg_res
, tcg_op
,
12409 tcg_rmode
, tcg_fpstatus
);
12411 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
12413 tcg_temp_free_i64(tcg_res
);
12414 tcg_temp_free_i64(tcg_op
);
12419 for (pass
= 0; pass
< (is_q
? 4 : 2); pass
++) {
12420 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12421 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12423 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_32
);
12426 /* Special cases for 32 bit elements */
12428 case 0x4: /* CLS */
12430 tcg_gen_clzi_i32(tcg_res
, tcg_op
, 32);
12432 tcg_gen_clrsb_i32(tcg_res
, tcg_op
);
12435 case 0x7: /* SQABS, SQNEG */
12437 gen_helper_neon_qneg_s32(tcg_res
, cpu_env
, tcg_op
);
12439 gen_helper_neon_qabs_s32(tcg_res
, cpu_env
, tcg_op
);
12442 case 0x2f: /* FABS */
12443 gen_helper_vfp_abss(tcg_res
, tcg_op
);
12445 case 0x6f: /* FNEG */
12446 gen_helper_vfp_negs(tcg_res
, tcg_op
);
12448 case 0x7f: /* FSQRT */
12449 gen_helper_vfp_sqrts(tcg_res
, tcg_op
, cpu_env
);
12451 case 0x1a: /* FCVTNS */
12452 case 0x1b: /* FCVTMS */
12453 case 0x1c: /* FCVTAS */
12454 case 0x3a: /* FCVTPS */
12455 case 0x3b: /* FCVTZS */
12457 TCGv_i32 tcg_shift
= tcg_const_i32(0);
12458 gen_helper_vfp_tosls(tcg_res
, tcg_op
,
12459 tcg_shift
, tcg_fpstatus
);
12460 tcg_temp_free_i32(tcg_shift
);
12463 case 0x5a: /* FCVTNU */
12464 case 0x5b: /* FCVTMU */
12465 case 0x5c: /* FCVTAU */
12466 case 0x7a: /* FCVTPU */
12467 case 0x7b: /* FCVTZU */
12469 TCGv_i32 tcg_shift
= tcg_const_i32(0);
12470 gen_helper_vfp_touls(tcg_res
, tcg_op
,
12471 tcg_shift
, tcg_fpstatus
);
12472 tcg_temp_free_i32(tcg_shift
);
12475 case 0x18: /* FRINTN */
12476 case 0x19: /* FRINTM */
12477 case 0x38: /* FRINTP */
12478 case 0x39: /* FRINTZ */
12479 case 0x58: /* FRINTA */
12480 case 0x79: /* FRINTI */
12481 gen_helper_rints(tcg_res
, tcg_op
, tcg_fpstatus
);
12483 case 0x59: /* FRINTX */
12484 gen_helper_rints_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
12486 case 0x7c: /* URSQRTE */
12487 gen_helper_rsqrte_u32(tcg_res
, tcg_op
);
12489 case 0x1e: /* FRINT32Z */
12490 case 0x5e: /* FRINT32X */
12491 gen_helper_frint32_s(tcg_res
, tcg_op
, tcg_fpstatus
);
12493 case 0x1f: /* FRINT64Z */
12494 case 0x5f: /* FRINT64X */
12495 gen_helper_frint64_s(tcg_res
, tcg_op
, tcg_fpstatus
);
12498 g_assert_not_reached();
12501 /* Use helpers for 8 and 16 bit elements */
12503 case 0x5: /* CNT, RBIT */
12504 /* For these two insns size is part of the opcode specifier
12505 * (handled earlier); they always operate on byte elements.
12508 gen_helper_neon_rbit_u8(tcg_res
, tcg_op
);
12510 gen_helper_neon_cnt_u8(tcg_res
, tcg_op
);
12513 case 0x7: /* SQABS, SQNEG */
12515 NeonGenOneOpEnvFn
*genfn
;
12516 static NeonGenOneOpEnvFn
* const fns
[2][2] = {
12517 { gen_helper_neon_qabs_s8
, gen_helper_neon_qneg_s8
},
12518 { gen_helper_neon_qabs_s16
, gen_helper_neon_qneg_s16
},
12520 genfn
= fns
[size
][u
];
12521 genfn(tcg_res
, cpu_env
, tcg_op
);
12524 case 0x4: /* CLS, CLZ */
12527 gen_helper_neon_clz_u8(tcg_res
, tcg_op
);
12529 gen_helper_neon_clz_u16(tcg_res
, tcg_op
);
12533 gen_helper_neon_cls_s8(tcg_res
, tcg_op
);
12535 gen_helper_neon_cls_s16(tcg_res
, tcg_op
);
12540 g_assert_not_reached();
12544 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
12546 tcg_temp_free_i32(tcg_res
);
12547 tcg_temp_free_i32(tcg_op
);
12550 clear_vec_high(s
, is_q
, rd
);
12553 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12554 tcg_temp_free_i32(tcg_rmode
);
12556 if (need_fpstatus
) {
12557 tcg_temp_free_ptr(tcg_fpstatus
);
12561 /* AdvSIMD [scalar] two register miscellaneous (FP16)
12563 * 31 30 29 28 27 24 23 22 21 17 16 12 11 10 9 5 4 0
12564 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
12565 * | 0 | Q | U | S | 1 1 1 0 | a | 1 1 1 1 0 0 | opcode | 1 0 | Rn | Rd |
12566 * +---+---+---+---+---------+---+-------------+--------+-----+------+------+
12567 * mask: 1000 1111 0111 1110 0000 1100 0000 0000 0x8f7e 0c00
12568 * val: 0000 1110 0111 1000 0000 1000 0000 0000 0x0e78 0800
12570 * This actually covers two groups where scalar access is governed by
12571 * bit 28. A bunch of the instructions (float to integral) only exist
12572 * in the vector form and are un-allocated for the scalar decode. Also
12573 * in the scalar decode Q is always 1.
12575 static void disas_simd_two_reg_misc_fp16(DisasContext
*s
, uint32_t insn
)
12577 int fpop
, opcode
, a
, u
;
12581 bool only_in_vector
= false;
12584 TCGv_i32 tcg_rmode
= NULL
;
12585 TCGv_ptr tcg_fpstatus
= NULL
;
12586 bool need_rmode
= false;
12587 bool need_fpst
= true;
12590 if (!dc_isar_feature(aa64_fp16
, s
)) {
12591 unallocated_encoding(s
);
12595 rd
= extract32(insn
, 0, 5);
12596 rn
= extract32(insn
, 5, 5);
12598 a
= extract32(insn
, 23, 1);
12599 u
= extract32(insn
, 29, 1);
12600 is_scalar
= extract32(insn
, 28, 1);
12601 is_q
= extract32(insn
, 30, 1);
12603 opcode
= extract32(insn
, 12, 5);
12604 fpop
= deposit32(opcode
, 5, 1, a
);
12605 fpop
= deposit32(fpop
, 6, 1, u
);
12607 rd
= extract32(insn
, 0, 5);
12608 rn
= extract32(insn
, 5, 5);
12611 case 0x1d: /* SCVTF */
12612 case 0x5d: /* UCVTF */
12619 elements
= (is_q
? 8 : 4);
12622 if (!fp_access_check(s
)) {
12625 handle_simd_intfp_conv(s
, rd
, rn
, elements
, !u
, 0, MO_16
);
12629 case 0x2c: /* FCMGT (zero) */
12630 case 0x2d: /* FCMEQ (zero) */
12631 case 0x2e: /* FCMLT (zero) */
12632 case 0x6c: /* FCMGE (zero) */
12633 case 0x6d: /* FCMLE (zero) */
12634 handle_2misc_fcmp_zero(s
, fpop
, is_scalar
, 0, is_q
, MO_16
, rn
, rd
);
12636 case 0x3d: /* FRECPE */
12637 case 0x3f: /* FRECPX */
12639 case 0x18: /* FRINTN */
12641 only_in_vector
= true;
12642 rmode
= FPROUNDING_TIEEVEN
;
12644 case 0x19: /* FRINTM */
12646 only_in_vector
= true;
12647 rmode
= FPROUNDING_NEGINF
;
12649 case 0x38: /* FRINTP */
12651 only_in_vector
= true;
12652 rmode
= FPROUNDING_POSINF
;
12654 case 0x39: /* FRINTZ */
12656 only_in_vector
= true;
12657 rmode
= FPROUNDING_ZERO
;
12659 case 0x58: /* FRINTA */
12661 only_in_vector
= true;
12662 rmode
= FPROUNDING_TIEAWAY
;
12664 case 0x59: /* FRINTX */
12665 case 0x79: /* FRINTI */
12666 only_in_vector
= true;
12667 /* current rounding mode */
12669 case 0x1a: /* FCVTNS */
12671 rmode
= FPROUNDING_TIEEVEN
;
12673 case 0x1b: /* FCVTMS */
12675 rmode
= FPROUNDING_NEGINF
;
12677 case 0x1c: /* FCVTAS */
12679 rmode
= FPROUNDING_TIEAWAY
;
12681 case 0x3a: /* FCVTPS */
12683 rmode
= FPROUNDING_POSINF
;
12685 case 0x3b: /* FCVTZS */
12687 rmode
= FPROUNDING_ZERO
;
12689 case 0x5a: /* FCVTNU */
12691 rmode
= FPROUNDING_TIEEVEN
;
12693 case 0x5b: /* FCVTMU */
12695 rmode
= FPROUNDING_NEGINF
;
12697 case 0x5c: /* FCVTAU */
12699 rmode
= FPROUNDING_TIEAWAY
;
12701 case 0x7a: /* FCVTPU */
12703 rmode
= FPROUNDING_POSINF
;
12705 case 0x7b: /* FCVTZU */
12707 rmode
= FPROUNDING_ZERO
;
12709 case 0x2f: /* FABS */
12710 case 0x6f: /* FNEG */
12713 case 0x7d: /* FRSQRTE */
12714 case 0x7f: /* FSQRT (vector) */
12717 fprintf(stderr
, "%s: insn %#04x fpop %#2x\n", __func__
, insn
, fpop
);
12718 g_assert_not_reached();
12722 /* Check additional constraints for the scalar encoding */
12725 unallocated_encoding(s
);
12728 /* FRINTxx is only in the vector form */
12729 if (only_in_vector
) {
12730 unallocated_encoding(s
);
12735 if (!fp_access_check(s
)) {
12739 if (need_rmode
|| need_fpst
) {
12740 tcg_fpstatus
= get_fpstatus_ptr(true);
12744 tcg_rmode
= tcg_const_i32(arm_rmode_to_sf(rmode
));
12745 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12749 TCGv_i32 tcg_op
= read_fp_hreg(s
, rn
);
12750 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12753 case 0x1a: /* FCVTNS */
12754 case 0x1b: /* FCVTMS */
12755 case 0x1c: /* FCVTAS */
12756 case 0x3a: /* FCVTPS */
12757 case 0x3b: /* FCVTZS */
12758 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12760 case 0x3d: /* FRECPE */
12761 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12763 case 0x3f: /* FRECPX */
12764 gen_helper_frecpx_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12766 case 0x5a: /* FCVTNU */
12767 case 0x5b: /* FCVTMU */
12768 case 0x5c: /* FCVTAU */
12769 case 0x7a: /* FCVTPU */
12770 case 0x7b: /* FCVTZU */
12771 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12773 case 0x6f: /* FNEG */
12774 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
12776 case 0x7d: /* FRSQRTE */
12777 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12780 g_assert_not_reached();
12783 /* limit any sign extension going on */
12784 tcg_gen_andi_i32(tcg_res
, tcg_res
, 0xffff);
12785 write_fp_sreg(s
, rd
, tcg_res
);
12787 tcg_temp_free_i32(tcg_res
);
12788 tcg_temp_free_i32(tcg_op
);
12790 for (pass
= 0; pass
< (is_q
? 8 : 4); pass
++) {
12791 TCGv_i32 tcg_op
= tcg_temp_new_i32();
12792 TCGv_i32 tcg_res
= tcg_temp_new_i32();
12794 read_vec_element_i32(s
, tcg_op
, rn
, pass
, MO_16
);
12797 case 0x1a: /* FCVTNS */
12798 case 0x1b: /* FCVTMS */
12799 case 0x1c: /* FCVTAS */
12800 case 0x3a: /* FCVTPS */
12801 case 0x3b: /* FCVTZS */
12802 gen_helper_advsimd_f16tosinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12804 case 0x3d: /* FRECPE */
12805 gen_helper_recpe_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12807 case 0x5a: /* FCVTNU */
12808 case 0x5b: /* FCVTMU */
12809 case 0x5c: /* FCVTAU */
12810 case 0x7a: /* FCVTPU */
12811 case 0x7b: /* FCVTZU */
12812 gen_helper_advsimd_f16touinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12814 case 0x18: /* FRINTN */
12815 case 0x19: /* FRINTM */
12816 case 0x38: /* FRINTP */
12817 case 0x39: /* FRINTZ */
12818 case 0x58: /* FRINTA */
12819 case 0x79: /* FRINTI */
12820 gen_helper_advsimd_rinth(tcg_res
, tcg_op
, tcg_fpstatus
);
12822 case 0x59: /* FRINTX */
12823 gen_helper_advsimd_rinth_exact(tcg_res
, tcg_op
, tcg_fpstatus
);
12825 case 0x2f: /* FABS */
12826 tcg_gen_andi_i32(tcg_res
, tcg_op
, 0x7fff);
12828 case 0x6f: /* FNEG */
12829 tcg_gen_xori_i32(tcg_res
, tcg_op
, 0x8000);
12831 case 0x7d: /* FRSQRTE */
12832 gen_helper_rsqrte_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12834 case 0x7f: /* FSQRT */
12835 gen_helper_sqrt_f16(tcg_res
, tcg_op
, tcg_fpstatus
);
12838 g_assert_not_reached();
12841 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_16
);
12843 tcg_temp_free_i32(tcg_res
);
12844 tcg_temp_free_i32(tcg_op
);
12847 clear_vec_high(s
, is_q
, rd
);
12851 gen_helper_set_rmode(tcg_rmode
, tcg_rmode
, tcg_fpstatus
);
12852 tcg_temp_free_i32(tcg_rmode
);
12855 if (tcg_fpstatus
) {
12856 tcg_temp_free_ptr(tcg_fpstatus
);
12860 /* AdvSIMD scalar x indexed element
12861 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
12862 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
12863 * | 0 1 | U | 1 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
12864 * +-----+---+-----------+------+---+---+------+-----+---+---+------+------+
12865 * AdvSIMD vector x indexed element
12866 * 31 30 29 28 24 23 22 21 20 19 16 15 12 11 10 9 5 4 0
12867 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
12868 * | 0 | Q | U | 0 1 1 1 1 | size | L | M | Rm | opc | H | 0 | Rn | Rd |
12869 * +---+---+---+-----------+------+---+---+------+-----+---+---+------+------+
12871 static void disas_simd_indexed(DisasContext
*s
, uint32_t insn
)
12873 /* This encoding has two kinds of instruction:
12874 * normal, where we perform elt x idxelt => elt for each
12875 * element in the vector
12876 * long, where we perform elt x idxelt and generate a result of
12877 * double the width of the input element
12878 * The long ops have a 'part' specifier (ie come in INSN, INSN2 pairs).
12880 bool is_scalar
= extract32(insn
, 28, 1);
12881 bool is_q
= extract32(insn
, 30, 1);
12882 bool u
= extract32(insn
, 29, 1);
12883 int size
= extract32(insn
, 22, 2);
12884 int l
= extract32(insn
, 21, 1);
12885 int m
= extract32(insn
, 20, 1);
12886 /* Note that the Rm field here is only 4 bits, not 5 as it usually is */
12887 int rm
= extract32(insn
, 16, 4);
12888 int opcode
= extract32(insn
, 12, 4);
12889 int h
= extract32(insn
, 11, 1);
12890 int rn
= extract32(insn
, 5, 5);
12891 int rd
= extract32(insn
, 0, 5);
12892 bool is_long
= false;
12894 bool is_fp16
= false;
12898 switch (16 * u
+ opcode
) {
12899 case 0x08: /* MUL */
12900 case 0x10: /* MLA */
12901 case 0x14: /* MLS */
12903 unallocated_encoding(s
);
12907 case 0x02: /* SMLAL, SMLAL2 */
12908 case 0x12: /* UMLAL, UMLAL2 */
12909 case 0x06: /* SMLSL, SMLSL2 */
12910 case 0x16: /* UMLSL, UMLSL2 */
12911 case 0x0a: /* SMULL, SMULL2 */
12912 case 0x1a: /* UMULL, UMULL2 */
12914 unallocated_encoding(s
);
12919 case 0x03: /* SQDMLAL, SQDMLAL2 */
12920 case 0x07: /* SQDMLSL, SQDMLSL2 */
12921 case 0x0b: /* SQDMULL, SQDMULL2 */
12924 case 0x0c: /* SQDMULH */
12925 case 0x0d: /* SQRDMULH */
12927 case 0x01: /* FMLA */
12928 case 0x05: /* FMLS */
12929 case 0x09: /* FMUL */
12930 case 0x19: /* FMULX */
12933 case 0x1d: /* SQRDMLAH */
12934 case 0x1f: /* SQRDMLSH */
12935 if (!dc_isar_feature(aa64_rdm
, s
)) {
12936 unallocated_encoding(s
);
12940 case 0x0e: /* SDOT */
12941 case 0x1e: /* UDOT */
12942 if (is_scalar
|| size
!= MO_32
|| !dc_isar_feature(aa64_dp
, s
)) {
12943 unallocated_encoding(s
);
12947 case 0x11: /* FCMLA #0 */
12948 case 0x13: /* FCMLA #90 */
12949 case 0x15: /* FCMLA #180 */
12950 case 0x17: /* FCMLA #270 */
12951 if (is_scalar
|| !dc_isar_feature(aa64_fcma
, s
)) {
12952 unallocated_encoding(s
);
12957 case 0x00: /* FMLAL */
12958 case 0x04: /* FMLSL */
12959 case 0x18: /* FMLAL2 */
12960 case 0x1c: /* FMLSL2 */
12961 if (is_scalar
|| size
!= MO_32
|| !dc_isar_feature(aa64_fhm
, s
)) {
12962 unallocated_encoding(s
);
12966 /* is_fp, but we pass cpu_env not fp_status. */
12969 unallocated_encoding(s
);
12974 case 1: /* normal fp */
12975 /* convert insn encoded size to MemOp size */
12977 case 0: /* half-precision */
12981 case MO_32
: /* single precision */
12982 case MO_64
: /* double precision */
12985 unallocated_encoding(s
);
12990 case 2: /* complex fp */
12991 /* Each indexable element is a complex pair. */
12996 unallocated_encoding(s
);
13004 unallocated_encoding(s
);
13009 default: /* integer */
13013 unallocated_encoding(s
);
13018 if (is_fp16
&& !dc_isar_feature(aa64_fp16
, s
)) {
13019 unallocated_encoding(s
);
13023 /* Given MemOp size, adjust register and indexing. */
13026 index
= h
<< 2 | l
<< 1 | m
;
13029 index
= h
<< 1 | l
;
13034 unallocated_encoding(s
);
13041 g_assert_not_reached();
13044 if (!fp_access_check(s
)) {
13049 fpst
= get_fpstatus_ptr(is_fp16
);
13054 switch (16 * u
+ opcode
) {
13055 case 0x0e: /* SDOT */
13056 case 0x1e: /* UDOT */
13057 gen_gvec_op3_ool(s
, is_q
, rd
, rn
, rm
, index
,
13058 u
? gen_helper_gvec_udot_idx_b
13059 : gen_helper_gvec_sdot_idx_b
);
13061 case 0x11: /* FCMLA #0 */
13062 case 0x13: /* FCMLA #90 */
13063 case 0x15: /* FCMLA #180 */
13064 case 0x17: /* FCMLA #270 */
13066 int rot
= extract32(insn
, 13, 2);
13067 int data
= (index
<< 2) | rot
;
13068 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
13069 vec_full_reg_offset(s
, rn
),
13070 vec_full_reg_offset(s
, rm
), fpst
,
13071 is_q
? 16 : 8, vec_full_reg_size(s
), data
,
13073 ? gen_helper_gvec_fcmlas_idx
13074 : gen_helper_gvec_fcmlah_idx
);
13075 tcg_temp_free_ptr(fpst
);
13079 case 0x00: /* FMLAL */
13080 case 0x04: /* FMLSL */
13081 case 0x18: /* FMLAL2 */
13082 case 0x1c: /* FMLSL2 */
13084 int is_s
= extract32(opcode
, 2, 1);
13086 int data
= (index
<< 2) | (is_2
<< 1) | is_s
;
13087 tcg_gen_gvec_3_ptr(vec_full_reg_offset(s
, rd
),
13088 vec_full_reg_offset(s
, rn
),
13089 vec_full_reg_offset(s
, rm
), cpu_env
,
13090 is_q
? 16 : 8, vec_full_reg_size(s
),
13091 data
, gen_helper_gvec_fmlal_idx_a64
);
13097 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
13100 assert(is_fp
&& is_q
&& !is_long
);
13102 read_vec_element(s
, tcg_idx
, rm
, index
, MO_64
);
13104 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13105 TCGv_i64 tcg_op
= tcg_temp_new_i64();
13106 TCGv_i64 tcg_res
= tcg_temp_new_i64();
13108 read_vec_element(s
, tcg_op
, rn
, pass
, MO_64
);
13110 switch (16 * u
+ opcode
) {
13111 case 0x05: /* FMLS */
13112 /* As usual for ARM, separate negation for fused multiply-add */
13113 gen_helper_vfp_negd(tcg_op
, tcg_op
);
13115 case 0x01: /* FMLA */
13116 read_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
13117 gen_helper_vfp_muladdd(tcg_res
, tcg_op
, tcg_idx
, tcg_res
, fpst
);
13119 case 0x09: /* FMUL */
13120 gen_helper_vfp_muld(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13122 case 0x19: /* FMULX */
13123 gen_helper_vfp_mulxd(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13126 g_assert_not_reached();
13129 write_vec_element(s
, tcg_res
, rd
, pass
, MO_64
);
13130 tcg_temp_free_i64(tcg_op
);
13131 tcg_temp_free_i64(tcg_res
);
13134 tcg_temp_free_i64(tcg_idx
);
13135 clear_vec_high(s
, !is_scalar
, rd
);
13136 } else if (!is_long
) {
13137 /* 32 bit floating point, or 16 or 32 bit integer.
13138 * For the 16 bit scalar case we use the usual Neon helpers and
13139 * rely on the fact that 0 op 0 == 0 with no side effects.
13141 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
13142 int pass
, maxpasses
;
13147 maxpasses
= is_q
? 4 : 2;
13150 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
13152 if (size
== 1 && !is_scalar
) {
13153 /* The simplest way to handle the 16x16 indexed ops is to duplicate
13154 * the index into both halves of the 32 bit tcg_idx and then use
13155 * the usual Neon helpers.
13157 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
13160 for (pass
= 0; pass
< maxpasses
; pass
++) {
13161 TCGv_i32 tcg_op
= tcg_temp_new_i32();
13162 TCGv_i32 tcg_res
= tcg_temp_new_i32();
13164 read_vec_element_i32(s
, tcg_op
, rn
, pass
, is_scalar
? size
: MO_32
);
13166 switch (16 * u
+ opcode
) {
13167 case 0x08: /* MUL */
13168 case 0x10: /* MLA */
13169 case 0x14: /* MLS */
13171 static NeonGenTwoOpFn
* const fns
[2][2] = {
13172 { gen_helper_neon_add_u16
, gen_helper_neon_sub_u16
},
13173 { tcg_gen_add_i32
, tcg_gen_sub_i32
},
13175 NeonGenTwoOpFn
*genfn
;
13176 bool is_sub
= opcode
== 0x4;
13179 gen_helper_neon_mul_u16(tcg_res
, tcg_op
, tcg_idx
);
13181 tcg_gen_mul_i32(tcg_res
, tcg_op
, tcg_idx
);
13183 if (opcode
== 0x8) {
13186 read_vec_element_i32(s
, tcg_op
, rd
, pass
, MO_32
);
13187 genfn
= fns
[size
- 1][is_sub
];
13188 genfn(tcg_res
, tcg_op
, tcg_res
);
13191 case 0x05: /* FMLS */
13192 case 0x01: /* FMLA */
13193 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13194 is_scalar
? size
: MO_32
);
13197 if (opcode
== 0x5) {
13198 /* As usual for ARM, separate negation for fused
13200 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80008000);
13203 gen_helper_advsimd_muladdh(tcg_res
, tcg_op
, tcg_idx
,
13206 gen_helper_advsimd_muladd2h(tcg_res
, tcg_op
, tcg_idx
,
13211 if (opcode
== 0x5) {
13212 /* As usual for ARM, separate negation for
13213 * fused multiply-add */
13214 tcg_gen_xori_i32(tcg_op
, tcg_op
, 0x80000000);
13216 gen_helper_vfp_muladds(tcg_res
, tcg_op
, tcg_idx
,
13220 g_assert_not_reached();
13223 case 0x09: /* FMUL */
13227 gen_helper_advsimd_mulh(tcg_res
, tcg_op
,
13230 gen_helper_advsimd_mul2h(tcg_res
, tcg_op
,
13235 gen_helper_vfp_muls(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13238 g_assert_not_reached();
13241 case 0x19: /* FMULX */
13245 gen_helper_advsimd_mulxh(tcg_res
, tcg_op
,
13248 gen_helper_advsimd_mulx2h(tcg_res
, tcg_op
,
13253 gen_helper_vfp_mulxs(tcg_res
, tcg_op
, tcg_idx
, fpst
);
13256 g_assert_not_reached();
13259 case 0x0c: /* SQDMULH */
13261 gen_helper_neon_qdmulh_s16(tcg_res
, cpu_env
,
13264 gen_helper_neon_qdmulh_s32(tcg_res
, cpu_env
,
13268 case 0x0d: /* SQRDMULH */
13270 gen_helper_neon_qrdmulh_s16(tcg_res
, cpu_env
,
13273 gen_helper_neon_qrdmulh_s32(tcg_res
, cpu_env
,
13277 case 0x1d: /* SQRDMLAH */
13278 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13279 is_scalar
? size
: MO_32
);
13281 gen_helper_neon_qrdmlah_s16(tcg_res
, cpu_env
,
13282 tcg_op
, tcg_idx
, tcg_res
);
13284 gen_helper_neon_qrdmlah_s32(tcg_res
, cpu_env
,
13285 tcg_op
, tcg_idx
, tcg_res
);
13288 case 0x1f: /* SQRDMLSH */
13289 read_vec_element_i32(s
, tcg_res
, rd
, pass
,
13290 is_scalar
? size
: MO_32
);
13292 gen_helper_neon_qrdmlsh_s16(tcg_res
, cpu_env
,
13293 tcg_op
, tcg_idx
, tcg_res
);
13295 gen_helper_neon_qrdmlsh_s32(tcg_res
, cpu_env
,
13296 tcg_op
, tcg_idx
, tcg_res
);
13300 g_assert_not_reached();
13304 write_fp_sreg(s
, rd
, tcg_res
);
13306 write_vec_element_i32(s
, tcg_res
, rd
, pass
, MO_32
);
13309 tcg_temp_free_i32(tcg_op
);
13310 tcg_temp_free_i32(tcg_res
);
13313 tcg_temp_free_i32(tcg_idx
);
13314 clear_vec_high(s
, is_q
, rd
);
13316 /* long ops: 16x16->32 or 32x32->64 */
13317 TCGv_i64 tcg_res
[2];
13319 bool satop
= extract32(opcode
, 0, 1);
13320 MemOp memop
= MO_32
;
13327 TCGv_i64 tcg_idx
= tcg_temp_new_i64();
13329 read_vec_element(s
, tcg_idx
, rm
, index
, memop
);
13331 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13332 TCGv_i64 tcg_op
= tcg_temp_new_i64();
13333 TCGv_i64 tcg_passres
;
13339 passelt
= pass
+ (is_q
* 2);
13342 read_vec_element(s
, tcg_op
, rn
, passelt
, memop
);
13344 tcg_res
[pass
] = tcg_temp_new_i64();
13346 if (opcode
== 0xa || opcode
== 0xb) {
13347 /* Non-accumulating ops */
13348 tcg_passres
= tcg_res
[pass
];
13350 tcg_passres
= tcg_temp_new_i64();
13353 tcg_gen_mul_i64(tcg_passres
, tcg_op
, tcg_idx
);
13354 tcg_temp_free_i64(tcg_op
);
13357 /* saturating, doubling */
13358 gen_helper_neon_addl_saturate_s64(tcg_passres
, cpu_env
,
13359 tcg_passres
, tcg_passres
);
13362 if (opcode
== 0xa || opcode
== 0xb) {
13366 /* Accumulating op: handle accumulate step */
13367 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13370 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13371 tcg_gen_add_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
13373 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13374 tcg_gen_sub_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_passres
);
13376 case 0x7: /* SQDMLSL, SQDMLSL2 */
13377 tcg_gen_neg_i64(tcg_passres
, tcg_passres
);
13379 case 0x3: /* SQDMLAL, SQDMLAL2 */
13380 gen_helper_neon_addl_saturate_s64(tcg_res
[pass
], cpu_env
,
13385 g_assert_not_reached();
13387 tcg_temp_free_i64(tcg_passres
);
13389 tcg_temp_free_i64(tcg_idx
);
13391 clear_vec_high(s
, !is_scalar
, rd
);
13393 TCGv_i32 tcg_idx
= tcg_temp_new_i32();
13396 read_vec_element_i32(s
, tcg_idx
, rm
, index
, size
);
13399 /* The simplest way to handle the 16x16 indexed ops is to
13400 * duplicate the index into both halves of the 32 bit tcg_idx
13401 * and then use the usual Neon helpers.
13403 tcg_gen_deposit_i32(tcg_idx
, tcg_idx
, tcg_idx
, 16, 16);
13406 for (pass
= 0; pass
< (is_scalar
? 1 : 2); pass
++) {
13407 TCGv_i32 tcg_op
= tcg_temp_new_i32();
13408 TCGv_i64 tcg_passres
;
13411 read_vec_element_i32(s
, tcg_op
, rn
, pass
, size
);
13413 read_vec_element_i32(s
, tcg_op
, rn
,
13414 pass
+ (is_q
* 2), MO_32
);
13417 tcg_res
[pass
] = tcg_temp_new_i64();
13419 if (opcode
== 0xa || opcode
== 0xb) {
13420 /* Non-accumulating ops */
13421 tcg_passres
= tcg_res
[pass
];
13423 tcg_passres
= tcg_temp_new_i64();
13426 if (memop
& MO_SIGN
) {
13427 gen_helper_neon_mull_s16(tcg_passres
, tcg_op
, tcg_idx
);
13429 gen_helper_neon_mull_u16(tcg_passres
, tcg_op
, tcg_idx
);
13432 gen_helper_neon_addl_saturate_s32(tcg_passres
, cpu_env
,
13433 tcg_passres
, tcg_passres
);
13435 tcg_temp_free_i32(tcg_op
);
13437 if (opcode
== 0xa || opcode
== 0xb) {
13441 /* Accumulating op: handle accumulate step */
13442 read_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13445 case 0x2: /* SMLAL, SMLAL2, UMLAL, UMLAL2 */
13446 gen_helper_neon_addl_u32(tcg_res
[pass
], tcg_res
[pass
],
13449 case 0x6: /* SMLSL, SMLSL2, UMLSL, UMLSL2 */
13450 gen_helper_neon_subl_u32(tcg_res
[pass
], tcg_res
[pass
],
13453 case 0x7: /* SQDMLSL, SQDMLSL2 */
13454 gen_helper_neon_negl_u32(tcg_passres
, tcg_passres
);
13456 case 0x3: /* SQDMLAL, SQDMLAL2 */
13457 gen_helper_neon_addl_saturate_s32(tcg_res
[pass
], cpu_env
,
13462 g_assert_not_reached();
13464 tcg_temp_free_i64(tcg_passres
);
13466 tcg_temp_free_i32(tcg_idx
);
13469 tcg_gen_ext32u_i64(tcg_res
[0], tcg_res
[0]);
13474 tcg_res
[1] = tcg_const_i64(0);
13477 for (pass
= 0; pass
< 2; pass
++) {
13478 write_vec_element(s
, tcg_res
[pass
], rd
, pass
, MO_64
);
13479 tcg_temp_free_i64(tcg_res
[pass
]);
13484 tcg_temp_free_ptr(fpst
);
13489 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
13490 * +-----------------+------+-----------+--------+-----+------+------+
13491 * | 0 1 0 0 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
13492 * +-----------------+------+-----------+--------+-----+------+------+
13494 static void disas_crypto_aes(DisasContext
*s
, uint32_t insn
)
13496 int size
= extract32(insn
, 22, 2);
13497 int opcode
= extract32(insn
, 12, 5);
13498 int rn
= extract32(insn
, 5, 5);
13499 int rd
= extract32(insn
, 0, 5);
13501 gen_helper_gvec_2
*genfn2
= NULL
;
13502 gen_helper_gvec_3
*genfn3
= NULL
;
13504 if (!dc_isar_feature(aa64_aes
, s
) || size
!= 0) {
13505 unallocated_encoding(s
);
13510 case 0x4: /* AESE */
13512 genfn3
= gen_helper_crypto_aese
;
13514 case 0x6: /* AESMC */
13516 genfn2
= gen_helper_crypto_aesmc
;
13518 case 0x5: /* AESD */
13520 genfn3
= gen_helper_crypto_aese
;
13522 case 0x7: /* AESIMC */
13524 genfn2
= gen_helper_crypto_aesmc
;
13527 unallocated_encoding(s
);
13531 if (!fp_access_check(s
)) {
13535 gen_gvec_op2_ool(s
, true, rd
, rn
, decrypt
, genfn2
);
13537 gen_gvec_op3_ool(s
, true, rd
, rd
, rn
, decrypt
, genfn3
);
13541 /* Crypto three-reg SHA
13542 * 31 24 23 22 21 20 16 15 14 12 11 10 9 5 4 0
13543 * +-----------------+------+---+------+---+--------+-----+------+------+
13544 * | 0 1 0 1 1 1 1 0 | size | 0 | Rm | 0 | opcode | 0 0 | Rn | Rd |
13545 * +-----------------+------+---+------+---+--------+-----+------+------+
13547 static void disas_crypto_three_reg_sha(DisasContext
*s
, uint32_t insn
)
13549 int size
= extract32(insn
, 22, 2);
13550 int opcode
= extract32(insn
, 12, 3);
13551 int rm
= extract32(insn
, 16, 5);
13552 int rn
= extract32(insn
, 5, 5);
13553 int rd
= extract32(insn
, 0, 5);
13554 gen_helper_gvec_3
*genfn
;
13558 unallocated_encoding(s
);
13563 case 0: /* SHA1C */
13564 genfn
= gen_helper_crypto_sha1c
;
13565 feature
= dc_isar_feature(aa64_sha1
, s
);
13567 case 1: /* SHA1P */
13568 genfn
= gen_helper_crypto_sha1p
;
13569 feature
= dc_isar_feature(aa64_sha1
, s
);
13571 case 2: /* SHA1M */
13572 genfn
= gen_helper_crypto_sha1m
;
13573 feature
= dc_isar_feature(aa64_sha1
, s
);
13575 case 3: /* SHA1SU0 */
13576 genfn
= gen_helper_crypto_sha1su0
;
13577 feature
= dc_isar_feature(aa64_sha1
, s
);
13579 case 4: /* SHA256H */
13580 genfn
= gen_helper_crypto_sha256h
;
13581 feature
= dc_isar_feature(aa64_sha256
, s
);
13583 case 5: /* SHA256H2 */
13584 genfn
= gen_helper_crypto_sha256h2
;
13585 feature
= dc_isar_feature(aa64_sha256
, s
);
13587 case 6: /* SHA256SU1 */
13588 genfn
= gen_helper_crypto_sha256su1
;
13589 feature
= dc_isar_feature(aa64_sha256
, s
);
13592 unallocated_encoding(s
);
13597 unallocated_encoding(s
);
13601 if (!fp_access_check(s
)) {
13604 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, 0, genfn
);
13607 /* Crypto two-reg SHA
13608 * 31 24 23 22 21 17 16 12 11 10 9 5 4 0
13609 * +-----------------+------+-----------+--------+-----+------+------+
13610 * | 0 1 0 1 1 1 1 0 | size | 1 0 1 0 0 | opcode | 1 0 | Rn | Rd |
13611 * +-----------------+------+-----------+--------+-----+------+------+
13613 static void disas_crypto_two_reg_sha(DisasContext
*s
, uint32_t insn
)
13615 int size
= extract32(insn
, 22, 2);
13616 int opcode
= extract32(insn
, 12, 5);
13617 int rn
= extract32(insn
, 5, 5);
13618 int rd
= extract32(insn
, 0, 5);
13619 gen_helper_gvec_2
*genfn
;
13623 unallocated_encoding(s
);
13628 case 0: /* SHA1H */
13629 feature
= dc_isar_feature(aa64_sha1
, s
);
13630 genfn
= gen_helper_crypto_sha1h
;
13632 case 1: /* SHA1SU1 */
13633 feature
= dc_isar_feature(aa64_sha1
, s
);
13634 genfn
= gen_helper_crypto_sha1su1
;
13636 case 2: /* SHA256SU0 */
13637 feature
= dc_isar_feature(aa64_sha256
, s
);
13638 genfn
= gen_helper_crypto_sha256su0
;
13641 unallocated_encoding(s
);
13646 unallocated_encoding(s
);
13650 if (!fp_access_check(s
)) {
13653 gen_gvec_op2_ool(s
, true, rd
, rn
, 0, genfn
);
13656 static void gen_rax1_i64(TCGv_i64 d
, TCGv_i64 n
, TCGv_i64 m
)
13658 tcg_gen_rotli_i64(d
, m
, 1);
13659 tcg_gen_xor_i64(d
, d
, n
);
13662 static void gen_rax1_vec(unsigned vece
, TCGv_vec d
, TCGv_vec n
, TCGv_vec m
)
13664 tcg_gen_rotli_vec(vece
, d
, m
, 1);
13665 tcg_gen_xor_vec(vece
, d
, d
, n
);
13668 void gen_gvec_rax1(unsigned vece
, uint32_t rd_ofs
, uint32_t rn_ofs
,
13669 uint32_t rm_ofs
, uint32_t opr_sz
, uint32_t max_sz
)
13671 static const TCGOpcode vecop_list
[] = { INDEX_op_rotli_vec
, 0 };
13672 static const GVecGen3 op
= {
13673 .fni8
= gen_rax1_i64
,
13674 .fniv
= gen_rax1_vec
,
13675 .opt_opc
= vecop_list
,
13676 .fno
= gen_helper_crypto_rax1
,
13679 tcg_gen_gvec_3(rd_ofs
, rn_ofs
, rm_ofs
, opr_sz
, max_sz
, &op
);
13682 /* Crypto three-reg SHA512
13683 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
13684 * +-----------------------+------+---+---+-----+--------+------+------+
13685 * | 1 1 0 0 1 1 1 0 0 1 1 | Rm | 1 | O | 0 0 | opcode | Rn | Rd |
13686 * +-----------------------+------+---+---+-----+--------+------+------+
13688 static void disas_crypto_three_reg_sha512(DisasContext
*s
, uint32_t insn
)
13690 int opcode
= extract32(insn
, 10, 2);
13691 int o
= extract32(insn
, 14, 1);
13692 int rm
= extract32(insn
, 16, 5);
13693 int rn
= extract32(insn
, 5, 5);
13694 int rd
= extract32(insn
, 0, 5);
13696 gen_helper_gvec_3
*oolfn
= NULL
;
13697 GVecGen3Fn
*gvecfn
= NULL
;
13701 case 0: /* SHA512H */
13702 feature
= dc_isar_feature(aa64_sha512
, s
);
13703 oolfn
= gen_helper_crypto_sha512h
;
13705 case 1: /* SHA512H2 */
13706 feature
= dc_isar_feature(aa64_sha512
, s
);
13707 oolfn
= gen_helper_crypto_sha512h2
;
13709 case 2: /* SHA512SU1 */
13710 feature
= dc_isar_feature(aa64_sha512
, s
);
13711 oolfn
= gen_helper_crypto_sha512su1
;
13714 feature
= dc_isar_feature(aa64_sha3
, s
);
13715 gvecfn
= gen_gvec_rax1
;
13718 g_assert_not_reached();
13722 case 0: /* SM3PARTW1 */
13723 feature
= dc_isar_feature(aa64_sm3
, s
);
13724 oolfn
= gen_helper_crypto_sm3partw1
;
13726 case 1: /* SM3PARTW2 */
13727 feature
= dc_isar_feature(aa64_sm3
, s
);
13728 oolfn
= gen_helper_crypto_sm3partw2
;
13730 case 2: /* SM4EKEY */
13731 feature
= dc_isar_feature(aa64_sm4
, s
);
13732 oolfn
= gen_helper_crypto_sm4ekey
;
13735 unallocated_encoding(s
);
13741 unallocated_encoding(s
);
13745 if (!fp_access_check(s
)) {
13750 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, 0, oolfn
);
13752 gen_gvec_fn3(s
, true, rd
, rn
, rm
, gvecfn
, MO_64
);
13756 /* Crypto two-reg SHA512
13757 * 31 12 11 10 9 5 4 0
13758 * +-----------------------------------------+--------+------+------+
13759 * | 1 1 0 0 1 1 1 0 1 1 0 0 0 0 0 0 1 0 0 0 | opcode | Rn | Rd |
13760 * +-----------------------------------------+--------+------+------+
13762 static void disas_crypto_two_reg_sha512(DisasContext
*s
, uint32_t insn
)
13764 int opcode
= extract32(insn
, 10, 2);
13765 int rn
= extract32(insn
, 5, 5);
13766 int rd
= extract32(insn
, 0, 5);
13770 case 0: /* SHA512SU0 */
13771 feature
= dc_isar_feature(aa64_sha512
, s
);
13774 feature
= dc_isar_feature(aa64_sm4
, s
);
13777 unallocated_encoding(s
);
13782 unallocated_encoding(s
);
13786 if (!fp_access_check(s
)) {
13791 case 0: /* SHA512SU0 */
13792 gen_gvec_op2_ool(s
, true, rd
, rn
, 0, gen_helper_crypto_sha512su0
);
13795 gen_gvec_op3_ool(s
, true, rd
, rd
, rn
, 0, gen_helper_crypto_sm4e
);
13798 g_assert_not_reached();
13802 /* Crypto four-register
13803 * 31 23 22 21 20 16 15 14 10 9 5 4 0
13804 * +-------------------+-----+------+---+------+------+------+
13805 * | 1 1 0 0 1 1 1 0 0 | Op0 | Rm | 0 | Ra | Rn | Rd |
13806 * +-------------------+-----+------+---+------+------+------+
13808 static void disas_crypto_four_reg(DisasContext
*s
, uint32_t insn
)
13810 int op0
= extract32(insn
, 21, 2);
13811 int rm
= extract32(insn
, 16, 5);
13812 int ra
= extract32(insn
, 10, 5);
13813 int rn
= extract32(insn
, 5, 5);
13814 int rd
= extract32(insn
, 0, 5);
13820 feature
= dc_isar_feature(aa64_sha3
, s
);
13822 case 2: /* SM3SS1 */
13823 feature
= dc_isar_feature(aa64_sm3
, s
);
13826 unallocated_encoding(s
);
13831 unallocated_encoding(s
);
13835 if (!fp_access_check(s
)) {
13840 TCGv_i64 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
[2];
13843 tcg_op1
= tcg_temp_new_i64();
13844 tcg_op2
= tcg_temp_new_i64();
13845 tcg_op3
= tcg_temp_new_i64();
13846 tcg_res
[0] = tcg_temp_new_i64();
13847 tcg_res
[1] = tcg_temp_new_i64();
13849 for (pass
= 0; pass
< 2; pass
++) {
13850 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
13851 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
13852 read_vec_element(s
, tcg_op3
, ra
, pass
, MO_64
);
13856 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
13859 tcg_gen_andc_i64(tcg_res
[pass
], tcg_op2
, tcg_op3
);
13861 tcg_gen_xor_i64(tcg_res
[pass
], tcg_res
[pass
], tcg_op1
);
13863 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
13864 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
13866 tcg_temp_free_i64(tcg_op1
);
13867 tcg_temp_free_i64(tcg_op2
);
13868 tcg_temp_free_i64(tcg_op3
);
13869 tcg_temp_free_i64(tcg_res
[0]);
13870 tcg_temp_free_i64(tcg_res
[1]);
13872 TCGv_i32 tcg_op1
, tcg_op2
, tcg_op3
, tcg_res
, tcg_zero
;
13874 tcg_op1
= tcg_temp_new_i32();
13875 tcg_op2
= tcg_temp_new_i32();
13876 tcg_op3
= tcg_temp_new_i32();
13877 tcg_res
= tcg_temp_new_i32();
13878 tcg_zero
= tcg_const_i32(0);
13880 read_vec_element_i32(s
, tcg_op1
, rn
, 3, MO_32
);
13881 read_vec_element_i32(s
, tcg_op2
, rm
, 3, MO_32
);
13882 read_vec_element_i32(s
, tcg_op3
, ra
, 3, MO_32
);
13884 tcg_gen_rotri_i32(tcg_res
, tcg_op1
, 20);
13885 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op2
);
13886 tcg_gen_add_i32(tcg_res
, tcg_res
, tcg_op3
);
13887 tcg_gen_rotri_i32(tcg_res
, tcg_res
, 25);
13889 write_vec_element_i32(s
, tcg_zero
, rd
, 0, MO_32
);
13890 write_vec_element_i32(s
, tcg_zero
, rd
, 1, MO_32
);
13891 write_vec_element_i32(s
, tcg_zero
, rd
, 2, MO_32
);
13892 write_vec_element_i32(s
, tcg_res
, rd
, 3, MO_32
);
13894 tcg_temp_free_i32(tcg_op1
);
13895 tcg_temp_free_i32(tcg_op2
);
13896 tcg_temp_free_i32(tcg_op3
);
13897 tcg_temp_free_i32(tcg_res
);
13898 tcg_temp_free_i32(tcg_zero
);
13903 * 31 21 20 16 15 10 9 5 4 0
13904 * +-----------------------+------+--------+------+------+
13905 * | 1 1 0 0 1 1 1 0 1 0 0 | Rm | imm6 | Rn | Rd |
13906 * +-----------------------+------+--------+------+------+
13908 static void disas_crypto_xar(DisasContext
*s
, uint32_t insn
)
13910 int rm
= extract32(insn
, 16, 5);
13911 int imm6
= extract32(insn
, 10, 6);
13912 int rn
= extract32(insn
, 5, 5);
13913 int rd
= extract32(insn
, 0, 5);
13914 TCGv_i64 tcg_op1
, tcg_op2
, tcg_res
[2];
13917 if (!dc_isar_feature(aa64_sha3
, s
)) {
13918 unallocated_encoding(s
);
13922 if (!fp_access_check(s
)) {
13926 tcg_op1
= tcg_temp_new_i64();
13927 tcg_op2
= tcg_temp_new_i64();
13928 tcg_res
[0] = tcg_temp_new_i64();
13929 tcg_res
[1] = tcg_temp_new_i64();
13931 for (pass
= 0; pass
< 2; pass
++) {
13932 read_vec_element(s
, tcg_op1
, rn
, pass
, MO_64
);
13933 read_vec_element(s
, tcg_op2
, rm
, pass
, MO_64
);
13935 tcg_gen_xor_i64(tcg_res
[pass
], tcg_op1
, tcg_op2
);
13936 tcg_gen_rotri_i64(tcg_res
[pass
], tcg_res
[pass
], imm6
);
13938 write_vec_element(s
, tcg_res
[0], rd
, 0, MO_64
);
13939 write_vec_element(s
, tcg_res
[1], rd
, 1, MO_64
);
13941 tcg_temp_free_i64(tcg_op1
);
13942 tcg_temp_free_i64(tcg_op2
);
13943 tcg_temp_free_i64(tcg_res
[0]);
13944 tcg_temp_free_i64(tcg_res
[1]);
13947 /* Crypto three-reg imm2
13948 * 31 21 20 16 15 14 13 12 11 10 9 5 4 0
13949 * +-----------------------+------+-----+------+--------+------+------+
13950 * | 1 1 0 0 1 1 1 0 0 1 0 | Rm | 1 0 | imm2 | opcode | Rn | Rd |
13951 * +-----------------------+------+-----+------+--------+------+------+
13953 static void disas_crypto_three_reg_imm2(DisasContext
*s
, uint32_t insn
)
13955 static gen_helper_gvec_3
* const fns
[4] = {
13956 gen_helper_crypto_sm3tt1a
, gen_helper_crypto_sm3tt1b
,
13957 gen_helper_crypto_sm3tt2a
, gen_helper_crypto_sm3tt2b
,
13959 int opcode
= extract32(insn
, 10, 2);
13960 int imm2
= extract32(insn
, 12, 2);
13961 int rm
= extract32(insn
, 16, 5);
13962 int rn
= extract32(insn
, 5, 5);
13963 int rd
= extract32(insn
, 0, 5);
13965 if (!dc_isar_feature(aa64_sm3
, s
)) {
13966 unallocated_encoding(s
);
13970 if (!fp_access_check(s
)) {
13974 gen_gvec_op3_ool(s
, true, rd
, rn
, rm
, imm2
, fns
[opcode
]);
13977 /* C3.6 Data processing - SIMD, inc Crypto
13979 * As the decode gets a little complex we are using a table based
13980 * approach for this part of the decode.
13982 static const AArch64DecodeTable data_proc_simd
[] = {
13983 /* pattern , mask , fn */
13984 { 0x0e200400, 0x9f200400, disas_simd_three_reg_same
},
13985 { 0x0e008400, 0x9f208400, disas_simd_three_reg_same_extra
},
13986 { 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff
},
13987 { 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc
},
13988 { 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes
},
13989 { 0x0e000400, 0x9fe08400, disas_simd_copy
},
13990 { 0x0f000000, 0x9f000400, disas_simd_indexed
}, /* vector indexed */
13991 /* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
13992 { 0x0f000400, 0x9ff80400, disas_simd_mod_imm
},
13993 { 0x0f000400, 0x9f800400, disas_simd_shift_imm
},
13994 { 0x0e000000, 0xbf208c00, disas_simd_tb
},
13995 { 0x0e000800, 0xbf208c00, disas_simd_zip_trn
},
13996 { 0x2e000000, 0xbf208400, disas_simd_ext
},
13997 { 0x5e200400, 0xdf200400, disas_simd_scalar_three_reg_same
},
13998 { 0x5e008400, 0xdf208400, disas_simd_scalar_three_reg_same_extra
},
13999 { 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff
},
14000 { 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc
},
14001 { 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise
},
14002 { 0x5e000400, 0xdfe08400, disas_simd_scalar_copy
},
14003 { 0x5f000000, 0xdf000400, disas_simd_indexed
}, /* scalar indexed */
14004 { 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm
},
14005 { 0x4e280800, 0xff3e0c00, disas_crypto_aes
},
14006 { 0x5e000000, 0xff208c00, disas_crypto_three_reg_sha
},
14007 { 0x5e280800, 0xff3e0c00, disas_crypto_two_reg_sha
},
14008 { 0xce608000, 0xffe0b000, disas_crypto_three_reg_sha512
},
14009 { 0xcec08000, 0xfffff000, disas_crypto_two_reg_sha512
},
14010 { 0xce000000, 0xff808000, disas_crypto_four_reg
},
14011 { 0xce800000, 0xffe00000, disas_crypto_xar
},
14012 { 0xce408000, 0xffe0c000, disas_crypto_three_reg_imm2
},
14013 { 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16
},
14014 { 0x0e780800, 0x8f7e0c00, disas_simd_two_reg_misc_fp16
},
14015 { 0x5e400400, 0xdf60c400, disas_simd_scalar_three_reg_same_fp16
},
14016 { 0x00000000, 0x00000000, NULL
}
14019 static void disas_data_proc_simd(DisasContext
*s
, uint32_t insn
)
14021 /* Note that this is called with all non-FP cases from
14022 * table C3-6 so it must UNDEF for entries not specifically
14023 * allocated to instructions in that table.
14025 AArch64DecodeFn
*fn
= lookup_disas_fn(&data_proc_simd
[0], insn
);
14029 unallocated_encoding(s
);
14033 /* C3.6 Data processing - SIMD and floating point */
14034 static void disas_data_proc_simd_fp(DisasContext
*s
, uint32_t insn
)
14036 if (extract32(insn
, 28, 1) == 1 && extract32(insn
, 30, 1) == 0) {
14037 disas_data_proc_fp(s
, insn
);
14039 /* SIMD, including crypto */
14040 disas_data_proc_simd(s
, insn
);
14046 * @env: The cpu environment
14047 * @s: The DisasContext
14049 * Return true if the page is guarded.
14051 static bool is_guarded_page(CPUARMState
*env
, DisasContext
*s
)
14053 #ifdef CONFIG_USER_ONLY
14054 return false; /* FIXME */
14056 uint64_t addr
= s
->base
.pc_first
;
14057 int mmu_idx
= arm_to_core_mmu_idx(s
->mmu_idx
);
14058 unsigned int index
= tlb_index(env
, mmu_idx
, addr
);
14059 CPUTLBEntry
*entry
= tlb_entry(env
, mmu_idx
, addr
);
14062 * We test this immediately after reading an insn, which means
14063 * that any normal page must be in the TLB. The only exception
14064 * would be for executing from flash or device memory, which
14065 * does not retain the TLB entry.
14067 * FIXME: Assume false for those, for now. We could use
14068 * arm_cpu_get_phys_page_attrs_debug to re-read the page
14069 * table entry even for that case.
14071 return (tlb_hit(entry
->addr_code
, addr
) &&
14072 env_tlb(env
)->d
[mmu_idx
].iotlb
[index
].attrs
.target_tlb_bit0
);
14077 * btype_destination_ok:
14078 * @insn: The instruction at the branch destination
14079 * @bt: SCTLR_ELx.BT
14080 * @btype: PSTATE.BTYPE, and is non-zero
14082 * On a guarded page, there are a limited number of insns
14083 * that may be present at the branch target:
14084 * - branch target identifiers,
14085 * - paciasp, pacibsp,
14088 * Anything else causes a Branch Target Exception.
14090 * Return true if the branch is compatible, false to raise BTITRAP.
14092 static bool btype_destination_ok(uint32_t insn
, bool bt
, int btype
)
14094 if ((insn
& 0xfffff01fu
) == 0xd503201fu
) {
14096 switch (extract32(insn
, 5, 7)) {
14097 case 0b011001: /* PACIASP */
14098 case 0b011011: /* PACIBSP */
14100 * If SCTLR_ELx.BT, then PACI*SP are not compatible
14101 * with btype == 3. Otherwise all btype are ok.
14103 return !bt
|| btype
!= 3;
14104 case 0b100000: /* BTI */
14105 /* Not compatible with any btype. */
14107 case 0b100010: /* BTI c */
14108 /* Not compatible with btype == 3 */
14110 case 0b100100: /* BTI j */
14111 /* Not compatible with btype == 2 */
14113 case 0b100110: /* BTI jc */
14114 /* Compatible with any btype. */
14118 switch (insn
& 0xffe0001fu
) {
14119 case 0xd4200000u
: /* BRK */
14120 case 0xd4400000u
: /* HLT */
14121 /* Give priority to the breakpoint exception. */
14128 /* C3.1 A64 instruction index by encoding */
14129 static void disas_a64_insn(CPUARMState
*env
, DisasContext
*s
)
14133 s
->pc_curr
= s
->base
.pc_next
;
14134 insn
= arm_ldl_code(env
, s
->base
.pc_next
, s
->sctlr_b
);
14136 s
->base
.pc_next
+= 4;
14138 s
->fp_access_checked
= false;
14140 if (dc_isar_feature(aa64_bti
, s
)) {
14141 if (s
->base
.num_insns
== 1) {
14143 * At the first insn of the TB, compute s->guarded_page.
14144 * We delayed computing this until successfully reading
14145 * the first insn of the TB, above. This (mostly) ensures
14146 * that the softmmu tlb entry has been populated, and the
14147 * page table GP bit is available.
14149 * Note that we need to compute this even if btype == 0,
14150 * because this value is used for BR instructions later
14151 * where ENV is not available.
14153 s
->guarded_page
= is_guarded_page(env
, s
);
14155 /* First insn can have btype set to non-zero. */
14156 tcg_debug_assert(s
->btype
>= 0);
14159 * Note that the Branch Target Exception has fairly high
14160 * priority -- below debugging exceptions but above most
14161 * everything else. This allows us to handle this now
14162 * instead of waiting until the insn is otherwise decoded.
14166 && !btype_destination_ok(insn
, s
->bt
, s
->btype
)) {
14167 gen_exception_insn(s
, s
->pc_curr
, EXCP_UDEF
,
14168 syn_btitrap(s
->btype
),
14169 default_exception_el(s
));
14173 /* Not the first insn: btype must be 0. */
14174 tcg_debug_assert(s
->btype
== 0);
14178 switch (extract32(insn
, 25, 4)) {
14179 case 0x0: case 0x1: case 0x3: /* UNALLOCATED */
14180 unallocated_encoding(s
);
14183 if (!dc_isar_feature(aa64_sve
, s
) || !disas_sve(s
, insn
)) {
14184 unallocated_encoding(s
);
14187 case 0x8: case 0x9: /* Data processing - immediate */
14188 disas_data_proc_imm(s
, insn
);
14190 case 0xa: case 0xb: /* Branch, exception generation and system insns */
14191 disas_b_exc_sys(s
, insn
);
14196 case 0xe: /* Loads and stores */
14197 disas_ldst(s
, insn
);
14200 case 0xd: /* Data processing - register */
14201 disas_data_proc_reg(s
, insn
);
14204 case 0xf: /* Data processing - SIMD and floating point */
14205 disas_data_proc_simd_fp(s
, insn
);
14208 assert(FALSE
); /* all 15 cases should be handled above */
14212 /* if we allocated any temporaries, free them here */
14216 * After execution of most insns, btype is reset to 0.
14217 * Note that we set btype == -1 when the insn sets btype.
14219 if (s
->btype
> 0 && s
->base
.is_jmp
!= DISAS_NORETURN
) {
14224 static void aarch64_tr_init_disas_context(DisasContextBase
*dcbase
,
14227 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14228 CPUARMState
*env
= cpu
->env_ptr
;
14229 ARMCPU
*arm_cpu
= env_archcpu(env
);
14230 uint32_t tb_flags
= dc
->base
.tb
->flags
;
14231 int bound
, core_mmu_idx
;
14233 dc
->isar
= &arm_cpu
->isar
;
14237 /* If we are coming from secure EL0 in a system with a 32-bit EL3, then
14238 * there is no secure EL1, so we route exceptions to EL3.
14240 dc
->secure_routed_to_el3
= arm_feature(env
, ARM_FEATURE_EL3
) &&
14241 !arm_el_is_aa64(env
, 3);
14244 dc
->be_data
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, BE_DATA
) ? MO_BE
: MO_LE
;
14245 dc
->condexec_mask
= 0;
14246 dc
->condexec_cond
= 0;
14247 core_mmu_idx
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, MMUIDX
);
14248 dc
->mmu_idx
= core_to_aa64_mmu_idx(core_mmu_idx
);
14249 dc
->tbii
= FIELD_EX32(tb_flags
, TBFLAG_A64
, TBII
);
14250 dc
->tbid
= FIELD_EX32(tb_flags
, TBFLAG_A64
, TBID
);
14251 dc
->tcma
= FIELD_EX32(tb_flags
, TBFLAG_A64
, TCMA
);
14252 dc
->current_el
= arm_mmu_idx_to_el(dc
->mmu_idx
);
14253 #if !defined(CONFIG_USER_ONLY)
14254 dc
->user
= (dc
->current_el
== 0);
14256 dc
->fp_excp_el
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, FPEXC_EL
);
14257 dc
->sve_excp_el
= FIELD_EX32(tb_flags
, TBFLAG_A64
, SVEEXC_EL
);
14258 dc
->sve_len
= (FIELD_EX32(tb_flags
, TBFLAG_A64
, ZCR_LEN
) + 1) * 16;
14259 dc
->pauth_active
= FIELD_EX32(tb_flags
, TBFLAG_A64
, PAUTH_ACTIVE
);
14260 dc
->bt
= FIELD_EX32(tb_flags
, TBFLAG_A64
, BT
);
14261 dc
->btype
= FIELD_EX32(tb_flags
, TBFLAG_A64
, BTYPE
);
14262 dc
->unpriv
= FIELD_EX32(tb_flags
, TBFLAG_A64
, UNPRIV
);
14263 dc
->ata
= FIELD_EX32(tb_flags
, TBFLAG_A64
, ATA
);
14264 dc
->mte_active
[0] = FIELD_EX32(tb_flags
, TBFLAG_A64
, MTE_ACTIVE
);
14265 dc
->mte_active
[1] = FIELD_EX32(tb_flags
, TBFLAG_A64
, MTE0_ACTIVE
);
14267 dc
->vec_stride
= 0;
14268 dc
->cp_regs
= arm_cpu
->cp_regs
;
14269 dc
->features
= env
->features
;
14271 /* Single step state. The code-generation logic here is:
14273 * generate code with no special handling for single-stepping (except
14274 * that anything that can make us go to SS_ACTIVE == 1 must end the TB;
14275 * this happens anyway because those changes are all system register or
14277 * SS_ACTIVE == 1, PSTATE.SS == 1: (active-not-pending)
14278 * emit code for one insn
14279 * emit code to clear PSTATE.SS
14280 * emit code to generate software step exception for completed step
14281 * end TB (as usual for having generated an exception)
14282 * SS_ACTIVE == 1, PSTATE.SS == 0: (active-pending)
14283 * emit code to generate a software step exception
14286 dc
->ss_active
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, SS_ACTIVE
);
14287 dc
->pstate_ss
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, PSTATE_SS
);
14288 dc
->is_ldex
= false;
14289 dc
->debug_target_el
= FIELD_EX32(tb_flags
, TBFLAG_ANY
, DEBUG_TARGET_EL
);
14291 /* Bound the number of insns to execute to those left on the page. */
14292 bound
= -(dc
->base
.pc_first
| TARGET_PAGE_MASK
) / 4;
14294 /* If architectural single step active, limit to 1. */
14295 if (dc
->ss_active
) {
14298 dc
->base
.max_insns
= MIN(dc
->base
.max_insns
, bound
);
14300 init_tmp_a64_array(dc
);
14303 static void aarch64_tr_tb_start(DisasContextBase
*db
, CPUState
*cpu
)
14307 static void aarch64_tr_insn_start(DisasContextBase
*dcbase
, CPUState
*cpu
)
14309 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14311 tcg_gen_insn_start(dc
->base
.pc_next
, 0, 0);
14312 dc
->insn_start
= tcg_last_op();
14315 static bool aarch64_tr_breakpoint_check(DisasContextBase
*dcbase
, CPUState
*cpu
,
14316 const CPUBreakpoint
*bp
)
14318 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14320 if (bp
->flags
& BP_CPU
) {
14321 gen_a64_set_pc_im(dc
->base
.pc_next
);
14322 gen_helper_check_breakpoints(cpu_env
);
14323 /* End the TB early; it likely won't be executed */
14324 dc
->base
.is_jmp
= DISAS_TOO_MANY
;
14326 gen_exception_internal_insn(dc
, dc
->base
.pc_next
, EXCP_DEBUG
);
14327 /* The address covered by the breakpoint must be
14328 included in [tb->pc, tb->pc + tb->size) in order
14329 to for it to be properly cleared -- thus we
14330 increment the PC here so that the logic setting
14331 tb->size below does the right thing. */
14332 dc
->base
.pc_next
+= 4;
14333 dc
->base
.is_jmp
= DISAS_NORETURN
;
14339 static void aarch64_tr_translate_insn(DisasContextBase
*dcbase
, CPUState
*cpu
)
14341 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14342 CPUARMState
*env
= cpu
->env_ptr
;
14344 if (dc
->ss_active
&& !dc
->pstate_ss
) {
14345 /* Singlestep state is Active-pending.
14346 * If we're in this state at the start of a TB then either
14347 * a) we just took an exception to an EL which is being debugged
14348 * and this is the first insn in the exception handler
14349 * b) debug exceptions were masked and we just unmasked them
14350 * without changing EL (eg by clearing PSTATE.D)
14351 * In either case we're going to take a swstep exception in the
14352 * "did not step an insn" case, and so the syndrome ISV and EX
14353 * bits should be zero.
14355 assert(dc
->base
.num_insns
== 1);
14356 gen_swstep_exception(dc
, 0, 0);
14357 dc
->base
.is_jmp
= DISAS_NORETURN
;
14359 disas_a64_insn(env
, dc
);
14362 translator_loop_temp_check(&dc
->base
);
14365 static void aarch64_tr_tb_stop(DisasContextBase
*dcbase
, CPUState
*cpu
)
14367 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14369 if (unlikely(dc
->base
.singlestep_enabled
|| dc
->ss_active
)) {
14370 /* Note that this means single stepping WFI doesn't halt the CPU.
14371 * For conditional branch insns this is harmless unreachable code as
14372 * gen_goto_tb() has already handled emitting the debug exception
14373 * (and thus a tb-jump is not possible when singlestepping).
14375 switch (dc
->base
.is_jmp
) {
14377 gen_a64_set_pc_im(dc
->base
.pc_next
);
14381 if (dc
->base
.singlestep_enabled
) {
14382 gen_exception_internal(EXCP_DEBUG
);
14384 gen_step_complete_exception(dc
);
14387 case DISAS_NORETURN
:
14391 switch (dc
->base
.is_jmp
) {
14393 case DISAS_TOO_MANY
:
14394 gen_goto_tb(dc
, 1, dc
->base
.pc_next
);
14397 case DISAS_UPDATE_EXIT
:
14398 gen_a64_set_pc_im(dc
->base
.pc_next
);
14401 tcg_gen_exit_tb(NULL
, 0);
14403 case DISAS_UPDATE_NOCHAIN
:
14404 gen_a64_set_pc_im(dc
->base
.pc_next
);
14407 tcg_gen_lookup_and_goto_ptr();
14409 case DISAS_NORETURN
:
14413 gen_a64_set_pc_im(dc
->base
.pc_next
);
14414 gen_helper_wfe(cpu_env
);
14417 gen_a64_set_pc_im(dc
->base
.pc_next
);
14418 gen_helper_yield(cpu_env
);
14422 /* This is a special case because we don't want to just halt the CPU
14423 * if trying to debug across a WFI.
14425 TCGv_i32 tmp
= tcg_const_i32(4);
14427 gen_a64_set_pc_im(dc
->base
.pc_next
);
14428 gen_helper_wfi(cpu_env
, tmp
);
14429 tcg_temp_free_i32(tmp
);
14430 /* The helper doesn't necessarily throw an exception, but we
14431 * must go back to the main loop to check for interrupts anyway.
14433 tcg_gen_exit_tb(NULL
, 0);
14440 static void aarch64_tr_disas_log(const DisasContextBase
*dcbase
,
14443 DisasContext
*dc
= container_of(dcbase
, DisasContext
, base
);
14445 qemu_log("IN: %s\n", lookup_symbol(dc
->base
.pc_first
));
14446 log_target_disas(cpu
, dc
->base
.pc_first
, dc
->base
.tb
->size
);
14449 const TranslatorOps aarch64_translator_ops
= {
14450 .init_disas_context
= aarch64_tr_init_disas_context
,
14451 .tb_start
= aarch64_tr_tb_start
,
14452 .insn_start
= aarch64_tr_insn_start
,
14453 .breakpoint_check
= aarch64_tr_breakpoint_check
,
14454 .translate_insn
= aarch64_tr_translate_insn
,
14455 .tb_stop
= aarch64_tr_tb_stop
,
14456 .disas_log
= aarch64_tr_disas_log
,