hw/scsi/esp-pci.c

   1 /*
   2  * QEMU ESP/NCR53C9x emulation
   3  *
   4  * Copyright (c) 2005-2006 Fabrice Bellard
   5  * Copyright (c) 2012 Herve Poussineau
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "qemu/osdep.h"
  27 #include "hw/pci/pci.h"
  28 #include "hw/nvram/eeprom93xx.h"
  29 #include "hw/scsi/esp.h"
  30 #include "trace.h"
  31 #include "qemu/log.h"
  32
  33 #define TYPE_AM53C974_DEVICE "am53c974"
  34
  35 #define PCI_ESP(obj) \
  36     OBJECT_CHECK(PCIESPState, (obj), TYPE_AM53C974_DEVICE)
  37
  38 #define DMA_CMD   0x0
  39 #define DMA_STC   0x1
  40 #define DMA_SPA   0x2
  41 #define DMA_WBC   0x3
  42 #define DMA_WAC   0x4
  43 #define DMA_STAT  0x5
  44 #define DMA_SMDLA 0x6
  45 #define DMA_WMAC  0x7
  46
  47 #define DMA_CMD_MASK   0x03
  48 #define DMA_CMD_DIAG   0x04
  49 #define DMA_CMD_MDL    0x10
  50 #define DMA_CMD_INTE_P 0x20
  51 #define DMA_CMD_INTE_D 0x40
  52 #define DMA_CMD_DIR    0x80
  53
  54 #define DMA_STAT_PWDN    0x01
  55 #define DMA_STAT_ERROR   0x02
  56 #define DMA_STAT_ABORT   0x04
  57 #define DMA_STAT_DONE    0x08
  58 #define DMA_STAT_SCSIINT 0x10
  59 #define DMA_STAT_BCMBLT  0x20
  60
  61 #define SBAC_STATUS 0x1000
  62
  63 typedef struct PCIESPState {
  64     /*< private >*/
  65     PCIDevice parent_obj;
  66     /*< public >*/
  67
  68     MemoryRegion io;
  69     uint32_t dma_regs[8];
  70     uint32_t sbac;
  71     ESPState esp;
  72 } PCIESPState;
  73
  74 static void esp_pci_handle_idle(PCIESPState *pci, uint32_t val)
  75 {
  76     trace_esp_pci_dma_idle(val);
  77     esp_dma_enable(&pci->esp, 0, 0);
  78 }
  79
  80 static void esp_pci_handle_blast(PCIESPState *pci, uint32_t val)
  81 {
  82     trace_esp_pci_dma_blast(val);
  83     qemu_log_mask(LOG_UNIMP, "am53c974: cmd BLAST not implemented\n");
  84 }
  85
  86 static void esp_pci_handle_abort(PCIESPState *pci, uint32_t val)
  87 {
  88     trace_esp_pci_dma_abort(val);
  89     if (pci->esp.current_req) {
  90         scsi_req_cancel(pci->esp.current_req);
  91     }
  92 }
  93
  94 static void esp_pci_handle_start(PCIESPState *pci, uint32_t val)
  95 {
  96     trace_esp_pci_dma_start(val);
  97
  98     pci->dma_regs[DMA_WBC] = pci->dma_regs[DMA_STC];
  99     pci->dma_regs[DMA_WAC] = pci->dma_regs[DMA_SPA];
 100     pci->dma_regs[DMA_WMAC] = pci->dma_regs[DMA_SMDLA];
 101
 102     pci->dma_regs[DMA_STAT] &= ~(DMA_STAT_BCMBLT | DMA_STAT_SCSIINT
 103                                | DMA_STAT_DONE | DMA_STAT_ABORT
 104                                | DMA_STAT_ERROR | DMA_STAT_PWDN);
 105
 106     esp_dma_enable(&pci->esp, 0, 1);
 107 }
 108
 109 static void esp_pci_dma_write(PCIESPState *pci, uint32_t saddr, uint32_t val)
 110 {
 111     trace_esp_pci_dma_write(saddr, pci->dma_regs[saddr], val);
 112     switch (saddr) {
 113     case DMA_CMD:
 114         pci->dma_regs[saddr] = val;
 115         switch (val & DMA_CMD_MASK) {
 116         case 0x0: /* IDLE */
 117             esp_pci_handle_idle(pci, val);
 118             break;
 119         case 0x1: /* BLAST */
 120             esp_pci_handle_blast(pci, val);
 121             break;
 122         case 0x2: /* ABORT */
 123             esp_pci_handle_abort(pci, val);
 124             break;
 125         case 0x3: /* START */
 126             esp_pci_handle_start(pci, val);
 127             break;
 128         default: /* can't happen */
 129             abort();
 130         }
 131         break;
 132     case DMA_STC:
 133     case DMA_SPA:
 134     case DMA_SMDLA:
 135         pci->dma_regs[saddr] = val;
 136         break;
 137     case DMA_STAT:
 138         if (!(pci->sbac & SBAC_STATUS)) {
 139             /* clear some bits on write */
 140             uint32_t mask = DMA_STAT_ERROR | DMA_STAT_ABORT | DMA_STAT_DONE;
 141             pci->dma_regs[DMA_STAT] &= ~(val & mask);
 142         }
 143         break;
 144     default:
 145         trace_esp_pci_error_invalid_write_dma(val, saddr);
 146         return;
 147     }
 148 }
 149
 150 static uint32_t esp_pci_dma_read(PCIESPState *pci, uint32_t saddr)
 151 {
 152     uint32_t val;
 153
 154     val = pci->dma_regs[saddr];
 155     if (saddr == DMA_STAT) {
 156         if (pci->esp.rregs[ESP_RSTAT] & STAT_INT) {
 157             val |= DMA_STAT_SCSIINT;
 158         }
 159         if (pci->sbac & SBAC_STATUS) {
 160             pci->dma_regs[DMA_STAT] &= ~(DMA_STAT_ERROR | DMA_STAT_ABORT |
 161                                          DMA_STAT_DONE);
 162         }
 163     }
 164
 165     trace_esp_pci_dma_read(saddr, val);
 166     return val;
 167 }
 168
 169 static void esp_pci_io_write(void *opaque, hwaddr addr,
 170                              uint64_t val, unsigned int size)
 171 {
 172     PCIESPState *pci = opaque;
 173
 174     if (size < 4 || addr & 3) {
 175         /* need to upgrade request: we only support 4-bytes accesses */
 176         uint32_t current = 0, mask;
 177         int shift;
 178
 179         if (addr < 0x40) {
 180             current = pci->esp.wregs[addr >> 2];
 181         } else if (addr < 0x60) {
 182             current = pci->dma_regs[(addr - 0x40) >> 2];
 183         } else if (addr < 0x74) {
 184             current = pci->sbac;
 185         }
 186
 187         shift = (4 - size) * 8;
 188         mask = (~(uint32_t)0 << shift) >> shift;
 189
 190         shift = ((4 - (addr & 3)) & 3) * 8;
 191         val <<= shift;
 192         val |= current & ~(mask << shift);
 193         addr &= ~3;
 194         size = 4;
 195     }
 196
 197     if (addr < 0x40) {
 198         /* SCSI core reg */
 199         esp_reg_write(&pci->esp, addr >> 2, val);
 200     } else if (addr < 0x60) {
 201         /* PCI DMA CCB */
 202         esp_pci_dma_write(pci, (addr - 0x40) >> 2, val);
 203     } else if (addr == 0x70) {
 204         /* DMA SCSI Bus and control */
 205         trace_esp_pci_sbac_write(pci->sbac, val);
 206         pci->sbac = val;
 207     } else {
 208         trace_esp_pci_error_invalid_write((int)addr);
 209     }
 210 }
 211
 212 static uint64_t esp_pci_io_read(void *opaque, hwaddr addr,
 213                                 unsigned int size)
 214 {
 215     PCIESPState *pci = opaque;
 216     uint32_t ret;
 217
 218     if (addr < 0x40) {
 219         /* SCSI core reg */
 220         ret = esp_reg_read(&pci->esp, addr >> 2);
 221     } else if (addr < 0x60) {
 222         /* PCI DMA CCB */
 223         ret = esp_pci_dma_read(pci, (addr - 0x40) >> 2);
 224     } else if (addr == 0x70) {
 225         /* DMA SCSI Bus and control */
 226         trace_esp_pci_sbac_read(pci->sbac);
 227         ret = pci->sbac;
 228     } else {
 229         /* Invalid region */
 230         trace_esp_pci_error_invalid_read((int)addr);
 231         ret = 0;
 232     }
 233
 234     /* give only requested data */
 235     ret >>= (addr & 3) * 8;
 236     ret &= ~(~(uint64_t)0 << (8 * size));
 237
 238     return ret;
 239 }
 240
 241 static void esp_pci_dma_memory_rw(PCIESPState *pci, uint8_t *buf, int len,
 242                                   DMADirection dir)
 243 {
 244     dma_addr_t addr;
 245     DMADirection expected_dir;
 246
 247     if (pci->dma_regs[DMA_CMD] & DMA_CMD_DIR) {
 248         expected_dir = DMA_DIRECTION_FROM_DEVICE;
 249     } else {
 250         expected_dir = DMA_DIRECTION_TO_DEVICE;
 251     }
 252
 253     if (dir != expected_dir) {
 254         trace_esp_pci_error_invalid_dma_direction();
 255         return;
 256     }
 257
 258     if (pci->dma_regs[DMA_STAT] & DMA_CMD_MDL) {
 259         qemu_log_mask(LOG_UNIMP, "am53c974: MDL transfer not implemented\n");
 260     }
 261
 262     addr = pci->dma_regs[DMA_SPA];
 263     if (pci->dma_regs[DMA_WBC] < len) {
 264         len = pci->dma_regs[DMA_WBC];
 265     }
 266
 267     pci_dma_rw(PCI_DEVICE(pci), addr, buf, len, dir);
 268
 269     /* update status registers */
 270     pci->dma_regs[DMA_WBC] -= len;
 271     pci->dma_regs[DMA_WAC] += len;
 272     if (pci->dma_regs[DMA_WBC] == 0) {
 273         pci->dma_regs[DMA_STAT] |= DMA_STAT_DONE;
 274     }
 275 }
 276
 277 static void esp_pci_dma_memory_read(void *opaque, uint8_t *buf, int len)
 278 {
 279     PCIESPState *pci = opaque;
 280     esp_pci_dma_memory_rw(pci, buf, len, DMA_DIRECTION_TO_DEVICE);
 281 }
 282
 283 static void esp_pci_dma_memory_write(void *opaque, uint8_t *buf, int len)
 284 {
 285     PCIESPState *pci = opaque;
 286     esp_pci_dma_memory_rw(pci, buf, len, DMA_DIRECTION_FROM_DEVICE);
 287 }
 288
 289 static const MemoryRegionOps esp_pci_io_ops = {
 290     .read = esp_pci_io_read,
 291     .write = esp_pci_io_write,
 292     .endianness = DEVICE_LITTLE_ENDIAN,
 293     .impl = {
 294         .min_access_size = 1,
 295         .max_access_size = 4,
 296     },
 297 };
 298
 299 static void esp_pci_hard_reset(DeviceState *dev)
 300 {
 301     PCIESPState *pci = PCI_ESP(dev);
 302     esp_hard_reset(&pci->esp);
 303     pci->dma_regs[DMA_CMD] &= ~(DMA_CMD_DIR | DMA_CMD_INTE_D | DMA_CMD_INTE_P
 304                               | DMA_CMD_MDL | DMA_CMD_DIAG | DMA_CMD_MASK);
 305     pci->dma_regs[DMA_WBC] &= ~0xffff;
 306     pci->dma_regs[DMA_WAC] = 0xffffffff;
 307     pci->dma_regs[DMA_STAT] &= ~(DMA_STAT_BCMBLT | DMA_STAT_SCSIINT
 308                                | DMA_STAT_DONE | DMA_STAT_ABORT
 309                                | DMA_STAT_ERROR);
 310     pci->dma_regs[DMA_WMAC] = 0xfffffffd;
 311 }
 312
 313 static const VMStateDescription vmstate_esp_pci_scsi = {
 314     .name = "pciespscsi",
 315     .version_id = 0,
 316     .minimum_version_id = 0,
 317     .fields = (VMStateField[]) {
 318         VMSTATE_PCI_DEVICE(parent_obj, PCIESPState),
 319         VMSTATE_BUFFER_UNSAFE(dma_regs, PCIESPState, 0, 8 * sizeof(uint32_t)),
 320         VMSTATE_STRUCT(esp, PCIESPState, 0, vmstate_esp, ESPState),
 321         VMSTATE_END_OF_LIST()
 322     }
 323 };
 324
 325 static void esp_pci_command_complete(SCSIRequest *req, uint32_t status,
 326                                      size_t resid)
 327 {
 328     ESPState *s = req->hba_private;
 329     PCIESPState *pci = container_of(s, PCIESPState, esp);
 330
 331     esp_command_complete(req, status, resid);
 332     pci->dma_regs[DMA_WBC] = 0;
 333     pci->dma_regs[DMA_STAT] |= DMA_STAT_DONE;
 334 }
 335
 336 static const struct SCSIBusInfo esp_pci_scsi_info = {
 337     .tcq = false,
 338     .max_target = ESP_MAX_DEVS,
 339     .max_lun = 7,
 340
 341     .transfer_data = esp_transfer_data,
 342     .complete = esp_pci_command_complete,
 343     .cancel = esp_request_cancelled,
 344 };
 345
 346 static void esp_pci_scsi_realize(PCIDevice *dev, Error **errp)
 347 {
 348     PCIESPState *pci = PCI_ESP(dev);
 349     DeviceState *d = DEVICE(dev);
 350     ESPState *s = &pci->esp;
 351     uint8_t *pci_conf;
 352
 353     pci_conf = dev->config;
 354
 355     /* Interrupt pin A */
 356     pci_conf[PCI_INTERRUPT_PIN] = 0x01;
 357
 358     s->dma_memory_read = esp_pci_dma_memory_read;
 359     s->dma_memory_write = esp_pci_dma_memory_write;
 360     s->dma_opaque = pci;
 361     s->chip_id = TCHI_AM53C974;
 362     memory_region_init_io(&pci->io, OBJECT(pci), &esp_pci_io_ops, pci,
 363                           "esp-io", 0x80);
 364
 365     pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->io);
 366     s->irq = pci_allocate_irq(dev);
 367
 368     scsi_bus_new(&s->bus, sizeof(s->bus), d, &esp_pci_scsi_info, NULL);
 369     if (!d->hotplugged) {
 370         scsi_bus_legacy_handle_cmdline(&s->bus, errp);
 371     }
 372 }
 373
 374 static void esp_pci_scsi_uninit(PCIDevice *d)
 375 {
 376     PCIESPState *pci = PCI_ESP(d);
 377
 378     qemu_free_irq(pci->esp.irq);
 379 }
 380
 381 static void esp_pci_class_init(ObjectClass *klass, void *data)
 382 {
 383     DeviceClass *dc = DEVICE_CLASS(klass);
 384     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 385
 386     k->realize = esp_pci_scsi_realize;
 387     k->exit = esp_pci_scsi_uninit;
 388     k->vendor_id = PCI_VENDOR_ID_AMD;
 389     k->device_id = PCI_DEVICE_ID_AMD_SCSI;
 390     k->revision = 0x10;
 391     k->class_id = PCI_CLASS_STORAGE_SCSI;
 392     set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
 393     dc->desc = "AMD Am53c974 PCscsi-PCI SCSI adapter";
 394     dc->reset = esp_pci_hard_reset;
 395     dc->vmsd = &vmstate_esp_pci_scsi;
 396 }
 397
 398 static const TypeInfo esp_pci_info = {
 399     .name = TYPE_AM53C974_DEVICE,
 400     .parent = TYPE_PCI_DEVICE,
 401     .instance_size = sizeof(PCIESPState),
 402     .class_init = esp_pci_class_init,
 403 };
 404
 405 typedef struct {
 406     PCIESPState pci;
 407     eeprom_t *eeprom;
 408 } DC390State;
 409
 410 #define TYPE_DC390_DEVICE "dc390"
 411 #define DC390(obj) \
 412     OBJECT_CHECK(DC390State, obj, TYPE_DC390_DEVICE)
 413
 414 #define EE_ADAPT_SCSI_ID 64
 415 #define EE_MODE2         65
 416 #define EE_DELAY         66
 417 #define EE_TAG_CMD_NUM   67
 418 #define EE_ADAPT_OPTIONS 68
 419 #define EE_BOOT_SCSI_ID  69
 420 #define EE_BOOT_SCSI_LUN 70
 421 #define EE_CHKSUM1       126
 422 #define EE_CHKSUM2       127
 423
 424 #define EE_ADAPT_OPTION_F6_F8_AT_BOOT   0x01
 425 #define EE_ADAPT_OPTION_BOOT_FROM_CDROM 0x02
 426 #define EE_ADAPT_OPTION_INT13           0x04
 427 #define EE_ADAPT_OPTION_SCAM_SUPPORT    0x08
 428
 429
 430 static uint32_t dc390_read_config(PCIDevice *dev, uint32_t addr, int l)
 431 {
 432     DC390State *pci = DC390(dev);
 433     uint32_t val;
 434
 435     val = pci_default_read_config(dev, addr, l);
 436
 437     if (addr == 0x00 && l == 1) {
 438         /* First byte of address space is AND-ed with EEPROM DO line */
 439         if (!eeprom93xx_read(pci->eeprom)) {
 440             val &= ~0xff;
 441         }
 442     }
 443
 444     return val;
 445 }
 446
 447 static void dc390_write_config(PCIDevice *dev,
 448                                uint32_t addr, uint32_t val, int l)
 449 {
 450     DC390State *pci = DC390(dev);
 451     if (addr == 0x80) {
 452         /* EEPROM write */
 453         int eesk = val & 0x80 ? 1 : 0;
 454         int eedi = val & 0x40 ? 1 : 0;
 455         eeprom93xx_write(pci->eeprom, 1, eesk, eedi);
 456     } else if (addr == 0xc0) {
 457         /* EEPROM CS low */
 458         eeprom93xx_write(pci->eeprom, 0, 0, 0);
 459     } else {
 460         pci_default_write_config(dev, addr, val, l);
 461     }
 462 }
 463
 464 static void dc390_scsi_realize(PCIDevice *dev, Error **errp)
 465 {
 466     DC390State *pci = DC390(dev);
 467     Error *err = NULL;
 468     uint8_t *contents;
 469     uint16_t chksum = 0;
 470     int i;
 471
 472     /* init base class */
 473     esp_pci_scsi_realize(dev, &err);
 474     if (err) {
 475         error_propagate(errp, err);
 476         return;
 477     }
 478
 479     /* EEPROM */
 480     pci->eeprom = eeprom93xx_new(DEVICE(dev), 64);
 481
 482     /* set default eeprom values */
 483     contents = (uint8_t *)eeprom93xx_data(pci->eeprom);
 484
 485     for (i = 0; i < 16; i++) {
 486         contents[i * 2] = 0x57;
 487         contents[i * 2 + 1] = 0x00;
 488     }
 489     contents[EE_ADAPT_SCSI_ID] = 7;
 490     contents[EE_MODE2] = 0x0f;
 491     contents[EE_TAG_CMD_NUM] = 0x04;
 492     contents[EE_ADAPT_OPTIONS] = EE_ADAPT_OPTION_F6_F8_AT_BOOT
 493                                | EE_ADAPT_OPTION_BOOT_FROM_CDROM
 494                                | EE_ADAPT_OPTION_INT13;
 495
 496     /* update eeprom checksum */
 497     for (i = 0; i < EE_CHKSUM1; i += 2) {
 498         chksum += contents[i] + (((uint16_t)contents[i + 1]) << 8);
 499     }
 500     chksum = 0x1234 - chksum;
 501     contents[EE_CHKSUM1] = chksum & 0xff;
 502     contents[EE_CHKSUM2] = chksum >> 8;
 503 }
 504
 505 static void dc390_class_init(ObjectClass *klass, void *data)
 506 {
 507     DeviceClass *dc = DEVICE_CLASS(klass);
 508     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 509
 510     k->realize = dc390_scsi_realize;
 511     k->config_read = dc390_read_config;
 512     k->config_write = dc390_write_config;
 513     set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
 514     dc->desc = "Tekram DC-390 SCSI adapter";
 515 }
 516
 517 static const TypeInfo dc390_info = {
 518     .name = "dc390",
 519     .parent = TYPE_AM53C974_DEVICE,
 520     .instance_size = sizeof(DC390State),
 521     .class_init = dc390_class_init,
 522 };
 523
 524 static void esp_pci_register_types(void)
 525 {
 526     type_register_static(&esp_pci_info);
 527     type_register_static(&dc390_info);
 528 }
 529
 530 type_init(esp_pci_register_types)