| blob | 4761d1921e7574ffdd8917ca662402e81ae3deea |
1 # AArch64 SVE instruction descriptions
2 #
3 # Copyright (c) 2017 Linaro, Ltd
4 #
5 # This library is free software; you can redistribute it and/or
6 # modify it under the terms of the GNU Lesser General Public
7 # License as published by the Free Software Foundation; either
8 # version 2 of the License, or (at your option) any later version.
9 #
10 # This library is distributed in the hope that it will be useful,
11 # but WITHOUT ANY WARRANTY; without even the implied warranty of
12 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 # Lesser General Public License for more details.
14 #
15 # You should have received a copy of the GNU Lesser General Public
16 # License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 #
19 # This file is processed by scripts/decodetree.py
20 #
22 ###########################################################################
23 # Named fields. These are primarily for disjoint fields.
25 %imm4_16_p1 16:4 !function=plus1
26 %imm6_22_5 22:1 5:5
27 %imm8_16_10 16:5 10:3
28 %imm9_16_10 16:s6 10:3
30 # A combination of tsz:imm3 -- extract esize.
31 %tszimm_esz 22:2 5:5 !function=tszimm_esz
32 # A combination of tsz:imm3 -- extract (2 * esize) - (tsz:imm3)
33 %tszimm_shr 22:2 5:5 !function=tszimm_shr
34 # A combination of tsz:imm3 -- extract (tsz:imm3) - esize
35 %tszimm_shl 22:2 5:5 !function=tszimm_shl
37 # Similarly for the tszh/tszl pair at 22/16 for zzi
38 %tszimm16_esz 22:2 16:5 !function=tszimm_esz
39 %tszimm16_shr 22:2 16:5 !function=tszimm_shr
40 %tszimm16_shl 22:2 16:5 !function=tszimm_shl
42 # Signed 8-bit immediate, optionally shifted left by 8.
43 %sh8_i8s 5:9 !function=expand_imm_sh8s
45 # Either a copy of rd (at bit 0), or a different source
46 # as propagated via the MOVPRFX instruction.
47 %reg_movprfx 0:5
49 ###########################################################################
50 # Named attribute sets. These are used to make nice(er) names
51 # when creating helpers common to those for the individual
52 # instruction patterns.
54 &rr_esz rd rn esz
55 &rri rd rn imm
56 &rr_dbm rd rn dbm
57 &rrri rd rn rm imm
58 &rri_esz rd rn imm esz
59 &rrr_esz rd rn rm esz
60 &rpr_esz rd pg rn esz
61 &rprr_s rd pg rn rm s
62 &rprr_esz rd pg rn rm esz
63 &rprrr_esz rd pg rn rm ra esz
64 &rpri_esz rd pg rn imm esz
65 &ptrue rd esz pat s
66 &incdec_cnt rd pat esz imm d u
67 &incdec2_cnt rd rn pat esz imm d u
69 ###########################################################################
70 # Named instruction formats. These are generally used to
71 # reduce the amount of duplication between instruction patterns.
73 # Two operand with unused vector element size
74 @pd_pn_e0 ........ ........ ....... rn:4 . rd:4 &rr_esz esz=0
76 # Two operand
77 @pd_pn ........ esz:2 .. .... ....... rn:4 . rd:4 &rr_esz
78 @rd_rn ........ esz:2 ...... ...... rn:5 rd:5 &rr_esz
80 # Three operand with unused vector element size
81 @rd_rn_rm_e0 ........ ... rm:5 ... ... rn:5 rd:5 &rrr_esz esz=0
83 # Three predicate operand, with governing predicate, flag setting
84 @pd_pg_pn_pm_s ........ . s:1 .. rm:4 .. pg:4 . rn:4 . rd:4 &rprr_s
86 # Three operand, vector element size
87 @rd_rn_rm ........ esz:2 . rm:5 ... ... rn:5 rd:5 &rrr_esz
89 # Three operand with "memory" size, aka immediate left shift
90 @rd_rn_msz_rm ........ ... rm:5 .... imm:2 rn:5 rd:5 &rrri
92 # Two register operand, with governing predicate, vector element size
93 @rdn_pg_rm ........ esz:2 ... ... ... pg:3 rm:5 rd:5 \
94 &rprr_esz rn=%reg_movprfx
95 @rdm_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 \
96 &rprr_esz rm=%reg_movprfx
98 # Three register operand, with governing predicate, vector element size
99 @rda_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 rd:5 \
100 &rprrr_esz ra=%reg_movprfx
101 @rdn_pg_ra_rm ........ esz:2 . rm:5 ... pg:3 ra:5 rd:5 \
102 &rprrr_esz rn=%reg_movprfx
104 # One register operand, with governing predicate, vector element size
105 @rd_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 &rpr_esz
107 # Two register operands with a 6-bit signed immediate.
108 @rd_rn_i6 ........ ... rn:5 ..... imm:s6 rd:5 &rri
110 # Two register operand, one immediate operand, with predicate,
111 # element size encoded as TSZHL. User must fill in imm.
112 @rdn_pg_tszimm ........ .. ... ... ... pg:3 ..... rd:5 \
113 &rpri_esz rn=%reg_movprfx esz=%tszimm_esz
115 # Similarly without predicate.
116 @rd_rn_tszimm ........ .. ... ... ...... rn:5 rd:5 \
117 &rri_esz esz=%tszimm16_esz
119 # Two register operand, one immediate operand, with 4-bit predicate.
120 # User must fill in imm.
121 @rdn_pg4 ........ esz:2 .. pg:4 ... ........ rd:5 \
122 &rpri_esz rn=%reg_movprfx
124 # Two register operand, one encoded bitmask.
125 @rdn_dbm ........ .. .... dbm:13 rd:5 \
126 &rr_dbm rn=%reg_movprfx
128 # Basic Load/Store with 9-bit immediate offset
129 @pd_rn_i9 ........ ........ ...... rn:5 . rd:4 \
130 &rri imm=%imm9_16_10
131 @rd_rn_i9 ........ ........ ...... rn:5 rd:5 \
132 &rri imm=%imm9_16_10
134 # One register, pattern, and uint4+1.
135 # User must fill in U and D.
136 @incdec_cnt ........ esz:2 .. .... ...... pat:5 rd:5 \
137 &incdec_cnt imm=%imm4_16_p1
138 @incdec2_cnt ........ esz:2 .. .... ...... pat:5 rd:5 \
139 &incdec2_cnt imm=%imm4_16_p1 rn=%reg_movprfx
141 ###########################################################################
142 # Instruction patterns. Grouped according to the SVE encodingindex.xhtml.
144 ### SVE Integer Arithmetic - Binary Predicated Group
146 # SVE bitwise logical vector operations (predicated)
147 ORR_zpzz 00000100 .. 011 000 000 ... ..... ..... @rdn_pg_rm
148 EOR_zpzz 00000100 .. 011 001 000 ... ..... ..... @rdn_pg_rm
149 AND_zpzz 00000100 .. 011 010 000 ... ..... ..... @rdn_pg_rm
150 BIC_zpzz 00000100 .. 011 011 000 ... ..... ..... @rdn_pg_rm
152 # SVE integer add/subtract vectors (predicated)
153 ADD_zpzz 00000100 .. 000 000 000 ... ..... ..... @rdn_pg_rm
154 SUB_zpzz 00000100 .. 000 001 000 ... ..... ..... @rdn_pg_rm
155 SUB_zpzz 00000100 .. 000 011 000 ... ..... ..... @rdm_pg_rn # SUBR
157 # SVE integer min/max/difference (predicated)
158 SMAX_zpzz 00000100 .. 001 000 000 ... ..... ..... @rdn_pg_rm
159 UMAX_zpzz 00000100 .. 001 001 000 ... ..... ..... @rdn_pg_rm
160 SMIN_zpzz 00000100 .. 001 010 000 ... ..... ..... @rdn_pg_rm
161 UMIN_zpzz 00000100 .. 001 011 000 ... ..... ..... @rdn_pg_rm
162 SABD_zpzz 00000100 .. 001 100 000 ... ..... ..... @rdn_pg_rm
163 UABD_zpzz 00000100 .. 001 101 000 ... ..... ..... @rdn_pg_rm
165 # SVE integer multiply/divide (predicated)
166 MUL_zpzz 00000100 .. 010 000 000 ... ..... ..... @rdn_pg_rm
167 SMULH_zpzz 00000100 .. 010 010 000 ... ..... ..... @rdn_pg_rm
168 UMULH_zpzz 00000100 .. 010 011 000 ... ..... ..... @rdn_pg_rm
169 # Note that divide requires size >= 2; below 2 is unallocated.
170 SDIV_zpzz 00000100 .. 010 100 000 ... ..... ..... @rdn_pg_rm
171 UDIV_zpzz 00000100 .. 010 101 000 ... ..... ..... @rdn_pg_rm
172 SDIV_zpzz 00000100 .. 010 110 000 ... ..... ..... @rdm_pg_rn # SDIVR
173 UDIV_zpzz 00000100 .. 010 111 000 ... ..... ..... @rdm_pg_rn # UDIVR
175 ### SVE Integer Reduction Group
177 # SVE bitwise logical reduction (predicated)
178 ORV 00000100 .. 011 000 001 ... ..... ..... @rd_pg_rn
179 EORV 00000100 .. 011 001 001 ... ..... ..... @rd_pg_rn
180 ANDV 00000100 .. 011 010 001 ... ..... ..... @rd_pg_rn
182 # SVE integer add reduction (predicated)
183 # Note that saddv requires size != 3.
184 UADDV 00000100 .. 000 001 001 ... ..... ..... @rd_pg_rn
185 SADDV 00000100 .. 000 000 001 ... ..... ..... @rd_pg_rn
187 # SVE integer min/max reduction (predicated)
188 SMAXV 00000100 .. 001 000 001 ... ..... ..... @rd_pg_rn
189 UMAXV 00000100 .. 001 001 001 ... ..... ..... @rd_pg_rn
190 SMINV 00000100 .. 001 010 001 ... ..... ..... @rd_pg_rn
191 UMINV 00000100 .. 001 011 001 ... ..... ..... @rd_pg_rn
193 ### SVE Shift by Immediate - Predicated Group
195 # SVE bitwise shift by immediate (predicated)
196 ASR_zpzi 00000100 .. 000 000 100 ... .. ... ..... \
197 @rdn_pg_tszimm imm=%tszimm_shr
198 LSR_zpzi 00000100 .. 000 001 100 ... .. ... ..... \
199 @rdn_pg_tszimm imm=%tszimm_shr
200 LSL_zpzi 00000100 .. 000 011 100 ... .. ... ..... \
201 @rdn_pg_tszimm imm=%tszimm_shl
202 ASRD 00000100 .. 000 100 100 ... .. ... ..... \
203 @rdn_pg_tszimm imm=%tszimm_shr
205 # SVE bitwise shift by vector (predicated)
206 ASR_zpzz 00000100 .. 010 000 100 ... ..... ..... @rdn_pg_rm
207 LSR_zpzz 00000100 .. 010 001 100 ... ..... ..... @rdn_pg_rm
208 LSL_zpzz 00000100 .. 010 011 100 ... ..... ..... @rdn_pg_rm
209 ASR_zpzz 00000100 .. 010 100 100 ... ..... ..... @rdm_pg_rn # ASRR
210 LSR_zpzz 00000100 .. 010 101 100 ... ..... ..... @rdm_pg_rn # LSRR
211 LSL_zpzz 00000100 .. 010 111 100 ... ..... ..... @rdm_pg_rn # LSLR
213 # SVE bitwise shift by wide elements (predicated)
214 # Note these require size != 3.
215 ASR_zpzw 00000100 .. 011 000 100 ... ..... ..... @rdn_pg_rm
216 LSR_zpzw 00000100 .. 011 001 100 ... ..... ..... @rdn_pg_rm
217 LSL_zpzw 00000100 .. 011 011 100 ... ..... ..... @rdn_pg_rm
219 ### SVE Integer Arithmetic - Unary Predicated Group
221 # SVE unary bit operations (predicated)
222 # Note esz != 0 for FABS and FNEG.
223 CLS 00000100 .. 011 000 101 ... ..... ..... @rd_pg_rn
224 CLZ 00000100 .. 011 001 101 ... ..... ..... @rd_pg_rn
225 CNT_zpz 00000100 .. 011 010 101 ... ..... ..... @rd_pg_rn
226 CNOT 00000100 .. 011 011 101 ... ..... ..... @rd_pg_rn
227 NOT_zpz 00000100 .. 011 110 101 ... ..... ..... @rd_pg_rn
228 FABS 00000100 .. 011 100 101 ... ..... ..... @rd_pg_rn
229 FNEG 00000100 .. 011 101 101 ... ..... ..... @rd_pg_rn
231 # SVE integer unary operations (predicated)
232 # Note esz > original size for extensions.
233 ABS 00000100 .. 010 110 101 ... ..... ..... @rd_pg_rn
234 NEG 00000100 .. 010 111 101 ... ..... ..... @rd_pg_rn
235 SXTB 00000100 .. 010 000 101 ... ..... ..... @rd_pg_rn
236 UXTB 00000100 .. 010 001 101 ... ..... ..... @rd_pg_rn
237 SXTH 00000100 .. 010 010 101 ... ..... ..... @rd_pg_rn
238 UXTH 00000100 .. 010 011 101 ... ..... ..... @rd_pg_rn
239 SXTW 00000100 .. 010 100 101 ... ..... ..... @rd_pg_rn
240 UXTW 00000100 .. 010 101 101 ... ..... ..... @rd_pg_rn
242 ### SVE Integer Multiply-Add Group
244 # SVE integer multiply-add writing addend (predicated)
245 MLA 00000100 .. 0 ..... 010 ... ..... ..... @rda_pg_rn_rm
246 MLS 00000100 .. 0 ..... 011 ... ..... ..... @rda_pg_rn_rm
248 # SVE integer multiply-add writing multiplicand (predicated)
249 MLA 00000100 .. 0 ..... 110 ... ..... ..... @rdn_pg_ra_rm # MAD
250 MLS 00000100 .. 0 ..... 111 ... ..... ..... @rdn_pg_ra_rm # MSB
252 ### SVE Integer Arithmetic - Unpredicated Group
254 # SVE integer add/subtract vectors (unpredicated)
255 ADD_zzz 00000100 .. 1 ..... 000 000 ..... ..... @rd_rn_rm
256 SUB_zzz 00000100 .. 1 ..... 000 001 ..... ..... @rd_rn_rm
257 SQADD_zzz 00000100 .. 1 ..... 000 100 ..... ..... @rd_rn_rm
258 UQADD_zzz 00000100 .. 1 ..... 000 101 ..... ..... @rd_rn_rm
259 SQSUB_zzz 00000100 .. 1 ..... 000 110 ..... ..... @rd_rn_rm
260 UQSUB_zzz 00000100 .. 1 ..... 000 111 ..... ..... @rd_rn_rm
262 ### SVE Logical - Unpredicated Group
264 # SVE bitwise logical operations (unpredicated)
265 AND_zzz 00000100 00 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
266 ORR_zzz 00000100 01 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
267 EOR_zzz 00000100 10 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
268 BIC_zzz 00000100 11 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
270 ### SVE Index Generation Group
272 # SVE index generation (immediate start, immediate increment)
273 INDEX_ii 00000100 esz:2 1 imm2:s5 010000 imm1:s5 rd:5
275 # SVE index generation (immediate start, register increment)
276 INDEX_ir 00000100 esz:2 1 rm:5 010010 imm:s5 rd:5
278 # SVE index generation (register start, immediate increment)
279 INDEX_ri 00000100 esz:2 1 imm:s5 010001 rn:5 rd:5
281 # SVE index generation (register start, register increment)
282 INDEX_rr 00000100 .. 1 ..... 010011 ..... ..... @rd_rn_rm
284 ### SVE Stack Allocation Group
286 # SVE stack frame adjustment
287 ADDVL 00000100 001 ..... 01010 ...... ..... @rd_rn_i6
288 ADDPL 00000100 011 ..... 01010 ...... ..... @rd_rn_i6
290 # SVE stack frame size
291 RDVL 00000100 101 11111 01010 imm:s6 rd:5
293 ### SVE Bitwise Shift - Unpredicated Group
295 # SVE bitwise shift by immediate (unpredicated)
296 ASR_zzi 00000100 .. 1 ..... 1001 00 ..... ..... \
297 @rd_rn_tszimm imm=%tszimm16_shr
298 LSR_zzi 00000100 .. 1 ..... 1001 01 ..... ..... \
299 @rd_rn_tszimm imm=%tszimm16_shr
300 LSL_zzi 00000100 .. 1 ..... 1001 11 ..... ..... \
301 @rd_rn_tszimm imm=%tszimm16_shl
303 # SVE bitwise shift by wide elements (unpredicated)
304 # Note esz != 3
305 ASR_zzw 00000100 .. 1 ..... 1000 00 ..... ..... @rd_rn_rm
306 LSR_zzw 00000100 .. 1 ..... 1000 01 ..... ..... @rd_rn_rm
307 LSL_zzw 00000100 .. 1 ..... 1000 11 ..... ..... @rd_rn_rm
309 ### SVE Compute Vector Address Group
311 # SVE vector address generation
312 ADR_s32 00000100 00 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
313 ADR_u32 00000100 01 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
314 ADR_p32 00000100 10 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
315 ADR_p64 00000100 11 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
317 ### SVE Integer Misc - Unpredicated Group
319 # SVE floating-point exponential accelerator
320 # Note esz != 0
321 FEXPA 00000100 .. 1 00000 101110 ..... ..... @rd_rn
323 # SVE floating-point trig select coefficient
324 # Note esz != 0
325 FTSSEL 00000100 .. 1 ..... 101100 ..... ..... @rd_rn_rm
327 ### SVE Element Count Group
329 # SVE element count
330 CNT_r 00000100 .. 10 .... 1110 0 0 ..... ..... @incdec_cnt d=0 u=1
332 # SVE inc/dec register by element count
333 INCDEC_r 00000100 .. 11 .... 1110 0 d:1 ..... ..... @incdec_cnt u=1
335 # SVE saturating inc/dec register by element count
336 SINCDEC_r_32 00000100 .. 10 .... 1111 d:1 u:1 ..... ..... @incdec_cnt
337 SINCDEC_r_64 00000100 .. 11 .... 1111 d:1 u:1 ..... ..... @incdec_cnt
339 # SVE inc/dec vector by element count
340 # Note this requires esz != 0.
341 INCDEC_v 00000100 .. 1 1 .... 1100 0 d:1 ..... ..... @incdec2_cnt u=1
343 # SVE saturating inc/dec vector by element count
344 # Note these require esz != 0.
345 SINCDEC_v 00000100 .. 1 0 .... 1100 d:1 u:1 ..... ..... @incdec2_cnt
347 ### SVE Bitwise Immediate Group
349 # SVE bitwise logical with immediate (unpredicated)
350 ORR_zzi 00000101 00 0000 ............. ..... @rdn_dbm
351 EOR_zzi 00000101 01 0000 ............. ..... @rdn_dbm
352 AND_zzi 00000101 10 0000 ............. ..... @rdn_dbm
354 # SVE broadcast bitmask immediate
355 DUPM 00000101 11 0000 dbm:13 rd:5
357 ### SVE Integer Wide Immediate - Predicated Group
359 # SVE copy floating-point immediate (predicated)
360 FCPY 00000101 .. 01 .... 110 imm:8 ..... @rdn_pg4
362 # SVE copy integer immediate (predicated)
363 CPY_m_i 00000101 .. 01 .... 01 . ........ ..... @rdn_pg4 imm=%sh8_i8s
364 CPY_z_i 00000101 .. 01 .... 00 . ........ ..... @rdn_pg4 imm=%sh8_i8s
366 ### SVE Permute - Extract Group
368 # SVE extract vector (immediate offset)
369 EXT 00000101 001 ..... 000 ... rm:5 rd:5 \
370 &rrri rn=%reg_movprfx imm=%imm8_16_10
372 ### SVE Predicate Logical Operations Group
374 # SVE predicate logical operations
375 AND_pppp 00100101 0. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_pm_s
376 BIC_pppp 00100101 0. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_pm_s
377 EOR_pppp 00100101 0. 00 .... 01 .... 1 .... 0 .... @pd_pg_pn_pm_s
378 SEL_pppp 00100101 0. 00 .... 01 .... 1 .... 1 .... @pd_pg_pn_pm_s
379 ORR_pppp 00100101 1. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_pm_s
380 ORN_pppp 00100101 1. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_pm_s
381 NOR_pppp 00100101 1. 00 .... 01 .... 1 .... 0 .... @pd_pg_pn_pm_s
382 NAND_pppp 00100101 1. 00 .... 01 .... 1 .... 1 .... @pd_pg_pn_pm_s
384 ### SVE Predicate Misc Group
386 # SVE predicate test
387 PTEST 00100101 01 010000 11 pg:4 0 rn:4 0 0000
389 # SVE predicate initialize
390 PTRUE 00100101 esz:2 01100 s:1 111000 pat:5 0 rd:4
392 # SVE initialize FFR
393 SETFFR 00100101 0010 1100 1001 0000 0000 0000
395 # SVE zero predicate register
396 PFALSE 00100101 0001 1000 1110 0100 0000 rd:4
398 # SVE predicate read from FFR (predicated)
399 RDFFR_p 00100101 0 s:1 0110001111000 pg:4 0 rd:4
401 # SVE predicate read from FFR (unpredicated)
402 RDFFR 00100101 0001 1001 1111 0000 0000 rd:4
404 # SVE FFR write from predicate (WRFFR)
405 WRFFR 00100101 0010 1000 1001 000 rn:4 00000
407 # SVE predicate first active
408 PFIRST 00100101 01 011 000 11000 00 .... 0 .... @pd_pn_e0
410 # SVE predicate next active
411 PNEXT 00100101 .. 011 001 11000 10 .... 0 .... @pd_pn
413 ### SVE Memory - 32-bit Gather and Unsized Contiguous Group
415 # SVE load predicate register
416 LDR_pri 10000101 10 ...... 000 ... ..... 0 .... @pd_rn_i9
418 # SVE load vector register
419 LDR_zri 10000101 10 ...... 010 ... ..... ..... @rd_rn_i9