target-arm/machine.c

   1 #include "hw/hw.h"
   2 #include "hw/boards.h"
   3
   4 void cpu_save(QEMUFile *f, void *opaque)
   5 {
   6     int i;
   7     CPUARMState *env = (CPUARMState *)opaque;
   8
   9     for (i = 0; i < 16; i++) {
  10         qemu_put_be32(f, env->regs[i]);
  11     }
  12     qemu_put_be32(f, cpsr_read(env));
  13     qemu_put_be32(f, env->spsr);
  14     for (i = 0; i < 6; i++) {
  15         qemu_put_be32(f, env->banked_spsr[i]);
  16         qemu_put_be32(f, env->banked_r13[i]);
  17         qemu_put_be32(f, env->banked_r14[i]);
  18     }
  19     for (i = 0; i < 5; i++) {
  20         qemu_put_be32(f, env->usr_regs[i]);
  21         qemu_put_be32(f, env->fiq_regs[i]);
  22     }
  23     qemu_put_be32(f, env->cp15.c0_cpuid);
  24     qemu_put_be32(f, env->cp15.c0_cachetype);
  25     qemu_put_be32(f, env->cp15.c0_cssel);
  26     qemu_put_be32(f, env->cp15.c1_sys);
  27     qemu_put_be32(f, env->cp15.c1_coproc);
  28     qemu_put_be32(f, env->cp15.c1_xscaleauxcr);
  29     qemu_put_be32(f, env->cp15.c2_base0);
  30     qemu_put_be32(f, env->cp15.c2_base1);
  31     qemu_put_be32(f, env->cp15.c2_control);
  32     qemu_put_be32(f, env->cp15.c2_mask);
  33     qemu_put_be32(f, env->cp15.c2_base_mask);
  34     qemu_put_be32(f, env->cp15.c2_data);
  35     qemu_put_be32(f, env->cp15.c2_insn);
  36     qemu_put_be32(f, env->cp15.c3);
  37     qemu_put_be32(f, env->cp15.c5_insn);
  38     qemu_put_be32(f, env->cp15.c5_data);
  39     for (i = 0; i < 8; i++) {
  40         qemu_put_be32(f, env->cp15.c6_region[i]);
  41     }
  42     qemu_put_be32(f, env->cp15.c6_insn);
  43     qemu_put_be32(f, env->cp15.c6_data);
  44     qemu_put_be32(f, env->cp15.c7_par);
  45     qemu_put_be32(f, env->cp15.c9_insn);
  46     qemu_put_be32(f, env->cp15.c9_data);
  47     qemu_put_be32(f, env->cp15.c13_fcse);
  48     qemu_put_be32(f, env->cp15.c13_context);
  49     qemu_put_be32(f, env->cp15.c13_tls1);
  50     qemu_put_be32(f, env->cp15.c13_tls2);
  51     qemu_put_be32(f, env->cp15.c13_tls3);
  52     qemu_put_be32(f, env->cp15.c15_cpar);
  53
  54     qemu_put_be32(f, env->features);
  55
  56     if (arm_feature(env, ARM_FEATURE_VFP)) {
  57         for (i = 0;  i < 16; i++) {
  58             CPU_DoubleU u;
  59             u.d = env->vfp.regs[i];
  60             qemu_put_be32(f, u.l.upper);
  61             qemu_put_be32(f, u.l.lower);
  62         }
  63         for (i = 0; i < 16; i++) {
  64             qemu_put_be32(f, env->vfp.xregs[i]);
  65         }
  66
  67         /* TODO: Should use proper FPSCR access functions.  */
  68         qemu_put_be32(f, env->vfp.vec_len);
  69         qemu_put_be32(f, env->vfp.vec_stride);
  70
  71         if (arm_feature(env, ARM_FEATURE_VFP3)) {
  72             for (i = 16;  i < 32; i++) {
  73                 CPU_DoubleU u;
  74                 u.d = env->vfp.regs[i];
  75                 qemu_put_be32(f, u.l.upper);
  76                 qemu_put_be32(f, u.l.lower);
  77             }
  78         }
  79     }
  80
  81     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
  82         for (i = 0; i < 16; i++) {
  83             qemu_put_be64(f, env->iwmmxt.regs[i]);
  84         }
  85         for (i = 0; i < 16; i++) {
  86             qemu_put_be32(f, env->iwmmxt.cregs[i]);
  87         }
  88     }
  89
  90     if (arm_feature(env, ARM_FEATURE_M)) {
  91         qemu_put_be32(f, env->v7m.other_sp);
  92         qemu_put_be32(f, env->v7m.vecbase);
  93         qemu_put_be32(f, env->v7m.basepri);
  94         qemu_put_be32(f, env->v7m.control);
  95         qemu_put_be32(f, env->v7m.current_sp);
  96         qemu_put_be32(f, env->v7m.exception);
  97     }
  98
  99     if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
 100         qemu_put_be32(f, env->teecr);
 101         qemu_put_be32(f, env->teehbr);
 102     }
 103 }
 104
 105 int cpu_load(QEMUFile *f, void *opaque, int version_id)
 106 {
 107     CPUARMState *env = (CPUARMState *)opaque;
 108     int i;
 109     uint32_t val;
 110
 111     if (version_id != CPU_SAVE_VERSION)
 112         return -EINVAL;
 113
 114     for (i = 0; i < 16; i++) {
 115         env->regs[i] = qemu_get_be32(f);
 116     }
 117     val = qemu_get_be32(f);
 118     /* Avoid mode switch when restoring CPSR.  */
 119     env->uncached_cpsr = val & CPSR_M;
 120     cpsr_write(env, val, 0xffffffff);
 121     env->spsr = qemu_get_be32(f);
 122     for (i = 0; i < 6; i++) {
 123         env->banked_spsr[i] = qemu_get_be32(f);
 124         env->banked_r13[i] = qemu_get_be32(f);
 125         env->banked_r14[i] = qemu_get_be32(f);
 126     }
 127     for (i = 0; i < 5; i++) {
 128         env->usr_regs[i] = qemu_get_be32(f);
 129         env->fiq_regs[i] = qemu_get_be32(f);
 130     }
 131     env->cp15.c0_cpuid = qemu_get_be32(f);
 132     env->cp15.c0_cachetype = qemu_get_be32(f);
 133     env->cp15.c0_cssel = qemu_get_be32(f);
 134     env->cp15.c1_sys = qemu_get_be32(f);
 135     env->cp15.c1_coproc = qemu_get_be32(f);
 136     env->cp15.c1_xscaleauxcr = qemu_get_be32(f);
 137     env->cp15.c2_base0 = qemu_get_be32(f);
 138     env->cp15.c2_base1 = qemu_get_be32(f);
 139     env->cp15.c2_control = qemu_get_be32(f);
 140     env->cp15.c2_mask = qemu_get_be32(f);
 141     env->cp15.c2_base_mask = qemu_get_be32(f);
 142     env->cp15.c2_data = qemu_get_be32(f);
 143     env->cp15.c2_insn = qemu_get_be32(f);
 144     env->cp15.c3 = qemu_get_be32(f);
 145     env->cp15.c5_insn = qemu_get_be32(f);
 146     env->cp15.c5_data = qemu_get_be32(f);
 147     for (i = 0; i < 8; i++) {
 148         env->cp15.c6_region[i] = qemu_get_be32(f);
 149     }
 150     env->cp15.c6_insn = qemu_get_be32(f);
 151     env->cp15.c6_data = qemu_get_be32(f);
 152     env->cp15.c7_par = qemu_get_be32(f);
 153     env->cp15.c9_insn = qemu_get_be32(f);
 154     env->cp15.c9_data = qemu_get_be32(f);
 155     env->cp15.c13_fcse = qemu_get_be32(f);
 156     env->cp15.c13_context = qemu_get_be32(f);
 157     env->cp15.c13_tls1 = qemu_get_be32(f);
 158     env->cp15.c13_tls2 = qemu_get_be32(f);
 159     env->cp15.c13_tls3 = qemu_get_be32(f);
 160     env->cp15.c15_cpar = qemu_get_be32(f);
 161
 162     env->features = qemu_get_be32(f);
 163
 164     if (arm_feature(env, ARM_FEATURE_VFP)) {
 165         for (i = 0;  i < 16; i++) {
 166             CPU_DoubleU u;
 167             u.l.upper = qemu_get_be32(f);
 168             u.l.lower = qemu_get_be32(f);
 169             env->vfp.regs[i] = u.d;
 170         }
 171         for (i = 0; i < 16; i++) {
 172             env->vfp.xregs[i] = qemu_get_be32(f);
 173         }
 174
 175         /* TODO: Should use proper FPSCR access functions.  */
 176         env->vfp.vec_len = qemu_get_be32(f);
 177         env->vfp.vec_stride = qemu_get_be32(f);
 178
 179         if (arm_feature(env, ARM_FEATURE_VFP3)) {
 180             for (i = 0;  i < 16; i++) {
 181                 CPU_DoubleU u;
 182                 u.l.upper = qemu_get_be32(f);
 183                 u.l.lower = qemu_get_be32(f);
 184                 env->vfp.regs[i] = u.d;
 185             }
 186         }
 187     }
 188
 189     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 190         for (i = 0; i < 16; i++) {
 191             env->iwmmxt.regs[i] = qemu_get_be64(f);
 192         }
 193         for (i = 0; i < 16; i++) {
 194             env->iwmmxt.cregs[i] = qemu_get_be32(f);
 195         }
 196     }
 197
 198     if (arm_feature(env, ARM_FEATURE_M)) {
 199         env->v7m.other_sp = qemu_get_be32(f);
 200         env->v7m.vecbase = qemu_get_be32(f);
 201         env->v7m.basepri = qemu_get_be32(f);
 202         env->v7m.control = qemu_get_be32(f);
 203         env->v7m.current_sp = qemu_get_be32(f);
 204         env->v7m.exception = qemu_get_be32(f);
 205     }
 206
 207     if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
 208         env->teecr = qemu_get_be32(f);
 209         env->teehbr = qemu_get_be32(f);
 210     }
 211
 212     return 0;
 213 }