disas/mips.c

   1 /* Print mips instructions for GDB, the GNU debugger, or for objdump.
   2    Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
   3    2000, 2001, 2002, 2003
   4    Free Software Foundation, Inc.
   5    Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
   6
   7 This file is part of GDB, GAS, and the GNU binutils.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2 of the License, or
  12 (at your option) any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License
  20 along with this program; if not, see <http://www.gnu.org/licenses/>.  */
  21
  22 #include "qemu/osdep.h"
  23 #include "disas/bfd.h"
  24
  25 /* mips.h.  Mips opcode list for GDB, the GNU debugger.
  26    Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
  27    Free Software Foundation, Inc.
  28    Contributed by Ralph Campbell and OSF
  29    Commented and modified by Ian Lance Taylor, Cygnus Support
  30
  31 This file is part of GDB, GAS, and the GNU binutils.
  32
  33 GDB, GAS, and the GNU binutils are free software; you can redistribute
  34 them and/or modify them under the terms of the GNU General Public
  35 License as published by the Free Software Foundation; either version
  36 1, or (at your option) any later version.
  37
  38 GDB, GAS, and the GNU binutils are distributed in the hope that they
  39 will be useful, but WITHOUT ANY WARRANTY; without even the implied
  40 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  41 the GNU General Public License for more details.
  42
  43 You should have received a copy of the GNU General Public License
  44 along with this file; see the file COPYING.  If not,
  45 see <http://www.gnu.org/licenses/>.  */
  46
  47 /* These are bit masks and shift counts to use to access the various
  48    fields of an instruction.  To retrieve the X field of an
  49    instruction, use the expression
  50         (i >> OP_SH_X) & OP_MASK_X
  51    To set the same field (to j), use
  52         i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)
  53
  54    Make sure you use fields that are appropriate for the instruction,
  55    of course.
  56
  57    The 'i' format uses OP, RS, RT and IMMEDIATE.
  58
  59    The 'j' format uses OP and TARGET.
  60
  61    The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.
  62
  63    The 'b' format uses OP, RS, RT and DELTA.
  64
  65    The floating point 'i' format uses OP, RS, RT and IMMEDIATE.
  66
  67    The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.
  68
  69    A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
  70    breakpoint instruction are not defined; Kane says the breakpoint
  71    code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
  72    only use ten bits).  An optional two-operand form of break/sdbbp
  73    allows the lower ten bits to be set too, and MIPS32 and later
  74    architectures allow 20 bits to be set with a signal operand
  75    (using CODE20).
  76
  77    The syscall instruction uses CODE20.
  78
  79    The general coprocessor instructions use COPZ.  */
  80
  81 #define OP_MASK_OP              0x3f
  82 #define OP_SH_OP                26
  83 #define OP_MASK_RS              0x1f
  84 #define OP_SH_RS                21
  85 #define OP_MASK_FR              0x1f
  86 #define OP_SH_FR                21
  87 #define OP_MASK_FMT             0x1f
  88 #define OP_SH_FMT               21
  89 #define OP_MASK_BCC             0x7
  90 #define OP_SH_BCC               18
  91 #define OP_MASK_CODE            0x3ff
  92 #define OP_SH_CODE              16
  93 #define OP_MASK_CODE2           0x3ff
  94 #define OP_SH_CODE2             6
  95 #define OP_MASK_RT              0x1f
  96 #define OP_SH_RT                16
  97 #define OP_MASK_FT              0x1f
  98 #define OP_SH_FT                16
  99 #define OP_MASK_CACHE           0x1f
 100 #define OP_SH_CACHE             16
 101 #define OP_MASK_RD              0x1f
 102 #define OP_SH_RD                11
 103 #define OP_MASK_FS              0x1f
 104 #define OP_SH_FS                11
 105 #define OP_MASK_PREFX           0x1f
 106 #define OP_SH_PREFX             11
 107 #define OP_MASK_CCC             0x7
 108 #define OP_SH_CCC               8
 109 #define OP_MASK_CODE20          0xfffff /* 20 bit syscall/breakpoint code.  */
 110 #define OP_SH_CODE20            6
 111 #define OP_MASK_SHAMT           0x1f
 112 #define OP_SH_SHAMT             6
 113 #define OP_MASK_FD              0x1f
 114 #define OP_SH_FD                6
 115 #define OP_MASK_TARGET          0x3ffffff
 116 #define OP_SH_TARGET            0
 117 #define OP_MASK_COPZ            0x1ffffff
 118 #define OP_SH_COPZ              0
 119 #define OP_MASK_IMMEDIATE       0xffff
 120 #define OP_SH_IMMEDIATE         0
 121 #define OP_MASK_DELTA           0xffff
 122 #define OP_SH_DELTA             0
 123 #define OP_MASK_DELTA_R6        0x1ff
 124 #define OP_SH_DELTA_R6          7
 125 #define OP_MASK_FUNCT           0x3f
 126 #define OP_SH_FUNCT             0
 127 #define OP_MASK_SPEC            0x3f
 128 #define OP_SH_SPEC              0
 129 #define OP_SH_LOCC              8       /* FP condition code.  */
 130 #define OP_SH_HICC              18      /* FP condition code.  */
 131 #define OP_MASK_CC              0x7
 132 #define OP_SH_COP1NORM          25      /* Normal COP1 encoding.  */
 133 #define OP_MASK_COP1NORM        0x1     /* a single bit.  */
 134 #define OP_SH_COP1SPEC          21      /* COP1 encodings.  */
 135 #define OP_MASK_COP1SPEC        0xf
 136 #define OP_MASK_COP1SCLR        0x4
 137 #define OP_MASK_COP1CMP         0x3
 138 #define OP_SH_COP1CMP           4
 139 #define OP_SH_FORMAT            21      /* FP short format field.  */
 140 #define OP_MASK_FORMAT          0x7
 141 #define OP_SH_TRUE              16
 142 #define OP_MASK_TRUE            0x1
 143 #define OP_SH_GE                17
 144 #define OP_MASK_GE              0x01
 145 #define OP_SH_UNSIGNED          16
 146 #define OP_MASK_UNSIGNED        0x1
 147 #define OP_SH_HINT              16
 148 #define OP_MASK_HINT            0x1f
 149 #define OP_SH_MMI               0       /* Multimedia (parallel) op.  */
 150 #define OP_MASK_MMI             0x3f
 151 #define OP_SH_MMISUB            6
 152 #define OP_MASK_MMISUB          0x1f
 153 #define OP_MASK_PERFREG         0x1f    /* Performance monitoring.  */
 154 #define OP_SH_PERFREG           1
 155 #define OP_SH_SEL               0       /* Coprocessor select field.  */
 156 #define OP_MASK_SEL             0x7     /* The sel field of mfcZ and mtcZ.  */
 157 #define OP_SH_CODE19            6       /* 19 bit wait code.  */
 158 #define OP_MASK_CODE19          0x7ffff
 159 #define OP_SH_ALN               21
 160 #define OP_MASK_ALN             0x7
 161 #define OP_SH_VSEL              21
 162 #define OP_MASK_VSEL            0x1f
 163 #define OP_MASK_VECBYTE         0x7     /* Selector field is really 4 bits,
 164                                            but 0x8-0xf don't select bytes.  */
 165 #define OP_SH_VECBYTE           22
 166 #define OP_MASK_VECALIGN        0x7     /* Vector byte-align (alni.ob) op.  */
 167 #define OP_SH_VECALIGN          21
 168 #define OP_MASK_INSMSB          0x1f    /* "ins" MSB.  */
 169 #define OP_SH_INSMSB            11
 170 #define OP_MASK_EXTMSBD         0x1f    /* "ext" MSBD.  */
 171 #define OP_SH_EXTMSBD           11
 172
 173 #define OP_OP_COP0              0x10
 174 #define OP_OP_COP1              0x11
 175 #define OP_OP_COP2              0x12
 176 #define OP_OP_COP3              0x13
 177 #define OP_OP_LWC1              0x31
 178 #define OP_OP_LWC2              0x32
 179 #define OP_OP_LWC3              0x33    /* a.k.a. pref */
 180 #define OP_OP_LDC1              0x35
 181 #define OP_OP_LDC2              0x36
 182 #define OP_OP_LDC3              0x37    /* a.k.a. ld */
 183 #define OP_OP_SWC1              0x39
 184 #define OP_OP_SWC2              0x3a
 185 #define OP_OP_SWC3              0x3b
 186 #define OP_OP_SDC1              0x3d
 187 #define OP_OP_SDC2              0x3e
 188 #define OP_OP_SDC3              0x3f    /* a.k.a. sd */
 189
 190 /* MIPS DSP ASE */
 191 #define OP_SH_DSPACC            11
 192 #define OP_MASK_DSPACC          0x3
 193 #define OP_SH_DSPACC_S          21
 194 #define OP_MASK_DSPACC_S        0x3
 195 #define OP_SH_DSPSFT            20
 196 #define OP_MASK_DSPSFT          0x3f
 197 #define OP_SH_DSPSFT_7          19
 198 #define OP_MASK_DSPSFT_7        0x7f
 199 #define OP_SH_SA3               21
 200 #define OP_MASK_SA3             0x7
 201 #define OP_SH_SA4               21
 202 #define OP_MASK_SA4             0xf
 203 #define OP_SH_IMM8              16
 204 #define OP_MASK_IMM8            0xff
 205 #define OP_SH_IMM10             16
 206 #define OP_MASK_IMM10           0x3ff
 207 #define OP_SH_WRDSP             11
 208 #define OP_MASK_WRDSP           0x3f
 209 #define OP_SH_RDDSP             16
 210 #define OP_MASK_RDDSP           0x3f
 211 #define OP_SH_BP                11
 212 #define OP_MASK_BP              0x3
 213
 214 /* MIPS MT ASE */
 215 #define OP_SH_MT_U              5
 216 #define OP_MASK_MT_U            0x1
 217 #define OP_SH_MT_H              4
 218 #define OP_MASK_MT_H            0x1
 219 #define OP_SH_MTACC_T           18
 220 #define OP_MASK_MTACC_T         0x3
 221 #define OP_SH_MTACC_D           13
 222 #define OP_MASK_MTACC_D         0x3
 223
 224 /* MSA */
 225 #define OP_MASK_1BIT            0x1
 226 #define OP_SH_1BIT              16
 227 #define OP_MASK_2BIT            0x3
 228 #define OP_SH_2BIT              16
 229 #define OP_MASK_3BIT            0x7
 230 #define OP_SH_3BIT              16
 231 #define OP_MASK_4BIT            0xf
 232 #define OP_SH_4BIT              16
 233 #define OP_MASK_5BIT            0x1f
 234 #define OP_SH_5BIT              16
 235 #define OP_MASK_10BIT           0x3ff
 236 #define OP_SH_10BIT             11
 237 #define OP_MASK_MSACR11         0x1f
 238 #define OP_SH_MSACR11           11
 239 #define OP_MASK_MSACR6          0x1f
 240 #define OP_SH_MSACR6            6
 241 #define OP_MASK_GPR             0x1f
 242 #define OP_SH_GPR               6
 243 #define OP_MASK_1_TO_4          0x3
 244 #define OP_SH_1_TO_4            6
 245
 246 #define OP_OP_COP0              0x10
 247 #define OP_OP_COP1              0x11
 248 #define OP_OP_COP2              0x12
 249 #define OP_OP_COP3              0x13
 250 #define OP_OP_LWC1              0x31
 251 #define OP_OP_LWC2              0x32
 252 #define OP_OP_LWC3              0x33    /* a.k.a. pref */
 253 #define OP_OP_LDC1              0x35
 254 #define OP_OP_LDC2              0x36
 255 #define OP_OP_LDC3              0x37    /* a.k.a. ld */
 256 #define OP_OP_SWC1              0x39
 257 #define OP_OP_SWC2              0x3a
 258 #define OP_OP_SWC3              0x3b
 259 #define OP_OP_SDC1              0x3d
 260 #define OP_OP_SDC2              0x3e
 261 #define OP_OP_SDC3              0x3f    /* a.k.a. sd */
 262
 263 /* Values in the 'VSEL' field.  */
 264 #define MDMX_FMTSEL_IMM_QH      0x1d
 265 #define MDMX_FMTSEL_IMM_OB      0x1e
 266 #define MDMX_FMTSEL_VEC_QH      0x15
 267 #define MDMX_FMTSEL_VEC_OB      0x16
 268
 269 /* UDI */
 270 #define OP_SH_UDI1              6
 271 #define OP_MASK_UDI1            0x1f
 272 #define OP_SH_UDI2              6
 273 #define OP_MASK_UDI2            0x3ff
 274 #define OP_SH_UDI3              6
 275 #define OP_MASK_UDI3            0x7fff
 276 #define OP_SH_UDI4              6
 277 #define OP_MASK_UDI4            0xfffff
 278 /* This structure holds information for a particular instruction.  */
 279
 280 struct mips_opcode
 281 {
 282   /* The name of the instruction.  */
 283   const char *name;
 284   /* A string describing the arguments for this instruction.  */
 285   const char *args;
 286   /* The basic opcode for the instruction.  When assembling, this
 287      opcode is modified by the arguments to produce the actual opcode
 288      that is used.  If pinfo is INSN_MACRO, then this is 0.  */
 289   unsigned long match;
 290   /* If pinfo is not INSN_MACRO, then this is a bit mask for the
 291      relevant portions of the opcode when disassembling.  If the
 292      actual opcode anded with the match field equals the opcode field,
 293      then we have found the correct instruction.  If pinfo is
 294      INSN_MACRO, then this field is the macro identifier.  */
 295   unsigned long mask;
 296   /* For a macro, this is INSN_MACRO.  Otherwise, it is a collection
 297      of bits describing the instruction, notably any relevant hazard
 298      information.  */
 299   unsigned long pinfo;
 300   /* A collection of additional bits describing the instruction. */
 301   unsigned long pinfo2;
 302   /* A collection of bits describing the instruction sets of which this
 303      instruction or macro is a member. */
 304   unsigned long membership;
 305 };
 306
 307 /* These are the characters which may appear in the args field of an
 308    instruction.  They appear in the order in which the fields appear
 309    when the instruction is used.  Commas and parentheses in the args
 310    string are ignored when assembling, and written into the output
 311    when disassembling.
 312
 313    Each of these characters corresponds to a mask field defined above.
 314
 315    "<" 5 bit shift amount (OP_*_SHAMT)
 316    ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
 317    "a" 26 bit target address (OP_*_TARGET)
 318    "b" 5 bit base register (OP_*_RS)
 319    "c" 10 bit breakpoint code (OP_*_CODE)
 320    "d" 5 bit destination register specifier (OP_*_RD)
 321    "h" 5 bit prefx hint (OP_*_PREFX)
 322    "i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
 323    "j" 16 bit signed immediate (OP_*_DELTA)
 324    "k" 5 bit cache opcode in target register position (OP_*_CACHE)
 325        Also used for immediate operands in vr5400 vector insns.
 326    "o" 16 bit signed offset (OP_*_DELTA)
 327    "p" 16 bit PC relative branch target address (OP_*_DELTA)
 328    "q" 10 bit extra breakpoint code (OP_*_CODE2)
 329    "r" 5 bit same register used as both source and target (OP_*_RS)
 330    "s" 5 bit source register specifier (OP_*_RS)
 331    "t" 5 bit target register (OP_*_RT)
 332    "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
 333    "v" 5 bit same register used as both source and destination (OP_*_RS)
 334    "w" 5 bit same register used as both target and destination (OP_*_RT)
 335    "U" 5 bit same destination register in both OP_*_RD and OP_*_RT
 336        (used by clo and clz)
 337    "C" 25 bit coprocessor function code (OP_*_COPZ)
 338    "B" 20 bit syscall/breakpoint function code (OP_*_CODE20)
 339    "J" 19 bit wait function code (OP_*_CODE19)
 340    "x" accept and ignore register name
 341    "z" must be zero register
 342    "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD)
 343    "+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes
 344         LSB (OP_*_SHAMT).
 345         Enforces: 0 <= pos < 32.
 346    "+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB).
 347         Requires that "+A" or "+E" occur first to set position.
 348         Enforces: 0 < (pos+size) <= 32.
 349    "+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD).
 350         Requires that "+A" or "+E" occur first to set position.
 351         Enforces: 0 < (pos+size) <= 32.
 352         (Also used by "dext" w/ different limits, but limits for
 353         that are checked by the M_DEXT macro.)
 354    "+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT).
 355         Enforces: 32 <= pos < 64.
 356    "+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB).
 357         Requires that "+A" or "+E" occur first to set position.
 358         Enforces: 32 < (pos+size) <= 64.
 359    "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD).
 360         Requires that "+A" or "+E" occur first to set position.
 361         Enforces: 32 < (pos+size) <= 64.
 362    "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD).
 363         Requires that "+A" or "+E" occur first to set position.
 364         Enforces: 32 < (pos+size) <= 64.
 365
 366    Floating point instructions:
 367    "D" 5 bit destination register (OP_*_FD)
 368    "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
 369    "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up)
 370    "S" 5 bit fs source 1 register (OP_*_FS)
 371    "T" 5 bit ft source 2 register (OP_*_FT)
 372    "R" 5 bit fr source 3 register (OP_*_FR)
 373    "V" 5 bit same register used as floating source and destination (OP_*_FS)
 374    "W" 5 bit same register used as floating target and destination (OP_*_FT)
 375
 376    Coprocessor instructions:
 377    "E" 5 bit target register (OP_*_RT)
 378    "G" 5 bit destination register (OP_*_RD)
 379    "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL)
 380    "P" 5 bit performance-monitor register (OP_*_PERFREG)
 381    "e" 5 bit vector register byte specifier (OP_*_VECBYTE)
 382    "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
 383    see also "k" above
 384    "+D" Combined destination register ("G") and sel ("H") for CP0 ops,
 385         for pretty-printing in disassembly only.
 386
 387    Macro instructions:
 388    "A" General 32 bit expression
 389    "I" 32 bit immediate (value placed in imm_expr).
 390    "+I" 32 bit immediate (value placed in imm2_expr).
 391    "F" 64 bit floating point constant in .rdata
 392    "L" 64 bit floating point constant in .lit8
 393    "f" 32 bit floating point constant
 394    "l" 32 bit floating point constant in .lit4
 395
 396    MDMX instruction operands (note that while these use the FP register
 397    fields, they accept both $fN and $vN names for the registers):
 398    "O"  MDMX alignment offset (OP_*_ALN)
 399    "Q"  MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT)
 400    "X"  MDMX destination register (OP_*_FD)
 401    "Y"  MDMX source register (OP_*_FS)
 402    "Z"  MDMX source register (OP_*_FT)
 403
 404    DSP ASE usage:
 405    "2" 2 bit unsigned immediate for byte align (OP_*_BP)
 406    "3" 3 bit unsigned immediate (OP_*_SA3)
 407    "4" 4 bit unsigned immediate (OP_*_SA4)
 408    "5" 8 bit unsigned immediate (OP_*_IMM8)
 409    "6" 5 bit unsigned immediate (OP_*_RS)
 410    "7" 2 bit dsp accumulator register (OP_*_DSPACC)
 411    "8" 6 bit unsigned immediate (OP_*_WRDSP)
 412    "9" 2 bit dsp accumulator register (OP_*_DSPACC_S)
 413    "0" 6 bit signed immediate (OP_*_DSPSFT)
 414    ":" 7 bit signed immediate (OP_*_DSPSFT_7)
 415    "'" 6 bit unsigned immediate (OP_*_RDDSP)
 416    "@" 10 bit signed immediate (OP_*_IMM10)
 417
 418    MT ASE usage:
 419    "!" 1 bit usermode flag (OP_*_MT_U)
 420    "$" 1 bit load high flag (OP_*_MT_H)
 421    "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T)
 422    "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D)
 423    "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD)
 424    "+t" 5 bit coprocessor 0 destination register (OP_*_RT)
 425    "+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only
 426
 427    UDI immediates:
 428    "+1" UDI immediate bits 6-10
 429    "+2" UDI immediate bits 6-15
 430    "+3" UDI immediate bits 6-20
 431    "+4" UDI immediate bits 6-25
 432
 433    R6 immediates/displacements :
 434    (adding suffix to 'o' to avoid adding new characters)
 435    "+o"  9 bits immediate/displacement (shift = 7)
 436    "+o1" 18 bits immediate/displacement (shift = 0)
 437    "+o2" 19 bits immediate/displacement (shift = 0)
 438
 439    Other:
 440    "()" parens surrounding optional value
 441    ","  separates operands
 442    "[]" brackets around index for vector-op scalar operand specifier (vr5400)
 443    "+"  Start of extension sequence.
 444
 445    Characters used so far, for quick reference when adding more:
 446    "234567890"
 447    "%[]<>(),+:'@!$*&"
 448    "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
 449    "abcdefghijklopqrstuvwxz"
 450
 451    Extension character sequences used so far ("+" followed by the
 452    following), for quick reference when adding more:
 453    "1234"
 454    "ABCDEFGHIT"
 455    "t"
 456 */
 457
 458 /* These are the bits which may be set in the pinfo field of an
 459    instructions, if it is not equal to INSN_MACRO.  */
 460
 461 /* Modifies the general purpose register in OP_*_RD.  */
 462 #define INSN_WRITE_GPR_D            0x00000001
 463 /* Modifies the general purpose register in OP_*_RT.  */
 464 #define INSN_WRITE_GPR_T            0x00000002
 465 /* Modifies general purpose register 31.  */
 466 #define INSN_WRITE_GPR_31           0x00000004
 467 /* Modifies the floating point register in OP_*_FD.  */
 468 #define INSN_WRITE_FPR_D            0x00000008
 469 /* Modifies the floating point register in OP_*_FS.  */
 470 #define INSN_WRITE_FPR_S            0x00000010
 471 /* Modifies the floating point register in OP_*_FT.  */
 472 #define INSN_WRITE_FPR_T            0x00000020
 473 /* Reads the general purpose register in OP_*_RS.  */
 474 #define INSN_READ_GPR_S             0x00000040
 475 /* Reads the general purpose register in OP_*_RT.  */
 476 #define INSN_READ_GPR_T             0x00000080
 477 /* Reads the floating point register in OP_*_FS.  */
 478 #define INSN_READ_FPR_S             0x00000100
 479 /* Reads the floating point register in OP_*_FT.  */
 480 #define INSN_READ_FPR_T             0x00000200
 481 /* Reads the floating point register in OP_*_FR.  */
 482 #define INSN_READ_FPR_R             0x00000400
 483 /* Modifies coprocessor condition code.  */
 484 #define INSN_WRITE_COND_CODE        0x00000800
 485 /* Reads coprocessor condition code.  */
 486 #define INSN_READ_COND_CODE         0x00001000
 487 /* TLB operation.  */
 488 #define INSN_TLB                    0x00002000
 489 /* Reads coprocessor register other than floating point register.  */
 490 #define INSN_COP                    0x00004000
 491 /* Instruction loads value from memory, requiring delay.  */
 492 #define INSN_LOAD_MEMORY_DELAY      0x00008000
 493 /* Instruction loads value from coprocessor, requiring delay.  */
 494 #define INSN_LOAD_COPROC_DELAY      0x00010000
 495 /* Instruction has unconditional branch delay slot.  */
 496 #define INSN_UNCOND_BRANCH_DELAY    0x00020000
 497 /* Instruction has conditional branch delay slot.  */
 498 #define INSN_COND_BRANCH_DELAY      0x00040000
 499 /* Conditional branch likely: if branch not taken, insn nullified.  */
 500 #define INSN_COND_BRANCH_LIKELY     0x00080000
 501 /* Moves to coprocessor register, requiring delay.  */
 502 #define INSN_COPROC_MOVE_DELAY      0x00100000
 503 /* Loads coprocessor register from memory, requiring delay.  */
 504 #define INSN_COPROC_MEMORY_DELAY    0x00200000
 505 /* Reads the HI register.  */
 506 #define INSN_READ_HI                0x00400000
 507 /* Reads the LO register.  */
 508 #define INSN_READ_LO                0x00800000
 509 /* Modifies the HI register.  */
 510 #define INSN_WRITE_HI               0x01000000
 511 /* Modifies the LO register.  */
 512 #define INSN_WRITE_LO               0x02000000
 513 /* Takes a trap (easier to keep out of delay slot).  */
 514 #define INSN_TRAP                   0x04000000
 515 /* Instruction stores value into memory.  */
 516 #define INSN_STORE_MEMORY           0x08000000
 517 /* Instruction uses single precision floating point.  */
 518 #define FP_S                        0x10000000
 519 /* Instruction uses double precision floating point.  */
 520 #define FP_D                        0x20000000
 521 /* Instruction is part of the tx39's integer multiply family.    */
 522 #define INSN_MULT                   0x40000000
 523 /* Instruction synchronize shared memory.  */
 524 #define INSN_SYNC                   0x80000000
 525
 526 /* These are the bits which may be set in the pinfo2 field of an
 527    instruction. */
 528
 529 /* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */
 530 #define INSN2_ALIAS                 0x00000001
 531 /* Instruction reads MDMX accumulator. */
 532 #define INSN2_READ_MDMX_ACC         0x00000002
 533 /* Instruction writes MDMX accumulator. */
 534 #define INSN2_WRITE_MDMX_ACC        0x00000004
 535
 536 /* Reads the general purpose register in OP_*_RD.  */
 537 #define INSN2_READ_GPR_D    0x00000200
 538
 539 /* Instruction is actually a macro.  It should be ignored by the
 540    disassembler, and requires special treatment by the assembler.  */
 541 #define INSN_MACRO                  0xffffffff
 542
 543 /* Masks used to mark instructions to indicate which MIPS ISA level
 544    they were introduced in.  ISAs, as defined below, are logical
 545    ORs of these bits, indicating that they support the instructions
 546    defined at the given level.  */
 547
 548 #define INSN_ISA_MASK             0x00000fff
 549 #define INSN_ISA1                 0x00000001
 550 #define INSN_ISA2                 0x00000002
 551 #define INSN_ISA3                 0x00000004
 552 #define INSN_ISA4                 0x00000008
 553 #define INSN_ISA5                 0x00000010
 554 #define INSN_ISA32                0x00000020
 555 #define INSN_ISA64                0x00000040
 556 #define INSN_ISA32R2              0x00000080
 557 #define INSN_ISA64R2              0x00000100
 558 #define INSN_ISA32R6              0x00000200
 559 #define INSN_ISA64R6              0x00000400
 560
 561 /* Masks used for MIPS-defined ASEs.  */
 562 #define INSN_ASE_MASK             0x0000f000
 563
 564 /* DSP ASE */
 565 #define INSN_DSP                  0x00001000
 566 #define INSN_DSP64                0x00002000
 567 /* MIPS 16 ASE */
 568 #define INSN_MIPS16               0x00004000
 569 /* MIPS-3D ASE */
 570 #define INSN_MIPS3D               0x00008000
 571
 572 /* Chip specific instructions.  These are bitmasks.  */
 573
 574 /* MIPS R4650 instruction.  */
 575 #define INSN_4650                 0x00010000
 576 /* LSI R4010 instruction.  */
 577 #define INSN_4010                 0x00020000
 578 /* NEC VR4100 instruction.  */
 579 #define INSN_4100                 0x00040000
 580 /* Toshiba R3900 instruction.  */
 581 #define INSN_3900                 0x00080000
 582 /* MIPS R10000 instruction.  */
 583 #define INSN_10000                0x00100000
 584 /* Broadcom SB-1 instruction.  */
 585 #define INSN_SB1                  0x00200000
 586 /* NEC VR4111/VR4181 instruction.  */
 587 #define INSN_4111                 0x00400000
 588 /* NEC VR4120 instruction.  */
 589 #define INSN_4120                 0x00800000
 590 /* NEC VR5400 instruction.  */
 591 #define INSN_5400                 0x01000000
 592 /* NEC VR5500 instruction.  */
 593 #define INSN_5500                 0x02000000
 594
 595 /* MDMX ASE */
 596 #define INSN_MDMX                 0x00000000    /* Deprecated */
 597
 598 /* MIPS MSA Extension */
 599 #define INSN_MSA                  0x04000000
 600 #define INSN_MSA64                0x04000000
 601
 602 /* MT ASE */
 603 #define INSN_MT                   0x08000000
 604 /* SmartMIPS ASE  */
 605 #define INSN_SMARTMIPS            0x10000000
 606 /* DSP R2 ASE  */
 607 #define INSN_DSPR2                0x20000000
 608
 609 /* ST Microelectronics Loongson 2E.  */
 610 #define INSN_LOONGSON_2E          0x40000000
 611 /* ST Microelectronics Loongson 2F.  */
 612 #define INSN_LOONGSON_2F          0x80000000
 613
 614 /* MIPS ISA defines, use instead of hardcoding ISA level.  */
 615
 616 #define       ISA_UNKNOWN     0               /* Gas internal use.  */
 617 #define       ISA_MIPS1       (INSN_ISA1)
 618 #define       ISA_MIPS2       (ISA_MIPS1 | INSN_ISA2)
 619 #define       ISA_MIPS3       (ISA_MIPS2 | INSN_ISA3)
 620 #define       ISA_MIPS4       (ISA_MIPS3 | INSN_ISA4)
 621 #define       ISA_MIPS5       (ISA_MIPS4 | INSN_ISA5)
 622
 623 #define       ISA_MIPS32      (ISA_MIPS2 | INSN_ISA32)
 624 #define       ISA_MIPS64      (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64)
 625
 626 #define       ISA_MIPS32R2    (ISA_MIPS32 | INSN_ISA32R2)
 627 #define       ISA_MIPS64R2    (ISA_MIPS64 | INSN_ISA32R2 | INSN_ISA64R2)
 628
 629 #define       ISA_MIPS32R6    (ISA_MIPS32R2 | INSN_ISA32R6)
 630 #define       ISA_MIPS64R6    (ISA_MIPS64R2 | INSN_ISA32R6 | INSN_ISA64R6)
 631
 632 /* CPU defines, use instead of hardcoding processor number. Keep this
 633    in sync with bfd/archures.c in order for machine selection to work.  */
 634 #define CPU_UNKNOWN     0               /* Gas internal use.  */
 635 #define CPU_R3000       3000
 636 #define CPU_R3900       3900
 637 #define CPU_R4000       4000
 638 #define CPU_R4010       4010
 639 #define CPU_VR4100      4100
 640 #define CPU_R4111       4111
 641 #define CPU_VR4120      4120
 642 #define CPU_R4300       4300
 643 #define CPU_R4400       4400
 644 #define CPU_R4600       4600
 645 #define CPU_R4650       4650
 646 #define CPU_R5000       5000
 647 #define CPU_VR5400      5400
 648 #define CPU_VR5500      5500
 649 #define CPU_R6000       6000
 650 #define CPU_RM7000      7000
 651 #define CPU_R8000       8000
 652 #define CPU_R10000      10000
 653 #define CPU_R12000      12000
 654 #define CPU_MIPS16      16
 655 #define CPU_MIPS32      32
 656 #define CPU_MIPS32R2    33
 657 #define CPU_MIPS5       5
 658 #define CPU_MIPS64      64
 659 #define CPU_MIPS64R2    65
 660 #define CPU_SB1         12310201        /* octal 'SB', 01.  */
 661
 662 /* Test for membership in an ISA including chip specific ISAs.  INSN
 663    is pointer to an element of the opcode table; ISA is the specified
 664    ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
 665    test, or zero if no CPU specific ISA test is desired.  */
 666
 667 #if 0
 668 #define OPCODE_IS_MEMBER(insn, isa, cpu)                                \
 669     (((insn)->membership & isa) != 0                                    \
 670      || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0)     \
 671      || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0)    \
 672      || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0)    \
 673      || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0)     \
 674      || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0)    \
 675      || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0)     \
 676      || ((cpu == CPU_R10000 || cpu == CPU_R12000)                       \
 677          && ((insn)->membership & INSN_10000) != 0)                     \
 678      || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0)        \
 679      || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0)     \
 680      || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0)    \
 681      || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0)    \
 682      || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0)    \
 683      || 0)      /* Please keep this term for easier source merging.  */
 684 #else
 685 #define OPCODE_IS_MEMBER(insn, isa, cpu)                               \
 686     (1 != 0)
 687 #endif
 688
 689 /* This is a list of macro expanded instructions.
 690
 691    _I appended means immediate
 692    _A appended means address
 693    _AB appended means address with base register
 694    _D appended means 64 bit floating point constant
 695    _S appended means 32 bit floating point constant.  */
 696
 697 enum
 698 {
 699   M_ABS,
 700   M_ADD_I,
 701   M_ADDU_I,
 702   M_AND_I,
 703   M_BALIGN,
 704   M_BEQ,
 705   M_BEQ_I,
 706   M_BEQL_I,
 707   M_BGE,
 708   M_BGEL,
 709   M_BGE_I,
 710   M_BGEL_I,
 711   M_BGEU,
 712   M_BGEUL,
 713   M_BGEU_I,
 714   M_BGEUL_I,
 715   M_BGT,
 716   M_BGTL,
 717   M_BGT_I,
 718   M_BGTL_I,
 719   M_BGTU,
 720   M_BGTUL,
 721   M_BGTU_I,
 722   M_BGTUL_I,
 723   M_BLE,
 724   M_BLEL,
 725   M_BLE_I,
 726   M_BLEL_I,
 727   M_BLEU,
 728   M_BLEUL,
 729   M_BLEU_I,
 730   M_BLEUL_I,
 731   M_BLT,
 732   M_BLTL,
 733   M_BLT_I,
 734   M_BLTL_I,
 735   M_BLTU,
 736   M_BLTUL,
 737   M_BLTU_I,
 738   M_BLTUL_I,
 739   M_BNE,
 740   M_BNE_I,
 741   M_BNEL_I,
 742   M_CACHE_AB,
 743   M_DABS,
 744   M_DADD_I,
 745   M_DADDU_I,
 746   M_DDIV_3,
 747   M_DDIV_3I,
 748   M_DDIVU_3,
 749   M_DDIVU_3I,
 750   M_DEXT,
 751   M_DINS,
 752   M_DIV_3,
 753   M_DIV_3I,
 754   M_DIVU_3,
 755   M_DIVU_3I,
 756   M_DLA_AB,
 757   M_DLCA_AB,
 758   M_DLI,
 759   M_DMUL,
 760   M_DMUL_I,
 761   M_DMULO,
 762   M_DMULO_I,
 763   M_DMULOU,
 764   M_DMULOU_I,
 765   M_DREM_3,
 766   M_DREM_3I,
 767   M_DREMU_3,
 768   M_DREMU_3I,
 769   M_DSUB_I,
 770   M_DSUBU_I,
 771   M_DSUBU_I_2,
 772   M_J_A,
 773   M_JAL_1,
 774   M_JAL_2,
 775   M_JAL_A,
 776   M_L_DOB,
 777   M_L_DAB,
 778   M_LA_AB,
 779   M_LB_A,
 780   M_LB_AB,
 781   M_LBU_A,
 782   M_LBU_AB,
 783   M_LCA_AB,
 784   M_LD_A,
 785   M_LD_OB,
 786   M_LD_AB,
 787   M_LDC1_AB,
 788   M_LDC2_AB,
 789   M_LDC3_AB,
 790   M_LDL_AB,
 791   M_LDR_AB,
 792   M_LH_A,
 793   M_LH_AB,
 794   M_LHU_A,
 795   M_LHU_AB,
 796   M_LI,
 797   M_LI_D,
 798   M_LI_DD,
 799   M_LI_S,
 800   M_LI_SS,
 801   M_LL_AB,
 802   M_LLD_AB,
 803   M_LS_A,
 804   M_LW_A,
 805   M_LW_AB,
 806   M_LWC0_A,
 807   M_LWC0_AB,
 808   M_LWC1_A,
 809   M_LWC1_AB,
 810   M_LWC2_A,
 811   M_LWC2_AB,
 812   M_LWC3_A,
 813   M_LWC3_AB,
 814   M_LWL_A,
 815   M_LWL_AB,
 816   M_LWR_A,
 817   M_LWR_AB,
 818   M_LWU_AB,
 819   M_MOVE,
 820   M_MUL,
 821   M_MUL_I,
 822   M_MULO,
 823   M_MULO_I,
 824   M_MULOU,
 825   M_MULOU_I,
 826   M_NOR_I,
 827   M_OR_I,
 828   M_REM_3,
 829   M_REM_3I,
 830   M_REMU_3,
 831   M_REMU_3I,
 832   M_DROL,
 833   M_ROL,
 834   M_DROL_I,
 835   M_ROL_I,
 836   M_DROR,
 837   M_ROR,
 838   M_DROR_I,
 839   M_ROR_I,
 840   M_S_DA,
 841   M_S_DOB,
 842   M_S_DAB,
 843   M_S_S,
 844   M_SC_AB,
 845   M_SCD_AB,
 846   M_SD_A,
 847   M_SD_OB,
 848   M_SD_AB,
 849   M_SDC1_AB,
 850   M_SDC2_AB,
 851   M_SDC3_AB,
 852   M_SDL_AB,
 853   M_SDR_AB,
 854   M_SEQ,
 855   M_SEQ_I,
 856   M_SGE,
 857   M_SGE_I,
 858   M_SGEU,
 859   M_SGEU_I,
 860   M_SGT,
 861   M_SGT_I,
 862   M_SGTU,
 863   M_SGTU_I,
 864   M_SLE,
 865   M_SLE_I,
 866   M_SLEU,
 867   M_SLEU_I,
 868   M_SLT_I,
 869   M_SLTU_I,
 870   M_SNE,
 871   M_SNE_I,
 872   M_SB_A,
 873   M_SB_AB,
 874   M_SH_A,
 875   M_SH_AB,
 876   M_SW_A,
 877   M_SW_AB,
 878   M_SWC0_A,
 879   M_SWC0_AB,
 880   M_SWC1_A,
 881   M_SWC1_AB,
 882   M_SWC2_A,
 883   M_SWC2_AB,
 884   M_SWC3_A,
 885   M_SWC3_AB,
 886   M_SWL_A,
 887   M_SWL_AB,
 888   M_SWR_A,
 889   M_SWR_AB,
 890   M_SUB_I,
 891   M_SUBU_I,
 892   M_SUBU_I_2,
 893   M_TEQ_I,
 894   M_TGE_I,
 895   M_TGEU_I,
 896   M_TLT_I,
 897   M_TLTU_I,
 898   M_TNE_I,
 899   M_TRUNCWD,
 900   M_TRUNCWS,
 901   M_ULD,
 902   M_ULD_A,
 903   M_ULH,
 904   M_ULH_A,
 905   M_ULHU,
 906   M_ULHU_A,
 907   M_ULW,
 908   M_ULW_A,
 909   M_USH,
 910   M_USH_A,
 911   M_USW,
 912   M_USW_A,
 913   M_USD,
 914   M_USD_A,
 915   M_XOR_I,
 916   M_COP0,
 917   M_COP1,
 918   M_COP2,
 919   M_COP3,
 920   M_NUM_MACROS
 921 };
 922
 923
 924 /* The order of overloaded instructions matters.  Label arguments and
 925    register arguments look the same. Instructions that can have either
 926    for arguments must apear in the correct order in this table for the
 927    assembler to pick the right one. In other words, entries with
 928    immediate operands must apear after the same instruction with
 929    registers.
 930
 931    Many instructions are short hand for other instructions (i.e., The
 932    jal <register> instruction is short for jalr <register>).  */
 933
 934 extern const struct mips_opcode mips_builtin_opcodes[];
 935 extern const int bfd_mips_num_builtin_opcodes;
 936 extern struct mips_opcode *mips_opcodes;
 937 extern int bfd_mips_num_opcodes;
 938 #define NUMOPCODES bfd_mips_num_opcodes
 939
 940 \f
 941 /* The rest of this file adds definitions for the mips16 TinyRISC
 942    processor.  */
 943
 944 /* These are the bitmasks and shift counts used for the different
 945    fields in the instruction formats.  Other than OP, no masks are
 946    provided for the fixed portions of an instruction, since they are
 947    not needed.
 948
 949    The I format uses IMM11.
 950
 951    The RI format uses RX and IMM8.
 952
 953    The RR format uses RX, and RY.
 954
 955    The RRI format uses RX, RY, and IMM5.
 956
 957    The RRR format uses RX, RY, and RZ.
 958
 959    The RRI_A format uses RX, RY, and IMM4.
 960
 961    The SHIFT format uses RX, RY, and SHAMT.
 962
 963    The I8 format uses IMM8.
 964
 965    The I8_MOVR32 format uses RY and REGR32.
 966
 967    The IR_MOV32R format uses REG32R and MOV32Z.
 968
 969    The I64 format uses IMM8.
 970
 971    The RI64 format uses RY and IMM5.
 972    */
 973
 974 #define MIPS16OP_MASK_OP        0x1f
 975 #define MIPS16OP_SH_OP          11
 976 #define MIPS16OP_MASK_IMM11     0x7ff
 977 #define MIPS16OP_SH_IMM11       0
 978 #define MIPS16OP_MASK_RX        0x7
 979 #define MIPS16OP_SH_RX          8
 980 #define MIPS16OP_MASK_IMM8      0xff
 981 #define MIPS16OP_SH_IMM8        0
 982 #define MIPS16OP_MASK_RY        0x7
 983 #define MIPS16OP_SH_RY          5
 984 #define MIPS16OP_MASK_IMM5      0x1f
 985 #define MIPS16OP_SH_IMM5        0
 986 #define MIPS16OP_MASK_RZ        0x7
 987 #define MIPS16OP_SH_RZ          2
 988 #define MIPS16OP_MASK_IMM4      0xf
 989 #define MIPS16OP_SH_IMM4        0
 990 #define MIPS16OP_MASK_REGR32    0x1f
 991 #define MIPS16OP_SH_REGR32      0
 992 #define MIPS16OP_MASK_REG32R    0x1f
 993 #define MIPS16OP_SH_REG32R      3
 994 #define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18))
 995 #define MIPS16OP_MASK_MOVE32Z   0x7
 996 #define MIPS16OP_SH_MOVE32Z     0
 997 #define MIPS16OP_MASK_IMM6      0x3f
 998 #define MIPS16OP_SH_IMM6        5
 999
1000 /* These are the characters which may appears in the args field of an
1001    instruction.  They appear in the order in which the fields appear
1002    when the instruction is used.  Commas and parentheses in the args
1003    string are ignored when assembling, and written into the output
1004    when disassembling.
1005
1006    "y" 3 bit register (MIPS16OP_*_RY)
1007    "x" 3 bit register (MIPS16OP_*_RX)
1008    "z" 3 bit register (MIPS16OP_*_RZ)
1009    "Z" 3 bit register (MIPS16OP_*_MOVE32Z)
1010    "v" 3 bit same register as source and destination (MIPS16OP_*_RX)
1011    "w" 3 bit same register as source and destination (MIPS16OP_*_RY)
1012    "0" zero register ($0)
1013    "S" stack pointer ($sp or $29)
1014    "P" program counter
1015    "R" return address register ($ra or $31)
1016    "X" 5 bit MIPS register (MIPS16OP_*_REGR32)
1017    "Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
1018    "6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
1019    "a" 26 bit jump address
1020    "e" 11 bit extension value
1021    "l" register list for entry instruction
1022    "L" register list for exit instruction
1023
1024    The remaining codes may be extended.  Except as otherwise noted,
1025    the full extended operand is a 16 bit signed value.
1026    "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
1027    ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned)
1028    "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
1029    "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
1030    "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
1031    "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
1032    "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
1033    "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
1034    "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
1035    "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5)
1036    "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8)
1037    "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8)
1038    "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8)
1039    "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned)
1040    "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8)
1041    "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8)
1042    "p" 8 bit conditional branch address (MIPS16OP_*_IMM8)
1043    "q" 11 bit branch address (MIPS16OP_*_IMM11)
1044    "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
1045    "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
1046    "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
1047    */
1048
1049 /* Save/restore encoding for the args field when all 4 registers are
1050    either saved as arguments or saved/restored as statics.  */
1051 #define MIPS16_ALL_ARGS    0xe
1052 #define MIPS16_ALL_STATICS 0xb
1053
1054 /* For the mips16, we use the same opcode table format and a few of
1055    the same flags.  However, most of the flags are different.  */
1056
1057 /* Modifies the register in MIPS16OP_*_RX.  */
1058 #define MIPS16_INSN_WRITE_X                 0x00000001
1059 /* Modifies the register in MIPS16OP_*_RY.  */
1060 #define MIPS16_INSN_WRITE_Y                 0x00000002
1061 /* Modifies the register in MIPS16OP_*_RZ.  */
1062 #define MIPS16_INSN_WRITE_Z                 0x00000004
1063 /* Modifies the T ($24) register.  */
1064 #define MIPS16_INSN_WRITE_T                 0x00000008
1065 /* Modifies the SP ($29) register.  */
1066 #define MIPS16_INSN_WRITE_SP                0x00000010
1067 /* Modifies the RA ($31) register.  */
1068 #define MIPS16_INSN_WRITE_31                0x00000020
1069 /* Modifies the general purpose register in MIPS16OP_*_REG32R.  */
1070 #define MIPS16_INSN_WRITE_GPR_Y             0x00000040
1071 /* Reads the register in MIPS16OP_*_RX.  */
1072 #define MIPS16_INSN_READ_X                  0x00000080
1073 /* Reads the register in MIPS16OP_*_RY.  */
1074 #define MIPS16_INSN_READ_Y                  0x00000100
1075 /* Reads the register in MIPS16OP_*_MOVE32Z.  */
1076 #define MIPS16_INSN_READ_Z                  0x00000200
1077 /* Reads the T ($24) register.  */
1078 #define MIPS16_INSN_READ_T                  0x00000400
1079 /* Reads the SP ($29) register.  */
1080 #define MIPS16_INSN_READ_SP                 0x00000800
1081 /* Reads the RA ($31) register.  */
1082 #define MIPS16_INSN_READ_31                 0x00001000
1083 /* Reads the program counter.  */
1084 #define MIPS16_INSN_READ_PC                 0x00002000
1085 /* Reads the general purpose register in MIPS16OP_*_REGR32.  */
1086 #define MIPS16_INSN_READ_GPR_X              0x00004000
1087 /* Is a branch insn. */
1088 #define MIPS16_INSN_BRANCH                  0x00010000
1089
1090 /* The following flags have the same value for the mips16 opcode
1091    table:
1092    INSN_UNCOND_BRANCH_DELAY
1093    INSN_COND_BRANCH_DELAY
1094    INSN_COND_BRANCH_LIKELY (never used)
1095    INSN_READ_HI
1096    INSN_READ_LO
1097    INSN_WRITE_HI
1098    INSN_WRITE_LO
1099    INSN_TRAP
1100    INSN_ISA3
1101    */
1102
1103 extern const struct mips_opcode mips16_opcodes[];
1104 extern const int bfd_mips16_num_opcodes;
1105
1106 /* Short hand so the lines aren't too long.  */
1107
1108 #define LDD     INSN_LOAD_MEMORY_DELAY
1109 #define LCD     INSN_LOAD_COPROC_DELAY
1110 #define UBD     INSN_UNCOND_BRANCH_DELAY
1111 #define CBD     INSN_COND_BRANCH_DELAY
1112 #define COD     INSN_COPROC_MOVE_DELAY
1113 #define CLD     INSN_COPROC_MEMORY_DELAY
1114 #define CBL     INSN_COND_BRANCH_LIKELY
1115 #define TRAP    INSN_TRAP
1116 #define SM      INSN_STORE_MEMORY
1117
1118 #define WR_d    INSN_WRITE_GPR_D
1119 #define WR_t    INSN_WRITE_GPR_T
1120 #define WR_31   INSN_WRITE_GPR_31
1121 #define WR_D    INSN_WRITE_FPR_D
1122 #define WR_T    INSN_WRITE_FPR_T
1123 #define WR_S    INSN_WRITE_FPR_S
1124 #define RD_s    INSN_READ_GPR_S
1125 #define RD_b    INSN_READ_GPR_S
1126 #define RD_t    INSN_READ_GPR_T
1127 #define RD_S    INSN_READ_FPR_S
1128 #define RD_T    INSN_READ_FPR_T
1129 #define RD_R    INSN_READ_FPR_R
1130 #define WR_CC   INSN_WRITE_COND_CODE
1131 #define RD_CC   INSN_READ_COND_CODE
1132 #define RD_C0   INSN_COP
1133 #define RD_C1   INSN_COP
1134 #define RD_C2   INSN_COP
1135 #define RD_C3   INSN_COP
1136 #define WR_C0   INSN_COP
1137 #define WR_C1   INSN_COP
1138 #define WR_C2   INSN_COP
1139 #define WR_C3   INSN_COP
1140
1141 #define WR_HI   INSN_WRITE_HI
1142 #define RD_HI   INSN_READ_HI
1143 #define MOD_HI  WR_HI|RD_HI
1144
1145 #define WR_LO   INSN_WRITE_LO
1146 #define RD_LO   INSN_READ_LO
1147 #define MOD_LO  WR_LO|RD_LO
1148
1149 #define WR_HILO WR_HI|WR_LO
1150 #define RD_HILO RD_HI|RD_LO
1151 #define MOD_HILO WR_HILO|RD_HILO
1152
1153 #define IS_M    INSN_MULT
1154
1155 #define WR_MACC INSN2_WRITE_MDMX_ACC
1156 #define RD_MACC INSN2_READ_MDMX_ACC
1157
1158 #define I1      INSN_ISA1
1159 #define I2      INSN_ISA2
1160 #define I3      INSN_ISA3
1161 #define I4      INSN_ISA4
1162 #define I5      INSN_ISA5
1163 #define I32     INSN_ISA32
1164 #define I64     INSN_ISA64
1165 #define I33     INSN_ISA32R2
1166 #define I65     INSN_ISA64R2
1167 #define I32R6   INSN_ISA32R6
1168 #define I64R6   INSN_ISA64R6
1169
1170 /* MIPS64 MIPS-3D ASE support.  */
1171 #define I16     INSN_MIPS16
1172
1173 /* MIPS32 SmartMIPS ASE support.  */
1174 #define SMT     INSN_SMARTMIPS
1175
1176 /* MIPS64 MIPS-3D ASE support.  */
1177 #define M3D     INSN_MIPS3D
1178
1179 /* MIPS64 MDMX ASE support.  */
1180 #define MX      INSN_MDMX
1181
1182 #define IL2E    (INSN_LOONGSON_2E)
1183 #define IL2F    (INSN_LOONGSON_2F)
1184
1185 #define P3      INSN_4650
1186 #define L1      INSN_4010
1187 #define V1      (INSN_4100 | INSN_4111 | INSN_4120)
1188 #define T3      INSN_3900
1189 #define M1      INSN_10000
1190 #define SB1     INSN_SB1
1191 #define N411    INSN_4111
1192 #define N412    INSN_4120
1193 #define N5      (INSN_5400 | INSN_5500)
1194 #define N54     INSN_5400
1195 #define N55     INSN_5500
1196
1197 #define G1      (T3             \
1198                  )
1199
1200 #define G2      (T3             \
1201                  )
1202
1203 #define G3      (I4             \
1204                  )
1205
1206 /* MIPS DSP ASE support.
1207    NOTE:
1208    1. MIPS DSP ASE includes 4 accumulators ($ac0 - $ac3).  $ac0 is the pair
1209    of original HI and LO.  $ac1, $ac2 and $ac3 are new registers, and have
1210    the same structure as $ac0 (HI + LO).  For DSP instructions that write or
1211    read accumulators (that may be $ac0), we add WR_a (WR_HILO) or RD_a
1212    (RD_HILO) attributes, such that HILO dependencies are maintained
1213    conservatively.
1214
1215    2. For some mul. instructions that use integer registers as destinations
1216    but destroy HI+LO as side-effect, we add WR_HILO to their attributes.
1217
1218    3. MIPS DSP ASE includes a new DSP control register, which has 6 fields
1219    (ccond, outflag, EFI, c, scount, pos).  Many DSP instructions read or write
1220    certain fields of the DSP control register.  For simplicity, we decide not
1221    to track dependencies of these fields.
1222    However, "bposge32" is a branch instruction that depends on the "pos"
1223    field.  In order to make sure that GAS does not reorder DSP instructions
1224    that writes the "pos" field and "bposge32", we add DSP_VOLA (INSN_TRAP)
1225    attribute to those instructions that write the "pos" field.  */
1226
1227 #define WR_a    WR_HILO /* Write dsp accumulators (reuse WR_HILO)  */
1228 #define RD_a    RD_HILO /* Read dsp accumulators (reuse RD_HILO)  */
1229 #define MOD_a   WR_a|RD_a
1230 #define DSP_VOLA        INSN_TRAP
1231 #define D32     INSN_DSP
1232 #define D33     INSN_DSPR2
1233 #define D64     INSN_DSP64
1234
1235 /* MIPS MT ASE support.  */
1236 #define MT32    INSN_MT
1237
1238 /* MSA */
1239 #define MSA     INSN_MSA
1240 #define MSA64   INSN_MSA64
1241 #define WR_VD   INSN_WRITE_FPR_D    /* Reuse INSN_WRITE_FPR_D */
1242 #define RD_VD   WR_VD               /* Reuse WR_VD */
1243 #define RD_VT   INSN_READ_FPR_T     /* Reuse INSN_READ_FPR_T */
1244 #define RD_VS   INSN_READ_FPR_S     /* Reuse INSN_READ_FPR_S */
1245 #define RD_d    INSN2_READ_GPR_D    /* Reuse INSN2_READ_GPR_D */
1246
1247 #define RD_rd6  0
1248
1249 /* The order of overloaded instructions matters.  Label arguments and
1250    register arguments look the same. Instructions that can have either
1251    for arguments must apear in the correct order in this table for the
1252    assembler to pick the right one. In other words, entries with
1253    immediate operands must apear after the same instruction with
1254    registers.
1255
1256    Because of the lookup algorithm used, entries with the same opcode
1257    name must be contiguous.
1258
1259    Many instructions are short hand for other instructions (i.e., The
1260    jal <register> instruction is short for jalr <register>).  */
1261
1262 const struct mips_opcode mips_builtin_opcodes[] =
1263 {
1264 /* These instructions appear first so that the disassembler will find
1265    them first.  The assemblers uses a hash table based on the
1266    instruction name anyhow.  */
1267 /* name,    args,       match,      mask,       pinfo,                  membership */
1268 {"lwpc",    "s,+o2",    0xec080000, 0xfc180000, WR_d,                 0, I32R6},
1269 {"lwupc",   "s,+o2",    0xec100000, 0xfc180000, WR_d,                 0, I64R6},
1270 {"ldpc",    "s,+o1",    0xec180000, 0xfc1c0000, WR_d,                 0, I64R6},
1271 {"addiupc", "s,+o2",    0xec000000, 0xfc180000, WR_d,                 0, I32R6},
1272 {"auipc",   "s,u",      0xec1e0000, 0xfc1f0000, WR_d,                 0, I32R6},
1273 {"aluipc",  "s,u",      0xec1f0000, 0xfc1f0000, WR_d,                 0, I32R6},
1274 {"daui",    "s,t,u",    0x74000000, 0xfc000000, RD_s|WR_t,            0, I64R6},
1275 {"dahi",    "s,u",      0x04060000, 0xfc1f0000, RD_s,                 0, I64R6},
1276 {"dati",    "s,u",      0x041e0000, 0xfc1f0000, RD_s,                 0, I64R6},
1277 {"lsa",     "d,s,t",    0x00000005, 0xfc00073f, WR_d|RD_s|RD_t,       0, I32R6},
1278 {"dlsa",    "d,s,t",    0x00000015, 0xfc00073f, WR_d|RD_s|RD_t,       0, I64R6},
1279 {"clz",     "U,s",      0x00000050, 0xfc1f07ff, WR_d|RD_s,            0, I32R6},
1280 {"clo",     "U,s",      0x00000051, 0xfc1f07ff, WR_d|RD_s,            0, I32R6},
1281 {"dclz",    "U,s",      0x00000052, 0xfc1f07ff, WR_d|RD_s,            0, I64R6},
1282 {"dclo",    "U,s",      0x00000053, 0xfc1f07ff, WR_d|RD_s,            0, I64R6},
1283 {"sdbbp",   "B",        0x0000000e, 0xfc00003f, TRAP,                 0, I32R6},
1284 {"mul",     "d,s,t",    0x00000098, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I32R6},
1285 {"muh",     "d,s,t",    0x000000d8, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I32R6},
1286 {"mulu",    "d,s,t",    0x00000099, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I32R6},
1287 {"muhu",    "d,s,t",    0x000000d9, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I32R6},
1288 {"div",     "d,s,t",    0x0000009a, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I32R6},
1289 {"mod",     "d,s,t",    0x000000da, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I32R6},
1290 {"divu",    "d,s,t",    0x0000009b, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I32R6},
1291 {"modu",    "d,s,t",    0x000000db, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I32R6},
1292 {"dmul",    "d,s,t",    0x0000009c, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I64R6},
1293 {"dmuh",    "d,s,t",    0x000000dc, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I64R6},
1294 {"dmulu",   "d,s,t",    0x0000009d, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I64R6},
1295 {"dmuhu",   "d,s,t",    0x000000dd, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I64R6},
1296 {"ddiv",    "d,s,t",    0x0000009e, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I64R6},
1297 {"dmod",    "d,s,t",    0x000000de, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I64R6},
1298 {"ddivu",   "d,s,t",    0x0000009f, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I64R6},
1299 {"dmodu",   "d,s,t",    0x000000df, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I64R6},
1300 {"ll",      "t,+o(b)",  0x7c000036, 0xfc00007f, LDD|RD_b|WR_t,        0, I32R6},
1301 {"sc",      "t,+o(b)",  0x7c000026, 0xfc00007f, LDD|RD_b|WR_t,        0, I32R6},
1302 {"lld",     "t,+o(b)",  0x7c000037, 0xfc00007f, LDD|RD_b|WR_t,        0, I64R6},
1303 {"scd",     "t,+o(b)",  0x7c000027, 0xfc00007f, LDD|RD_b|WR_t,        0, I64R6},
1304 {"pref",    "h,+o(b)",  0x7c000035, 0xfc00007f, RD_b,                 0, I32R6},
1305 {"cache",   "k,+o(b)",  0x7c000025, 0xfc00007f, RD_b,                 0, I32R6},
1306 {"seleqz",  "d,v,t",    0x00000035, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I32R6},
1307 {"selnez",  "d,v,t",    0x00000037, 0xfc0007ff, WR_d|RD_s|RD_t,       0, I32R6},
1308 {"maddf.s", "D,S,T",    0x46000018, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,  0, I32R6},
1309 {"maddf.d", "D,S,T",    0x46200018, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0, I32R6},
1310 {"msubf.s", "D,S,T",    0x46000019, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,  0, I32R6},
1311 {"msubf.d", "D,S,T",    0x46200019, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0, I32R6},
1312 {"max.s",   "D,S,T",    0x4600001e, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,  0, I32R6},
1313 {"max.d",   "D,S,T",    0x4620001e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0, I32R6},
1314 {"maxa.s",  "D,S,T",    0x4600001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,  0, I32R6},
1315 {"maxa.d",  "D,S,T",    0x4620001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0, I32R6},
1316 {"rint.s",  "D,S",      0x4600001a, 0xffff003f, WR_D|RD_S|FP_S,       0, I32R6},
1317 {"rint.d",  "D,S",      0x4620001a, 0xffff003f, WR_D|RD_S|FP_D,       0, I32R6},
1318 {"class.s", "D,S",      0x4600001b, 0xffff003f, WR_D|RD_S|FP_S,       0, I32R6},
1319 {"class.d", "D,S",      0x4620001b, 0xffff003f, WR_D|RD_S|FP_D,       0, I32R6},
1320 {"min.s",   "D,S,T",    0x4600001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,  0, I32R6},
1321 {"min.d",   "D,S,T",    0x4620001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0, I32R6},
1322 {"mina.s",  "D,S,T",    0x4600001d, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,  0, I32R6},
1323 {"mina.d",  "D,S,T",    0x4620001d, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0, I32R6},
1324 {"sel.s",   "D,S,T",    0x46000010, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,  0, I32R6},
1325 {"sel.d",   "D,S,T",    0x46200010, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0, I32R6},
1326 {"seleqz.s", "D,S,T",   0x46000014, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,  0, I32R6},
1327 {"seleqz.d", "D,S,T",   0x46200014, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0, I32R6},
1328 {"selnez.s", "D,S,T",   0x46000017, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,  0, I32R6},
1329 {"selnez.d", "D,S,T",   0x46200017, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0, I32R6},
1330 {"align",   "d,v,t",    0x7c000220, 0xfc00073f, WR_d|RD_s|RD_t,       0, I32R6},
1331 {"dalign",  "d,v,t",    0x7c000224, 0xfc00063f, WR_d|RD_s|RD_t,       0, I64R6},
1332 {"bitswap", "d,w",      0x7c000020, 0xffe007ff, WR_d|RD_t,            0, I32R6},
1333 {"dbitswap","d,w",      0x7c000024, 0xffe007ff, WR_d|RD_t,            0, I64R6},
1334 {"balc",    "+p",       0xe8000000, 0xfc000000, UBD|WR_31,            0, I32R6},
1335 {"bc",      "+p",       0xc8000000, 0xfc000000, UBD|WR_31,            0, I32R6},
1336 {"jic",     "t,o",      0xd8000000, 0xffe00000, UBD|RD_t,             0, I32R6},
1337 {"beqzc",   "s,+p",     0xd8000000, 0xfc000000, CBD|RD_s,             0, I32R6},
1338 {"jialc",   "t,o",      0xf8000000, 0xffe00000, UBD|RD_t,             0, I32R6},
1339 {"bnezc",   "s,+p",     0xf8000000, 0xfc000000, CBD|RD_s,             0, I32R6},
1340 {"beqzalc", "s,t,p",    0x20000000, 0xffe00000, CBD|RD_s|RD_t,        0, I32R6},
1341 {"bovc",    "s,t,p",    0x20000000, 0xfc000000, CBD|RD_s|RD_t,        0, I32R6},
1342 {"beqc",    "s,t,p",    0x20000000, 0xfc000000, CBD|RD_s|RD_t,        0, I32R6},
1343 {"bnezalc", "s,t,p",    0x60000000, 0xffe00000, CBD|RD_s|RD_t,        0, I32R6},
1344 {"bnvc",    "s,t,p",    0x60000000, 0xfc000000, CBD|RD_s|RD_t,        0, I32R6},
1345 {"bnec",    "s,t,p",    0x60000000, 0xfc000000, CBD|RD_s|RD_t,        0, I32R6},
1346 {"blezc",   "s,t,p",    0x58000000, 0xffe00000, CBD|RD_s|RD_t,        0, I32R6},
1347 {"bgezc",   "s,t,p",    0x58000000, 0xfc000000, CBD|RD_s|RD_t,        0, I32R6},
1348 {"bgec",    "s,t,p",    0x58000000, 0xfc000000, CBD|RD_s|RD_t,        0, I32R6},
1349 {"bgtzc",   "s,t,p",    0x5c000000, 0xffe00000, CBD|RD_s|RD_t,        0, I32R6},
1350 {"bltzc",   "s,t,p",    0x5c000000, 0xfc000000, CBD|RD_s|RD_t,        0, I32R6},
1351 {"bltc",    "s,t,p",    0x5c000000, 0xfc000000, CBD|RD_s|RD_t,        0, I32R6},
1352 {"blezalc", "s,t,p",    0x18000000, 0xffe00000, CBD|RD_s|RD_t,        0, I32R6},
1353 {"bgezalc", "s,t,p",    0x18000000, 0xfc000000, CBD|RD_s|RD_t,        0, I32R6},
1354 {"bgeuc",   "s,t,p",    0x18000000, 0xfc000000, CBD|RD_s|RD_t,        0, I32R6},
1355 {"bgtzalc", "s,t,p",    0x1c000000, 0xffe00000, CBD|RD_s|RD_t,        0, I32R6},
1356 {"bltzalc", "s,t,p",    0x1c000000, 0xfc000000, CBD|RD_s|RD_t,        0, I32R6},
1357 {"bltuc",   "s,t,p",    0x1c000000, 0xfc000000, CBD|RD_s|RD_t,        0, I32R6},
1358 {"nal",     "p",        0x04100000, 0xffff0000, WR_31,                0, I32R6},
1359 {"bal",     "p",        0x04110000, 0xffff0000, UBD|WR_31,            0, I32R6},
1360 {"bc1eqz",  "T,p",      0x45200000, 0xffe00000, CBD|RD_T|FP_S|FP_D,   0, I32R6},
1361 {"bc1nez",  "T,p",      0x45a00000, 0xffe00000, CBD|RD_T|FP_S|FP_D,   0, I32R6},
1362 {"bc2eqz",  "E,p",      0x49200000, 0xffe00000, CBD|RD_C2,            0, I32R6},
1363 {"bc2nez",  "E,p",      0x49a00000, 0xffe00000, CBD|RD_C2,            0, I32R6},
1364 {"cmp.af.s",   "D,S,T", 0x46800000, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1365 {"cmp.un.s",   "D,S,T", 0x46800001, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1366 {"cmp.eq.s",   "D,S,T", 0x46800002, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1367 {"cmp.ueq.s",  "D,S,T", 0x46800003, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1368 {"cmp.lt.s",   "D,S,T", 0x46800004, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1369 {"cmp.ult.s",  "D,S,T", 0x46800005, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1370 {"cmp.le.s",   "D,S,T", 0x46800006, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1371 {"cmp.ule.s",  "D,S,T", 0x46800007, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1372 {"cmp.saf.s",  "D,S,T", 0x46800008, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1373 {"cmp.sun.s",  "D,S,T", 0x46800009, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1374 {"cmp.seq.s",  "D,S,T", 0x4680000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1375 {"cmp.sueq.s", "D,S,T", 0x4680000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1376 {"cmp.slt.s",  "D,S,T", 0x4680000c, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1377 {"cmp.sult.s", "D,S,T", 0x4680000d, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1378 {"cmp.sle.s",  "D,S,T", 0x4680000e, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1379 {"cmp.sule.s", "D,S,T", 0x4680000f, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1380 {"cmp.or.s",   "D,S,T", 0x46800011, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1381 {"cmp.une.s",  "D,S,T", 0x46800012, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1382 {"cmp.ne.s",   "D,S,T", 0x46800013, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1383 {"cmp.sor.s",  "D,S,T", 0x46800019, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1384 {"cmp.sune.s", "D,S,T", 0x4680001a, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1385 {"cmp.sne.s",  "D,S,T", 0x4680001b, 0xffe0003f, RD_S|RD_T|WR_D|FP_S,  0, I32R6},
1386 {"cmp.af.d",   "D,S,T", 0x46a00000, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1387 {"cmp.un.d",   "D,S,T", 0x46a00001, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1388 {"cmp.eq.d",   "D,S,T", 0x46a00002, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1389 {"cmp.ueq.d",  "D,S,T", 0x46a00003, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1390 {"cmp.lt.d",   "D,S,T", 0x46a00004, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1391 {"cmp.ult.d",  "D,S,T", 0x46a00005, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1392 {"cmp.le.d",   "D,S,T", 0x46a00006, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1393 {"cmp.ule.d",  "D,S,T", 0x46a00007, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1394 {"cmp.saf.d",  "D,S,T", 0x46a00008, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1395 {"cmp.sun.d",  "D,S,T", 0x46a00009, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1396 {"cmp.seq.d",  "D,S,T", 0x46a0000a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1397 {"cmp.sueq.d", "D,S,T", 0x46a0000b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1398 {"cmp.slt.d",  "D,S,T", 0x46a0000c, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1399 {"cmp.sult.d", "D,S,T", 0x46a0000d, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1400 {"cmp.sle.d",  "D,S,T", 0x46a0000e, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1401 {"cmp.sule.d", "D,S,T", 0x46a0000f, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1402 {"cmp.or.d",   "D,S,T", 0x46a00011, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1403 {"cmp.une.d",  "D,S,T", 0x46a00012, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1404 {"cmp.ne.d",   "D,S,T", 0x46a00013, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1405 {"cmp.sor.d",  "D,S,T", 0x46a00019, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1406 {"cmp.sune.d", "D,S,T", 0x46a0001a, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1407 {"cmp.sne.d",  "D,S,T", 0x46a0001b, 0xffe0003f, RD_S|RD_T|WR_D|FP_D,  0, I32R6},
1408
1409 /* MSA */
1410 {"sll.b",   "+d,+e,+f", 0x7800000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1411 {"sll.h",   "+d,+e,+f", 0x7820000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1412 {"sll.w",   "+d,+e,+f", 0x7840000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1413 {"sll.d",   "+d,+e,+f", 0x7860000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1414 {"slli.b",  "+d,+e,+7", 0x78700009, 0xfff8003f, WR_VD|RD_VS,        0, MSA},
1415 {"slli.h",  "+d,+e,+8", 0x78600009, 0xfff0003f, WR_VD|RD_VS,        0, MSA},
1416 {"slli.w",  "+d,+e,+9", 0x78400009, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1417 {"slli.d",  "+d,+e,'",  0x78000009, 0xffc0003f, WR_VD|RD_VS,        0, MSA},
1418 {"sra.b",   "+d,+e,+f", 0x7880000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1419 {"sra.h",   "+d,+e,+f", 0x78a0000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1420 {"sra.w",   "+d,+e,+f", 0x78c0000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1421 {"sra.d",   "+d,+e,+f", 0x78e0000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1422 {"srai.b",  "+d,+e,+7", 0x78f00009, 0xfff8003f, WR_VD|RD_VS,        0, MSA},
1423 {"srai.h",  "+d,+e,+8", 0x78e00009, 0xfff0003f, WR_VD|RD_VS,        0, MSA},
1424 {"srai.w",  "+d,+e,+9", 0x78c00009, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1425 {"srai.d",  "+d,+e,'",  0x78800009, 0xffc0003f, WR_VD|RD_VS,        0, MSA},
1426 {"srl.b",   "+d,+e,+f", 0x7900000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1427 {"srl.h",   "+d,+e,+f", 0x7920000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1428 {"srl.w",   "+d,+e,+f", 0x7940000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1429 {"srl.d",   "+d,+e,+f", 0x7960000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1430 {"srli.b",  "+d,+e,+7", 0x79700009, 0xfff8003f, WR_VD|RD_VS,        0, MSA},
1431 {"srli.h",  "+d,+e,+8", 0x79600009, 0xfff0003f, WR_VD|RD_VS,        0, MSA},
1432 {"srli.w",  "+d,+e,+9", 0x79400009, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1433 {"srli.d",  "+d,+e,'",  0x79000009, 0xffc0003f, WR_VD|RD_VS,        0, MSA},
1434 {"bclr.b",  "+d,+e,+f", 0x7980000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1435 {"bclr.h",  "+d,+e,+f", 0x79a0000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1436 {"bclr.w",  "+d,+e,+f", 0x79c0000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1437 {"bclr.d",  "+d,+e,+f", 0x79e0000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1438 {"bclri.b", "+d,+e,+7", 0x79f00009, 0xfff8003f, WR_VD|RD_VS,        0, MSA},
1439 {"bclri.h", "+d,+e,+8", 0x79e00009, 0xfff0003f, WR_VD|RD_VS,        0, MSA},
1440 {"bclri.w", "+d,+e,+9", 0x79c00009, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1441 {"bclri.d", "+d,+e,'",  0x79800009, 0xffc0003f, WR_VD|RD_VS,        0, MSA},
1442 {"bset.b",  "+d,+e,+f", 0x7a00000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1443 {"bset.h",  "+d,+e,+f", 0x7a20000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1444 {"bset.w",  "+d,+e,+f", 0x7a40000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1445 {"bset.d",  "+d,+e,+f", 0x7a60000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1446 {"bseti.b", "+d,+e,+7", 0x7a700009, 0xfff8003f, WR_VD|RD_VS,        0, MSA},
1447 {"bseti.h", "+d,+e,+8", 0x7a600009, 0xfff0003f, WR_VD|RD_VS,        0, MSA},
1448 {"bseti.w", "+d,+e,+9", 0x7a400009, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1449 {"bseti.d", "+d,+e,'",  0x7a000009, 0xffc0003f, WR_VD|RD_VS,        0, MSA},
1450 {"bneg.b",  "+d,+e,+f", 0x7a80000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1451 {"bneg.h",  "+d,+e,+f", 0x7aa0000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1452 {"bneg.w",  "+d,+e,+f", 0x7ac0000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1453 {"bneg.d",  "+d,+e,+f", 0x7ae0000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1454 {"bnegi.b", "+d,+e,+7", 0x7af00009, 0xfff8003f, WR_VD|RD_VS,        0, MSA},
1455 {"bnegi.h", "+d,+e,+8", 0x7ae00009, 0xfff0003f, WR_VD|RD_VS,        0, MSA},
1456 {"bnegi.w", "+d,+e,+9", 0x7ac00009, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1457 {"bnegi.d", "+d,+e,'",  0x7a800009, 0xffc0003f, WR_VD|RD_VS,        0, MSA},
1458 {"binsl.b", "+d,+e,+f", 0x7b00000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1459 {"binsl.h", "+d,+e,+f", 0x7b20000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1460 {"binsl.w", "+d,+e,+f", 0x7b40000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1461 {"binsl.d", "+d,+e,+f", 0x7b60000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1462 {"binsli.b", "+d,+e,+7", 0x7b700009, 0xfff8003f, WR_VD|RD_VS,       0, MSA},
1463 {"binsli.h", "+d,+e,+8", 0x7b600009, 0xfff0003f, WR_VD|RD_VS,       0, MSA},
1464 {"binsli.w", "+d,+e,+9", 0x7b400009, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1465 {"binsli.d", "+d,+e,'",  0x7b000009, 0xffc0003f, WR_VD|RD_VS,       0, MSA},
1466 {"binsr.b", "+d,+e,+f", 0x7b80000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1467 {"binsr.h", "+d,+e,+f", 0x7ba0000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1468 {"binsr.w", "+d,+e,+f", 0x7bc0000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1469 {"binsr.d", "+d,+e,+f", 0x7be0000d, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1470 {"binsri.b", "+d,+e,+7", 0x7bf00009, 0xfff8003f, WR_VD|RD_VS,       0, MSA},
1471 {"binsri.h", "+d,+e,+8", 0x7be00009, 0xfff0003f, WR_VD|RD_VS,       0, MSA},
1472 {"binsri.w", "+d,+e,+9", 0x7bc00009, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1473 {"binsri.d", "+d,+e,'",  0x7b800009, 0xffc0003f, WR_VD|RD_VS,       0, MSA},
1474 {"addv.b",  "+d,+e,+f", 0x7800000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1475 {"addv.h",  "+d,+e,+f", 0x7820000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1476 {"addv.w",  "+d,+e,+f", 0x7840000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1477 {"addv.d",  "+d,+e,+f", 0x7860000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1478 {"addvi.b", "+d,+e,k",  0x78000006, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1479 {"addvi.h", "+d,+e,k",  0x78200006, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1480 {"addvi.w", "+d,+e,k",  0x78400006, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1481 {"addvi.d", "+d,+e,k",  0x78600006, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1482 {"subv.b",  "+d,+e,+f", 0x7880000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1483 {"subv.h",  "+d,+e,+f", 0x78a0000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1484 {"subv.w",  "+d,+e,+f", 0x78c0000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1485 {"subv.d",  "+d,+e,+f", 0x78e0000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1486 {"subvi.b", "+d,+e,k",  0x78800006, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1487 {"subvi.h", "+d,+e,k",  0x78a00006, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1488 {"subvi.w", "+d,+e,k",  0x78c00006, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1489 {"subvi.d", "+d,+e,k",  0x78e00006, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1490 {"max_s.b", "+d,+e,+f", 0x7900000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1491 {"max_s.h", "+d,+e,+f", 0x7920000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1492 {"max_s.w", "+d,+e,+f", 0x7940000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1493 {"max_s.d", "+d,+e,+f", 0x7960000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1494 {"maxi_s.b", "+d,+e,+5", 0x79000006, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1495 {"maxi_s.h", "+d,+e,+5", 0x79200006, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1496 {"maxi_s.w", "+d,+e,+5", 0x79400006, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1497 {"maxi_s.d", "+d,+e,+5", 0x79600006, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1498 {"max_u.b", "+d,+e,+f", 0x7980000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1499 {"max_u.h", "+d,+e,+f", 0x79a0000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1500 {"max_u.w", "+d,+e,+f", 0x79c0000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1501 {"max_u.d", "+d,+e,+f", 0x79e0000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1502 {"maxi_u.b", "+d,+e,k",  0x79800006, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1503 {"maxi_u.h", "+d,+e,k",  0x79a00006, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1504 {"maxi_u.w", "+d,+e,k",  0x79c00006, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1505 {"maxi_u.d", "+d,+e,k",  0x79e00006, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1506 {"min_s.b", "+d,+e,+f", 0x7a00000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1507 {"min_s.h", "+d,+e,+f", 0x7a20000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1508 {"min_s.w", "+d,+e,+f", 0x7a40000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1509 {"min_s.d", "+d,+e,+f", 0x7a60000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1510 {"mini_s.b", "+d,+e,+5", 0x7a000006, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1511 {"mini_s.h", "+d,+e,+5", 0x7a200006, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1512 {"mini_s.w", "+d,+e,+5", 0x7a400006, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1513 {"mini_s.d", "+d,+e,+5", 0x7a600006, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1514 {"min_u.b", "+d,+e,+f", 0x7a80000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1515 {"min_u.h", "+d,+e,+f", 0x7aa0000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1516 {"min_u.w", "+d,+e,+f", 0x7ac0000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1517 {"min_u.d", "+d,+e,+f", 0x7ae0000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1518 {"mini_u.b", "+d,+e,k",  0x7a800006, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1519 {"mini_u.h", "+d,+e,k",  0x7aa00006, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1520 {"mini_u.w", "+d,+e,k",  0x7ac00006, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1521 {"mini_u.d", "+d,+e,k",  0x7ae00006, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1522 {"max_a.b", "+d,+e,+f", 0x7b00000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1523 {"max_a.h", "+d,+e,+f", 0x7b20000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1524 {"max_a.w", "+d,+e,+f", 0x7b40000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1525 {"max_a.d", "+d,+e,+f", 0x7b60000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1526 {"min_a.b", "+d,+e,+f", 0x7b80000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1527 {"min_a.h", "+d,+e,+f", 0x7ba0000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1528 {"min_a.w", "+d,+e,+f", 0x7bc0000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1529 {"min_a.d", "+d,+e,+f", 0x7be0000e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1530 {"ceq.b",   "+d,+e,+f", 0x7800000f, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1531 {"ceq.h",   "+d,+e,+f", 0x7820000f, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1532 {"ceq.w",   "+d,+e,+f", 0x7840000f, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1533 {"ceq.d",   "+d,+e,+f", 0x7860000f, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1534 {"ceqi.b",  "+d,+e,+5", 0x78000007, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1535 {"ceqi.h",  "+d,+e,+5", 0x78200007, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1536 {"ceqi.w",  "+d,+e,+5", 0x78400007, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1537 {"ceqi.d",  "+d,+e,+5", 0x78600007, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1538 {"clt_s.b", "+d,+e,+f", 0x7900000f, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1539 {"clt_s.h", "+d,+e,+f", 0x7920000f, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1540 {"clt_s.w", "+d,+e,+f", 0x7940000f, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1541 {"clt_s.d", "+d,+e,+f", 0x7960000f, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1542 {"clti_s.b", "+d,+e,+5", 0x79000007, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1543 {"clti_s.h", "+d,+e,+5", 0x79200007, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1544 {"clti_s.w", "+d,+e,+5", 0x79400007, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1545 {"clti_s.d", "+d,+e,+5", 0x79600007, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1546 {"clt_u.b", "+d,+e,+f", 0x7980000f, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1547 {"clt_u.h", "+d,+e,+f", 0x79a0000f, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1548 {"clt_u.w", "+d,+e,+f", 0x79c0000f, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1549 {"clt_u.d", "+d,+e,+f", 0x79e0000f, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1550 {"clti_u.b", "+d,+e,k",  0x79800007, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1551 {"clti_u.h", "+d,+e,k",  0x79a00007, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1552 {"clti_u.w", "+d,+e,k",  0x79c00007, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1553 {"clti_u.d", "+d,+e,k",  0x79e00007, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1554 {"cle_s.b", "+d,+e,+f", 0x7a00000f, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1555 {"cle_s.h", "+d,+e,+f", 0x7a20000f, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1556 {"cle_s.w", "+d,+e,+f", 0x7a40000f, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1557 {"cle_s.d", "+d,+e,+f", 0x7a60000f, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1558 {"clei_s.b", "+d,+e,+5", 0x7a000007, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1559 {"clei_s.h", "+d,+e,+5", 0x7a200007, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1560 {"clei_s.w", "+d,+e,+5", 0x7a400007, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1561 {"clei_s.d", "+d,+e,+5", 0x7a600007, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1562 {"cle_u.b", "+d,+e,+f", 0x7a80000f, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1563 {"cle_u.h", "+d,+e,+f", 0x7aa0000f, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1564 {"cle_u.w", "+d,+e,+f", 0x7ac0000f, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1565 {"cle_u.d", "+d,+e,+f", 0x7ae0000f, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1566 {"clei_u.b", "+d,+e,k",  0x7a800007, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1567 {"clei_u.h", "+d,+e,k",  0x7aa00007, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1568 {"clei_u.w", "+d,+e,k",  0x7ac00007, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1569 {"clei_u.d", "+d,+e,k",  0x7ae00007, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1570 {"ld.b",    "+d,+^(d)", 0x78000020, 0xfc00003f, WR_VD|LDD,       RD_d, MSA},
1571 {"ld.h",    "+d,+#(d)", 0x78000021, 0xfc00003f, WR_VD|LDD,       RD_d, MSA},
1572 {"ld.w",    "+d,+$(d)", 0x78000022, 0xfc00003f, WR_VD|LDD,       RD_d, MSA},
1573 {"ld.d",    "+d,+%(d)", 0x78000023, 0xfc00003f, WR_VD|LDD,       RD_d, MSA},
1574 {"st.b",    "+d,+^(d)", 0x78000024, 0xfc00003f, RD_VD|SM,        RD_d, MSA},
1575 {"st.h",    "+d,+#(d)", 0x78000025, 0xfc00003f, RD_VD|SM,        RD_d, MSA},
1576 {"st.w",    "+d,+$(d)", 0x78000026, 0xfc00003f, RD_VD|SM,        RD_d, MSA},
1577 {"st.d",    "+d,+%(d)", 0x78000027, 0xfc00003f, RD_VD|SM,        RD_d, MSA},
1578 {"sat_s.b", "+d,+e,+7", 0x7870000a, 0xfff8003f, WR_VD|RD_VS,        0, MSA},
1579 {"sat_s.h", "+d,+e,+8", 0x7860000a, 0xfff0003f, WR_VD|RD_VS,        0, MSA},
1580 {"sat_s.w", "+d,+e,+9", 0x7840000a, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1581 {"sat_s.d", "+d,+e,'",  0x7800000a, 0xffc0003f, WR_VD|RD_VS,        0, MSA},
1582 {"sat_u.b", "+d,+e,+7", 0x78f0000a, 0xfff8003f, WR_VD|RD_VS,        0, MSA},
1583 {"sat_u.h", "+d,+e,+8", 0x78e0000a, 0xfff0003f, WR_VD|RD_VS,        0, MSA},
1584 {"sat_u.w", "+d,+e,+9", 0x78c0000a, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1585 {"sat_u.d", "+d,+e,'",  0x7880000a, 0xffc0003f, WR_VD|RD_VS,        0, MSA},
1586 {"add_a.b", "+d,+e,+f", 0x78000010, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1587 {"add_a.h", "+d,+e,+f", 0x78200010, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1588 {"add_a.w", "+d,+e,+f", 0x78400010, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1589 {"add_a.d", "+d,+e,+f", 0x78600010, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1590 {"adds_a.b", "+d,+e,+f", 0x78800010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1591 {"adds_a.h", "+d,+e,+f", 0x78a00010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1592 {"adds_a.w", "+d,+e,+f", 0x78c00010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1593 {"adds_a.d", "+d,+e,+f", 0x78e00010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1594 {"adds_s.b", "+d,+e,+f", 0x79000010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1595 {"adds_s.h", "+d,+e,+f", 0x79200010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1596 {"adds_s.w", "+d,+e,+f", 0x79400010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1597 {"adds_s.d", "+d,+e,+f", 0x79600010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1598 {"adds_u.b", "+d,+e,+f", 0x79800010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1599 {"adds_u.h", "+d,+e,+f", 0x79a00010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1600 {"adds_u.w", "+d,+e,+f", 0x79c00010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1601 {"adds_u.d", "+d,+e,+f", 0x79e00010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1602 {"ave_s.b", "+d,+e,+f", 0x7a000010, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1603 {"ave_s.h", "+d,+e,+f", 0x7a200010, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1604 {"ave_s.w", "+d,+e,+f", 0x7a400010, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1605 {"ave_s.d", "+d,+e,+f", 0x7a600010, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1606 {"ave_u.b", "+d,+e,+f", 0x7a800010, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1607 {"ave_u.h", "+d,+e,+f", 0x7aa00010, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1608 {"ave_u.w", "+d,+e,+f", 0x7ac00010, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1609 {"ave_u.d", "+d,+e,+f", 0x7ae00010, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1610 {"aver_s.b", "+d,+e,+f", 0x7b000010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1611 {"aver_s.h", "+d,+e,+f", 0x7b200010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1612 {"aver_s.w", "+d,+e,+f", 0x7b400010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1613 {"aver_s.d", "+d,+e,+f", 0x7b600010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1614 {"aver_u.b", "+d,+e,+f", 0x7b800010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1615 {"aver_u.h", "+d,+e,+f", 0x7ba00010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1616 {"aver_u.w", "+d,+e,+f", 0x7bc00010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1617 {"aver_u.d", "+d,+e,+f", 0x7be00010, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1618 {"subs_s.b", "+d,+e,+f", 0x78000011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1619 {"subs_s.h", "+d,+e,+f", 0x78200011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1620 {"subs_s.w", "+d,+e,+f", 0x78400011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1621 {"subs_s.d", "+d,+e,+f", 0x78600011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1622 {"subs_u.b", "+d,+e,+f", 0x78800011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1623 {"subs_u.h", "+d,+e,+f", 0x78a00011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1624 {"subs_u.w", "+d,+e,+f", 0x78c00011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1625 {"subs_u.d", "+d,+e,+f", 0x78e00011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1626 {"subsus_u.b", "+d,+e,+f", 0x79000011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1627 {"subsus_u.h", "+d,+e,+f", 0x79200011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1628 {"subsus_u.w", "+d,+e,+f", 0x79400011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1629 {"subsus_u.d", "+d,+e,+f", 0x79600011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1630 {"subsuu_s.b", "+d,+e,+f", 0x79800011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1631 {"subsuu_s.h", "+d,+e,+f", 0x79a00011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1632 {"subsuu_s.w", "+d,+e,+f", 0x79c00011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1633 {"subsuu_s.d", "+d,+e,+f", 0x79e00011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1634 {"asub_s.b", "+d,+e,+f", 0x7a000011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1635 {"asub_s.h", "+d,+e,+f", 0x7a200011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1636 {"asub_s.w", "+d,+e,+f", 0x7a400011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1637 {"asub_s.d", "+d,+e,+f", 0x7a600011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1638 {"asub_u.b", "+d,+e,+f", 0x7a800011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1639 {"asub_u.h", "+d,+e,+f", 0x7aa00011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1640 {"asub_u.w", "+d,+e,+f", 0x7ac00011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1641 {"asub_u.d", "+d,+e,+f", 0x7ae00011, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1642 {"mulv.b",  "+d,+e,+f", 0x78000012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1643 {"mulv.h",  "+d,+e,+f", 0x78200012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1644 {"mulv.w",  "+d,+e,+f", 0x78400012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1645 {"mulv.d",  "+d,+e,+f", 0x78600012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1646 {"maddv.b", "+d,+e,+f", 0x78800012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1647 {"maddv.h", "+d,+e,+f", 0x78a00012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1648 {"maddv.w", "+d,+e,+f", 0x78c00012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1649 {"maddv.d", "+d,+e,+f", 0x78e00012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1650 {"msubv.b", "+d,+e,+f", 0x79000012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1651 {"msubv.h", "+d,+e,+f", 0x79200012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1652 {"msubv.w", "+d,+e,+f", 0x79400012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1653 {"msubv.d", "+d,+e,+f", 0x79600012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1654 {"div_s.b", "+d,+e,+f", 0x7a000012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1655 {"div_s.h", "+d,+e,+f", 0x7a200012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1656 {"div_s.w", "+d,+e,+f", 0x7a400012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1657 {"div_s.d", "+d,+e,+f", 0x7a600012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1658 {"div_u.b", "+d,+e,+f", 0x7a800012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1659 {"div_u.h", "+d,+e,+f", 0x7aa00012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1660 {"div_u.w", "+d,+e,+f", 0x7ac00012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1661 {"div_u.d", "+d,+e,+f", 0x7ae00012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1662 {"mod_s.b", "+d,+e,+f", 0x7b000012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1663 {"mod_s.h", "+d,+e,+f", 0x7b200012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1664 {"mod_s.w", "+d,+e,+f", 0x7b400012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1665 {"mod_s.d", "+d,+e,+f", 0x7b600012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1666 {"mod_u.b", "+d,+e,+f", 0x7b800012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1667 {"mod_u.h", "+d,+e,+f", 0x7ba00012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1668 {"mod_u.w", "+d,+e,+f", 0x7bc00012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1669 {"mod_u.d", "+d,+e,+f", 0x7be00012, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1670 {"dotp_s.h", "+d,+e,+f", 0x78200013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1671 {"dotp_s.w", "+d,+e,+f", 0x78400013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1672 {"dotp_s.d", "+d,+e,+f", 0x78600013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1673 {"dotp_u.h", "+d,+e,+f", 0x78a00013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1674 {"dotp_u.w", "+d,+e,+f", 0x78c00013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1675 {"dotp_u.d", "+d,+e,+f", 0x78e00013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1676 {"dpadd_s.h", "+d,+e,+f", 0x79200013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1677 {"dpadd_s.w", "+d,+e,+f", 0x79400013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1678 {"dpadd_s.d", "+d,+e,+f", 0x79600013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1679 {"dpadd_u.h", "+d,+e,+f", 0x79a00013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1680 {"dpadd_u.w", "+d,+e,+f", 0x79c00013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1681 {"dpadd_u.d", "+d,+e,+f", 0x79e00013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1682 {"dpsub_s.h", "+d,+e,+f", 0x7a200013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1683 {"dpsub_s.w", "+d,+e,+f", 0x7a400013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1684 {"dpsub_s.d", "+d,+e,+f", 0x7a600013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1685 {"dpsub_u.h", "+d,+e,+f", 0x7aa00013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1686 {"dpsub_u.w", "+d,+e,+f", 0x7ac00013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1687 {"dpsub_u.d", "+d,+e,+f", 0x7ae00013, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1688 {"sld.b",   "+d,+e[t]", 0x78000014, 0xffe0003f, WR_VD|RD_VS|RD_t,   0, MSA},
1689 {"sld.h",   "+d,+e[t]", 0x78200014, 0xffe0003f, WR_VD|RD_VS|RD_t,   0, MSA},
1690 {"sld.w",   "+d,+e[t]", 0x78400014, 0xffe0003f, WR_VD|RD_VS|RD_t,   0, MSA},
1691 {"sld.d",   "+d,+e[t]", 0x78600014, 0xffe0003f, WR_VD|RD_VS|RD_t,   0, MSA},
1692 {"sldi.b",  "+d,+e[+9]", 0x78000019, 0xffe0003f, WR_VD|RD_VS,       0, MSA},
1693 {"sldi.h",  "+d,+e[+8]", 0x78200019, 0xfff0003f, WR_VD|RD_VS,       0, MSA},
1694 {"sldi.w",  "+d,+e[+7]", 0x78300019, 0xfff8003f, WR_VD|RD_VS,       0, MSA},
1695 {"sldi.d",  "+d,+e[+6]", 0x78380019, 0xfffc003f, WR_VD|RD_VS,       0, MSA},
1696 {"splat.b", "+d,+e[t]", 0x78800014, 0xffe0003f, WR_VD|RD_VS|RD_t,   0, MSA},
1697 {"splat.h", "+d,+e[t]", 0x78a00014, 0xffe0003f, WR_VD|RD_VS|RD_t,   0, MSA},
1698 {"splat.w", "+d,+e[t]", 0x78c00014, 0xffe0003f, WR_VD|RD_VS|RD_t,   0, MSA},
1699 {"splat.d", "+d,+e[t]", 0x78e00014, 0xffe0003f, WR_VD|RD_VS|RD_t,   0, MSA},
1700 {"splati.b", "+d,+e[+9]", 0x78400019, 0xffe0003f, WR_VD|RD_VS,      0, MSA},
1701 {"splati.h", "+d,+e[+8]", 0x78600019, 0xfff0003f, WR_VD|RD_VS,      0, MSA},
1702 {"splati.w", "+d,+e[+7]", 0x78700019, 0xfff8003f, WR_VD|RD_VS,      0, MSA},
1703 {"splati.d", "+d,+e[+6]", 0x78780019, 0xfffc003f, WR_VD|RD_VS,      0, MSA},
1704 {"pckev.b", "+d,+e,+f", 0x79000014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1705 {"pckev.h", "+d,+e,+f", 0x79200014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1706 {"pckev.w", "+d,+e,+f", 0x79400014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1707 {"pckev.d", "+d,+e,+f", 0x79600014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1708 {"pckod.b", "+d,+e,+f", 0x79800014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1709 {"pckod.h", "+d,+e,+f", 0x79a00014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1710 {"pckod.w", "+d,+e,+f", 0x79c00014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1711 {"pckod.d", "+d,+e,+f", 0x79e00014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1712 {"ilvl.b",  "+d,+e,+f", 0x7a000014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1713 {"ilvl.h",  "+d,+e,+f", 0x7a200014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1714 {"ilvl.w",  "+d,+e,+f", 0x7a400014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1715 {"ilvl.d",  "+d,+e,+f", 0x7a600014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1716 {"ilvr.b",  "+d,+e,+f", 0x7a800014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1717 {"ilvr.h",  "+d,+e,+f", 0x7aa00014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1718 {"ilvr.w",  "+d,+e,+f", 0x7ac00014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1719 {"ilvr.d",  "+d,+e,+f", 0x7ae00014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1720 {"ilvev.b", "+d,+e,+f", 0x7b000014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1721 {"ilvev.h", "+d,+e,+f", 0x7b200014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1722 {"ilvev.w", "+d,+e,+f", 0x7b400014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1723 {"ilvev.d", "+d,+e,+f", 0x7b600014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1724 {"ilvod.b", "+d,+e,+f", 0x7b800014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1725 {"ilvod.h", "+d,+e,+f", 0x7ba00014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1726 {"ilvod.w", "+d,+e,+f", 0x7bc00014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1727 {"ilvod.d", "+d,+e,+f", 0x7be00014, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1728 {"vshf.b",  "+d,+e,+f", 0x78000015, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1729 {"vshf.h",  "+d,+e,+f", 0x78200015, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1730 {"vshf.w",  "+d,+e,+f", 0x78400015, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1731 {"vshf.d",  "+d,+e,+f", 0x78600015, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1732 {"srar.b",  "+d,+e,+f", 0x78800015, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1733 {"srar.h",  "+d,+e,+f", 0x78a00015, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1734 {"srar.w",  "+d,+e,+f", 0x78c00015, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1735 {"srar.d",  "+d,+e,+f", 0x78e00015, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1736 {"srari.b", "+d,+e,+7", 0x7970000a, 0xfff8003f, WR_VD|RD_VS,        0, MSA},
1737 {"srari.h", "+d,+e,+8", 0x7960000a, 0xfff0003f, WR_VD|RD_VS,        0, MSA},
1738 {"srari.w", "+d,+e,+9", 0x7940000a, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1739 {"srari.d", "+d,+e,'",  0x7900000a, 0xffc0003f, WR_VD|RD_VS,        0, MSA},
1740 {"srlr.b",  "+d,+e,+f", 0x79000015, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1741 {"srlr.h",  "+d,+e,+f", 0x79200015, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1742 {"srlr.w",  "+d,+e,+f", 0x79400015, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1743 {"srlr.d",  "+d,+e,+f", 0x79600015, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1744 {"srlri.b", "+d,+e,+7", 0x79f0000a, 0xfff8003f, WR_VD|RD_VS,        0, MSA},
1745 {"srlri.h", "+d,+e,+8", 0x79e0000a, 0xfff0003f, WR_VD|RD_VS,        0, MSA},
1746 {"srlri.w", "+d,+e,+9", 0x79c0000a, 0xffe0003f, WR_VD|RD_VS,        0, MSA},
1747 {"srlri.d", "+d,+e,'",  0x7980000a, 0xffc0003f, WR_VD|RD_VS,        0, MSA},
1748 {"hadd_s.h", "+d,+e,+f", 0x7a200015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1749 {"hadd_s.w", "+d,+e,+f", 0x7a400015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1750 {"hadd_s.d", "+d,+e,+f", 0x7a600015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1751 {"hadd_u.h", "+d,+e,+f", 0x7aa00015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1752 {"hadd_u.w", "+d,+e,+f", 0x7ac00015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1753 {"hadd_u.d", "+d,+e,+f", 0x7ae00015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1754 {"hsub_s.h", "+d,+e,+f", 0x7b200015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1755 {"hsub_s.w", "+d,+e,+f", 0x7b400015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1756 {"hsub_s.d", "+d,+e,+f", 0x7b600015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1757 {"hsub_u.h", "+d,+e,+f", 0x7ba00015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1758 {"hsub_u.w", "+d,+e,+f", 0x7bc00015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1759 {"hsub_u.d", "+d,+e,+f", 0x7be00015, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1760 {"and.v",   "+d,+e,+f", 0x7800001e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1761 {"andi.b",  "+d,+e,5",  0x78000000, 0xff00003f, WR_VD|RD_VS,        0, MSA},
1762 {"or.v",    "+d,+e,+f", 0x7820001e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1763 {"ori.b",   "+d,+e,5",  0x79000000, 0xff00003f, WR_VD|RD_VS,        0, MSA},
1764 {"nor.v",   "+d,+e,+f", 0x7840001e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1765 {"nori.b",  "+d,+e,5",  0x7a000000, 0xff00003f, WR_VD|RD_VS,        0, MSA},
1766 {"xor.v",   "+d,+e,+f", 0x7860001e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1767 {"xori.b",  "+d,+e,5",  0x7b000000, 0xff00003f, WR_VD|RD_VS,        0, MSA},
1768 {"bmnz.v",  "+d,+e,+f", 0x7880001e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1769 {"bmnzi.b", "+d,+e,5",  0x78000001, 0xff00003f, WR_VD|RD_VS,        0, MSA},
1770 {"bmz.v",   "+d,+e,+f", 0x78a0001e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1771 {"bmzi.b",  "+d,+e,5",  0x79000001, 0xff00003f, WR_VD|RD_VS,        0, MSA},
1772 {"bsel.v",  "+d,+e,+f", 0x78c0001e, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1773 {"bseli.b", "+d,+e,5",  0x7a000001, 0xff00003f, WR_VD|RD_VS,        0, MSA},
1774 {"shf.b",   "+d,+e,5",  0x78000002, 0xff00003f, WR_VD|RD_VS,        0, MSA},
1775 {"shf.h",   "+d,+e,5",  0x79000002, 0xff00003f, WR_VD|RD_VS,        0, MSA},
1776 {"shf.w",   "+d,+e,5",  0x7a000002, 0xff00003f, WR_VD|RD_VS,        0, MSA},
1777 {"bnz.v",    "+f,p",    0x45e00000, 0xffe00000, CBD|RD_VT,          0, MSA},
1778 {"bz.v",    "+f,p",     0x45600000, 0xffe00000, CBD|RD_VT,          0, MSA},
1779 {"fill.b",  "+d,d",     0x7b00001e, 0xffff003f, WR_VD,           RD_d, MSA},
1780 {"fill.h",  "+d,d",     0x7b01001e, 0xffff003f, WR_VD,           RD_d, MSA},
1781 {"fill.w",  "+d,d",     0x7b02001e, 0xffff003f, WR_VD,           RD_d, MSA},
1782 {"fill.d",  "+d,d",     0x7b03001e, 0xffff003f, WR_VD,           RD_d, MSA64},
1783 {"pcnt.b",  "+d,+e",    0x7b04001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1784 {"pcnt.h",  "+d,+e",    0x7b05001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1785 {"pcnt.w",  "+d,+e",    0x7b06001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1786 {"pcnt.d",  "+d,+e",    0x7b07001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1787 {"nloc.b",  "+d,+e",    0x7b08001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1788 {"nloc.h",  "+d,+e",    0x7b09001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1789 {"nloc.w",  "+d,+e",    0x7b0a001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1790 {"nloc.d",  "+d,+e",    0x7b0b001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1791 {"nlzc.b",  "+d,+e",    0x7b0c001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1792 {"nlzc.h",  "+d,+e",    0x7b0d001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1793 {"nlzc.w",  "+d,+e",    0x7b0e001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1794 {"nlzc.d",  "+d,+e",    0x7b0f001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1795 {"copy_s.b", "+i,+e[+9]", 0x78800019, 0xffe0003f, RD_VS,       RD_rd6, MSA},
1796 {"copy_s.h", "+i,+e[+8]", 0x78a00019, 0xfff0003f, RD_VS,       RD_rd6, MSA},
1797 {"copy_s.w", "+i,+e[+7]", 0x78b00019, 0xfff8003f, RD_VS,       RD_rd6, MSA},
1798 {"copy_s.d", "+i,+e[+6]", 0x78b80019, 0xfffc003f, RD_VS,       RD_rd6, MSA64},
1799 {"copy_u.b", "+i,+e[+9]", 0x78c00019, 0xffe0003f, RD_VS,       RD_rd6, MSA},
1800 {"copy_u.h", "+i,+e[+8]", 0x78e00019, 0xfff0003f, RD_VS,       RD_rd6, MSA},
1801 {"copy_u.w", "+i,+e[+7]", 0x78f00019, 0xfff8003f, RD_VS,       RD_rd6, MSA},
1802 {"copy_u.d", "+i,+e[+6]", 0x78f80019, 0xfffc003f, RD_VS,       RD_rd6, MSA64},
1803 {"insert.b", "+d[+9],d", 0x79000019, 0xffe0003f, WR_VD|RD_VD,    RD_d, MSA},
1804 {"insert.h", "+d[+8],d", 0x79200019, 0xfff0003f, WR_VD|RD_VD,    RD_d, MSA},
1805 {"insert.w", "+d[+7],d", 0x79300019, 0xfff8003f, WR_VD|RD_VD,    RD_d, MSA},
1806 {"insert.d", "+d[+6],d", 0x79380019, 0xfffc003f, WR_VD|RD_VD,    RD_d, MSA64},
1807 {"insve.b", "+d[+9],+e[+~]", 0x79400019, 0xffe0003f, WR_VD|RD_VD|RD_VS, 0, MSA},
1808 {"insve.h", "+d[+8],+e[+~]", 0x79600019, 0xfff0003f, WR_VD|RD_VD|RD_VS, 0, MSA},
1809 {"insve.w", "+d[+7],+e[+~]", 0x79700019, 0xfff8003f, WR_VD|RD_VD|RD_VS, 0, MSA},
1810 {"insve.d", "+d[+6],+e[+~]", 0x79780019, 0xfffc003f, WR_VD|RD_VD|RD_VS, 0, MSA},
1811 {"bnz.b",    "+f,p",    0x47800000, 0xffe00000, CBD|RD_VT,          0, MSA},
1812 {"bnz.h",    "+f,p",    0x47a00000, 0xffe00000, CBD|RD_VT,          0, MSA},
1813 {"bnz.w",    "+f,p",    0x47c00000, 0xffe00000, CBD|RD_VT,          0, MSA},
1814 {"bnz.d",    "+f,p",    0x47e00000, 0xffe00000, CBD|RD_VT,          0, MSA},
1815 {"bz.b",    "+f,p",     0x47000000, 0xffe00000, CBD|RD_VT,          0, MSA},
1816 {"bz.h",    "+f,p",     0x47200000, 0xffe00000, CBD|RD_VT,          0, MSA},
1817 {"bz.w",    "+f,p",     0x47400000, 0xffe00000, CBD|RD_VT,          0, MSA},
1818 {"bz.d",    "+f,p",     0x47600000, 0xffe00000, CBD|RD_VT,          0, MSA},
1819 {"ldi.b",   "+d,+0",    0x7b000007, 0xffe0003f, WR_VD,              0, MSA},
1820 {"ldi.h",   "+d,+0",    0x7b200007, 0xffe0003f, WR_VD,              0, MSA},
1821 {"ldi.w",   "+d,+0",    0x7b400007, 0xffe0003f, WR_VD,              0, MSA},
1822 {"ldi.d",   "+d,+0",    0x7b600007, 0xffe0003f, WR_VD,              0, MSA},
1823 {"fcaf.w",  "+d,+e,+f", 0x7800001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1824 {"fcaf.d",  "+d,+e,+f", 0x7820001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1825 {"fcun.w",  "+d,+e,+f", 0x7840001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1826 {"fcun.d",  "+d,+e,+f", 0x7860001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1827 {"fceq.w",  "+d,+e,+f", 0x7880001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1828 {"fceq.d",  "+d,+e,+f", 0x78a0001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1829 {"fcueq.w", "+d,+e,+f", 0x78c0001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1830 {"fcueq.d", "+d,+e,+f", 0x78e0001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1831 {"fclt.w",  "+d,+e,+f", 0x7900001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1832 {"fclt.d",  "+d,+e,+f", 0x7920001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1833 {"fcult.w", "+d,+e,+f", 0x7940001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1834 {"fcult.d", "+d,+e,+f", 0x7960001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1835 {"fcle.w",  "+d,+e,+f", 0x7980001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1836 {"fcle.d",  "+d,+e,+f", 0x79a0001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1837 {"fcule.w", "+d,+e,+f", 0x79c0001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1838 {"fcule.d", "+d,+e,+f", 0x79e0001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1839 {"fsaf.w",  "+d,+e,+f", 0x7a00001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1840 {"fsaf.d",  "+d,+e,+f", 0x7a20001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1841 {"fsun.w",  "+d,+e,+f", 0x7a40001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1842 {"fsun.d",  "+d,+e,+f", 0x7a60001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1843 {"fseq.w",  "+d,+e,+f", 0x7a80001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1844 {"fseq.d",  "+d,+e,+f", 0x7aa0001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1845 {"fsueq.w", "+d,+e,+f", 0x7ac0001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1846 {"fsueq.d", "+d,+e,+f", 0x7ae0001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1847 {"fslt.w",  "+d,+e,+f", 0x7b00001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1848 {"fslt.d",  "+d,+e,+f", 0x7b20001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1849 {"fsult.w", "+d,+e,+f", 0x7b40001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1850 {"fsult.d", "+d,+e,+f", 0x7b60001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1851 {"fsle.w",  "+d,+e,+f", 0x7b80001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1852 {"fsle.d",  "+d,+e,+f", 0x7ba0001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1853 {"fsule.w", "+d,+e,+f", 0x7bc0001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1854 {"fsule.d", "+d,+e,+f", 0x7be0001a, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1855 {"fadd.w",  "+d,+e,+f", 0x7800001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1856 {"fadd.d",  "+d,+e,+f", 0x7820001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1857 {"fsub.w",  "+d,+e,+f", 0x7840001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1858 {"fsub.d",  "+d,+e,+f", 0x7860001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1859 {"fmul.w",  "+d,+e,+f", 0x7880001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1860 {"fmul.d",  "+d,+e,+f", 0x78a0001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1861 {"fdiv.w",  "+d,+e,+f", 0x78c0001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1862 {"fdiv.d",  "+d,+e,+f", 0x78e0001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1863 {"fmadd.w", "+d,+e,+f", 0x7900001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1864 {"fmadd.d", "+d,+e,+f", 0x7920001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1865 {"fmsub.w", "+d,+e,+f", 0x7940001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1866 {"fmsub.d", "+d,+e,+f", 0x7960001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1867 {"fexp2.w", "+d,+e,+f", 0x79c0001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1868 {"fexp2.d", "+d,+e,+f", 0x79e0001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1869 {"fexdo.h", "+d,+e,+f", 0x7a00001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1870 {"fexdo.w", "+d,+e,+f", 0x7a20001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1871 {"ftq.h",   "+d,+e,+f", 0x7a80001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1872 {"ftq.w",   "+d,+e,+f", 0x7aa0001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1873 {"fmin.w",  "+d,+e,+f", 0x7b00001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1874 {"fmin.d",  "+d,+e,+f", 0x7b20001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1875 {"fmin_a.w", "+d,+e,+f", 0x7b40001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1876 {"fmin_a.d", "+d,+e,+f", 0x7b60001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1877 {"fmax.w",  "+d,+e,+f", 0x7b80001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1878 {"fmax.d",  "+d,+e,+f", 0x7ba0001b, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1879 {"fmax_a.w", "+d,+e,+f", 0x7bc0001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1880 {"fmax_a.d", "+d,+e,+f", 0x7be0001b, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1881 {"fcor.w",  "+d,+e,+f", 0x7840001c, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1882 {"fcor.d",  "+d,+e,+f", 0x7860001c, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1883 {"fcune.w", "+d,+e,+f", 0x7880001c, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1884 {"fcune.d", "+d,+e,+f", 0x78a0001c, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1885 {"fcne.w",  "+d,+e,+f", 0x78c0001c, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1886 {"fcne.d",  "+d,+e,+f", 0x78e0001c, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1887 {"mul_q.h", "+d,+e,+f", 0x7900001c, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1888 {"mul_q.w", "+d,+e,+f", 0x7920001c, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1889 {"madd_q.h", "+d,+e,+f", 0x7940001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1890 {"madd_q.w", "+d,+e,+f", 0x7960001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1891 {"msub_q.h", "+d,+e,+f", 0x7980001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1892 {"msub_q.w", "+d,+e,+f", 0x79a0001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1893 {"fsor.w",  "+d,+e,+f", 0x7a40001c, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1894 {"fsor.d",  "+d,+e,+f", 0x7a60001c, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1895 {"fsune.w", "+d,+e,+f", 0x7a80001c, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1896 {"fsune.d", "+d,+e,+f", 0x7aa0001c, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1897 {"fsne.w",  "+d,+e,+f", 0x7ac0001c, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1898 {"fsne.d",  "+d,+e,+f", 0x7ae0001c, 0xffe0003f, WR_VD|RD_VS|RD_VT,  0, MSA},
1899 {"mulr_q.h", "+d,+e,+f", 0x7b00001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1900 {"mulr_q.w", "+d,+e,+f", 0x7b20001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1901 {"maddr_q.h", "+d,+e,+f", 0x7b40001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1902 {"maddr_q.w", "+d,+e,+f", 0x7b60001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1903 {"msubr_q.h", "+d,+e,+f", 0x7b80001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1904 {"msubr_q.w", "+d,+e,+f", 0x7ba0001c, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA},
1905 {"fclass.w", "+d,+e",    0x7b20001e, 0xffff003f, WR_VD|RD_VS,       0, MSA},
1906 {"fclass.d", "+d,+e",    0x7b21001e, 0xffff003f, WR_VD|RD_VS,       0, MSA},
1907 {"fsqrt.w", "+d,+e",    0x7b26001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1908 {"fsqrt.d", "+d,+e",    0x7b27001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1909 {"frsqrt.w", "+d,+e",    0x7b28001e, 0xffff003f, WR_VD|RD_VS,       0, MSA},
1910 {"frsqrt.d", "+d,+e",    0x7b29001e, 0xffff003f, WR_VD|RD_VS,       0, MSA},
1911 {"frcp.w",  "+d,+e",    0x7b2a001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1912 {"frcp.d",  "+d,+e",    0x7b2b001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1913 {"frint.w", "+d,+e",    0x7b2c001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1914 {"frint.d", "+d,+e",    0x7b2d001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1915 {"flog2.w", "+d,+e",    0x7b2e001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1916 {"flog2.d", "+d,+e",    0x7b2f001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1917 {"fexupl.w", "+d,+e",    0x7b30001e, 0xffff003f, WR_VD|RD_VS,       0, MSA},
1918 {"fexupl.d", "+d,+e",    0x7b31001e, 0xffff003f, WR_VD|RD_VS,       0, MSA},
1919 {"fexupr.w", "+d,+e",    0x7b32001e, 0xffff003f, WR_VD|RD_VS,       0, MSA},
1920 {"fexupr.d", "+d,+e",    0x7b33001e, 0xffff003f, WR_VD|RD_VS,       0, MSA},
1921 {"ffql.w",  "+d,+e",    0x7b34001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1922 {"ffql.d",  "+d,+e",    0x7b35001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1923 {"ffqr.w",  "+d,+e",    0x7b36001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1924 {"ffqr.d",  "+d,+e",    0x7b37001e, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1925 {"ftint_s.w", "+d,+e",   0x7b38001e, 0xffff003f, WR_VD|RD_VS,       0, MSA},
1926 {"ftint_s.d", "+d,+e",   0x7b39001e, 0xffff003f, WR_VD|RD_VS,       0, MSA},
1927 {"ftint_u.w", "+d,+e",   0x7b3a001e, 0xffff003f, WR_VD|RD_VS,       0, MSA},
1928 {"ftint_u.d", "+d,+e",   0x7b3b001e, 0xffff003f, WR_VD|RD_VS,       0, MSA},
1929 {"ffint_s.w", "+d,+e",   0x7b3c001e, 0xffff003f, WR_VD|RD_VS,       0, MSA},
1930 {"ffint_s.d", "+d,+e",   0x7b3d001e, 0xffff003f, WR_VD|RD_VS,       0, MSA},
1931 {"ffint_u.w", "+d,+e",   0x7b3e001e, 0xffff003f, WR_VD|RD_VS,       0, MSA},
1932 {"ffint_u.d", "+d,+e",   0x7b3f001e, 0xffff003f, WR_VD|RD_VS,       0, MSA},
1933 {"ftrunc_s.w", "+d,+e",  0x7b40001e, 0xffff003f, WR_VD|RD_VS,       0, MSA},
1934 {"ftrunc_s.d", "+d,+e",  0x7b41001e, 0xffff003f, WR_VD|RD_VS,       0, MSA},
1935 {"ftrunc_u.w", "+d,+e",  0x7b42001e, 0xffff003f, WR_VD|RD_VS,       0, MSA},
1936 {"ftrunc_u.d", "+d,+e",  0x7b43001e, 0xffff003f, WR_VD|RD_VS,       0, MSA},
1937 {"ctcmsa",  "+h,d",     0x783e0019, 0xffff003f, COD,             RD_d, MSA},
1938 {"cfcmsa",  "+i,+g",    0x787e0019, 0xffff003f, COD,                0, MSA},
1939 {"move.v",  "+d,+e",    0x78be0019, 0xffff003f, WR_VD|RD_VS,        0, MSA},
1940 {"lsa",     "d,v,t,+@", 0x00000005, 0xfc00073f, WR_d|RD_s|RD_t,     0, MSA},
1941 {"dlsa",    "d,v,t,+@", 0x00000015, 0xfc00073f, WR_d|RD_s|RD_t,     0, MSA64},
1942
1943 {"pref",    "k,o(b)",   0xcc000000, 0xfc000000, RD_b,                   0,              I4|I32|G3       },
1944 {"prefx",   "h,t(b)",   0x4c00000f, 0xfc0007ff, RD_b|RD_t,              0,              I4|I33  },
1945 {"nop",     "",         0x00000000, 0xffffffff, 0,                      INSN2_ALIAS,    I1      }, /* sll */
1946 {"ssnop",   "",         0x00000040, 0xffffffff, 0,                      INSN2_ALIAS,    I32|N55 }, /* sll */
1947 {"ehb",     "",         0x000000c0, 0xffffffff, 0,                      INSN2_ALIAS,    I33     }, /* sll */
1948 {"li",      "t,j",      0x24000000, 0xffe00000, WR_t,                   INSN2_ALIAS,    I1      }, /* addiu */
1949 {"li",      "t,i",      0x34000000, 0xffe00000, WR_t,                   INSN2_ALIAS,    I1      }, /* ori */
1950 {"li",      "t,I",      0,    (int) M_LI,       INSN_MACRO,             0,              I1      },
1951 {"move",    "d,s",      0,    (int) M_MOVE,     INSN_MACRO,             0,              I1      },
1952 {"move",    "d,s",      0x0000002d, 0xfc1f07ff, WR_d|RD_s,              INSN2_ALIAS,    I3      },/* daddu */
1953 {"move",    "d,s",      0x00000021, 0xfc1f07ff, WR_d|RD_s,              INSN2_ALIAS,    I1      },/* addu */
1954 {"move",    "d,s",      0x00000025, 0xfc1f07ff, WR_d|RD_s,              INSN2_ALIAS,    I1      },/* or */
1955 {"b",       "p",        0x10000000, 0xffff0000, UBD,                    INSN2_ALIAS,    I1      },/* beq 0,0 */
1956 {"b",       "p",        0x04010000, 0xffff0000, UBD,                    INSN2_ALIAS,    I1      },/* bgez 0 */
1957 {"bal",     "p",        0x04110000, 0xffff0000, UBD|WR_31,              INSN2_ALIAS,    I1      },/* bgezal 0*/
1958
1959 {"abs",     "d,v",      0,    (int) M_ABS,      INSN_MACRO,             0,              I1      },
1960 {"abs.s",   "D,V",      0x46000005, 0xffff003f, WR_D|RD_S|FP_S,         0,              I1      },
1961 {"abs.d",   "D,V",      0x46200005, 0xffff003f, WR_D|RD_S|FP_D,         0,              I1      },
1962 {"abs.ps",  "D,V",      0x46c00005, 0xffff003f, WR_D|RD_S|FP_D,         0,              I5|I33  },
1963 {"add",     "d,v,t",    0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
1964 {"add",     "t,r,I",    0,    (int) M_ADD_I,    INSN_MACRO,             0,              I1      },
1965 {"add.s",   "D,V,T",    0x46000000, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              I1      },
1966 {"add.d",   "D,V,T",    0x46200000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I1      },
1967 {"add.ob",  "X,Y,Q",    0x7800000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
1968 {"add.ob",  "D,S,T",    0x4ac0000b, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
1969 {"add.ob",  "D,S,T[e]", 0x4800000b, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
1970 {"add.ob",  "D,S,k",    0x4bc0000b, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
1971 {"add.ps",  "D,V,T",    0x46c00000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5|I33  },
1972 {"add.qh",  "X,Y,Q",    0x7820000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
1973 {"adda.ob", "Y,Q",      0x78000037, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
1974 {"adda.qh", "Y,Q",      0x78200037, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
1975 {"addi",    "t,r,j",    0x20000000, 0xfc000000, WR_t|RD_s,              0,              I1      },
1976 {"addiu",   "t,r,j",    0x24000000, 0xfc000000, WR_t|RD_s,              0,              I1      },
1977 {"addl.ob", "Y,Q",      0x78000437, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
1978 {"addl.qh", "Y,Q",      0x78200437, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
1979 {"addr.ps", "D,S,T",    0x46c00018, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              M3D     },
1980 {"addu",    "d,v,t",    0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
1981 {"addu",    "t,r,I",    0,    (int) M_ADDU_I,   INSN_MACRO,             0,              I1      },
1982 {"alni.ob", "X,Y,Z,O",  0x78000018, 0xff00003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
1983 {"alni.ob", "D,S,T,%",  0x48000018, 0xff00003f, WR_D|RD_S|RD_T,         0,              N54     },
1984 {"alni.qh", "X,Y,Z,O",  0x7800001a, 0xff00003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
1985 {"alnv.ps", "D,V,T,s",  0x4c00001e, 0xfc00003f, WR_D|RD_S|RD_T|FP_D,    0,              I5|I33  },
1986 {"alnv.ob", "X,Y,Z,s",  0x78000019, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0,            MX|SB1  },
1987 {"alnv.qh", "X,Y,Z,s",  0x7800001b, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0,            MX      },
1988 {"and",     "d,v,t",    0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
1989 {"and",     "t,r,I",    0,    (int) M_AND_I,    INSN_MACRO,             0,              I1      },
1990 {"and.ob",  "X,Y,Q",    0x7800000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
1991 {"and.ob",  "D,S,T",    0x4ac0000c, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
1992 {"and.ob",  "D,S,T[e]", 0x4800000c, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
1993 {"and.ob",  "D,S,k",    0x4bc0000c, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
1994 {"and.qh",  "X,Y,Q",    0x7820000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
1995 {"andi",    "t,r,i",    0x30000000, 0xfc000000, WR_t|RD_s,              0,              I1      },
1996 /* b is at the top of the table.  */
1997 /* bal is at the top of the table.  */
1998 /* bc0[tf]l? are at the bottom of the table.  */
1999 {"bc1any2f", "N,p",     0x45200000, 0xffe30000, CBD|RD_CC|FP_S,         0,              M3D     },
2000 {"bc1any2t", "N,p",     0x45210000, 0xffe30000, CBD|RD_CC|FP_S,         0,              M3D     },
2001 {"bc1any4f", "N,p",     0x45400000, 0xffe30000, CBD|RD_CC|FP_S,         0,              M3D     },
2002 {"bc1any4t", "N,p",     0x45410000, 0xffe30000, CBD|RD_CC|FP_S,         0,              M3D     },
2003 {"bc1f",    "p",        0x45000000, 0xffff0000, CBD|RD_CC|FP_S,         0,              I1      },
2004 {"bc1f",    "N,p",      0x45000000, 0xffe30000, CBD|RD_CC|FP_S,         0,              I4|I32  },
2005 {"bc1fl",   "p",        0x45020000, 0xffff0000, CBL|RD_CC|FP_S,         0,              I2|T3   },
2006 {"bc1fl",   "N,p",      0x45020000, 0xffe30000, CBL|RD_CC|FP_S,         0,              I4|I32  },
2007 {"bc1t",    "p",        0x45010000, 0xffff0000, CBD|RD_CC|FP_S,         0,              I1      },
2008 {"bc1t",    "N,p",      0x45010000, 0xffe30000, CBD|RD_CC|FP_S,         0,              I4|I32  },
2009 {"bc1tl",   "p",        0x45030000, 0xffff0000, CBL|RD_CC|FP_S,         0,              I2|T3   },
2010 {"bc1tl",   "N,p",      0x45030000, 0xffe30000, CBL|RD_CC|FP_S,         0,              I4|I32  },
2011 /* bc2* are at the bottom of the table.  */
2012 /* bc3* are at the bottom of the table.  */
2013 {"beqz",    "s,p",      0x10000000, 0xfc1f0000, CBD|RD_s,               0,              I1      },
2014 {"beqzl",   "s,p",      0x50000000, 0xfc1f0000, CBL|RD_s,               0,              I2|T3   },
2015 {"beq",     "s,t,p",    0x10000000, 0xfc000000, CBD|RD_s|RD_t,          0,              I1      },
2016 {"beq",     "s,I,p",    0,    (int) M_BEQ_I,    INSN_MACRO,             0,              I1      },
2017 {"beql",    "s,t,p",    0x50000000, 0xfc000000, CBL|RD_s|RD_t,          0,              I2|T3   },
2018 {"beql",    "s,I,p",    0,    (int) M_BEQL_I,   INSN_MACRO,             0,              I2|T3   },
2019 {"bge",     "s,t,p",    0,    (int) M_BGE,      INSN_MACRO,             0,              I1      },
2020 {"bge",     "s,I,p",    0,    (int) M_BGE_I,    INSN_MACRO,             0,              I1      },
2021 {"bgel",    "s,t,p",    0,    (int) M_BGEL,     INSN_MACRO,             0,              I2|T3   },
2022 {"bgel",    "s,I,p",    0,    (int) M_BGEL_I,   INSN_MACRO,             0,              I2|T3   },
2023 {"bgeu",    "s,t,p",    0,    (int) M_BGEU,     INSN_MACRO,             0,              I1      },
2024 {"bgeu",    "s,I,p",    0,    (int) M_BGEU_I,   INSN_MACRO,             0,              I1      },
2025 {"bgeul",   "s,t,p",    0,    (int) M_BGEUL,    INSN_MACRO,             0,              I2|T3   },
2026 {"bgeul",   "s,I,p",    0,    (int) M_BGEUL_I,  INSN_MACRO,             0,              I2|T3   },
2027 {"bgez",    "s,p",      0x04010000, 0xfc1f0000, CBD|RD_s,               0,              I1      },
2028 {"bgezl",   "s,p",      0x04030000, 0xfc1f0000, CBL|RD_s,               0,              I2|T3   },
2029 {"bgezal",  "s,p",      0x04110000, 0xfc1f0000, CBD|RD_s|WR_31,         0,              I1      },
2030 {"bgezall", "s,p",      0x04130000, 0xfc1f0000, CBL|RD_s|WR_31,         0,              I2|T3   },
2031 {"bgt",     "s,t,p",    0,    (int) M_BGT,      INSN_MACRO,             0,              I1      },
2032 {"bgt",     "s,I,p",    0,    (int) M_BGT_I,    INSN_MACRO,             0,              I1      },
2033 {"bgtl",    "s,t,p",    0,    (int) M_BGTL,     INSN_MACRO,             0,              I2|T3   },
2034 {"bgtl",    "s,I,p",    0,    (int) M_BGTL_I,   INSN_MACRO,             0,              I2|T3   },
2035 {"bgtu",    "s,t,p",    0,    (int) M_BGTU,     INSN_MACRO,             0,              I1      },
2036 {"bgtu",    "s,I,p",    0,    (int) M_BGTU_I,   INSN_MACRO,             0,              I1      },
2037 {"bgtul",   "s,t,p",    0,    (int) M_BGTUL,    INSN_MACRO,             0,              I2|T3   },
2038 {"bgtul",   "s,I,p",    0,    (int) M_BGTUL_I,  INSN_MACRO,             0,              I2|T3   },
2039 {"bgtz",    "s,p",      0x1c000000, 0xfc1f0000, CBD|RD_s,               0,              I1      },
2040 {"bgtzl",   "s,p",      0x5c000000, 0xfc1f0000, CBL|RD_s,               0,              I2|T3   },
2041 {"ble",     "s,t,p",    0,    (int) M_BLE,      INSN_MACRO,             0,              I1      },
2042 {"ble",     "s,I,p",    0,    (int) M_BLE_I,    INSN_MACRO,             0,              I1      },
2043 {"blel",    "s,t,p",    0,    (int) M_BLEL,     INSN_MACRO,             0,              I2|T3   },
2044 {"blel",    "s,I,p",    0,    (int) M_BLEL_I,   INSN_MACRO,             0,              I2|T3   },
2045 {"bleu",    "s,t,p",    0,    (int) M_BLEU,     INSN_MACRO,             0,              I1      },
2046 {"bleu",    "s,I,p",    0,    (int) M_BLEU_I,   INSN_MACRO,             0,              I1      },
2047 {"bleul",   "s,t,p",    0,    (int) M_BLEUL,    INSN_MACRO,             0,              I2|T3   },
2048 {"bleul",   "s,I,p",    0,    (int) M_BLEUL_I,  INSN_MACRO,             0,              I2|T3   },
2049 {"blez",    "s,p",      0x18000000, 0xfc1f0000, CBD|RD_s,               0,              I1      },
2050 {"blezl",   "s,p",      0x58000000, 0xfc1f0000, CBL|RD_s,               0,              I2|T3   },
2051 {"blt",     "s,t,p",    0,    (int) M_BLT,      INSN_MACRO,             0,              I1      },
2052 {"blt",     "s,I,p",    0,    (int) M_BLT_I,    INSN_MACRO,             0,              I1      },
2053 {"bltl",    "s,t,p",    0,    (int) M_BLTL,     INSN_MACRO,             0,              I2|T3   },
2054 {"bltl",    "s,I,p",    0,    (int) M_BLTL_I,   INSN_MACRO,             0,              I2|T3   },
2055 {"bltu",    "s,t,p",    0,    (int) M_BLTU,     INSN_MACRO,             0,              I1      },
2056 {"bltu",    "s,I,p",    0,    (int) M_BLTU_I,   INSN_MACRO,             0,              I1      },
2057 {"bltul",   "s,t,p",    0,    (int) M_BLTUL,    INSN_MACRO,             0,              I2|T3   },
2058 {"bltul",   "s,I,p",    0,    (int) M_BLTUL_I,  INSN_MACRO,             0,              I2|T3   },
2059 {"bltz",    "s,p",      0x04000000, 0xfc1f0000, CBD|RD_s,               0,              I1      },
2060 {"bltzl",   "s,p",      0x04020000, 0xfc1f0000, CBL|RD_s,               0,              I2|T3   },
2061 {"bltzal",  "s,p",      0x04100000, 0xfc1f0000, CBD|RD_s|WR_31,         0,              I1      },
2062 {"bltzall", "s,p",      0x04120000, 0xfc1f0000, CBL|RD_s|WR_31,         0,              I2|T3   },
2063 {"bnez",    "s,p",      0x14000000, 0xfc1f0000, CBD|RD_s,               0,              I1      },
2064 {"bnezl",   "s,p",      0x54000000, 0xfc1f0000, CBL|RD_s,               0,              I2|T3   },
2065 {"bne",     "s,t,p",    0x14000000, 0xfc000000, CBD|RD_s|RD_t,          0,              I1      },
2066 {"bne",     "s,I,p",    0,    (int) M_BNE_I,    INSN_MACRO,             0,              I1      },
2067 {"bnel",    "s,t,p",    0x54000000, 0xfc000000, CBL|RD_s|RD_t,          0,              I2|T3   },
2068 {"bnel",    "s,I,p",    0,    (int) M_BNEL_I,   INSN_MACRO,             0,              I2|T3   },
2069 {"break",   "",         0x0000000d, 0xffffffff, TRAP,                   0,              I1      },
2070 {"break",   "c",        0x0000000d, 0xfc00ffff, TRAP,                   0,              I1      },
2071 {"break",   "c,q",      0x0000000d, 0xfc00003f, TRAP,                   0,              I1      },
2072 {"c.f.d",   "S,T",      0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
2073 {"c.f.d",   "M,S,T",    0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
2074 {"c.f.s",   "S,T",      0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
2075 {"c.f.s",   "M,S,T",    0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
2076 {"c.f.ps",  "S,T",      0x46c00030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2077 {"c.f.ps",  "M,S,T",    0x46c00030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2078 {"c.un.d",  "S,T",      0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
2079 {"c.un.d",  "M,S,T",    0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
2080 {"c.un.s",  "S,T",      0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
2081 {"c.un.s",  "M,S,T",    0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
2082 {"c.un.ps", "S,T",      0x46c00031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2083 {"c.un.ps", "M,S,T",    0x46c00031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2084 {"c.eq.d",  "S,T",      0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
2085 {"c.eq.d",  "M,S,T",    0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
2086 {"c.eq.s",  "S,T",      0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
2087 {"c.eq.s",  "M,S,T",    0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
2088 {"c.eq.ob", "Y,Q",      0x78000001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,              MX|SB1  },
2089 {"c.eq.ob", "S,T",      0x4ac00001, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2090 {"c.eq.ob", "S,T[e]",   0x48000001, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2091 {"c.eq.ob", "S,k",      0x4bc00001, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2092 {"c.eq.ps", "S,T",      0x46c00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2093 {"c.eq.ps", "M,S,T",    0x46c00032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2094 {"c.eq.qh", "Y,Q",      0x78200001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,              MX      },
2095 {"c.ueq.d", "S,T",      0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
2096 {"c.ueq.d", "M,S,T",    0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
2097 {"c.ueq.s", "S,T",      0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
2098 {"c.ueq.s", "M,S,T",    0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
2099 {"c.ueq.ps","S,T",      0x46c00033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2100 {"c.ueq.ps","M,S,T",    0x46c00033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2101 {"c.olt.d", "S,T",      0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
2102 {"c.olt.d", "M,S,T",    0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
2103 {"c.olt.s", "S,T",      0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
2104 {"c.olt.s", "M,S,T",    0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
2105 {"c.olt.ps","S,T",      0x46c00034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2106 {"c.olt.ps","M,S,T",    0x46c00034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2107 {"c.ult.d", "S,T",      0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
2108 {"c.ult.d", "M,S,T",    0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
2109 {"c.ult.s", "S,T",      0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
2110 {"c.ult.s", "M,S,T",    0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
2111 {"c.ult.ps","S,T",      0x46c00035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2112 {"c.ult.ps","M,S,T",    0x46c00035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2113 {"c.ole.d", "S,T",      0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
2114 {"c.ole.d", "M,S,T",    0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
2115 {"c.ole.s", "S,T",      0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
2116 {"c.ole.s", "M,S,T",    0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
2117 {"c.ole.ps","S,T",      0x46c00036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2118 {"c.ole.ps","M,S,T",    0x46c00036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2119 {"c.ule.d", "S,T",      0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
2120 {"c.ule.d", "M,S,T",    0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
2121 {"c.ule.s", "S,T",      0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
2122 {"c.ule.s", "M,S,T",    0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
2123 {"c.ule.ps","S,T",      0x46c00037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2124 {"c.ule.ps","M,S,T",    0x46c00037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2125 {"c.sf.d",  "S,T",      0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
2126 {"c.sf.d",  "M,S,T",    0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
2127 {"c.sf.s",  "S,T",      0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
2128 {"c.sf.s",  "M,S,T",    0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
2129 {"c.sf.ps", "S,T",      0x46c00038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2130 {"c.sf.ps", "M,S,T",    0x46c00038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2131 {"c.ngle.d","S,T",      0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
2132 {"c.ngle.d","M,S,T",    0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
2133 {"c.ngle.s","S,T",      0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
2134 {"c.ngle.s","M,S,T",    0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
2135 {"c.ngle.ps","S,T",     0x46c00039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2136 {"c.ngle.ps","M,S,T",   0x46c00039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2137 {"c.seq.d", "S,T",      0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
2138 {"c.seq.d", "M,S,T",    0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
2139 {"c.seq.s", "S,T",      0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
2140 {"c.seq.s", "M,S,T",    0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
2141 {"c.seq.ps","S,T",      0x46c0003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2142 {"c.seq.ps","M,S,T",    0x46c0003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2143 {"c.ngl.d", "S,T",      0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
2144 {"c.ngl.d", "M,S,T",    0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
2145 {"c.ngl.s", "S,T",      0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
2146 {"c.ngl.s", "M,S,T",    0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
2147 {"c.ngl.ps","S,T",      0x46c0003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2148 {"c.ngl.ps","M,S,T",    0x46c0003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2149 {"c.lt.d",  "S,T",      0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
2150 {"c.lt.d",  "M,S,T",    0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
2151 {"c.lt.s",  "S,T",      0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
2152 {"c.lt.s",  "M,S,T",    0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
2153 {"c.lt.ob", "Y,Q",      0x78000004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,              MX|SB1  },
2154 {"c.lt.ob", "S,T",      0x4ac00004, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2155 {"c.lt.ob", "S,T[e]",   0x48000004, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2156 {"c.lt.ob", "S,k",      0x4bc00004, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2157 {"c.lt.ps", "S,T",      0x46c0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2158 {"c.lt.ps", "M,S,T",    0x46c0003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2159 {"c.lt.qh", "Y,Q",      0x78200004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,              MX      },
2160 {"c.nge.d", "S,T",      0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
2161 {"c.nge.d", "M,S,T",    0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
2162 {"c.nge.s", "S,T",      0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
2163 {"c.nge.s", "M,S,T",    0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
2164 {"c.nge.ps","S,T",      0x46c0003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2165 {"c.nge.ps","M,S,T",    0x46c0003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2166 {"c.le.d",  "S,T",      0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
2167 {"c.le.d",  "M,S,T",    0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
2168 {"c.le.s",  "S,T",      0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
2169 {"c.le.s",  "M,S,T",    0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
2170 {"c.le.ob", "Y,Q",      0x78000005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,              MX|SB1  },
2171 {"c.le.ob", "S,T",      0x4ac00005, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2172 {"c.le.ob", "S,T[e]",   0x48000005, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2173 {"c.le.ob", "S,k",      0x4bc00005, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2174 {"c.le.ps", "S,T",      0x46c0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2175 {"c.le.ps", "M,S,T",    0x46c0003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2176 {"c.le.qh", "Y,Q",      0x78200005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,              MX      },
2177 {"c.ngt.d", "S,T",      0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
2178 {"c.ngt.d", "M,S,T",    0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I4|I32  },
2179 {"c.ngt.s", "S,T",      0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
2180 {"c.ngt.s", "M,S,T",    0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              I4|I32  },
2181 {"c.ngt.ps","S,T",      0x46c0003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2182 {"c.ngt.ps","M,S,T",    0x46c0003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5|I33  },
2183 {"cabs.eq.d",  "M,S,T", 0x46200072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2184 {"cabs.eq.ps", "M,S,T", 0x46c00072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2185 {"cabs.eq.s",  "M,S,T", 0x46000072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
2186 {"cabs.f.d",   "M,S,T", 0x46200070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2187 {"cabs.f.ps",  "M,S,T", 0x46c00070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2188 {"cabs.f.s",   "M,S,T", 0x46000070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
2189 {"cabs.le.d",  "M,S,T", 0x4620007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2190 {"cabs.le.ps", "M,S,T", 0x46c0007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2191 {"cabs.le.s",  "M,S,T", 0x4600007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
2192 {"cabs.lt.d",  "M,S,T", 0x4620007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2193 {"cabs.lt.ps", "M,S,T", 0x46c0007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2194 {"cabs.lt.s",  "M,S,T", 0x4600007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
2195 {"cabs.nge.d", "M,S,T", 0x4620007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2196 {"cabs.nge.ps","M,S,T", 0x46c0007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2197 {"cabs.nge.s", "M,S,T", 0x4600007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
2198 {"cabs.ngl.d", "M,S,T", 0x4620007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2199 {"cabs.ngl.ps","M,S,T", 0x46c0007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2200 {"cabs.ngl.s", "M,S,T", 0x4600007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
2201 {"cabs.ngle.d","M,S,T", 0x46200079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2202 {"cabs.ngle.ps","M,S,T",0x46c00079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2203 {"cabs.ngle.s","M,S,T", 0x46000079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
2204 {"cabs.ngt.d", "M,S,T", 0x4620007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2205 {"cabs.ngt.ps","M,S,T", 0x46c0007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2206 {"cabs.ngt.s", "M,S,T", 0x4600007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
2207 {"cabs.ole.d", "M,S,T", 0x46200076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2208 {"cabs.ole.ps","M,S,T", 0x46c00076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2209 {"cabs.ole.s", "M,S,T", 0x46000076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
2210 {"cabs.olt.d", "M,S,T", 0x46200074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2211 {"cabs.olt.ps","M,S,T", 0x46c00074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2212 {"cabs.olt.s", "M,S,T", 0x46000074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
2213 {"cabs.seq.d", "M,S,T", 0x4620007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2214 {"cabs.seq.ps","M,S,T", 0x46c0007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2215 {"cabs.seq.s", "M,S,T", 0x4600007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
2216 {"cabs.sf.d",  "M,S,T", 0x46200078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2217 {"cabs.sf.ps", "M,S,T", 0x46c00078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2218 {"cabs.sf.s",  "M,S,T", 0x46000078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
2219 {"cabs.ueq.d", "M,S,T", 0x46200073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2220 {"cabs.ueq.ps","M,S,T", 0x46c00073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2221 {"cabs.ueq.s", "M,S,T", 0x46000073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
2222 {"cabs.ule.d", "M,S,T", 0x46200077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2223 {"cabs.ule.ps","M,S,T", 0x46c00077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2224 {"cabs.ule.s", "M,S,T", 0x46000077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
2225 {"cabs.ult.d", "M,S,T", 0x46200075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2226 {"cabs.ult.ps","M,S,T", 0x46c00075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2227 {"cabs.ult.s", "M,S,T", 0x46000075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
2228 {"cabs.un.d",  "M,S,T", 0x46200071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2229 {"cabs.un.ps", "M,S,T", 0x46c00071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
2230 {"cabs.un.s",  "M,S,T", 0x46000071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,              M3D     },
2231 /* CW4010 instructions which are aliases for the cache instruction.  */
2232 {"flushi",  "",         0xbc010000, 0xffffffff, 0,                      0,              L1      },
2233 {"flushd",  "",         0xbc020000, 0xffffffff, 0,                      0,              L1      },
2234 {"flushid", "",         0xbc030000, 0xffffffff, 0,                      0,              L1      },
2235 {"wb",      "o(b)",     0xbc040000, 0xfc1f0000, SM|RD_b,                0,              L1      },
2236 {"cache",   "k,o(b)",   0xbc000000, 0xfc000000, RD_b,                   0,              I3|I32|T3},
2237 {"cache",   "k,A(b)",   0,    (int) M_CACHE_AB, INSN_MACRO,             0,              I3|I32|T3},
2238 {"ceil.l.d", "D,S",     0x4620000a, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3|I33  },
2239 {"ceil.l.s", "D,S",     0x4600000a, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I3|I33  },
2240 {"ceil.w.d", "D,S",     0x4620000e, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I2      },
2241 {"ceil.w.s", "D,S",     0x4600000e, 0xffff003f, WR_D|RD_S|FP_S,         0,              I2      },
2242 {"mfhc0",   "t,G,H",    0x40400000, 0xffe007f8, LCD|WR_t|RD_C0,       0, I33},
2243 {"mthc0",   "t,G,H",    0x40c00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I33},
2244 {"cfc0",    "t,G",      0x40400000, 0xffe007ff, LCD|WR_t|RD_C0,         0,              I1      },
2245 {"cfc1",    "t,G",      0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S,    0,              I1      },
2246 {"cfc1",    "t,S",      0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S,    0,              I1      },
2247 /* cfc2 is at the bottom of the table.  */
2248 /* cfc3 is at the bottom of the table.  */
2249 {"cftc1",   "d,E",      0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0,            MT32    },
2250 {"cftc1",   "d,T",      0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0,            MT32    },
2251 {"cftc2",   "d,E",      0x41000025, 0xffe007ff, TRAP|LCD|WR_d|RD_C2,    0,              MT32    },
2252 {"clo",     "U,s",      0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s,         0,              I32|N55 },
2253 {"clz",     "U,s",      0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s,         0,              I32|N55 },
2254 {"ctc0",    "t,G",      0x40c00000, 0xffe007ff, COD|RD_t|WR_CC,         0,              I1      },
2255 {"ctc1",    "t,G",      0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S,    0,              I1      },
2256 {"ctc1",    "t,S",      0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S,    0,              I1      },
2257 /* ctc2 is at the bottom of the table.  */
2258 /* ctc3 is at the bottom of the table.  */
2259 {"cttc1",   "t,g",      0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0,            MT32    },
2260 {"cttc1",   "t,S",      0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0,            MT32    },
2261 {"cttc2",   "t,g",      0x41800025, 0xffe007ff, TRAP|COD|RD_t|WR_CC,    0,              MT32    },
2262 {"cvt.d.l", "D,S",      0x46a00021, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3|I33  },
2263 {"cvt.d.s", "D,S",      0x46000021, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I1      },
2264 {"cvt.d.w", "D,S",      0x46800021, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I1      },
2265 {"cvt.l.d", "D,S",      0x46200025, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3|I33  },
2266 {"cvt.l.s", "D,S",      0x46000025, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I3|I33  },
2267 {"cvt.s.l", "D,S",      0x46a00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I3|I33  },
2268 {"cvt.s.d", "D,S",      0x46200020, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I1      },
2269 {"cvt.s.w", "D,S",      0x46800020, 0xffff003f, WR_D|RD_S|FP_S,         0,              I1      },
2270 {"cvt.s.pl","D,S",      0x46c00028, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I5|I33  },
2271 {"cvt.s.pu","D,S",      0x46c00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I5|I33  },
2272 {"cvt.w.d", "D,S",      0x46200024, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I1      },
2273 {"cvt.w.s", "D,S",      0x46000024, 0xffff003f, WR_D|RD_S|FP_S,         0,              I1      },
2274 {"cvt.ps.pw", "D,S",    0x46800026, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              M3D     },
2275 {"cvt.ps.s","D,V,T",    0x46000026, 0xffe0003f, WR_D|RD_S|RD_T|FP_S|FP_D, 0,            I5|I33  },
2276 {"cvt.pw.ps", "D,S",    0x46c00024, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              M3D     },
2277 {"dabs",    "d,v",      0,    (int) M_DABS,     INSN_MACRO,             0,              I3      },
2278 {"dadd",    "d,v,t",    0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I3      },
2279 {"dadd",    "t,r,I",    0,    (int) M_DADD_I,   INSN_MACRO,             0,              I3      },
2280 {"daddi",   "t,r,j",    0x60000000, 0xfc000000, WR_t|RD_s,              0,              I3      },
2281 {"daddiu",  "t,r,j",    0x64000000, 0xfc000000, WR_t|RD_s,              0,              I3      },
2282 {"daddu",   "d,v,t",    0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I3      },
2283 {"daddu",   "t,r,I",    0,    (int) M_DADDU_I,  INSN_MACRO,             0,              I3      },
2284 {"dbreak",  "",         0x7000003f, 0xffffffff, 0,                      0,              N5      },
2285 {"dclo",    "U,s",      0x70000025, 0xfc0007ff, RD_s|WR_d|WR_t,         0,              I64|N55 },
2286 {"dclz",    "U,s",      0x70000024, 0xfc0007ff, RD_s|WR_d|WR_t,         0,              I64|N55 },
2287 /* dctr and dctw are used on the r5000.  */
2288 {"dctr",    "o(b)",     0xbc050000, 0xfc1f0000, RD_b,                   0,              I3      },
2289 {"dctw",    "o(b)",     0xbc090000, 0xfc1f0000, RD_b,                   0,              I3      },
2290 {"deret",   "",         0x4200001f, 0xffffffff, 0,                      0,              I32|G2  },
2291 {"dext",    "t,r,I,+I", 0,    (int) M_DEXT,     INSN_MACRO,             0,              I65     },
2292 {"dext",    "t,r,+A,+C", 0x7c000003, 0xfc00003f, WR_t|RD_s,             0,              I65     },
2293 {"dextm",   "t,r,+A,+G", 0x7c000001, 0xfc00003f, WR_t|RD_s,             0,              I65     },
2294 {"dextu",   "t,r,+E,+H", 0x7c000002, 0xfc00003f, WR_t|RD_s,             0,              I65     },
2295 /* For ddiv, see the comments about div.  */
2296 {"ddiv",    "z,s,t",    0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I3      },
2297 {"ddiv",    "d,v,t",    0,    (int) M_DDIV_3,   INSN_MACRO,             0,              I3      },
2298 {"ddiv",    "d,v,I",    0,    (int) M_DDIV_3I,  INSN_MACRO,             0,              I3      },
2299 /* For ddivu, see the comments about div.  */
2300 {"ddivu",   "z,s,t",    0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I3      },
2301 {"ddivu",   "d,v,t",    0,    (int) M_DDIVU_3,  INSN_MACRO,             0,              I3      },
2302 {"ddivu",   "d,v,I",    0,    (int) M_DDIVU_3I, INSN_MACRO,             0,              I3      },
2303 {"di",      "",         0x41606000, 0xffffffff, WR_t|WR_C0,             0,              I33     },
2304 {"di",      "t",        0x41606000, 0xffe0ffff, WR_t|WR_C0,             0,              I33     },
2305 {"dins",    "t,r,I,+I", 0,    (int) M_DINS,     INSN_MACRO,             0,              I65     },
2306 {"dins",    "t,r,+A,+B", 0x7c000007, 0xfc00003f, WR_t|RD_s,             0,              I65     },
2307 {"dinsm",   "t,r,+A,+F", 0x7c000005, 0xfc00003f, WR_t|RD_s,             0,              I65     },
2308 {"dinsu",   "t,r,+E,+F", 0x7c000006, 0xfc00003f, WR_t|RD_s,             0,              I65     },
2309 /* The MIPS assembler treats the div opcode with two operands as
2310    though the first operand appeared twice (the first operand is both
2311    a source and a destination).  To get the div machine instruction,
2312    you must use an explicit destination of $0.  */
2313 {"div",     "z,s,t",    0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I1      },
2314 {"div",     "z,t",      0x0000001a, 0xffe0ffff, RD_s|RD_t|WR_HILO,      0,              I1      },
2315 {"div",     "d,v,t",    0,    (int) M_DIV_3,    INSN_MACRO,             0,              I1      },
2316 {"div",     "d,v,I",    0,    (int) M_DIV_3I,   INSN_MACRO,             0,              I1      },
2317 {"div.d",   "D,V,T",    0x46200003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I1      },
2318 {"div.s",   "D,V,T",    0x46000003, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              I1      },
2319 {"div.ps",  "D,V,T",    0x46c00003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              SB1     },
2320 /* For divu, see the comments about div.  */
2321 {"divu",    "z,s,t",    0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I1      },
2322 {"divu",    "z,t",      0x0000001b, 0xffe0ffff, RD_s|RD_t|WR_HILO,      0,              I1      },
2323 {"divu",    "d,v,t",    0,    (int) M_DIVU_3,   INSN_MACRO,             0,              I1      },
2324 {"divu",    "d,v,I",    0,    (int) M_DIVU_3I,  INSN_MACRO,             0,              I1      },
2325 {"dla",     "t,A(b)",   0,    (int) M_DLA_AB,   INSN_MACRO,             0,              I3      },
2326 {"dlca",    "t,A(b)",   0,    (int) M_DLCA_AB,  INSN_MACRO,             0,              I3      },
2327 {"dli",     "t,j",      0x24000000, 0xffe00000, WR_t,                   0,              I3      }, /* addiu */
2328 {"dli",     "t,i",      0x34000000, 0xffe00000, WR_t,                   0,              I3      }, /* ori */
2329 {"dli",     "t,I",      0,    (int) M_DLI,      INSN_MACRO,             0,              I3      },
2330 {"dmacc",   "d,s,t",    0x00000029, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,              N412    },
2331 {"dmacchi", "d,s,t",    0x00000229, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,              N412    },
2332 {"dmacchis", "d,s,t",   0x00000629, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,              N412    },
2333 {"dmacchiu", "d,s,t",   0x00000269, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,              N412    },
2334 {"dmacchius", "d,s,t",  0x00000669, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,              N412    },
2335 {"dmaccs",  "d,s,t",    0x00000429, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,              N412    },
2336 {"dmaccu",  "d,s,t",    0x00000069, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,              N412    },
2337 {"dmaccus", "d,s,t",    0x00000469, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d,   0,              N412    },
2338 {"dmadd16", "s,t",      0x00000029, 0xfc00ffff, RD_s|RD_t|MOD_LO,       0,              N411    },
2339 {"dmfc0",   "t,G",      0x40200000, 0xffe007ff, LCD|WR_t|RD_C0,         0,              I3      },
2340 {"dmfc0",   "t,+D",     0x40200000, 0xffe007f8, LCD|WR_t|RD_C0,         0,              I64     },
2341 {"dmfc0",   "t,G,H",    0x40200000, 0xffe007f8, LCD|WR_t|RD_C0,         0,              I64     },
2342 {"dmt",     "",         0x41600bc1, 0xffffffff, TRAP,                   0,              MT32    },
2343 {"dmt",     "t",        0x41600bc1, 0xffe0ffff, TRAP|WR_t,              0,              MT32    },
2344 {"dmtc0",   "t,G",      0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC,   0,              I3      },
2345 {"dmtc0",   "t,+D",     0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,              I64     },
2346 {"dmtc0",   "t,G,H",    0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,              I64     },
2347 {"dmfc1",   "t,S",      0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,     0,              I3      },
2348 {"dmfc1",   "t,G",      0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,     0,              I3      },
2349 {"dmtc1",   "t,S",      0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D,     0,              I3      },
2350 {"dmtc1",   "t,G",      0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D,     0,              I3      },
2351 /* dmfc2 is at the bottom of the table.  */
2352 /* dmtc2 is at the bottom of the table.  */
2353 /* dmfc3 is at the bottom of the table.  */
2354 /* dmtc3 is at the bottom of the table.  */
2355 {"dmul",    "d,v,t",    0,    (int) M_DMUL,     INSN_MACRO,             0,              I3      },
2356 {"dmul",    "d,v,I",    0,    (int) M_DMUL_I,   INSN_MACRO,             0,              I3      },
2357 {"dmulo",   "d,v,t",    0,    (int) M_DMULO,    INSN_MACRO,             0,              I3      },
2358 {"dmulo",   "d,v,I",    0,    (int) M_DMULO_I,  INSN_MACRO,             0,              I3      },
2359 {"dmulou",  "d,v,t",    0,    (int) M_DMULOU,   INSN_MACRO,             0,              I3      },
2360 {"dmulou",  "d,v,I",    0,    (int) M_DMULOU_I, INSN_MACRO,             0,              I3      },
2361 {"dmult",   "s,t",      0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I3      },
2362 {"dmultu",  "s,t",      0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I3      },
2363 {"dneg",    "d,w",      0x0000002e, 0xffe007ff, WR_d|RD_t,              0,              I3      }, /* dsub 0 */
2364 {"dnegu",   "d,w",      0x0000002f, 0xffe007ff, WR_d|RD_t,              0,              I3      }, /* dsubu 0*/
2365 {"drem",    "z,s,t",    0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I3      },
2366 {"drem",    "d,v,t",    3,    (int) M_DREM_3,   INSN_MACRO,             0,              I3      },
2367 {"drem",    "d,v,I",    3,    (int) M_DREM_3I,  INSN_MACRO,             0,              I3      },
2368 {"dremu",   "z,s,t",    0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I3      },
2369 {"dremu",   "d,v,t",    3,    (int) M_DREMU_3,  INSN_MACRO,             0,              I3      },
2370 {"dremu",   "d,v,I",    3,    (int) M_DREMU_3I, INSN_MACRO,             0,              I3      },
2371 {"dret",    "",         0x7000003e, 0xffffffff, 0,                      0,              N5      },
2372 {"drol",    "d,v,t",    0,    (int) M_DROL,     INSN_MACRO,             0,              I3      },
2373 {"drol",    "d,v,I",    0,    (int) M_DROL_I,   INSN_MACRO,             0,              I3      },
2374 {"dror",    "d,v,t",    0,    (int) M_DROR,     INSN_MACRO,             0,              I3      },
2375 {"dror",    "d,v,I",    0,    (int) M_DROR_I,   INSN_MACRO,             0,              I3      },
2376 {"dror",    "d,w,<",    0x0020003a, 0xffe0003f, WR_d|RD_t,              0,              N5|I65  },
2377 {"drorv",   "d,t,s",    0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d,         0,              N5|I65  },
2378 {"dror32",  "d,w,<",    0x0020003e, 0xffe0003f, WR_d|RD_t,              0,              N5|I65  },
2379 {"drotl",   "d,v,t",    0,    (int) M_DROL,     INSN_MACRO,             0,              I65     },
2380 {"drotl",   "d,v,I",    0,    (int) M_DROL_I,   INSN_MACRO,             0,              I65     },
2381 {"drotr",   "d,v,t",    0,    (int) M_DROR,     INSN_MACRO,             0,              I65     },
2382 {"drotr",   "d,v,I",    0,    (int) M_DROR_I,   INSN_MACRO,             0,              I65     },
2383 {"drotrv",  "d,t,s",    0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d,         0,              I65     },
2384 {"drotr32", "d,w,<",    0x0020003e, 0xffe0003f, WR_d|RD_t,              0,              I65     },
2385 {"dsbh",    "d,w",      0x7c0000a4, 0xffe007ff, WR_d|RD_t,              0,              I65     },
2386 {"dshd",    "d,w",      0x7c000164, 0xffe007ff, WR_d|RD_t,              0,              I65     },
2387 {"dsllv",   "d,t,s",    0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I3      },
2388 {"dsll32",  "d,w,<",    0x0000003c, 0xffe0003f, WR_d|RD_t,              0,              I3      },
2389 {"dsll",    "d,w,s",    0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I3      }, /* dsllv */
2390 {"dsll",    "d,w,>",    0x0000003c, 0xffe0003f, WR_d|RD_t,              0,              I3      }, /* dsll32 */
2391 {"dsll",    "d,w,<",    0x00000038, 0xffe0003f, WR_d|RD_t,              0,              I3      },
2392 {"dsrav",   "d,t,s",    0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I3      },
2393 {"dsra32",  "d,w,<",    0x0000003f, 0xffe0003f, WR_d|RD_t,              0,              I3      },
2394 {"dsra",    "d,w,s",    0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I3      }, /* dsrav */
2395 {"dsra",    "d,w,>",    0x0000003f, 0xffe0003f, WR_d|RD_t,              0,              I3      }, /* dsra32 */
2396 {"dsra",    "d,w,<",    0x0000003b, 0xffe0003f, WR_d|RD_t,              0,              I3      },
2397 {"dsrlv",   "d,t,s",    0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I3      },
2398 {"dsrl32",  "d,w,<",    0x0000003e, 0xffe0003f, WR_d|RD_t,              0,              I3      },
2399 {"dsrl",    "d,w,s",    0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I3      }, /* dsrlv */
2400 {"dsrl",    "d,w,>",    0x0000003e, 0xffe0003f, WR_d|RD_t,              0,              I3      }, /* dsrl32 */
2401 {"dsrl",    "d,w,<",    0x0000003a, 0xffe0003f, WR_d|RD_t,              0,              I3      },
2402 {"dsub",    "d,v,t",    0x0000002e, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I3      },
2403 {"dsub",    "d,v,I",    0,    (int) M_DSUB_I,   INSN_MACRO,             0,              I3      },
2404 {"dsubu",   "d,v,t",    0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I3      },
2405 {"dsubu",   "d,v,I",    0,    (int) M_DSUBU_I,  INSN_MACRO,             0,              I3      },
2406 {"dvpe",    "",         0x41600001, 0xffffffff, TRAP,                   0,              MT32    },
2407 {"dvpe",    "t",        0x41600001, 0xffe0ffff, TRAP|WR_t,              0,              MT32    },
2408 {"ei",      "",         0x41606020, 0xffffffff, WR_t|WR_C0,             0,              I33     },
2409 {"ei",      "t",        0x41606020, 0xffe0ffff, WR_t|WR_C0,             0,              I33     },
2410 {"emt",     "",         0x41600be1, 0xffffffff, TRAP,                   0,              MT32    },
2411 {"emt",     "t",        0x41600be1, 0xffe0ffff, TRAP|WR_t,              0,              MT32    },
2412 {"eret",    "",         0x42000018, 0xffffffff, 0,                      0,              I3|I32  },
2413 {"eretnc",  "",         0x42000058, 0xffffffff, 0,                    0, I33},
2414 {"evpe",    "",         0x41600021, 0xffffffff, TRAP,                   0,              MT32    },
2415 {"evpe",    "t",        0x41600021, 0xffe0ffff, TRAP|WR_t,              0,              MT32    },
2416 {"ext",     "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s,             0,              I33     },
2417 {"floor.l.d", "D,S",    0x4620000b, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3|I33  },
2418 {"floor.l.s", "D,S",    0x4600000b, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I3|I33  },
2419 {"floor.w.d", "D,S",    0x4620000f, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I2      },
2420 {"floor.w.s", "D,S",    0x4600000f, 0xffff003f, WR_D|RD_S|FP_S,         0,              I2      },
2421 {"hibernate","",        0x42000023, 0xffffffff, 0,                      0,              V1      },
2422 {"ins",     "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s,             0,              I33     },
2423 {"jr",      "s",        0x00000008, 0xfc1fffff, UBD|RD_s,               0,              I1      },
2424 {"jr",      "s",        0x00000009, 0xfc1fffff, UBD|RD_s,               0,              I32R6   }, /* jalr */
2425 /* jr.hb is officially MIPS{32,64}R2, but it works on R1 as jr with
2426    the same hazard barrier effect.  */
2427 {"jr.hb",   "s",        0x00000408, 0xfc1fffff, UBD|RD_s,               0,              I32     },
2428 {"jr.hb",   "s",        0x00000409, 0xfc1fffff, UBD|RD_s,               0,              I32R6   }, /* jalr.hb */
2429 {"j",       "s",        0x00000008, 0xfc1fffff, UBD|RD_s,               0,              I1      }, /* jr */
2430 /* SVR4 PIC code requires special handling for j, so it must be a
2431    macro.  */
2432 {"j",       "a",        0,     (int) M_J_A,     INSN_MACRO,             0,              I1      },
2433 /* This form of j is used by the disassembler and internally by the
2434    assembler, but will never match user input (because the line above
2435    will match first).  */
2436 {"j",       "a",        0x08000000, 0xfc000000, UBD,                    0,              I1      },
2437 {"jalr",    "s",        0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d,          0,              I1      },
2438 {"jalr",    "d,s",      0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d,          0,              I1      },
2439 /* jalr.hb is officially MIPS{32,64}R2, but it works on R1 as jalr
2440    with the same hazard barrier effect.  */
2441 {"jalr.hb", "s",        0x0000fc09, 0xfc1fffff, UBD|RD_s|WR_d,          0,              I32     },
2442 {"jalr.hb", "d,s",      0x00000409, 0xfc1f07ff, UBD|RD_s|WR_d,          0,              I32     },
2443 /* SVR4 PIC code requires special handling for jal, so it must be a
2444    macro.  */
2445 {"jal",     "d,s",      0,     (int) M_JAL_2,   INSN_MACRO,             0,              I1      },
2446 {"jal",     "s",        0,     (int) M_JAL_1,   INSN_MACRO,             0,              I1      },
2447 {"jal",     "a",        0,     (int) M_JAL_A,   INSN_MACRO,             0,              I1      },
2448 /* This form of jal is used by the disassembler and internally by the
2449    assembler, but will never match user input (because the line above
2450    will match first).  */
2451 {"jal",     "a",        0x0c000000, 0xfc000000, UBD|WR_31,              0,              I1      },
2452 {"jalx",    "a",        0x74000000, 0xfc000000, UBD|WR_31,              0,              I16     },
2453 {"la",      "t,A(b)",   0,    (int) M_LA_AB,    INSN_MACRO,             0,              I1      },
2454 {"lb",      "t,o(b)",   0x80000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I1      },
2455 {"lb",      "t,A(b)",   0,    (int) M_LB_AB,    INSN_MACRO,             0,              I1      },
2456 {"lbu",     "t,o(b)",   0x90000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I1      },
2457 {"lbu",     "t,A(b)",   0,    (int) M_LBU_AB,   INSN_MACRO,             0,              I1      },
2458 {"lca",     "t,A(b)",   0,    (int) M_LCA_AB,   INSN_MACRO,             0,              I1      },
2459 {"ld",      "t,o(b)",   0xdc000000, 0xfc000000, WR_t|RD_b,              0,              I3      },
2460 {"ld",      "t,o(b)",   0,    (int) M_LD_OB,    INSN_MACRO,             0,              I1      },
2461 {"ld",      "t,A(b)",   0,    (int) M_LD_AB,    INSN_MACRO,             0,              I1      },
2462 {"ldc1",    "T,o(b)",   0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,     0,              I2      },
2463 {"ldc1",    "E,o(b)",   0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,     0,              I2      },
2464 {"ldc1",    "T,A(b)",   0,    (int) M_LDC1_AB,  INSN_MACRO,             0,              I2      },
2465 {"ldc1",    "E,A(b)",   0,    (int) M_LDC1_AB,  INSN_MACRO,             0,              I2      },
2466 {"l.d",     "T,o(b)",   0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D,     0,              I2      }, /* ldc1 */
2467 {"l.d",     "T,o(b)",   0,    (int) M_L_DOB,    INSN_MACRO,             0,              I1      },
2468 {"l.d",     "T,A(b)",   0,    (int) M_L_DAB,    INSN_MACRO,             0,              I1      },
2469 {"ldc2",    "E,o(b)",   0xd8000000, 0xfc000000, CLD|RD_b|WR_CC,         0,              I2      },
2470 {"ldc2",    "E,A(b)",   0,    (int) M_LDC2_AB,  INSN_MACRO,             0,              I2      },
2471 {"ldc3",    "E,o(b)",   0xdc000000, 0xfc000000, CLD|RD_b|WR_CC,         0,              I2      },
2472 {"ldc3",    "E,A(b)",   0,    (int) M_LDC3_AB,  INSN_MACRO,             0,              I2      },
2473 {"ldl",     "t,o(b)",   0x68000000, 0xfc000000, LDD|WR_t|RD_b,          0,              I3      },
2474 {"ldl",     "t,A(b)",   0,    (int) M_LDL_AB,   INSN_MACRO,             0,              I3      },
2475 {"ldr",     "t,o(b)",   0x6c000000, 0xfc000000, LDD|WR_t|RD_b,          0,              I3      },
2476 {"ldr",     "t,A(b)",   0,    (int) M_LDR_AB,   INSN_MACRO,             0,              I3      },
2477 {"ldxc1",   "D,t(b)",   0x4c000001, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0,             I4|I33  },
2478 {"lh",      "t,o(b)",   0x84000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I1      },
2479 {"lh",      "t,A(b)",   0,    (int) M_LH_AB,    INSN_MACRO,             0,              I1      },
2480 {"lhu",     "t,o(b)",   0x94000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I1      },
2481 {"lhu",     "t,A(b)",   0,    (int) M_LHU_AB,   INSN_MACRO,             0,              I1      },
2482 /* li is at the start of the table.  */
2483 {"li.d",    "t,F",      0,    (int) M_LI_D,     INSN_MACRO,             0,              I1      },
2484 {"li.d",    "T,L",      0,    (int) M_LI_DD,    INSN_MACRO,             0,              I1      },
2485 {"li.s",    "t,f",      0,    (int) M_LI_S,     INSN_MACRO,             0,              I1      },
2486 {"li.s",    "T,l",      0,    (int) M_LI_SS,    INSN_MACRO,             0,              I1      },
2487 {"ll",      "t,o(b)",   0xc0000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I2      },
2488 {"ll",      "t,A(b)",   0,    (int) M_LL_AB,    INSN_MACRO,             0,              I2      },
2489 {"lld",     "t,o(b)",   0xd0000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I3      },
2490 {"lld",     "t,A(b)",   0,    (int) M_LLD_AB,   INSN_MACRO,             0,              I3      },
2491 {"lui",     "t,u",      0x3c000000, 0xffe00000, WR_t,                   0,              I1      },
2492 {"aui",     "s,t,u",    0x3c000000, 0xfc000000, RD_s|WR_t,            0, I32R6},
2493 {"luxc1",   "D,t(b)",   0x4c000005, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0,             I5|I33|N55},
2494 {"lw",      "t,o(b)",   0x8c000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I1      },
2495 {"lw",      "t,A(b)",   0,    (int) M_LW_AB,    INSN_MACRO,             0,              I1      },
2496 {"lwc0",    "E,o(b)",   0xc0000000, 0xfc000000, CLD|RD_b|WR_CC,         0,              I1      },
2497 {"lwc0",    "E,A(b)",   0,    (int) M_LWC0_AB,  INSN_MACRO,             0,              I1      },
2498 {"lwc1",    "T,o(b)",   0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S,     0,              I1      },
2499 {"lwc1",    "E,o(b)",   0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S,     0,              I1      },
2500 {"lwc1",    "T,A(b)",   0,    (int) M_LWC1_AB,  INSN_MACRO,             0,              I1      },
2501 {"lwc1",    "E,A(b)",   0,    (int) M_LWC1_AB,  INSN_MACRO,             0,              I1      },
2502 {"l.s",     "T,o(b)",   0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S,     0,              I1      }, /* lwc1 */
2503 {"l.s",     "T,A(b)",   0,    (int) M_LWC1_AB,  INSN_MACRO,             0,              I1      },
2504 {"lwc2",    "E,o(b)",   0xc8000000, 0xfc000000, CLD|RD_b|WR_CC,         0,              I1      },
2505 {"lwc2",    "E,A(b)",   0,    (int) M_LWC2_AB,  INSN_MACRO,             0,              I1      },
2506 {"lwc3",    "E,o(b)",   0xcc000000, 0xfc000000, CLD|RD_b|WR_CC,         0,              I1      },
2507 {"lwc3",    "E,A(b)",   0,    (int) M_LWC3_AB,  INSN_MACRO,             0,              I1      },
2508 {"lwl",     "t,o(b)",   0x88000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I1      },
2509 {"lwl",     "t,A(b)",   0,    (int) M_LWL_AB,   INSN_MACRO,             0,              I1      },
2510 {"lcache",  "t,o(b)",   0x88000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I2      }, /* same */
2511 {"lcache",  "t,A(b)",   0,    (int) M_LWL_AB,   INSN_MACRO,             0,              I2      }, /* as lwl */
2512 {"lwr",     "t,o(b)",   0x98000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I1      },
2513 {"lwr",     "t,A(b)",   0,    (int) M_LWR_AB,   INSN_MACRO,             0,              I1      },
2514 {"flush",   "t,o(b)",   0x98000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I2      }, /* same */
2515 {"flush",   "t,A(b)",   0,    (int) M_LWR_AB,   INSN_MACRO,             0,              I2      }, /* as lwr */
2516 {"fork",    "d,s,t",    0x7c000008, 0xfc0007ff, TRAP|WR_d|RD_s|RD_t,    0,              MT32    },
2517 {"lwu",     "t,o(b)",   0x9c000000, 0xfc000000, LDD|RD_b|WR_t,          0,              I3      },
2518 {"lwu",     "t,A(b)",   0,    (int) M_LWU_AB,   INSN_MACRO,             0,              I3      },
2519 {"lwxc1",   "D,t(b)",   0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0,             I4|I33  },
2520 {"lwxs",    "d,t(b)",   0x70000088, 0xfc0007ff, LDD|RD_b|RD_t|WR_d,     0,              SMT     },
2521 {"macc",    "d,s,t",    0x00000028, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N412    },
2522 {"macc",    "d,s,t",    0x00000158, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
2523 {"maccs",   "d,s,t",    0x00000428, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N412    },
2524 {"macchi",  "d,s,t",    0x00000228, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N412    },
2525 {"macchi",  "d,s,t",    0x00000358, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
2526 {"macchis", "d,s,t",    0x00000628, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N412    },
2527 {"macchiu", "d,s,t",    0x00000268, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N412    },
2528 {"macchiu", "d,s,t",    0x00000359, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
2529 {"macchius","d,s,t",    0x00000668, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N412    },
2530 {"maccu",   "d,s,t",    0x00000068, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N412    },
2531 {"maccu",   "d,s,t",    0x00000159, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
2532 {"maccus",  "d,s,t",    0x00000468, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N412    },
2533 {"mad",     "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,              P3      },
2534 {"madu",    "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,              P3      },
2535 {"madd.d",  "D,R,S,T",  0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,    0,         I4|I33  },
2536 {"madd.s",  "D,R,S,T",  0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S,    0,         I4|I33  },
2537 {"madd.ps", "D,R,S,T",  0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,    0,         I5|I33  },
2538 {"madd",    "s,t",      0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO,           0,         L1      },
2539 {"madd",    "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO,          0,         I32|N55 },
2540 {"madd",    "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M,      0,         G1      },
2541 {"madd",    "7,s,t",    0x70000000, 0xfc00e7ff, MOD_a|RD_s|RD_t,             0,         D33     },
2542 {"madd",    "d,s,t",    0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,         G1      },
2543 {"maddp",   "s,t",      0x70000441, 0xfc00ffff, RD_s|RD_t|MOD_HILO,          0,         SMT     },
2544 {"maddu",   "s,t",      0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO,           0,         L1      },
2545 {"maddu",   "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO,          0,         I32|N55 },
2546 {"maddu",   "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M,      0,         G1      },
2547 {"maddu",   "7,s,t",    0x70000001, 0xfc00e7ff, MOD_a|RD_s|RD_t,             0,         D33     },
2548 {"maddu",   "d,s,t",    0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,         G1      },
2549 {"madd16",  "s,t",      0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,              N411    },
2550 {"max.ob",  "X,Y,Q",    0x78000007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
2551 {"max.ob",  "D,S,T",    0x4ac00007, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2552 {"max.ob",  "D,S,T[e]", 0x48000007, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
2553 {"max.ob",  "D,S,k",    0x4bc00007, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2554 {"max.qh",  "X,Y,Q",    0x78200007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2555 {"mfpc",    "t,P",      0x4000c801, 0xffe0ffc1, LCD|WR_t|RD_C0,         0,              M1|N5   },
2556 {"mfps",    "t,P",      0x4000c800, 0xffe0ffc1, LCD|WR_t|RD_C0,         0,              M1|N5   },
2557 {"mftacx",  "d",        0x41020021, 0xffff07ff, TRAP|WR_d|RD_a,         0,              MT32    },
2558 {"mftacx",  "d,*",      0x41020021, 0xfff307ff, TRAP|WR_d|RD_a,         0,              MT32    },
2559 {"mftc0",   "d,+t",     0x41000000, 0xffe007ff, TRAP|LCD|WR_d|RD_C0,    0,              MT32    },
2560 {"mftc0",   "d,+T",     0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0,    0,              MT32    },
2561 {"mftc0",   "d,E,H",    0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0,    0,              MT32    },
2562 {"mftc1",   "d,T",      0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0,             MT32    },
2563 {"mftc1",   "d,E",      0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0,             MT32    },
2564 {"mftc2",   "d,E",      0x41000024, 0xffe007ff, TRAP|LCD|WR_d|RD_C2,    0,              MT32    },
2565 {"mftdsp",  "d",        0x41100021, 0xffff07ff, TRAP|WR_d,              0,              MT32    },
2566 {"mftgpr",  "d,t",      0x41000020, 0xffe007ff, TRAP|WR_d|RD_t,         0,              MT32    },
2567 {"mfthc1",  "d,T",      0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0,             MT32    },
2568 {"mfthc1",  "d,E",      0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0,             MT32    },
2569 {"mfthc2",  "d,E",      0x41000034, 0xffe007ff, TRAP|LCD|WR_d|RD_C2,    0,              MT32    },
2570 {"mfthi",   "d",        0x41010021, 0xffff07ff, TRAP|WR_d|RD_a,         0,              MT32    },
2571 {"mfthi",   "d,*",      0x41010021, 0xfff307ff, TRAP|WR_d|RD_a,         0,              MT32    },
2572 {"mftlo",   "d",        0x41000021, 0xffff07ff, TRAP|WR_d|RD_a,         0,              MT32    },
2573 {"mftlo",   "d,*",      0x41000021, 0xfff307ff, TRAP|WR_d|RD_a,         0,              MT32    },
2574 {"mftr",    "d,t,!,H,$", 0x41000000, 0xffe007c8, TRAP|WR_d,             0,              MT32    },
2575 {"mfc0",    "t,G",      0x40000000, 0xffe007ff, LCD|WR_t|RD_C0,         0,              I1      },
2576 {"mfc0",    "t,+D",     0x40000000, 0xffe007f8, LCD|WR_t|RD_C0,         0,              I32     },
2577 {"mfc0",    "t,G,H",    0x40000000, 0xffe007f8, LCD|WR_t|RD_C0,         0,              I32     },
2578 {"mfc1",    "t,S",      0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S,     0,              I1      },
2579 {"mfc1",    "t,G",      0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S,     0,              I1      },
2580 {"mfhc1",   "t,S",      0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,     0,              I33     },
2581 {"mfhc1",   "t,G",      0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D,     0,              I33     },
2582 /* mfc2 is at the bottom of the table.  */
2583 /* mfhc2 is at the bottom of the table.  */
2584 /* mfc3 is at the bottom of the table.  */
2585 {"mfdr",    "t,G",      0x7000003d, 0xffe007ff, LCD|WR_t|RD_C0,         0,              N5      },
2586 {"mfhi",    "d",        0x00000010, 0xffff07ff, WR_d|RD_HI,             0,              I1      },
2587 {"mfhi",    "d,9",      0x00000010, 0xff9f07ff, WR_d|RD_HI,             0,              D32     },
2588 {"mflo",    "d",        0x00000012, 0xffff07ff, WR_d|RD_LO,             0,              I1      },
2589 {"mflo",    "d,9",      0x00000012, 0xff9f07ff, WR_d|RD_LO,             0,              D32     },
2590 {"mflhxu",  "d",        0x00000052, 0xffff07ff, WR_d|MOD_HILO,          0,              SMT     },
2591 {"min.ob",  "X,Y,Q",    0x78000006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
2592 {"min.ob",  "D,S,T",    0x4ac00006, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2593 {"min.ob",  "D,S,T[e]", 0x48000006, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
2594 {"min.ob",  "D,S,k",    0x4bc00006, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2595 {"min.qh",  "X,Y,Q",    0x78200006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2596 {"mov.d",   "D,S",      0x46200006, 0xffff003f, WR_D|RD_S|FP_D,         0,              I1      },
2597 {"mov.s",   "D,S",      0x46000006, 0xffff003f, WR_D|RD_S|FP_S,         0,              I1      },
2598 {"mov.ps",  "D,S",      0x46c00006, 0xffff003f, WR_D|RD_S|FP_D,         0,              I5|I33  },
2599 {"movf",    "d,s,N",    0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0,           I4|I32  },
2600 {"movf.d",  "D,S,N",    0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              I4|I32  },
2601 {"movf.l",  "D,S,N",    0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              MX|SB1  },
2602 {"movf.l",  "X,Y,N",    0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              MX|SB1  },
2603 {"movf.s",  "D,S,N",    0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,   0,              I4|I32  },
2604 {"movf.ps", "D,S,N",    0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              I5|I33  },
2605 {"movn",    "d,v,t",    0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I4|I32  },
2606 {"ffc",     "d,v",      0x0000000b, 0xfc1f07ff, WR_d|RD_s,              0,              L1      },
2607 {"movn.d",  "D,S,t",    0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,              I4|I32  },
2608 {"movn.l",  "D,S,t",    0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,              MX|SB1  },
2609 {"movn.l",  "X,Y,t",    0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,              MX|SB1  },
2610 {"movn.s",  "D,S,t",    0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,    0,              I4|I32  },
2611 {"movn.ps", "D,S,t",    0x46c00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,              I5|I33  },
2612 {"movt",    "d,s,N",    0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0,           I4|I32  },
2613 {"movt.d",  "D,S,N",    0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              I4|I32  },
2614 {"movt.l",  "D,S,N",    0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              MX|SB1  },
2615 {"movt.l",  "X,Y,N",    0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              MX|SB1  },
2616 {"movt.s",  "D,S,N",    0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,   0,              I4|I32  },
2617 {"movt.ps", "D,S,N",    0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              I5|I33  },
2618 {"movz",    "d,v,t",    0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I4|I32  },
2619 {"ffs",     "d,v",      0x0000000a, 0xfc1f07ff, WR_d|RD_s,              0,              L1      },
2620 {"movz.d",  "D,S,t",    0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,              I4|I32  },
2621 {"movz.l",  "D,S,t",    0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,              MX|SB1  },
2622 {"movz.l",  "X,Y,t",    0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,              MX|SB1  },
2623 {"movz.s",  "D,S,t",    0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S,    0,              I4|I32  },
2624 {"movz.ps", "D,S,t",    0x46c00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,              I5|I33  },
2625 {"msac",    "d,s,t",    0x000001d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
2626 {"msacu",   "d,s,t",    0x000001d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
2627 {"msachi",  "d,s,t",    0x000003d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
2628 {"msachiu", "d,s,t",    0x000003d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
2629 /* move is at the top of the table.  */
2630 {"msgn.qh", "X,Y,Q",    0x78200000, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2631 {"msub.d",  "D,R,S,T",  0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I4|I33  },
2632 {"msub.s",  "D,R,S,T",  0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0,            I4|I33  },
2633 {"msub.ps", "D,R,S,T",  0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I5|I33  },
2634 {"msub",    "s,t",      0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              L1      },
2635 {"msub",    "s,t",      0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,              I32|N55 },
2636 {"msub",    "7,s,t",    0x70000004, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33     },
2637 {"msubu",   "s,t",      0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              L1      },
2638 {"msubu",   "s,t",      0x70000005, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,              I32|N55 },
2639 {"msubu",   "7,s,t",    0x70000005, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33     },
2640 {"mtpc",    "t,P",      0x4080c801, 0xffe0ffc1, COD|RD_t|WR_C0,         0,              M1|N5   },
2641 {"mtps",    "t,P",      0x4080c800, 0xffe0ffc1, COD|RD_t|WR_C0,         0,              M1|N5   },
2642 {"mtc0",    "t,G",      0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC,   0,              I1      },
2643 {"mtc0",    "t,+D",     0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,              I32     },
2644 {"mtc0",    "t,G,H",    0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC,   0,              I32     },
2645 {"mtc1",    "t,S",      0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S,     0,              I1      },
2646 {"mtc1",    "t,G",      0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S,     0,              I1      },
2647 {"mthc1",   "t,S",      0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D,     0,              I33     },
2648 {"mthc1",   "t,G",      0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D,     0,              I33     },
2649 /* mtc2 is at the bottom of the table.  */
2650 /* mthc2 is at the bottom of the table.  */
2651 /* mtc3 is at the bottom of the table.  */
2652 {"mtdr",    "t,G",      0x7080003d, 0xffe007ff, COD|RD_t|WR_C0,         0,              N5      },
2653 {"mthi",    "s",        0x00000011, 0xfc1fffff, RD_s|WR_HI,             0,              I1      },
2654 {"mthi",    "s,7",      0x00000011, 0xfc1fe7ff, RD_s|WR_HI,             0,              D32     },
2655 {"mtlo",    "s",        0x00000013, 0xfc1fffff, RD_s|WR_LO,             0,              I1      },
2656 {"mtlo",    "s,7",      0x00000013, 0xfc1fe7ff, RD_s|WR_LO,             0,              D32     },
2657 {"mtlhx",   "s",        0x00000053, 0xfc1fffff, RD_s|MOD_HILO,          0,              SMT     },
2658 {"mttc0",   "t,G",      0x41800000, 0xffe007ff, TRAP|COD|RD_t|WR_C0|WR_CC, 0,           MT32    },
2659 {"mttc0",   "t,+D",     0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0,           MT32    },
2660 {"mttc0",   "t,G,H",    0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0,           MT32    },
2661 {"mttc1",   "t,S",      0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0,             MT32    },
2662 {"mttc1",   "t,G",      0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0,             MT32    },
2663 {"mttc2",   "t,g",      0x41800024, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0,           MT32    },
2664 {"mttacx",  "t",        0x41801021, 0xffe0ffff, TRAP|WR_a|RD_t,         0,              MT32    },
2665 {"mttacx",  "t,&",      0x41801021, 0xffe09fff, TRAP|WR_a|RD_t,         0,              MT32    },
2666 {"mttdsp",  "t",        0x41808021, 0xffe0ffff, TRAP|RD_t,              0,              MT32    },
2667 {"mttgpr",  "t,d",      0x41800020, 0xffe007ff, TRAP|WR_d|RD_t,         0,              MT32    },
2668 {"mtthc1",  "t,S",      0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0,             MT32    },
2669 {"mtthc1",  "t,G",      0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0,             MT32    },
2670 {"mtthc2",  "t,g",      0x41800034, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0,           MT32    },
2671 {"mtthi",   "t",        0x41800821, 0xffe0ffff, TRAP|WR_a|RD_t,         0,              MT32    },
2672 {"mtthi",   "t,&",      0x41800821, 0xffe09fff, TRAP|WR_a|RD_t,         0,              MT32    },
2673 {"mttlo",   "t",        0x41800021, 0xffe0ffff, TRAP|WR_a|RD_t,         0,              MT32    },
2674 {"mttlo",   "t,&",      0x41800021, 0xffe09fff, TRAP|WR_a|RD_t,         0,              MT32    },
2675 {"mttr",    "t,d,!,H,$", 0x41800000, 0xffe007c8, TRAP|RD_t,             0,              MT32    },
2676 {"mul.d",   "D,V,T",    0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I1      },
2677 {"mul.s",   "D,V,T",    0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              I1      },
2678 {"mul.ob",  "X,Y,Q",    0x78000030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
2679 {"mul.ob",  "D,S,T",    0x4ac00030, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2680 {"mul.ob",  "D,S,T[e]", 0x48000030, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
2681 {"mul.ob",  "D,S,k",    0x4bc00030, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2682 {"mul.ps",  "D,V,T",    0x46c00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5|I33  },
2683 {"mul.qh",  "X,Y,Q",    0x78200030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2684 {"mul",     "d,v,t",    0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              I32|P3|N55},
2685 {"mul",     "d,s,t",    0x00000058, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N54     },
2686 {"mul",     "d,v,t",    0,    (int) M_MUL,      INSN_MACRO,             0,              I1      },
2687 {"mul",     "d,v,I",    0,    (int) M_MUL_I,    INSN_MACRO,             0,              I1      },
2688 {"mula.ob", "Y,Q",      0x78000033, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
2689 {"mula.ob", "S,T",      0x4ac00033, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2690 {"mula.ob", "S,T[e]",   0x48000033, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2691 {"mula.ob", "S,k",      0x4bc00033, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2692 {"mula.qh", "Y,Q",      0x78200033, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
2693 {"mulhi",   "d,s,t",    0x00000258, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
2694 {"mulhiu",  "d,s,t",    0x00000259, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
2695 {"mull.ob", "Y,Q",      0x78000433, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
2696 {"mull.ob", "S,T",      0x4ac00433, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2697 {"mull.ob", "S,T[e]",   0x48000433, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2698 {"mull.ob", "S,k",      0x4bc00433, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2699 {"mull.qh", "Y,Q",      0x78200433, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
2700 {"mulo",    "d,v,t",    0,    (int) M_MULO,     INSN_MACRO,             0,              I1      },
2701 {"mulo",    "d,v,I",    0,    (int) M_MULO_I,   INSN_MACRO,             0,              I1      },
2702 {"mulou",   "d,v,t",    0,    (int) M_MULOU,    INSN_MACRO,             0,              I1      },
2703 {"mulou",   "d,v,I",    0,    (int) M_MULOU_I,  INSN_MACRO,             0,              I1      },
2704 {"mulr.ps", "D,S,T",    0x46c0001a, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              M3D     },
2705 {"muls",    "d,s,t",    0x000000d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
2706 {"mulsu",   "d,s,t",    0x000000d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
2707 {"mulshi",  "d,s,t",    0x000002d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
2708 {"mulshiu", "d,s,t",    0x000002d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
2709 {"muls.ob", "Y,Q",      0x78000032, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
2710 {"muls.ob", "S,T",      0x4ac00032, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2711 {"muls.ob", "S,T[e]",   0x48000032, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2712 {"muls.ob", "S,k",      0x4bc00032, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2713 {"muls.qh", "Y,Q",      0x78200032, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
2714 {"mulsl.ob", "Y,Q",     0x78000432, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
2715 {"mulsl.ob", "S,T",     0x4ac00432, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2716 {"mulsl.ob", "S,T[e]",  0x48000432, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2717 {"mulsl.ob", "S,k",     0x4bc00432, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
2718 {"mulsl.qh", "Y,Q",     0x78200432, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
2719 {"mult",    "s,t",      0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0,              I1      },
2720 {"mult",    "7,s,t",    0x00000018, 0xfc00e7ff, WR_a|RD_s|RD_t,         0,              D33     },
2721 {"mult",    "d,s,t",    0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,         G1      },
2722 {"multp",   "s,t",      0x00000459, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,              SMT     },
2723 {"multu",   "s,t",      0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0,              I1      },
2724 {"multu",   "7,s,t",    0x00000019, 0xfc00e7ff, WR_a|RD_s|RD_t,         0,              D33     },
2725 {"multu",   "d,s,t",    0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0,         G1      },
2726 {"mulu",    "d,s,t",    0x00000059, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N5      },
2727 {"neg",     "d,w",      0x00000022, 0xffe007ff, WR_d|RD_t,              0,              I1      }, /* sub 0 */
2728 {"negu",    "d,w",      0x00000023, 0xffe007ff, WR_d|RD_t,              0,              I1      }, /* subu 0 */
2729 {"neg.d",   "D,V",      0x46200007, 0xffff003f, WR_D|RD_S|FP_D,         0,              I1      },
2730 {"neg.s",   "D,V",      0x46000007, 0xffff003f, WR_D|RD_S|FP_S,         0,              I1      },
2731 {"neg.ps",  "D,V",      0x46c00007, 0xffff003f, WR_D|RD_S|FP_D,         0,              I5|I33  },
2732 {"nmadd.d", "D,R,S,T",  0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I4|I33  },
2733 {"nmadd.s", "D,R,S,T",  0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0,            I4|I33  },
2734 {"nmadd.ps","D,R,S,T",  0x4c000036, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I5|I33  },
2735 {"nmsub.d", "D,R,S,T",  0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I4|I33  },
2736 {"nmsub.s", "D,R,S,T",  0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0,            I4|I33  },
2737 {"nmsub.ps","D,R,S,T",  0x4c00003e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I5|I33  },
2738 /* nop is at the start of the table.  */
2739 {"nor",     "d,v,t",    0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
2740 {"nor",     "t,r,I",    0,    (int) M_NOR_I,    INSN_MACRO,             0,              I1      },
2741 {"nor.ob",  "X,Y,Q",    0x7800000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
2742 {"nor.ob",  "D,S,T",    0x4ac0000f, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2743 {"nor.ob",  "D,S,T[e]", 0x4800000f, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
2744 {"nor.ob",  "D,S,k",    0x4bc0000f, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2745 {"nor.qh",  "X,Y,Q",    0x7820000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2746 {"not",     "d,v",      0x00000027, 0xfc1f07ff, WR_d|RD_s|RD_t,         0,              I1      },/*nor d,s,0*/
2747 {"or",      "d,v,t",    0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
2748 {"or",      "t,r,I",    0,    (int) M_OR_I,     INSN_MACRO,             0,              I1      },
2749 {"or.ob",   "X,Y,Q",    0x7800000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
2750 {"or.ob",   "D,S,T",    0x4ac0000e, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2751 {"or.ob",   "D,S,T[e]", 0x4800000e, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
2752 {"or.ob",   "D,S,k",    0x4bc0000e, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2753 {"or.qh",   "X,Y,Q",    0x7820000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2754 {"ori",     "t,r,i",    0x34000000, 0xfc000000, WR_t|RD_s,              0,              I1      },
2755 {"pabsdiff.ob", "X,Y,Q",0x78000009, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              SB1     },
2756 {"pabsdiffc.ob", "Y,Q", 0x78000035, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        SB1     },
2757 {"pavg.ob", "X,Y,Q",    0x78000008, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              SB1     },
2758 {"pickf.ob", "X,Y,Q",   0x78000002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
2759 {"pickf.ob", "D,S,T",   0x4ac00002, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2760 {"pickf.ob", "D,S,T[e]",0x48000002, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
2761 {"pickf.ob", "D,S,k",   0x4bc00002, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2762 {"pickf.qh", "X,Y,Q",   0x78200002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2763 {"pickt.ob", "X,Y,Q",   0x78000003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
2764 {"pickt.ob", "D,S,T",   0x4ac00003, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2765 {"pickt.ob", "D,S,T[e]",0x48000003, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
2766 {"pickt.ob", "D,S,k",   0x4bc00003, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2767 {"pickt.qh", "X,Y,Q",   0x78200003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2768 {"pll.ps",  "D,V,T",    0x46c0002c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5|I33  },
2769 {"plu.ps",  "D,V,T",    0x46c0002d, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5|I33  },
2770   /* pref and prefx are at the start of the table.  */
2771 {"pul.ps",  "D,V,T",    0x46c0002e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5|I33  },
2772 {"puu.ps",  "D,V,T",    0x46c0002f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5|I33  },
2773 {"pperm",   "s,t",      0x70000481, 0xfc00ffff, MOD_HILO|RD_s|RD_t,     0,              SMT     },
2774 {"rach.ob", "X",        0x7a00003f, 0xfffff83f, WR_D|FP_D,              RD_MACC,        MX|SB1  },
2775 {"rach.ob", "D",        0x4a00003f, 0xfffff83f, WR_D,                   0,              N54     },
2776 {"rach.qh", "X",        0x7a20003f, 0xfffff83f, WR_D|FP_D,              RD_MACC,        MX      },
2777 {"racl.ob", "X",        0x7800003f, 0xfffff83f, WR_D|FP_D,              RD_MACC,        MX|SB1  },
2778 {"racl.ob", "D",        0x4800003f, 0xfffff83f, WR_D,                   0,              N54     },
2779 {"racl.qh", "X",        0x7820003f, 0xfffff83f, WR_D|FP_D,              RD_MACC,        MX      },
2780 {"racm.ob", "X",        0x7900003f, 0xfffff83f, WR_D|FP_D,              RD_MACC,        MX|SB1  },
2781 {"racm.ob", "D",        0x4900003f, 0xfffff83f, WR_D,                   0,              N54     },
2782 {"racm.qh", "X",        0x7920003f, 0xfffff83f, WR_D|FP_D,              RD_MACC,        MX      },
2783 {"recip.d", "D,S",      0x46200015, 0xffff003f, WR_D|RD_S|FP_D,         0,              I4|I33  },
2784 {"recip.ps","D,S",      0x46c00015, 0xffff003f, WR_D|RD_S|FP_D,         0,              SB1     },
2785 {"recip.s", "D,S",      0x46000015, 0xffff003f, WR_D|RD_S|FP_S,         0,              I4|I33  },
2786 {"recip1.d",  "D,S",    0x4620001d, 0xffff003f, WR_D|RD_S|FP_D,         0,              M3D     },
2787 {"recip1.ps", "D,S",    0x46c0001d, 0xffff003f, WR_D|RD_S|FP_S,         0,              M3D     },
2788 {"recip1.s",  "D,S",    0x4600001d, 0xffff003f, WR_D|RD_S|FP_S,         0,              M3D     },
2789 {"recip2.d",  "D,S,T",  0x4620001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              M3D     },
2790 {"recip2.ps", "D,S,T",  0x46c0001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              M3D     },
2791 {"recip2.s",  "D,S,T",  0x4600001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              M3D     },
2792 {"rem",     "z,s,t",    0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I1      },
2793 {"rem",     "d,v,t",    0,    (int) M_REM_3,    INSN_MACRO,             0,              I1      },
2794 {"rem",     "d,v,I",    0,    (int) M_REM_3I,   INSN_MACRO,             0,              I1      },
2795 {"remu",    "z,s,t",    0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,              I1      },
2796 {"remu",    "d,v,t",    0,    (int) M_REMU_3,   INSN_MACRO,             0,              I1      },
2797 {"remu",    "d,v,I",    0,    (int) M_REMU_3I,  INSN_MACRO,             0,              I1      },
2798 {"rdhwr",   "t,K",      0x7c00003b, 0xffe007ff, WR_t,                   0,              I33     },
2799 {"rdpgpr",  "d,w",      0x41400000, 0xffe007ff, WR_d,                   0,              I33     },
2800 {"rfe",     "",         0x42000010, 0xffffffff, 0,                      0,              I1|T3   },
2801 {"rnas.qh", "X,Q",      0x78200025, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX      },
2802 {"rnau.ob", "X,Q",      0x78000021, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX|SB1  },
2803 {"rnau.qh", "X,Q",      0x78200021, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX      },
2804 {"rnes.qh", "X,Q",      0x78200026, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX      },
2805 {"rneu.ob", "X,Q",      0x78000022, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX|SB1  },
2806 {"rneu.qh", "X,Q",      0x78200022, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX      },
2807 {"rol",     "d,v,t",    0,    (int) M_ROL,      INSN_MACRO,             0,              I1      },
2808 {"rol",     "d,v,I",    0,    (int) M_ROL_I,    INSN_MACRO,             0,              I1      },
2809 {"ror",     "d,v,t",    0,    (int) M_ROR,      INSN_MACRO,             0,              I1      },
2810 {"ror",     "d,v,I",    0,    (int) M_ROR_I,    INSN_MACRO,             0,              I1      },
2811 {"ror",     "d,w,<",    0x00200002, 0xffe0003f, WR_d|RD_t,              0,              N5|I33|SMT },
2812 {"rorv",    "d,t,s",    0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d,         0,              N5|I33|SMT },
2813 {"rotl",    "d,v,t",    0,    (int) M_ROL,      INSN_MACRO,             0,              I33|SMT },
2814 {"rotl",    "d,v,I",    0,    (int) M_ROL_I,    INSN_MACRO,             0,              I33|SMT },
2815 {"rotr",    "d,v,t",    0,    (int) M_ROR,      INSN_MACRO,             0,              I33|SMT },
2816 {"rotr",    "d,v,I",    0,    (int) M_ROR_I,    INSN_MACRO,             0,              I33|SMT },
2817 {"rotrv",   "d,t,s",    0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d,         0,              I33|SMT },
2818 {"round.l.d", "D,S",    0x46200008, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3|I33  },
2819 {"round.l.s", "D,S",    0x46000008, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I3|I33  },
2820 {"round.w.d", "D,S",    0x4620000c, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I2      },
2821 {"round.w.s", "D,S",    0x4600000c, 0xffff003f, WR_D|RD_S|FP_S,         0,              I2      },
2822 {"rsqrt.d", "D,S",      0x46200016, 0xffff003f, WR_D|RD_S|FP_D,         0,              I4|I33  },
2823 {"rsqrt.ps","D,S",      0x46c00016, 0xffff003f, WR_D|RD_S|FP_D,         0,              SB1     },
2824 {"rsqrt.s", "D,S",      0x46000016, 0xffff003f, WR_D|RD_S|FP_S,         0,              I4|I33  },
2825 {"rsqrt1.d",  "D,S",    0x4620001e, 0xffff003f, WR_D|RD_S|FP_D,         0,              M3D     },
2826 {"rsqrt1.ps", "D,S",    0x46c0001e, 0xffff003f, WR_D|RD_S|FP_S,         0,              M3D     },
2827 {"rsqrt1.s",  "D,S",    0x4600001e, 0xffff003f, WR_D|RD_S|FP_S,         0,              M3D     },
2828 {"rsqrt2.d",  "D,S,T",  0x4620001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              M3D     },
2829 {"rsqrt2.ps", "D,S,T",  0x46c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              M3D     },
2830 {"rsqrt2.s",  "D,S,T",  0x4600001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              M3D     },
2831 {"rzs.qh",  "X,Q",      0x78200024, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX      },
2832 {"rzu.ob",  "X,Q",      0x78000020, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX|SB1  },
2833 {"rzu.ob",  "D,k",      0x4bc00020, 0xffe0f83f, WR_D|RD_S|RD_T,         0,              N54     },
2834 {"rzu.qh",  "X,Q",      0x78200020, 0xfc20f83f, WR_D|RD_T|FP_D,         RD_MACC,        MX      },
2835 {"sb",      "t,o(b)",   0xa0000000, 0xfc000000, SM|RD_t|RD_b,           0,              I1      },
2836 {"sb",      "t,A(b)",   0,    (int) M_SB_AB,    INSN_MACRO,             0,              I1      },
2837 {"sc",      "t,o(b)",   0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b,      0,              I2      },
2838 {"sc",      "t,A(b)",   0,    (int) M_SC_AB,    INSN_MACRO,             0,              I2      },
2839 {"scd",     "t,o(b)",   0xf0000000, 0xfc000000, SM|RD_t|WR_t|RD_b,      0,              I3      },
2840 {"scd",     "t,A(b)",   0,    (int) M_SCD_AB,   INSN_MACRO,             0,              I3      },
2841 {"sd",      "t,o(b)",   0xfc000000, 0xfc000000, SM|RD_t|RD_b,           0,              I3      },
2842 {"sd",      "t,o(b)",   0,    (int) M_SD_OB,    INSN_MACRO,             0,              I1      },
2843 {"sd",      "t,A(b)",   0,    (int) M_SD_AB,    INSN_MACRO,             0,              I1      },
2844 {"sdbbp",   "",         0x0000000e, 0xffffffff, TRAP,                   0,              G2      },
2845 {"sdbbp",   "c",        0x0000000e, 0xfc00ffff, TRAP,                   0,              G2      },
2846 {"sdbbp",   "c,q",      0x0000000e, 0xfc00003f, TRAP,                   0,              G2      },
2847 {"sdbbp",   "",         0x7000003f, 0xffffffff, TRAP,                   0,              I32     },
2848 {"sdbbp",   "B",        0x7000003f, 0xfc00003f, TRAP,                   0,              I32     },
2849 {"sdc1",    "T,o(b)",   0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,      0,              I2      },
2850 {"sdc1",    "E,o(b)",   0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,      0,              I2      },
2851 {"sdc1",    "T,A(b)",   0,    (int) M_SDC1_AB,  INSN_MACRO,             0,              I2      },
2852 {"sdc1",    "E,A(b)",   0,    (int) M_SDC1_AB,  INSN_MACRO,             0,              I2      },
2853 {"sdc2",    "E,o(b)",   0xf8000000, 0xfc000000, SM|RD_C2|RD_b,          0,              I2      },
2854 {"sdc2",    "E,A(b)",   0,    (int) M_SDC2_AB,  INSN_MACRO,             0,              I2      },
2855 {"sdc3",    "E,o(b)",   0xfc000000, 0xfc000000, SM|RD_C3|RD_b,          0,              I2      },
2856 {"sdc3",    "E,A(b)",   0,    (int) M_SDC3_AB,  INSN_MACRO,             0,              I2      },
2857 {"s.d",     "T,o(b)",   0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D,      0,              I2      },
2858 {"s.d",     "T,o(b)",   0,    (int) M_S_DOB,    INSN_MACRO,             0,              I1      },
2859 {"s.d",     "T,A(b)",   0,    (int) M_S_DAB,    INSN_MACRO,             0,              I1      },
2860 {"sdl",     "t,o(b)",   0xb0000000, 0xfc000000, SM|RD_t|RD_b,           0,              I3      },
2861 {"sdl",     "t,A(b)",   0,    (int) M_SDL_AB,   INSN_MACRO,             0,              I3      },
2862 {"sdr",     "t,o(b)",   0xb4000000, 0xfc000000, SM|RD_t|RD_b,           0,              I3      },
2863 {"sdr",     "t,A(b)",   0,    (int) M_SDR_AB,   INSN_MACRO,             0,              I3      },
2864 {"sdxc1",   "S,t(b)",   0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_D, 0,              I4|I33  },
2865 {"seb",     "d,w",      0x7c000420, 0xffe007ff, WR_d|RD_t,              0,              I33     },
2866 {"seh",     "d,w",      0x7c000620, 0xffe007ff, WR_d|RD_t,              0,              I33     },
2867 {"selsl",   "d,v,t",    0x00000005, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              L1      },
2868 {"selsr",   "d,v,t",    0x00000001, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              L1      },
2869 {"seq",     "d,v,t",    0,    (int) M_SEQ,      INSN_MACRO,             0,              I1      },
2870 {"seq",     "d,v,I",    0,    (int) M_SEQ_I,    INSN_MACRO,             0,              I1      },
2871 {"sge",     "d,v,t",    0,    (int) M_SGE,      INSN_MACRO,             0,              I1      },
2872 {"sge",     "d,v,I",    0,    (int) M_SGE_I,    INSN_MACRO,             0,              I1      },
2873 {"sgeu",    "d,v,t",    0,    (int) M_SGEU,     INSN_MACRO,             0,              I1      },
2874 {"sgeu",    "d,v,I",    0,    (int) M_SGEU_I,   INSN_MACRO,             0,              I1      },
2875 {"sgt",     "d,v,t",    0,    (int) M_SGT,      INSN_MACRO,             0,              I1      },
2876 {"sgt",     "d,v,I",    0,    (int) M_SGT_I,    INSN_MACRO,             0,              I1      },
2877 {"sgtu",    "d,v,t",    0,    (int) M_SGTU,     INSN_MACRO,             0,              I1      },
2878 {"sgtu",    "d,v,I",    0,    (int) M_SGTU_I,   INSN_MACRO,             0,              I1      },
2879 {"sh",      "t,o(b)",   0xa4000000, 0xfc000000, SM|RD_t|RD_b,           0,              I1      },
2880 {"sh",      "t,A(b)",   0,    (int) M_SH_AB,    INSN_MACRO,             0,              I1      },
2881 {"shfl.bfla.qh", "X,Y,Z", 0x7a20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,              MX      },
2882 {"shfl.mixh.ob", "X,Y,Z", 0x7980001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,              MX|SB1  },
2883 {"shfl.mixh.ob", "D,S,T", 0x4980001f, 0xffe0003f, WR_D|RD_S|RD_T,       0,              N54     },
2884 {"shfl.mixh.qh", "X,Y,Z", 0x7820001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,              MX      },
2885 {"shfl.mixl.ob", "X,Y,Z", 0x79c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,              MX|SB1  },
2886 {"shfl.mixl.ob", "D,S,T", 0x49c0001f, 0xffe0003f, WR_D|RD_S|RD_T,       0,              N54     },
2887 {"shfl.mixl.qh", "X,Y,Z", 0x78a0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,              MX      },
2888 {"shfl.pach.ob", "X,Y,Z", 0x7900001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,              MX|SB1  },
2889 {"shfl.pach.ob", "D,S,T", 0x4900001f, 0xffe0003f, WR_D|RD_S|RD_T,       0,              N54     },
2890 {"shfl.pach.qh", "X,Y,Z", 0x7920001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,              MX      },
2891 {"shfl.pacl.ob", "D,S,T", 0x4940001f, 0xffe0003f, WR_D|RD_S|RD_T,       0,              N54     },
2892 {"shfl.repa.qh", "X,Y,Z", 0x7b20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,              MX      },
2893 {"shfl.repb.qh", "X,Y,Z", 0x7ba0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,              MX      },
2894 {"shfl.upsl.ob", "X,Y,Z", 0x78c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,  0,              MX|SB1  },
2895 {"sle",     "d,v,t",    0,    (int) M_SLE,      INSN_MACRO,             0,              I1      },
2896 {"sle",     "d,v,I",    0,    (int) M_SLE_I,    INSN_MACRO,             0,              I1      },
2897 {"sleu",    "d,v,t",    0,    (int) M_SLEU,     INSN_MACRO,             0,              I1      },
2898 {"sleu",    "d,v,I",    0,    (int) M_SLEU_I,   INSN_MACRO,             0,              I1      },
2899 {"sllv",    "d,t,s",    0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I1      },
2900 {"sll",     "d,w,s",    0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I1      }, /* sllv */
2901 {"sll",     "d,w,<",    0x00000000, 0xffe0003f, WR_d|RD_t,              0,              I1      },
2902 {"sll.ob",  "X,Y,Q",    0x78000010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
2903 {"sll.ob",  "D,S,T[e]", 0x48000010, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
2904 {"sll.ob",  "D,S,k",    0x4bc00010, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2905 {"sll.qh",  "X,Y,Q",    0x78200010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2906 {"slt",     "d,v,t",    0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
2907 {"slt",     "d,v,I",    0,    (int) M_SLT_I,    INSN_MACRO,             0,              I1      },
2908 {"slti",    "t,r,j",    0x28000000, 0xfc000000, WR_t|RD_s,              0,              I1      },
2909 {"sltiu",   "t,r,j",    0x2c000000, 0xfc000000, WR_t|RD_s,              0,              I1      },
2910 {"sltu",    "d,v,t",    0x0000002b, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
2911 {"sltu",    "d,v,I",    0,    (int) M_SLTU_I,   INSN_MACRO,             0,              I1      },
2912 {"sne",     "d,v,t",    0,    (int) M_SNE,      INSN_MACRO,             0,              I1      },
2913 {"sne",     "d,v,I",    0,    (int) M_SNE_I,    INSN_MACRO,             0,              I1      },
2914 {"sqrt.d",  "D,S",      0x46200004, 0xffff003f, WR_D|RD_S|FP_D,         0,              I2      },
2915 {"sqrt.s",  "D,S",      0x46000004, 0xffff003f, WR_D|RD_S|FP_S,         0,              I2      },
2916 {"sqrt.ps", "D,S",      0x46c00004, 0xffff003f, WR_D|RD_S|FP_D,         0,              SB1     },
2917 {"srav",    "d,t,s",    0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I1      },
2918 {"sra",     "d,w,s",    0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I1      }, /* srav */
2919 {"sra",     "d,w,<",    0x00000003, 0xffe0003f, WR_d|RD_t,              0,              I1      },
2920 {"sra.qh",  "X,Y,Q",    0x78200013, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2921 {"srlv",    "d,t,s",    0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I1      },
2922 {"srl",     "d,w,s",    0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I1      }, /* srlv */
2923 {"srl",     "d,w,<",    0x00000002, 0xffe0003f, WR_d|RD_t,              0,              I1      },
2924 {"srl.ob",  "X,Y,Q",    0x78000012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
2925 {"srl.ob",  "D,S,T[e]", 0x48000012, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
2926 {"srl.ob",  "D,S,k",    0x4bc00012, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2927 {"srl.qh",  "X,Y,Q",    0x78200012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2928 /* ssnop is at the start of the table.  */
2929 {"standby", "",         0x42000021, 0xffffffff, 0,                      0,              V1      },
2930 {"sub",     "d,v,t",    0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
2931 {"sub",     "d,v,I",    0,    (int) M_SUB_I,    INSN_MACRO,             0,              I1      },
2932 {"sub.d",   "D,V,T",    0x46200001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I1      },
2933 {"sub.s",   "D,V,T",    0x46000001, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              I1      },
2934 {"sub.ob",  "X,Y,Q",    0x7800000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
2935 {"sub.ob",  "D,S,T",    0x4ac0000a, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2936 {"sub.ob",  "D,S,T[e]", 0x4800000a, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
2937 {"sub.ob",  "D,S,k",    0x4bc0000a, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
2938 {"sub.ps",  "D,V,T",    0x46c00001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5|I33  },
2939 {"sub.qh",  "X,Y,Q",    0x7820000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
2940 {"suba.ob", "Y,Q",      0x78000036, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
2941 {"suba.qh", "Y,Q",      0x78200036, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
2942 {"subl.ob", "Y,Q",      0x78000436, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
2943 {"subl.qh", "Y,Q",      0x78200436, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
2944 {"subu",    "d,v,t",    0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
2945 {"subu",    "d,v,I",    0,    (int) M_SUBU_I,   INSN_MACRO,             0,              I1      },
2946 {"suspend", "",         0x42000022, 0xffffffff, 0,                      0,              V1      },
2947 {"suxc1",   "S,t(b)",   0x4c00000d, 0xfc0007ff, SM|RD_S|RD_t|RD_b,      0,              I5|I33|N55},
2948 {"sw",      "t,o(b)",   0xac000000, 0xfc000000, SM|RD_t|RD_b,           0,              I1      },
2949 {"sw",      "t,A(b)",   0,    (int) M_SW_AB,    INSN_MACRO,             0,              I1      },
2950 {"swc0",    "E,o(b)",   0xe0000000, 0xfc000000, SM|RD_C0|RD_b,          0,              I1      },
2951 {"swc0",    "E,A(b)",   0,    (int) M_SWC0_AB,  INSN_MACRO,             0,              I1      },
2952 {"swc1",    "T,o(b)",   0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S,      0,              I1      },
2953 {"swc1",    "E,o(b)",   0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S,      0,              I1      },
2954 {"swc1",    "T,A(b)",   0,    (int) M_SWC1_AB,  INSN_MACRO,             0,              I1      },
2955 {"swc1",    "E,A(b)",   0,    (int) M_SWC1_AB,  INSN_MACRO,             0,              I1      },
2956 {"s.s",     "T,o(b)",   0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S,      0,              I1      }, /* swc1 */
2957 {"s.s",     "T,A(b)",   0,    (int) M_SWC1_AB,  INSN_MACRO,             0,              I1      },
2958 {"swc2",    "E,o(b)",   0xe8000000, 0xfc000000, SM|RD_C2|RD_b,          0,              I1      },
2959 {"swc2",    "E,A(b)",   0,    (int) M_SWC2_AB,  INSN_MACRO,             0,              I1      },
2960 {"swc3",    "E,o(b)",   0xec000000, 0xfc000000, SM|RD_C3|RD_b,          0,              I1      },
2961 {"swc3",    "E,A(b)",   0,    (int) M_SWC3_AB,  INSN_MACRO,             0,              I1      },
2962 {"swl",     "t,o(b)",   0xa8000000, 0xfc000000, SM|RD_t|RD_b,           0,              I1      },
2963 {"swl",     "t,A(b)",   0,    (int) M_SWL_AB,   INSN_MACRO,             0,              I1      },
2964 {"scache",  "t,o(b)",   0xa8000000, 0xfc000000, RD_t|RD_b,              0,              I2      }, /* same */
2965 {"scache",  "t,A(b)",   0,    (int) M_SWL_AB,   INSN_MACRO,             0,              I2      }, /* as swl */
2966 {"swr",     "t,o(b)",   0xb8000000, 0xfc000000, SM|RD_t|RD_b,           0,              I1      },
2967 {"swr",     "t,A(b)",   0,    (int) M_SWR_AB,   INSN_MACRO,             0,              I1      },
2968 {"invalidate", "t,o(b)",0xb8000000, 0xfc000000, RD_t|RD_b,              0,              I2      }, /* same */
2969 {"invalidate", "t,A(b)",0,    (int) M_SWR_AB,   INSN_MACRO,             0,              I2      }, /* as swr */
2970 {"swxc1",   "S,t(b)",   0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_S, 0,              I4|I33  },
2971 {"sync",    "",         0x0000000f, 0xffffffff, INSN_SYNC,              0,              I2|G1   },
2972 {"sync.p",  "",         0x0000040f, 0xffffffff, INSN_SYNC,              0,              I2      },
2973 {"sync.l",  "",         0x0000000f, 0xffffffff, INSN_SYNC,              0,              I2      },
2974 {"synci",   "o(b)",     0x041f0000, 0xfc1f0000, SM|RD_b,                0,              I33     },
2975 {"syscall", "",         0x0000000c, 0xffffffff, TRAP,                   0,              I1      },
2976 {"syscall", "B",        0x0000000c, 0xfc00003f, TRAP,                   0,              I1      },
2977 {"teqi",    "s,j",      0x040c0000, 0xfc1f0000, RD_s|TRAP,              0,              I2      },
2978 {"teq",     "s,t",      0x00000034, 0xfc00ffff, RD_s|RD_t|TRAP,         0,              I2      },
2979 {"teq",     "s,t,q",    0x00000034, 0xfc00003f, RD_s|RD_t|TRAP,         0,              I2      },
2980 {"teq",     "s,j",      0x040c0000, 0xfc1f0000, RD_s|TRAP,              0,              I2      }, /* teqi */
2981 {"teq",     "s,I",      0,    (int) M_TEQ_I,    INSN_MACRO,             0,              I2      },
2982 {"tgei",    "s,j",      0x04080000, 0xfc1f0000, RD_s|TRAP,              0,              I2      },
2983 {"tge",     "s,t",      0x00000030, 0xfc00ffff, RD_s|RD_t|TRAP,         0,              I2      },
2984 {"tge",     "s,t,q",    0x00000030, 0xfc00003f, RD_s|RD_t|TRAP,         0,              I2      },
2985 {"tge",     "s,j",      0x04080000, 0xfc1f0000, RD_s|TRAP,              0,              I2      }, /* tgei */
2986 {"tge",     "s,I",      0,    (int) M_TGE_I,    INSN_MACRO,             0,              I2      },
2987 {"tgeiu",   "s,j",      0x04090000, 0xfc1f0000, RD_s|TRAP,              0,              I2      },
2988 {"tgeu",    "s,t",      0x00000031, 0xfc00ffff, RD_s|RD_t|TRAP,         0,              I2      },
2989 {"tgeu",    "s,t,q",    0x00000031, 0xfc00003f, RD_s|RD_t|TRAP,         0,              I2      },
2990 {"tgeu",    "s,j",      0x04090000, 0xfc1f0000, RD_s|TRAP,              0,              I2      }, /* tgeiu */
2991 {"tgeu",    "s,I",      0,    (int) M_TGEU_I,   INSN_MACRO,             0,              I2      },
2992 {"tlbp",    "",         0x42000008, 0xffffffff, INSN_TLB,               0,              I1      },
2993 {"tlbr",    "",         0x42000001, 0xffffffff, INSN_TLB,               0,              I1      },
2994 {"tlbwi",   "",         0x42000002, 0xffffffff, INSN_TLB,               0,              I1      },
2995 {"tlbinv",  "",         0x42000003, 0xffffffff, INSN_TLB,             0, I32  },
2996 {"tlbinvf", "",         0x42000004, 0xffffffff, INSN_TLB,             0, I32  },
2997 {"tlbwr",   "",         0x42000006, 0xffffffff, INSN_TLB,               0,              I1      },
2998 {"tlti",    "s,j",      0x040a0000, 0xfc1f0000, RD_s|TRAP,              0,              I2      },
2999 {"tlt",     "s,t",      0x00000032, 0xfc00ffff, RD_s|RD_t|TRAP,         0,              I2      },
3000 {"tlt",     "s,t,q",    0x00000032, 0xfc00003f, RD_s|RD_t|TRAP,         0,              I2      },
3001 {"tlt",     "s,j",      0x040a0000, 0xfc1f0000, RD_s|TRAP,              0,              I2      }, /* tlti */
3002 {"tlt",     "s,I",      0,    (int) M_TLT_I,    INSN_MACRO,             0,              I2      },
3003 {"tltiu",   "s,j",      0x040b0000, 0xfc1f0000, RD_s|TRAP,              0,              I2      },
3004 {"tltu",    "s,t",      0x00000033, 0xfc00ffff, RD_s|RD_t|TRAP,         0,              I2      },
3005 {"tltu",    "s,t,q",    0x00000033, 0xfc00003f, RD_s|RD_t|TRAP,         0,              I2      },
3006 {"tltu",    "s,j",      0x040b0000, 0xfc1f0000, RD_s|TRAP,              0,              I2      }, /* tltiu */
3007 {"tltu",    "s,I",      0,    (int) M_TLTU_I,   INSN_MACRO,             0,              I2      },
3008 {"tnei",    "s,j",      0x040e0000, 0xfc1f0000, RD_s|TRAP,              0,              I2      },
3009 {"tne",     "s,t",      0x00000036, 0xfc00ffff, RD_s|RD_t|TRAP,         0,              I2      },
3010 {"tne",     "s,t,q",    0x00000036, 0xfc00003f, RD_s|RD_t|TRAP,         0,              I2      },
3011 {"tne",     "s,j",      0x040e0000, 0xfc1f0000, RD_s|TRAP,              0,              I2      }, /* tnei */
3012 {"tne",     "s,I",      0,    (int) M_TNE_I,    INSN_MACRO,             0,              I2      },
3013 {"trunc.l.d", "D,S",    0x46200009, 0xffff003f, WR_D|RD_S|FP_D,         0,              I3|I33  },
3014 {"trunc.l.s", "D,S",    0x46000009, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I3|I33  },
3015 {"trunc.w.d", "D,S",    0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I2      },
3016 {"trunc.w.d", "D,S,x",  0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D,    0,              I2      },
3017 {"trunc.w.d", "D,S,t",  0,    (int) M_TRUNCWD,  INSN_MACRO,             0,              I1      },
3018 {"trunc.w.s", "D,S",    0x4600000d, 0xffff003f, WR_D|RD_S|FP_S,         0,              I2      },
3019 {"trunc.w.s", "D,S,x",  0x4600000d, 0xffff003f, WR_D|RD_S|FP_S,         0,              I2      },
3020 {"trunc.w.s", "D,S,t",  0,    (int) M_TRUNCWS,  INSN_MACRO,             0,              I1      },
3021 {"uld",     "t,o(b)",   0,    (int) M_ULD,      INSN_MACRO,             0,              I3      },
3022 {"uld",     "t,A(b)",   0,    (int) M_ULD_A,    INSN_MACRO,             0,              I3      },
3023 {"ulh",     "t,o(b)",   0,    (int) M_ULH,      INSN_MACRO,             0,              I1      },
3024 {"ulh",     "t,A(b)",   0,    (int) M_ULH_A,    INSN_MACRO,             0,              I1      },
3025 {"ulhu",    "t,o(b)",   0,    (int) M_ULHU,     INSN_MACRO,             0,              I1      },
3026 {"ulhu",    "t,A(b)",   0,    (int) M_ULHU_A,   INSN_MACRO,             0,              I1      },
3027 {"ulw",     "t,o(b)",   0,    (int) M_ULW,      INSN_MACRO,             0,              I1      },
3028 {"ulw",     "t,A(b)",   0,    (int) M_ULW_A,    INSN_MACRO,             0,              I1      },
3029 {"usd",     "t,o(b)",   0,    (int) M_USD,      INSN_MACRO,             0,              I3      },
3030 {"usd",     "t,A(b)",   0,    (int) M_USD_A,    INSN_MACRO,             0,              I3      },
3031 {"ush",     "t,o(b)",   0,    (int) M_USH,      INSN_MACRO,             0,              I1      },
3032 {"ush",     "t,A(b)",   0,    (int) M_USH_A,    INSN_MACRO,             0,              I1      },
3033 {"usw",     "t,o(b)",   0,    (int) M_USW,      INSN_MACRO,             0,              I1      },
3034 {"usw",     "t,A(b)",   0,    (int) M_USW_A,    INSN_MACRO,             0,              I1      },
3035 {"wach.ob", "Y",        0x7a00003e, 0xffff07ff, RD_S|FP_D,              WR_MACC,        MX|SB1  },
3036 {"wach.ob", "S",        0x4a00003e, 0xffff07ff, RD_S,                   0,              N54     },
3037 {"wach.qh", "Y",        0x7a20003e, 0xffff07ff, RD_S|FP_D,              WR_MACC,        MX      },
3038 {"wacl.ob", "Y,Z",      0x7800003e, 0xffe007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
3039 {"wacl.ob", "S,T",      0x4800003e, 0xffe007ff, RD_S|RD_T,              0,              N54     },
3040 {"wacl.qh", "Y,Z",      0x7820003e, 0xffe007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
3041 {"wait",    "",         0x42000020, 0xffffffff, TRAP,                   0,              I3|I32  },
3042 {"wait",    "J",        0x42000020, 0xfe00003f, TRAP,                   0,              I32|N55 },
3043 {"waiti",   "",         0x42000020, 0xffffffff, TRAP,                   0,              L1      },
3044 {"wrpgpr",  "d,w",      0x41c00000, 0xffe007ff, RD_t,                   0,              I33     },
3045 {"wsbh",    "d,w",      0x7c0000a0, 0xffe007ff, WR_d|RD_t,              0,              I33     },
3046 {"xor",     "d,v,t",    0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
3047 {"xor",     "t,r,I",    0,    (int) M_XOR_I,    INSN_MACRO,             0,              I1      },
3048 {"xor.ob",  "X,Y,Q",    0x7800000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
3049 {"xor.ob",  "D,S,T",    0x4ac0000d, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
3050 {"xor.ob",  "D,S,T[e]", 0x4800000d, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
3051 {"xor.ob",  "D,S,k",    0x4bc0000d, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
3052 {"xor.qh",  "X,Y,Q",    0x7820000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
3053 {"xori",    "t,r,i",    0x38000000, 0xfc000000, WR_t|RD_s,              0,              I1      },
3054 {"yield",   "s",        0x7c000009, 0xfc1fffff, TRAP|RD_s,              0,              MT32    },
3055 {"yield",   "d,s",      0x7c000009, 0xfc1f07ff, TRAP|WR_d|RD_s,         0,              MT32    },
3056
3057 /* User Defined Instruction.  */
3058 {"udi0",     "s,t,d,+1",0x70000010, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3059 {"udi0",     "s,t,+2",  0x70000010, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3060 {"udi0",     "s,+3",    0x70000010, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3061 {"udi0",     "+4",      0x70000010, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3062 {"udi1",     "s,t,d,+1",0x70000011, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3063 {"udi1",     "s,t,+2",  0x70000011, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3064 {"udi1",     "s,+3",    0x70000011, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3065 {"udi1",     "+4",      0x70000011, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3066 {"udi2",     "s,t,d,+1",0x70000012, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3067 {"udi2",     "s,t,+2",  0x70000012, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3068 {"udi2",     "s,+3",    0x70000012, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3069 {"udi2",     "+4",      0x70000012, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3070 {"udi3",     "s,t,d,+1",0x70000013, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3071 {"udi3",     "s,t,+2",  0x70000013, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3072 {"udi3",     "s,+3",    0x70000013, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3073 {"udi3",     "+4",      0x70000013, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3074 {"udi4",     "s,t,d,+1",0x70000014, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3075 {"udi4",     "s,t,+2",  0x70000014, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3076 {"udi4",     "s,+3",    0x70000014, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3077 {"udi4",     "+4",      0x70000014, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3078 {"udi5",     "s,t,d,+1",0x70000015, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3079 {"udi5",     "s,t,+2",  0x70000015, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3080 {"udi5",     "s,+3",    0x70000015, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3081 {"udi5",     "+4",      0x70000015, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3082 {"udi6",     "s,t,d,+1",0x70000016, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3083 {"udi6",     "s,t,+2",  0x70000016, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3084 {"udi6",     "s,+3",    0x70000016, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3085 {"udi6",     "+4",      0x70000016, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3086 {"udi7",     "s,t,d,+1",0x70000017, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3087 {"udi7",     "s,t,+2",  0x70000017, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3088 {"udi7",     "s,+3",    0x70000017, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3089 {"udi7",     "+4",      0x70000017, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3090 {"udi8",     "s,t,d,+1",0x70000018, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3091 {"udi8",     "s,t,+2",  0x70000018, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3092 {"udi8",     "s,+3",    0x70000018, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3093 {"udi8",     "+4",      0x70000018, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3094 {"udi9",     "s,t,d,+1",0x70000019, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3095 {"udi9",      "s,t,+2", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3096 {"udi9",     "s,+3",    0x70000019, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3097 {"udi9",     "+4",      0x70000019, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3098 {"udi10",    "s,t,d,+1",0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3099 {"udi10",    "s,t,+2",  0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3100 {"udi10",    "s,+3",    0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3101 {"udi10",    "+4",      0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3102 {"udi11",    "s,t,d,+1",0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3103 {"udi11",    "s,t,+2",  0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3104 {"udi11",    "s,+3",    0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3105 {"udi11",    "+4",      0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3106 {"udi12",    "s,t,d,+1",0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3107 {"udi12",    "s,t,+2",  0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3108 {"udi12",    "s,+3",    0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3109 {"udi12",    "+4",      0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3110 {"udi13",    "s,t,d,+1",0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3111 {"udi13",    "s,t,+2",  0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3112 {"udi13",    "s,+3",    0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3113 {"udi13",    "+4",      0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3114 {"udi14",    "s,t,d,+1",0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3115 {"udi14",    "s,t,+2",  0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3116 {"udi14",    "s,+3",    0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3117 {"udi14",    "+4",      0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3118 {"udi15",    "s,t,d,+1",0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3119 {"udi15",    "s,t,+2",  0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3120 {"udi15",    "s,+3",    0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3121 {"udi15",    "+4",      0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t,         0,              I33     },
3122
3123 /* Coprocessor 2 move/branch operations overlap with VR5400 .ob format
3124    instructions so they are here for the latters to take precedence.  */
3125 {"bc2f",    "p",        0x49000000, 0xffff0000, CBD|RD_CC,              0,              I1      },
3126 {"bc2f",    "N,p",      0x49000000, 0xffe30000, CBD|RD_CC,              0,              I32     },
3127 {"bc2fl",   "p",        0x49020000, 0xffff0000, CBL|RD_CC,              0,              I2|T3   },
3128 {"bc2fl",   "N,p",      0x49020000, 0xffe30000, CBL|RD_CC,              0,              I32     },
3129 {"bc2t",    "p",        0x49010000, 0xffff0000, CBD|RD_CC,              0,              I1      },
3130 {"bc2t",    "N,p",      0x49010000, 0xffe30000, CBD|RD_CC,              0,              I32     },
3131 {"bc2tl",   "p",        0x49030000, 0xffff0000, CBL|RD_CC,              0,              I2|T3   },
3132 {"bc2tl",   "N,p",      0x49030000, 0xffe30000, CBL|RD_CC,              0,              I32     },
3133 {"cfc2",    "t,G",      0x48400000, 0xffe007ff, LCD|WR_t|RD_C2,         0,              I1      },
3134 {"ctc2",    "t,G",      0x48c00000, 0xffe007ff, COD|RD_t|WR_CC,         0,              I1      },
3135 {"dmfc2",   "t,G",      0x48200000, 0xffe007ff, LCD|WR_t|RD_C2,         0,              I3      },
3136 {"dmfc2",   "t,G,H",    0x48200000, 0xffe007f8, LCD|WR_t|RD_C2,         0,              I64     },
3137 {"dmtc2",   "t,G",      0x48a00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC,   0,              I3      },
3138 {"dmtc2",   "t,G,H",    0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC,   0,              I64     },
3139 {"mfc2",    "t,G",      0x48000000, 0xffe007ff, LCD|WR_t|RD_C2,         0,              I1      },
3140 {"mfc2",    "t,G,H",    0x48000000, 0xffe007f8, LCD|WR_t|RD_C2,         0,              I32     },
3141 {"mfhc2",   "t,G",      0x48600000, 0xffe007ff, LCD|WR_t|RD_C2,         0,              I33     },
3142 {"mfhc2",   "t,G,H",    0x48600000, 0xffe007f8, LCD|WR_t|RD_C2,         0,              I33     },
3143 {"mfhc2",   "t,i",      0x48600000, 0xffe00000, LCD|WR_t|RD_C2,         0,              I33     },
3144 {"mtc2",    "t,G",      0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC,   0,              I1      },
3145 {"mtc2",    "t,G,H",    0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC,   0,              I32     },
3146 {"mthc2",   "t,G",      0x48e00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC,   0,              I33     },
3147 {"mthc2",   "t,G,H",    0x48e00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC,   0,              I33     },
3148 {"mthc2",   "t,i",      0x48e00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC,   0,              I33     },
3149
3150 /* Coprocessor 3 move/branch operations overlap with MIPS IV COP1X
3151    instructions, so they are here for the latters to take precedence.  */
3152 {"bc3f",    "p",        0x4d000000, 0xffff0000, CBD|RD_CC,              0,              I1      },
3153 {"bc3fl",   "p",        0x4d020000, 0xffff0000, CBL|RD_CC,              0,              I2|T3   },
3154 {"bc3t",    "p",        0x4d010000, 0xffff0000, CBD|RD_CC,              0,              I1      },
3155 {"bc3tl",   "p",        0x4d030000, 0xffff0000, CBL|RD_CC,              0,              I2|T3   },
3156 {"cfc3",    "t,G",      0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3,         0,              I1      },
3157 {"ctc3",    "t,G",      0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC,         0,              I1      },
3158 {"dmfc3",   "t,G",      0x4c200000, 0xffe007ff, LCD|WR_t|RD_C3,         0,              I3      },
3159 {"dmtc3",   "t,G",      0x4ca00000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC,   0,              I3      },
3160 {"mfc3",    "t,G",      0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3,         0,              I1      },
3161 {"mfc3",    "t,G,H",    0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3,         0,              I32     },
3162 {"mtc3",    "t,G",      0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC,   0,              I1      },
3163 {"mtc3",    "t,G,H",    0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC,   0,              I32     },
3164
3165 /* No hazard protection on coprocessor instructions--they shouldn't
3166    change the state of the processor and if they do it's up to the
3167    user to put in nops as necessary.  These are at the end so that the
3168    disassembler recognizes more specific versions first.  */
3169 {"c0",      "C",        0x42000000, 0xfe000000, 0,                      0,              I1      },
3170 {"c1",      "C",        0x46000000, 0xfe000000, 0,                      0,              I1      },
3171 {"c2",      "C",        0x4a000000, 0xfe000000, 0,                      0,              I1      },
3172 {"c3",      "C",        0x4e000000, 0xfe000000, 0,                      0,              I1      },
3173 {"cop0",     "C",       0,    (int) M_COP0,     INSN_MACRO,             0,              I1      },
3174 {"cop1",     "C",       0,    (int) M_COP1,     INSN_MACRO,             0,              I1      },
3175 {"cop2",     "C",       0,    (int) M_COP2,     INSN_MACRO,             0,              I1      },
3176 {"cop3",     "C",       0,    (int) M_COP3,     INSN_MACRO,             0,              I1      },
3177   /* Conflicts with the 4650's "mul" instruction.  Nobody's using the
3178      4010 any more, so move this insn out of the way.  If the object
3179      format gave us more info, we could do this right.  */
3180 {"addciu",  "t,r,j",    0x70000000, 0xfc000000, WR_t|RD_s,              0,              L1      },
3181 /* MIPS DSP ASE */
3182 {"absq_s.ph", "d,t",    0x7c000252, 0xffe007ff, WR_d|RD_t,              0,              D32     },
3183 {"absq_s.pw", "d,t",    0x7c000456, 0xffe007ff, WR_d|RD_t,              0,              D64     },
3184 {"absq_s.qh", "d,t",    0x7c000256, 0xffe007ff, WR_d|RD_t,              0,              D64     },
3185 {"absq_s.w", "d,t",     0x7c000452, 0xffe007ff, WR_d|RD_t,              0,              D32     },
3186 {"addq.ph", "d,s,t",    0x7c000290, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3187 {"addq.pw", "d,s,t",    0x7c000494, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3188 {"addq.qh", "d,s,t",    0x7c000294, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3189 {"addq_s.ph", "d,s,t",  0x7c000390, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3190 {"addq_s.pw", "d,s,t",  0x7c000594, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3191 {"addq_s.qh", "d,s,t",  0x7c000394, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3192 {"addq_s.w", "d,s,t",   0x7c000590, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3193 {"addsc",   "d,s,t",    0x7c000410, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3194 {"addu.ob", "d,s,t",    0x7c000014, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3195 {"addu.qb", "d,s,t",    0x7c000010, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3196 {"addu_s.ob", "d,s,t",  0x7c000114, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3197 {"addu_s.qb", "d,s,t",  0x7c000110, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3198 {"addwc",   "d,s,t",    0x7c000450, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3199 {"bitrev",  "d,t",      0x7c0006d2, 0xffe007ff, WR_d|RD_t,              0,              D32     },
3200 {"bposge32", "p",       0x041c0000, 0xffff0000, CBD,                    0,              D32     },
3201 {"bposge64", "p",       0x041d0000, 0xffff0000, CBD,                    0,              D64     },
3202 {"cmp.eq.ph", "s,t",    0x7c000211, 0xfc00ffff, RD_s|RD_t,              0,              D32     },
3203 {"cmp.eq.pw", "s,t",    0x7c000415, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
3204 {"cmp.eq.qh", "s,t",    0x7c000215, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
3205 {"cmpgu.eq.ob", "d,s,t", 0x7c000115, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              D64     },
3206 {"cmpgu.eq.qb", "d,s,t", 0x7c000111, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              D32     },
3207 {"cmpgu.le.ob", "d,s,t", 0x7c000195, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              D64     },
3208 {"cmpgu.le.qb", "d,s,t", 0x7c000191, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              D32     },
3209 {"cmpgu.lt.ob", "d,s,t", 0x7c000155, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              D64     },
3210 {"cmpgu.lt.qb", "d,s,t", 0x7c000151, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              D32     },
3211 {"cmp.le.ph", "s,t",    0x7c000291, 0xfc00ffff, RD_s|RD_t,              0,              D32     },
3212 {"cmp.le.pw", "s,t",    0x7c000495, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
3213 {"cmp.le.qh", "s,t",    0x7c000295, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
3214 {"cmp.lt.ph", "s,t",    0x7c000251, 0xfc00ffff, RD_s|RD_t,              0,              D32     },
3215 {"cmp.lt.pw", "s,t",    0x7c000455, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
3216 {"cmp.lt.qh", "s,t",    0x7c000255, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
3217 {"cmpu.eq.ob", "s,t",   0x7c000015, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
3218 {"cmpu.eq.qb", "s,t",   0x7c000011, 0xfc00ffff, RD_s|RD_t,              0,              D32     },
3219 {"cmpu.le.ob", "s,t",   0x7c000095, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
3220 {"cmpu.le.qb", "s,t",   0x7c000091, 0xfc00ffff, RD_s|RD_t,              0,              D32     },
3221 {"cmpu.lt.ob", "s,t",   0x7c000055, 0xfc00ffff, RD_s|RD_t,              0,              D64     },
3222 {"cmpu.lt.qb", "s,t",   0x7c000051, 0xfc00ffff, RD_s|RD_t,              0,              D32     },
3223 {"dextpdp", "t,7,6",    0x7c0002bc, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA,     0,              D64     },
3224 {"dextpdpv", "t,7,s",   0x7c0002fc, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, 0,             D64     },
3225 {"dextp",   "t,7,6",    0x7c0000bc, 0xfc00e7ff, WR_t|RD_a,              0,              D64     },
3226 {"dextpv",  "t,7,s",    0x7c0000fc, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D64     },
3227 {"dextr.l", "t,7,6",    0x7c00043c, 0xfc00e7ff, WR_t|RD_a,              0,              D64     },
3228 {"dextr_r.l", "t,7,6",  0x7c00053c, 0xfc00e7ff, WR_t|RD_a,              0,              D64     },
3229 {"dextr_rs.l", "t,7,6", 0x7c0005bc, 0xfc00e7ff, WR_t|RD_a,              0,              D64     },
3230 {"dextr_rs.w", "t,7,6", 0x7c0001bc, 0xfc00e7ff, WR_t|RD_a,              0,              D64     },
3231 {"dextr_r.w", "t,7,6",  0x7c00013c, 0xfc00e7ff, WR_t|RD_a,              0,              D64     },
3232 {"dextr_s.h", "t,7,6",  0x7c0003bc, 0xfc00e7ff, WR_t|RD_a,              0,              D64     },
3233 {"dextrv.l", "t,7,s",   0x7c00047c, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D64     },
3234 {"dextrv_r.l", "t,7,s", 0x7c00057c, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D64     },
3235 {"dextrv_rs.l", "t,7,s", 0x7c0005fc, 0xfc00e7ff, WR_t|RD_a|RD_s,        0,              D64     },
3236 {"dextrv_rs.w", "t,7,s", 0x7c0001fc, 0xfc00e7ff, WR_t|RD_a|RD_s,        0,              D64     },
3237 {"dextrv_r.w", "t,7,s", 0x7c00017c, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D64     },
3238 {"dextrv_s.h", "t,7,s", 0x7c0003fc, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D64     },
3239 {"dextrv.w", "t,7,s",   0x7c00007c, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D64     },
3240 {"dextr.w", "t,7,6",    0x7c00003c, 0xfc00e7ff, WR_t|RD_a,              0,              D64     },
3241 {"dinsv",   "t,s",      0x7c00000d, 0xfc00ffff, WR_t|RD_s,              0,              D64     },
3242 {"dmadd",   "7,s,t",    0x7c000674, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D64     },
3243 {"dmaddu",  "7,s,t",    0x7c000774, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D64     },
3244 {"dmsub",   "7,s,t",    0x7c0006f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D64     },
3245 {"dmsubu",  "7,s,t",    0x7c0007f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D64     },
3246 {"dmthlip", "s,7",      0x7c0007fc, 0xfc1fe7ff, RD_s|MOD_a|DSP_VOLA,    0,              D64     },
3247 {"dpaq_sa.l.pw", "7,s,t", 0x7c000334, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D64     },
3248 {"dpaq_sa.l.w", "7,s,t", 0x7c000330, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,              D32     },
3249 {"dpaq_s.w.ph", "7,s,t", 0x7c000130, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,              D32     },
3250 {"dpaq_s.w.qh", "7,s,t", 0x7c000134, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,              D64     },
3251 {"dpau.h.obl", "7,s,t", 0x7c0000f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D64     },
3252 {"dpau.h.obr", "7,s,t", 0x7c0001f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D64     },
3253 {"dpau.h.qbl", "7,s,t", 0x7c0000f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D32     },
3254 {"dpau.h.qbr", "7,s,t", 0x7c0001f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D32     },
3255 {"dpsq_sa.l.pw", "7,s,t", 0x7c000374, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D64     },
3256 {"dpsq_sa.l.w", "7,s,t", 0x7c000370, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,              D32     },
3257 {"dpsq_s.w.ph", "7,s,t", 0x7c000170, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,              D32     },
3258 {"dpsq_s.w.qh", "7,s,t", 0x7c000174, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,              D64     },
3259 {"dpsu.h.obl", "7,s,t", 0x7c0002f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D64     },
3260 {"dpsu.h.obr", "7,s,t", 0x7c0003f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D64     },
3261 {"dpsu.h.qbl", "7,s,t", 0x7c0002f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D32     },
3262 {"dpsu.h.qbr", "7,s,t", 0x7c0003f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D32     },
3263 {"dshilo",  "7,:",      0x7c0006bc, 0xfc07e7ff, MOD_a,                  0,              D64     },
3264 {"dshilov", "7,s",      0x7c0006fc, 0xfc1fe7ff, MOD_a|RD_s,             0,              D64     },
3265 {"extpdp",  "t,7,6",    0x7c0002b8, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA,     0,              D32     },
3266 {"extpdpv", "t,7,s",    0x7c0002f8, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, 0,             D32     },
3267 {"extp",    "t,7,6",    0x7c0000b8, 0xfc00e7ff, WR_t|RD_a,              0,              D32     },
3268 {"extpv",   "t,7,s",    0x7c0000f8, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D32     },
3269 {"extr_rs.w", "t,7,6",  0x7c0001b8, 0xfc00e7ff, WR_t|RD_a,              0,              D32     },
3270 {"extr_r.w", "t,7,6",   0x7c000138, 0xfc00e7ff, WR_t|RD_a,              0,              D32     },
3271 {"extr_s.h", "t,7,6",   0x7c0003b8, 0xfc00e7ff, WR_t|RD_a,              0,              D32     },
3272 {"extrv_rs.w", "t,7,s", 0x7c0001f8, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D32     },
3273 {"extrv_r.w", "t,7,s",  0x7c000178, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D32     },
3274 {"extrv_s.h", "t,7,s",  0x7c0003f8, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D32     },
3275 {"extrv.w", "t,7,s",    0x7c000078, 0xfc00e7ff, WR_t|RD_a|RD_s,         0,              D32     },
3276 {"extr.w",  "t,7,6",    0x7c000038, 0xfc00e7ff, WR_t|RD_a,              0,              D32     },
3277 {"insv",    "t,s",      0x7c00000c, 0xfc00ffff, WR_t|RD_s,              0,              D32     },
3278 {"lbux",    "d,t(b)",   0x7c00018a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b,     0,              D32     },
3279 {"ldx",     "d,t(b)",   0x7c00020a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b,     0,              D64     },
3280 {"lhx",     "d,t(b)",   0x7c00010a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b,     0,              D32     },
3281 {"lwx",     "d,t(b)",   0x7c00000a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b,     0,              D32     },
3282 {"maq_sa.w.phl", "7,s,t", 0x7c000430, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D32     },
3283 {"maq_sa.w.phr", "7,s,t", 0x7c0004b0, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D32     },
3284 {"maq_sa.w.qhll", "7,s,t", 0x7c000434, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D64     },
3285 {"maq_sa.w.qhlr", "7,s,t", 0x7c000474, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D64     },
3286 {"maq_sa.w.qhrl", "7,s,t", 0x7c0004b4, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D64     },
3287 {"maq_sa.w.qhrr", "7,s,t", 0x7c0004f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D64     },
3288 {"maq_s.l.pwl", "7,s,t", 0x7c000734, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,              D64     },
3289 {"maq_s.l.pwr", "7,s,t", 0x7c0007b4, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,              D64     },
3290 {"maq_s.w.phl", "7,s,t", 0x7c000530, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,              D32     },
3291 {"maq_s.w.phr", "7,s,t", 0x7c0005b0, 0xfc00e7ff, MOD_a|RD_s|RD_t,       0,              D32     },
3292 {"maq_s.w.qhll", "7,s,t", 0x7c000534, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D64     },
3293 {"maq_s.w.qhlr", "7,s,t", 0x7c000574, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D64     },
3294 {"maq_s.w.qhrl", "7,s,t", 0x7c0005b4, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D64     },
3295 {"maq_s.w.qhrr", "7,s,t", 0x7c0005f4, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D64     },
3296 {"modsub",  "d,s,t",    0x7c000490, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3297 {"mthlip",  "s,7",      0x7c0007f8, 0xfc1fe7ff, RD_s|MOD_a|DSP_VOLA,    0,              D32     },
3298 {"muleq_s.pw.qhl", "d,s,t", 0x7c000714, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,          D64     },
3299 {"muleq_s.pw.qhr", "d,s,t", 0x7c000754, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,          D64     },
3300 {"muleq_s.w.phl", "d,s,t", 0x7c000710, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,           D32     },
3301 {"muleq_s.w.phr", "d,s,t", 0x7c000750, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,           D32     },
3302 {"muleu_s.ph.qbl", "d,s,t", 0x7c000190, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,          D32     },
3303 {"muleu_s.ph.qbr", "d,s,t", 0x7c0001d0, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,          D32     },
3304 {"muleu_s.qh.obl", "d,s,t", 0x7c000194, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,          D64     },
3305 {"muleu_s.qh.obr", "d,s,t", 0x7c0001d4, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,          D64     },
3306 {"mulq_rs.ph", "d,s,t", 0x7c0007d0, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D32     },
3307 {"mulq_rs.qh", "d,s,t", 0x7c0007d4, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D64     },
3308 {"mulsaq_s.l.pw", "7,s,t", 0x7c0003b4, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D64     },
3309 {"mulsaq_s.w.ph", "7,s,t", 0x7c0001b0, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D32     },
3310 {"mulsaq_s.w.qh", "7,s,t", 0x7c0001b4, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D64     },
3311 {"packrl.ph", "d,s,t",  0x7c000391, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3312 {"packrl.pw", "d,s,t",  0x7c000395, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3313 {"pick.ob", "d,s,t",    0x7c0000d5, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3314 {"pick.ph", "d,s,t",    0x7c0002d1, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3315 {"pick.pw", "d,s,t",    0x7c0004d5, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3316 {"pick.qb", "d,s,t",    0x7c0000d1, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3317 {"pick.qh", "d,s,t",    0x7c0002d5, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3318 {"preceq.pw.qhla", "d,t", 0x7c000396, 0xffe007ff, WR_d|RD_t,            0,              D64     },
3319 {"preceq.pw.qhl", "d,t", 0x7c000316, 0xffe007ff, WR_d|RD_t,             0,              D64     },
3320 {"preceq.pw.qhra", "d,t", 0x7c0003d6, 0xffe007ff, WR_d|RD_t,            0,              D64     },
3321 {"preceq.pw.qhr", "d,t", 0x7c000356, 0xffe007ff, WR_d|RD_t,             0,              D64     },
3322 {"preceq.s.l.pwl", "d,t", 0x7c000516, 0xffe007ff, WR_d|RD_t,            0,              D64     },
3323 {"preceq.s.l.pwr", "d,t", 0x7c000556, 0xffe007ff, WR_d|RD_t,            0,              D64     },
3324 {"precequ.ph.qbla", "d,t", 0x7c000192, 0xffe007ff, WR_d|RD_t,           0,              D32     },
3325 {"precequ.ph.qbl", "d,t", 0x7c000112, 0xffe007ff, WR_d|RD_t,            0,              D32     },
3326 {"precequ.ph.qbra", "d,t", 0x7c0001d2, 0xffe007ff, WR_d|RD_t,           0,              D32     },
3327 {"precequ.ph.qbr", "d,t", 0x7c000152, 0xffe007ff, WR_d|RD_t,            0,              D32     },
3328 {"precequ.pw.qhla", "d,t", 0x7c000196, 0xffe007ff, WR_d|RD_t,           0,              D64     },
3329 {"precequ.pw.qhl", "d,t", 0x7c000116, 0xffe007ff, WR_d|RD_t,            0,              D64     },
3330 {"precequ.pw.qhra", "d,t", 0x7c0001d6, 0xffe007ff, WR_d|RD_t,           0,              D64     },
3331 {"precequ.pw.qhr", "d,t", 0x7c000156, 0xffe007ff, WR_d|RD_t,            0,              D64     },
3332 {"preceq.w.phl", "d,t", 0x7c000312, 0xffe007ff, WR_d|RD_t,              0,              D32     },
3333 {"preceq.w.phr", "d,t", 0x7c000352, 0xffe007ff, WR_d|RD_t,              0,              D32     },
3334 {"preceu.ph.qbla", "d,t", 0x7c000792, 0xffe007ff, WR_d|RD_t,            0,              D32     },
3335 {"preceu.ph.qbl", "d,t", 0x7c000712, 0xffe007ff, WR_d|RD_t,             0,              D32     },
3336 {"preceu.ph.qbra", "d,t", 0x7c0007d2, 0xffe007ff, WR_d|RD_t,            0,              D32     },
3337 {"preceu.ph.qbr", "d,t", 0x7c000752, 0xffe007ff, WR_d|RD_t,             0,              D32     },
3338 {"preceu.qh.obla", "d,t", 0x7c000796, 0xffe007ff, WR_d|RD_t,            0,              D64     },
3339 {"preceu.qh.obl", "d,t", 0x7c000716, 0xffe007ff, WR_d|RD_t,             0,              D64     },
3340 {"preceu.qh.obra", "d,t", 0x7c0007d6, 0xffe007ff, WR_d|RD_t,            0,              D64     },
3341 {"preceu.qh.obr", "d,t", 0x7c000756, 0xffe007ff, WR_d|RD_t,             0,              D64     },
3342 {"precrq.ob.qh", "d,s,t", 0x7c000315, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              D64     },
3343 {"precrq.ph.w", "d,s,t", 0x7c000511, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              D32     },
3344 {"precrq.pw.l", "d,s,t", 0x7c000715, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              D64     },
3345 {"precrq.qb.ph", "d,s,t", 0x7c000311, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              D32     },
3346 {"precrq.qh.pw", "d,s,t", 0x7c000515, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              D64     },
3347 {"precrq_rs.ph.w", "d,s,t", 0x7c000551, 0xfc0007ff, WR_d|RD_s|RD_t,     0,              D32     },
3348 {"precrq_rs.qh.pw", "d,s,t", 0x7c000555, 0xfc0007ff, WR_d|RD_s|RD_t,    0,              D64     },
3349 {"precrqu_s.ob.qh", "d,s,t", 0x7c0003d5, 0xfc0007ff, WR_d|RD_s|RD_t,    0,              D64     },
3350 {"precrqu_s.qb.ph", "d,s,t", 0x7c0003d1, 0xfc0007ff, WR_d|RD_s|RD_t,    0,              D32     },
3351 {"raddu.l.ob", "d,s",   0x7c000514, 0xfc1f07ff, WR_d|RD_s,              0,              D64     },
3352 {"raddu.w.qb", "d,s",   0x7c000510, 0xfc1f07ff, WR_d|RD_s,              0,              D32     },
3353 {"rddsp",   "d",        0x7fff04b8, 0xffff07ff, WR_d,                   0,              D32     },
3354 {"rddsp",   "d,'",      0x7c0004b8, 0xffc007ff, WR_d,                   0,              D32     },
3355 {"repl.ob", "d,5",      0x7c000096, 0xff0007ff, WR_d,                   0,              D64     },
3356 {"repl.ph", "d,@",      0x7c000292, 0xfc0007ff, WR_d,                   0,              D32     },
3357 {"repl.pw", "d,@",      0x7c000496, 0xfc0007ff, WR_d,                   0,              D64     },
3358 {"repl.qb", "d,5",      0x7c000092, 0xff0007ff, WR_d,                   0,              D32     },
3359 {"repl.qh", "d,@",      0x7c000296, 0xfc0007ff, WR_d,                   0,              D64     },
3360 {"replv.ob", "d,t",     0x7c0000d6, 0xffe007ff, WR_d|RD_t,              0,              D64     },
3361 {"replv.ph", "d,t",     0x7c0002d2, 0xffe007ff, WR_d|RD_t,              0,              D32     },
3362 {"replv.pw", "d,t",     0x7c0004d6, 0xffe007ff, WR_d|RD_t,              0,              D64     },
3363 {"replv.qb", "d,t",     0x7c0000d2, 0xffe007ff, WR_d|RD_t,              0,              D32     },
3364 {"replv.qh", "d,t",     0x7c0002d6, 0xffe007ff, WR_d|RD_t,              0,              D64     },
3365 {"shilo",   "7,0",      0x7c0006b8, 0xfc0fe7ff, MOD_a,                  0,              D32     },
3366 {"shilov",  "7,s",      0x7c0006f8, 0xfc1fe7ff, MOD_a|RD_s,             0,              D32     },
3367 {"shll.ob", "d,t,3",    0x7c000017, 0xff0007ff, WR_d|RD_t,              0,              D64     },
3368 {"shll.ph", "d,t,4",    0x7c000213, 0xfe0007ff, WR_d|RD_t,              0,              D32     },
3369 {"shll.pw", "d,t,6",    0x7c000417, 0xfc0007ff, WR_d|RD_t,              0,              D64     },
3370 {"shll.qb", "d,t,3",    0x7c000013, 0xff0007ff, WR_d|RD_t,              0,              D32     },
3371 {"shll.qh", "d,t,4",    0x7c000217, 0xfe0007ff, WR_d|RD_t,              0,              D64     },
3372 {"shll_s.ph", "d,t,4",  0x7c000313, 0xfe0007ff, WR_d|RD_t,              0,              D32     },
3373 {"shll_s.pw", "d,t,6",  0x7c000517, 0xfc0007ff, WR_d|RD_t,              0,              D64     },
3374 {"shll_s.qh", "d,t,4",  0x7c000317, 0xfe0007ff, WR_d|RD_t,              0,              D64     },
3375 {"shll_s.w", "d,t,6",   0x7c000513, 0xfc0007ff, WR_d|RD_t,              0,              D32     },
3376 {"shllv.ob", "d,t,s",   0x7c000097, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3377 {"shllv.ph", "d,t,s",   0x7c000293, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3378 {"shllv.pw", "d,t,s",   0x7c000497, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3379 {"shllv.qb", "d,t,s",   0x7c000093, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3380 {"shllv.qh", "d,t,s",   0x7c000297, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3381 {"shllv_s.ph", "d,t,s", 0x7c000393, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3382 {"shllv_s.pw", "d,t,s", 0x7c000597, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3383 {"shllv_s.qh", "d,t,s", 0x7c000397, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3384 {"shllv_s.w", "d,t,s",  0x7c000593, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3385 {"shra.ph", "d,t,4",    0x7c000253, 0xfe0007ff, WR_d|RD_t,              0,              D32     },
3386 {"shra.pw", "d,t,6",    0x7c000457, 0xfc0007ff, WR_d|RD_t,              0,              D64     },
3387 {"shra.qh", "d,t,4",    0x7c000257, 0xfe0007ff, WR_d|RD_t,              0,              D64     },
3388 {"shra_r.ph", "d,t,4",  0x7c000353, 0xfe0007ff, WR_d|RD_t,              0,              D32     },
3389 {"shra_r.pw", "d,t,6",  0x7c000557, 0xfc0007ff, WR_d|RD_t,              0,              D64     },
3390 {"shra_r.qh", "d,t,4",  0x7c000357, 0xfe0007ff, WR_d|RD_t,              0,              D64     },
3391 {"shra_r.w", "d,t,6",   0x7c000553, 0xfc0007ff, WR_d|RD_t,              0,              D32     },
3392 {"shrav.ph", "d,t,s",   0x7c0002d3, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3393 {"shrav.pw", "d,t,s",   0x7c0004d7, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3394 {"shrav.qh", "d,t,s",   0x7c0002d7, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3395 {"shrav_r.ph", "d,t,s", 0x7c0003d3, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3396 {"shrav_r.pw", "d,t,s", 0x7c0005d7, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3397 {"shrav_r.qh", "d,t,s", 0x7c0003d7, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3398 {"shrav_r.w", "d,t,s",  0x7c0005d3, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3399 {"shrl.ob", "d,t,3",    0x7c000057, 0xff0007ff, WR_d|RD_t,              0,              D64     },
3400 {"shrl.qb", "d,t,3",    0x7c000053, 0xff0007ff, WR_d|RD_t,              0,              D32     },
3401 {"shrlv.ob", "d,t,s",   0x7c0000d7, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3402 {"shrlv.qb", "d,t,s",   0x7c0000d3, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3403 {"subq.ph", "d,s,t",    0x7c0002d0, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3404 {"subq.pw", "d,s,t",    0x7c0004d4, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3405 {"subq.qh", "d,s,t",    0x7c0002d4, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3406 {"subq_s.ph", "d,s,t",  0x7c0003d0, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3407 {"subq_s.pw", "d,s,t",  0x7c0005d4, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3408 {"subq_s.qh", "d,s,t",  0x7c0003d4, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3409 {"subq_s.w", "d,s,t",   0x7c0005d0, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3410 {"subu.ob", "d,s,t",    0x7c000054, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3411 {"subu.qb", "d,s,t",    0x7c000050, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3412 {"subu_s.ob", "d,s,t",  0x7c000154, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D64     },
3413 {"subu_s.qb", "d,s,t",  0x7c000150, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D32     },
3414 {"wrdsp",   "s",        0x7c1ffcf8, 0xfc1fffff, RD_s|DSP_VOLA,          0,              D32     },
3415 {"wrdsp",   "s,8",      0x7c0004f8, 0xfc1e07ff, RD_s|DSP_VOLA,          0,              D32     },
3416 /* MIPS DSP ASE Rev2 */
3417 {"absq_s.qb", "d,t",    0x7c000052, 0xffe007ff, WR_d|RD_t,              0,              D33     },
3418 {"addu.ph", "d,s,t",    0x7c000210, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
3419 {"addu_s.ph", "d,s,t",  0x7c000310, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
3420 {"adduh.qb", "d,s,t",   0x7c000018, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
3421 {"adduh_r.qb", "d,s,t", 0x7c000098, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
3422 {"append",  "t,s,h",    0x7c000031, 0xfc0007ff, WR_t|RD_t|RD_s,         0,              D33     },
3423 {"balign",  "t,s,I",    0,    (int) M_BALIGN,   INSN_MACRO,             0,              D33     },
3424 {"balign",  "t,s,2",    0x7c000431, 0xfc00e7ff, WR_t|RD_t|RD_s,         0,              D33     },
3425 {"cmpgdu.eq.qb", "d,s,t", 0x7c000611, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              D33     },
3426 {"cmpgdu.lt.qb", "d,s,t", 0x7c000651, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              D33     },
3427 {"cmpgdu.le.qb", "d,s,t", 0x7c000691, 0xfc0007ff, WR_d|RD_s|RD_t,       0,              D33     },
3428 {"dpa.w.ph", "7,s,t",   0x7c000030, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33     },
3429 {"dps.w.ph", "7,s,t",   0x7c000070, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33     },
3430 {"mul.ph",  "d,s,t",    0x7c000318, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D33     },
3431 {"mul_s.ph", "d,s,t",   0x7c000398, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D33     },
3432 {"mulq_rs.w", "d,s,t",  0x7c0005d8, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D33     },
3433 {"mulq_s.ph", "d,s,t",  0x7c000790, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D33     },
3434 {"mulq_s.w", "d,s,t",   0x7c000598, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,              D33     },
3435 {"mulsa.w.ph", "7,s,t", 0x7c0000b0, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33     },
3436 {"precr.qb.ph", "d,s,t", 0x7c000351, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              D33     },
3437 {"precr_sra.ph.w", "t,s,h", 0x7c000791, 0xfc0007ff, WR_t|RD_t|RD_s,     0,              D33     },
3438 {"precr_sra_r.ph.w", "t,s,h", 0x7c0007d1, 0xfc0007ff, WR_t|RD_t|RD_s,   0,              D33     },
3439 {"prepend", "t,s,h",    0x7c000071, 0xfc0007ff, WR_t|RD_t|RD_s,         0,              D33     },
3440 {"shra.qb", "d,t,3",    0x7c000113, 0xff0007ff, WR_d|RD_t,              0,              D33     },
3441 {"shra_r.qb", "d,t,3",  0x7c000153, 0xff0007ff, WR_d|RD_t,              0,              D33     },
3442 {"shrav.qb", "d,t,s",   0x7c000193, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
3443 {"shrav_r.qb", "d,t,s", 0x7c0001d3, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
3444 {"shrl.ph", "d,t,4",    0x7c000653, 0xfe0007ff, WR_d|RD_t,              0,              D33     },
3445 {"shrlv.ph", "d,t,s",   0x7c0006d3, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
3446 {"subu.ph", "d,s,t",    0x7c000250, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
3447 {"subu_s.ph", "d,s,t",  0x7c000350, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
3448 {"subuh.qb", "d,s,t",   0x7c000058, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
3449 {"subuh_r.qb", "d,s,t", 0x7c0000d8, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
3450 {"addqh.ph", "d,s,t",   0x7c000218, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
3451 {"addqh_r.ph", "d,s,t", 0x7c000298, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
3452 {"addqh.w", "d,s,t",    0x7c000418, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
3453 {"addqh_r.w", "d,s,t",  0x7c000498, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
3454 {"subqh.ph", "d,s,t",   0x7c000258, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
3455 {"subqh_r.ph", "d,s,t", 0x7c0002d8, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
3456 {"subqh.w", "d,s,t",    0x7c000458, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
3457 {"subqh_r.w", "d,s,t",  0x7c0004d8, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              D33     },
3458 {"dpax.w.ph", "7,s,t",  0x7c000230, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33     },
3459 {"dpsx.w.ph", "7,s,t",  0x7c000270, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33     },
3460 {"dpaqx_s.w.ph", "7,s,t", 0x7c000630, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D33     },
3461 {"dpaqx_sa.w.ph", "7,s,t", 0x7c0006b0, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D33     },
3462 {"dpsqx_s.w.ph", "7,s,t", 0x7c000670, 0xfc00e7ff, MOD_a|RD_s|RD_t,      0,              D33     },
3463 {"dpsqx_sa.w.ph", "7,s,t", 0x7c0006f0, 0xfc00e7ff, MOD_a|RD_s|RD_t,     0,              D33     },
3464 /* Move bc0* after mftr and mttr to avoid opcode collision.  */
3465 {"bc0f",    "p",        0x41000000, 0xffff0000, CBD|RD_CC,              0,              I1      },
3466 {"bc0fl",   "p",        0x41020000, 0xffff0000, CBL|RD_CC,              0,              I2|T3   },
3467 {"bc0t",    "p",        0x41010000, 0xffff0000, CBD|RD_CC,              0,              I1      },
3468 {"bc0tl",   "p",        0x41030000, 0xffff0000, CBL|RD_CC,              0,              I2|T3   },
3469 /* ST Microelectronics Loongson-2E and -2F.  */
3470 {"mult.g",      "d,s,t",        0x7c000018,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
3471 {"mult.g",      "d,s,t",        0x70000010,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
3472 {"multu.g",     "d,s,t",        0x7c000019,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
3473 {"multu.g",     "d,s,t",        0x70000012,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
3474 {"dmult.g",     "d,s,t",        0x7c00001c,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
3475 {"dmult.g",     "d,s,t",        0x70000011,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
3476 {"dmultu.g",    "d,s,t",        0x7c00001d,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
3477 {"dmultu.g",    "d,s,t",        0x70000013,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
3478 {"div.g",       "d,s,t",        0x7c00001a,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
3479 {"div.g",       "d,s,t",        0x70000014,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
3480 {"divu.g",      "d,s,t",        0x7c00001b,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
3481 {"divu.g",      "d,s,t",        0x70000016,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
3482 {"ddiv.g",      "d,s,t",        0x7c00001e,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
3483 {"ddiv.g",      "d,s,t",        0x70000015,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
3484 {"ddivu.g",     "d,s,t",        0x7c00001f,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
3485 {"ddivu.g",     "d,s,t",        0x70000017,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
3486 {"mod.g",       "d,s,t",        0x7c000022,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
3487 {"mod.g",       "d,s,t",        0x7000001c,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
3488 {"modu.g",      "d,s,t",        0x7c000023,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
3489 {"modu.g",      "d,s,t",        0x7000001e,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
3490 {"dmod.g",      "d,s,t",        0x7c000026,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
3491 {"dmod.g",      "d,s,t",        0x7000001d,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
3492 {"dmodu.g",     "d,s,t",        0x7c000027,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
3493 {"dmodu.g",     "d,s,t",        0x7000001f,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
3494 };
3495
3496 #define MIPS_NUM_OPCODES \
3497         ((sizeof mips_builtin_opcodes) / (sizeof (mips_builtin_opcodes[0])))
3498 const int bfd_mips_num_builtin_opcodes = MIPS_NUM_OPCODES;
3499
3500 /* const removed from the following to allow for dynamic extensions to the
3501  * built-in instruction set. */
3502 struct mips_opcode *mips_opcodes =
3503   (struct mips_opcode *) mips_builtin_opcodes;
3504 int bfd_mips_num_opcodes = MIPS_NUM_OPCODES;
3505 #undef MIPS_NUM_OPCODES
3506
3507 /* Mips instructions are at maximum this many bytes long.  */
3508 #define INSNLEN 4
3509
3510 \f
3511 /* FIXME: These should be shared with gdb somehow.  */
3512
3513 struct mips_cp0sel_name
3514 {
3515   unsigned int cp0reg;
3516   unsigned int sel;
3517   const char * const name;
3518 };
3519
3520 #if 0
3521 /* The mips16 registers.  */
3522 static const unsigned int mips16_to_32_reg_map[] =
3523 {
3524   16, 17, 2, 3, 4, 5, 6, 7
3525 };
3526
3527 #define mips16_reg_names(rn)    mips_gpr_names[mips16_to_32_reg_map[rn]]
3528 #endif
3529
3530 static const char * const mips_gpr_names_numeric[32] =
3531 {
3532   "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
3533   "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
3534   "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
3535   "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31"
3536 };
3537
3538 static const char * const mips_gpr_names_oldabi[32] =
3539 {
3540   "zero", "at",   "v0",   "v1",   "a0",   "a1",   "a2",   "a3",
3541   "t0",   "t1",   "t2",   "t3",   "t4",   "t5",   "t6",   "t7",
3542   "s0",   "s1",   "s2",   "s3",   "s4",   "s5",   "s6",   "s7",
3543   "t8",   "t9",   "k0",   "k1",   "gp",   "sp",   "s8",   "ra"
3544 };
3545
3546 static const char * const mips_gpr_names_newabi[32] =
3547 {
3548   "zero", "at",   "v0",   "v1",   "a0",   "a1",   "a2",   "a3",
3549   "a4",   "a5",   "a6",   "a7",   "t0",   "t1",   "t2",   "t3",
3550   "s0",   "s1",   "s2",   "s3",   "s4",   "s5",   "s6",   "s7",
3551   "t8",   "t9",   "k0",   "k1",   "gp",   "sp",   "s8",   "ra"
3552 };
3553
3554 static const char * const mips_fpr_names_numeric[32] =
3555 {
3556   "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",
3557   "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
3558   "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
3559   "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31"
3560 };
3561
3562 static const char * const mips_fpr_names_32[32] =
3563 {
3564   "fv0",  "fv0f", "fv1",  "fv1f", "ft0",  "ft0f", "ft1",  "ft1f",
3565   "ft2",  "ft2f", "ft3",  "ft3f", "fa0",  "fa0f", "fa1",  "fa1f",
3566   "ft4",  "ft4f", "ft5",  "ft5f", "fs0",  "fs0f", "fs1",  "fs1f",
3567   "fs2",  "fs2f", "fs3",  "fs3f", "fs4",  "fs4f", "fs5",  "fs5f"
3568 };
3569
3570 static const char * const mips_fpr_names_n32[32] =
3571 {
3572   "fv0",  "ft14", "fv1",  "ft15", "ft0",  "ft1",  "ft2",  "ft3",
3573   "ft4",  "ft5",  "ft6",  "ft7",  "fa0",  "fa1",  "fa2",  "fa3",
3574   "fa4",  "fa5",  "fa6",  "fa7",  "fs0",  "ft8",  "fs1",  "ft9",
3575   "fs2",  "ft10", "fs3",  "ft11", "fs4",  "ft12", "fs5",  "ft13"
3576 };
3577
3578 static const char * const mips_fpr_names_64[32] =
3579 {
3580   "fv0",  "ft12", "fv1",  "ft13", "ft0",  "ft1",  "ft2",  "ft3",
3581   "ft4",  "ft5",  "ft6",  "ft7",  "fa0",  "fa1",  "fa2",  "fa3",
3582   "fa4",  "fa5",  "fa6",  "fa7",  "ft8",  "ft9",  "ft10", "ft11",
3583   "fs0",  "fs1",  "fs2",  "fs3",  "fs4",  "fs5",  "fs6",  "fs7"
3584 };
3585
3586 static const char * const mips_wr_names[32] = {
3587   "w0",  "w1",  "w2",  "w3",  "w4",  "w5",  "w6",  "w7",
3588   "w8",  "w9",  "w10", "w11", "w12", "w13", "w14", "w15",
3589   "w16", "w17", "w18", "w19", "w20", "w21", "w22", "w23",
3590   "w24", "w25", "w26", "w27", "w28", "w29", "w30", "w31"
3591 };
3592
3593 static const char * const mips_cp0_names_numeric[32] =
3594 {
3595   "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
3596   "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
3597   "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
3598   "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31"
3599 };
3600
3601 static const char * const mips_cp0_names_mips3264[32] =
3602 {
3603   "c0_index",     "c0_random",    "c0_entrylo0",  "c0_entrylo1",
3604   "c0_context",   "c0_pagemask",  "c0_wired",     "$7",
3605   "c0_badvaddr",  "c0_count",     "c0_entryhi",   "c0_compare",
3606   "c0_status",    "c0_cause",     "c0_epc",       "c0_prid",
3607   "c0_config",    "c0_lladdr",    "c0_watchlo",   "c0_watchhi",
3608   "c0_xcontext",  "$21",          "$22",          "c0_debug",
3609   "c0_depc",      "c0_perfcnt",   "c0_errctl",    "c0_cacheerr",
3610   "c0_taglo",     "c0_taghi",     "c0_errorepc",  "c0_desave",
3611 };
3612
3613 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] =
3614 {
3615   {  4, 1, "c0_contextconfig"   },
3616   {  0, 1, "c0_mvpcontrol"      },
3617   {  0, 2, "c0_mvpconf0"        },
3618   {  0, 3, "c0_mvpconf1"        },
3619   {  1, 1, "c0_vpecontrol"      },
3620   {  1, 2, "c0_vpeconf0"        },
3621   {  1, 3, "c0_vpeconf1"        },
3622   {  1, 4, "c0_yqmask"          },
3623   {  1, 5, "c0_vpeschedule"     },
3624   {  1, 6, "c0_vpeschefback"    },
3625   {  2, 1, "c0_tcstatus"        },
3626   {  2, 2, "c0_tcbind"          },
3627   {  2, 3, "c0_tcrestart"       },
3628   {  2, 4, "c0_tchalt"          },
3629   {  2, 5, "c0_tccontext"       },
3630   {  2, 6, "c0_tcschedule"      },
3631   {  2, 7, "c0_tcschefback"     },
3632   {  5, 1, "c0_pagegrain"       },
3633   {  6, 1, "c0_srsconf0"        },
3634   {  6, 2, "c0_srsconf1"        },
3635   {  6, 3, "c0_srsconf2"        },
3636   {  6, 4, "c0_srsconf3"        },
3637   {  6, 5, "c0_srsconf4"        },
3638   { 12, 1, "c0_intctl"          },
3639   { 12, 2, "c0_srsctl"          },
3640   { 12, 3, "c0_srsmap"          },
3641   { 15, 1, "c0_ebase"           },
3642   { 16, 1, "c0_config1"         },
3643   { 16, 2, "c0_config2"         },
3644   { 16, 3, "c0_config3"         },
3645   { 18, 1, "c0_watchlo,1"       },
3646   { 18, 2, "c0_watchlo,2"       },
3647   { 18, 3, "c0_watchlo,3"       },
3648   { 18, 4, "c0_watchlo,4"       },
3649   { 18, 5, "c0_watchlo,5"       },
3650   { 18, 6, "c0_watchlo,6"       },
3651   { 18, 7, "c0_watchlo,7"       },
3652   { 19, 1, "c0_watchhi,1"       },
3653   { 19, 2, "c0_watchhi,2"       },
3654   { 19, 3, "c0_watchhi,3"       },
3655   { 19, 4, "c0_watchhi,4"       },
3656   { 19, 5, "c0_watchhi,5"       },
3657   { 19, 6, "c0_watchhi,6"       },
3658   { 19, 7, "c0_watchhi,7"       },
3659   { 23, 1, "c0_tracecontrol"    },
3660   { 23, 2, "c0_tracecontrol2"   },
3661   { 23, 3, "c0_usertracedata"   },
3662   { 23, 4, "c0_tracebpc"        },
3663   { 25, 1, "c0_perfcnt,1"       },
3664   { 25, 2, "c0_perfcnt,2"       },
3665   { 25, 3, "c0_perfcnt,3"       },
3666   { 25, 4, "c0_perfcnt,4"       },
3667   { 25, 5, "c0_perfcnt,5"       },
3668   { 25, 6, "c0_perfcnt,6"       },
3669   { 25, 7, "c0_perfcnt,7"       },
3670   { 27, 1, "c0_cacheerr,1"      },
3671   { 27, 2, "c0_cacheerr,2"      },
3672   { 27, 3, "c0_cacheerr,3"      },
3673   { 28, 1, "c0_datalo"          },
3674   { 28, 2, "c0_taglo1"          },
3675   { 28, 3, "c0_datalo1"         },
3676   { 28, 4, "c0_taglo2"          },
3677   { 28, 5, "c0_datalo2"         },
3678   { 28, 6, "c0_taglo3"          },
3679   { 28, 7, "c0_datalo3"         },
3680   { 29, 1, "c0_datahi"          },
3681   { 29, 2, "c0_taghi1"          },
3682   { 29, 3, "c0_datahi1"         },
3683   { 29, 4, "c0_taghi2"          },
3684   { 29, 5, "c0_datahi2"         },
3685   { 29, 6, "c0_taghi3"          },
3686   { 29, 7, "c0_datahi3"         },
3687 };
3688
3689 static const char * const mips_cp0_names_mips3264r2[32] =
3690 {
3691   "c0_index",     "c0_random",    "c0_entrylo0",  "c0_entrylo1",
3692   "c0_context",   "c0_pagemask",  "c0_wired",     "c0_hwrena",
3693   "c0_badvaddr",  "c0_count",     "c0_entryhi",   "c0_compare",
3694   "c0_status",    "c0_cause",     "c0_epc",       "c0_prid",
3695   "c0_config",    "c0_lladdr",    "c0_watchlo",   "c0_watchhi",
3696   "c0_xcontext",  "$21",          "$22",          "c0_debug",
3697   "c0_depc",      "c0_perfcnt",   "c0_errctl",    "c0_cacheerr",
3698   "c0_taglo",     "c0_taghi",     "c0_errorepc",  "c0_desave",
3699 };
3700
3701 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] =
3702 {
3703   {  4, 1, "c0_contextconfig"   },
3704   {  5, 1, "c0_pagegrain"       },
3705   { 12, 1, "c0_intctl"          },
3706   { 12, 2, "c0_srsctl"          },
3707   { 12, 3, "c0_srsmap"          },
3708   { 15, 1, "c0_ebase"           },
3709   { 16, 1, "c0_config1"         },
3710   { 16, 2, "c0_config2"         },
3711   { 16, 3, "c0_config3"         },
3712   { 18, 1, "c0_watchlo,1"       },
3713   { 18, 2, "c0_watchlo,2"       },
3714   { 18, 3, "c0_watchlo,3"       },
3715   { 18, 4, "c0_watchlo,4"       },
3716   { 18, 5, "c0_watchlo,5"       },
3717   { 18, 6, "c0_watchlo,6"       },
3718   { 18, 7, "c0_watchlo,7"       },
3719   { 19, 1, "c0_watchhi,1"       },
3720   { 19, 2, "c0_watchhi,2"       },
3721   { 19, 3, "c0_watchhi,3"       },
3722   { 19, 4, "c0_watchhi,4"       },
3723   { 19, 5, "c0_watchhi,5"       },
3724   { 19, 6, "c0_watchhi,6"       },
3725   { 19, 7, "c0_watchhi,7"       },
3726   { 23, 1, "c0_tracecontrol"    },
3727   { 23, 2, "c0_tracecontrol2"   },
3728   { 23, 3, "c0_usertracedata"   },
3729   { 23, 4, "c0_tracebpc"        },
3730   { 25, 1, "c0_perfcnt,1"       },
3731   { 25, 2, "c0_perfcnt,2"       },
3732   { 25, 3, "c0_perfcnt,3"       },
3733   { 25, 4, "c0_perfcnt,4"       },
3734   { 25, 5, "c0_perfcnt,5"       },
3735   { 25, 6, "c0_perfcnt,6"       },
3736   { 25, 7, "c0_perfcnt,7"       },
3737   { 27, 1, "c0_cacheerr,1"      },
3738   { 27, 2, "c0_cacheerr,2"      },
3739   { 27, 3, "c0_cacheerr,3"      },
3740   { 28, 1, "c0_datalo"          },
3741   { 28, 2, "c0_taglo1"          },
3742   { 28, 3, "c0_datalo1"         },
3743   { 28, 4, "c0_taglo2"          },
3744   { 28, 5, "c0_datalo2"         },
3745   { 28, 6, "c0_taglo3"          },
3746   { 28, 7, "c0_datalo3"         },
3747   { 29, 1, "c0_datahi"          },
3748   { 29, 2, "c0_taghi1"          },
3749   { 29, 3, "c0_datahi1"         },
3750   { 29, 4, "c0_taghi2"          },
3751   { 29, 5, "c0_datahi2"         },
3752   { 29, 6, "c0_taghi3"          },
3753   { 29, 7, "c0_datahi3"         },
3754 };
3755
3756 /* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods.  */
3757 static const char * const mips_cp0_names_sb1[32] =
3758 {
3759   "c0_index",     "c0_random",    "c0_entrylo0",  "c0_entrylo1",
3760   "c0_context",   "c0_pagemask",  "c0_wired",     "$7",
3761   "c0_badvaddr",  "c0_count",     "c0_entryhi",   "c0_compare",
3762   "c0_status",    "c0_cause",     "c0_epc",       "c0_prid",
3763   "c0_config",    "c0_lladdr",    "c0_watchlo",   "c0_watchhi",
3764   "c0_xcontext",  "$21",          "$22",          "c0_debug",
3765   "c0_depc",      "c0_perfcnt",   "c0_errctl",    "c0_cacheerr_i",
3766   "c0_taglo_i",   "c0_taghi_i",   "c0_errorepc",  "c0_desave",
3767 };
3768
3769 static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] =
3770 {
3771   { 16, 1, "c0_config1"         },
3772   { 18, 1, "c0_watchlo,1"       },
3773   { 19, 1, "c0_watchhi,1"       },
3774   { 22, 0, "c0_perftrace"       },
3775   { 23, 3, "c0_edebug"          },
3776   { 25, 1, "c0_perfcnt,1"       },
3777   { 25, 2, "c0_perfcnt,2"       },
3778   { 25, 3, "c0_perfcnt,3"       },
3779   { 25, 4, "c0_perfcnt,4"       },
3780   { 25, 5, "c0_perfcnt,5"       },
3781   { 25, 6, "c0_perfcnt,6"       },
3782   { 25, 7, "c0_perfcnt,7"       },
3783   { 26, 1, "c0_buserr_pa"       },
3784   { 27, 1, "c0_cacheerr_d"      },
3785   { 27, 3, "c0_cacheerr_d_pa"   },
3786   { 28, 1, "c0_datalo_i"        },
3787   { 28, 2, "c0_taglo_d"         },
3788   { 28, 3, "c0_datalo_d"        },
3789   { 29, 1, "c0_datahi_i"        },
3790   { 29, 2, "c0_taghi_d"         },
3791   { 29, 3, "c0_datahi_d"        },
3792 };
3793
3794 static const char * const mips_hwr_names_numeric[32] =
3795 {
3796   "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
3797   "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
3798   "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
3799   "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31"
3800 };
3801
3802 static const char * const mips_hwr_names_mips3264r2[32] =
3803 {
3804   "hwr_cpunum",   "hwr_synci_step", "hwr_cc",     "hwr_ccres",
3805   "$4",          "$5",            "$6",           "$7",
3806   "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
3807   "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
3808   "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31"
3809 };
3810
3811 static const char * const mips_msa_control_names_mips3264r2[32] = {
3812   "MSAIR", "MSACSR", "$2", "$3",  "$4",   "$5",   "$6",   "$7",
3813   "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
3814   "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
3815   "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31"
3816 };
3817
3818 struct mips_abi_choice
3819 {
3820   const char *name;
3821   const char * const *gpr_names;
3822   const char * const *fpr_names;
3823 };
3824
3825 static struct mips_abi_choice mips_abi_choices[] =
3826 {
3827   { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric },
3828   { "32", mips_gpr_names_oldabi, mips_fpr_names_32 },
3829   { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 },
3830   { "64", mips_gpr_names_newabi, mips_fpr_names_64 },
3831 };
3832
3833 struct mips_arch_choice
3834 {
3835   const char *name;
3836   int bfd_mach_valid;
3837   unsigned long bfd_mach;
3838   int processor;
3839   int isa;
3840   const char * const *cp0_names;
3841   const struct mips_cp0sel_name *cp0sel_names;
3842   unsigned int cp0sel_names_len;
3843   const char * const *hwr_names;
3844 };
3845
3846 #define bfd_mach_mips3000              3000
3847 #define bfd_mach_mips3900              3900
3848 #define bfd_mach_mips4000              4000
3849 #define bfd_mach_mips4010              4010
3850 #define bfd_mach_mips4100              4100
3851 #define bfd_mach_mips4111              4111
3852 #define bfd_mach_mips4120              4120
3853 #define bfd_mach_mips4300              4300
3854 #define bfd_mach_mips4400              4400
3855 #define bfd_mach_mips4600              4600
3856 #define bfd_mach_mips4650              4650
3857 #define bfd_mach_mips5000              5000
3858 #define bfd_mach_mips5400              5400
3859 #define bfd_mach_mips5500              5500
3860 #define bfd_mach_mips6000              6000
3861 #define bfd_mach_mips7000              7000
3862 #define bfd_mach_mips8000              8000
3863 #define bfd_mach_mips9000              9000
3864 #define bfd_mach_mips10000             10000
3865 #define bfd_mach_mips12000             12000
3866 #define bfd_mach_mips16                16
3867 #define bfd_mach_mips5                 5
3868 #define bfd_mach_mips_sb1              12310201 /* octal 'SB', 01 */
3869 #define bfd_mach_mipsisa32             32
3870 #define bfd_mach_mipsisa32r2           33
3871 #define bfd_mach_mipsisa64             64
3872 #define bfd_mach_mipsisa64r2           65
3873
3874 static const struct mips_arch_choice mips_arch_choices[] =
3875 {
3876   { "numeric",  0, 0, 0, 0,
3877     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3878
3879   { "r3000",    1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1,
3880     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3881   { "r3900",    1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1,
3882     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3883   { "r4000",    1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3,
3884     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3885   { "r4010",    1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2,
3886     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3887   { "vr4100",   1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3,
3888     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3889   { "vr4111",   1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3,
3890     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3891   { "vr4120",   1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3,
3892     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3893   { "r4300",    1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3,
3894     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3895   { "r4400",    1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3,
3896     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3897   { "r4600",    1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3,
3898     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3899   { "r4650",    1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3,
3900     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3901   { "r5000",    1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4,
3902     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3903   { "vr5400",   1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4,
3904     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3905   { "vr5500",   1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4,
3906     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3907   { "r6000",    1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2,
3908     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3909   { "rm7000",   1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
3910     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3911   { "rm9000",   1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
3912     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3913   { "r8000",    1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4,
3914     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3915   { "r10000",   1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4,
3916     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3917   { "r12000",   1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4,
3918     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3919   { "mips5",    1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5,
3920     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3921
3922   /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
3923      Note that MIPS-3D and MDMX are not applicable to MIPS32.  (See
3924      _MIPS32 Architecture For Programmers Volume I: Introduction to the
3925      MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
3926      page 1.  */
3927   { "mips32",   1, bfd_mach_mipsisa32, CPU_MIPS32,
3928     ISA_MIPS32 | INSN_MIPS16 | INSN_SMARTMIPS,
3929     mips_cp0_names_mips3264,
3930     mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
3931     mips_hwr_names_numeric },
3932
3933   { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
3934     (ISA_MIPS32R2 | INSN_MIPS16 | INSN_SMARTMIPS | INSN_DSP | INSN_DSPR2
3935      | INSN_MIPS3D | INSN_MT | INSN_MSA),
3936     mips_cp0_names_mips3264r2,
3937     mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
3938     mips_hwr_names_mips3264r2 },
3939
3940   /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs.  */
3941   { "mips64",   1, bfd_mach_mipsisa64, CPU_MIPS64,
3942     ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX,
3943     mips_cp0_names_mips3264,
3944     mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
3945     mips_hwr_names_numeric },
3946
3947   { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
3948     (ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_DSP | INSN_DSPR2
3949      | INSN_DSP64 | INSN_MT | INSN_MDMX),
3950     mips_cp0_names_mips3264r2,
3951     mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
3952     mips_hwr_names_mips3264r2 },
3953
3954   { "sb1",      1, bfd_mach_mips_sb1, CPU_SB1,
3955     ISA_MIPS64 | INSN_MIPS3D | INSN_SB1,
3956     mips_cp0_names_sb1,
3957     mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1),
3958     mips_hwr_names_numeric },
3959
3960   /* This entry, mips16, is here only for ISA/processor selection; do
3961      not print its name.  */
3962   { "",         1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16,
3963     mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3964 };
3965
3966 /* ISA and processor type to disassemble for, and register names to use.
3967    set_default_mips_dis_options and parse_mips_dis_options fill in these
3968    values.  */
3969 static int mips_processor;
3970 static int mips_isa;
3971 static const char * const *mips_gpr_names;
3972 static const char * const *mips_fpr_names;
3973 static const char * const *mips_cp0_names;
3974 static const struct mips_cp0sel_name *mips_cp0sel_names;
3975 static int mips_cp0sel_names_len;
3976 static const char * const *mips_hwr_names;
3977
3978 /* Other options */
3979 static int no_aliases;  /* If set disassemble as most general inst.  */
3980 \f
3981 static const struct mips_abi_choice *
3982 choose_abi_by_name (const char *name, unsigned int namelen)
3983 {
3984   const struct mips_abi_choice *c;
3985   unsigned int i;
3986
3987   for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++)
3988     if (strncmp (mips_abi_choices[i].name, name, namelen) == 0
3989         && strlen (mips_abi_choices[i].name) == namelen)
3990       c = &mips_abi_choices[i];
3991
3992   return c;
3993 }
3994
3995 static const struct mips_arch_choice *
3996 choose_arch_by_name (const char *name, unsigned int namelen)
3997 {
3998   const struct mips_arch_choice *c = NULL;
3999   unsigned int i;
4000
4001   for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
4002     if (strncmp (mips_arch_choices[i].name, name, namelen) == 0
4003         && strlen (mips_arch_choices[i].name) == namelen)
4004       c = &mips_arch_choices[i];
4005
4006   return c;
4007 }
4008
4009 static const struct mips_arch_choice *
4010 choose_arch_by_number (unsigned long mach)
4011 {
4012   static unsigned long hint_bfd_mach;
4013   static const struct mips_arch_choice *hint_arch_choice;
4014   const struct mips_arch_choice *c;
4015   unsigned int i;
4016
4017   /* We optimize this because even if the user specifies no
4018      flags, this will be done for every instruction!  */
4019   if (hint_bfd_mach == mach
4020       && hint_arch_choice != NULL
4021       && hint_arch_choice->bfd_mach == hint_bfd_mach)
4022     return hint_arch_choice;
4023
4024   for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
4025     {
4026       if (mips_arch_choices[i].bfd_mach_valid
4027           && mips_arch_choices[i].bfd_mach == mach)
4028         {
4029           c = &mips_arch_choices[i];
4030           hint_bfd_mach = mach;
4031           hint_arch_choice = c;
4032         }
4033     }
4034   return c;
4035 }
4036
4037 static void
4038 set_default_mips_dis_options (struct disassemble_info *info)
4039 {
4040   const struct mips_arch_choice *chosen_arch;
4041
4042   /* Defaults: mipsIII/r3000 (?!), (o)32-style ("oldabi") GPR names,
4043      and numeric FPR, CP0 register, and HWR names.  */
4044   mips_isa = ISA_MIPS3;
4045   mips_processor =  CPU_R3000;
4046   mips_gpr_names = mips_gpr_names_oldabi;
4047   mips_fpr_names = mips_fpr_names_numeric;
4048   mips_cp0_names = mips_cp0_names_numeric;
4049   mips_cp0sel_names = NULL;
4050   mips_cp0sel_names_len = 0;
4051   mips_hwr_names = mips_hwr_names_numeric;
4052   no_aliases = 0;
4053
4054   /* If an ELF "newabi" binary, use the n32/(n)64 GPR names.  */
4055 #if 0
4056   if (info->flavour == bfd_target_elf_flavour && info->section != NULL)
4057     {
4058       Elf_Internal_Ehdr *header;
4059
4060       header = elf_elfheader (info->section->owner);
4061       if (is_newabi (header))
4062         mips_gpr_names = mips_gpr_names_newabi;
4063     }
4064 #endif
4065
4066   /* Set ISA, architecture, and cp0 register names as best we can.  */
4067 #if !defined(SYMTAB_AVAILABLE) && 0
4068   /* This is running out on a target machine, not in a host tool.
4069      FIXME: Where does mips_target_info come from?  */
4070   target_processor = mips_target_info.processor;
4071   mips_isa = mips_target_info.isa;
4072 #else
4073   chosen_arch = choose_arch_by_number (info->mach);
4074   if (chosen_arch != NULL)
4075     {
4076       mips_processor = chosen_arch->processor;
4077       mips_isa = chosen_arch->isa;
4078       mips_cp0_names = chosen_arch->cp0_names;
4079       mips_cp0sel_names = chosen_arch->cp0sel_names;
4080       mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
4081       mips_hwr_names = chosen_arch->hwr_names;
4082     }
4083 #endif
4084 }
4085
4086 static void
4087 parse_mips_dis_option (const char *option, unsigned int len)
4088 {
4089   unsigned int i, optionlen, vallen;
4090   const char *val;
4091   const struct mips_abi_choice *chosen_abi;
4092   const struct mips_arch_choice *chosen_arch;
4093
4094   /* Look for the = that delimits the end of the option name.  */
4095   for (i = 0; i < len; i++)
4096     {
4097       if (option[i] == '=')
4098         break;
4099     }
4100   if (i == 0)           /* Invalid option: no name before '='.  */
4101     return;
4102   if (i == len)         /* Invalid option: no '='.  */
4103     return;
4104   if (i == (len - 1))   /* Invalid option: no value after '='.  */
4105     return;
4106
4107   optionlen = i;
4108   val = option + (optionlen + 1);
4109   vallen = len - (optionlen + 1);
4110
4111   if (strncmp("gpr-names", option, optionlen) == 0
4112       && strlen("gpr-names") == optionlen)
4113     {
4114       chosen_abi = choose_abi_by_name (val, vallen);
4115       if (chosen_abi != NULL)
4116         mips_gpr_names = chosen_abi->gpr_names;
4117       return;
4118     }
4119
4120   if (strncmp("fpr-names", option, optionlen) == 0
4121       && strlen("fpr-names") == optionlen)
4122     {
4123       chosen_abi = choose_abi_by_name (val, vallen);
4124       if (chosen_abi != NULL)
4125         mips_fpr_names = chosen_abi->fpr_names;
4126       return;
4127     }
4128
4129   if (strncmp("cp0-names", option, optionlen) == 0
4130       && strlen("cp0-names") == optionlen)
4131     {
4132       chosen_arch = choose_arch_by_name (val, vallen);
4133       if (chosen_arch != NULL)
4134         {
4135           mips_cp0_names = chosen_arch->cp0_names;
4136           mips_cp0sel_names = chosen_arch->cp0sel_names;
4137           mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
4138         }
4139       return;
4140     }
4141
4142   if (strncmp("hwr-names", option, optionlen) == 0
4143       && strlen("hwr-names") == optionlen)
4144     {
4145       chosen_arch = choose_arch_by_name (val, vallen);
4146       if (chosen_arch != NULL)
4147         mips_hwr_names = chosen_arch->hwr_names;
4148       return;
4149     }
4150
4151   if (strncmp("reg-names", option, optionlen) == 0
4152       && strlen("reg-names") == optionlen)
4153     {
4154       /* We check both ABI and ARCH here unconditionally, so
4155          that "numeric" will do the desirable thing: select
4156          numeric register names for all registers.  Other than
4157          that, a given name probably won't match both.  */
4158       chosen_abi = choose_abi_by_name (val, vallen);
4159       if (chosen_abi != NULL)
4160         {
4161           mips_gpr_names = chosen_abi->gpr_names;
4162           mips_fpr_names = chosen_abi->fpr_names;
4163         }
4164       chosen_arch = choose_arch_by_name (val, vallen);
4165       if (chosen_arch != NULL)
4166         {
4167           mips_cp0_names = chosen_arch->cp0_names;
4168           mips_cp0sel_names = chosen_arch->cp0sel_names;
4169           mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
4170           mips_hwr_names = chosen_arch->hwr_names;
4171         }
4172       return;
4173     }
4174
4175   /* Invalid option.  */
4176 }
4177
4178 static void
4179 parse_mips_dis_options (const char *options)
4180 {
4181   const char *option_end;
4182
4183   if (options == NULL)
4184     return;
4185
4186   while (*options != '\0')
4187     {
4188       /* Skip empty options.  */
4189       if (*options == ',')
4190         {
4191           options++;
4192           continue;
4193         }
4194
4195       /* We know that *options is neither NUL or a comma.  */
4196       option_end = options + 1;
4197       while (*option_end != ',' && *option_end != '\0')
4198         option_end++;
4199
4200       parse_mips_dis_option (options, option_end - options);
4201
4202       /* Go on to the next one.  If option_end points to a comma, it
4203          will be skipped above.  */
4204       options = option_end;
4205     }
4206 }
4207
4208 static const struct mips_cp0sel_name *
4209 lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names,
4210                          unsigned int len,
4211                          unsigned int cp0reg,
4212                          unsigned int sel)
4213 {
4214   unsigned int i;
4215
4216   for (i = 0; i < len; i++)
4217     if (names[i].cp0reg == cp0reg && names[i].sel == sel)
4218       return &names[i];
4219   return NULL;
4220 }
4221 \f
4222 /* Print insn arguments for 32/64-bit code.  */
4223
4224 static void
4225 print_insn_args (const char *d,
4226                  register unsigned long int l,
4227                  bfd_vma pc,
4228                  struct disassemble_info *info,
4229                  const struct mips_opcode *opp)
4230 {
4231   int op, delta;
4232   unsigned int lsb, msb, msbd;
4233
4234   lsb = 0;
4235
4236   for (; *d != '\0'; d++)
4237     {
4238       switch (*d)
4239         {
4240         case ',':
4241         case '(':
4242         case ')':
4243         case '[':
4244         case ']':
4245           (*info->fprintf_func) (info->stream, "%c", *d);
4246           break;
4247
4248         case '+':
4249           /* Extension character; switch for second char.  */
4250           d++;
4251           switch (*d)
4252             {
4253             case '\0':
4254               /* xgettext:c-format */
4255               (*info->fprintf_func) (info->stream,
4256                                      _("# internal error, incomplete extension sequence (+)"));
4257               return;
4258
4259             case 'A':
4260               lsb = (l >> OP_SH_SHAMT) & OP_MASK_SHAMT;
4261               (*info->fprintf_func) (info->stream, "0x%x", lsb);
4262               break;
4263
4264             case 'B':
4265               msb = (l >> OP_SH_INSMSB) & OP_MASK_INSMSB;
4266               (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
4267               break;
4268
4269             case '1':
4270               (*info->fprintf_func) (info->stream, "0x%lx",
4271                                      (l >> OP_SH_UDI1) & OP_MASK_UDI1);
4272               break;
4273
4274             case '2':
4275               (*info->fprintf_func) (info->stream, "0x%lx",
4276                                      (l >> OP_SH_UDI2) & OP_MASK_UDI2);
4277               break;
4278
4279             case '3':
4280               (*info->fprintf_func) (info->stream, "0x%lx",
4281                                      (l >> OP_SH_UDI3) & OP_MASK_UDI3);
4282               break;
4283
4284             case '4':
4285               (*info->fprintf_func) (info->stream, "0x%lx",
4286                                      (l >> OP_SH_UDI4) & OP_MASK_UDI4);
4287               break;
4288
4289         case '5': /* 5-bit signed immediate in bit 16 */
4290             delta = ((l >> OP_SH_RT) & OP_MASK_RT);
4291             if (delta & 0x10) { /* test sign bit */
4292                 delta |= ~OP_MASK_RT;
4293             }
4294             (*info->fprintf_func) (info->stream, "%d", delta);
4295             break;
4296
4297         case '6':
4298             (*info->fprintf_func) (info->stream, "0x%lx",
4299                     (l >> OP_SH_2BIT) & OP_MASK_2BIT);
4300             break;
4301
4302         case '7':
4303             (*info->fprintf_func) (info->stream, "0x%lx",
4304                     (l >> OP_SH_3BIT) & OP_MASK_3BIT);
4305             break;
4306
4307         case '8':
4308             (*info->fprintf_func) (info->stream, "0x%lx",
4309                     (l >> OP_SH_4BIT) & OP_MASK_4BIT);
4310             break;
4311
4312         case '9':
4313             (*info->fprintf_func) (info->stream, "0x%lx",
4314                     (l >> OP_SH_5BIT) & OP_MASK_5BIT);
4315             break;
4316
4317         case ':':
4318             (*info->fprintf_func) (info->stream, "0x%lx",
4319                     (l >> OP_SH_1BIT) & OP_MASK_1BIT);
4320             break;
4321
4322         case '!': /* 10-bit pc-relative target in bit 11 */
4323             delta = ((l >> OP_SH_10BIT) & OP_MASK_10BIT);
4324             if (delta & 0x200) { /* test sign bit */
4325                 delta |= ~OP_MASK_10BIT;
4326             }
4327             info->target = (delta << 2) + pc + INSNLEN;
4328             (*info->print_address_func) (info->target, info);
4329             break;
4330
4331         case '~':
4332             (*info->fprintf_func) (info->stream, "0");
4333             break;
4334
4335         case '@':
4336             (*info->fprintf_func) (info->stream, "0x%lx",
4337                     ((l >> OP_SH_1_TO_4) & OP_MASK_1_TO_4)+1);
4338             break;
4339
4340         case '^': /* 10-bit signed immediate << 0 in bit 16 */
4341             delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10);
4342             if (delta & 0x200) { /* test sign bit */
4343                 delta |= ~OP_MASK_IMM10;
4344             }
4345             (*info->fprintf_func) (info->stream, "%d", delta);
4346             break;
4347
4348         case '#': /* 10-bit signed immediate << 1 in bit 16 */
4349             delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10);
4350             if (delta & 0x200) { /* test sign bit */
4351                 delta |= ~OP_MASK_IMM10;
4352             }
4353             (*info->fprintf_func) (info->stream, "%d", delta << 1);
4354             break;
4355
4356         case '$': /* 10-bit signed immediate << 2 in bit 16 */
4357             delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10);
4358             if (delta & 0x200) { /* test sign bit */
4359                 delta |= ~OP_MASK_IMM10;
4360             }
4361             (*info->fprintf_func) (info->stream, "%d", delta << 2);
4362             break;
4363
4364         case '%': /* 10-bit signed immediate << 3 in bit 16 */
4365             delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10);
4366             if (delta & 0x200) { /* test sign bit */
4367                 delta |= ~OP_MASK_IMM10;
4368             }
4369             (*info->fprintf_func) (info->stream, "%d", delta << 3);
4370             break;
4371
4372             case 'C':
4373             case 'H':
4374               msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD;
4375               (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
4376               break;
4377
4378             case 'D':
4379               {
4380                 const struct mips_cp0sel_name *n;
4381                 unsigned int cp0reg, sel;
4382
4383                 cp0reg = (l >> OP_SH_RD) & OP_MASK_RD;
4384                 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
4385
4386                 /* CP0 register including 'sel' code for mtcN (et al.), to be
4387                    printed textually if known.  If not known, print both
4388                    CP0 register name and sel numerically since CP0 register
4389                    with sel 0 may have a name unrelated to register being
4390                    printed.  */
4391                 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
4392                                             mips_cp0sel_names_len, cp0reg, sel);
4393                 if (n != NULL)
4394                   (*info->fprintf_func) (info->stream, "%s", n->name);
4395                 else
4396                   (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
4397                 break;
4398               }
4399
4400             case 'E':
4401               lsb = ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT) + 32;
4402               (*info->fprintf_func) (info->stream, "0x%x", lsb);
4403               break;
4404
4405             case 'F':
4406               msb = ((l >> OP_SH_INSMSB) & OP_MASK_INSMSB) + 32;
4407               (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
4408               break;
4409
4410             case 'G':
4411               msbd = ((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD) + 32;
4412               (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
4413               break;
4414
4415             case 'o':
4416                 switch (*(d+1)) {
4417                 case '1':
4418                     d++;
4419                     delta = l & ((1 << 18) - 1);
4420                     if (delta & 0x20000) {
4421                         delta |= ~0x1ffff;
4422                     }
4423                     break;
4424                 case '2':
4425                     d++;
4426                     delta = l & ((1 << 19) - 1);
4427                     if (delta & 0x40000) {
4428                         delta |= ~0x3ffff;
4429                     }
4430                     break;
4431                 default:
4432                     delta = (l >> OP_SH_DELTA_R6) & OP_MASK_DELTA_R6;
4433                     if (delta & 0x8000) {
4434                         delta |= ~0xffff;
4435                     }
4436                 }
4437
4438                 (*info->fprintf_func) (info->stream, "%d", delta);
4439                 break;
4440
4441             case 'p':
4442                 /* Sign extend the displacement with 26 bits.  */
4443                 delta = (l >> OP_SH_DELTA) & OP_MASK_TARGET;
4444                 if (delta & 0x2000000) {
4445                     delta |= ~0x3FFFFFF;
4446                 }
4447                 info->target = (delta << 2) + pc + INSNLEN;
4448                 (*info->print_address_func) (info->target, info);
4449                 break;
4450
4451             case 't': /* Coprocessor 0 reg name */
4452               (*info->fprintf_func) (info->stream, "%s",
4453                                      mips_cp0_names[(l >> OP_SH_RT) &
4454                                                      OP_MASK_RT]);
4455               break;
4456
4457             case 'T': /* Coprocessor 0 reg name */
4458               {
4459                 const struct mips_cp0sel_name *n;
4460                 unsigned int cp0reg, sel;
4461
4462                 cp0reg = (l >> OP_SH_RT) & OP_MASK_RT;
4463                 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
4464
4465                 /* CP0 register including 'sel' code for mftc0, to be
4466                    printed textually if known.  If not known, print both
4467                    CP0 register name and sel numerically since CP0 register
4468                    with sel 0 may have a name unrelated to register being
4469                    printed.  */
4470                 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
4471                                             mips_cp0sel_names_len, cp0reg, sel);
4472                 if (n != NULL)
4473                   (*info->fprintf_func) (info->stream, "%s", n->name);
4474                 else
4475                   (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
4476                 break;
4477               }
4478
4479         case 'd':
4480             (*info->fprintf_func) (info->stream, "%s",
4481                     mips_wr_names[(l >> OP_SH_FD) & OP_MASK_FD]);
4482             break;
4483
4484         case 'e':
4485             (*info->fprintf_func) (info->stream, "%s",
4486                     mips_wr_names[(l >> OP_SH_FS) & OP_MASK_FS]);
4487             break;
4488
4489         case 'f':
4490             (*info->fprintf_func) (info->stream, "%s",
4491                     mips_wr_names[(l >> OP_SH_FT) & OP_MASK_FT]);
4492             break;
4493
4494         case 'g':
4495             (*info->fprintf_func) (info->stream, "%s",
4496                     mips_msa_control_names_mips3264r2[(l >> OP_SH_MSACR11)
4497                                                       & OP_MASK_MSACR11]);
4498             break;
4499
4500         case 'h':
4501             (*info->fprintf_func) (info->stream, "%s",
4502                     mips_msa_control_names_mips3264r2[(l >> OP_SH_MSACR6)
4503                                                       & OP_MASK_MSACR6]);
4504             break;
4505
4506         case 'i':
4507             (*info->fprintf_func) (info->stream, "%s",
4508                     mips_gpr_names[(l >> OP_SH_GPR) & OP_MASK_GPR]);
4509             break;
4510
4511             default:
4512               /* xgettext:c-format */
4513               (*info->fprintf_func) (info->stream,
4514                                      _("# internal error, undefined extension sequence (+%c)"),
4515                                      *d);
4516               return;
4517             }
4518           break;
4519
4520         case '2':
4521           (*info->fprintf_func) (info->stream, "0x%lx",
4522                                  (l >> OP_SH_BP) & OP_MASK_BP);
4523           break;
4524
4525         case '3':
4526           (*info->fprintf_func) (info->stream, "0x%lx",
4527                                  (l >> OP_SH_SA3) & OP_MASK_SA3);
4528           break;
4529
4530         case '4':
4531           (*info->fprintf_func) (info->stream, "0x%lx",
4532                                  (l >> OP_SH_SA4) & OP_MASK_SA4);
4533           break;
4534
4535         case '5':
4536           (*info->fprintf_func) (info->stream, "0x%lx",
4537                                  (l >> OP_SH_IMM8) & OP_MASK_IMM8);
4538           break;
4539
4540         case '6':
4541           (*info->fprintf_func) (info->stream, "0x%lx",
4542                                  (l >> OP_SH_RS) & OP_MASK_RS);
4543           break;
4544
4545         case '7':
4546           (*info->fprintf_func) (info->stream, "$ac%ld",
4547                                  (l >> OP_SH_DSPACC) & OP_MASK_DSPACC);
4548           break;
4549
4550         case '8':
4551           (*info->fprintf_func) (info->stream, "0x%lx",
4552                                  (l >> OP_SH_WRDSP) & OP_MASK_WRDSP);
4553           break;
4554
4555         case '9':
4556           (*info->fprintf_func) (info->stream, "$ac%ld",
4557                                  (l >> OP_SH_DSPACC_S) & OP_MASK_DSPACC_S);
4558           break;
4559
4560         case '0': /* dsp 6-bit signed immediate in bit 20 */
4561           delta = ((l >> OP_SH_DSPSFT) & OP_MASK_DSPSFT);
4562           if (delta & 0x20) /* test sign bit */
4563             delta |= ~OP_MASK_DSPSFT;
4564           (*info->fprintf_func) (info->stream, "%d", delta);
4565           break;
4566
4567         case ':': /* dsp 7-bit signed immediate in bit 19 */
4568           delta = ((l >> OP_SH_DSPSFT_7) & OP_MASK_DSPSFT_7);
4569           if (delta & 0x40) /* test sign bit */
4570             delta |= ~OP_MASK_DSPSFT_7;
4571           (*info->fprintf_func) (info->stream, "%d", delta);
4572           break;
4573
4574         case '\'':
4575           (*info->fprintf_func) (info->stream, "0x%lx",
4576                                  (l >> OP_SH_RDDSP) & OP_MASK_RDDSP);
4577           break;
4578
4579         case '@': /* dsp 10-bit signed immediate in bit 16 */
4580           delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10);
4581           if (delta & 0x200) /* test sign bit */
4582             delta |= ~OP_MASK_IMM10;
4583           (*info->fprintf_func) (info->stream, "%d", delta);
4584           break;
4585
4586         case '!':
4587           (*info->fprintf_func) (info->stream, "%ld",
4588                                  (l >> OP_SH_MT_U) & OP_MASK_MT_U);
4589           break;
4590
4591         case '$':
4592           (*info->fprintf_func) (info->stream, "%ld",
4593                                  (l >> OP_SH_MT_H) & OP_MASK_MT_H);
4594           break;
4595
4596         case '*':
4597           (*info->fprintf_func) (info->stream, "$ac%ld",
4598                                  (l >> OP_SH_MTACC_T) & OP_MASK_MTACC_T);
4599           break;
4600
4601         case '&':
4602           (*info->fprintf_func) (info->stream, "$ac%ld",
4603                                  (l >> OP_SH_MTACC_D) & OP_MASK_MTACC_D);
4604           break;
4605
4606         case 'g':
4607           /* Coprocessor register for CTTC1, MTTC2, MTHC2, CTTC2.  */
4608           (*info->fprintf_func) (info->stream, "$%ld",
4609                                  (l >> OP_SH_RD) & OP_MASK_RD);
4610           break;
4611
4612         case 's':
4613         case 'b':
4614         case 'r':
4615         case 'v':
4616           (*info->fprintf_func) (info->stream, "%s",
4617                                  mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]);
4618           break;
4619
4620         case 't':
4621         case 'w':
4622           (*info->fprintf_func) (info->stream, "%s",
4623                                  mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
4624           break;
4625
4626         case 'i':
4627         case 'u':
4628           (*info->fprintf_func) (info->stream, "0x%lx",
4629                                  (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE);
4630           break;
4631
4632         case 'j': /* Same as i, but sign-extended.  */
4633         case 'o':
4634             delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
4635
4636           if (delta & 0x8000)
4637             delta |= ~0xffff;
4638           (*info->fprintf_func) (info->stream, "%d",
4639                                  delta);
4640           break;
4641
4642         case 'h':
4643           (*info->fprintf_func) (info->stream, "0x%x",
4644                                  (unsigned int) ((l >> OP_SH_PREFX)
4645                                                  & OP_MASK_PREFX));
4646           break;
4647
4648         case 'k':
4649           (*info->fprintf_func) (info->stream, "0x%x",
4650                                  (unsigned int) ((l >> OP_SH_CACHE)
4651                                                  & OP_MASK_CACHE));
4652           break;
4653
4654         case 'a':
4655           info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff)
4656                           | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2));
4657           /* For gdb disassembler, force odd address on jalx.  */
4658           if (info->flavour == bfd_target_unknown_flavour
4659               && strcmp (opp->name, "jalx") == 0)
4660             info->target |= 1;
4661           (*info->print_address_func) (info->target, info);
4662           break;
4663
4664         case 'p':
4665           /* Sign extend the displacement.  */
4666           delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
4667           if (delta & 0x8000)
4668             delta |= ~0xffff;
4669           info->target = (delta << 2) + pc + INSNLEN;
4670           (*info->print_address_func) (info->target, info);
4671           break;
4672
4673         case 'd':
4674           (*info->fprintf_func) (info->stream, "%s",
4675                                  mips_gpr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
4676           break;
4677
4678         case 'U':
4679           {
4680             /* First check for both rd and rt being equal.  */
4681             unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD;
4682             if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))
4683               (*info->fprintf_func) (info->stream, "%s",
4684                                      mips_gpr_names[reg]);
4685             else
4686               {
4687                 /* If one is zero use the other.  */
4688                 if (reg == 0)
4689                   (*info->fprintf_func) (info->stream, "%s",
4690                                          mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
4691                 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0)
4692                   (*info->fprintf_func) (info->stream, "%s",
4693                                          mips_gpr_names[reg]);
4694                 else /* Bogus, result depends on processor.  */
4695                   (*info->fprintf_func) (info->stream, "%s or %s",
4696                                          mips_gpr_names[reg],
4697                                          mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
4698               }
4699           }
4700           break;
4701
4702         case 'z':
4703           (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
4704           break;
4705
4706         case '<':
4707           (*info->fprintf_func) (info->stream, "0x%lx",
4708                                  (l >> OP_SH_SHAMT) & OP_MASK_SHAMT);
4709           break;
4710
4711         case 'c':
4712           (*info->fprintf_func) (info->stream, "0x%lx",
4713                                  (l >> OP_SH_CODE) & OP_MASK_CODE);
4714           break;
4715
4716         case 'q':
4717           (*info->fprintf_func) (info->stream, "0x%lx",
4718                                  (l >> OP_SH_CODE2) & OP_MASK_CODE2);
4719           break;
4720
4721         case 'C':
4722           (*info->fprintf_func) (info->stream, "0x%lx",
4723                                  (l >> OP_SH_COPZ) & OP_MASK_COPZ);
4724           break;
4725
4726         case 'B':
4727           (*info->fprintf_func) (info->stream, "0x%lx",
4728
4729                                  (l >> OP_SH_CODE20) & OP_MASK_CODE20);
4730           break;
4731
4732         case 'J':
4733           (*info->fprintf_func) (info->stream, "0x%lx",
4734                                  (l >> OP_SH_CODE19) & OP_MASK_CODE19);
4735           break;
4736
4737         case 'S':
4738         case 'V':
4739           (*info->fprintf_func) (info->stream, "%s",
4740                                  mips_fpr_names[(l >> OP_SH_FS) & OP_MASK_FS]);
4741           break;
4742
4743         case 'T':
4744         case 'W':
4745           (*info->fprintf_func) (info->stream, "%s",
4746                                  mips_fpr_names[(l >> OP_SH_FT) & OP_MASK_FT]);
4747           break;
4748
4749         case 'D':
4750           (*info->fprintf_func) (info->stream, "%s",
4751                                  mips_fpr_names[(l >> OP_SH_FD) & OP_MASK_FD]);
4752           break;
4753
4754         case 'R':
4755           (*info->fprintf_func) (info->stream, "%s",
4756                                  mips_fpr_names[(l >> OP_SH_FR) & OP_MASK_FR]);
4757           break;
4758
4759         case 'E':
4760           /* Coprocessor register for lwcN instructions, et al.
4761
4762              Note that there is no load/store cp0 instructions, and
4763              that FPU (cp1) instructions disassemble this field using
4764              'T' format.  Therefore, until we gain understanding of
4765              cp2 register names, we can simply print the register
4766              numbers.  */
4767           (*info->fprintf_func) (info->stream, "$%ld",
4768                                  (l >> OP_SH_RT) & OP_MASK_RT);
4769           break;
4770
4771         case 'G':
4772           /* Coprocessor register for mtcN instructions, et al.  Note
4773              that FPU (cp1) instructions disassemble this field using
4774              'S' format.  Therefore, we only need to worry about cp0,
4775              cp2, and cp3.  */
4776           op = (l >> OP_SH_OP) & OP_MASK_OP;
4777           if (op == OP_OP_COP0)
4778             (*info->fprintf_func) (info->stream, "%s",
4779                                    mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]);
4780           else
4781             (*info->fprintf_func) (info->stream, "$%ld",
4782                                    (l >> OP_SH_RD) & OP_MASK_RD);
4783           break;
4784
4785         case 'K':
4786           (*info->fprintf_func) (info->stream, "%s",
4787                                  mips_hwr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
4788           break;
4789
4790         case 'N':
4791           (*info->fprintf_func) (info->stream,
4792                                  ((opp->pinfo & (FP_D | FP_S)) != 0
4793                                   ? "$fcc%ld" : "$cc%ld"),
4794                                  (l >> OP_SH_BCC) & OP_MASK_BCC);
4795           break;
4796
4797         case 'M':
4798           (*info->fprintf_func) (info->stream, "$fcc%ld",
4799                                  (l >> OP_SH_CCC) & OP_MASK_CCC);
4800           break;
4801
4802         case 'P':
4803           (*info->fprintf_func) (info->stream, "%ld",
4804                                  (l >> OP_SH_PERFREG) & OP_MASK_PERFREG);
4805           break;
4806
4807         case 'e':
4808           (*info->fprintf_func) (info->stream, "%ld",
4809                                  (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE);
4810           break;
4811
4812         case '%':
4813           (*info->fprintf_func) (info->stream, "%ld",
4814                                  (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN);
4815           break;
4816
4817         case 'H':
4818           (*info->fprintf_func) (info->stream, "%ld",
4819                                  (l >> OP_SH_SEL) & OP_MASK_SEL);
4820           break;
4821
4822         case 'O':
4823           (*info->fprintf_func) (info->stream, "%ld",
4824                                  (l >> OP_SH_ALN) & OP_MASK_ALN);
4825           break;
4826
4827         case 'Q':
4828           {
4829             unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL;
4830
4831             if ((vsel & 0x10) == 0)
4832               {
4833                 int fmt;
4834
4835                 vsel &= 0x0f;
4836                 for (fmt = 0; fmt < 3; fmt++, vsel >>= 1)
4837                   if ((vsel & 1) == 0)
4838                     break;
4839                 (*info->fprintf_func) (info->stream, "$v%ld[%d]",
4840                                        (l >> OP_SH_FT) & OP_MASK_FT,
4841                                        vsel >> 1);
4842               }
4843             else if ((vsel & 0x08) == 0)
4844               {
4845                 (*info->fprintf_func) (info->stream, "$v%ld",
4846                                        (l >> OP_SH_FT) & OP_MASK_FT);
4847               }
4848             else
4849               {
4850                 (*info->fprintf_func) (info->stream, "0x%lx",
4851                                        (l >> OP_SH_FT) & OP_MASK_FT);
4852               }
4853           }
4854           break;
4855
4856         case 'X':
4857           (*info->fprintf_func) (info->stream, "$v%ld",
4858                                  (l >> OP_SH_FD) & OP_MASK_FD);
4859           break;
4860
4861         case 'Y':
4862           (*info->fprintf_func) (info->stream, "$v%ld",
4863                                  (l >> OP_SH_FS) & OP_MASK_FS);
4864           break;
4865
4866         case 'Z':
4867           (*info->fprintf_func) (info->stream, "$v%ld",
4868                                  (l >> OP_SH_FT) & OP_MASK_FT);
4869           break;
4870
4871         default:
4872           /* xgettext:c-format */
4873           (*info->fprintf_func) (info->stream,
4874                                  _("# internal error, undefined modifier(%c)"),
4875                                  *d);
4876           return;
4877         }
4878     }
4879 }
4880 \f
4881 /* Check if the object uses NewABI conventions.  */
4882 #if 0
4883 static int
4884 is_newabi (header)
4885      Elf_Internal_Ehdr *header;
4886 {
4887   /* There are no old-style ABIs which use 64-bit ELF.  */
4888   if (header->e_ident[EI_CLASS] == ELFCLASS64)
4889     return 1;
4890
4891   /* If a 32-bit ELF file, n32 is a new-style ABI.  */
4892   if ((header->e_flags & EF_MIPS_ABI2) != 0)
4893     return 1;
4894
4895   return 0;
4896 }
4897 #endif
4898 \f
4899 /* Print the mips instruction at address MEMADDR in debugged memory,
4900    on using INFO.  Returns length of the instruction, in bytes, which is
4901    always INSNLEN.  BIGENDIAN must be 1 if this is big-endian code, 0 if
4902    this is little-endian code.  */
4903
4904 static int
4905 print_insn_mips (bfd_vma memaddr,
4906                  unsigned long int word,
4907                  struct disassemble_info *info)
4908 {
4909   const struct mips_opcode *op;
4910   static bfd_boolean init = 0;
4911   static const struct mips_opcode *mips_hash[OP_MASK_OP + 1];
4912
4913   /* Build a hash table to shorten the search time.  */
4914   if (! init)
4915     {
4916       unsigned int i;
4917
4918       for (i = 0; i <= OP_MASK_OP; i++)
4919         {
4920           for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++)
4921             {
4922               if (op->pinfo == INSN_MACRO
4923                   || (no_aliases && (op->pinfo2 & INSN2_ALIAS)))
4924                 continue;
4925               if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP))
4926                 {
4927                   mips_hash[i] = op;
4928                   break;
4929                 }
4930             }
4931         }
4932
4933       init = 1;
4934     }
4935
4936   info->bytes_per_chunk = INSNLEN;
4937   info->display_endian = info->endian;
4938   info->insn_info_valid = 1;
4939   info->branch_delay_insns = 0;
4940   info->data_size = 0;
4941   info->insn_type = dis_nonbranch;
4942   info->target = 0;
4943   info->target2 = 0;
4944
4945   op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP];
4946   if (op != NULL)
4947     {
4948       for (; op < &mips_opcodes[NUMOPCODES]; op++)
4949         {
4950           if (op->pinfo != INSN_MACRO
4951               && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
4952               && (word & op->mask) == op->match)
4953             {
4954               const char *d;
4955
4956               /* We always allow to disassemble the jalx instruction.  */
4957               if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor)
4958                   && strcmp (op->name, "jalx"))
4959                 continue;
4960
4961               if (strcmp(op->name, "bovc") == 0
4962                   || strcmp(op->name, "bnvc") == 0) {
4963                   if (((word >> OP_SH_RS) & OP_MASK_RS) <
4964                       ((word >> OP_SH_RT) & OP_MASK_RT)) {
4965                       continue;
4966                   }
4967               }
4968               if (strcmp(op->name, "bgezc") == 0
4969                   || strcmp(op->name, "bltzc") == 0
4970                   || strcmp(op->name, "bgezalc") == 0
4971                   || strcmp(op->name, "bltzalc") == 0) {
4972                   if (((word >> OP_SH_RS) & OP_MASK_RS) !=
4973                       ((word >> OP_SH_RT) & OP_MASK_RT)) {
4974                       continue;
4975                   }
4976               }
4977
4978               /* Figure out instruction type and branch delay information.  */
4979               if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
4980                 {
4981                   if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
4982                     info->insn_type = dis_jsr;
4983                   else
4984                     info->insn_type = dis_branch;
4985                   info->branch_delay_insns = 1;
4986                 }
4987               else if ((op->pinfo & (INSN_COND_BRANCH_DELAY
4988                                      | INSN_COND_BRANCH_LIKELY)) != 0)
4989                 {
4990                   if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
4991                     info->insn_type = dis_condjsr;
4992                   else
4993                     info->insn_type = dis_condbranch;
4994                   info->branch_delay_insns = 1;
4995                 }
4996               else if ((op->pinfo & (INSN_STORE_MEMORY
4997                                      | INSN_LOAD_MEMORY_DELAY)) != 0)
4998                 info->insn_type = dis_dref;
4999
5000               (*info->fprintf_func) (info->stream, "%s", op->name);
5001
5002               d = op->args;
5003               if (d != NULL && *d != '\0')
5004                 {
5005                   (*info->fprintf_func) (info->stream, "\t");
5006                   print_insn_args (d, word, memaddr, info, op);
5007                 }
5008
5009               return INSNLEN;
5010             }
5011         }
5012     }
5013
5014   /* Handle undefined instructions.  */
5015   info->insn_type = dis_noninsn;
5016   (*info->fprintf_func) (info->stream, "0x%lx", word);
5017   return INSNLEN;
5018 }
5019 \f
5020 /* In an environment where we do not know the symbol type of the
5021    instruction we are forced to assume that the low order bit of the
5022    instructions' address may mark it as a mips16 instruction.  If we
5023    are single stepping, or the pc is within the disassembled function,
5024    this works.  Otherwise, we need a clue.  Sometimes.  */
5025
5026 static int
5027 _print_insn_mips (bfd_vma memaddr,
5028                   struct disassemble_info *info,
5029                   enum bfd_endian endianness)
5030 {
5031   bfd_byte buffer[INSNLEN];
5032   int status;
5033
5034   set_default_mips_dis_options (info);
5035   parse_mips_dis_options (info->disassembler_options);
5036
5037 #if 0
5038 #if 1
5039   /* FIXME: If odd address, this is CLEARLY a mips 16 instruction.  */
5040   /* Only a few tools will work this way.  */
5041   if (memaddr & 0x01)
5042     return print_insn_mips16 (memaddr, info);
5043 #endif
5044
5045 #if SYMTAB_AVAILABLE
5046   if (info->mach == bfd_mach_mips16
5047       || (info->flavour == bfd_target_elf_flavour
5048           && info->symbols != NULL
5049           && ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other
5050               == STO_MIPS16)))
5051     return print_insn_mips16 (memaddr, info);
5052 #endif
5053 #endif
5054
5055   status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info);
5056   if (status == 0)
5057     {
5058       unsigned long insn;
5059
5060       if (endianness == BFD_ENDIAN_BIG)
5061         insn = (unsigned long) bfd_getb32 (buffer);
5062       else
5063         insn = (unsigned long) bfd_getl32 (buffer);
5064
5065       return print_insn_mips (memaddr, insn, info);
5066     }
5067   else
5068     {
5069       (*info->memory_error_func) (status, memaddr, info);
5070       return -1;
5071     }
5072 }
5073
5074 int
5075 print_insn_big_mips (bfd_vma memaddr, struct disassemble_info *info)
5076 {
5077   return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG);
5078 }
5079
5080 int
5081 print_insn_little_mips (bfd_vma memaddr, struct disassemble_info *info)
5082 {
5083   return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE);
5084 }
5085 \f
5086 /* Disassemble mips16 instructions.  */
5087 #if 0
5088 static int
5089 print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
5090 {
5091   int status;
5092   bfd_byte buffer[2];
5093   int length;
5094   int insn;
5095   bfd_boolean use_extend;
5096   int extend = 0;
5097   const struct mips_opcode *op, *opend;
5098
5099   info->bytes_per_chunk = 2;
5100   info->display_endian = info->endian;
5101   info->insn_info_valid = 1;
5102   info->branch_delay_insns = 0;
5103   info->data_size = 0;
5104   info->insn_type = dis_nonbranch;
5105   info->target = 0;
5106   info->target2 = 0;
5107
5108   status = (*info->read_memory_func) (memaddr, buffer, 2, info);
5109   if (status != 0)
5110     {
5111       (*info->memory_error_func) (status, memaddr, info);
5112       return -1;
5113     }
5114
5115   length = 2;
5116
5117   if (info->endian == BFD_ENDIAN_BIG)
5118     insn = bfd_getb16 (buffer);
5119   else
5120     insn = bfd_getl16 (buffer);
5121
5122   /* Handle the extend opcode specially.  */
5123   use_extend = FALSE;
5124   if ((insn & 0xf800) == 0xf000)
5125     {
5126       use_extend = TRUE;
5127       extend = insn & 0x7ff;
5128
5129       memaddr += 2;
5130
5131       status = (*info->read_memory_func) (memaddr, buffer, 2, info);
5132       if (status != 0)
5133         {
5134           (*info->fprintf_func) (info->stream, "extend 0x%x",
5135                                  (unsigned int) extend);
5136           (*info->memory_error_func) (status, memaddr, info);
5137           return -1;
5138         }
5139
5140       if (info->endian == BFD_ENDIAN_BIG)
5141         insn = bfd_getb16 (buffer);
5142       else
5143         insn = bfd_getl16 (buffer);
5144
5145       /* Check for an extend opcode followed by an extend opcode.  */
5146       if ((insn & 0xf800) == 0xf000)
5147         {
5148           (*info->fprintf_func) (info->stream, "extend 0x%x",
5149                                  (unsigned int) extend);
5150           info->insn_type = dis_noninsn;
5151           return length;
5152         }
5153
5154       length += 2;
5155     }
5156
5157   /* FIXME: Should probably use a hash table on the major opcode here.  */
5158
5159   opend = mips16_opcodes + bfd_mips16_num_opcodes;
5160   for (op = mips16_opcodes; op < opend; op++)
5161     {
5162       if (op->pinfo != INSN_MACRO
5163           && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
5164           && (insn & op->mask) == op->match)
5165         {
5166           const char *s;
5167
5168           if (strchr (op->args, 'a') != NULL)
5169             {
5170               if (use_extend)
5171                 {
5172                   (*info->fprintf_func) (info->stream, "extend 0x%x",
5173                                          (unsigned int) extend);
5174                   info->insn_type = dis_noninsn;
5175                   return length - 2;
5176                 }
5177
5178               use_extend = FALSE;
5179
5180               memaddr += 2;
5181
5182               status = (*info->read_memory_func) (memaddr, buffer, 2,
5183                                                   info);
5184               if (status == 0)
5185                 {
5186                   use_extend = TRUE;
5187                   if (info->endian == BFD_ENDIAN_BIG)
5188                     extend = bfd_getb16 (buffer);
5189                   else
5190                     extend = bfd_getl16 (buffer);
5191                   length += 2;
5192                 }
5193             }
5194
5195           (*info->fprintf_func) (info->stream, "%s", op->name);
5196           if (op->args[0] != '\0')
5197             (*info->fprintf_func) (info->stream, "\t");
5198
5199           for (s = op->args; *s != '\0'; s++)
5200             {
5201               if (*s == ','
5202                   && s[1] == 'w'
5203                   && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)
5204                       == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY)))
5205                 {
5206                   /* Skip the register and the comma.  */
5207                   ++s;
5208                   continue;
5209                 }
5210               if (*s == ','
5211                   && s[1] == 'v'
5212                   && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ)
5213                       == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)))
5214                 {
5215                   /* Skip the register and the comma.  */
5216                   ++s;
5217                   continue;
5218                 }
5219               print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr,
5220                                      info);
5221             }
5222
5223           if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
5224             {
5225               info->branch_delay_insns = 1;
5226               if (info->insn_type != dis_jsr)
5227                 info->insn_type = dis_branch;
5228             }
5229
5230           return length;
5231         }
5232     }
5233
5234   if (use_extend)
5235     (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000);
5236   (*info->fprintf_func) (info->stream, "0x%x", insn);
5237   info->insn_type = dis_noninsn;
5238
5239   return length;
5240 }
5241
5242 /* Disassemble an operand for a mips16 instruction.  */
5243
5244 static void
5245 print_mips16_insn_arg (char type,
5246                        const struct mips_opcode *op,
5247                        int l,
5248                        bfd_boolean use_extend,
5249                        int extend,
5250                        bfd_vma memaddr,
5251                        struct disassemble_info *info)
5252 {
5253   switch (type)
5254     {
5255     case ',':
5256     case '(':
5257     case ')':
5258       (*info->fprintf_func) (info->stream, "%c", type);
5259       break;
5260
5261     case 'y':
5262     case 'w':
5263       (*info->fprintf_func) (info->stream, "%s",
5264                              mips16_reg_names(((l >> MIPS16OP_SH_RY)
5265                                                & MIPS16OP_MASK_RY)));
5266       break;
5267
5268     case 'x':
5269     case 'v':
5270       (*info->fprintf_func) (info->stream, "%s",
5271                              mips16_reg_names(((l >> MIPS16OP_SH_RX)
5272                                                & MIPS16OP_MASK_RX)));
5273       break;
5274
5275     case 'z':
5276       (*info->fprintf_func) (info->stream, "%s",
5277                              mips16_reg_names(((l >> MIPS16OP_SH_RZ)
5278                                                & MIPS16OP_MASK_RZ)));
5279       break;
5280
5281     case 'Z':
5282       (*info->fprintf_func) (info->stream, "%s",
5283                              mips16_reg_names(((l >> MIPS16OP_SH_MOVE32Z)
5284                                                & MIPS16OP_MASK_MOVE32Z)));
5285       break;
5286
5287     case '0':
5288       (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
5289       break;
5290
5291     case 'S':
5292       (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[29]);
5293       break;
5294
5295     case 'P':
5296       (*info->fprintf_func) (info->stream, "$pc");
5297       break;
5298
5299     case 'R':
5300       (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[31]);
5301       break;
5302
5303     case 'X':
5304       (*info->fprintf_func) (info->stream, "%s",
5305                              mips_gpr_names[((l >> MIPS16OP_SH_REGR32)
5306                                             & MIPS16OP_MASK_REGR32)]);
5307       break;
5308
5309     case 'Y':
5310       (*info->fprintf_func) (info->stream, "%s",
5311                              mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]);
5312       break;
5313
5314     case '<':
5315     case '>':
5316     case '[':
5317     case ']':
5318     case '4':
5319     case '5':
5320     case 'H':
5321     case 'W':
5322     case 'D':
5323     case 'j':
5324     case '6':
5325     case '8':
5326     case 'V':
5327     case 'C':
5328     case 'U':
5329     case 'k':
5330     case 'K':
5331     case 'p':
5332     case 'q':
5333     case 'A':
5334     case 'B':
5335     case 'E':
5336       {
5337         int immed, nbits, shift, signedp, extbits, pcrel, extu, branch;
5338
5339         shift = 0;
5340         signedp = 0;
5341         extbits = 16;
5342         pcrel = 0;
5343         extu = 0;
5344         branch = 0;
5345         switch (type)
5346           {
5347           case '<':
5348             nbits = 3;
5349             immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
5350             extbits = 5;
5351             extu = 1;
5352             break;
5353           case '>':
5354             nbits = 3;
5355             immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
5356             extbits = 5;
5357             extu = 1;
5358             break;
5359           case '[':
5360             nbits = 3;
5361             immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
5362             extbits = 6;
5363             extu = 1;
5364             break;
5365           case ']':
5366             nbits = 3;
5367             immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
5368             extbits = 6;
5369             extu = 1;
5370             break;
5371           case '4':
5372             nbits = 4;
5373             immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4;
5374             signedp = 1;
5375             extbits = 15;
5376             break;
5377           case '5':
5378             nbits = 5;
5379             immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
5380             info->insn_type = dis_dref;
5381             info->data_size = 1;
5382             break;
5383           case 'H':
5384             nbits = 5;
5385             shift = 1;
5386             immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
5387             info->insn_type = dis_dref;
5388             info->data_size = 2;
5389             break;
5390           case 'W':
5391             nbits = 5;
5392             shift = 2;
5393             immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
5394             if ((op->pinfo & MIPS16_INSN_READ_PC) == 0
5395                 && (op->pinfo & MIPS16_INSN_READ_SP) == 0)
5396               {
5397                 info->insn_type = dis_dref;
5398                 info->data_size = 4;
5399               }
5400             break;
5401           case 'D':
5402             nbits = 5;
5403             shift = 3;
5404             immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
5405             info->insn_type = dis_dref;
5406             info->data_size = 8;
5407             break;
5408           case 'j':
5409             nbits = 5;
5410             immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
5411             signedp = 1;
5412             break;
5413           case '6':
5414             nbits = 6;
5415             immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
5416             break;
5417           case '8':
5418             nbits = 8;
5419             immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
5420             break;
5421           case 'V':
5422             nbits = 8;
5423             shift = 2;
5424             immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
5425             /* FIXME: This might be lw, or it might be addiu to $sp or
5426                $pc.  We assume it's load.  */
5427             info->insn_type = dis_dref;
5428             info->data_size = 4;
5429             break;
5430           case 'C':
5431             nbits = 8;
5432             shift = 3;
5433             immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
5434             info->insn_type = dis_dref;
5435             info->data_size = 8;
5436             break;
5437           case 'U':
5438             nbits = 8;
5439             immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
5440             extu = 1;
5441             break;
5442           case 'k':
5443             nbits = 8;
5444             immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
5445             signedp = 1;
5446             break;
5447           case 'K':
5448             nbits = 8;
5449             shift = 3;
5450             immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
5451             signedp = 1;
5452             break;
5453           case 'p':
5454             nbits = 8;
5455             immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
5456             signedp = 1;
5457             pcrel = 1;
5458             branch = 1;
5459             info->insn_type = dis_condbranch;
5460             break;
5461           case 'q':
5462             nbits = 11;
5463             immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11;
5464             signedp = 1;
5465             pcrel = 1;
5466             branch = 1;
5467             info->insn_type = dis_branch;
5468             break;
5469           case 'A':
5470             nbits = 8;
5471             shift = 2;
5472             immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
5473             pcrel = 1;
5474             /* FIXME: This can be lw or la.  We assume it is lw.  */
5475             info->insn_type = dis_dref;
5476             info->data_size = 4;
5477             break;
5478           case 'B':
5479             nbits = 5;
5480             shift = 3;
5481             immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
5482             pcrel = 1;
5483             info->insn_type = dis_dref;
5484             info->data_size = 8;
5485             break;
5486           case 'E':
5487             nbits = 5;
5488             shift = 2;
5489             immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
5490             pcrel = 1;
5491             break;
5492           default:
5493             abort ();
5494           }
5495
5496         if (! use_extend)
5497           {
5498             if (signedp && immed >= (1 << (nbits - 1)))
5499               immed -= 1 << nbits;
5500             immed <<= shift;
5501             if ((type == '<' || type == '>' || type == '[' || type == ']')
5502                 && immed == 0)
5503               immed = 8;
5504           }
5505         else
5506           {
5507             if (extbits == 16)
5508               immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0);
5509             else if (extbits == 15)
5510               immed |= ((extend & 0xf) << 11) | (extend & 0x7f0);
5511             else
5512               immed = ((extend >> 6) & 0x1f) | (extend & 0x20);
5513             immed &= (1 << extbits) - 1;
5514             if (! extu && immed >= (1 << (extbits - 1)))
5515               immed -= 1 << extbits;
5516           }
5517
5518         if (! pcrel)
5519           (*info->fprintf_func) (info->stream, "%d", immed);
5520         else
5521           {
5522             bfd_vma baseaddr;
5523
5524             if (branch)
5525               {
5526                 immed *= 2;
5527                 baseaddr = memaddr + 2;
5528               }
5529             else if (use_extend)
5530               baseaddr = memaddr - 2;
5531             else
5532               {
5533                 int status;
5534                 bfd_byte buffer[2];
5535
5536                 baseaddr = memaddr;
5537
5538                 /* If this instruction is in the delay slot of a jr
5539                    instruction, the base address is the address of the
5540                    jr instruction.  If it is in the delay slot of jalr
5541                    instruction, the base address is the address of the
5542                    jalr instruction.  This test is unreliable: we have
5543                    no way of knowing whether the previous word is
5544                    instruction or data.  */
5545                 status = (*info->read_memory_func) (memaddr - 4, buffer, 2,
5546                                                     info);
5547                 if (status == 0
5548                     && (((info->endian == BFD_ENDIAN_BIG
5549                           ? bfd_getb16 (buffer)
5550                           : bfd_getl16 (buffer))
5551                          & 0xf800) == 0x1800))
5552                   baseaddr = memaddr - 4;
5553                 else
5554                   {
5555                     status = (*info->read_memory_func) (memaddr - 2, buffer,
5556                                                         2, info);
5557                     if (status == 0
5558                         && (((info->endian == BFD_ENDIAN_BIG
5559                               ? bfd_getb16 (buffer)
5560                               : bfd_getl16 (buffer))
5561                              & 0xf81f) == 0xe800))
5562                       baseaddr = memaddr - 2;
5563                   }
5564               }
5565             info->target = (baseaddr & ~((1 << shift) - 1)) + immed;
5566             if (pcrel && branch
5567                 && info->flavour == bfd_target_unknown_flavour)
5568               /* For gdb disassembler, maintain odd address.  */
5569               info->target |= 1;
5570             (*info->print_address_func) (info->target, info);
5571           }
5572       }
5573       break;
5574
5575     case 'a':
5576       {
5577         int jalx = l & 0x400;
5578
5579         if (! use_extend)
5580           extend = 0;
5581         l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2);
5582         if (!jalx && info->flavour == bfd_target_unknown_flavour)
5583           /* For gdb disassembler, maintain odd address.  */
5584           l |= 1;
5585       }
5586       info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l;
5587       (*info->print_address_func) (info->target, info);
5588       info->insn_type = dis_jsr;
5589       info->branch_delay_insns = 1;
5590       break;
5591
5592     case 'l':
5593     case 'L':
5594       {
5595         int need_comma, amask, smask;
5596
5597         need_comma = 0;
5598
5599         l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
5600
5601         amask = (l >> 3) & 7;
5602
5603         if (amask > 0 && amask < 5)
5604           {
5605             (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
5606             if (amask > 1)
5607               (*info->fprintf_func) (info->stream, "-%s",
5608                                      mips_gpr_names[amask + 3]);
5609             need_comma = 1;
5610           }
5611
5612         smask = (l >> 1) & 3;
5613         if (smask == 3)
5614           {
5615             (*info->fprintf_func) (info->stream, "%s??",
5616                                    need_comma ? "," : "");
5617             need_comma = 1;
5618           }
5619         else if (smask > 0)
5620           {
5621             (*info->fprintf_func) (info->stream, "%s%s",
5622                                    need_comma ? "," : "",
5623                                    mips_gpr_names[16]);
5624             if (smask > 1)
5625               (*info->fprintf_func) (info->stream, "-%s",
5626                                      mips_gpr_names[smask + 15]);
5627             need_comma = 1;
5628           }
5629
5630         if (l & 1)
5631           {
5632             (*info->fprintf_func) (info->stream, "%s%s",
5633                                    need_comma ? "," : "",
5634                                    mips_gpr_names[31]);
5635             need_comma = 1;
5636           }
5637
5638         if (amask == 5 || amask == 6)
5639           {
5640             (*info->fprintf_func) (info->stream, "%s$f0",
5641                                    need_comma ? "," : "");
5642             if (amask == 6)
5643               (*info->fprintf_func) (info->stream, "-$f1");
5644           }
5645       }
5646       break;
5647
5648     case 'm':
5649     case 'M':
5650       /* MIPS16e save/restore.  */
5651       {
5652       int need_comma = 0;
5653       int amask, args, statics;
5654       int nsreg, smask;
5655       int framesz;
5656       int i, j;
5657
5658       l = l & 0x7f;
5659       if (use_extend)
5660         l |= extend << 16;
5661
5662       amask = (l >> 16) & 0xf;
5663       if (amask == MIPS16_ALL_ARGS)
5664         {
5665           args = 4;
5666           statics = 0;
5667         }
5668       else if (amask == MIPS16_ALL_STATICS)
5669         {
5670           args = 0;
5671           statics = 4;
5672         }
5673       else
5674         {
5675           args = amask >> 2;
5676           statics = amask & 3;
5677         }
5678
5679       if (args > 0) {
5680           (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
5681           if (args > 1)
5682             (*info->fprintf_func) (info->stream, "-%s",
5683                                    mips_gpr_names[4 + args - 1]);
5684           need_comma = 1;
5685       }
5686
5687       framesz = (((l >> 16) & 0xf0) | (l & 0x0f)) * 8;
5688       if (framesz == 0 && !use_extend)
5689         framesz = 128;
5690
5691       (*info->fprintf_func) (info->stream, "%s%d",
5692                              need_comma ? "," : "",
5693                              framesz);
5694
5695       if (l & 0x40)                   /* $ra */
5696         (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[31]);
5697
5698       nsreg = (l >> 24) & 0x7;
5699       smask = 0;
5700       if (l & 0x20)                   /* $s0 */
5701         smask |= 1 << 0;
5702       if (l & 0x10)                   /* $s1 */
5703         smask |= 1 << 1;
5704       if (nsreg > 0)                  /* $s2-$s8 */
5705         smask |= ((1 << nsreg) - 1) << 2;
5706
5707       /* Find first set static reg bit.  */
5708       for (i = 0; i < 9; i++)
5709         {
5710           if (smask & (1 << i))
5711             {
5712               (*info->fprintf_func) (info->stream, ",%s",
5713                                      mips_gpr_names[i == 8 ? 30 : (16 + i)]);
5714               /* Skip over string of set bits.  */
5715               for (j = i; smask & (2 << j); j++)
5716                 continue;
5717               if (j > i)
5718                 (*info->fprintf_func) (info->stream, "-%s",
5719                                        mips_gpr_names[j == 8 ? 30 : (16 + j)]);
5720               i = j + 1;
5721             }
5722         }
5723
5724       /* Statics $ax - $a3.  */
5725       if (statics == 1)
5726         (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[7]);
5727       else if (statics > 0)
5728         (*info->fprintf_func) (info->stream, ",%s-%s",
5729                                mips_gpr_names[7 - statics + 1],
5730                                mips_gpr_names[7]);
5731       }
5732       break;
5733
5734     default:
5735       /* xgettext:c-format */
5736       (*info->fprintf_func)
5737         (info->stream,
5738          _("# internal disassembler error, unrecognised modifier (%c)"),
5739          type);
5740       abort ();
5741     }
5742 }
5743
5744 void
5745 print_mips_disassembler_options (FILE *stream)
5746 {
5747   unsigned int i;
5748
5749   fprintf (stream, _("\n\
5750 The following MIPS specific disassembler options are supported for use\n\
5751 with the -M switch (multiple options should be separated by commas):\n"));
5752
5753   fprintf (stream, _("\n\
5754   gpr-names=ABI            Print GPR names according to  specified ABI.\n\
5755                            Default: based on binary being disassembled.\n"));
5756
5757   fprintf (stream, _("\n\
5758   fpr-names=ABI            Print FPR names according to specified ABI.\n\
5759                            Default: numeric.\n"));
5760
5761   fprintf (stream, _("\n\
5762   cp0-names=ARCH           Print CP0 register names according to\n\
5763                            specified architecture.\n\
5764                            Default: based on binary being disassembled.\n"));
5765
5766   fprintf (stream, _("\n\
5767   hwr-names=ARCH           Print HWR names according to specified\n\
5768                            architecture.\n\
5769                            Default: based on binary being disassembled.\n"));
5770
5771   fprintf (stream, _("\n\
5772   reg-names=ABI            Print GPR and FPR names according to\n\
5773                            specified ABI.\n"));
5774
5775   fprintf (stream, _("\n\
5776   reg-names=ARCH           Print CP0 register and HWR names according to\n\
5777                            specified architecture.\n"));
5778
5779   fprintf (stream, _("\n\
5780   For the options above, the following values are supported for \"ABI\":\n\
5781    "));
5782   for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++)
5783     fprintf (stream, " %s", mips_abi_choices[i].name);
5784   fprintf (stream, _("\n"));
5785
5786   fprintf (stream, _("\n\
5787   For the options above, The following values are supported for \"ARCH\":\n\
5788    "));
5789   for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++)
5790     if (*mips_arch_choices[i].name != '\0')
5791       fprintf (stream, " %s", mips_arch_choices[i].name);
5792   fprintf (stream, _("\n"));
5793
5794   fprintf (stream, _("\n"));
5795 }
5796 #endif