2 * Bochs/QEMU ACPI DSDT ASL definition
4 * Copyright (c) 2006 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License version 2 as published by the Free Software Foundation.
10 * This library is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * Lesser General Public License for more details.
15 * You should have received a copy of the GNU Lesser General Public
16 * License along with this library; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * Copyright (c) 2010 Isaku Yamahata
21 * yamahata at valinux co jp
22 * Based on acpi-dsdt.dsl, but heavily modified for q35 chipset.
26 ACPI_EXTRACT_ALL_CODE Q35AcpiDsdtAmlCode
29 "q35-acpi-dsdt.aml",// Output Filename
31 0x01, // DSDT Compliance Revision
39 OperationRegion(PCST, SystemIO, 0xae00, 0x0c)
40 OperationRegion(PCSB, SystemIO, 0xae0c, 0x01)
41 Field(PCSB, AnyAcc, NoLock, WriteAsZeros) {
47 /****************************************************************
49 ****************************************************************/
52 Name(_HID, EisaId("PNP0A08"))
53 Name(_CID, EisaId("PNP0A03"))
57 External(ISA, DeviceObj)
59 // _OSC: based on sample of ACPI3.0b spec
60 Name(SUPP, 0) // PCI _OSC Support Field value
61 Name(CTRL, 0) // PCI _OSC Control Field value
63 // Create DWORD-addressable fields from the Capabilities Buffer
64 CreateDWordField(Arg3, 0, CDW1)
66 // Check for proper UUID
67 If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
68 // Create DWORD-addressable fields from the Capabilities Buffer
69 CreateDWordField(Arg3, 4, CDW2)
70 CreateDWordField(Arg3, 8, CDW3)
72 // Save Capabilities DWORD2 & 3
76 // Always allow native PME, AER (no dependencies)
77 // Never allow SHPC (no SHPC controller in this system)
80 #if 0 // For now, nothing to do
81 If (Not(And(CDW1, 1))) { // Query flag clear?
82 // Disable GPEs for features granted native control.
83 If (And(CTRL, 0x01)) { // Hot plug control granted?
84 Store(0, HPCE) // clear the hot plug SCI enable bit
85 Store(1, HPCS) // clear the hot plug SCI status bit
87 If (And(CTRL, 0x04)) { // PME control granted?
88 Store(0, PMCE) // clear the PME SCI enable bit
89 Store(1, PMCS) // clear the PME SCI status bit
91 If (And(CTRL, 0x10)) { // OS restoring PCI Express cap structure?
92 // Set status to not restore PCI Express cap structure
93 // upon resume from S3
98 If (LNotEqual(Arg1, One)) {
102 If (LNotEqual(CDW3, CTRL)) {
103 // Capabilities bits were masked
106 // Update DWORD3 in the buffer
109 Or(CDW1, 4, CDW1) // Unrecognized UUID
116 /****************************************************************
118 ****************************************************************/
120 /* Zero => PIC mode, One => APIC Mode */
122 Method(\_PIC, 1, NotSerialized) {
128 #define prt_slot_lnk(nr, lnk0, lnk1, lnk2, lnk3) \
129 Package() { nr##ffff, 0, lnk0, 0 }, \
130 Package() { nr##ffff, 1, lnk1, 0 }, \
131 Package() { nr##ffff, 2, lnk2, 0 }, \
132 Package() { nr##ffff, 3, lnk3, 0 }
134 #define prt_slot_lnkA(nr) prt_slot_lnk(nr, LNKA, LNKB, LNKC, LNKD)
135 #define prt_slot_lnkB(nr) prt_slot_lnk(nr, LNKB, LNKC, LNKD, LNKA)
136 #define prt_slot_lnkC(nr) prt_slot_lnk(nr, LNKC, LNKD, LNKA, LNKB)
137 #define prt_slot_lnkD(nr) prt_slot_lnk(nr, LNKD, LNKA, LNKB, LNKC)
139 #define prt_slot_lnkE(nr) prt_slot_lnk(nr, LNKE, LNKF, LNKG, LNKH)
140 #define prt_slot_lnkF(nr) prt_slot_lnk(nr, LNKF, LNKG, LNKH, LNKE)
141 #define prt_slot_lnkG(nr) prt_slot_lnk(nr, LNKG, LNKH, LNKE, LNKF)
142 #define prt_slot_lnkH(nr) prt_slot_lnk(nr, LNKH, LNKE, LNKF, LNKG)
144 Name(PRTP, package() {
145 prt_slot_lnkE(0x0000),
146 prt_slot_lnkF(0x0001),
147 prt_slot_lnkG(0x0002),
148 prt_slot_lnkH(0x0003),
149 prt_slot_lnkE(0x0004),
150 prt_slot_lnkF(0x0005),
151 prt_slot_lnkG(0x0006),
152 prt_slot_lnkH(0x0007),
153 prt_slot_lnkE(0x0008),
154 prt_slot_lnkF(0x0009),
155 prt_slot_lnkG(0x000a),
156 prt_slot_lnkH(0x000b),
157 prt_slot_lnkE(0x000c),
158 prt_slot_lnkF(0x000d),
159 prt_slot_lnkG(0x000e),
160 prt_slot_lnkH(0x000f),
161 prt_slot_lnkE(0x0010),
162 prt_slot_lnkF(0x0011),
163 prt_slot_lnkG(0x0012),
164 prt_slot_lnkH(0x0013),
165 prt_slot_lnkE(0x0014),
166 prt_slot_lnkF(0x0015),
167 prt_slot_lnkG(0x0016),
168 prt_slot_lnkH(0x0017),
169 prt_slot_lnkE(0x0018),
171 /* INTA -> PIRQA for slot 25 - 31
172 see the default value of D<N>IR */
173 prt_slot_lnkA(0x0019),
174 prt_slot_lnkA(0x001a),
175 prt_slot_lnkA(0x001b),
176 prt_slot_lnkA(0x001c),
177 prt_slot_lnkA(0x001d),
179 /* PCIe->PCI bridge. use PIRQ[E-H] */
180 prt_slot_lnkE(0x001e),
182 prt_slot_lnkA(0x001f)
185 #define prt_slot_gsi(nr, gsi0, gsi1, gsi2, gsi3) \
186 Package() { nr##ffff, 0, gsi0, 0 }, \
187 Package() { nr##ffff, 1, gsi1, 0 }, \
188 Package() { nr##ffff, 2, gsi2, 0 }, \
189 Package() { nr##ffff, 3, gsi3, 0 }
191 #define prt_slot_gsiA(nr) prt_slot_gsi(nr, GSIA, GSIB, GSIC, GSID)
192 #define prt_slot_gsiB(nr) prt_slot_gsi(nr, GSIB, GSIC, GSID, GSIA)
193 #define prt_slot_gsiC(nr) prt_slot_gsi(nr, GSIC, GSID, GSIA, GSIB)
194 #define prt_slot_gsiD(nr) prt_slot_gsi(nr, GSID, GSIA, GSIB, GSIC)
196 #define prt_slot_gsiE(nr) prt_slot_gsi(nr, GSIE, GSIF, GSIG, GSIH)
197 #define prt_slot_gsiF(nr) prt_slot_gsi(nr, GSIF, GSIG, GSIH, GSIE)
198 #define prt_slot_gsiG(nr) prt_slot_gsi(nr, GSIG, GSIH, GSIE, GSIF)
199 #define prt_slot_gsiH(nr) prt_slot_gsi(nr, GSIH, GSIE, GSIF, GSIG)
201 Name(PRTA, package() {
202 prt_slot_gsiE(0x0000),
203 prt_slot_gsiF(0x0001),
204 prt_slot_gsiG(0x0002),
205 prt_slot_gsiH(0x0003),
206 prt_slot_gsiE(0x0004),
207 prt_slot_gsiF(0x0005),
208 prt_slot_gsiG(0x0006),
209 prt_slot_gsiH(0x0007),
210 prt_slot_gsiE(0x0008),
211 prt_slot_gsiF(0x0009),
212 prt_slot_gsiG(0x000a),
213 prt_slot_gsiH(0x000b),
214 prt_slot_gsiE(0x000c),
215 prt_slot_gsiF(0x000d),
216 prt_slot_gsiG(0x000e),
217 prt_slot_gsiH(0x000f),
218 prt_slot_gsiE(0x0010),
219 prt_slot_gsiF(0x0011),
220 prt_slot_gsiG(0x0012),
221 prt_slot_gsiH(0x0013),
222 prt_slot_gsiE(0x0014),
223 prt_slot_gsiF(0x0015),
224 prt_slot_gsiG(0x0016),
225 prt_slot_gsiH(0x0017),
226 prt_slot_gsiE(0x0018),
228 /* INTA -> PIRQA for slot 25 - 31, but 30
229 see the default value of D<N>IR */
230 prt_slot_gsiA(0x0019),
231 prt_slot_gsiA(0x001a),
232 prt_slot_gsiA(0x001b),
233 prt_slot_gsiA(0x001c),
234 prt_slot_gsiA(0x001d),
236 /* PCIe->PCI bridge. use PIRQ[E-H] */
237 prt_slot_gsiE(0x001e),
239 prt_slot_gsiA(0x001f)
242 Method(_PRT, 0, NotSerialized) {
243 /* PCI IRQ routing table, example from ACPI 2.0a specification,
245 /* Note: we provide the same info as the PCI routing
246 table of the Bochs BIOS */
247 If (LEqual(\PICF, Zero)) {
255 External(LNKA, DeviceObj)
256 External(LNKB, DeviceObj)
257 External(LNKC, DeviceObj)
258 External(LNKD, DeviceObj)
259 External(LNKE, DeviceObj)
260 External(LNKF, DeviceObj)
261 External(LNKG, DeviceObj)
262 External(LNKH, DeviceObj)
264 External(GSIA, DeviceObj)
265 External(GSIB, DeviceObj)
266 External(GSIC, DeviceObj)
267 External(GSID, DeviceObj)
268 External(GSIE, DeviceObj)
269 External(GSIF, DeviceObj)
270 External(GSIG, DeviceObj)
271 External(GSIH, DeviceObj)