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pc: acpi: q35: move ISA bridge into SSDT
[qemu.git] / hw / i386 / acpi-build.c
blob103a08f3bd7ef837f2f0d6ccca0497ed0ee4e48b
1 /* Support for generating ACPI tables and passing them to Guests
2 *
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
6 *
7 * Author: Michael S. Tsirkin <mst@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #include "acpi-build.h"
24 #include <stddef.h>
25 #include <glib.h>
26 #include "qemu-common.h"
27 #include "qemu/bitmap.h"
28 #include "qemu/osdep.h"
29 #include "qemu/error-report.h"
30 #include "hw/pci/pci.h"
31 #include "qom/cpu.h"
32 #include "hw/i386/pc.h"
33 #include "target-i386/cpu.h"
34 #include "hw/timer/hpet.h"
35 #include "hw/acpi/acpi-defs.h"
36 #include "hw/acpi/acpi.h"
37 #include "hw/nvram/fw_cfg.h"
38 #include "hw/acpi/bios-linker-loader.h"
39 #include "hw/loader.h"
40 #include "hw/isa/isa.h"
41 #include "hw/acpi/memory_hotplug.h"
42 #include "hw/mem/nvdimm.h"
43 #include "sysemu/tpm.h"
44 #include "hw/acpi/tpm.h"
45 #include "sysemu/tpm_backend.h"
46 #include "hw/timer/mc146818rtc_regs.h"
47
48 /* Supported chipsets: */
49 #include "hw/acpi/piix4.h"
50 #include "hw/acpi/pcihp.h"
51 #include "hw/i386/ich9.h"
52 #include "hw/pci/pci_bus.h"
53 #include "hw/pci-host/q35.h"
54 #include "hw/i386/intel_iommu.h"
55 #include "hw/timer/hpet.h"
56
57 #include "hw/i386/q35-acpi-dsdt.hex"
58 #include "hw/i386/acpi-dsdt.hex"
59
60 #include "hw/acpi/aml-build.h"
61
62 #include "qapi/qmp/qint.h"
63 #include "qom/qom-qobject.h"
64
65 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
66 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
67 * a little bit, there should be plenty of free space since the DSDT
68 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
69 */
70 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
71 #define ACPI_BUILD_ALIGN_SIZE 0x1000
72
73 #define ACPI_BUILD_TABLE_SIZE 0x20000
74
75 /* #define DEBUG_ACPI_BUILD */
76 #ifdef DEBUG_ACPI_BUILD
77 #define ACPI_BUILD_DPRINTF(fmt, ...) \
78 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
79 #else
80 #define ACPI_BUILD_DPRINTF(fmt, ...)
81 #endif
82
83 typedef struct AcpiCpuInfo {
84 DECLARE_BITMAP(found_cpus, ACPI_CPU_HOTPLUG_ID_LIMIT);
85 } AcpiCpuInfo;
86
87 typedef struct AcpiMcfgInfo {
88 uint64_t mcfg_base;
89 uint32_t mcfg_size;
90 } AcpiMcfgInfo;
91
92 typedef struct AcpiPmInfo {
93 bool s3_disabled;
94 bool s4_disabled;
95 bool pcihp_bridge_en;
96 uint8_t s4_val;
97 uint16_t sci_int;
98 uint8_t acpi_enable_cmd;
99 uint8_t acpi_disable_cmd;
100 uint32_t gpe0_blk;
101 uint32_t gpe0_blk_len;
102 uint32_t io_base;
103 uint16_t cpu_hp_io_base;
104 uint16_t cpu_hp_io_len;
105 uint16_t mem_hp_io_base;
106 uint16_t mem_hp_io_len;
107 uint16_t pcihp_io_base;
108 uint16_t pcihp_io_len;
109 } AcpiPmInfo;
110
111 typedef struct AcpiMiscInfo {
112 bool is_piix4;
113 bool has_hpet;
114 TPMVersion tpm_version;
115 const unsigned char *dsdt_code;
116 unsigned dsdt_size;
117 uint16_t pvpanic_port;
118 uint16_t applesmc_io_base;
119 } AcpiMiscInfo;
120
121 typedef struct AcpiBuildPciBusHotplugState {
122 GArray *device_table;
123 GArray *notify_table;
124 struct AcpiBuildPciBusHotplugState *parent;
125 bool pcihp_bridge_en;
126 } AcpiBuildPciBusHotplugState;
127
128 static void acpi_get_dsdt(AcpiMiscInfo *info)
129 {
130 Object *piix = piix4_pm_find();
131 Object *lpc = ich9_lpc_find();
132 assert(!!piix != !!lpc);
133
134 if (piix) {
135 info->is_piix4 = true;
136 info->dsdt_code = AcpiDsdtAmlCode;
137 info->dsdt_size = sizeof AcpiDsdtAmlCode;
138 }
139 if (lpc) {
140 info->is_piix4 = false;
141 info->dsdt_code = Q35AcpiDsdtAmlCode;
142 info->dsdt_size = sizeof Q35AcpiDsdtAmlCode;
143 }
144 }
145
146 static
147 int acpi_add_cpu_info(Object *o, void *opaque)
148 {
149 AcpiCpuInfo *cpu = opaque;
150 uint64_t apic_id;
151
152 if (object_dynamic_cast(o, TYPE_CPU)) {
153 apic_id = object_property_get_int(o, "apic-id", NULL);
154 assert(apic_id < ACPI_CPU_HOTPLUG_ID_LIMIT);
155
156 set_bit(apic_id, cpu->found_cpus);
157 }
158
159 object_child_foreach(o, acpi_add_cpu_info, opaque);
160 return 0;
161 }
162
163 static void acpi_get_cpu_info(AcpiCpuInfo *cpu)
164 {
165 Object *root = object_get_root();
166
167 memset(cpu->found_cpus, 0, sizeof cpu->found_cpus);
168 object_child_foreach(root, acpi_add_cpu_info, cpu);
169 }
170
171 static void acpi_get_pm_info(AcpiPmInfo *pm)
172 {
173 Object *piix = piix4_pm_find();
174 Object *lpc = ich9_lpc_find();
175 Object *obj = NULL;
176 QObject *o;
177
178 pm->cpu_hp_io_base = 0;
179 pm->pcihp_io_base = 0;
180 pm->pcihp_io_len = 0;
181 if (piix) {
182 obj = piix;
183 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
184 pm->pcihp_io_base =
185 object_property_get_int(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
186 pm->pcihp_io_len =
187 object_property_get_int(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
188 }
189 if (lpc) {
190 obj = lpc;
191 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
192 }
193 assert(obj);
194
195 pm->cpu_hp_io_len = ACPI_GPE_PROC_LEN;
196 pm->mem_hp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
197 pm->mem_hp_io_len = ACPI_MEMORY_HOTPLUG_IO_LEN;
198
199 /* Fill in optional s3/s4 related properties */
200 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
201 if (o) {
202 pm->s3_disabled = qint_get_int(qobject_to_qint(o));
203 } else {
204 pm->s3_disabled = false;
205 }
206 qobject_decref(o);
207 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL);
208 if (o) {
209 pm->s4_disabled = qint_get_int(qobject_to_qint(o));
210 } else {
211 pm->s4_disabled = false;
212 }
213 qobject_decref(o);
214 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL);
215 if (o) {
216 pm->s4_val = qint_get_int(qobject_to_qint(o));
217 } else {
218 pm->s4_val = false;
219 }
220 qobject_decref(o);
221
222 /* Fill in mandatory properties */
223 pm->sci_int = object_property_get_int(obj, ACPI_PM_PROP_SCI_INT, NULL);
224
225 pm->acpi_enable_cmd = object_property_get_int(obj,
226 ACPI_PM_PROP_ACPI_ENABLE_CMD,
227 NULL);
228 pm->acpi_disable_cmd = object_property_get_int(obj,
229 ACPI_PM_PROP_ACPI_DISABLE_CMD,
230 NULL);
231 pm->io_base = object_property_get_int(obj, ACPI_PM_PROP_PM_IO_BASE,
232 NULL);
233 pm->gpe0_blk = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK,
234 NULL);
235 pm->gpe0_blk_len = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK_LEN,
236 NULL);
237 pm->pcihp_bridge_en =
238 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support",
239 NULL);
240 }
241
242 static void acpi_get_misc_info(AcpiMiscInfo *info)
243 {
244 info->has_hpet = hpet_find();
245 info->tpm_version = tpm_get_version();
246 info->pvpanic_port = pvpanic_port();
247 info->applesmc_io_base = applesmc_port();
248 }
249
250 /*
251 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
252 * On i386 arch we only have two pci hosts, so we can look only for them.
253 */
254 static Object *acpi_get_i386_pci_host(void)
255 {
256 PCIHostState *host;
257
258 host = OBJECT_CHECK(PCIHostState,
259 object_resolve_path("/machine/i440fx", NULL),
260 TYPE_PCI_HOST_BRIDGE);
261 if (!host) {
262 host = OBJECT_CHECK(PCIHostState,
263 object_resolve_path("/machine/q35", NULL),
264 TYPE_PCI_HOST_BRIDGE);
265 }
266
267 return OBJECT(host);
268 }
269
270 static void acpi_get_pci_info(PcPciInfo *info)
271 {
272 Object *pci_host;
273
274
275 pci_host = acpi_get_i386_pci_host();
276 g_assert(pci_host);
277
278 info->w32.begin = object_property_get_int(pci_host,
279 PCI_HOST_PROP_PCI_HOLE_START,
280 NULL);
281 info->w32.end = object_property_get_int(pci_host,
282 PCI_HOST_PROP_PCI_HOLE_END,
283 NULL);
284 info->w64.begin = object_property_get_int(pci_host,
285 PCI_HOST_PROP_PCI_HOLE64_START,
286 NULL);
287 info->w64.end = object_property_get_int(pci_host,
288 PCI_HOST_PROP_PCI_HOLE64_END,
289 NULL);
290 }
291
292 #define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */
293
294 static void acpi_align_size(GArray *blob, unsigned align)
295 {
296 /* Align size to multiple of given size. This reduces the chance
297 * we need to change size in the future (breaking cross version migration).
298 */
299 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
300 }
301
302 /* FACS */
303 static void
304 build_facs(GArray *table_data, GArray *linker, PcGuestInfo *guest_info)
305 {
306 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs);
307 memcpy(&facs->signature, "FACS", 4);
308 facs->length = cpu_to_le32(sizeof(*facs));
309 }
310
311 /* Load chipset information in FADT */
312 static void fadt_setup(AcpiFadtDescriptorRev1 *fadt, AcpiPmInfo *pm)
313 {
314 fadt->model = 1;
315 fadt->reserved1 = 0;
316 fadt->sci_int = cpu_to_le16(pm->sci_int);
317 fadt->smi_cmd = cpu_to_le32(ACPI_PORT_SMI_CMD);
318 fadt->acpi_enable = pm->acpi_enable_cmd;
319 fadt->acpi_disable = pm->acpi_disable_cmd;
320 /* EVT, CNT, TMR offset matches hw/acpi/core.c */
321 fadt->pm1a_evt_blk = cpu_to_le32(pm->io_base);
322 fadt->pm1a_cnt_blk = cpu_to_le32(pm->io_base + 0x04);
323 fadt->pm_tmr_blk = cpu_to_le32(pm->io_base + 0x08);
324 fadt->gpe0_blk = cpu_to_le32(pm->gpe0_blk);
325 /* EVT, CNT, TMR length matches hw/acpi/core.c */
326 fadt->pm1_evt_len = 4;
327 fadt->pm1_cnt_len = 2;
328 fadt->pm_tmr_len = 4;
329 fadt->gpe0_blk_len = pm->gpe0_blk_len;
330 fadt->plvl2_lat = cpu_to_le16(0xfff); /* C2 state not supported */
331 fadt->plvl3_lat = cpu_to_le16(0xfff); /* C3 state not supported */
332 fadt->flags = cpu_to_le32((1 << ACPI_FADT_F_WBINVD) |
333 (1 << ACPI_FADT_F_PROC_C1) |
334 (1 << ACPI_FADT_F_SLP_BUTTON) |
335 (1 << ACPI_FADT_F_RTC_S4));
336 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK);
337 /* APIC destination mode ("Flat Logical") has an upper limit of 8 CPUs
338 * For more than 8 CPUs, "Clustered Logical" mode has to be used
339 */
340 if (max_cpus > 8) {
341 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL);
342 }
343 fadt->century = RTC_CENTURY;
344 }
345
346
347 /* FADT */
348 static void
349 build_fadt(GArray *table_data, GArray *linker, AcpiPmInfo *pm,
350 unsigned facs, unsigned dsdt)
351 {
352 AcpiFadtDescriptorRev1 *fadt = acpi_data_push(table_data, sizeof(*fadt));
353
354 fadt->firmware_ctrl = cpu_to_le32(facs);
355 /* FACS address to be filled by Guest linker */
356 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
357 ACPI_BUILD_TABLE_FILE,
358 table_data, &fadt->firmware_ctrl,
359 sizeof fadt->firmware_ctrl);
360
361 fadt->dsdt = cpu_to_le32(dsdt);
362 /* DSDT address to be filled by Guest linker */
363 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
364 ACPI_BUILD_TABLE_FILE,
365 table_data, &fadt->dsdt,
366 sizeof fadt->dsdt);
367
368 fadt_setup(fadt, pm);
369
370 build_header(linker, table_data,
371 (void *)fadt, "FACP", sizeof(*fadt), 1, NULL);
372 }
373
374 static void
375 build_madt(GArray *table_data, GArray *linker, AcpiCpuInfo *cpu,
376 PcGuestInfo *guest_info)
377 {
378 int madt_start = table_data->len;
379
380 AcpiMultipleApicTable *madt;
381 AcpiMadtIoApic *io_apic;
382 AcpiMadtIntsrcovr *intsrcovr;
383 AcpiMadtLocalNmi *local_nmi;
384 int i;
385
386 madt = acpi_data_push(table_data, sizeof *madt);
387 madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS);
388 madt->flags = cpu_to_le32(1);
389
390 for (i = 0; i < guest_info->apic_id_limit; i++) {
391 AcpiMadtProcessorApic *apic = acpi_data_push(table_data, sizeof *apic);
392 apic->type = ACPI_APIC_PROCESSOR;
393 apic->length = sizeof(*apic);
394 apic->processor_id = i;
395 apic->local_apic_id = i;
396 if (test_bit(i, cpu->found_cpus)) {
397 apic->flags = cpu_to_le32(1);
398 } else {
399 apic->flags = cpu_to_le32(0);
400 }
401 }
402 io_apic = acpi_data_push(table_data, sizeof *io_apic);
403 io_apic->type = ACPI_APIC_IO;
404 io_apic->length = sizeof(*io_apic);
405 #define ACPI_BUILD_IOAPIC_ID 0x0
406 io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID;
407 io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS);
408 io_apic->interrupt = cpu_to_le32(0);
409
410 if (guest_info->apic_xrupt_override) {
411 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
412 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
413 intsrcovr->length = sizeof(*intsrcovr);
414 intsrcovr->source = 0;
415 intsrcovr->gsi = cpu_to_le32(2);
416 intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */
417 }
418 for (i = 1; i < 16; i++) {
419 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
420 if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) {
421 /* No need for a INT source override structure. */
422 continue;
423 }
424 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
425 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
426 intsrcovr->length = sizeof(*intsrcovr);
427 intsrcovr->source = i;
428 intsrcovr->gsi = cpu_to_le32(i);
429 intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */
430 }
431
432 local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
433 local_nmi->type = ACPI_APIC_LOCAL_NMI;
434 local_nmi->length = sizeof(*local_nmi);
435 local_nmi->processor_id = 0xff; /* all processors */
436 local_nmi->flags = cpu_to_le16(0);
437 local_nmi->lint = 1; /* ACPI_LINT1 */
438
439 build_header(linker, table_data,
440 (void *)(table_data->data + madt_start), "APIC",
441 table_data->len - madt_start, 1, NULL);
442 }
443
444 /* Assign BSEL property to all buses. In the future, this can be changed
445 * to only assign to buses that support hotplug.
446 */
447 static void *acpi_set_bsel(PCIBus *bus, void *opaque)
448 {
449 unsigned *bsel_alloc = opaque;
450 unsigned *bus_bsel;
451
452 if (qbus_is_hotpluggable(BUS(bus))) {
453 bus_bsel = g_malloc(sizeof *bus_bsel);
454
455 *bus_bsel = (*bsel_alloc)++;
456 object_property_add_uint32_ptr(OBJECT(bus), ACPI_PCIHP_PROP_BSEL,
457 bus_bsel, NULL);
458 }
459
460 return bsel_alloc;
461 }
462
463 static void acpi_set_pci_info(void)
464 {
465 PCIBus *bus = find_i440fx(); /* TODO: Q35 support */
466 unsigned bsel_alloc = 0;
467
468 if (bus) {
469 /* Scan all PCI buses. Set property to enable acpi based hotplug. */
470 pci_for_each_bus_depth_first(bus, acpi_set_bsel, NULL, &bsel_alloc);
471 }
472 }
473
474 static void build_append_pcihp_notify_entry(Aml *method, int slot)
475 {
476 Aml *if_ctx;
477 int32_t devfn = PCI_DEVFN(slot, 0);
478
479 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL));
480 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1)));
481 aml_append(method, if_ctx);
482 }
483
484 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus,
485 bool pcihp_bridge_en)
486 {
487 Aml *dev, *notify_method, *method;
488 QObject *bsel;
489 PCIBus *sec;
490 int i;
491
492 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
493 if (bsel) {
494 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel));
495
496 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val)));
497 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED);
498 }
499
500 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) {
501 DeviceClass *dc;
502 PCIDeviceClass *pc;
503 PCIDevice *pdev = bus->devices[i];
504 int slot = PCI_SLOT(i);
505 bool hotplug_enabled_dev;
506 bool bridge_in_acpi;
507
508 if (!pdev) {
509 if (bsel) { /* add hotplug slots for non present devices */
510 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
511 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
512 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
513 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
514 aml_append(method,
515 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
516 );
517 aml_append(dev, method);
518 aml_append(parent_scope, dev);
519
520 build_append_pcihp_notify_entry(notify_method, slot);
521 }
522 continue;
523 }
524
525 pc = PCI_DEVICE_GET_CLASS(pdev);
526 dc = DEVICE_GET_CLASS(pdev);
527
528 /* When hotplug for bridges is enabled, bridges are
529 * described in ACPI separately (see build_pci_bus_end).
530 * In this case they aren't themselves hot-pluggable.
531 * Hotplugged bridges *are* hot-pluggable.
532 */
533 bridge_in_acpi = pc->is_bridge && pcihp_bridge_en &&
534 !DEVICE(pdev)->hotplugged;
535
536 hotplug_enabled_dev = bsel && dc->hotpluggable && !bridge_in_acpi;
537
538 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) {
539 continue;
540 }
541
542 /* start to compose PCI slot descriptor */
543 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
544 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
545
546 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) {
547 /* add VGA specific AML methods */
548 int s3d;
549
550 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) {
551 s3d = 3;
552 } else {
553 s3d = 0;
554 }
555
556 method = aml_method("_S1D", 0, AML_NOTSERIALIZED);
557 aml_append(method, aml_return(aml_int(0)));
558 aml_append(dev, method);
559
560 method = aml_method("_S2D", 0, AML_NOTSERIALIZED);
561 aml_append(method, aml_return(aml_int(0)));
562 aml_append(dev, method);
563
564 method = aml_method("_S3D", 0, AML_NOTSERIALIZED);
565 aml_append(method, aml_return(aml_int(s3d)));
566 aml_append(dev, method);
567 } else if (hotplug_enabled_dev) {
568 /* add _SUN/_EJ0 to make slot hotpluggable */
569 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
570
571 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
572 aml_append(method,
573 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
574 );
575 aml_append(dev, method);
576
577 if (bsel) {
578 build_append_pcihp_notify_entry(notify_method, slot);
579 }
580 } else if (bridge_in_acpi) {
581 /*
582 * device is coldplugged bridge,
583 * add child device descriptions into its scope
584 */
585 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
586
587 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en);
588 }
589 /* slot descriptor has been composed, add it into parent context */
590 aml_append(parent_scope, dev);
591 }
592
593 if (bsel) {
594 aml_append(parent_scope, notify_method);
595 }
596
597 /* Append PCNT method to notify about events on local and child buses.
598 * Add unconditionally for root since DSDT expects it.
599 */
600 method = aml_method("PCNT", 0, AML_NOTSERIALIZED);
601
602 /* If bus supports hotplug select it and notify about local events */
603 if (bsel) {
604 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel));
605 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM")));
606 aml_append(method,
607 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */)
608 );
609 aml_append(method,
610 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */)
611 );
612 }
613
614 /* Notify about child bus events in any case */
615 if (pcihp_bridge_en) {
616 QLIST_FOREACH(sec, &bus->child, sibling) {
617 int32_t devfn = sec->parent_dev->devfn;
618
619 aml_append(method, aml_name("^S%.02X.PCNT", devfn));
620 }
621 }
622 aml_append(parent_scope, method);
623 qobject_decref(bsel);
624 }
625
626 /**
627 * build_prt_entry:
628 * @link_name: link name for PCI route entry
629 *
630 * build AML package containing a PCI route entry for @link_name
631 */
632 static Aml *build_prt_entry(const char *link_name)
633 {
634 Aml *a_zero = aml_int(0);
635 Aml *pkg = aml_package(4);
636 aml_append(pkg, a_zero);
637 aml_append(pkg, a_zero);
638 aml_append(pkg, aml_name("%s", link_name));
639 aml_append(pkg, a_zero);
640 return pkg;
641 }
642
643 /*
644 * initialize_route - Initialize the interrupt routing rule
645 * through a specific LINK:
646 * if (lnk_idx == idx)
647 * route using link 'link_name'
648 */
649 static Aml *initialize_route(Aml *route, const char *link_name,
650 Aml *lnk_idx, int idx)
651 {
652 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx)));
653 Aml *pkg = build_prt_entry(link_name);
654
655 aml_append(if_ctx, aml_store(pkg, route));
656
657 return if_ctx;
658 }
659
660 /*
661 * build_prt - Define interrupt rounting rules
662 *
663 * Returns an array of 128 routes, one for each device,
664 * based on device location.
665 * The main goal is to equaly distribute the interrupts
666 * over the 4 existing ACPI links (works only for i440fx).
667 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]".
668 *
669 */
670 static Aml *build_prt(bool is_pci0_prt)
671 {
672 Aml *method, *while_ctx, *pin, *res;
673
674 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
675 res = aml_local(0);
676 pin = aml_local(1);
677 aml_append(method, aml_store(aml_package(128), res));
678 aml_append(method, aml_store(aml_int(0), pin));
679
680 /* while (pin < 128) */
681 while_ctx = aml_while(aml_lless(pin, aml_int(128)));
682 {
683 Aml *slot = aml_local(2);
684 Aml *lnk_idx = aml_local(3);
685 Aml *route = aml_local(4);
686
687 /* slot = pin >> 2 */
688 aml_append(while_ctx,
689 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot));
690 /* lnk_idx = (slot + pin) & 3 */
691 aml_append(while_ctx,
692 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL),
693 lnk_idx));
694
695 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */
696 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0));
697 if (is_pci0_prt) {
698 Aml *if_device_1, *if_pin_4, *else_pin_4;
699
700 /* device 1 is the power-management device, needs SCI */
701 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1)));
702 {
703 if_pin_4 = aml_if(aml_equal(pin, aml_int(4)));
704 {
705 aml_append(if_pin_4,
706 aml_store(build_prt_entry("LNKS"), route));
707 }
708 aml_append(if_device_1, if_pin_4);
709 else_pin_4 = aml_else();
710 {
711 aml_append(else_pin_4,
712 aml_store(build_prt_entry("LNKA"), route));
713 }
714 aml_append(if_device_1, else_pin_4);
715 }
716 aml_append(while_ctx, if_device_1);
717 } else {
718 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1));
719 }
720 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2));
721 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3));
722
723 /* route[0] = 0x[slot]FFFF */
724 aml_append(while_ctx,
725 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF),
726 NULL),
727 aml_index(route, aml_int(0))));
728 /* route[1] = pin & 3 */
729 aml_append(while_ctx,
730 aml_store(aml_and(pin, aml_int(3), NULL),
731 aml_index(route, aml_int(1))));
732 /* res[pin] = route */
733 aml_append(while_ctx, aml_store(route, aml_index(res, pin)));
734 /* pin++ */
735 aml_append(while_ctx, aml_increment(pin));
736 }
737 aml_append(method, while_ctx);
738 /* return res*/
739 aml_append(method, aml_return(res));
740
741 return method;
742 }
743
744 typedef struct CrsRangeEntry {
745 uint64_t base;
746 uint64_t limit;
747 } CrsRangeEntry;
748
749 static void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit)
750 {
751 CrsRangeEntry *entry;
752
753 entry = g_malloc(sizeof(*entry));
754 entry->base = base;
755 entry->limit = limit;
756
757 g_ptr_array_add(ranges, entry);
758 }
759
760 static void crs_range_free(gpointer data)
761 {
762 CrsRangeEntry *entry = (CrsRangeEntry *)data;
763 g_free(entry);
764 }
765
766 static gint crs_range_compare(gconstpointer a, gconstpointer b)
767 {
768 CrsRangeEntry *entry_a = *(CrsRangeEntry **)a;
769 CrsRangeEntry *entry_b = *(CrsRangeEntry **)b;
770
771 return (int64_t)entry_a->base - (int64_t)entry_b->base;
772 }
773
774 /*
775 * crs_replace_with_free_ranges - given the 'used' ranges within [start - end]
776 * interval, computes the 'free' ranges from the same interval.
777 * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function
778 * will return { [base - a1], [a2 - b1], [b2 - limit] }.
779 */
780 static void crs_replace_with_free_ranges(GPtrArray *ranges,
781 uint64_t start, uint64_t end)
782 {
783 GPtrArray *free_ranges = g_ptr_array_new_with_free_func(crs_range_free);
784 uint64_t free_base = start;
785 int i;
786
787 g_ptr_array_sort(ranges, crs_range_compare);
788 for (i = 0; i < ranges->len; i++) {
789 CrsRangeEntry *used = g_ptr_array_index(ranges, i);
790
791 if (free_base < used->base) {
792 crs_range_insert(free_ranges, free_base, used->base - 1);
793 }
794
795 free_base = used->limit + 1;
796 }
797
798 if (free_base < end) {
799 crs_range_insert(free_ranges, free_base, end);
800 }
801
802 g_ptr_array_set_size(ranges, 0);
803 for (i = 0; i < free_ranges->len; i++) {
804 g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i));
805 }
806
807 g_ptr_array_free(free_ranges, false);
808 }
809
810 /*
811 * crs_range_merge - merges adjacent ranges in the given array.
812 * Array elements are deleted and replaced with the merged ranges.
813 */
814 static void crs_range_merge(GPtrArray *range)
815 {
816 GPtrArray *tmp = g_ptr_array_new_with_free_func(crs_range_free);
817 CrsRangeEntry *entry;
818 uint64_t range_base, range_limit;
819 int i;
820
821 if (!range->len) {
822 return;
823 }
824
825 g_ptr_array_sort(range, crs_range_compare);
826
827 entry = g_ptr_array_index(range, 0);
828 range_base = entry->base;
829 range_limit = entry->limit;
830 for (i = 1; i < range->len; i++) {
831 entry = g_ptr_array_index(range, i);
832 if (entry->base - 1 == range_limit) {
833 range_limit = entry->limit;
834 } else {
835 crs_range_insert(tmp, range_base, range_limit);
836 range_base = entry->base;
837 range_limit = entry->limit;
838 }
839 }
840 crs_range_insert(tmp, range_base, range_limit);
841
842 g_ptr_array_set_size(range, 0);
843 for (i = 0; i < tmp->len; i++) {
844 entry = g_ptr_array_index(tmp, i);
845 crs_range_insert(range, entry->base, entry->limit);
846 }
847 g_ptr_array_free(tmp, true);
848 }
849
850 static Aml *build_crs(PCIHostState *host,
851 GPtrArray *io_ranges, GPtrArray *mem_ranges)
852 {
853 Aml *crs = aml_resource_template();
854 GPtrArray *host_io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
855 GPtrArray *host_mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
856 CrsRangeEntry *entry;
857 uint8_t max_bus = pci_bus_num(host->bus);
858 uint8_t type;
859 int devfn;
860 int i;
861
862 for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) {
863 uint64_t range_base, range_limit;
864 PCIDevice *dev = host->bus->devices[devfn];
865
866 if (!dev) {
867 continue;
868 }
869
870 for (i = 0; i < PCI_NUM_REGIONS; i++) {
871 PCIIORegion *r = &dev->io_regions[i];
872
873 range_base = r->addr;
874 range_limit = r->addr + r->size - 1;
875
876 /*
877 * Work-around for old bioses
878 * that do not support multiple root buses
879 */
880 if (!range_base || range_base > range_limit) {
881 continue;
882 }
883
884 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
885 crs_range_insert(host_io_ranges, range_base, range_limit);
886 } else { /* "memory" */
887 crs_range_insert(host_mem_ranges, range_base, range_limit);
888 }
889 }
890
891 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
892 if (type == PCI_HEADER_TYPE_BRIDGE) {
893 uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS];
894 if (subordinate > max_bus) {
895 max_bus = subordinate;
896 }
897
898 range_base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
899 range_limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
900
901 /*
902 * Work-around for old bioses
903 * that do not support multiple root buses
904 */
905 if (range_base && range_base <= range_limit) {
906 crs_range_insert(host_io_ranges, range_base, range_limit);
907 }
908
909 range_base =
910 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
911 range_limit =
912 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
913
914 /*
915 * Work-around for old bioses
916 * that do not support multiple root buses
917 */
918 if (range_base && range_base <= range_limit) {
919 crs_range_insert(host_mem_ranges, range_base, range_limit);
920 }
921
922 range_base =
923 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
924 range_limit =
925 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
926
927 /*
928 * Work-around for old bioses
929 * that do not support multiple root buses
930 */
931 if (range_base && range_base <= range_limit) {
932 crs_range_insert(host_mem_ranges, range_base, range_limit);
933 }
934 }
935 }
936
937 crs_range_merge(host_io_ranges);
938 for (i = 0; i < host_io_ranges->len; i++) {
939 entry = g_ptr_array_index(host_io_ranges, i);
940 aml_append(crs,
941 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
942 AML_POS_DECODE, AML_ENTIRE_RANGE,
943 0, entry->base, entry->limit, 0,
944 entry->limit - entry->base + 1));
945 crs_range_insert(io_ranges, entry->base, entry->limit);
946 }
947 g_ptr_array_free(host_io_ranges, true);
948
949 crs_range_merge(host_mem_ranges);
950 for (i = 0; i < host_mem_ranges->len; i++) {
951 entry = g_ptr_array_index(host_mem_ranges, i);
952 aml_append(crs,
953 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED,
954 AML_MAX_FIXED, AML_NON_CACHEABLE,
955 AML_READ_WRITE,
956 0, entry->base, entry->limit, 0,
957 entry->limit - entry->base + 1));
958 crs_range_insert(mem_ranges, entry->base, entry->limit);
959 }
960 g_ptr_array_free(host_mem_ranges, true);
961
962 aml_append(crs,
963 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
964 0,
965 pci_bus_num(host->bus),
966 max_bus,
967 0,
968 max_bus - pci_bus_num(host->bus) + 1));
969
970 return crs;
971 }
972
973 static void build_processor_devices(Aml *sb_scope, unsigned acpi_cpus,
974 AcpiCpuInfo *cpu, AcpiPmInfo *pm)
975 {
976 int i;
977 Aml *dev;
978 Aml *crs;
979 Aml *pkg;
980 Aml *field;
981 Aml *ifctx;
982 Aml *method;
983
984 /* The current AML generator can cover the APIC ID range [0..255],
985 * inclusive, for VCPU hotplug. */
986 QEMU_BUILD_BUG_ON(ACPI_CPU_HOTPLUG_ID_LIMIT > 256);
987 g_assert(acpi_cpus <= ACPI_CPU_HOTPLUG_ID_LIMIT);
988
989 /* create PCI0.PRES device and its _CRS to reserve CPU hotplug MMIO */
990 dev = aml_device("PCI0." stringify(CPU_HOTPLUG_RESOURCE_DEVICE));
991 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06")));
992 aml_append(dev,
993 aml_name_decl("_UID", aml_string("CPU Hotplug resources"))
994 );
995 /* device present, functioning, decoding, not shown in UI */
996 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
997 crs = aml_resource_template();
998 aml_append(crs,
999 aml_io(AML_DECODE16, pm->cpu_hp_io_base, pm->cpu_hp_io_base, 1,
1000 pm->cpu_hp_io_len)
1001 );
1002 aml_append(dev, aml_name_decl("_CRS", crs));
1003 aml_append(sb_scope, dev);
1004 /* declare CPU hotplug MMIO region and PRS field to access it */
1005 aml_append(sb_scope, aml_operation_region(
1006 "PRST", AML_SYSTEM_IO, pm->cpu_hp_io_base, pm->cpu_hp_io_len));
1007 field = aml_field("PRST", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1008 aml_append(field, aml_named_field("PRS", 256));
1009 aml_append(sb_scope, field);
1010
1011 /* build Processor object for each processor */
1012 for (i = 0; i < acpi_cpus; i++) {
1013 dev = aml_processor(i, 0, 0, "CP%.02X", i);
1014
1015 method = aml_method("_MAT", 0, AML_NOTSERIALIZED);
1016 aml_append(method,
1017 aml_return(aml_call1(CPU_MAT_METHOD, aml_int(i))));
1018 aml_append(dev, method);
1019
1020 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1021 aml_append(method,
1022 aml_return(aml_call1(CPU_STATUS_METHOD, aml_int(i))));
1023 aml_append(dev, method);
1024
1025 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
1026 aml_append(method,
1027 aml_return(aml_call2(CPU_EJECT_METHOD, aml_int(i), aml_arg(0)))
1028 );
1029 aml_append(dev, method);
1030
1031 aml_append(sb_scope, dev);
1032 }
1033
1034 /* build this code:
1035 * Method(NTFY, 2) {If (LEqual(Arg0, 0x00)) {Notify(CP00, Arg1)} ...}
1036 */
1037 /* Arg0 = Processor ID = APIC ID */
1038 method = aml_method(AML_NOTIFY_METHOD, 2, AML_NOTSERIALIZED);
1039 for (i = 0; i < acpi_cpus; i++) {
1040 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i)));
1041 aml_append(ifctx,
1042 aml_notify(aml_name("CP%.02X", i), aml_arg(1))
1043 );
1044 aml_append(method, ifctx);
1045 }
1046 aml_append(sb_scope, method);
1047
1048 /* build "Name(CPON, Package() { One, One, ..., Zero, Zero, ... })"
1049 *
1050 * Note: The ability to create variable-sized packages was first
1051 * introduced in ACPI 2.0. ACPI 1.0 only allowed fixed-size packages
1052 * ith up to 255 elements. Windows guests up to win2k8 fail when
1053 * VarPackageOp is used.
1054 */
1055 pkg = acpi_cpus <= 255 ? aml_package(acpi_cpus) :
1056 aml_varpackage(acpi_cpus);
1057
1058 for (i = 0; i < acpi_cpus; i++) {
1059 uint8_t b = test_bit(i, cpu->found_cpus) ? 0x01 : 0x00;
1060 aml_append(pkg, aml_int(b));
1061 }
1062 aml_append(sb_scope, aml_name_decl(CPU_ON_BITMAP, pkg));
1063 }
1064
1065 static void build_memory_devices(Aml *sb_scope, int nr_mem,
1066 uint16_t io_base, uint16_t io_len)
1067 {
1068 int i;
1069 Aml *scope;
1070 Aml *crs;
1071 Aml *field;
1072 Aml *dev;
1073 Aml *method;
1074 Aml *ifctx;
1075
1076 /* build memory devices */
1077 assert(nr_mem <= ACPI_MAX_RAM_SLOTS);
1078 scope = aml_scope("\\_SB.PCI0." MEMORY_HOTPLUG_DEVICE);
1079 aml_append(scope,
1080 aml_name_decl(MEMORY_SLOTS_NUMBER, aml_int(nr_mem))
1081 );
1082
1083 crs = aml_resource_template();
1084 aml_append(crs,
1085 aml_io(AML_DECODE16, io_base, io_base, 0, io_len)
1086 );
1087 aml_append(scope, aml_name_decl("_CRS", crs));
1088
1089 aml_append(scope, aml_operation_region(
1090 MEMORY_HOTPLUG_IO_REGION, AML_SYSTEM_IO,
1091 io_base, io_len)
1092 );
1093
1094 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_DWORD_ACC,
1095 AML_NOLOCK, AML_PRESERVE);
1096 aml_append(field, /* read only */
1097 aml_named_field(MEMORY_SLOT_ADDR_LOW, 32));
1098 aml_append(field, /* read only */
1099 aml_named_field(MEMORY_SLOT_ADDR_HIGH, 32));
1100 aml_append(field, /* read only */
1101 aml_named_field(MEMORY_SLOT_SIZE_LOW, 32));
1102 aml_append(field, /* read only */
1103 aml_named_field(MEMORY_SLOT_SIZE_HIGH, 32));
1104 aml_append(field, /* read only */
1105 aml_named_field(MEMORY_SLOT_PROXIMITY, 32));
1106 aml_append(scope, field);
1107
1108 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_BYTE_ACC,
1109 AML_NOLOCK, AML_WRITE_AS_ZEROS);
1110 aml_append(field, aml_reserved_field(160 /* bits, Offset(20) */));
1111 aml_append(field, /* 1 if enabled, read only */
1112 aml_named_field(MEMORY_SLOT_ENABLED, 1));
1113 aml_append(field,
1114 /*(read) 1 if has a insert event. (write) 1 to clear event */
1115 aml_named_field(MEMORY_SLOT_INSERT_EVENT, 1));
1116 aml_append(field,
1117 /* (read) 1 if has a remove event. (write) 1 to clear event */
1118 aml_named_field(MEMORY_SLOT_REMOVE_EVENT, 1));
1119 aml_append(field,
1120 /* initiates device eject, write only */
1121 aml_named_field(MEMORY_SLOT_EJECT, 1));
1122 aml_append(scope, field);
1123
1124 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_DWORD_ACC,
1125 AML_NOLOCK, AML_PRESERVE);
1126 aml_append(field, /* DIMM selector, write only */
1127 aml_named_field(MEMORY_SLOT_SLECTOR, 32));
1128 aml_append(field, /* _OST event code, write only */
1129 aml_named_field(MEMORY_SLOT_OST_EVENT, 32));
1130 aml_append(field, /* _OST status code, write only */
1131 aml_named_field(MEMORY_SLOT_OST_STATUS, 32));
1132 aml_append(scope, field);
1133 aml_append(sb_scope, scope);
1134
1135 for (i = 0; i < nr_mem; i++) {
1136 #define BASEPATH "\\_SB.PCI0." MEMORY_HOTPLUG_DEVICE "."
1137 const char *s;
1138
1139 dev = aml_device("MP%02X", i);
1140 aml_append(dev, aml_name_decl("_UID", aml_string("0x%02X", i)));
1141 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C80")));
1142
1143 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1144 s = BASEPATH MEMORY_SLOT_CRS_METHOD;
1145 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1146 aml_append(dev, method);
1147
1148 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1149 s = BASEPATH MEMORY_SLOT_STATUS_METHOD;
1150 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1151 aml_append(dev, method);
1152
1153 method = aml_method("_PXM", 0, AML_NOTSERIALIZED);
1154 s = BASEPATH MEMORY_SLOT_PROXIMITY_METHOD;
1155 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1156 aml_append(dev, method);
1157
1158 method = aml_method("_OST", 3, AML_NOTSERIALIZED);
1159 s = BASEPATH MEMORY_SLOT_OST_METHOD;
1160
1161 aml_append(method, aml_return(aml_call4(
1162 s, aml_name("_UID"), aml_arg(0), aml_arg(1), aml_arg(2)
1163 )));
1164 aml_append(dev, method);
1165
1166 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
1167 s = BASEPATH MEMORY_SLOT_EJECT_METHOD;
1168 aml_append(method, aml_return(aml_call2(
1169 s, aml_name("_UID"), aml_arg(0))));
1170 aml_append(dev, method);
1171
1172 aml_append(sb_scope, dev);
1173 }
1174
1175 /* build Method(MEMORY_SLOT_NOTIFY_METHOD, 2) {
1176 * If (LEqual(Arg0, 0x00)) {Notify(MP00, Arg1)} ... }
1177 */
1178 method = aml_method(MEMORY_SLOT_NOTIFY_METHOD, 2, AML_NOTSERIALIZED);
1179 for (i = 0; i < nr_mem; i++) {
1180 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i)));
1181 aml_append(ifctx,
1182 aml_notify(aml_name("MP%.02X", i), aml_arg(1))
1183 );
1184 aml_append(method, ifctx);
1185 }
1186 aml_append(sb_scope, method);
1187 }
1188
1189 static void build_hpet_aml(Aml *table)
1190 {
1191 Aml *crs;
1192 Aml *field;
1193 Aml *method;
1194 Aml *if_ctx;
1195 Aml *scope = aml_scope("_SB");
1196 Aml *dev = aml_device("HPET");
1197 Aml *zero = aml_int(0);
1198 Aml *id = aml_local(0);
1199 Aml *period = aml_local(1);
1200
1201 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103")));
1202 aml_append(dev, aml_name_decl("_UID", zero));
1203
1204 aml_append(dev,
1205 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, HPET_BASE, HPET_LEN));
1206 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE);
1207 aml_append(field, aml_named_field("VEND", 32));
1208 aml_append(field, aml_named_field("PRD", 32));
1209 aml_append(dev, field);
1210
1211 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1212 aml_append(method, aml_store(aml_name("VEND"), id));
1213 aml_append(method, aml_store(aml_name("PRD"), period));
1214 aml_append(method, aml_shiftright(id, aml_int(16), id));
1215 if_ctx = aml_if(aml_lor(aml_equal(id, zero),
1216 aml_equal(id, aml_int(0xffff))));
1217 {
1218 aml_append(if_ctx, aml_return(zero));
1219 }
1220 aml_append(method, if_ctx);
1221
1222 if_ctx = aml_if(aml_lor(aml_equal(period, zero),
1223 aml_lgreater(period, aml_int(100000000))));
1224 {
1225 aml_append(if_ctx, aml_return(zero));
1226 }
1227 aml_append(method, if_ctx);
1228
1229 aml_append(method, aml_return(aml_int(0x0F)));
1230 aml_append(dev, method);
1231
1232 crs = aml_resource_template();
1233 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY));
1234 aml_append(dev, aml_name_decl("_CRS", crs));
1235
1236 aml_append(scope, dev);
1237 aml_append(table, scope);
1238 }
1239
1240 static Aml *build_fdc_device_aml(void)
1241 {
1242 Aml *dev;
1243 Aml *crs;
1244 Aml *method;
1245 Aml *if_ctx;
1246 Aml *else_ctx;
1247 Aml *zero = aml_int(0);
1248 Aml *is_present = aml_local(0);
1249
1250 dev = aml_device("FDC0");
1251 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0700")));
1252
1253 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1254 aml_append(method, aml_store(aml_name("FDEN"), is_present));
1255 if_ctx = aml_if(aml_equal(is_present, zero));
1256 {
1257 aml_append(if_ctx, aml_return(aml_int(0x00)));
1258 }
1259 aml_append(method, if_ctx);
1260 else_ctx = aml_else();
1261 {
1262 aml_append(else_ctx, aml_return(aml_int(0x0f)));
1263 }
1264 aml_append(method, else_ctx);
1265 aml_append(dev, method);
1266
1267 crs = aml_resource_template();
1268 aml_append(crs, aml_io(AML_DECODE16, 0x03F2, 0x03F2, 0x00, 0x04));
1269 aml_append(crs, aml_io(AML_DECODE16, 0x03F7, 0x03F7, 0x00, 0x01));
1270 aml_append(crs, aml_irq_no_flags(6));
1271 aml_append(crs,
1272 aml_dma(AML_COMPATIBILITY, AML_NOTBUSMASTER, AML_TRANSFER8, 2));
1273 aml_append(dev, aml_name_decl("_CRS", crs));
1274
1275 return dev;
1276 }
1277
1278 static Aml *build_rtc_device_aml(void)
1279 {
1280 Aml *dev;
1281 Aml *crs;
1282
1283 dev = aml_device("RTC");
1284 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0B00")));
1285 crs = aml_resource_template();
1286 aml_append(crs, aml_io(AML_DECODE16, 0x0070, 0x0070, 0x10, 0x02));
1287 aml_append(crs, aml_irq_no_flags(8));
1288 aml_append(crs, aml_io(AML_DECODE16, 0x0072, 0x0072, 0x02, 0x06));
1289 aml_append(dev, aml_name_decl("_CRS", crs));
1290
1291 return dev;
1292 }
1293
1294 static Aml *build_kbd_device_aml(void)
1295 {
1296 Aml *dev;
1297 Aml *crs;
1298 Aml *method;
1299
1300 dev = aml_device("KBD");
1301 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0303")));
1302
1303 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1304 aml_append(method, aml_return(aml_int(0x0f)));
1305 aml_append(dev, method);
1306
1307 crs = aml_resource_template();
1308 aml_append(crs, aml_io(AML_DECODE16, 0x0060, 0x0060, 0x01, 0x01));
1309 aml_append(crs, aml_io(AML_DECODE16, 0x0064, 0x0064, 0x01, 0x01));
1310 aml_append(crs, aml_irq_no_flags(1));
1311 aml_append(dev, aml_name_decl("_CRS", crs));
1312
1313 return dev;
1314 }
1315
1316 static Aml *build_mouse_device_aml(void)
1317 {
1318 Aml *dev;
1319 Aml *crs;
1320 Aml *method;
1321
1322 dev = aml_device("MOU");
1323 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0F13")));
1324
1325 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1326 aml_append(method, aml_return(aml_int(0x0f)));
1327 aml_append(dev, method);
1328
1329 crs = aml_resource_template();
1330 aml_append(crs, aml_irq_no_flags(12));
1331 aml_append(dev, aml_name_decl("_CRS", crs));
1332
1333 return dev;
1334 }
1335
1336 static Aml *build_lpt_device_aml(void)
1337 {
1338 Aml *dev;
1339 Aml *crs;
1340 Aml *method;
1341 Aml *if_ctx;
1342 Aml *else_ctx;
1343 Aml *zero = aml_int(0);
1344 Aml *is_present = aml_local(0);
1345
1346 dev = aml_device("LPT");
1347 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0400")));
1348
1349 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1350 aml_append(method, aml_store(aml_name("LPEN"), is_present));
1351 if_ctx = aml_if(aml_equal(is_present, zero));
1352 {
1353 aml_append(if_ctx, aml_return(aml_int(0x00)));
1354 }
1355 aml_append(method, if_ctx);
1356 else_ctx = aml_else();
1357 {
1358 aml_append(else_ctx, aml_return(aml_int(0x0f)));
1359 }
1360 aml_append(method, else_ctx);
1361 aml_append(dev, method);
1362
1363 crs = aml_resource_template();
1364 aml_append(crs, aml_io(AML_DECODE16, 0x0378, 0x0378, 0x08, 0x08));
1365 aml_append(crs, aml_irq_no_flags(7));
1366 aml_append(dev, aml_name_decl("_CRS", crs));
1367
1368 return dev;
1369 }
1370
1371 static Aml *build_com_device_aml(uint8_t uid)
1372 {
1373 Aml *dev;
1374 Aml *crs;
1375 Aml *method;
1376 Aml *if_ctx;
1377 Aml *else_ctx;
1378 Aml *zero = aml_int(0);
1379 Aml *is_present = aml_local(0);
1380 const char *enabled_field = "CAEN";
1381 uint8_t irq = 4;
1382 uint16_t io_port = 0x03F8;
1383
1384 assert(uid == 1 || uid == 2);
1385 if (uid == 2) {
1386 enabled_field = "CBEN";
1387 irq = 3;
1388 io_port = 0x02F8;
1389 }
1390
1391 dev = aml_device("COM%d", uid);
1392 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0501")));
1393 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1394
1395 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1396 aml_append(method, aml_store(aml_name("%s", enabled_field), is_present));
1397 if_ctx = aml_if(aml_equal(is_present, zero));
1398 {
1399 aml_append(if_ctx, aml_return(aml_int(0x00)));
1400 }
1401 aml_append(method, if_ctx);
1402 else_ctx = aml_else();
1403 {
1404 aml_append(else_ctx, aml_return(aml_int(0x0f)));
1405 }
1406 aml_append(method, else_ctx);
1407 aml_append(dev, method);
1408
1409 crs = aml_resource_template();
1410 aml_append(crs, aml_io(AML_DECODE16, io_port, io_port, 0x00, 0x08));
1411 aml_append(crs, aml_irq_no_flags(irq));
1412 aml_append(dev, aml_name_decl("_CRS", crs));
1413
1414 return dev;
1415 }
1416
1417 static void build_isa_devices_aml(Aml *table)
1418 {
1419 Aml *scope = aml_scope("_SB.PCI0.ISA");
1420
1421 aml_append(scope, build_rtc_device_aml());
1422 aml_append(scope, build_kbd_device_aml());
1423 aml_append(scope, build_mouse_device_aml());
1424 aml_append(scope, build_fdc_device_aml());
1425 aml_append(scope, build_lpt_device_aml());
1426 aml_append(scope, build_com_device_aml(1));
1427 aml_append(scope, build_com_device_aml(2));
1428
1429 aml_append(table, scope);
1430 }
1431
1432 static void build_dbg_aml(Aml *table)
1433 {
1434 Aml *field;
1435 Aml *method;
1436 Aml *while_ctx;
1437 Aml *scope = aml_scope("\\");
1438 Aml *buf = aml_local(0);
1439 Aml *len = aml_local(1);
1440 Aml *idx = aml_local(2);
1441
1442 aml_append(scope,
1443 aml_operation_region("DBG", AML_SYSTEM_IO, 0x0402, 0x01));
1444 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1445 aml_append(field, aml_named_field("DBGB", 8));
1446 aml_append(scope, field);
1447
1448 method = aml_method("DBUG", 1, AML_NOTSERIALIZED);
1449
1450 aml_append(method, aml_to_hexstring(aml_arg(0), buf));
1451 aml_append(method, aml_to_buffer(buf, buf));
1452 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len));
1453 aml_append(method, aml_store(aml_int(0), idx));
1454
1455 while_ctx = aml_while(aml_lless(idx, len));
1456 aml_append(while_ctx,
1457 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB")));
1458 aml_append(while_ctx, aml_increment(idx));
1459 aml_append(method, while_ctx);
1460
1461 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB")));
1462 aml_append(scope, method);
1463
1464 aml_append(table, scope);
1465 }
1466
1467 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg)
1468 {
1469 Aml *dev;
1470 Aml *crs;
1471 Aml *method;
1472 uint32_t irqs[] = {5, 10, 11};
1473
1474 dev = aml_device("%s", name);
1475 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1476 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1477
1478 crs = aml_resource_template();
1479 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1480 AML_SHARED, irqs, ARRAY_SIZE(irqs)));
1481 aml_append(dev, aml_name_decl("_PRS", crs));
1482
1483 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1484 aml_append(method, aml_return(aml_call1("IQST", reg)));
1485 aml_append(dev, method);
1486
1487 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1488 aml_append(method, aml_or(reg, aml_int(0x80), reg));
1489 aml_append(dev, method);
1490
1491 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1492 aml_append(method, aml_return(aml_call1("IQCR", reg)));
1493 aml_append(dev, method);
1494
1495 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1496 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
1497 aml_append(method, aml_store(aml_name("PRRI"), reg));
1498 aml_append(dev, method);
1499
1500 return dev;
1501 }
1502
1503 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi)
1504 {
1505 Aml *dev;
1506 Aml *crs;
1507 Aml *method;
1508 uint32_t irqs;
1509
1510 dev = aml_device("%s", name);
1511 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1512 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1513
1514 crs = aml_resource_template();
1515 irqs = gsi;
1516 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1517 AML_SHARED, &irqs, 1));
1518 aml_append(dev, aml_name_decl("_PRS", crs));
1519
1520 aml_append(dev, aml_name_decl("_CRS", crs));
1521
1522 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1523 aml_append(dev, method);
1524
1525 return dev;
1526 }
1527
1528 /* _CRS method - get current settings */
1529 static Aml *build_iqcr_method(bool is_piix4)
1530 {
1531 Aml *if_ctx;
1532 uint32_t irqs;
1533 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED);
1534 Aml *crs = aml_resource_template();
1535
1536 irqs = 0;
1537 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1538 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1));
1539 aml_append(method, aml_name_decl("PRR0", crs));
1540
1541 aml_append(method,
1542 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
1543
1544 if (is_piix4) {
1545 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
1546 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI")));
1547 aml_append(method, if_ctx);
1548 } else {
1549 aml_append(method,
1550 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL),
1551 aml_name("PRRI")));
1552 }
1553
1554 aml_append(method, aml_return(aml_name("PRR0")));
1555 return method;
1556 }
1557
1558 /* _STA method - get status */
1559 static Aml *build_irq_status_method(void)
1560 {
1561 Aml *if_ctx;
1562 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED);
1563
1564 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL));
1565 aml_append(if_ctx, aml_return(aml_int(0x09)));
1566 aml_append(method, if_ctx);
1567 aml_append(method, aml_return(aml_int(0x0B)));
1568 return method;
1569 }
1570
1571 static void build_piix4_pci0_int(Aml *table)
1572 {
1573 Aml *dev;
1574 Aml *crs;
1575 Aml *field;
1576 Aml *method;
1577 uint32_t irqs;
1578 Aml *sb_scope = aml_scope("_SB");
1579 Aml *pci0_scope = aml_scope("PCI0");
1580
1581 aml_append(pci0_scope, build_prt(true));
1582 aml_append(sb_scope, pci0_scope);
1583
1584 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1585 aml_append(field, aml_named_field("PRQ0", 8));
1586 aml_append(field, aml_named_field("PRQ1", 8));
1587 aml_append(field, aml_named_field("PRQ2", 8));
1588 aml_append(field, aml_named_field("PRQ3", 8));
1589 aml_append(sb_scope, field);
1590
1591 aml_append(sb_scope, build_irq_status_method());
1592 aml_append(sb_scope, build_iqcr_method(true));
1593
1594 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0")));
1595 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1")));
1596 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2")));
1597 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3")));
1598
1599 dev = aml_device("LNKS");
1600 {
1601 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1602 aml_append(dev, aml_name_decl("_UID", aml_int(4)));
1603
1604 crs = aml_resource_template();
1605 irqs = 9;
1606 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1607 AML_ACTIVE_HIGH, AML_SHARED,
1608 &irqs, 1));
1609 aml_append(dev, aml_name_decl("_PRS", crs));
1610
1611 /* The SCI cannot be disabled and is always attached to GSI 9,
1612 * so these are no-ops. We only need this link to override the
1613 * polarity to active high and match the content of the MADT.
1614 */
1615 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1616 aml_append(method, aml_return(aml_int(0x0b)));
1617 aml_append(dev, method);
1618
1619 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1620 aml_append(dev, method);
1621
1622 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1623 aml_append(method, aml_return(aml_name("_PRS")));
1624 aml_append(dev, method);
1625
1626 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1627 aml_append(dev, method);
1628 }
1629 aml_append(sb_scope, dev);
1630
1631 aml_append(table, sb_scope);
1632 }
1633
1634 static void build_q35_pci0_int(Aml *table)
1635 {
1636 Aml *field;
1637 Aml *sb_scope = aml_scope("_SB");
1638
1639 field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1640 aml_append(field, aml_named_field("PRQA", 8));
1641 aml_append(field, aml_named_field("PRQB", 8));
1642 aml_append(field, aml_named_field("PRQC", 8));
1643 aml_append(field, aml_named_field("PRQD", 8));
1644 aml_append(field, aml_reserved_field(0x20));
1645 aml_append(field, aml_named_field("PRQE", 8));
1646 aml_append(field, aml_named_field("PRQF", 8));
1647 aml_append(field, aml_named_field("PRQG", 8));
1648 aml_append(field, aml_named_field("PRQH", 8));
1649 aml_append(sb_scope, field);
1650
1651 aml_append(sb_scope, build_irq_status_method());
1652 aml_append(sb_scope, build_iqcr_method(false));
1653
1654 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA")));
1655 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB")));
1656 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC")));
1657 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD")));
1658 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE")));
1659 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF")));
1660 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG")));
1661 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH")));
1662
1663 /*
1664 * TODO: UID probably shouldn't be the same for GSIx devices
1665 * but that's how it was in original ASL so keep it for now
1666 */
1667 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0, 0x10));
1668 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0, 0x11));
1669 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0, 0x12));
1670 aml_append(sb_scope, build_gsi_link_dev("GSID", 0, 0x13));
1671 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0, 0x14));
1672 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0, 0x15));
1673 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0, 0x16));
1674 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0, 0x17));
1675
1676 aml_append(table, sb_scope);
1677 }
1678
1679 static void build_q35_isa_bridge(Aml *table)
1680 {
1681 Aml *dev;
1682 Aml *scope;
1683 Aml *field;
1684
1685 scope = aml_scope("_SB.PCI0");
1686 dev = aml_device("ISA");
1687 aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000)));
1688
1689 /* ICH9 PCI to ISA irq remapping */
1690 aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG,
1691 0x60, 0x0C));
1692
1693 aml_append(dev, aml_operation_region("LPCD", AML_PCI_CONFIG,
1694 0x80, 0x02));
1695 field = aml_field("LPCD", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1696 aml_append(field, aml_named_field("COMA", 3));
1697 aml_append(field, aml_reserved_field(1));
1698 aml_append(field, aml_named_field("COMB", 3));
1699 aml_append(field, aml_reserved_field(1));
1700 aml_append(field, aml_named_field("LPTD", 2));
1701 aml_append(field, aml_reserved_field(2));
1702 aml_append(field, aml_named_field("FDCD", 2));
1703 aml_append(dev, field);
1704
1705 aml_append(dev, aml_operation_region("LPCE", AML_PCI_CONFIG,
1706 0x82, 0x02));
1707 /* enable bits */
1708 field = aml_field("LPCE", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1709 aml_append(field, aml_named_field("CAEN", 1));
1710 aml_append(field, aml_named_field("CBEN", 1));
1711 aml_append(field, aml_named_field("LPEN", 1));
1712 aml_append(field, aml_named_field("FDEN", 1));
1713 aml_append(dev, field);
1714
1715 aml_append(scope, dev);
1716 aml_append(table, scope);
1717 }
1718
1719 static void build_piix4_pm(Aml *table)
1720 {
1721 Aml *dev;
1722 Aml *scope;
1723
1724 scope = aml_scope("_SB.PCI0");
1725 dev = aml_device("PX13");
1726 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010003)));
1727
1728 aml_append(dev, aml_operation_region("P13C", AML_PCI_CONFIG,
1729 0x00, 0xff));
1730 aml_append(scope, dev);
1731 aml_append(table, scope);
1732 }
1733
1734 static void build_piix4_isa_bridge(Aml *table)
1735 {
1736 Aml *dev;
1737 Aml *scope;
1738 Aml *field;
1739
1740 scope = aml_scope("_SB.PCI0");
1741 dev = aml_device("ISA");
1742 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000)));
1743
1744 /* PIIX PCI to ISA irq remapping */
1745 aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG,
1746 0x60, 0x04));
1747 /* enable bits */
1748 field = aml_field("^PX13.P13C", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1749 /* Offset(0x5f),, 7, */
1750 aml_append(field, aml_reserved_field(0x2f8));
1751 aml_append(field, aml_reserved_field(7));
1752 aml_append(field, aml_named_field("LPEN", 1));
1753 /* Offset(0x67),, 3, */
1754 aml_append(field, aml_reserved_field(0x38));
1755 aml_append(field, aml_reserved_field(3));
1756 aml_append(field, aml_named_field("CAEN", 1));
1757 aml_append(field, aml_reserved_field(3));
1758 aml_append(field, aml_named_field("CBEN", 1));
1759 aml_append(dev, field);
1760 aml_append(dev, aml_name_decl("FDEN", aml_int(1)));
1761
1762 aml_append(scope, dev);
1763 aml_append(table, scope);
1764 }
1765
1766 static void build_piix4_pci_hotplug(Aml *table)
1767 {
1768 Aml *scope;
1769 Aml *field;
1770 Aml *method;
1771
1772 scope = aml_scope("_SB.PCI0");
1773
1774 aml_append(scope,
1775 aml_operation_region("PCST", AML_SYSTEM_IO, 0xae00, 0x08));
1776 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1777 aml_append(field, aml_named_field("PCIU", 32));
1778 aml_append(field, aml_named_field("PCID", 32));
1779 aml_append(scope, field);
1780
1781 aml_append(scope,
1782 aml_operation_region("SEJ", AML_SYSTEM_IO, 0xae08, 0x04));
1783 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1784 aml_append(field, aml_named_field("B0EJ", 32));
1785 aml_append(scope, field);
1786
1787 aml_append(scope,
1788 aml_operation_region("BNMR", AML_SYSTEM_IO, 0xae10, 0x04));
1789 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1790 aml_append(field, aml_named_field("BNUM", 32));
1791 aml_append(scope, field);
1792
1793 aml_append(scope, aml_mutex("BLCK", 0));
1794
1795 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED);
1796 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF));
1797 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM")));
1798 aml_append(method,
1799 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ")));
1800 aml_append(method, aml_release(aml_name("BLCK")));
1801 aml_append(method, aml_return(aml_int(0)));
1802 aml_append(scope, method);
1803
1804 aml_append(table, scope);
1805 }
1806
1807
1808 static void
1809 build_ssdt(GArray *table_data, GArray *linker,
1810 AcpiCpuInfo *cpu, AcpiPmInfo *pm, AcpiMiscInfo *misc,
1811 PcPciInfo *pci, PcGuestInfo *guest_info)
1812 {
1813 MachineState *machine = MACHINE(qdev_get_machine());
1814 uint32_t nr_mem = machine->ram_slots;
1815 Aml *ssdt, *sb_scope, *scope, *pkg, *dev, *method, *crs, *field;
1816 PCIBus *bus = NULL;
1817 GPtrArray *io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
1818 GPtrArray *mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
1819 CrsRangeEntry *entry;
1820 int root_bus_limit = 0xFF;
1821 int i;
1822
1823 ssdt = init_aml_allocator();
1824
1825 /* Reserve space for header */
1826 acpi_data_push(ssdt->buf, sizeof(AcpiTableHeader));
1827
1828 build_dbg_aml(ssdt);
1829 if (misc->is_piix4) {
1830 sb_scope = aml_scope("_SB");
1831 dev = aml_device("PCI0");
1832 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1833 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1834 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
1835 aml_append(sb_scope, dev);
1836 aml_append(ssdt, sb_scope);
1837
1838 build_hpet_aml(ssdt);
1839 build_piix4_pm(ssdt);
1840 build_piix4_isa_bridge(ssdt);
1841 build_isa_devices_aml(ssdt);
1842 build_piix4_pci_hotplug(ssdt);
1843 build_piix4_pci0_int(ssdt);
1844 } else {
1845 build_hpet_aml(ssdt);
1846 build_q35_isa_bridge(ssdt);
1847 build_isa_devices_aml(ssdt);
1848 build_q35_pci0_int(ssdt);
1849 }
1850
1851 build_cpu_hotplug_aml(ssdt);
1852 build_memory_hotplug_aml(ssdt, nr_mem, pm->mem_hp_io_base,
1853 pm->mem_hp_io_len);
1854
1855 scope = aml_scope("_GPE");
1856 {
1857 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006")));
1858
1859 aml_append(scope, aml_method("_L00", 0, AML_NOTSERIALIZED));
1860
1861 if (misc->is_piix4) {
1862 method = aml_method("_E01", 0, AML_NOTSERIALIZED);
1863 aml_append(method,
1864 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
1865 aml_append(method, aml_call0("\\_SB.PCI0.PCNT"));
1866 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK")));
1867 aml_append(scope, method);
1868 } else {
1869 aml_append(scope, aml_method("_L01", 0, AML_NOTSERIALIZED));
1870 }
1871
1872 method = aml_method("_E02", 0, AML_NOTSERIALIZED);
1873 aml_append(method, aml_call0("\\_SB." CPU_SCAN_METHOD));
1874 aml_append(scope, method);
1875
1876 method = aml_method("_E03", 0, AML_NOTSERIALIZED);
1877 aml_append(method, aml_call0(MEMORY_HOTPLUG_HANDLER_PATH));
1878 aml_append(scope, method);
1879
1880 aml_append(scope, aml_method("_L04", 0, AML_NOTSERIALIZED));
1881 aml_append(scope, aml_method("_L05", 0, AML_NOTSERIALIZED));
1882 aml_append(scope, aml_method("_L06", 0, AML_NOTSERIALIZED));
1883 aml_append(scope, aml_method("_L07", 0, AML_NOTSERIALIZED));
1884 aml_append(scope, aml_method("_L08", 0, AML_NOTSERIALIZED));
1885 aml_append(scope, aml_method("_L09", 0, AML_NOTSERIALIZED));
1886 aml_append(scope, aml_method("_L0A", 0, AML_NOTSERIALIZED));
1887 aml_append(scope, aml_method("_L0B", 0, AML_NOTSERIALIZED));
1888 aml_append(scope, aml_method("_L0C", 0, AML_NOTSERIALIZED));
1889 aml_append(scope, aml_method("_L0D", 0, AML_NOTSERIALIZED));
1890 aml_append(scope, aml_method("_L0E", 0, AML_NOTSERIALIZED));
1891 aml_append(scope, aml_method("_L0F", 0, AML_NOTSERIALIZED));
1892 }
1893 aml_append(ssdt, scope);
1894
1895 bus = PC_MACHINE(machine)->bus;
1896 if (bus) {
1897 QLIST_FOREACH(bus, &bus->child, sibling) {
1898 uint8_t bus_num = pci_bus_num(bus);
1899 uint8_t numa_node = pci_bus_numa_node(bus);
1900
1901 /* look only for expander root buses */
1902 if (!pci_bus_is_root(bus)) {
1903 continue;
1904 }
1905
1906 if (bus_num < root_bus_limit) {
1907 root_bus_limit = bus_num - 1;
1908 }
1909
1910 scope = aml_scope("\\_SB");
1911 dev = aml_device("PC%.02X", bus_num);
1912 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
1913 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1914 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
1915
1916 if (numa_node != NUMA_NODE_UNASSIGNED) {
1917 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node)));
1918 }
1919
1920 aml_append(dev, build_prt(false));
1921 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent),
1922 io_ranges, mem_ranges);
1923 aml_append(dev, aml_name_decl("_CRS", crs));
1924 aml_append(scope, dev);
1925 aml_append(ssdt, scope);
1926 }
1927 }
1928
1929 scope = aml_scope("\\_SB.PCI0");
1930 /* build PCI0._CRS */
1931 crs = aml_resource_template();
1932 aml_append(crs,
1933 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
1934 0x0000, 0x0, root_bus_limit,
1935 0x0000, root_bus_limit + 1));
1936 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08));
1937
1938 aml_append(crs,
1939 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1940 AML_POS_DECODE, AML_ENTIRE_RANGE,
1941 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
1942
1943 crs_replace_with_free_ranges(io_ranges, 0x0D00, 0xFFFF);
1944 for (i = 0; i < io_ranges->len; i++) {
1945 entry = g_ptr_array_index(io_ranges, i);
1946 aml_append(crs,
1947 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
1948 AML_POS_DECODE, AML_ENTIRE_RANGE,
1949 0x0000, entry->base, entry->limit,
1950 0x0000, entry->limit - entry->base + 1));
1951 }
1952
1953 aml_append(crs,
1954 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1955 AML_CACHEABLE, AML_READ_WRITE,
1956 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
1957
1958 crs_replace_with_free_ranges(mem_ranges, pci->w32.begin, pci->w32.end - 1);
1959 for (i = 0; i < mem_ranges->len; i++) {
1960 entry = g_ptr_array_index(mem_ranges, i);
1961 aml_append(crs,
1962 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1963 AML_NON_CACHEABLE, AML_READ_WRITE,
1964 0, entry->base, entry->limit,
1965 0, entry->limit - entry->base + 1));
1966 }
1967
1968 if (pci->w64.begin) {
1969 aml_append(crs,
1970 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
1971 AML_CACHEABLE, AML_READ_WRITE,
1972 0, pci->w64.begin, pci->w64.end - 1, 0,
1973 pci->w64.end - pci->w64.begin));
1974 }
1975 aml_append(scope, aml_name_decl("_CRS", crs));
1976
1977 /* reserve GPE0 block resources */
1978 dev = aml_device("GPE0");
1979 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
1980 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources")));
1981 /* device present, functioning, decoding, not shown in UI */
1982 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
1983 crs = aml_resource_template();
1984 aml_append(crs,
1985 aml_io(AML_DECODE16, pm->gpe0_blk, pm->gpe0_blk, 1, pm->gpe0_blk_len)
1986 );
1987 aml_append(dev, aml_name_decl("_CRS", crs));
1988 aml_append(scope, dev);
1989
1990 g_ptr_array_free(io_ranges, true);
1991 g_ptr_array_free(mem_ranges, true);
1992
1993 /* reserve PCIHP resources */
1994 if (pm->pcihp_io_len) {
1995 dev = aml_device("PHPR");
1996 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
1997 aml_append(dev,
1998 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
1999 /* device present, functioning, decoding, not shown in UI */
2000 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2001 crs = aml_resource_template();
2002 aml_append(crs,
2003 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1,
2004 pm->pcihp_io_len)
2005 );
2006 aml_append(dev, aml_name_decl("_CRS", crs));
2007 aml_append(scope, dev);
2008 }
2009 aml_append(ssdt, scope);
2010
2011 /* create S3_ / S4_ / S5_ packages if necessary */
2012 scope = aml_scope("\\");
2013 if (!pm->s3_disabled) {
2014 pkg = aml_package(4);
2015 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */
2016 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2017 aml_append(pkg, aml_int(0)); /* reserved */
2018 aml_append(pkg, aml_int(0)); /* reserved */
2019 aml_append(scope, aml_name_decl("_S3", pkg));
2020 }
2021
2022 if (!pm->s4_disabled) {
2023 pkg = aml_package(4);
2024 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */
2025 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2026 aml_append(pkg, aml_int(pm->s4_val));
2027 aml_append(pkg, aml_int(0)); /* reserved */
2028 aml_append(pkg, aml_int(0)); /* reserved */
2029 aml_append(scope, aml_name_decl("_S4", pkg));
2030 }
2031
2032 pkg = aml_package(4);
2033 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */
2034 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
2035 aml_append(pkg, aml_int(0)); /* reserved */
2036 aml_append(pkg, aml_int(0)); /* reserved */
2037 aml_append(scope, aml_name_decl("_S5", pkg));
2038 aml_append(ssdt, scope);
2039
2040 if (misc->applesmc_io_base) {
2041 scope = aml_scope("\\_SB.PCI0.ISA");
2042 dev = aml_device("SMC");
2043
2044 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001")));
2045 /* device present, functioning, decoding, not shown in UI */
2046 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2047
2048 crs = aml_resource_template();
2049 aml_append(crs,
2050 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base,
2051 0x01, APPLESMC_MAX_DATA_LENGTH)
2052 );
2053 aml_append(crs, aml_irq_no_flags(6));
2054 aml_append(dev, aml_name_decl("_CRS", crs));
2055
2056 aml_append(scope, dev);
2057 aml_append(ssdt, scope);
2058 }
2059
2060 if (misc->pvpanic_port) {
2061 scope = aml_scope("\\_SB.PCI0.ISA");
2062
2063 dev = aml_device("PEVT");
2064 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001")));
2065
2066 crs = aml_resource_template();
2067 aml_append(crs,
2068 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1)
2069 );
2070 aml_append(dev, aml_name_decl("_CRS", crs));
2071
2072 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO,
2073 misc->pvpanic_port, 1));
2074 field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
2075 aml_append(field, aml_named_field("PEPT", 8));
2076 aml_append(dev, field);
2077
2078 /* device present, functioning, decoding, shown in UI */
2079 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
2080
2081 method = aml_method("RDPT", 0, AML_NOTSERIALIZED);
2082 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0)));
2083 aml_append(method, aml_return(aml_local(0)));
2084 aml_append(dev, method);
2085
2086 method = aml_method("WRPT", 1, AML_NOTSERIALIZED);
2087 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT")));
2088 aml_append(dev, method);
2089
2090 aml_append(scope, dev);
2091 aml_append(ssdt, scope);
2092 }
2093
2094 sb_scope = aml_scope("\\_SB");
2095 {
2096 build_processor_devices(sb_scope, guest_info->apic_id_limit, cpu, pm);
2097
2098 build_memory_devices(sb_scope, nr_mem, pm->mem_hp_io_base,
2099 pm->mem_hp_io_len);
2100
2101 {
2102 Object *pci_host;
2103 PCIBus *bus = NULL;
2104
2105 pci_host = acpi_get_i386_pci_host();
2106 if (pci_host) {
2107 bus = PCI_HOST_BRIDGE(pci_host)->bus;
2108 }
2109
2110 if (bus) {
2111 Aml *scope = aml_scope("PCI0");
2112 /* Scan all PCI buses. Generate tables to support hotplug. */
2113 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en);
2114
2115 if (misc->tpm_version != TPM_VERSION_UNSPEC) {
2116 dev = aml_device("ISA.TPM");
2117 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C31")));
2118 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
2119 crs = aml_resource_template();
2120 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
2121 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
2122 aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ));
2123 aml_append(dev, aml_name_decl("_CRS", crs));
2124 aml_append(scope, dev);
2125 }
2126
2127 aml_append(sb_scope, scope);
2128 }
2129 }
2130 aml_append(ssdt, sb_scope);
2131 }
2132
2133 /* copy AML table into ACPI tables blob and patch header there */
2134 g_array_append_vals(table_data, ssdt->buf->data, ssdt->buf->len);
2135 build_header(linker, table_data,
2136 (void *)(table_data->data + table_data->len - ssdt->buf->len),
2137 "SSDT", ssdt->buf->len, 1, NULL);
2138 free_aml_allocator();
2139 }
2140
2141 static void
2142 build_hpet(GArray *table_data, GArray *linker)
2143 {
2144 Acpi20Hpet *hpet;
2145
2146 hpet = acpi_data_push(table_data, sizeof(*hpet));
2147 /* Note timer_block_id value must be kept in sync with value advertised by
2148 * emulated hpet
2149 */
2150 hpet->timer_block_id = cpu_to_le32(0x8086a201);
2151 hpet->addr.address = cpu_to_le64(HPET_BASE);
2152 build_header(linker, table_data,
2153 (void *)hpet, "HPET", sizeof(*hpet), 1, NULL);
2154 }
2155
2156 static void
2157 build_tpm_tcpa(GArray *table_data, GArray *linker, GArray *tcpalog)
2158 {
2159 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa);
2160 uint64_t log_area_start_address = acpi_data_len(tcpalog);
2161
2162 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT);
2163 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE);
2164 tcpa->log_area_start_address = cpu_to_le64(log_area_start_address);
2165
2166 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, 1,
2167 false /* high memory */);
2168
2169 /* log area start address to be filled by Guest linker */
2170 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
2171 ACPI_BUILD_TPMLOG_FILE,
2172 table_data, &tcpa->log_area_start_address,
2173 sizeof(tcpa->log_area_start_address));
2174
2175 build_header(linker, table_data,
2176 (void *)tcpa, "TCPA", sizeof(*tcpa), 2, NULL);
2177
2178 acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE);
2179 }
2180
2181 static void
2182 build_tpm2(GArray *table_data, GArray *linker)
2183 {
2184 Acpi20TPM2 *tpm2_ptr;
2185
2186 tpm2_ptr = acpi_data_push(table_data, sizeof *tpm2_ptr);
2187
2188 tpm2_ptr->platform_class = cpu_to_le16(TPM2_ACPI_CLASS_CLIENT);
2189 tpm2_ptr->control_area_address = cpu_to_le64(0);
2190 tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_MMIO);
2191
2192 build_header(linker, table_data,
2193 (void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4, NULL);
2194 }
2195
2196 typedef enum {
2197 MEM_AFFINITY_NOFLAGS = 0,
2198 MEM_AFFINITY_ENABLED = (1 << 0),
2199 MEM_AFFINITY_HOTPLUGGABLE = (1 << 1),
2200 MEM_AFFINITY_NON_VOLATILE = (1 << 2),
2201 } MemoryAffinityFlags;
2202
2203 static void
2204 acpi_build_srat_memory(AcpiSratMemoryAffinity *numamem, uint64_t base,
2205 uint64_t len, int node, MemoryAffinityFlags flags)
2206 {
2207 numamem->type = ACPI_SRAT_MEMORY;
2208 numamem->length = sizeof(*numamem);
2209 memset(numamem->proximity, 0, 4);
2210 numamem->proximity[0] = node;
2211 numamem->flags = cpu_to_le32(flags);
2212 numamem->base_addr = cpu_to_le64(base);
2213 numamem->range_length = cpu_to_le64(len);
2214 }
2215
2216 static void
2217 build_srat(GArray *table_data, GArray *linker, PcGuestInfo *guest_info)
2218 {
2219 AcpiSystemResourceAffinityTable *srat;
2220 AcpiSratProcessorAffinity *core;
2221 AcpiSratMemoryAffinity *numamem;
2222
2223 int i;
2224 uint64_t curnode;
2225 int srat_start, numa_start, slots;
2226 uint64_t mem_len, mem_base, next_base;
2227 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
2228 ram_addr_t hotplugabble_address_space_size =
2229 object_property_get_int(OBJECT(pcms), PC_MACHINE_MEMHP_REGION_SIZE,
2230 NULL);
2231
2232 srat_start = table_data->len;
2233
2234 srat = acpi_data_push(table_data, sizeof *srat);
2235 srat->reserved1 = cpu_to_le32(1);
2236 core = (void *)(srat + 1);
2237
2238 for (i = 0; i < guest_info->apic_id_limit; ++i) {
2239 core = acpi_data_push(table_data, sizeof *core);
2240 core->type = ACPI_SRAT_PROCESSOR;
2241 core->length = sizeof(*core);
2242 core->local_apic_id = i;
2243 curnode = guest_info->node_cpu[i];
2244 core->proximity_lo = curnode;
2245 memset(core->proximity_hi, 0, 3);
2246 core->local_sapic_eid = 0;
2247 core->flags = cpu_to_le32(1);
2248 }
2249
2250
2251 /* the memory map is a bit tricky, it contains at least one hole
2252 * from 640k-1M and possibly another one from 3.5G-4G.
2253 */
2254 next_base = 0;
2255 numa_start = table_data->len;
2256
2257 numamem = acpi_data_push(table_data, sizeof *numamem);
2258 acpi_build_srat_memory(numamem, 0, 640*1024, 0, MEM_AFFINITY_ENABLED);
2259 next_base = 1024 * 1024;
2260 for (i = 1; i < guest_info->numa_nodes + 1; ++i) {
2261 mem_base = next_base;
2262 mem_len = guest_info->node_mem[i - 1];
2263 if (i == 1) {
2264 mem_len -= 1024 * 1024;
2265 }
2266 next_base = mem_base + mem_len;
2267
2268 /* Cut out the ACPI_PCI hole */
2269 if (mem_base <= guest_info->ram_size_below_4g &&
2270 next_base > guest_info->ram_size_below_4g) {
2271 mem_len -= next_base - guest_info->ram_size_below_4g;
2272 if (mem_len > 0) {
2273 numamem = acpi_data_push(table_data, sizeof *numamem);
2274 acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1,
2275 MEM_AFFINITY_ENABLED);
2276 }
2277 mem_base = 1ULL << 32;
2278 mem_len = next_base - guest_info->ram_size_below_4g;
2279 next_base += (1ULL << 32) - guest_info->ram_size_below_4g;
2280 }
2281 numamem = acpi_data_push(table_data, sizeof *numamem);
2282 acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1,
2283 MEM_AFFINITY_ENABLED);
2284 }
2285 slots = (table_data->len - numa_start) / sizeof *numamem;
2286 for (; slots < guest_info->numa_nodes + 2; slots++) {
2287 numamem = acpi_data_push(table_data, sizeof *numamem);
2288 acpi_build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS);
2289 }
2290
2291 /*
2292 * Entry is required for Windows to enable memory hotplug in OS.
2293 * Memory devices may override proximity set by this entry,
2294 * providing _PXM method if necessary.
2295 */
2296 if (hotplugabble_address_space_size) {
2297 numamem = acpi_data_push(table_data, sizeof *numamem);
2298 acpi_build_srat_memory(numamem, pcms->hotplug_memory.base,
2299 hotplugabble_address_space_size, 0,
2300 MEM_AFFINITY_HOTPLUGGABLE |
2301 MEM_AFFINITY_ENABLED);
2302 }
2303
2304 build_header(linker, table_data,
2305 (void *)(table_data->data + srat_start),
2306 "SRAT",
2307 table_data->len - srat_start, 1, NULL);
2308 }
2309
2310 static void
2311 build_mcfg_q35(GArray *table_data, GArray *linker, AcpiMcfgInfo *info)
2312 {
2313 AcpiTableMcfg *mcfg;
2314 const char *sig;
2315 int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]);
2316
2317 mcfg = acpi_data_push(table_data, len);
2318 mcfg->allocation[0].address = cpu_to_le64(info->mcfg_base);
2319 /* Only a single allocation so no need to play with segments */
2320 mcfg->allocation[0].pci_segment = cpu_to_le16(0);
2321 mcfg->allocation[0].start_bus_number = 0;
2322 mcfg->allocation[0].end_bus_number = PCIE_MMCFG_BUS(info->mcfg_size - 1);
2323
2324 /* MCFG is used for ECAM which can be enabled or disabled by guest.
2325 * To avoid table size changes (which create migration issues),
2326 * always create the table even if there are no allocations,
2327 * but set the signature to a reserved value in this case.
2328 * ACPI spec requires OSPMs to ignore such tables.
2329 */
2330 if (info->mcfg_base == PCIE_BASE_ADDR_UNMAPPED) {
2331 /* Reserved signature: ignored by OSPM */
2332 sig = "QEMU";
2333 } else {
2334 sig = "MCFG";
2335 }
2336 build_header(linker, table_data, (void *)mcfg, sig, len, 1, NULL);
2337 }
2338
2339 static void
2340 build_dmar_q35(GArray *table_data, GArray *linker)
2341 {
2342 int dmar_start = table_data->len;
2343
2344 AcpiTableDmar *dmar;
2345 AcpiDmarHardwareUnit *drhd;
2346
2347 dmar = acpi_data_push(table_data, sizeof(*dmar));
2348 dmar->host_address_width = VTD_HOST_ADDRESS_WIDTH - 1;
2349 dmar->flags = 0; /* No intr_remap for now */
2350
2351 /* DMAR Remapping Hardware Unit Definition structure */
2352 drhd = acpi_data_push(table_data, sizeof(*drhd));
2353 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT);
2354 drhd->length = cpu_to_le16(sizeof(*drhd)); /* No device scope now */
2355 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL;
2356 drhd->pci_segment = cpu_to_le16(0);
2357 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR);
2358
2359 build_header(linker, table_data, (void *)(table_data->data + dmar_start),
2360 "DMAR", table_data->len - dmar_start, 1, NULL);
2361 }
2362
2363 static void
2364 build_dsdt(GArray *table_data, GArray *linker, AcpiMiscInfo *misc)
2365 {
2366 AcpiTableHeader *dsdt;
2367
2368 assert(misc->dsdt_code && misc->dsdt_size);
2369
2370 dsdt = acpi_data_push(table_data, misc->dsdt_size);
2371 memcpy(dsdt, misc->dsdt_code, misc->dsdt_size);
2372
2373 memset(dsdt, 0, sizeof *dsdt);
2374 build_header(linker, table_data, dsdt, "DSDT",
2375 misc->dsdt_size, 1, NULL);
2376 }
2377
2378 static GArray *
2379 build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt)
2380 {
2381 AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp);
2382
2383 bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, 16,
2384 true /* fseg memory */);
2385
2386 memcpy(&rsdp->signature, "RSD PTR ", 8);
2387 memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, 6);
2388 rsdp->rsdt_physical_address = cpu_to_le32(rsdt);
2389 /* Address to be filled by Guest linker */
2390 bios_linker_loader_add_pointer(linker, ACPI_BUILD_RSDP_FILE,
2391 ACPI_BUILD_TABLE_FILE,
2392 rsdp_table, &rsdp->rsdt_physical_address,
2393 sizeof rsdp->rsdt_physical_address);
2394 rsdp->checksum = 0;
2395 /* Checksum to be filled by Guest linker */
2396 bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE,
2397 rsdp, rsdp, sizeof *rsdp, &rsdp->checksum);
2398
2399 return rsdp_table;
2400 }
2401
2402 typedef
2403 struct AcpiBuildState {
2404 /* Copy of table in RAM (for patching). */
2405 MemoryRegion *table_mr;
2406 /* Is table patched? */
2407 uint8_t patched;
2408 PcGuestInfo *guest_info;
2409 void *rsdp;
2410 MemoryRegion *rsdp_mr;
2411 MemoryRegion *linker_mr;
2412 } AcpiBuildState;
2413
2414 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg)
2415 {
2416 Object *pci_host;
2417 QObject *o;
2418
2419 pci_host = acpi_get_i386_pci_host();
2420 g_assert(pci_host);
2421
2422 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL);
2423 if (!o) {
2424 return false;
2425 }
2426 mcfg->mcfg_base = qint_get_int(qobject_to_qint(o));
2427 qobject_decref(o);
2428
2429 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
2430 assert(o);
2431 mcfg->mcfg_size = qint_get_int(qobject_to_qint(o));
2432 qobject_decref(o);
2433 return true;
2434 }
2435
2436 static bool acpi_has_iommu(void)
2437 {
2438 bool ambiguous;
2439 Object *intel_iommu;
2440
2441 intel_iommu = object_resolve_path_type("", TYPE_INTEL_IOMMU_DEVICE,
2442 &ambiguous);
2443 return intel_iommu && !ambiguous;
2444 }
2445
2446 static bool acpi_has_nvdimm(void)
2447 {
2448 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
2449
2450 return pcms->nvdimm;
2451 }
2452
2453 static
2454 void acpi_build(PcGuestInfo *guest_info, AcpiBuildTables *tables)
2455 {
2456 GArray *table_offsets;
2457 unsigned facs, ssdt, dsdt, rsdt;
2458 AcpiCpuInfo cpu;
2459 AcpiPmInfo pm;
2460 AcpiMiscInfo misc;
2461 AcpiMcfgInfo mcfg;
2462 PcPciInfo pci;
2463 uint8_t *u;
2464 size_t aml_len = 0;
2465 GArray *tables_blob = tables->table_data;
2466
2467 acpi_get_cpu_info(&cpu);
2468 acpi_get_pm_info(&pm);
2469 acpi_get_dsdt(&misc);
2470 acpi_get_misc_info(&misc);
2471 acpi_get_pci_info(&pci);
2472
2473 table_offsets = g_array_new(false, true /* clear */,
2474 sizeof(uint32_t));
2475 ACPI_BUILD_DPRINTF("init ACPI tables\n");
2476
2477 bios_linker_loader_alloc(tables->linker, ACPI_BUILD_TABLE_FILE,
2478 64 /* Ensure FACS is aligned */,
2479 false /* high memory */);
2480
2481 /*
2482 * FACS is pointed to by FADT.
2483 * We place it first since it's the only table that has alignment
2484 * requirements.
2485 */
2486 facs = tables_blob->len;
2487 build_facs(tables_blob, tables->linker, guest_info);
2488
2489 /* DSDT is pointed to by FADT */
2490 dsdt = tables_blob->len;
2491 build_dsdt(tables_blob, tables->linker, &misc);
2492
2493 /* Count the size of the DSDT and SSDT, we will need it for legacy
2494 * sizing of ACPI tables.
2495 */
2496 aml_len += tables_blob->len - dsdt;
2497
2498 /* ACPI tables pointed to by RSDT */
2499 acpi_add_table(table_offsets, tables_blob);
2500 build_fadt(tables_blob, tables->linker, &pm, facs, dsdt);
2501
2502 ssdt = tables_blob->len;
2503 acpi_add_table(table_offsets, tables_blob);
2504 build_ssdt(tables_blob, tables->linker, &cpu, &pm, &misc, &pci,
2505 guest_info);
2506 aml_len += tables_blob->len - ssdt;
2507
2508 acpi_add_table(table_offsets, tables_blob);
2509 build_madt(tables_blob, tables->linker, &cpu, guest_info);
2510
2511 if (misc.has_hpet) {
2512 acpi_add_table(table_offsets, tables_blob);
2513 build_hpet(tables_blob, tables->linker);
2514 }
2515 if (misc.tpm_version != TPM_VERSION_UNSPEC) {
2516 acpi_add_table(table_offsets, tables_blob);
2517 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog);
2518
2519 if (misc.tpm_version == TPM_VERSION_2_0) {
2520 acpi_add_table(table_offsets, tables_blob);
2521 build_tpm2(tables_blob, tables->linker);
2522 }
2523 }
2524 if (guest_info->numa_nodes) {
2525 acpi_add_table(table_offsets, tables_blob);
2526 build_srat(tables_blob, tables->linker, guest_info);
2527 }
2528 if (acpi_get_mcfg(&mcfg)) {
2529 acpi_add_table(table_offsets, tables_blob);
2530 build_mcfg_q35(tables_blob, tables->linker, &mcfg);
2531 }
2532 if (acpi_has_iommu()) {
2533 acpi_add_table(table_offsets, tables_blob);
2534 build_dmar_q35(tables_blob, tables->linker);
2535 }
2536
2537 if (acpi_has_nvdimm()) {
2538 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker);
2539 }
2540
2541 /* Add tables supplied by user (if any) */
2542 for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
2543 unsigned len = acpi_table_len(u);
2544
2545 acpi_add_table(table_offsets, tables_blob);
2546 g_array_append_vals(tables_blob, u, len);
2547 }
2548
2549 /* RSDT is pointed to by RSDP */
2550 rsdt = tables_blob->len;
2551 build_rsdt(tables_blob, tables->linker, table_offsets);
2552
2553 /* RSDP is in FSEG memory, so allocate it separately */
2554 build_rsdp(tables->rsdp, tables->linker, rsdt);
2555
2556 /* We'll expose it all to Guest so we want to reduce
2557 * chance of size changes.
2558 *
2559 * We used to align the tables to 4k, but of course this would
2560 * too simple to be enough. 4k turned out to be too small an
2561 * alignment very soon, and in fact it is almost impossible to
2562 * keep the table size stable for all (max_cpus, max_memory_slots)
2563 * combinations. So the table size is always 64k for pc-i440fx-2.1
2564 * and we give an error if the table grows beyond that limit.
2565 *
2566 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
2567 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
2568 * than 2.0 and we can always pad the smaller tables with zeros. We can
2569 * then use the exact size of the 2.0 tables.
2570 *
2571 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
2572 */
2573 if (guest_info->legacy_acpi_table_size) {
2574 /* Subtracting aml_len gives the size of fixed tables. Then add the
2575 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
2576 */
2577 int legacy_aml_len =
2578 guest_info->legacy_acpi_table_size +
2579 ACPI_BUILD_LEGACY_CPU_AML_SIZE * max_cpus;
2580 int legacy_table_size =
2581 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len,
2582 ACPI_BUILD_ALIGN_SIZE);
2583 if (tables_blob->len > legacy_table_size) {
2584 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
2585 error_report("Warning: migration may not work.");
2586 }
2587 g_array_set_size(tables_blob, legacy_table_size);
2588 } else {
2589 /* Make sure we have a buffer in case we need to resize the tables. */
2590 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
2591 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
2592 error_report("Warning: ACPI tables are larger than 64k.");
2593 error_report("Warning: migration may not work.");
2594 error_report("Warning: please remove CPUs, NUMA nodes, "
2595 "memory slots or PCI bridges.");
2596 }
2597 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
2598 }
2599
2600 acpi_align_size(tables->linker, ACPI_BUILD_ALIGN_SIZE);
2601
2602 /* Cleanup memory that's no longer used. */
2603 g_array_free(table_offsets, true);
2604 }
2605
2606 static void acpi_ram_update(MemoryRegion *mr, GArray *data)
2607 {
2608 uint32_t size = acpi_data_len(data);
2609
2610 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
2611 memory_region_ram_resize(mr, size, &error_abort);
2612
2613 memcpy(memory_region_get_ram_ptr(mr), data->data, size);
2614 memory_region_set_dirty(mr, 0, size);
2615 }
2616
2617 static void acpi_build_update(void *build_opaque)
2618 {
2619 AcpiBuildState *build_state = build_opaque;
2620 AcpiBuildTables tables;
2621
2622 /* No state to update or already patched? Nothing to do. */
2623 if (!build_state || build_state->patched) {
2624 return;
2625 }
2626 build_state->patched = 1;
2627
2628 acpi_build_tables_init(&tables);
2629
2630 acpi_build(build_state->guest_info, &tables);
2631
2632 acpi_ram_update(build_state->table_mr, tables.table_data);
2633
2634 if (build_state->rsdp) {
2635 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp));
2636 } else {
2637 acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
2638 }
2639
2640 acpi_ram_update(build_state->linker_mr, tables.linker);
2641 acpi_build_tables_cleanup(&tables, true);
2642 }
2643
2644 static void acpi_build_reset(void *build_opaque)
2645 {
2646 AcpiBuildState *build_state = build_opaque;
2647 build_state->patched = 0;
2648 }
2649
2650 static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state,
2651 GArray *blob, const char *name,
2652 uint64_t max_size)
2653 {
2654 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1,
2655 name, acpi_build_update, build_state);
2656 }
2657
2658 static const VMStateDescription vmstate_acpi_build = {
2659 .name = "acpi_build",
2660 .version_id = 1,
2661 .minimum_version_id = 1,
2662 .fields = (VMStateField[]) {
2663 VMSTATE_UINT8(patched, AcpiBuildState),
2664 VMSTATE_END_OF_LIST()
2665 },
2666 };
2667
2668 void acpi_setup(PcGuestInfo *guest_info)
2669 {
2670 AcpiBuildTables tables;
2671 AcpiBuildState *build_state;
2672
2673 if (!guest_info->fw_cfg) {
2674 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
2675 return;
2676 }
2677
2678 if (!guest_info->has_acpi_build) {
2679 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
2680 return;
2681 }
2682
2683 if (!acpi_enabled) {
2684 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
2685 return;
2686 }
2687
2688 build_state = g_malloc0(sizeof *build_state);
2689
2690 build_state->guest_info = guest_info;
2691
2692 acpi_set_pci_info();
2693
2694 acpi_build_tables_init(&tables);
2695 acpi_build(build_state->guest_info, &tables);
2696
2697 /* Now expose it all to Guest */
2698 build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data,
2699 ACPI_BUILD_TABLE_FILE,
2700 ACPI_BUILD_TABLE_MAX_SIZE);
2701 assert(build_state->table_mr != NULL);
2702
2703 build_state->linker_mr =
2704 acpi_add_rom_blob(build_state, tables.linker, "etc/table-loader", 0);
2705
2706 fw_cfg_add_file(guest_info->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
2707 tables.tcpalog->data, acpi_data_len(tables.tcpalog));
2708
2709 if (!guest_info->rsdp_in_ram) {
2710 /*
2711 * Keep for compatibility with old machine types.
2712 * Though RSDP is small, its contents isn't immutable, so
2713 * we'll update it along with the rest of tables on guest access.
2714 */
2715 uint32_t rsdp_size = acpi_data_len(tables.rsdp);
2716
2717 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size);
2718 fw_cfg_add_file_callback(guest_info->fw_cfg, ACPI_BUILD_RSDP_FILE,
2719 acpi_build_update, build_state,
2720 build_state->rsdp, rsdp_size);
2721 build_state->rsdp_mr = NULL;
2722 } else {
2723 build_state->rsdp = NULL;
2724 build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp,
2725 ACPI_BUILD_RSDP_FILE, 0);
2726 }
2727
2728 qemu_register_reset(acpi_build_reset, build_state);
2729 acpi_build_reset(build_state);
2730 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state);
2731
2732 /* Cleanup tables but don't free the memory: we track it
2733 * in build_state.
2734 */
2735 acpi_build_tables_cleanup(&tables, false);
2736 }
QEmu