target-sh4/helper.c

   1 /*
   2  *  SH4 emulation
   3  *
   4  *  Copyright (c) 2005 Samuel Tardieu
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include <stdarg.h>
  20 #include <stdlib.h>
  21 #include <stdio.h>
  22 #include <string.h>
  23 #include <inttypes.h>
  24 #include <signal.h>
  25
  26 #include "cpu.h"
  27 #include "exec-all.h"
  28 #include "hw/sh_intc.h"
  29
  30 #if defined(CONFIG_USER_ONLY)
  31
  32 void do_interrupt (CPUState *env)
  33 {
  34   env->exception_index = -1;
  35 }
  36
  37 int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
  38                              int mmu_idx, int is_softmmu)
  39 {
  40     env->tea = address;
  41     env->exception_index = -1;
  42     switch (rw) {
  43     case 0:
  44         env->exception_index = 0x0a0;
  45         break;
  46     case 1:
  47         env->exception_index = 0x0c0;
  48         break;
  49     case 2:
  50         env->exception_index = 0x0a0;
  51         break;
  52     }
  53     return 1;
  54 }
  55
  56 int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
  57 {
  58     /* For user mode, only U0 area is cachable. */
  59     return !(addr & 0x80000000);
  60 }
  61
  62 #else /* !CONFIG_USER_ONLY */
  63
  64 #define MMU_OK                   0
  65 #define MMU_ITLB_MISS            (-1)
  66 #define MMU_ITLB_MULTIPLE        (-2)
  67 #define MMU_ITLB_VIOLATION       (-3)
  68 #define MMU_DTLB_MISS_READ       (-4)
  69 #define MMU_DTLB_MISS_WRITE      (-5)
  70 #define MMU_DTLB_INITIAL_WRITE   (-6)
  71 #define MMU_DTLB_VIOLATION_READ  (-7)
  72 #define MMU_DTLB_VIOLATION_WRITE (-8)
  73 #define MMU_DTLB_MULTIPLE        (-9)
  74 #define MMU_DTLB_MISS            (-10)
  75 #define MMU_IADDR_ERROR          (-11)
  76 #define MMU_DADDR_ERROR_READ     (-12)
  77 #define MMU_DADDR_ERROR_WRITE    (-13)
  78
  79 void do_interrupt(CPUState * env)
  80 {
  81     int do_irq = env->interrupt_request & CPU_INTERRUPT_HARD;
  82     int do_exp, irq_vector = env->exception_index;
  83
  84     /* prioritize exceptions over interrupts */
  85
  86     do_exp = env->exception_index != -1;
  87     do_irq = do_irq && (env->exception_index == -1);
  88
  89     if (env->sr & SR_BL) {
  90         if (do_exp && env->exception_index != 0x1e0) {
  91             env->exception_index = 0x000; /* masked exception -> reset */
  92         }
  93         if (do_irq && !env->intr_at_halt) {
  94             return; /* masked */
  95         }
  96         env->intr_at_halt = 0;
  97     }
  98
  99     if (do_irq) {
 100         irq_vector = sh_intc_get_pending_vector(env->intc_handle,
 101                                                 (env->sr >> 4) & 0xf);
 102         if (irq_vector == -1) {
 103             return; /* masked */
 104         }
 105     }
 106
 107     if (qemu_loglevel_mask(CPU_LOG_INT)) {
 108         const char *expname;
 109         switch (env->exception_index) {
 110         case 0x0e0:
 111             expname = "addr_error";
 112             break;
 113         case 0x040:
 114             expname = "tlb_miss";
 115             break;
 116         case 0x0a0:
 117             expname = "tlb_violation";
 118             break;
 119         case 0x180:
 120             expname = "illegal_instruction";
 121             break;
 122         case 0x1a0:
 123             expname = "slot_illegal_instruction";
 124             break;
 125         case 0x800:
 126             expname = "fpu_disable";
 127             break;
 128         case 0x820:
 129             expname = "slot_fpu";
 130             break;
 131         case 0x100:
 132             expname = "data_write";
 133             break;
 134         case 0x060:
 135             expname = "dtlb_miss_write";
 136             break;
 137         case 0x0c0:
 138             expname = "dtlb_violation_write";
 139             break;
 140         case 0x120:
 141             expname = "fpu_exception";
 142             break;
 143         case 0x080:
 144             expname = "initial_page_write";
 145             break;
 146         case 0x160:
 147             expname = "trapa";
 148             break;
 149         default:
 150             expname = do_irq ? "interrupt" : "???";
 151             break;
 152         }
 153         qemu_log("exception 0x%03x [%s] raised\n",
 154                   irq_vector, expname);
 155         log_cpu_state(env, 0);
 156     }
 157
 158     env->ssr = env->sr;
 159     env->spc = env->pc;
 160     env->sgr = env->gregs[15];
 161     env->sr |= SR_BL | SR_MD | SR_RB;
 162
 163     if (env->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {
 164         /* Branch instruction should be executed again before delay slot. */
 165         env->spc -= 2;
 166         /* Clear flags for exception/interrupt routine. */
 167         env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL | DELAY_SLOT_TRUE);
 168     }
 169     if (env->flags & DELAY_SLOT_CLEARME)
 170         env->flags = 0;
 171
 172     if (do_exp) {
 173         env->expevt = env->exception_index;
 174         switch (env->exception_index) {
 175         case 0x000:
 176         case 0x020:
 177         case 0x140:
 178             env->sr &= ~SR_FD;
 179             env->sr |= 0xf << 4; /* IMASK */
 180             env->pc = 0xa0000000;
 181             break;
 182         case 0x040:
 183         case 0x060:
 184             env->pc = env->vbr + 0x400;
 185             break;
 186         case 0x160:
 187             env->spc += 2; /* special case for TRAPA */
 188             /* fall through */
 189         default:
 190             env->pc = env->vbr + 0x100;
 191             break;
 192         }
 193         return;
 194     }
 195
 196     if (do_irq) {
 197         env->intevt = irq_vector;
 198         env->pc = env->vbr + 0x600;
 199         return;
 200     }
 201 }
 202
 203 static void update_itlb_use(CPUState * env, int itlbnb)
 204 {
 205     uint8_t or_mask = 0, and_mask = (uint8_t) - 1;
 206
 207     switch (itlbnb) {
 208     case 0:
 209         and_mask = 0x1f;
 210         break;
 211     case 1:
 212         and_mask = 0xe7;
 213         or_mask = 0x80;
 214         break;
 215     case 2:
 216         and_mask = 0xfb;
 217         or_mask = 0x50;
 218         break;
 219     case 3:
 220         or_mask = 0x2c;
 221         break;
 222     }
 223
 224     env->mmucr &= (and_mask << 24) | 0x00ffffff;
 225     env->mmucr |= (or_mask << 24);
 226 }
 227
 228 static int itlb_replacement(CPUState * env)
 229 {
 230     if ((env->mmucr & 0xe0000000) == 0xe0000000)
 231         return 0;
 232     if ((env->mmucr & 0x98000000) == 0x18000000)
 233         return 1;
 234     if ((env->mmucr & 0x54000000) == 0x04000000)
 235         return 2;
 236     if ((env->mmucr & 0x2c000000) == 0x00000000)
 237         return 3;
 238     cpu_abort(env, "Unhandled itlb_replacement");
 239 }
 240
 241 /* Find the corresponding entry in the right TLB
 242    Return entry, MMU_DTLB_MISS or MMU_DTLB_MULTIPLE
 243 */
 244 static int find_tlb_entry(CPUState * env, target_ulong address,
 245                           tlb_t * entries, uint8_t nbtlb, int use_asid)
 246 {
 247     int match = MMU_DTLB_MISS;
 248     uint32_t start, end;
 249     uint8_t asid;
 250     int i;
 251
 252     asid = env->pteh & 0xff;
 253
 254     for (i = 0; i < nbtlb; i++) {
 255         if (!entries[i].v)
 256             continue;           /* Invalid entry */
 257         if (!entries[i].sh && use_asid && entries[i].asid != asid)
 258             continue;           /* Bad ASID */
 259         start = (entries[i].vpn << 10) & ~(entries[i].size - 1);
 260         end = start + entries[i].size - 1;
 261         if (address >= start && address <= end) {       /* Match */
 262             if (match != MMU_DTLB_MISS)
 263                 return MMU_DTLB_MULTIPLE;       /* Multiple match */
 264             match = i;
 265         }
 266     }
 267     return match;
 268 }
 269
 270 static void increment_urc(CPUState * env)
 271 {
 272     uint8_t urb, urc;
 273
 274     /* Increment URC */
 275     urb = ((env->mmucr) >> 18) & 0x3f;
 276     urc = ((env->mmucr) >> 10) & 0x3f;
 277     urc++;
 278     if ((urb > 0 && urc > urb) || urc > (UTLB_SIZE - 1))
 279         urc = 0;
 280     env->mmucr = (env->mmucr & 0xffff03ff) | (urc << 10);
 281 }
 282
 283 /* Copy and utlb entry into itlb
 284    Return entry
 285 */
 286 static int copy_utlb_entry_itlb(CPUState *env, int utlb)
 287 {
 288     int itlb;
 289
 290     tlb_t * ientry;
 291     itlb = itlb_replacement(env);
 292     ientry = &env->itlb[itlb];
 293     if (ientry->v) {
 294         tlb_flush_page(env, ientry->vpn << 10);
 295     }
 296     *ientry = env->utlb[utlb];
 297     update_itlb_use(env, itlb);
 298     return itlb;
 299 }
 300
 301 /* Find itlb entry
 302    Return entry, MMU_ITLB_MISS, MMU_ITLB_MULTIPLE or MMU_DTLB_MULTIPLE
 303 */
 304 static int find_itlb_entry(CPUState * env, target_ulong address,
 305                            int use_asid)
 306 {
 307     int e;
 308
 309     e = find_tlb_entry(env, address, env->itlb, ITLB_SIZE, use_asid);
 310     if (e == MMU_DTLB_MULTIPLE) {
 311         e = MMU_ITLB_MULTIPLE;
 312     } else if (e == MMU_DTLB_MISS) {
 313         e = MMU_ITLB_MISS;
 314     } else if (e >= 0) {
 315         update_itlb_use(env, e);
 316     }
 317     return e;
 318 }
 319
 320 /* Find utlb entry
 321    Return entry, MMU_DTLB_MISS, MMU_DTLB_MULTIPLE */
 322 static int find_utlb_entry(CPUState * env, target_ulong address, int use_asid)
 323 {
 324     /* per utlb access */
 325     increment_urc(env);
 326
 327     /* Return entry */
 328     return find_tlb_entry(env, address, env->utlb, UTLB_SIZE, use_asid);
 329 }
 330
 331 /* Match address against MMU
 332    Return MMU_OK, MMU_DTLB_MISS_READ, MMU_DTLB_MISS_WRITE,
 333    MMU_DTLB_INITIAL_WRITE, MMU_DTLB_VIOLATION_READ,
 334    MMU_DTLB_VIOLATION_WRITE, MMU_ITLB_MISS,
 335    MMU_ITLB_MULTIPLE, MMU_ITLB_VIOLATION,
 336    MMU_IADDR_ERROR, MMU_DADDR_ERROR_READ, MMU_DADDR_ERROR_WRITE.
 337 */
 338 static int get_mmu_address(CPUState * env, target_ulong * physical,
 339                            int *prot, target_ulong address,
 340                            int rw, int access_type)
 341 {
 342     int use_asid, n;
 343     tlb_t *matching = NULL;
 344
 345     use_asid = (env->mmucr & MMUCR_SV) == 0 || (env->sr & SR_MD) == 0;
 346
 347     if (rw == 2) {
 348         n = find_itlb_entry(env, address, use_asid);
 349         if (n >= 0) {
 350             matching = &env->itlb[n];
 351             if (!(env->sr & SR_MD) && !(matching->pr & 2))
 352                 n = MMU_ITLB_VIOLATION;
 353             else
 354                 *prot = PAGE_EXEC;
 355         } else {
 356             n = find_utlb_entry(env, address, use_asid);
 357             if (n >= 0) {
 358                 n = copy_utlb_entry_itlb(env, n);
 359                 matching = &env->itlb[n];
 360                 if (!(env->sr & SR_MD) && !(matching->pr & 2)) {
 361                       n = MMU_ITLB_VIOLATION;
 362                 } else {
 363                     *prot = PAGE_READ | PAGE_EXEC;
 364                     if ((matching->pr & 1) && matching->d) {
 365                         *prot |= PAGE_WRITE;
 366                     }
 367                 }
 368             } else if (n == MMU_DTLB_MULTIPLE) {
 369                 n = MMU_ITLB_MULTIPLE;
 370             } else if (n == MMU_DTLB_MISS) {
 371                 n = MMU_ITLB_MISS;
 372             }
 373         }
 374     } else {
 375         n = find_utlb_entry(env, address, use_asid);
 376         if (n >= 0) {
 377             matching = &env->utlb[n];
 378             if (!(env->sr & SR_MD) && !(matching->pr & 2)) {
 379                 n = (rw == 1) ? MMU_DTLB_VIOLATION_WRITE :
 380                     MMU_DTLB_VIOLATION_READ;
 381             } else if ((rw == 1) && !(matching->pr & 1)) {
 382                 n = MMU_DTLB_VIOLATION_WRITE;
 383             } else if ((rw == 1) && !matching->d) {
 384                 n = MMU_DTLB_INITIAL_WRITE;
 385             } else {
 386                 *prot = PAGE_READ;
 387                 if ((matching->pr & 1) && matching->d) {
 388                     *prot |= PAGE_WRITE;
 389                 }
 390             }
 391         } else if (n == MMU_DTLB_MISS) {
 392             n = (rw == 1) ? MMU_DTLB_MISS_WRITE :
 393                 MMU_DTLB_MISS_READ;
 394         }
 395     }
 396     if (n >= 0) {
 397         n = MMU_OK;
 398         *physical = ((matching->ppn << 10) & ~(matching->size - 1)) |
 399             (address & (matching->size - 1));
 400     }
 401     return n;
 402 }
 403
 404 static int get_physical_address(CPUState * env, target_ulong * physical,
 405                                 int *prot, target_ulong address,
 406                                 int rw, int access_type)
 407 {
 408     /* P1, P2 and P4 areas do not use translation */
 409     if ((address >= 0x80000000 && address < 0xc0000000) ||
 410         address >= 0xe0000000) {
 411         if (!(env->sr & SR_MD)
 412             && (address < 0xe0000000 || address >= 0xe4000000)) {
 413             /* Unauthorized access in user mode (only store queues are available) */
 414             fprintf(stderr, "Unauthorized access\n");
 415             if (rw == 0)
 416                 return MMU_DADDR_ERROR_READ;
 417             else if (rw == 1)
 418                 return MMU_DADDR_ERROR_WRITE;
 419             else
 420                 return MMU_IADDR_ERROR;
 421         }
 422         if (address >= 0x80000000 && address < 0xc0000000) {
 423             /* Mask upper 3 bits for P1 and P2 areas */
 424             *physical = address & 0x1fffffff;
 425         } else {
 426             *physical = address;
 427         }
 428         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 429         return MMU_OK;
 430     }
 431
 432     /* If MMU is disabled, return the corresponding physical page */
 433     if (!(env->mmucr & MMUCR_AT)) {
 434         *physical = address & 0x1FFFFFFF;
 435         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 436         return MMU_OK;
 437     }
 438
 439     /* We need to resort to the MMU */
 440     return get_mmu_address(env, physical, prot, address, rw, access_type);
 441 }
 442
 443 int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
 444                              int mmu_idx, int is_softmmu)
 445 {
 446     target_ulong physical;
 447     int prot, ret, access_type;
 448
 449     access_type = ACCESS_INT;
 450     ret =
 451         get_physical_address(env, &physical, &prot, address, rw,
 452                              access_type);
 453
 454     if (ret != MMU_OK) {
 455         env->tea = address;
 456         switch (ret) {
 457         case MMU_ITLB_MISS:
 458         case MMU_DTLB_MISS_READ:
 459             env->exception_index = 0x040;
 460             break;
 461         case MMU_DTLB_MULTIPLE:
 462         case MMU_ITLB_MULTIPLE:
 463             env->exception_index = 0x140;
 464             break;
 465         case MMU_ITLB_VIOLATION:
 466             env->exception_index = 0x0a0;
 467             break;
 468         case MMU_DTLB_MISS_WRITE:
 469             env->exception_index = 0x060;
 470             break;
 471         case MMU_DTLB_INITIAL_WRITE:
 472             env->exception_index = 0x080;
 473             break;
 474         case MMU_DTLB_VIOLATION_READ:
 475             env->exception_index = 0x0a0;
 476             break;
 477         case MMU_DTLB_VIOLATION_WRITE:
 478             env->exception_index = 0x0c0;
 479             break;
 480         case MMU_IADDR_ERROR:
 481         case MMU_DADDR_ERROR_READ:
 482             env->exception_index = 0x0c0;
 483             break;
 484         case MMU_DADDR_ERROR_WRITE:
 485             env->exception_index = 0x100;
 486             break;
 487         default:
 488             cpu_abort(env, "Unhandled MMU fault");
 489         }
 490         return 1;
 491     }
 492
 493     address &= TARGET_PAGE_MASK;
 494     physical &= TARGET_PAGE_MASK;
 495
 496     tlb_set_page(env, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE);
 497     return 0;
 498 }
 499
 500 target_phys_addr_t cpu_get_phys_page_debug(CPUState * env, target_ulong addr)
 501 {
 502     target_ulong physical;
 503     int prot;
 504
 505     get_physical_address(env, &physical, &prot, addr, 0, 0);
 506     return physical;
 507 }
 508
 509 void cpu_load_tlb(CPUSH4State * env)
 510 {
 511     int n = cpu_mmucr_urc(env->mmucr);
 512     tlb_t * entry = &env->utlb[n];
 513
 514     if (entry->v) {
 515         /* Overwriting valid entry in utlb. */
 516         target_ulong address = entry->vpn << 10;
 517         tlb_flush_page(env, address);
 518     }
 519
 520     /* Take values into cpu status from registers. */
 521     entry->asid = (uint8_t)cpu_pteh_asid(env->pteh);
 522     entry->vpn  = cpu_pteh_vpn(env->pteh);
 523     entry->v    = (uint8_t)cpu_ptel_v(env->ptel);
 524     entry->ppn  = cpu_ptel_ppn(env->ptel);
 525     entry->sz   = (uint8_t)cpu_ptel_sz(env->ptel);
 526     switch (entry->sz) {
 527     case 0: /* 00 */
 528         entry->size = 1024; /* 1K */
 529         break;
 530     case 1: /* 01 */
 531         entry->size = 1024 * 4; /* 4K */
 532         break;
 533     case 2: /* 10 */
 534         entry->size = 1024 * 64; /* 64K */
 535         break;
 536     case 3: /* 11 */
 537         entry->size = 1024 * 1024; /* 1M */
 538         break;
 539     default:
 540         cpu_abort(env, "Unhandled load_tlb");
 541         break;
 542     }
 543     entry->sh   = (uint8_t)cpu_ptel_sh(env->ptel);
 544     entry->c    = (uint8_t)cpu_ptel_c(env->ptel);
 545     entry->pr   = (uint8_t)cpu_ptel_pr(env->ptel);
 546     entry->d    = (uint8_t)cpu_ptel_d(env->ptel);
 547     entry->wt   = (uint8_t)cpu_ptel_wt(env->ptel);
 548     entry->sa   = (uint8_t)cpu_ptea_sa(env->ptea);
 549     entry->tc   = (uint8_t)cpu_ptea_tc(env->ptea);
 550 }
 551
 552  void cpu_sh4_invalidate_tlb(CPUSH4State *s)
 553 {
 554     int i;
 555
 556     /* UTLB */
 557     for (i = 0; i < UTLB_SIZE; i++) {
 558         tlb_t * entry = &s->utlb[i];
 559         entry->v = 0;
 560     }
 561     /* ITLB */
 562     for (i = 0; i < UTLB_SIZE; i++) {
 563         tlb_t * entry = &s->utlb[i];
 564         entry->v = 0;
 565     }
 566
 567     tlb_flush(s, 1);
 568 }
 569
 570 void cpu_sh4_write_mmaped_itlb_addr(CPUSH4State *s, target_phys_addr_t addr,
 571                                     uint32_t mem_value)
 572 {
 573     uint32_t vpn = (mem_value & 0xfffffc00) >> 10;
 574     uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8);
 575     uint8_t asid = (uint8_t)(mem_value & 0x000000ff);
 576
 577     int index = (addr & 0x00003f00) >> 8;
 578     tlb_t * entry = &s->itlb[index];
 579     if (entry->v) {
 580         /* Overwriting valid entry in itlb. */
 581         target_ulong address = entry->vpn << 10;
 582         tlb_flush_page(s, address);
 583     }
 584     entry->asid = asid;
 585     entry->vpn = vpn;
 586     entry->v = v;
 587 }
 588
 589 void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
 590                                     uint32_t mem_value)
 591 {
 592     int associate = addr & 0x0000080;
 593     uint32_t vpn = (mem_value & 0xfffffc00) >> 10;
 594     uint8_t d = (uint8_t)((mem_value & 0x00000200) >> 9);
 595     uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8);
 596     uint8_t asid = (uint8_t)(mem_value & 0x000000ff);
 597     int use_asid = (s->mmucr & MMUCR_SV) == 0 || (s->sr & SR_MD) == 0;
 598
 599     if (associate) {
 600         int i;
 601         tlb_t * utlb_match_entry = NULL;
 602         int needs_tlb_flush = 0;
 603
 604         /* search UTLB */
 605         for (i = 0; i < UTLB_SIZE; i++) {
 606             tlb_t * entry = &s->utlb[i];
 607             if (!entry->v)
 608                 continue;
 609
 610             if (entry->vpn == vpn
 611                 && (!use_asid || entry->asid == asid || entry->sh)) {
 612                 if (utlb_match_entry) {
 613                     /* Multiple TLB Exception */
 614                     s->exception_index = 0x140;
 615                     s->tea = addr;
 616                     break;
 617                 }
 618                 if (entry->v && !v)
 619                     needs_tlb_flush = 1;
 620                 entry->v = v;
 621                 entry->d = d;
 622                 utlb_match_entry = entry;
 623             }
 624             increment_urc(s); /* per utlb access */
 625         }
 626
 627         /* search ITLB */
 628         for (i = 0; i < ITLB_SIZE; i++) {
 629             tlb_t * entry = &s->itlb[i];
 630             if (entry->vpn == vpn
 631                 && (!use_asid || entry->asid == asid || entry->sh)) {
 632                 if (entry->v && !v)
 633                     needs_tlb_flush = 1;
 634                 if (utlb_match_entry)
 635                     *entry = *utlb_match_entry;
 636                 else
 637                     entry->v = v;
 638                 break;
 639             }
 640         }
 641
 642         if (needs_tlb_flush)
 643             tlb_flush_page(s, vpn << 10);
 644
 645     } else {
 646         int index = (addr & 0x00003f00) >> 8;
 647         tlb_t * entry = &s->utlb[index];
 648         if (entry->v) {
 649             /* Overwriting valid entry in utlb. */
 650             target_ulong address = entry->vpn << 10;
 651             tlb_flush_page(s, address);
 652         }
 653         entry->asid = asid;
 654         entry->vpn = vpn;
 655         entry->d = d;
 656         entry->v = v;
 657         increment_urc(s);
 658     }
 659 }
 660
 661 int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
 662 {
 663     int n;
 664     int use_asid = (env->mmucr & MMUCR_SV) == 0 || (env->sr & SR_MD) == 0;
 665
 666     /* check area */
 667     if (env->sr & SR_MD) {
 668         /* For previledged mode, P2 and P4 area is not cachable. */
 669         if ((0xA0000000 <= addr && addr < 0xC0000000) || 0xE0000000 <= addr)
 670             return 0;
 671     } else {
 672         /* For user mode, only U0 area is cachable. */
 673         if (0x80000000 <= addr)
 674             return 0;
 675     }
 676
 677     /*
 678      * TODO : Evaluate CCR and check if the cache is on or off.
 679      *        Now CCR is not in CPUSH4State, but in SH7750State.
 680      *        When you move the ccr inot CPUSH4State, the code will be
 681      *        as follows.
 682      */
 683 #if 0
 684     /* check if operand cache is enabled or not. */
 685     if (!(env->ccr & 1))
 686         return 0;
 687 #endif
 688
 689     /* if MMU is off, no check for TLB. */
 690     if (env->mmucr & MMUCR_AT)
 691         return 1;
 692
 693     /* check TLB */
 694     n = find_tlb_entry(env, addr, env->itlb, ITLB_SIZE, use_asid);
 695     if (n >= 0)
 696         return env->itlb[n].c;
 697
 698     n = find_tlb_entry(env, addr, env->utlb, UTLB_SIZE, use_asid);
 699     if (n >= 0)
 700         return env->utlb[n].c;
 701
 702     return 0;
 703 }
 704
 705 #endif