target-sparc/machine.c

   1 #include "hw/hw.h"
   2 #include "hw/boards.h"
   3 #include "qemu-timer.h"
   4
   5 #include "cpu.h"
   6
   7 void cpu_save(QEMUFile *f, void *opaque)
   8 {
   9     CPUState *env = opaque;
  10     int i;
  11     uint32_t tmp;
  12
  13     // if env->cwp == env->nwindows - 1, this will set the ins of the last
  14     // window as the outs of the first window
  15     cpu_set_cwp(env, env->cwp);
  16
  17     for(i = 0; i < 8; i++)
  18         qemu_put_betls(f, &env->gregs[i]);
  19     qemu_put_be32s(f, &env->nwindows);
  20     for(i = 0; i < env->nwindows * 16; i++)
  21         qemu_put_betls(f, &env->regbase[i]);
  22
  23     /* FPU */
  24     for(i = 0; i < TARGET_FPREGS; i++) {
  25         union {
  26             float32 f;
  27             uint32_t i;
  28         } u;
  29         u.f = env->fpr[i];
  30         qemu_put_be32(f, u.i);
  31     }
  32
  33     qemu_put_betls(f, &env->pc);
  34     qemu_put_betls(f, &env->npc);
  35     qemu_put_betls(f, &env->y);
  36     tmp = cpu_get_psr(env);
  37     qemu_put_be32(f, tmp);
  38     qemu_put_betls(f, &env->fsr);
  39     qemu_put_betls(f, &env->tbr);
  40     tmp = env->interrupt_index;
  41     qemu_put_be32(f, tmp);
  42     qemu_put_be32s(f, &env->pil_in);
  43 #ifndef TARGET_SPARC64
  44     qemu_put_be32s(f, &env->wim);
  45     /* MMU */
  46     for (i = 0; i < 32; i++)
  47         qemu_put_be32s(f, &env->mmuregs[i]);
  48     for (i = 0; i < 4; i++) {
  49         qemu_put_be64s(f, &env->mxccdata[i]);
  50     }
  51     for (i = 0; i < 8; i++) {
  52         qemu_put_be64s(f, &env->mxccregs[i]);
  53     }
  54     qemu_put_be32s(f, &env->mmubpctrv);
  55     qemu_put_be32s(f, &env->mmubpctrc);
  56     qemu_put_be32s(f, &env->mmubpctrs);
  57     qemu_put_be64s(f, &env->mmubpaction);
  58     for (i = 0; i < 4; i++) {
  59         qemu_put_be64s(f, &env->mmubpregs[i]);
  60     }
  61 #else
  62     qemu_put_be64s(f, &env->lsu);
  63     for (i = 0; i < 16; i++) {
  64         qemu_put_be64s(f, &env->immuregs[i]);
  65         qemu_put_be64s(f, &env->dmmuregs[i]);
  66     }
  67     for (i = 0; i < 64; i++) {
  68         qemu_put_be64s(f, &env->itlb[i].tag);
  69         qemu_put_be64s(f, &env->itlb[i].tte);
  70         qemu_put_be64s(f, &env->dtlb[i].tag);
  71         qemu_put_be64s(f, &env->dtlb[i].tte);
  72     }
  73     qemu_put_be32s(f, &env->mmu_version);
  74     for (i = 0; i < MAXTL_MAX; i++) {
  75         qemu_put_be64s(f, &env->ts[i].tpc);
  76         qemu_put_be64s(f, &env->ts[i].tnpc);
  77         qemu_put_be64s(f, &env->ts[i].tstate);
  78         qemu_put_be32s(f, &env->ts[i].tt);
  79     }
  80     qemu_put_be32s(f, &env->xcc);
  81     qemu_put_be32s(f, &env->asi);
  82     qemu_put_be32s(f, &env->pstate);
  83     qemu_put_be32s(f, &env->tl);
  84     qemu_put_be32s(f, &env->cansave);
  85     qemu_put_be32s(f, &env->canrestore);
  86     qemu_put_be32s(f, &env->otherwin);
  87     qemu_put_be32s(f, &env->wstate);
  88     qemu_put_be32s(f, &env->cleanwin);
  89     for (i = 0; i < 8; i++)
  90         qemu_put_be64s(f, &env->agregs[i]);
  91     for (i = 0; i < 8; i++)
  92         qemu_put_be64s(f, &env->bgregs[i]);
  93     for (i = 0; i < 8; i++)
  94         qemu_put_be64s(f, &env->igregs[i]);
  95     for (i = 0; i < 8; i++)
  96         qemu_put_be64s(f, &env->mgregs[i]);
  97     qemu_put_be64s(f, &env->fprs);
  98     qemu_put_be64s(f, &env->tick_cmpr);
  99     qemu_put_be64s(f, &env->stick_cmpr);
 100     cpu_put_timer(f, env->tick);
 101     cpu_put_timer(f, env->stick);
 102     qemu_put_be64s(f, &env->gsr);
 103     qemu_put_be32s(f, &env->gl);
 104     qemu_put_be64s(f, &env->hpstate);
 105     for (i = 0; i < MAXTL_MAX; i++)
 106         qemu_put_be64s(f, &env->htstate[i]);
 107     qemu_put_be64s(f, &env->hintp);
 108     qemu_put_be64s(f, &env->htba);
 109     qemu_put_be64s(f, &env->hver);
 110     qemu_put_be64s(f, &env->hstick_cmpr);
 111     qemu_put_be64s(f, &env->ssr);
 112     cpu_put_timer(f, env->hstick);
 113 #endif
 114 }
 115
 116 int cpu_load(QEMUFile *f, void *opaque, int version_id)
 117 {
 118     CPUState *env = opaque;
 119     int i;
 120     uint32_t tmp;
 121
 122     if (version_id < 6)
 123         return -EINVAL;
 124     for(i = 0; i < 8; i++)
 125         qemu_get_betls(f, &env->gregs[i]);
 126     qemu_get_be32s(f, &env->nwindows);
 127     for(i = 0; i < env->nwindows * 16; i++)
 128         qemu_get_betls(f, &env->regbase[i]);
 129
 130     /* FPU */
 131     for(i = 0; i < TARGET_FPREGS; i++) {
 132         union {
 133             float32 f;
 134             uint32_t i;
 135         } u;
 136         u.i = qemu_get_be32(f);
 137         env->fpr[i] = u.f;
 138     }
 139
 140     qemu_get_betls(f, &env->pc);
 141     qemu_get_betls(f, &env->npc);
 142     qemu_get_betls(f, &env->y);
 143     tmp = qemu_get_be32(f);
 144     env->cwp = 0; /* needed to ensure that the wrapping registers are
 145                      correctly updated */
 146     cpu_put_psr(env, tmp);
 147     qemu_get_betls(f, &env->fsr);
 148     qemu_get_betls(f, &env->tbr);
 149     tmp = qemu_get_be32(f);
 150     env->interrupt_index = tmp;
 151     qemu_get_be32s(f, &env->pil_in);
 152 #ifndef TARGET_SPARC64
 153     qemu_get_be32s(f, &env->wim);
 154     /* MMU */
 155     for (i = 0; i < 32; i++)
 156         qemu_get_be32s(f, &env->mmuregs[i]);
 157     for (i = 0; i < 4; i++) {
 158         qemu_get_be64s(f, &env->mxccdata[i]);
 159     }
 160     for (i = 0; i < 8; i++) {
 161         qemu_get_be64s(f, &env->mxccregs[i]);
 162     }
 163     qemu_get_be32s(f, &env->mmubpctrv);
 164     qemu_get_be32s(f, &env->mmubpctrc);
 165     qemu_get_be32s(f, &env->mmubpctrs);
 166     qemu_get_be64s(f, &env->mmubpaction);
 167     for (i = 0; i < 4; i++) {
 168         qemu_get_be64s(f, &env->mmubpregs[i]);
 169     }
 170 #else
 171     qemu_get_be64s(f, &env->lsu);
 172     for (i = 0; i < 16; i++) {
 173         qemu_get_be64s(f, &env->immuregs[i]);
 174         qemu_get_be64s(f, &env->dmmuregs[i]);
 175     }
 176     for (i = 0; i < 64; i++) {
 177         qemu_get_be64s(f, &env->itlb[i].tag);
 178         qemu_get_be64s(f, &env->itlb[i].tte);
 179         qemu_get_be64s(f, &env->dtlb[i].tag);
 180         qemu_get_be64s(f, &env->dtlb[i].tte);
 181     }
 182     qemu_get_be32s(f, &env->mmu_version);
 183     for (i = 0; i < MAXTL_MAX; i++) {
 184         qemu_get_be64s(f, &env->ts[i].tpc);
 185         qemu_get_be64s(f, &env->ts[i].tnpc);
 186         qemu_get_be64s(f, &env->ts[i].tstate);
 187         qemu_get_be32s(f, &env->ts[i].tt);
 188     }
 189     qemu_get_be32s(f, &env->xcc);
 190     qemu_get_be32s(f, &env->asi);
 191     qemu_get_be32s(f, &env->pstate);
 192     qemu_get_be32s(f, &env->tl);
 193     qemu_get_be32s(f, &env->cansave);
 194     qemu_get_be32s(f, &env->canrestore);
 195     qemu_get_be32s(f, &env->otherwin);
 196     qemu_get_be32s(f, &env->wstate);
 197     qemu_get_be32s(f, &env->cleanwin);
 198     for (i = 0; i < 8; i++)
 199         qemu_get_be64s(f, &env->agregs[i]);
 200     for (i = 0; i < 8; i++)
 201         qemu_get_be64s(f, &env->bgregs[i]);
 202     for (i = 0; i < 8; i++)
 203         qemu_get_be64s(f, &env->igregs[i]);
 204     for (i = 0; i < 8; i++)
 205         qemu_get_be64s(f, &env->mgregs[i]);
 206     qemu_get_be64s(f, &env->fprs);
 207     qemu_get_be64s(f, &env->tick_cmpr);
 208     qemu_get_be64s(f, &env->stick_cmpr);
 209     cpu_get_timer(f, env->tick);
 210     cpu_get_timer(f, env->stick);
 211     qemu_get_be64s(f, &env->gsr);
 212     qemu_get_be32s(f, &env->gl);
 213     qemu_get_be64s(f, &env->hpstate);
 214     for (i = 0; i < MAXTL_MAX; i++)
 215         qemu_get_be64s(f, &env->htstate[i]);
 216     qemu_get_be64s(f, &env->hintp);
 217     qemu_get_be64s(f, &env->htba);
 218     qemu_get_be64s(f, &env->hver);
 219     qemu_get_be64s(f, &env->hstick_cmpr);
 220     qemu_get_be64s(f, &env->ssr);
 221     cpu_get_timer(f, env->hstick);
 222 #endif
 223     tlb_flush(env, 1);
 224     return 0;
 225 }