target-sparc/cpu.h

   1 #ifndef CPU_SPARC_H
   2 #define CPU_SPARC_H
   3
   4 #include "config.h"
   5 #include "qemu-common.h"
   6
   7 #if !defined(TARGET_SPARC64)
   8 #define TARGET_LONG_BITS 32
   9 #define TARGET_FPREGS 32
  10 #define TARGET_PAGE_BITS 12 /* 4k */
  11 #define TARGET_PHYS_ADDR_SPACE_BITS 36
  12 #define TARGET_VIRT_ADDR_SPACE_BITS 32
  13 #else
  14 #define TARGET_LONG_BITS 64
  15 #define TARGET_FPREGS 64
  16 #define TARGET_PAGE_BITS 13 /* 8k */
  17 #define TARGET_PHYS_ADDR_SPACE_BITS 41
  18 # ifdef TARGET_ABI32
  19 #  define TARGET_VIRT_ADDR_SPACE_BITS 32
  20 # else
  21 #  define TARGET_VIRT_ADDR_SPACE_BITS 44
  22 # endif
  23 #endif
  24
  25 #define CPUState struct CPUSPARCState
  26
  27 #include "cpu-defs.h"
  28
  29 #include "softfloat.h"
  30
  31 #define TARGET_HAS_ICE 1
  32
  33 #if !defined(TARGET_SPARC64)
  34 #define ELF_MACHINE     EM_SPARC
  35 #else
  36 #define ELF_MACHINE     EM_SPARCV9
  37 #endif
  38
  39 /*#define EXCP_INTERRUPT 0x100*/
  40
  41 /* trap definitions */
  42 #ifndef TARGET_SPARC64
  43 #define TT_TFAULT   0x01
  44 #define TT_ILL_INSN 0x02
  45 #define TT_PRIV_INSN 0x03
  46 #define TT_NFPU_INSN 0x04
  47 #define TT_WIN_OVF  0x05
  48 #define TT_WIN_UNF  0x06
  49 #define TT_UNALIGNED 0x07
  50 #define TT_FP_EXCP  0x08
  51 #define TT_DFAULT   0x09
  52 #define TT_TOVF     0x0a
  53 #define TT_EXTINT   0x10
  54 #define TT_CODE_ACCESS 0x21
  55 #define TT_UNIMP_FLUSH 0x25
  56 #define TT_DATA_ACCESS 0x29
  57 #define TT_DIV_ZERO 0x2a
  58 #define TT_NCP_INSN 0x24
  59 #define TT_TRAP     0x80
  60 #else
  61 #define TT_POWER_ON_RESET 0x01
  62 #define TT_TFAULT   0x08
  63 #define TT_CODE_ACCESS 0x0a
  64 #define TT_ILL_INSN 0x10
  65 #define TT_UNIMP_FLUSH TT_ILL_INSN
  66 #define TT_PRIV_INSN 0x11
  67 #define TT_NFPU_INSN 0x20
  68 #define TT_FP_EXCP  0x21
  69 #define TT_TOVF     0x23
  70 #define TT_CLRWIN   0x24
  71 #define TT_DIV_ZERO 0x28
  72 #define TT_DFAULT   0x30
  73 #define TT_DATA_ACCESS 0x32
  74 #define TT_UNALIGNED 0x34
  75 #define TT_PRIV_ACT 0x37
  76 #define TT_EXTINT   0x40
  77 #define TT_IVEC     0x60
  78 #define TT_TMISS    0x64
  79 #define TT_DMISS    0x68
  80 #define TT_DPROT    0x6c
  81 #define TT_SPILL    0x80
  82 #define TT_FILL     0xc0
  83 #define TT_WOTHER   (1 << 5)
  84 #define TT_TRAP     0x100
  85 #endif
  86
  87 #define PSR_NEG_SHIFT 23
  88 #define PSR_NEG   (1 << PSR_NEG_SHIFT)
  89 #define PSR_ZERO_SHIFT 22
  90 #define PSR_ZERO  (1 << PSR_ZERO_SHIFT)
  91 #define PSR_OVF_SHIFT 21
  92 #define PSR_OVF   (1 << PSR_OVF_SHIFT)
  93 #define PSR_CARRY_SHIFT 20
  94 #define PSR_CARRY (1 << PSR_CARRY_SHIFT)
  95 #define PSR_ICC   (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY)
  96 #if !defined(TARGET_SPARC64)
  97 #define PSR_EF    (1<<12)
  98 #define PSR_PIL   0xf00
  99 #define PSR_S     (1<<7)
 100 #define PSR_PS    (1<<6)
 101 #define PSR_ET    (1<<5)
 102 #define PSR_CWP   0x1f
 103 #endif
 104
 105 #define CC_SRC (env->cc_src)
 106 #define CC_SRC2 (env->cc_src2)
 107 #define CC_DST (env->cc_dst)
 108 #define CC_OP  (env->cc_op)
 109
 110 enum {
 111     CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
 112     CC_OP_FLAGS,   /* all cc are back in status register */
 113     CC_OP_DIV,     /* modify N, Z and V, C = 0*/
 114     CC_OP_ADD,     /* modify all flags, CC_DST = res, CC_SRC = src1 */
 115     CC_OP_ADDX,    /* modify all flags, CC_DST = res, CC_SRC = src1 */
 116     CC_OP_TADD,    /* modify all flags, CC_DST = res, CC_SRC = src1 */
 117     CC_OP_TADDTV,  /* modify all flags except V, CC_DST = res, CC_SRC = src1 */
 118     CC_OP_SUB,     /* modify all flags, CC_DST = res, CC_SRC = src1 */
 119     CC_OP_SUBX,    /* modify all flags, CC_DST = res, CC_SRC = src1 */
 120     CC_OP_TSUB,    /* modify all flags, CC_DST = res, CC_SRC = src1 */
 121     CC_OP_TSUBTV,  /* modify all flags except V, CC_DST = res, CC_SRC = src1 */
 122     CC_OP_LOGIC,   /* modify N and Z, C = V = 0, CC_DST = res */
 123     CC_OP_NB,
 124 };
 125
 126 /* Trap base register */
 127 #define TBR_BASE_MASK 0xfffff000
 128
 129 #if defined(TARGET_SPARC64)
 130 #define PS_TCT   (1<<12) /* UA2007, impl.dep. trap on control transfer */
 131 #define PS_IG    (1<<11) /* v9, zero on UA2007 */
 132 #define PS_MG    (1<<10) /* v9, zero on UA2007 */
 133 #define PS_CLE   (1<<9) /* UA2007 */
 134 #define PS_TLE   (1<<8) /* UA2007 */
 135 #define PS_RMO   (1<<7)
 136 #define PS_RED   (1<<5) /* v9, zero on UA2007 */
 137 #define PS_PEF   (1<<4) /* enable fpu */
 138 #define PS_AM    (1<<3) /* address mask */
 139 #define PS_PRIV  (1<<2)
 140 #define PS_IE    (1<<1)
 141 #define PS_AG    (1<<0) /* v9, zero on UA2007 */
 142
 143 #define FPRS_FEF (1<<2)
 144
 145 #define HS_PRIV  (1<<2)
 146 #endif
 147
 148 /* Fcc */
 149 #define FSR_RD1        (1ULL << 31)
 150 #define FSR_RD0        (1ULL << 30)
 151 #define FSR_RD_MASK    (FSR_RD1 | FSR_RD0)
 152 #define FSR_RD_NEAREST 0
 153 #define FSR_RD_ZERO    FSR_RD0
 154 #define FSR_RD_POS     FSR_RD1
 155 #define FSR_RD_NEG     (FSR_RD1 | FSR_RD0)
 156
 157 #define FSR_NVM   (1ULL << 27)
 158 #define FSR_OFM   (1ULL << 26)
 159 #define FSR_UFM   (1ULL << 25)
 160 #define FSR_DZM   (1ULL << 24)
 161 #define FSR_NXM   (1ULL << 23)
 162 #define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM)
 163
 164 #define FSR_NVA   (1ULL << 9)
 165 #define FSR_OFA   (1ULL << 8)
 166 #define FSR_UFA   (1ULL << 7)
 167 #define FSR_DZA   (1ULL << 6)
 168 #define FSR_NXA   (1ULL << 5)
 169 #define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
 170
 171 #define FSR_NVC   (1ULL << 4)
 172 #define FSR_OFC   (1ULL << 3)
 173 #define FSR_UFC   (1ULL << 2)
 174 #define FSR_DZC   (1ULL << 1)
 175 #define FSR_NXC   (1ULL << 0)
 176 #define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)
 177
 178 #define FSR_FTT2   (1ULL << 16)
 179 #define FSR_FTT1   (1ULL << 15)
 180 #define FSR_FTT0   (1ULL << 14)
 181 //gcc warns about constant overflow for ~FSR_FTT_MASK
 182 //#define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
 183 #ifdef TARGET_SPARC64
 184 #define FSR_FTT_NMASK      0xfffffffffffe3fffULL
 185 #define FSR_FTT_CEXC_NMASK 0xfffffffffffe3fe0ULL
 186 #define FSR_LDFSR_OLDMASK  0x0000003f000fc000ULL
 187 #define FSR_LDXFSR_MASK    0x0000003fcfc00fffULL
 188 #define FSR_LDXFSR_OLDMASK 0x00000000000fc000ULL
 189 #else
 190 #define FSR_FTT_NMASK      0xfffe3fffULL
 191 #define FSR_FTT_CEXC_NMASK 0xfffe3fe0ULL
 192 #define FSR_LDFSR_OLDMASK  0x000fc000ULL
 193 #endif
 194 #define FSR_LDFSR_MASK     0xcfc00fffULL
 195 #define FSR_FTT_IEEE_EXCP (1ULL << 14)
 196 #define FSR_FTT_UNIMPFPOP (3ULL << 14)
 197 #define FSR_FTT_SEQ_ERROR (4ULL << 14)
 198 #define FSR_FTT_INVAL_FPR (6ULL << 14)
 199
 200 #define FSR_FCC1_SHIFT 11
 201 #define FSR_FCC1  (1ULL << FSR_FCC1_SHIFT)
 202 #define FSR_FCC0_SHIFT 10
 203 #define FSR_FCC0  (1ULL << FSR_FCC0_SHIFT)
 204
 205 /* MMU */
 206 #define MMU_E     (1<<0)
 207 #define MMU_NF    (1<<1)
 208
 209 #define PTE_ENTRYTYPE_MASK 3
 210 #define PTE_ACCESS_MASK    0x1c
 211 #define PTE_ACCESS_SHIFT   2
 212 #define PTE_PPN_SHIFT      7
 213 #define PTE_ADDR_MASK      0xffffff00
 214
 215 #define PG_ACCESSED_BIT 5
 216 #define PG_MODIFIED_BIT 6
 217 #define PG_CACHE_BIT    7
 218
 219 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
 220 #define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT)
 221 #define PG_CACHE_MASK    (1 << PG_CACHE_BIT)
 222
 223 /* 3 <= NWINDOWS <= 32. */
 224 #define MIN_NWINDOWS 3
 225 #define MAX_NWINDOWS 32
 226
 227 #if !defined(TARGET_SPARC64)
 228 #define NB_MMU_MODES 2
 229 #else
 230 #define NB_MMU_MODES 6
 231 typedef struct trap_state {
 232     uint64_t tpc;
 233     uint64_t tnpc;
 234     uint64_t tstate;
 235     uint32_t tt;
 236 } trap_state;
 237 #endif
 238
 239 typedef struct sparc_def_t {
 240     const char *name;
 241     target_ulong iu_version;
 242     uint32_t fpu_version;
 243     uint32_t mmu_version;
 244     uint32_t mmu_bm;
 245     uint32_t mmu_ctpr_mask;
 246     uint32_t mmu_cxr_mask;
 247     uint32_t mmu_sfsr_mask;
 248     uint32_t mmu_trcr_mask;
 249     uint32_t mxcc_version;
 250     uint32_t features;
 251     uint32_t nwindows;
 252     uint32_t maxtl;
 253 } sparc_def_t;
 254
 255 #define CPU_FEATURE_FLOAT        (1 << 0)
 256 #define CPU_FEATURE_FLOAT128     (1 << 1)
 257 #define CPU_FEATURE_SWAP         (1 << 2)
 258 #define CPU_FEATURE_MUL          (1 << 3)
 259 #define CPU_FEATURE_DIV          (1 << 4)
 260 #define CPU_FEATURE_FLUSH        (1 << 5)
 261 #define CPU_FEATURE_FSQRT        (1 << 6)
 262 #define CPU_FEATURE_FMUL         (1 << 7)
 263 #define CPU_FEATURE_VIS1         (1 << 8)
 264 #define CPU_FEATURE_VIS2         (1 << 9)
 265 #define CPU_FEATURE_FSMULD       (1 << 10)
 266 #define CPU_FEATURE_HYPV         (1 << 11)
 267 #define CPU_FEATURE_CMT          (1 << 12)
 268 #define CPU_FEATURE_GL           (1 << 13)
 269 #define CPU_FEATURE_TA0_SHUTDOWN (1 << 14) /* Shutdown on "ta 0x0" */
 270 #define CPU_FEATURE_ASR17        (1 << 15)
 271 #define CPU_FEATURE_CACHE_CTRL   (1 << 16)
 272
 273 #ifndef TARGET_SPARC64
 274 #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP |  \
 275                               CPU_FEATURE_MUL | CPU_FEATURE_DIV |     \
 276                               CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \
 277                               CPU_FEATURE_FMUL | CPU_FEATURE_FSMULD)
 278 #else
 279 #define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP |  \
 280                               CPU_FEATURE_MUL | CPU_FEATURE_DIV |     \
 281                               CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \
 282                               CPU_FEATURE_FMUL | CPU_FEATURE_VIS1 |   \
 283                               CPU_FEATURE_VIS2 | CPU_FEATURE_FSMULD)
 284 enum {
 285     mmu_us_12, // Ultrasparc < III (64 entry TLB)
 286     mmu_us_3,  // Ultrasparc III (512 entry TLB)
 287     mmu_us_4,  // Ultrasparc IV (several TLBs, 32 and 256MB pages)
 288     mmu_sun4v, // T1, T2
 289 };
 290 #endif
 291
 292 #define TTE_VALID_BIT       (1ULL << 63)
 293 #define TTE_NFO_BIT         (1ULL << 60)
 294 #define TTE_USED_BIT        (1ULL << 41)
 295 #define TTE_LOCKED_BIT      (1ULL <<  6)
 296 #define TTE_SIDEEFFECT_BIT  (1ULL <<  3)
 297 #define TTE_PRIV_BIT        (1ULL <<  2)
 298 #define TTE_W_OK_BIT        (1ULL <<  1)
 299 #define TTE_GLOBAL_BIT      (1ULL <<  0)
 300
 301 #define TTE_IS_VALID(tte)   ((tte) & TTE_VALID_BIT)
 302 #define TTE_IS_NFO(tte)     ((tte) & TTE_NFO_BIT)
 303 #define TTE_IS_USED(tte)    ((tte) & TTE_USED_BIT)
 304 #define TTE_IS_LOCKED(tte)  ((tte) & TTE_LOCKED_BIT)
 305 #define TTE_IS_SIDEEFFECT(tte) ((tte) & TTE_SIDEEFFECT_BIT)
 306 #define TTE_IS_PRIV(tte)    ((tte) & TTE_PRIV_BIT)
 307 #define TTE_IS_W_OK(tte)    ((tte) & TTE_W_OK_BIT)
 308 #define TTE_IS_GLOBAL(tte)  ((tte) & TTE_GLOBAL_BIT)
 309
 310 #define TTE_SET_USED(tte)   ((tte) |= TTE_USED_BIT)
 311 #define TTE_SET_UNUSED(tte) ((tte) &= ~TTE_USED_BIT)
 312
 313 #define TTE_PGSIZE(tte)     (((tte) >> 61) & 3ULL)
 314 #define TTE_PA(tte)         ((tte) & 0x1ffffffe000ULL)
 315
 316 #define SFSR_NF_BIT         (1ULL << 24)   /* JPS1 NoFault */
 317 #define SFSR_TM_BIT         (1ULL << 15)   /* JPS1 TLB Miss */
 318 #define SFSR_FT_VA_IMMU_BIT (1ULL << 13)   /* USIIi VA out of range (IMMU) */
 319 #define SFSR_FT_VA_DMMU_BIT (1ULL << 12)   /* USIIi VA out of range (DMMU) */
 320 #define SFSR_FT_NFO_BIT     (1ULL << 11)   /* NFO page access */
 321 #define SFSR_FT_ILL_BIT     (1ULL << 10)   /* illegal LDA/STA ASI */
 322 #define SFSR_FT_ATOMIC_BIT  (1ULL <<  9)   /* atomic op on noncacheable area */
 323 #define SFSR_FT_NF_E_BIT    (1ULL <<  8)   /* NF access on side effect area */
 324 #define SFSR_FT_PRIV_BIT    (1ULL <<  7)   /* privilege violation */
 325 #define SFSR_PR_BIT         (1ULL <<  3)   /* privilege mode */
 326 #define SFSR_WRITE_BIT      (1ULL <<  2)   /* write access mode */
 327 #define SFSR_OW_BIT         (1ULL <<  1)   /* status overwritten */
 328 #define SFSR_VALID_BIT      (1ULL <<  0)   /* status valid */
 329
 330 #define SFSR_ASI_SHIFT      16             /* 23:16 ASI value */
 331 #define SFSR_ASI_MASK       (0xffULL << SFSR_ASI_SHIFT)
 332 #define SFSR_CT_PRIMARY     (0ULL <<  4)   /* 5:4 context type */
 333 #define SFSR_CT_SECONDARY   (1ULL <<  4)
 334 #define SFSR_CT_NUCLEUS     (2ULL <<  4)
 335 #define SFSR_CT_NOTRANS     (3ULL <<  4)
 336 #define SFSR_CT_MASK        (3ULL <<  4)
 337
 338 typedef struct SparcTLBEntry {
 339     uint64_t tag;
 340     uint64_t tte;
 341 } SparcTLBEntry;
 342
 343 struct CPUTimer
 344 {
 345     const char *name;
 346     uint32_t    frequency;
 347     uint32_t    disabled;
 348     uint64_t    disabled_mask;
 349     int64_t     clock_offset;
 350     struct QEMUTimer  *qtimer;
 351 };
 352
 353 typedef struct CPUTimer CPUTimer;
 354
 355 struct QEMUFile;
 356 void cpu_put_timer(struct QEMUFile *f, CPUTimer *s);
 357 void cpu_get_timer(struct QEMUFile *f, CPUTimer *s);
 358
 359 typedef struct CPUSPARCState {
 360     target_ulong gregs[8]; /* general registers */
 361     target_ulong *regwptr; /* pointer to current register window */
 362     target_ulong pc;       /* program counter */
 363     target_ulong npc;      /* next program counter */
 364     target_ulong y;        /* multiply/divide register */
 365
 366     /* emulator internal flags handling */
 367     target_ulong cc_src, cc_src2;
 368     target_ulong cc_dst;
 369     uint32_t cc_op;
 370
 371     target_ulong t0, t1; /* temporaries live across basic blocks */
 372     target_ulong cond; /* conditional branch result (XXX: save it in a
 373                           temporary register when possible) */
 374
 375     uint32_t psr;      /* processor state register */
 376     target_ulong fsr;      /* FPU state register */
 377     float32 fpr[TARGET_FPREGS];  /* floating point registers */
 378     uint32_t cwp;      /* index of current register window (extracted
 379                           from PSR) */
 380 #if !defined(TARGET_SPARC64) || defined(TARGET_ABI32)
 381     uint32_t wim;      /* window invalid mask */
 382 #endif
 383     target_ulong tbr;  /* trap base register */
 384 #if !defined(TARGET_SPARC64)
 385     int      psrs;     /* supervisor mode (extracted from PSR) */
 386     int      psrps;    /* previous supervisor mode */
 387     int      psret;    /* enable traps */
 388 #endif
 389     uint32_t psrpil;   /* interrupt blocking level */
 390     uint32_t pil_in;   /* incoming interrupt level bitmap */
 391 #if !defined(TARGET_SPARC64)
 392     int      psref;    /* enable fpu */
 393 #endif
 394     target_ulong version;
 395     int interrupt_index;
 396     uint32_t nwindows;
 397     /* NOTE: we allow 8 more registers to handle wrapping */
 398     target_ulong regbase[MAX_NWINDOWS * 16 + 8];
 399
 400     CPU_COMMON
 401
 402     /* MMU regs */
 403 #if defined(TARGET_SPARC64)
 404     uint64_t lsu;
 405 #define DMMU_E 0x8
 406 #define IMMU_E 0x4
 407     //typedef struct SparcMMU
 408     union {
 409         uint64_t immuregs[16];
 410         struct {
 411             uint64_t tsb_tag_target;
 412             uint64_t unused_mmu_primary_context;   // use DMMU
 413             uint64_t unused_mmu_secondary_context; // use DMMU
 414             uint64_t sfsr;
 415             uint64_t sfar;
 416             uint64_t tsb;
 417             uint64_t tag_access;
 418         } immu;
 419     };
 420     union {
 421         uint64_t dmmuregs[16];
 422         struct {
 423             uint64_t tsb_tag_target;
 424             uint64_t mmu_primary_context;
 425             uint64_t mmu_secondary_context;
 426             uint64_t sfsr;
 427             uint64_t sfar;
 428             uint64_t tsb;
 429             uint64_t tag_access;
 430         } dmmu;
 431     };
 432     SparcTLBEntry itlb[64];
 433     SparcTLBEntry dtlb[64];
 434     uint32_t mmu_version;
 435 #else
 436     uint32_t mmuregs[32];
 437     uint64_t mxccdata[4];
 438     uint64_t mxccregs[8];
 439     uint32_t mmubpctrv, mmubpctrc, mmubpctrs;
 440     uint64_t mmubpaction;
 441     uint64_t mmubpregs[4];
 442     uint64_t prom_addr;
 443 #endif
 444     /* temporary float registers */
 445     float64 dt0, dt1;
 446     float128 qt0, qt1;
 447     float_status fp_status;
 448 #if defined(TARGET_SPARC64)
 449 #define MAXTL_MAX 8
 450 #define MAXTL_MASK (MAXTL_MAX - 1)
 451     trap_state ts[MAXTL_MAX];
 452     uint32_t xcc;               /* Extended integer condition codes */
 453     uint32_t asi;
 454     uint32_t pstate;
 455     uint32_t tl;
 456     uint32_t maxtl;
 457     uint32_t cansave, canrestore, otherwin, wstate, cleanwin;
 458     uint64_t agregs[8]; /* alternate general registers */
 459     uint64_t bgregs[8]; /* backup for normal global registers */
 460     uint64_t igregs[8]; /* interrupt general registers */
 461     uint64_t mgregs[8]; /* mmu general registers */
 462     uint64_t fprs;
 463     uint64_t tick_cmpr, stick_cmpr;
 464     CPUTimer *tick, *stick;
 465 #define TICK_NPT_MASK        0x8000000000000000ULL
 466 #define TICK_INT_DIS         0x8000000000000000ULL
 467     uint64_t gsr;
 468     uint32_t gl; // UA2005
 469     /* UA 2005 hyperprivileged registers */
 470     uint64_t hpstate, htstate[MAXTL_MAX], hintp, htba, hver, hstick_cmpr, ssr;
 471     CPUTimer *hstick; // UA 2005
 472     uint32_t softint;
 473 #define SOFTINT_TIMER   1
 474 #define SOFTINT_STIMER  (1 << 16)
 475 #define SOFTINT_INTRMASK (0xFFFE)
 476 #define SOFTINT_REG_MASK (SOFTINT_STIMER|SOFTINT_INTRMASK|SOFTINT_TIMER)
 477 #endif
 478     sparc_def_t *def;
 479
 480     void *irq_manager;
 481     void (*qemu_irq_ack) (void *irq_manager, int intno);
 482
 483     /* Leon3 cache control */
 484     uint32_t cache_control;
 485 } CPUSPARCState;
 486
 487 #ifndef NO_CPU_IO_DEFS
 488 /* helper.c */
 489 CPUSPARCState *cpu_sparc_init(const char *cpu_model);
 490 void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu);
 491 void sparc_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 492 int cpu_sparc_handle_mmu_fault(CPUSPARCState *env1, target_ulong address, int rw,
 493                                int mmu_idx);
 494 #define cpu_handle_mmu_fault cpu_sparc_handle_mmu_fault
 495 target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev);
 496 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUState *env);
 497
 498 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
 499 int target_memory_rw_debug(CPUState *env, target_ulong addr,
 500                            uint8_t *buf, int len, int is_write);
 501 #define TARGET_CPU_MEMORY_RW_DEBUG
 502 #endif
 503
 504
 505 /* translate.c */
 506 void gen_intermediate_code_init(CPUSPARCState *env);
 507
 508 /* cpu-exec.c */
 509 int cpu_sparc_exec(CPUSPARCState *s);
 510
 511 /* op_helper.c */
 512 target_ulong cpu_get_psr(CPUState *env1);
 513 void cpu_put_psr(CPUState *env1, target_ulong val);
 514 #ifdef TARGET_SPARC64
 515 target_ulong cpu_get_ccr(CPUState *env1);
 516 void cpu_put_ccr(CPUState *env1, target_ulong val);
 517 target_ulong cpu_get_cwp64(CPUState *env1);
 518 void cpu_put_cwp64(CPUState *env1, int cwp);
 519 void cpu_change_pstate(CPUState *env1, uint32_t new_pstate);
 520 #endif
 521 int cpu_cwp_inc(CPUState *env1, int cwp);
 522 int cpu_cwp_dec(CPUState *env1, int cwp);
 523 void cpu_set_cwp(CPUState *env1, int new_cwp);
 524 void leon3_irq_manager(void *irq_manager, int intno);
 525
 526 /* sun4m.c, sun4u.c */
 527 void cpu_check_irqs(CPUSPARCState *env);
 528
 529 /* leon3.c */
 530 void leon3_irq_ack(void *irq_manager, int intno);
 531
 532 #if defined (TARGET_SPARC64)
 533
 534 static inline int compare_masked(uint64_t x, uint64_t y, uint64_t mask)
 535 {
 536     return (x & mask) == (y & mask);
 537 }
 538
 539 #define MMU_CONTEXT_BITS 13
 540 #define MMU_CONTEXT_MASK ((1 << MMU_CONTEXT_BITS) - 1)
 541
 542 static inline int tlb_compare_context(const SparcTLBEntry *tlb,
 543                                       uint64_t context)
 544 {
 545     return compare_masked(context, tlb->tag, MMU_CONTEXT_MASK);
 546 }
 547
 548 #endif
 549 #endif
 550
 551 /* cpu-exec.c */
 552 #if !defined(CONFIG_USER_ONLY)
 553 void cpu_unassigned_access(CPUState *env1, target_phys_addr_t addr,
 554                            int is_write, int is_exec, int is_asi, int size);
 555 #if defined(TARGET_SPARC64)
 556 target_phys_addr_t cpu_get_phys_page_nofault(CPUState *env, target_ulong addr,
 557                                            int mmu_idx);
 558
 559 #endif
 560 #endif
 561 int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);
 562
 563 #define cpu_init cpu_sparc_init
 564 #define cpu_exec cpu_sparc_exec
 565 #define cpu_gen_code cpu_sparc_gen_code
 566 #define cpu_signal_handler cpu_sparc_signal_handler
 567 #define cpu_list sparc_cpu_list
 568
 569 #define CPU_SAVE_VERSION 7
 570
 571 /* MMU modes definitions */
 572 #if defined (TARGET_SPARC64)
 573 #define MMU_USER_IDX   0
 574 #define MMU_MODE0_SUFFIX _user
 575 #define MMU_USER_SECONDARY_IDX   1
 576 #define MMU_MODE1_SUFFIX _user_secondary
 577 #define MMU_KERNEL_IDX 2
 578 #define MMU_MODE2_SUFFIX _kernel
 579 #define MMU_KERNEL_SECONDARY_IDX 3
 580 #define MMU_MODE3_SUFFIX _kernel_secondary
 581 #define MMU_NUCLEUS_IDX 4
 582 #define MMU_MODE4_SUFFIX _nucleus
 583 #define MMU_HYPV_IDX   5
 584 #define MMU_MODE5_SUFFIX _hypv
 585 #else
 586 #define MMU_USER_IDX   0
 587 #define MMU_MODE0_SUFFIX _user
 588 #define MMU_KERNEL_IDX 1
 589 #define MMU_MODE1_SUFFIX _kernel
 590 #endif
 591
 592 #if defined (TARGET_SPARC64)
 593 static inline int cpu_has_hypervisor(CPUState *env1)
 594 {
 595     return env1->def->features & CPU_FEATURE_HYPV;
 596 }
 597
 598 static inline int cpu_hypervisor_mode(CPUState *env1)
 599 {
 600     return cpu_has_hypervisor(env1) && (env1->hpstate & HS_PRIV);
 601 }
 602
 603 static inline int cpu_supervisor_mode(CPUState *env1)
 604 {
 605     return env1->pstate & PS_PRIV;
 606 }
 607 #endif
 608
 609 static inline int cpu_mmu_index(CPUState *env1)
 610 {
 611 #if defined(CONFIG_USER_ONLY)
 612     return MMU_USER_IDX;
 613 #elif !defined(TARGET_SPARC64)
 614     return env1->psrs;
 615 #else
 616     if (env1->tl > 0) {
 617         return MMU_NUCLEUS_IDX;
 618     } else if (cpu_hypervisor_mode(env1)) {
 619         return MMU_HYPV_IDX;
 620     } else if (cpu_supervisor_mode(env1)) {
 621         return MMU_KERNEL_IDX;
 622     } else {
 623         return MMU_USER_IDX;
 624     }
 625 #endif
 626 }
 627
 628 static inline int cpu_interrupts_enabled(CPUState *env1)
 629 {
 630 #if !defined (TARGET_SPARC64)
 631     if (env1->psret != 0)
 632         return 1;
 633 #else
 634     if (env1->pstate & PS_IE)
 635         return 1;
 636 #endif
 637
 638     return 0;
 639 }
 640
 641 static inline int cpu_pil_allowed(CPUState *env1, int pil)
 642 {
 643 #if !defined(TARGET_SPARC64)
 644     /* level 15 is non-maskable on sparc v8 */
 645     return pil == 15 || pil > env1->psrpil;
 646 #else
 647     return pil > env1->psrpil;
 648 #endif
 649 }
 650
 651 #if defined(CONFIG_USER_ONLY)
 652 static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
 653 {
 654     if (newsp)
 655         env->regwptr[22] = newsp;
 656     env->regwptr[0] = 0;
 657     /* FIXME: Do we also need to clear CF?  */
 658     /* XXXXX */
 659     printf ("HELPME: %s:%d\n", __FILE__, __LINE__);
 660 }
 661 #endif
 662
 663 #include "cpu-all.h"
 664
 665 #ifdef TARGET_SPARC64
 666 /* sun4u.c */
 667 void cpu_tick_set_count(CPUTimer *timer, uint64_t count);
 668 uint64_t cpu_tick_get_count(CPUTimer *timer);
 669 void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit);
 670 trap_state* cpu_tsptr(CPUState* env);
 671 #endif
 672
 673 #define TB_FLAG_FPU_ENABLED (1 << 4)
 674 #define TB_FLAG_AM_ENABLED (1 << 5)
 675
 676 static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
 677                                         target_ulong *cs_base, int *flags)
 678 {
 679     *pc = env->pc;
 680     *cs_base = env->npc;
 681 #ifdef TARGET_SPARC64
 682     // AM . Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled
 683     *flags = (env->pstate & PS_PRIV)               /* 2 */
 684         | ((env->lsu & (DMMU_E | IMMU_E)) >> 2)    /* 1, 0 */
 685         | ((env->tl & 0xff) << 8)
 686         | (env->dmmu.mmu_primary_context << 16);   /* 16... */
 687     if (env->pstate & PS_AM) {
 688         *flags |= TB_FLAG_AM_ENABLED;
 689     }
 690     if ((env->def->features & CPU_FEATURE_FLOAT) && (env->pstate & PS_PEF)
 691         && (env->fprs & FPRS_FEF)) {
 692         *flags |= TB_FLAG_FPU_ENABLED;
 693     }
 694 #else
 695     // FPU enable . Supervisor
 696     *flags = env->psrs;
 697     if ((env->def->features & CPU_FEATURE_FLOAT) && env->psref) {
 698         *flags |= TB_FLAG_FPU_ENABLED;
 699     }
 700 #endif
 701 }
 702
 703 static inline bool tb_fpu_enabled(int tb_flags)
 704 {
 705 #if defined(CONFIG_USER_ONLY)
 706     return true;
 707 #else
 708     return tb_flags & TB_FLAG_FPU_ENABLED;
 709 #endif
 710 }
 711
 712 static inline bool tb_am_enabled(int tb_flags)
 713 {
 714 #ifndef TARGET_SPARC64
 715     return false;
 716 #else
 717     return tb_flags & TB_FLAG_AM_ENABLED;
 718 #endif
 719 }
 720
 721 /* helper.c */
 722 void do_interrupt(CPUState *env);
 723
 724 static inline bool cpu_has_work(CPUState *env1)
 725 {
 726     return (env1->interrupt_request & CPU_INTERRUPT_HARD) &&
 727            cpu_interrupts_enabled(env1);
 728 }
 729
 730 #include "exec-all.h"
 731
 732 static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
 733 {
 734     env->pc = tb->pc;
 735     env->npc = tb->cs_base;
 736 }
 737
 738 #endif