include/exec/exec-all.h

   1 /*
   2  * internal execution defines for qemu
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef _EXEC_ALL_H_
  21 #define _EXEC_ALL_H_
  22
  23 #include "qemu-common.h"
  24
  25 /* allow to see translation results - the slowdown should be negligible, so we leave it */
  26 #define DEBUG_DISAS
  27
  28 /* Page tracking code uses ram addresses in system mode, and virtual
  29    addresses in userspace mode.  Define tb_page_addr_t to be an appropriate
  30    type.  */
  31 #if defined(CONFIG_USER_ONLY)
  32 typedef abi_ulong tb_page_addr_t;
  33 #else
  34 typedef ram_addr_t tb_page_addr_t;
  35 #endif
  36
  37 /* is_jmp field values */
  38 #define DISAS_NEXT    0 /* next instruction can be analyzed */
  39 #define DISAS_JUMP    1 /* only pc was modified dynamically */
  40 #define DISAS_UPDATE  2 /* cpu state was modified dynamically */
  41 #define DISAS_TB_JUMP 3 /* only pc was modified statically */
  42
  43 struct TranslationBlock;
  44 typedef struct TranslationBlock TranslationBlock;
  45
  46 /* XXX: make safe guess about sizes */
  47 #define MAX_OP_PER_INSTR 266
  48
  49 #if HOST_LONG_BITS == 32
  50 #define MAX_OPC_PARAM_PER_ARG 2
  51 #else
  52 #define MAX_OPC_PARAM_PER_ARG 1
  53 #endif
  54 #define MAX_OPC_PARAM_IARGS 5
  55 #define MAX_OPC_PARAM_OARGS 1
  56 #define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS)
  57
  58 /* A Call op needs up to 4 + 2N parameters on 32-bit archs,
  59  * and up to 4 + N parameters on 64-bit archs
  60  * (N = number of input arguments + output arguments).  */
  61 #define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS))
  62 #define OPC_BUF_SIZE 640
  63 #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
  64
  65 /* Maximum size a TCG op can expand to.  This is complicated because a
  66    single op may require several host instructions and register reloads.
  67    For now take a wild guess at 192 bytes, which should allow at least
  68    a couple of fixup instructions per argument.  */
  69 #define TCG_MAX_OP_SIZE 192
  70
  71 #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
  72
  73 #include "qemu/log.h"
  74
  75 void gen_intermediate_code(CPUArchState *env, struct TranslationBlock *tb);
  76 void gen_intermediate_code_pc(CPUArchState *env, struct TranslationBlock *tb);
  77 void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb,
  78                           int pc_pos);
  79
  80 void cpu_gen_init(void);
  81 int cpu_gen_code(CPUArchState *env, struct TranslationBlock *tb,
  82                  int *gen_code_size_ptr);
  83 bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc);
  84 void page_size_init(void);
  85
  86 void QEMU_NORETURN cpu_resume_from_signal(CPUState *cpu, void *puc);
  87 void QEMU_NORETURN cpu_io_recompile(CPUState *cpu, uintptr_t retaddr);
  88 TranslationBlock *tb_gen_code(CPUState *cpu,
  89                               target_ulong pc, target_ulong cs_base, int flags,
  90                               int cflags);
  91 void cpu_exec_init(CPUState *cpu, Error **errp);
  92 void QEMU_NORETURN cpu_loop_exit(CPUState *cpu);
  93
  94 #if !defined(CONFIG_USER_ONLY)
  95 bool qemu_in_vcpu_thread(void);
  96 void cpu_reload_memory_map(CPUState *cpu);
  97 void tcg_cpu_address_space_init(CPUState *cpu, AddressSpace *as);
  98 /* cputlb.c */
  99 void tlb_flush_page(CPUState *cpu, target_ulong addr);
 100 void tlb_flush(CPUState *cpu, int flush_global);
 101 void tlb_set_page(CPUState *cpu, target_ulong vaddr,
 102                   hwaddr paddr, int prot,
 103                   int mmu_idx, target_ulong size);
 104 void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
 105                              hwaddr paddr, MemTxAttrs attrs,
 106                              int prot, int mmu_idx, target_ulong size);
 107 void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr);
 108 void probe_write(CPUArchState *env, target_ulong addr, int mmu_idx,
 109                  uintptr_t retaddr);
 110 #else
 111 static inline void tlb_flush_page(CPUState *cpu, target_ulong addr)
 112 {
 113 }
 114
 115 static inline void tlb_flush(CPUState *cpu, int flush_global)
 116 {
 117 }
 118 #endif
 119
 120 #define CODE_GEN_ALIGN           16 /* must be >= of the size of a icache line */
 121
 122 #define CODE_GEN_PHYS_HASH_BITS     15
 123 #define CODE_GEN_PHYS_HASH_SIZE     (1 << CODE_GEN_PHYS_HASH_BITS)
 124
 125 /* estimated block size for TB allocation */
 126 /* XXX: use a per code average code fragment size and modulate it
 127    according to the host CPU */
 128 #if defined(CONFIG_SOFTMMU)
 129 #define CODE_GEN_AVG_BLOCK_SIZE 128
 130 #else
 131 #define CODE_GEN_AVG_BLOCK_SIZE 64
 132 #endif
 133
 134 #if defined(__arm__) || defined(_ARCH_PPC) \
 135     || defined(__x86_64__) || defined(__i386__) \
 136     || defined(__sparc__) || defined(__aarch64__) \
 137     || defined(__s390x__) || defined(__mips__) \
 138     || defined(CONFIG_TCG_INTERPRETER)
 139 #define USE_DIRECT_JUMP
 140 #endif
 141
 142 struct TranslationBlock {
 143     target_ulong pc;   /* simulated PC corresponding to this block (EIP + CS base) */
 144     target_ulong cs_base; /* CS base for this block */
 145     uint64_t flags; /* flags defining in which context the code was generated */
 146     uint16_t size;      /* size of target code for this block (1 <=
 147                            size <= TARGET_PAGE_SIZE) */
 148     uint16_t icount;
 149     uint32_t cflags;    /* compile flags */
 150 #define CF_COUNT_MASK  0x7fff
 151 #define CF_LAST_IO     0x8000 /* Last insn may be an IO access.  */
 152 #define CF_NOCACHE     0x10000 /* To be freed after execution */
 153 #define CF_USE_ICOUNT  0x20000
 154
 155     void *tc_ptr;    /* pointer to the translated code */
 156     /* next matching tb for physical address. */
 157     struct TranslationBlock *phys_hash_next;
 158     /* original tb when cflags has CF_NOCACHE */
 159     struct TranslationBlock *orig_tb;
 160     /* first and second physical page containing code. The lower bit
 161        of the pointer tells the index in page_next[] */
 162     struct TranslationBlock *page_next[2];
 163     tb_page_addr_t page_addr[2];
 164
 165     /* the following data are used to directly call another TB from
 166        the code of this one. */
 167     uint16_t tb_next_offset[2]; /* offset of original jump target */
 168 #ifdef USE_DIRECT_JUMP
 169     uint16_t tb_jmp_offset[2]; /* offset of jump instruction */
 170 #else
 171     uintptr_t tb_next[2]; /* address of jump generated code */
 172 #endif
 173     /* list of TBs jumping to this one. This is a circular list using
 174        the two least significant bits of the pointers to tell what is
 175        the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
 176        jmp_first */
 177     struct TranslationBlock *jmp_next[2];
 178     struct TranslationBlock *jmp_first;
 179 };
 180
 181 #include "exec/spinlock.h"
 182
 183 typedef struct TBContext TBContext;
 184
 185 struct TBContext {
 186
 187     TranslationBlock *tbs;
 188     TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
 189     int nb_tbs;
 190     /* any access to the tbs or the page table must use this lock */
 191     spinlock_t tb_lock;
 192
 193     /* statistics */
 194     int tb_flush_count;
 195     int tb_phys_invalidate_count;
 196
 197     int tb_invalidated_flag;
 198 };
 199
 200 void tb_free(TranslationBlock *tb);
 201 void tb_flush(CPUState *cpu);
 202 void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);
 203
 204 #if defined(USE_DIRECT_JUMP)
 205
 206 #if defined(CONFIG_TCG_INTERPRETER)
 207 static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
 208 {
 209     /* patch the branch destination */
 210     *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
 211     /* no need to flush icache explicitly */
 212 }
 213 #elif defined(_ARCH_PPC)
 214 void ppc_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr);
 215 #define tb_set_jmp_target1 ppc_tb_set_jmp_target
 216 #elif defined(__i386__) || defined(__x86_64__)
 217 static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
 218 {
 219     /* patch the branch destination */
 220     stl_le_p((void*)jmp_addr, addr - (jmp_addr + 4));
 221     /* no need to flush icache explicitly */
 222 }
 223 #elif defined(__s390x__)
 224 static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
 225 {
 226     /* patch the branch destination */
 227     intptr_t disp = addr - (jmp_addr - 2);
 228     stl_be_p((void*)jmp_addr, disp / 2);
 229     /* no need to flush icache explicitly */
 230 }
 231 #elif defined(__aarch64__)
 232 void aarch64_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr);
 233 #define tb_set_jmp_target1 aarch64_tb_set_jmp_target
 234 #elif defined(__arm__)
 235 static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
 236 {
 237 #if !QEMU_GNUC_PREREQ(4, 1)
 238     register unsigned long _beg __asm ("a1");
 239     register unsigned long _end __asm ("a2");
 240     register unsigned long _flg __asm ("a3");
 241 #endif
 242
 243     /* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */
 244     *(uint32_t *)jmp_addr =
 245         (*(uint32_t *)jmp_addr & ~0xffffff)
 246         | (((addr - (jmp_addr + 8)) >> 2) & 0xffffff);
 247
 248 #if QEMU_GNUC_PREREQ(4, 1)
 249     __builtin___clear_cache((char *) jmp_addr, (char *) jmp_addr + 4);
 250 #else
 251     /* flush icache */
 252     _beg = jmp_addr;
 253     _end = jmp_addr + 4;
 254     _flg = 0;
 255     __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
 256 #endif
 257 }
 258 #elif defined(__sparc__) || defined(__mips__)
 259 void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr);
 260 #else
 261 #error tb_set_jmp_target1 is missing
 262 #endif
 263
 264 static inline void tb_set_jmp_target(TranslationBlock *tb,
 265                                      int n, uintptr_t addr)
 266 {
 267     uint16_t offset = tb->tb_jmp_offset[n];
 268     tb_set_jmp_target1((uintptr_t)(tb->tc_ptr + offset), addr);
 269 }
 270
 271 #else
 272
 273 /* set the jump target */
 274 static inline void tb_set_jmp_target(TranslationBlock *tb,
 275                                      int n, uintptr_t addr)
 276 {
 277     tb->tb_next[n] = addr;
 278 }
 279
 280 #endif
 281
 282 static inline void tb_add_jump(TranslationBlock *tb, int n,
 283                                TranslationBlock *tb_next)
 284 {
 285     /* NOTE: this test is only needed for thread safety */
 286     if (!tb->jmp_next[n]) {
 287         /* patch the native jump address */
 288         tb_set_jmp_target(tb, n, (uintptr_t)tb_next->tc_ptr);
 289
 290         /* add in TB jmp circular list */
 291         tb->jmp_next[n] = tb_next->jmp_first;
 292         tb_next->jmp_first = (TranslationBlock *)((uintptr_t)(tb) | (n));
 293     }
 294 }
 295
 296 /* GETRA is the true target of the return instruction that we'll execute,
 297    defined here for simplicity of defining the follow-up macros.  */
 298 #if defined(CONFIG_TCG_INTERPRETER)
 299 extern uintptr_t tci_tb_ptr;
 300 # define GETRA() tci_tb_ptr
 301 #else
 302 # define GETRA() \
 303     ((uintptr_t)__builtin_extract_return_addr(__builtin_return_address(0)))
 304 #endif
 305
 306 /* The true return address will often point to a host insn that is part of
 307    the next translated guest insn.  Adjust the address backward to point to
 308    the middle of the call insn.  Subtracting one would do the job except for
 309    several compressed mode architectures (arm, mips) which set the low bit
 310    to indicate the compressed mode; subtracting two works around that.  It
 311    is also the case that there are no host isas that contain a call insn
 312    smaller than 4 bytes, so we don't worry about special-casing this.  */
 313 #if defined(CONFIG_TCG_INTERPRETER)
 314 # define GETPC_ADJ   0
 315 #else
 316 # define GETPC_ADJ   2
 317 #endif
 318
 319 #define GETPC()  (GETRA() - GETPC_ADJ)
 320
 321 #if !defined(CONFIG_USER_ONLY)
 322
 323 void phys_mem_set_alloc(void *(*alloc)(size_t, uint64_t *align));
 324
 325 struct MemoryRegion *iotlb_to_region(CPUState *cpu,
 326                                      hwaddr index);
 327
 328 void tlb_fill(CPUState *cpu, target_ulong addr, int is_write, int mmu_idx,
 329               uintptr_t retaddr);
 330
 331 #endif
 332
 333 #if defined(CONFIG_USER_ONLY)
 334 static inline tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr)
 335 {
 336     return addr;
 337 }
 338 #else
 339 /* cputlb.c */
 340 tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr);
 341 #endif
 342
 343 /* vl.c */
 344 extern int singlestep;
 345
 346 /* cpu-exec.c */
 347 extern volatile sig_atomic_t exit_request;
 348
 349 #if !defined(CONFIG_USER_ONLY)
 350 void migration_bitmap_extend(ram_addr_t old, ram_addr_t new);
 351 #endif
 352 #endif