include/hw/pci/pci.h

   1 #ifndef QEMU_PCI_H
   2 #define QEMU_PCI_H
   3
   4 #include "qemu-common.h"
   5
   6 #include "hw/qdev.h"
   7 #include "exec/memory.h"
   8 #include "sysemu/dma.h"
   9 #include "qapi/error.h"
  10
  11 /* PCI includes legacy ISA access.  */
  12 #include "hw/isa/isa.h"
  13
  14 #include "hw/pci/pcie.h"
  15
  16 /* PCI bus */
  17
  18 #define PCI_DEVFN(slot, func)   ((((slot) & 0x1f) << 3) | ((func) & 0x07))
  19 #define PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
  20 #define PCI_FUNC(devfn)         ((devfn) & 0x07)
  21 #define PCI_SLOT_MAX            32
  22 #define PCI_FUNC_MAX            8
  23
  24 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
  25 #include "hw/pci/pci_ids.h"
  26
  27 /* QEMU-specific Vendor and Device ID definitions */
  28
  29 /* IBM (0x1014) */
  30 #define PCI_DEVICE_ID_IBM_440GX          0x027f
  31 #define PCI_DEVICE_ID_IBM_OPENPIC2       0xffff
  32
  33 /* Hitachi (0x1054) */
  34 #define PCI_VENDOR_ID_HITACHI            0x1054
  35 #define PCI_DEVICE_ID_HITACHI_SH7751R    0x350e
  36
  37 /* Apple (0x106b) */
  38 #define PCI_DEVICE_ID_APPLE_343S1201     0x0010
  39 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI  0x001e
  40 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI    0x001f
  41 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL   0x0022
  42 #define PCI_DEVICE_ID_APPLE_IPID_USB     0x003f
  43
  44 /* Realtek (0x10ec) */
  45 #define PCI_DEVICE_ID_REALTEK_8029       0x8029
  46
  47 /* Xilinx (0x10ee) */
  48 #define PCI_DEVICE_ID_XILINX_XC2VP30     0x0300
  49
  50 /* Marvell (0x11ab) */
  51 #define PCI_DEVICE_ID_MARVELL_GT6412X    0x4620
  52
  53 /* QEMU/Bochs VGA (0x1234) */
  54 #define PCI_VENDOR_ID_QEMU               0x1234
  55 #define PCI_DEVICE_ID_QEMU_VGA           0x1111
  56
  57 /* VMWare (0x15ad) */
  58 #define PCI_VENDOR_ID_VMWARE             0x15ad
  59 #define PCI_DEVICE_ID_VMWARE_SVGA2       0x0405
  60 #define PCI_DEVICE_ID_VMWARE_SVGA        0x0710
  61 #define PCI_DEVICE_ID_VMWARE_NET         0x0720
  62 #define PCI_DEVICE_ID_VMWARE_SCSI        0x0730
  63 #define PCI_DEVICE_ID_VMWARE_PVSCSI      0x07C0
  64 #define PCI_DEVICE_ID_VMWARE_IDE         0x1729
  65 #define PCI_DEVICE_ID_VMWARE_VMXNET3     0x07B0
  66
  67 /* Intel (0x8086) */
  68 #define PCI_DEVICE_ID_INTEL_82551IT      0x1209
  69 #define PCI_DEVICE_ID_INTEL_82557        0x1229
  70 #define PCI_DEVICE_ID_INTEL_82801IR      0x2922
  71
  72 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
  73 #define PCI_VENDOR_ID_REDHAT_QUMRANET    0x1af4
  74 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
  75 #define PCI_SUBDEVICE_ID_QEMU            0x1100
  76
  77 #define PCI_DEVICE_ID_VIRTIO_NET         0x1000
  78 #define PCI_DEVICE_ID_VIRTIO_BLOCK       0x1001
  79 #define PCI_DEVICE_ID_VIRTIO_BALLOON     0x1002
  80 #define PCI_DEVICE_ID_VIRTIO_CONSOLE     0x1003
  81 #define PCI_DEVICE_ID_VIRTIO_SCSI        0x1004
  82 #define PCI_DEVICE_ID_VIRTIO_RNG         0x1005
  83 #define PCI_DEVICE_ID_VIRTIO_9P          0x1009
  84
  85 #define PCI_VENDOR_ID_REDHAT             0x1b36
  86 #define PCI_DEVICE_ID_REDHAT_BRIDGE      0x0001
  87 #define PCI_DEVICE_ID_REDHAT_SERIAL      0x0002
  88 #define PCI_DEVICE_ID_REDHAT_SERIAL2     0x0003
  89 #define PCI_DEVICE_ID_REDHAT_SERIAL4     0x0004
  90 #define PCI_DEVICE_ID_REDHAT_TEST        0x0005
  91 #define PCI_DEVICE_ID_REDHAT_ROCKER      0x0006
  92 #define PCI_DEVICE_ID_REDHAT_SDHCI       0x0007
  93 #define PCI_DEVICE_ID_REDHAT_PCIE_HOST   0x0008
  94 #define PCI_DEVICE_ID_REDHAT_PXB         0x0009
  95 #define PCI_DEVICE_ID_REDHAT_QXL         0x0100
  96
  97 #define FMT_PCIBUS                      PRIx64
  98
  99 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
 100                                 uint32_t address, uint32_t data, int len);
 101 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
 102                                    uint32_t address, int len);
 103 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
 104                                 pcibus_t addr, pcibus_t size, int type);
 105 typedef void PCIUnregisterFunc(PCIDevice *pci_dev);
 106
 107 typedef struct PCIIORegion {
 108     pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
 109 #define PCI_BAR_UNMAPPED (~(pcibus_t)0)
 110     pcibus_t size;
 111     uint8_t type;
 112     MemoryRegion *memory;
 113     MemoryRegion *address_space;
 114 } PCIIORegion;
 115
 116 #define PCI_ROM_SLOT 6
 117 #define PCI_NUM_REGIONS 7
 118
 119 enum {
 120     QEMU_PCI_VGA_MEM,
 121     QEMU_PCI_VGA_IO_LO,
 122     QEMU_PCI_VGA_IO_HI,
 123     QEMU_PCI_VGA_NUM_REGIONS,
 124 };
 125
 126 #define QEMU_PCI_VGA_MEM_BASE 0xa0000
 127 #define QEMU_PCI_VGA_MEM_SIZE 0x20000
 128 #define QEMU_PCI_VGA_IO_LO_BASE 0x3b0
 129 #define QEMU_PCI_VGA_IO_LO_SIZE 0xc
 130 #define QEMU_PCI_VGA_IO_HI_BASE 0x3c0
 131 #define QEMU_PCI_VGA_IO_HI_SIZE 0x20
 132
 133 #include "hw/pci/pci_regs.h"
 134
 135 /* PCI HEADER_TYPE */
 136 #define  PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
 137
 138 /* Size of the standard PCI config header */
 139 #define PCI_CONFIG_HEADER_SIZE 0x40
 140 /* Size of the standard PCI config space */
 141 #define PCI_CONFIG_SPACE_SIZE 0x100
 142 /* Size of the standard PCIe config space: 4KB */
 143 #define PCIE_CONFIG_SPACE_SIZE  0x1000
 144
 145 #define PCI_NUM_PINS 4 /* A-D */
 146
 147 /* Bits in cap_present field. */
 148 enum {
 149     QEMU_PCI_CAP_MSI = 0x1,
 150     QEMU_PCI_CAP_MSIX = 0x2,
 151     QEMU_PCI_CAP_EXPRESS = 0x4,
 152
 153     /* multifunction capable device */
 154 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR        3
 155     QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
 156
 157     /* command register SERR bit enabled */
 158 #define QEMU_PCI_CAP_SERR_BITNR 4
 159     QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
 160     /* Standard hot plug controller. */
 161 #define QEMU_PCI_SHPC_BITNR 5
 162     QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR),
 163 #define QEMU_PCI_SLOTID_BITNR 6
 164     QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR),
 165     /* PCI Express capability - Power Controller Present */
 166 #define QEMU_PCIE_SLTCAP_PCP_BITNR 7
 167     QEMU_PCIE_SLTCAP_PCP = (1 << QEMU_PCIE_SLTCAP_PCP_BITNR),
 168 };
 169
 170 #define TYPE_PCI_DEVICE "pci-device"
 171 #define PCI_DEVICE(obj) \
 172      OBJECT_CHECK(PCIDevice, (obj), TYPE_PCI_DEVICE)
 173 #define PCI_DEVICE_CLASS(klass) \
 174      OBJECT_CLASS_CHECK(PCIDeviceClass, (klass), TYPE_PCI_DEVICE)
 175 #define PCI_DEVICE_GET_CLASS(obj) \
 176      OBJECT_GET_CLASS(PCIDeviceClass, (obj), TYPE_PCI_DEVICE)
 177
 178 typedef struct PCIINTxRoute {
 179     enum {
 180         PCI_INTX_ENABLED,
 181         PCI_INTX_INVERTED,
 182         PCI_INTX_DISABLED,
 183     } mode;
 184     int irq;
 185 } PCIINTxRoute;
 186
 187 typedef struct PCIDeviceClass {
 188     DeviceClass parent_class;
 189
 190     void (*realize)(PCIDevice *dev, Error **errp);
 191     int (*init)(PCIDevice *dev);/* TODO convert to realize() and remove */
 192     PCIUnregisterFunc *exit;
 193     PCIConfigReadFunc *config_read;
 194     PCIConfigWriteFunc *config_write;
 195
 196     uint16_t vendor_id;
 197     uint16_t device_id;
 198     uint8_t revision;
 199     uint16_t class_id;
 200     uint16_t subsystem_vendor_id;       /* only for header type = 0 */
 201     uint16_t subsystem_id;              /* only for header type = 0 */
 202
 203     /*
 204      * pci-to-pci bridge or normal device.
 205      * This doesn't mean pci host switch.
 206      * When card bus bridge is supported, this would be enhanced.
 207      */
 208     int is_bridge;
 209
 210     /* pcie stuff */
 211     int is_express;   /* is this device pci express? */
 212
 213     /* rom bar */
 214     const char *romfile;
 215 } PCIDeviceClass;
 216
 217 typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev);
 218 typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector,
 219                                       MSIMessage msg);
 220 typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector);
 221 typedef void (*MSIVectorPollNotifier)(PCIDevice *dev,
 222                                       unsigned int vector_start,
 223                                       unsigned int vector_end);
 224
 225 struct PCIDevice {
 226     DeviceState qdev;
 227
 228     /* PCI config space */
 229     uint8_t *config;
 230
 231     /* Used to enable config checks on load. Note that writable bits are
 232      * never checked even if set in cmask. */
 233     uint8_t *cmask;
 234
 235     /* Used to implement R/W bytes */
 236     uint8_t *wmask;
 237
 238     /* Used to implement RW1C(Write 1 to Clear) bytes */
 239     uint8_t *w1cmask;
 240
 241     /* Used to allocate config space for capabilities. */
 242     uint8_t *used;
 243
 244     /* the following fields are read only */
 245     PCIBus *bus;
 246     int32_t devfn;
 247     char name[64];
 248     PCIIORegion io_regions[PCI_NUM_REGIONS];
 249     AddressSpace bus_master_as;
 250     MemoryRegion bus_master_enable_region;
 251
 252     /* do not access the following fields */
 253     PCIConfigReadFunc *config_read;
 254     PCIConfigWriteFunc *config_write;
 255
 256     /* Legacy PCI VGA regions */
 257     MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS];
 258     bool has_vga;
 259
 260     /* Current IRQ levels.  Used internally by the generic PCI code.  */
 261     uint8_t irq_state;
 262
 263     /* Capability bits */
 264     uint32_t cap_present;
 265
 266     /* Offset of MSI-X capability in config space */
 267     uint8_t msix_cap;
 268
 269     /* MSI-X entries */
 270     int msix_entries_nr;
 271
 272     /* Space to store MSIX table & pending bit array */
 273     uint8_t *msix_table;
 274     uint8_t *msix_pba;
 275     /* MemoryRegion container for msix exclusive BAR setup */
 276     MemoryRegion msix_exclusive_bar;
 277     /* Memory Regions for MSIX table and pending bit entries. */
 278     MemoryRegion msix_table_mmio;
 279     MemoryRegion msix_pba_mmio;
 280     /* Reference-count for entries actually in use by driver. */
 281     unsigned *msix_entry_used;
 282     /* MSIX function mask set or MSIX disabled */
 283     bool msix_function_masked;
 284     /* Version id needed for VMState */
 285     int32_t version_id;
 286
 287     /* Offset of MSI capability in config space */
 288     uint8_t msi_cap;
 289
 290     /* PCI Express */
 291     PCIExpressDevice exp;
 292
 293     /* SHPC */
 294     SHPCDevice *shpc;
 295
 296     /* Location of option rom */
 297     char *romfile;
 298     bool has_rom;
 299     MemoryRegion rom;
 300     uint32_t rom_bar;
 301
 302     /* INTx routing notifier */
 303     PCIINTxRoutingNotifier intx_routing_notifier;
 304
 305     /* MSI-X notifiers */
 306     MSIVectorUseNotifier msix_vector_use_notifier;
 307     MSIVectorReleaseNotifier msix_vector_release_notifier;
 308     MSIVectorPollNotifier msix_vector_poll_notifier;
 309 };
 310
 311 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 312                       uint8_t attr, MemoryRegion *memory);
 313 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem,
 314                       MemoryRegion *io_lo, MemoryRegion *io_hi);
 315 void pci_unregister_vga(PCIDevice *pci_dev);
 316 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num);
 317
 318 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
 319                        uint8_t offset, uint8_t size);
 320 int pci_add_capability2(PCIDevice *pdev, uint8_t cap_id,
 321                        uint8_t offset, uint8_t size,
 322                        Error **errp);
 323
 324 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
 325
 326 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
 327
 328
 329 uint32_t pci_default_read_config(PCIDevice *d,
 330                                  uint32_t address, int len);
 331 void pci_default_write_config(PCIDevice *d,
 332                               uint32_t address, uint32_t val, int len);
 333 void pci_device_save(PCIDevice *s, QEMUFile *f);
 334 int pci_device_load(PCIDevice *s, QEMUFile *f);
 335 MemoryRegion *pci_address_space(PCIDevice *dev);
 336 MemoryRegion *pci_address_space_io(PCIDevice *dev);
 337
 338 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
 339 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
 340 typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin);
 341
 342 #define TYPE_PCI_BUS "PCI"
 343 #define PCI_BUS(obj) OBJECT_CHECK(PCIBus, (obj), TYPE_PCI_BUS)
 344 #define PCI_BUS_CLASS(klass) OBJECT_CLASS_CHECK(PCIBusClass, (klass), TYPE_PCI_BUS)
 345 #define PCI_BUS_GET_CLASS(obj) OBJECT_GET_CLASS(PCIBusClass, (obj), TYPE_PCI_BUS)
 346 #define TYPE_PCIE_BUS "PCIE"
 347
 348 bool pci_bus_is_express(PCIBus *bus);
 349 bool pci_bus_is_root(PCIBus *bus);
 350 void pci_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent,
 351                          const char *name,
 352                          MemoryRegion *address_space_mem,
 353                          MemoryRegion *address_space_io,
 354                          uint8_t devfn_min, const char *typename);
 355 PCIBus *pci_bus_new(DeviceState *parent, const char *name,
 356                     MemoryRegion *address_space_mem,
 357                     MemoryRegion *address_space_io,
 358                     uint8_t devfn_min, const char *typename);
 359 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 360                   void *irq_opaque, int nirq);
 361 int pci_bus_get_irq_level(PCIBus *bus, int irq_num);
 362 /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */
 363 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin);
 364 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 365                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 366                          void *irq_opaque,
 367                          MemoryRegion *address_space_mem,
 368                          MemoryRegion *address_space_io,
 369                          uint8_t devfn_min, int nirq, const char *typename);
 370 void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn);
 371 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin);
 372 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new);
 373 void pci_bus_fire_intx_routing_notifier(PCIBus *bus);
 374 void pci_device_set_intx_routing_notifier(PCIDevice *dev,
 375                                           PCIINTxRoutingNotifier notifier);
 376 void pci_device_reset(PCIDevice *dev);
 377
 378 PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus,
 379                                const char *default_model,
 380                                const char *default_devaddr);
 381
 382 PCIDevice *pci_vga_init(PCIBus *bus);
 383
 384 int pci_bus_num(PCIBus *s);
 385 void pci_for_each_device(PCIBus *bus, int bus_num,
 386                          void (*fn)(PCIBus *bus, PCIDevice *d, void *opaque),
 387                          void *opaque);
 388 void pci_for_each_bus_depth_first(PCIBus *bus,
 389                                   void *(*begin)(PCIBus *bus, void *parent_state),
 390                                   void (*end)(PCIBus *bus, void *state),
 391                                   void *parent_state);
 392
 393 /* Use this wrapper when specific scan order is not required. */
 394 static inline
 395 void pci_for_each_bus(PCIBus *bus,
 396                       void (*fn)(PCIBus *bus, void *opaque),
 397                       void *opaque)
 398 {
 399     pci_for_each_bus_depth_first(bus, NULL, fn, opaque);
 400 }
 401
 402 PCIBus *pci_find_primary_bus(void);
 403 PCIBus *pci_device_root_bus(const PCIDevice *d);
 404 const char *pci_root_bus_path(PCIDevice *dev);
 405 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn);
 406 int pci_qdev_find_device(const char *id, PCIDevice **pdev);
 407 void pci_bus_get_w64_range(PCIBus *bus, Range *range);
 408
 409 void pci_device_deassert_intx(PCIDevice *dev);
 410
 411 typedef AddressSpace *(*PCIIOMMUFunc)(PCIBus *, void *, int);
 412
 413 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev);
 414 void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque);
 415
 416 static inline void
 417 pci_set_byte(uint8_t *config, uint8_t val)
 418 {
 419     *config = val;
 420 }
 421
 422 static inline uint8_t
 423 pci_get_byte(const uint8_t *config)
 424 {
 425     return *config;
 426 }
 427
 428 static inline void
 429 pci_set_word(uint8_t *config, uint16_t val)
 430 {
 431     stw_le_p(config, val);
 432 }
 433
 434 static inline uint16_t
 435 pci_get_word(const uint8_t *config)
 436 {
 437     return lduw_le_p(config);
 438 }
 439
 440 static inline void
 441 pci_set_long(uint8_t *config, uint32_t val)
 442 {
 443     stl_le_p(config, val);
 444 }
 445
 446 static inline uint32_t
 447 pci_get_long(const uint8_t *config)
 448 {
 449     return ldl_le_p(config);
 450 }
 451
 452 static inline void
 453 pci_set_quad(uint8_t *config, uint64_t val)
 454 {
 455     cpu_to_le64w((uint64_t *)config, val);
 456 }
 457
 458 static inline uint64_t
 459 pci_get_quad(const uint8_t *config)
 460 {
 461     return le64_to_cpup((const uint64_t *)config);
 462 }
 463
 464 static inline void
 465 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
 466 {
 467     pci_set_word(&pci_config[PCI_VENDOR_ID], val);
 468 }
 469
 470 static inline void
 471 pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
 472 {
 473     pci_set_word(&pci_config[PCI_DEVICE_ID], val);
 474 }
 475
 476 static inline void
 477 pci_config_set_revision(uint8_t *pci_config, uint8_t val)
 478 {
 479     pci_set_byte(&pci_config[PCI_REVISION_ID], val);
 480 }
 481
 482 static inline void
 483 pci_config_set_class(uint8_t *pci_config, uint16_t val)
 484 {
 485     pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
 486 }
 487
 488 static inline void
 489 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val)
 490 {
 491     pci_set_byte(&pci_config[PCI_CLASS_PROG], val);
 492 }
 493
 494 static inline void
 495 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val)
 496 {
 497     pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val);
 498 }
 499
 500 /*
 501  * helper functions to do bit mask operation on configuration space.
 502  * Just to set bit, use test-and-set and discard returned value.
 503  * Just to clear bit, use test-and-clear and discard returned value.
 504  * NOTE: They aren't atomic.
 505  */
 506 static inline uint8_t
 507 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask)
 508 {
 509     uint8_t val = pci_get_byte(config);
 510     pci_set_byte(config, val & ~mask);
 511     return val & mask;
 512 }
 513
 514 static inline uint8_t
 515 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask)
 516 {
 517     uint8_t val = pci_get_byte(config);
 518     pci_set_byte(config, val | mask);
 519     return val & mask;
 520 }
 521
 522 static inline uint16_t
 523 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask)
 524 {
 525     uint16_t val = pci_get_word(config);
 526     pci_set_word(config, val & ~mask);
 527     return val & mask;
 528 }
 529
 530 static inline uint16_t
 531 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask)
 532 {
 533     uint16_t val = pci_get_word(config);
 534     pci_set_word(config, val | mask);
 535     return val & mask;
 536 }
 537
 538 static inline uint32_t
 539 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask)
 540 {
 541     uint32_t val = pci_get_long(config);
 542     pci_set_long(config, val & ~mask);
 543     return val & mask;
 544 }
 545
 546 static inline uint32_t
 547 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask)
 548 {
 549     uint32_t val = pci_get_long(config);
 550     pci_set_long(config, val | mask);
 551     return val & mask;
 552 }
 553
 554 static inline uint64_t
 555 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask)
 556 {
 557     uint64_t val = pci_get_quad(config);
 558     pci_set_quad(config, val & ~mask);
 559     return val & mask;
 560 }
 561
 562 static inline uint64_t
 563 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask)
 564 {
 565     uint64_t val = pci_get_quad(config);
 566     pci_set_quad(config, val | mask);
 567     return val & mask;
 568 }
 569
 570 /* Access a register specified by a mask */
 571 static inline void
 572 pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg)
 573 {
 574     uint8_t val = pci_get_byte(config);
 575     uint8_t rval = reg << ctz32(mask);
 576     pci_set_byte(config, (~mask & val) | (mask & rval));
 577 }
 578
 579 static inline uint8_t
 580 pci_get_byte_by_mask(uint8_t *config, uint8_t mask)
 581 {
 582     uint8_t val = pci_get_byte(config);
 583     return (val & mask) >> ctz32(mask);
 584 }
 585
 586 static inline void
 587 pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg)
 588 {
 589     uint16_t val = pci_get_word(config);
 590     uint16_t rval = reg << ctz32(mask);
 591     pci_set_word(config, (~mask & val) | (mask & rval));
 592 }
 593
 594 static inline uint16_t
 595 pci_get_word_by_mask(uint8_t *config, uint16_t mask)
 596 {
 597     uint16_t val = pci_get_word(config);
 598     return (val & mask) >> ctz32(mask);
 599 }
 600
 601 static inline void
 602 pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg)
 603 {
 604     uint32_t val = pci_get_long(config);
 605     uint32_t rval = reg << ctz32(mask);
 606     pci_set_long(config, (~mask & val) | (mask & rval));
 607 }
 608
 609 static inline uint32_t
 610 pci_get_long_by_mask(uint8_t *config, uint32_t mask)
 611 {
 612     uint32_t val = pci_get_long(config);
 613     return (val & mask) >> ctz32(mask);
 614 }
 615
 616 static inline void
 617 pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg)
 618 {
 619     uint64_t val = pci_get_quad(config);
 620     uint64_t rval = reg << ctz32(mask);
 621     pci_set_quad(config, (~mask & val) | (mask & rval));
 622 }
 623
 624 static inline uint64_t
 625 pci_get_quad_by_mask(uint8_t *config, uint64_t mask)
 626 {
 627     uint64_t val = pci_get_quad(config);
 628     return (val & mask) >> ctz32(mask);
 629 }
 630
 631 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
 632                                     const char *name);
 633 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
 634                                            bool multifunction,
 635                                            const char *name);
 636 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name);
 637 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
 638
 639 qemu_irq pci_allocate_irq(PCIDevice *pci_dev);
 640 void pci_set_irq(PCIDevice *pci_dev, int level);
 641
 642 static inline void pci_irq_assert(PCIDevice *pci_dev)
 643 {
 644     pci_set_irq(pci_dev, 1);
 645 }
 646
 647 static inline void pci_irq_deassert(PCIDevice *pci_dev)
 648 {
 649     pci_set_irq(pci_dev, 0);
 650 }
 651
 652 /*
 653  * FIXME: PCI does not work this way.
 654  * All the callers to this method should be fixed.
 655  */
 656 static inline void pci_irq_pulse(PCIDevice *pci_dev)
 657 {
 658     pci_irq_assert(pci_dev);
 659     pci_irq_deassert(pci_dev);
 660 }
 661
 662 static inline int pci_is_express(const PCIDevice *d)
 663 {
 664     return d->cap_present & QEMU_PCI_CAP_EXPRESS;
 665 }
 666
 667 static inline uint32_t pci_config_size(const PCIDevice *d)
 668 {
 669     return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
 670 }
 671
 672 /* DMA access functions */
 673 static inline AddressSpace *pci_get_address_space(PCIDevice *dev)
 674 {
 675     return &dev->bus_master_as;
 676 }
 677
 678 static inline int pci_dma_rw(PCIDevice *dev, dma_addr_t addr,
 679                              void *buf, dma_addr_t len, DMADirection dir)
 680 {
 681     dma_memory_rw(pci_get_address_space(dev), addr, buf, len, dir);
 682     return 0;
 683 }
 684
 685 static inline int pci_dma_read(PCIDevice *dev, dma_addr_t addr,
 686                                void *buf, dma_addr_t len)
 687 {
 688     return pci_dma_rw(dev, addr, buf, len, DMA_DIRECTION_TO_DEVICE);
 689 }
 690
 691 static inline int pci_dma_write(PCIDevice *dev, dma_addr_t addr,
 692                                 const void *buf, dma_addr_t len)
 693 {
 694     return pci_dma_rw(dev, addr, (void *) buf, len, DMA_DIRECTION_FROM_DEVICE);
 695 }
 696
 697 #define PCI_DMA_DEFINE_LDST(_l, _s, _bits)                              \
 698     static inline uint##_bits##_t ld##_l##_pci_dma(PCIDevice *dev,      \
 699                                                    dma_addr_t addr)     \
 700     {                                                                   \
 701         return ld##_l##_dma(pci_get_address_space(dev), addr);          \
 702     }                                                                   \
 703     static inline void st##_s##_pci_dma(PCIDevice *dev,                 \
 704                                         dma_addr_t addr, uint##_bits##_t val) \
 705     {                                                                   \
 706         st##_s##_dma(pci_get_address_space(dev), addr, val);            \
 707     }
 708
 709 PCI_DMA_DEFINE_LDST(ub, b, 8);
 710 PCI_DMA_DEFINE_LDST(uw_le, w_le, 16)
 711 PCI_DMA_DEFINE_LDST(l_le, l_le, 32);
 712 PCI_DMA_DEFINE_LDST(q_le, q_le, 64);
 713 PCI_DMA_DEFINE_LDST(uw_be, w_be, 16)
 714 PCI_DMA_DEFINE_LDST(l_be, l_be, 32);
 715 PCI_DMA_DEFINE_LDST(q_be, q_be, 64);
 716
 717 #undef PCI_DMA_DEFINE_LDST
 718
 719 static inline void *pci_dma_map(PCIDevice *dev, dma_addr_t addr,
 720                                 dma_addr_t *plen, DMADirection dir)
 721 {
 722     void *buf;
 723
 724     buf = dma_memory_map(pci_get_address_space(dev), addr, plen, dir);
 725     return buf;
 726 }
 727
 728 static inline void pci_dma_unmap(PCIDevice *dev, void *buffer, dma_addr_t len,
 729                                  DMADirection dir, dma_addr_t access_len)
 730 {
 731     dma_memory_unmap(pci_get_address_space(dev), buffer, len, dir, access_len);
 732 }
 733
 734 static inline void pci_dma_sglist_init(QEMUSGList *qsg, PCIDevice *dev,
 735                                        int alloc_hint)
 736 {
 737     qemu_sglist_init(qsg, DEVICE(dev), alloc_hint, pci_get_address_space(dev));
 738 }
 739
 740 extern const VMStateDescription vmstate_pci_device;
 741
 742 #define VMSTATE_PCI_DEVICE(_field, _state) {                         \
 743     .name       = (stringify(_field)),                               \
 744     .size       = sizeof(PCIDevice),                                 \
 745     .vmsd       = &vmstate_pci_device,                               \
 746     .flags      = VMS_STRUCT,                                        \
 747     .offset     = vmstate_offset_value(_state, _field, PCIDevice),   \
 748 }
 749
 750 #define VMSTATE_PCI_DEVICE_POINTER(_field, _state) {                 \
 751     .name       = (stringify(_field)),                               \
 752     .size       = sizeof(PCIDevice),                                 \
 753     .vmsd       = &vmstate_pci_device,                               \
 754     .flags      = VMS_STRUCT|VMS_POINTER,                            \
 755     .offset     = vmstate_offset_pointer(_state, _field, PCIDevice), \
 756 }
 757
 758 #endif