2 * RISC-V translation routines for the RV64A Standard Extension.
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
6 * Bastian Koppelmann, kbastian@mail.uni-paderborn.de
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
21 static inline bool gen_lr(DisasContext
*ctx
, arg_atomic
*a
, TCGMemOp mop
)
23 TCGv src1
= tcg_temp_new();
24 /* Put addr in load_res, data in load_val. */
25 gen_get_gpr(src1
, a
->rs1
);
27 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_STRL
);
29 tcg_gen_qemu_ld_tl(load_val
, src1
, ctx
->mem_idx
, mop
);
31 tcg_gen_mb(TCG_MO_ALL
| TCG_BAR_LDAQ
);
33 tcg_gen_mov_tl(load_res
, src1
);
34 gen_set_gpr(a
->rd
, load_val
);
40 static inline bool gen_sc(DisasContext
*ctx
, arg_atomic
*a
, TCGMemOp mop
)
42 TCGv src1
= tcg_temp_new();
43 TCGv src2
= tcg_temp_new();
44 TCGv dat
= tcg_temp_new();
45 TCGLabel
*l1
= gen_new_label();
46 TCGLabel
*l2
= gen_new_label();
48 gen_get_gpr(src1
, a
->rs1
);
49 tcg_gen_brcond_tl(TCG_COND_NE
, load_res
, src1
, l1
);
51 gen_get_gpr(src2
, a
->rs2
);
53 * Note that the TCG atomic primitives are SC,
54 * so we can ignore AQ/RL along this path.
56 tcg_gen_atomic_cmpxchg_tl(src1
, load_res
, load_val
, src2
,
58 tcg_gen_setcond_tl(TCG_COND_NE
, dat
, src1
, load_val
);
59 gen_set_gpr(a
->rd
, dat
);
64 * Address comparion failure. However, we still need to
65 * provide the memory barrier implied by AQ/RL.
67 tcg_gen_mb(TCG_MO_ALL
+ a
->aq
* TCG_BAR_LDAQ
+ a
->rl
* TCG_BAR_STRL
);
68 tcg_gen_movi_tl(dat
, 1);
69 gen_set_gpr(a
->rd
, dat
);
78 static bool gen_amo(DisasContext
*ctx
, arg_atomic
*a
,
79 void(*func
)(TCGv
, TCGv
, TCGv
, TCGArg
, TCGMemOp
),
82 TCGv src1
= tcg_temp_new();
83 TCGv src2
= tcg_temp_new();
85 gen_get_gpr(src1
, a
->rs1
);
86 gen_get_gpr(src2
, a
->rs2
);
88 (*func
)(src2
, src1
, src2
, ctx
->mem_idx
, mop
);
90 gen_set_gpr(a
->rd
, src2
);
96 static bool trans_lr_w(DisasContext
*ctx
, arg_lr_w
*a
)
98 REQUIRE_EXT(ctx
, RVA
);
99 return gen_lr(ctx
, a
, (MO_ALIGN
| MO_TESL
));
102 static bool trans_sc_w(DisasContext
*ctx
, arg_sc_w
*a
)
104 REQUIRE_EXT(ctx
, RVA
);
105 return gen_sc(ctx
, a
, (MO_ALIGN
| MO_TESL
));
108 static bool trans_amoswap_w(DisasContext
*ctx
, arg_amoswap_w
*a
)
110 REQUIRE_EXT(ctx
, RVA
);
111 return gen_amo(ctx
, a
, &tcg_gen_atomic_xchg_tl
, (MO_ALIGN
| MO_TESL
));
114 static bool trans_amoadd_w(DisasContext
*ctx
, arg_amoadd_w
*a
)
116 REQUIRE_EXT(ctx
, RVA
);
117 return gen_amo(ctx
, a
, &tcg_gen_atomic_fetch_add_tl
, (MO_ALIGN
| MO_TESL
));
120 static bool trans_amoxor_w(DisasContext
*ctx
, arg_amoxor_w
*a
)
122 REQUIRE_EXT(ctx
, RVA
);
123 return gen_amo(ctx
, a
, &tcg_gen_atomic_fetch_xor_tl
, (MO_ALIGN
| MO_TESL
));
126 static bool trans_amoand_w(DisasContext
*ctx
, arg_amoand_w
*a
)
128 REQUIRE_EXT(ctx
, RVA
);
129 return gen_amo(ctx
, a
, &tcg_gen_atomic_fetch_and_tl
, (MO_ALIGN
| MO_TESL
));
132 static bool trans_amoor_w(DisasContext
*ctx
, arg_amoor_w
*a
)
134 REQUIRE_EXT(ctx
, RVA
);
135 return gen_amo(ctx
, a
, &tcg_gen_atomic_fetch_or_tl
, (MO_ALIGN
| MO_TESL
));
138 static bool trans_amomin_w(DisasContext
*ctx
, arg_amomin_w
*a
)
140 REQUIRE_EXT(ctx
, RVA
);
141 return gen_amo(ctx
, a
, &tcg_gen_atomic_fetch_smin_tl
, (MO_ALIGN
| MO_TESL
));
144 static bool trans_amomax_w(DisasContext
*ctx
, arg_amomax_w
*a
)
146 REQUIRE_EXT(ctx
, RVA
);
147 return gen_amo(ctx
, a
, &tcg_gen_atomic_fetch_smax_tl
, (MO_ALIGN
| MO_TESL
));
150 static bool trans_amominu_w(DisasContext
*ctx
, arg_amominu_w
*a
)
152 REQUIRE_EXT(ctx
, RVA
);
153 return gen_amo(ctx
, a
, &tcg_gen_atomic_fetch_umin_tl
, (MO_ALIGN
| MO_TESL
));
156 static bool trans_amomaxu_w(DisasContext
*ctx
, arg_amomaxu_w
*a
)
158 REQUIRE_EXT(ctx
, RVA
);
159 return gen_amo(ctx
, a
, &tcg_gen_atomic_fetch_umax_tl
, (MO_ALIGN
| MO_TESL
));
162 #ifdef TARGET_RISCV64
164 static bool trans_lr_d(DisasContext
*ctx
, arg_lr_d
*a
)
166 return gen_lr(ctx
, a
, MO_ALIGN
| MO_TEQ
);
169 static bool trans_sc_d(DisasContext
*ctx
, arg_sc_d
*a
)
171 return gen_sc(ctx
, a
, (MO_ALIGN
| MO_TEQ
));
174 static bool trans_amoswap_d(DisasContext
*ctx
, arg_amoswap_d
*a
)
176 return gen_amo(ctx
, a
, &tcg_gen_atomic_xchg_tl
, (MO_ALIGN
| MO_TEQ
));
179 static bool trans_amoadd_d(DisasContext
*ctx
, arg_amoadd_d
*a
)
181 return gen_amo(ctx
, a
, &tcg_gen_atomic_fetch_add_tl
, (MO_ALIGN
| MO_TEQ
));
184 static bool trans_amoxor_d(DisasContext
*ctx
, arg_amoxor_d
*a
)
186 return gen_amo(ctx
, a
, &tcg_gen_atomic_fetch_xor_tl
, (MO_ALIGN
| MO_TEQ
));
189 static bool trans_amoand_d(DisasContext
*ctx
, arg_amoand_d
*a
)
191 return gen_amo(ctx
, a
, &tcg_gen_atomic_fetch_and_tl
, (MO_ALIGN
| MO_TEQ
));
194 static bool trans_amoor_d(DisasContext
*ctx
, arg_amoor_d
*a
)
196 return gen_amo(ctx
, a
, &tcg_gen_atomic_fetch_or_tl
, (MO_ALIGN
| MO_TEQ
));
199 static bool trans_amomin_d(DisasContext
*ctx
, arg_amomin_d
*a
)
201 return gen_amo(ctx
, a
, &tcg_gen_atomic_fetch_smin_tl
, (MO_ALIGN
| MO_TEQ
));
204 static bool trans_amomax_d(DisasContext
*ctx
, arg_amomax_d
*a
)
206 return gen_amo(ctx
, a
, &tcg_gen_atomic_fetch_smax_tl
, (MO_ALIGN
| MO_TEQ
));
209 static bool trans_amominu_d(DisasContext
*ctx
, arg_amominu_d
*a
)
211 return gen_amo(ctx
, a
, &tcg_gen_atomic_fetch_umin_tl
, (MO_ALIGN
| MO_TEQ
));
214 static bool trans_amomaxu_d(DisasContext
*ctx
, arg_amomaxu_d
*a
)
216 return gen_amo(ctx
, a
, &tcg_gen_atomic_fetch_umax_tl
, (MO_ALIGN
| MO_TEQ
));