| blob | 75133ce65967b623fdce3ad2edd87332d06bf566 |
1 # AArch64 SVE instruction descriptions
2 #
3 # Copyright (c) 2017 Linaro, Ltd
4 #
5 # This library is free software; you can redistribute it and/or
6 # modify it under the terms of the GNU Lesser General Public
7 # License as published by the Free Software Foundation; either
8 # version 2 of the License, or (at your option) any later version.
9 #
10 # This library is distributed in the hope that it will be useful,
11 # but WITHOUT ANY WARRANTY; without even the implied warranty of
12 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 # Lesser General Public License for more details.
14 #
15 # You should have received a copy of the GNU Lesser General Public
16 # License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 #
19 # This file is processed by scripts/decodetree.py
20 #
22 ###########################################################################
23 # Named fields. These are primarily for disjoint fields.
25 %imm4_16_p1 16:4 !function=plus1
26 %imm6_22_5 22:1 5:5
27 %imm7_22_16 22:2 16:5
28 %imm8_16_10 16:5 10:3
29 %imm9_16_10 16:s6 10:3
30 %size_23 23:2
31 %dtype_23_13 23:2 13:2
33 # A combination of tsz:imm3 -- extract esize.
34 %tszimm_esz 22:2 5:5 !function=tszimm_esz
35 # A combination of tsz:imm3 -- extract (2 * esize) - (tsz:imm3)
36 %tszimm_shr 22:2 5:5 !function=tszimm_shr
37 # A combination of tsz:imm3 -- extract (tsz:imm3) - esize
38 %tszimm_shl 22:2 5:5 !function=tszimm_shl
40 # Similarly for the tszh/tszl pair at 22/16 for zzi
41 %tszimm16_esz 22:2 16:5 !function=tszimm_esz
42 %tszimm16_shr 22:2 16:5 !function=tszimm_shr
43 %tszimm16_shl 22:2 16:5 !function=tszimm_shl
45 # Signed 8-bit immediate, optionally shifted left by 8.
46 %sh8_i8s 5:9 !function=expand_imm_sh8s
47 # Unsigned 8-bit immediate, optionally shifted left by 8.
48 %sh8_i8u 5:9 !function=expand_imm_sh8u
50 # Unsigned load of msz into esz=2, represented as a dtype.
51 %msz_dtype 23:2 !function=msz_dtype
53 # Either a copy of rd (at bit 0), or a different source
54 # as propagated via the MOVPRFX instruction.
55 %reg_movprfx 0:5
57 ###########################################################################
58 # Named attribute sets. These are used to make nice(er) names
59 # when creating helpers common to those for the individual
60 # instruction patterns.
62 &rr_esz rd rn esz
63 &rri rd rn imm
64 &rr_dbm rd rn dbm
65 &rrri rd rn rm imm
66 &rri_esz rd rn imm esz
67 &rrr_esz rd rn rm esz
68 &rpr_esz rd pg rn esz
69 &rpr_s rd pg rn s
70 &rprr_s rd pg rn rm s
71 &rprr_esz rd pg rn rm esz
72 &rprrr_esz rd pg rn rm ra esz
73 &rpri_esz rd pg rn imm esz
74 &ptrue rd esz pat s
75 &incdec_cnt rd pat esz imm d u
76 &incdec2_cnt rd rn pat esz imm d u
77 &incdec_pred rd pg esz d u
78 &incdec2_pred rd rn pg esz d u
79 &rprr_load rd pg rn rm dtype nreg
80 &rpri_load rd pg rn imm dtype nreg
81 &rprr_store rd pg rn rm msz esz nreg
82 &rpri_store rd pg rn imm msz esz nreg
83 &rprr_gather_load rd pg rn rm esz msz u ff xs scale
84 &rpri_gather_load rd pg rn imm esz msz u ff
85 &rprr_scatter_store rd pg rn rm esz msz xs scale
86 &rpri_scatter_store rd pg rn imm esz msz
88 ###########################################################################
89 # Named instruction formats. These are generally used to
90 # reduce the amount of duplication between instruction patterns.
92 # Two operand with unused vector element size
93 @pd_pn_e0 ........ ........ ....... rn:4 . rd:4 &rr_esz esz=0
95 # Two operand
96 @pd_pn ........ esz:2 .. .... ....... rn:4 . rd:4 &rr_esz
97 @rd_rn ........ esz:2 ...... ...... rn:5 rd:5 &rr_esz
99 # Two operand with governing predicate, flags setting
100 @pd_pg_pn_s ........ . s:1 ...... .. pg:4 . rn:4 . rd:4 &rpr_s
102 # Three operand with unused vector element size
103 @rd_rn_rm_e0 ........ ... rm:5 ... ... rn:5 rd:5 &rrr_esz esz=0
105 # Three predicate operand, with governing predicate, flag setting
106 @pd_pg_pn_pm_s ........ . s:1 .. rm:4 .. pg:4 . rn:4 . rd:4 &rprr_s
108 # Three operand, vector element size
109 @rd_rn_rm ........ esz:2 . rm:5 ... ... rn:5 rd:5 &rrr_esz
110 @pd_pn_pm ........ esz:2 .. rm:4 ....... rn:4 . rd:4 &rrr_esz
111 @rdn_rm ........ esz:2 ...... ...... rm:5 rd:5 \
112 &rrr_esz rn=%reg_movprfx
113 @rdn_sh_i8u ........ esz:2 ...... ...... ..... rd:5 \
114 &rri_esz rn=%reg_movprfx imm=%sh8_i8u
115 @rdn_i8u ........ esz:2 ...... ... imm:8 rd:5 \
116 &rri_esz rn=%reg_movprfx
117 @rdn_i8s ........ esz:2 ...... ... imm:s8 rd:5 \
118 &rri_esz rn=%reg_movprfx
120 # Three operand with "memory" size, aka immediate left shift
121 @rd_rn_msz_rm ........ ... rm:5 .... imm:2 rn:5 rd:5 &rrri
123 # Two register operand, with governing predicate, vector element size
124 @rdn_pg_rm ........ esz:2 ... ... ... pg:3 rm:5 rd:5 \
125 &rprr_esz rn=%reg_movprfx
126 @rdm_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 \
127 &rprr_esz rm=%reg_movprfx
128 @rd_pg4_rn_rm ........ esz:2 . rm:5 .. pg:4 rn:5 rd:5 &rprr_esz
129 @pd_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 . rd:4 &rprr_esz
131 # Three register operand, with governing predicate, vector element size
132 @rda_pg_rn_rm ........ esz:2 . rm:5 ... pg:3 rn:5 rd:5 \
133 &rprrr_esz ra=%reg_movprfx
134 @rdn_pg_ra_rm ........ esz:2 . rm:5 ... pg:3 ra:5 rd:5 \
135 &rprrr_esz rn=%reg_movprfx
136 @rdn_pg_rm_ra ........ esz:2 . ra:5 ... pg:3 rm:5 rd:5 \
137 &rprrr_esz rn=%reg_movprfx
139 # One register operand, with governing predicate, vector element size
140 @rd_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 &rpr_esz
141 @rd_pg4_pn ........ esz:2 ... ... .. pg:4 . rn:4 rd:5 &rpr_esz
143 # One register operand, with governing predicate, no vector element size
144 @rd_pg_rn_e0 ........ .. ... ... ... pg:3 rn:5 rd:5 &rpr_esz esz=0
146 # Two register operands with a 6-bit signed immediate.
147 @rd_rn_i6 ........ ... rn:5 ..... imm:s6 rd:5 &rri
149 # Two register operand, one immediate operand, with predicate,
150 # element size encoded as TSZHL. User must fill in imm.
151 @rdn_pg_tszimm ........ .. ... ... ... pg:3 ..... rd:5 \
152 &rpri_esz rn=%reg_movprfx esz=%tszimm_esz
154 # Similarly without predicate.
155 @rd_rn_tszimm ........ .. ... ... ...... rn:5 rd:5 \
156 &rri_esz esz=%tszimm16_esz
158 # Two register operand, one immediate operand, with 4-bit predicate.
159 # User must fill in imm.
160 @rdn_pg4 ........ esz:2 .. pg:4 ... ........ rd:5 \
161 &rpri_esz rn=%reg_movprfx
163 # Two register operand, one encoded bitmask.
164 @rdn_dbm ........ .. .... dbm:13 rd:5 \
165 &rr_dbm rn=%reg_movprfx
167 # Predicate output, vector and immediate input,
168 # controlling predicate, element size.
169 @pd_pg_rn_i7 ........ esz:2 . imm:7 . pg:3 rn:5 . rd:4 &rpri_esz
170 @pd_pg_rn_i5 ........ esz:2 . imm:s5 ... pg:3 rn:5 . rd:4 &rpri_esz
172 # Basic Load/Store with 9-bit immediate offset
173 @pd_rn_i9 ........ ........ ...... rn:5 . rd:4 \
174 &rri imm=%imm9_16_10
175 @rd_rn_i9 ........ ........ ...... rn:5 rd:5 \
176 &rri imm=%imm9_16_10
178 # One register, pattern, and uint4+1.
179 # User must fill in U and D.
180 @incdec_cnt ........ esz:2 .. .... ...... pat:5 rd:5 \
181 &incdec_cnt imm=%imm4_16_p1
182 @incdec2_cnt ........ esz:2 .. .... ...... pat:5 rd:5 \
183 &incdec2_cnt imm=%imm4_16_p1 rn=%reg_movprfx
185 # One register, predicate.
186 # User must fill in U and D.
187 @incdec_pred ........ esz:2 .... .. ..... .. pg:4 rd:5 &incdec_pred
188 @incdec2_pred ........ esz:2 .... .. ..... .. pg:4 rd:5 \
189 &incdec2_pred rn=%reg_movprfx
191 # Loads; user must fill in NREG.
192 @rprr_load_dt ....... dtype:4 rm:5 ... pg:3 rn:5 rd:5 &rprr_load
193 @rpri_load_dt ....... dtype:4 . imm:s4 ... pg:3 rn:5 rd:5 &rpri_load
195 @rprr_load_msz ....... .... rm:5 ... pg:3 rn:5 rd:5 \
196 &rprr_load dtype=%msz_dtype
197 @rpri_load_msz ....... .... . imm:s4 ... pg:3 rn:5 rd:5 \
198 &rpri_load dtype=%msz_dtype
200 # Gather Loads.
201 @rprr_g_load_u ....... .. . . rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \
202 &rprr_gather_load xs=2
203 @rprr_g_load_xs_u ....... .. xs:1 . rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \
204 &rprr_gather_load
205 @rprr_g_load_xs_u_sc ....... .. xs:1 scale:1 rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \
206 &rprr_gather_load
207 @rprr_g_load_xs_sc ....... .. xs:1 scale:1 rm:5 . . ff:1 pg:3 rn:5 rd:5 \
208 &rprr_gather_load
209 @rprr_g_load_u_sc ....... .. . scale:1 rm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \
210 &rprr_gather_load xs=2
211 @rprr_g_load_sc ....... .. . scale:1 rm:5 . . ff:1 pg:3 rn:5 rd:5 \
212 &rprr_gather_load xs=2
213 @rpri_g_load ....... msz:2 .. imm:5 . u:1 ff:1 pg:3 rn:5 rd:5 \
214 &rpri_gather_load
216 # Stores; user must fill in ESZ, MSZ, NREG as needed.
217 @rprr_store ....... .. .. rm:5 ... pg:3 rn:5 rd:5 &rprr_store
218 @rpri_store_msz ....... msz:2 .. . imm:s4 ... pg:3 rn:5 rd:5 &rpri_store
219 @rprr_store_esz_n0 ....... .. esz:2 rm:5 ... pg:3 rn:5 rd:5 \
220 &rprr_store nreg=0
221 @rprr_scatter_store ....... msz:2 .. rm:5 ... pg:3 rn:5 rd:5 \
222 &rprr_scatter_store
223 @rpri_scatter_store ....... msz:2 .. imm:5 ... pg:3 rn:5 rd:5 \
224 &rpri_scatter_store
226 ###########################################################################
227 # Instruction patterns. Grouped according to the SVE encodingindex.xhtml.
229 ### SVE Integer Arithmetic - Binary Predicated Group
231 # SVE bitwise logical vector operations (predicated)
232 ORR_zpzz 00000100 .. 011 000 000 ... ..... ..... @rdn_pg_rm
233 EOR_zpzz 00000100 .. 011 001 000 ... ..... ..... @rdn_pg_rm
234 AND_zpzz 00000100 .. 011 010 000 ... ..... ..... @rdn_pg_rm
235 BIC_zpzz 00000100 .. 011 011 000 ... ..... ..... @rdn_pg_rm
237 # SVE integer add/subtract vectors (predicated)
238 ADD_zpzz 00000100 .. 000 000 000 ... ..... ..... @rdn_pg_rm
239 SUB_zpzz 00000100 .. 000 001 000 ... ..... ..... @rdn_pg_rm
240 SUB_zpzz 00000100 .. 000 011 000 ... ..... ..... @rdm_pg_rn # SUBR
242 # SVE integer min/max/difference (predicated)
243 SMAX_zpzz 00000100 .. 001 000 000 ... ..... ..... @rdn_pg_rm
244 UMAX_zpzz 00000100 .. 001 001 000 ... ..... ..... @rdn_pg_rm
245 SMIN_zpzz 00000100 .. 001 010 000 ... ..... ..... @rdn_pg_rm
246 UMIN_zpzz 00000100 .. 001 011 000 ... ..... ..... @rdn_pg_rm
247 SABD_zpzz 00000100 .. 001 100 000 ... ..... ..... @rdn_pg_rm
248 UABD_zpzz 00000100 .. 001 101 000 ... ..... ..... @rdn_pg_rm
250 # SVE integer multiply/divide (predicated)
251 MUL_zpzz 00000100 .. 010 000 000 ... ..... ..... @rdn_pg_rm
252 SMULH_zpzz 00000100 .. 010 010 000 ... ..... ..... @rdn_pg_rm
253 UMULH_zpzz 00000100 .. 010 011 000 ... ..... ..... @rdn_pg_rm
254 # Note that divide requires size >= 2; below 2 is unallocated.
255 SDIV_zpzz 00000100 .. 010 100 000 ... ..... ..... @rdn_pg_rm
256 UDIV_zpzz 00000100 .. 010 101 000 ... ..... ..... @rdn_pg_rm
257 SDIV_zpzz 00000100 .. 010 110 000 ... ..... ..... @rdm_pg_rn # SDIVR
258 UDIV_zpzz 00000100 .. 010 111 000 ... ..... ..... @rdm_pg_rn # UDIVR
260 ### SVE Integer Reduction Group
262 # SVE bitwise logical reduction (predicated)
263 ORV 00000100 .. 011 000 001 ... ..... ..... @rd_pg_rn
264 EORV 00000100 .. 011 001 001 ... ..... ..... @rd_pg_rn
265 ANDV 00000100 .. 011 010 001 ... ..... ..... @rd_pg_rn
267 # SVE integer add reduction (predicated)
268 # Note that saddv requires size != 3.
269 UADDV 00000100 .. 000 001 001 ... ..... ..... @rd_pg_rn
270 SADDV 00000100 .. 000 000 001 ... ..... ..... @rd_pg_rn
272 # SVE integer min/max reduction (predicated)
273 SMAXV 00000100 .. 001 000 001 ... ..... ..... @rd_pg_rn
274 UMAXV 00000100 .. 001 001 001 ... ..... ..... @rd_pg_rn
275 SMINV 00000100 .. 001 010 001 ... ..... ..... @rd_pg_rn
276 UMINV 00000100 .. 001 011 001 ... ..... ..... @rd_pg_rn
278 ### SVE Shift by Immediate - Predicated Group
280 # SVE bitwise shift by immediate (predicated)
281 ASR_zpzi 00000100 .. 000 000 100 ... .. ... ..... \
282 @rdn_pg_tszimm imm=%tszimm_shr
283 LSR_zpzi 00000100 .. 000 001 100 ... .. ... ..... \
284 @rdn_pg_tszimm imm=%tszimm_shr
285 LSL_zpzi 00000100 .. 000 011 100 ... .. ... ..... \
286 @rdn_pg_tszimm imm=%tszimm_shl
287 ASRD 00000100 .. 000 100 100 ... .. ... ..... \
288 @rdn_pg_tszimm imm=%tszimm_shr
290 # SVE bitwise shift by vector (predicated)
291 ASR_zpzz 00000100 .. 010 000 100 ... ..... ..... @rdn_pg_rm
292 LSR_zpzz 00000100 .. 010 001 100 ... ..... ..... @rdn_pg_rm
293 LSL_zpzz 00000100 .. 010 011 100 ... ..... ..... @rdn_pg_rm
294 ASR_zpzz 00000100 .. 010 100 100 ... ..... ..... @rdm_pg_rn # ASRR
295 LSR_zpzz 00000100 .. 010 101 100 ... ..... ..... @rdm_pg_rn # LSRR
296 LSL_zpzz 00000100 .. 010 111 100 ... ..... ..... @rdm_pg_rn # LSLR
298 # SVE bitwise shift by wide elements (predicated)
299 # Note these require size != 3.
300 ASR_zpzw 00000100 .. 011 000 100 ... ..... ..... @rdn_pg_rm
301 LSR_zpzw 00000100 .. 011 001 100 ... ..... ..... @rdn_pg_rm
302 LSL_zpzw 00000100 .. 011 011 100 ... ..... ..... @rdn_pg_rm
304 ### SVE Integer Arithmetic - Unary Predicated Group
306 # SVE unary bit operations (predicated)
307 # Note esz != 0 for FABS and FNEG.
308 CLS 00000100 .. 011 000 101 ... ..... ..... @rd_pg_rn
309 CLZ 00000100 .. 011 001 101 ... ..... ..... @rd_pg_rn
310 CNT_zpz 00000100 .. 011 010 101 ... ..... ..... @rd_pg_rn
311 CNOT 00000100 .. 011 011 101 ... ..... ..... @rd_pg_rn
312 NOT_zpz 00000100 .. 011 110 101 ... ..... ..... @rd_pg_rn
313 FABS 00000100 .. 011 100 101 ... ..... ..... @rd_pg_rn
314 FNEG 00000100 .. 011 101 101 ... ..... ..... @rd_pg_rn
316 # SVE integer unary operations (predicated)
317 # Note esz > original size for extensions.
318 ABS 00000100 .. 010 110 101 ... ..... ..... @rd_pg_rn
319 NEG 00000100 .. 010 111 101 ... ..... ..... @rd_pg_rn
320 SXTB 00000100 .. 010 000 101 ... ..... ..... @rd_pg_rn
321 UXTB 00000100 .. 010 001 101 ... ..... ..... @rd_pg_rn
322 SXTH 00000100 .. 010 010 101 ... ..... ..... @rd_pg_rn
323 UXTH 00000100 .. 010 011 101 ... ..... ..... @rd_pg_rn
324 SXTW 00000100 .. 010 100 101 ... ..... ..... @rd_pg_rn
325 UXTW 00000100 .. 010 101 101 ... ..... ..... @rd_pg_rn
327 ### SVE Integer Multiply-Add Group
329 # SVE integer multiply-add writing addend (predicated)
330 MLA 00000100 .. 0 ..... 010 ... ..... ..... @rda_pg_rn_rm
331 MLS 00000100 .. 0 ..... 011 ... ..... ..... @rda_pg_rn_rm
333 # SVE integer multiply-add writing multiplicand (predicated)
334 MLA 00000100 .. 0 ..... 110 ... ..... ..... @rdn_pg_ra_rm # MAD
335 MLS 00000100 .. 0 ..... 111 ... ..... ..... @rdn_pg_ra_rm # MSB
337 ### SVE Integer Arithmetic - Unpredicated Group
339 # SVE integer add/subtract vectors (unpredicated)
340 ADD_zzz 00000100 .. 1 ..... 000 000 ..... ..... @rd_rn_rm
341 SUB_zzz 00000100 .. 1 ..... 000 001 ..... ..... @rd_rn_rm
342 SQADD_zzz 00000100 .. 1 ..... 000 100 ..... ..... @rd_rn_rm
343 UQADD_zzz 00000100 .. 1 ..... 000 101 ..... ..... @rd_rn_rm
344 SQSUB_zzz 00000100 .. 1 ..... 000 110 ..... ..... @rd_rn_rm
345 UQSUB_zzz 00000100 .. 1 ..... 000 111 ..... ..... @rd_rn_rm
347 ### SVE Logical - Unpredicated Group
349 # SVE bitwise logical operations (unpredicated)
350 AND_zzz 00000100 00 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
351 ORR_zzz 00000100 01 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
352 EOR_zzz 00000100 10 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
353 BIC_zzz 00000100 11 1 ..... 001 100 ..... ..... @rd_rn_rm_e0
355 ### SVE Index Generation Group
357 # SVE index generation (immediate start, immediate increment)
358 INDEX_ii 00000100 esz:2 1 imm2:s5 010000 imm1:s5 rd:5
360 # SVE index generation (immediate start, register increment)
361 INDEX_ir 00000100 esz:2 1 rm:5 010010 imm:s5 rd:5
363 # SVE index generation (register start, immediate increment)
364 INDEX_ri 00000100 esz:2 1 imm:s5 010001 rn:5 rd:5
366 # SVE index generation (register start, register increment)
367 INDEX_rr 00000100 .. 1 ..... 010011 ..... ..... @rd_rn_rm
369 ### SVE Stack Allocation Group
371 # SVE stack frame adjustment
372 ADDVL 00000100 001 ..... 01010 ...... ..... @rd_rn_i6
373 ADDPL 00000100 011 ..... 01010 ...... ..... @rd_rn_i6
375 # SVE stack frame size
376 RDVL 00000100 101 11111 01010 imm:s6 rd:5
378 ### SVE Bitwise Shift - Unpredicated Group
380 # SVE bitwise shift by immediate (unpredicated)
381 ASR_zzi 00000100 .. 1 ..... 1001 00 ..... ..... \
382 @rd_rn_tszimm imm=%tszimm16_shr
383 LSR_zzi 00000100 .. 1 ..... 1001 01 ..... ..... \
384 @rd_rn_tszimm imm=%tszimm16_shr
385 LSL_zzi 00000100 .. 1 ..... 1001 11 ..... ..... \
386 @rd_rn_tszimm imm=%tszimm16_shl
388 # SVE bitwise shift by wide elements (unpredicated)
389 # Note esz != 3
390 ASR_zzw 00000100 .. 1 ..... 1000 00 ..... ..... @rd_rn_rm
391 LSR_zzw 00000100 .. 1 ..... 1000 01 ..... ..... @rd_rn_rm
392 LSL_zzw 00000100 .. 1 ..... 1000 11 ..... ..... @rd_rn_rm
394 ### SVE Compute Vector Address Group
396 # SVE vector address generation
397 ADR_s32 00000100 00 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
398 ADR_u32 00000100 01 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
399 ADR_p32 00000100 10 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
400 ADR_p64 00000100 11 1 ..... 1010 .. ..... ..... @rd_rn_msz_rm
402 ### SVE Integer Misc - Unpredicated Group
404 # SVE floating-point exponential accelerator
405 # Note esz != 0
406 FEXPA 00000100 .. 1 00000 101110 ..... ..... @rd_rn
408 # SVE floating-point trig select coefficient
409 # Note esz != 0
410 FTSSEL 00000100 .. 1 ..... 101100 ..... ..... @rd_rn_rm
412 ### SVE Element Count Group
414 # SVE element count
415 CNT_r 00000100 .. 10 .... 1110 0 0 ..... ..... @incdec_cnt d=0 u=1
417 # SVE inc/dec register by element count
418 INCDEC_r 00000100 .. 11 .... 1110 0 d:1 ..... ..... @incdec_cnt u=1
420 # SVE saturating inc/dec register by element count
421 SINCDEC_r_32 00000100 .. 10 .... 1111 d:1 u:1 ..... ..... @incdec_cnt
422 SINCDEC_r_64 00000100 .. 11 .... 1111 d:1 u:1 ..... ..... @incdec_cnt
424 # SVE inc/dec vector by element count
425 # Note this requires esz != 0.
426 INCDEC_v 00000100 .. 1 1 .... 1100 0 d:1 ..... ..... @incdec2_cnt u=1
428 # SVE saturating inc/dec vector by element count
429 # Note these require esz != 0.
430 SINCDEC_v 00000100 .. 1 0 .... 1100 d:1 u:1 ..... ..... @incdec2_cnt
432 ### SVE Bitwise Immediate Group
434 # SVE bitwise logical with immediate (unpredicated)
435 ORR_zzi 00000101 00 0000 ............. ..... @rdn_dbm
436 EOR_zzi 00000101 01 0000 ............. ..... @rdn_dbm
437 AND_zzi 00000101 10 0000 ............. ..... @rdn_dbm
439 # SVE broadcast bitmask immediate
440 DUPM 00000101 11 0000 dbm:13 rd:5
442 ### SVE Integer Wide Immediate - Predicated Group
444 # SVE copy floating-point immediate (predicated)
445 FCPY 00000101 .. 01 .... 110 imm:8 ..... @rdn_pg4
447 # SVE copy integer immediate (predicated)
448 CPY_m_i 00000101 .. 01 .... 01 . ........ ..... @rdn_pg4 imm=%sh8_i8s
449 CPY_z_i 00000101 .. 01 .... 00 . ........ ..... @rdn_pg4 imm=%sh8_i8s
451 ### SVE Permute - Extract Group
453 # SVE extract vector (immediate offset)
454 EXT 00000101 001 ..... 000 ... rm:5 rd:5 \
455 &rrri rn=%reg_movprfx imm=%imm8_16_10
457 ### SVE Permute - Unpredicated Group
459 # SVE broadcast general register
460 DUP_s 00000101 .. 1 00000 001110 ..... ..... @rd_rn
462 # SVE broadcast indexed element
463 DUP_x 00000101 .. 1 ..... 001000 rn:5 rd:5 \
464 &rri imm=%imm7_22_16
466 # SVE insert SIMD&FP scalar register
467 INSR_f 00000101 .. 1 10100 001110 ..... ..... @rdn_rm
469 # SVE insert general register
470 INSR_r 00000101 .. 1 00100 001110 ..... ..... @rdn_rm
472 # SVE reverse vector elements
473 REV_v 00000101 .. 1 11000 001110 ..... ..... @rd_rn
475 # SVE vector table lookup
476 TBL 00000101 .. 1 ..... 001100 ..... ..... @rd_rn_rm
478 # SVE unpack vector elements
479 UNPK 00000101 esz:2 1100 u:1 h:1 001110 rn:5 rd:5
481 ### SVE Permute - Predicates Group
483 # SVE permute predicate elements
484 ZIP1_p 00000101 .. 10 .... 010 000 0 .... 0 .... @pd_pn_pm
485 ZIP2_p 00000101 .. 10 .... 010 001 0 .... 0 .... @pd_pn_pm
486 UZP1_p 00000101 .. 10 .... 010 010 0 .... 0 .... @pd_pn_pm
487 UZP2_p 00000101 .. 10 .... 010 011 0 .... 0 .... @pd_pn_pm
488 TRN1_p 00000101 .. 10 .... 010 100 0 .... 0 .... @pd_pn_pm
489 TRN2_p 00000101 .. 10 .... 010 101 0 .... 0 .... @pd_pn_pm
491 # SVE reverse predicate elements
492 REV_p 00000101 .. 11 0100 010 000 0 .... 0 .... @pd_pn
494 # SVE unpack predicate elements
495 PUNPKLO 00000101 00 11 0000 010 000 0 .... 0 .... @pd_pn_e0
496 PUNPKHI 00000101 00 11 0001 010 000 0 .... 0 .... @pd_pn_e0
498 ### SVE Permute - Interleaving Group
500 # SVE permute vector elements
501 ZIP1_z 00000101 .. 1 ..... 011 000 ..... ..... @rd_rn_rm
502 ZIP2_z 00000101 .. 1 ..... 011 001 ..... ..... @rd_rn_rm
503 UZP1_z 00000101 .. 1 ..... 011 010 ..... ..... @rd_rn_rm
504 UZP2_z 00000101 .. 1 ..... 011 011 ..... ..... @rd_rn_rm
505 TRN1_z 00000101 .. 1 ..... 011 100 ..... ..... @rd_rn_rm
506 TRN2_z 00000101 .. 1 ..... 011 101 ..... ..... @rd_rn_rm
508 ### SVE Permute - Predicated Group
510 # SVE compress active elements
511 # Note esz >= 2
512 COMPACT 00000101 .. 100001 100 ... ..... ..... @rd_pg_rn
514 # SVE conditionally broadcast element to vector
515 CLASTA_z 00000101 .. 10100 0 100 ... ..... ..... @rdn_pg_rm
516 CLASTB_z 00000101 .. 10100 1 100 ... ..... ..... @rdn_pg_rm
518 # SVE conditionally copy element to SIMD&FP scalar
519 CLASTA_v 00000101 .. 10101 0 100 ... ..... ..... @rd_pg_rn
520 CLASTB_v 00000101 .. 10101 1 100 ... ..... ..... @rd_pg_rn
522 # SVE conditionally copy element to general register
523 CLASTA_r 00000101 .. 11000 0 101 ... ..... ..... @rd_pg_rn
524 CLASTB_r 00000101 .. 11000 1 101 ... ..... ..... @rd_pg_rn
526 # SVE copy element to SIMD&FP scalar register
527 LASTA_v 00000101 .. 10001 0 100 ... ..... ..... @rd_pg_rn
528 LASTB_v 00000101 .. 10001 1 100 ... ..... ..... @rd_pg_rn
530 # SVE copy element to general register
531 LASTA_r 00000101 .. 10000 0 101 ... ..... ..... @rd_pg_rn
532 LASTB_r 00000101 .. 10000 1 101 ... ..... ..... @rd_pg_rn
534 # SVE copy element from SIMD&FP scalar register
535 CPY_m_v 00000101 .. 100000 100 ... ..... ..... @rd_pg_rn
537 # SVE copy element from general register to vector (predicated)
538 CPY_m_r 00000101 .. 101000 101 ... ..... ..... @rd_pg_rn
540 # SVE reverse within elements
541 # Note esz >= operation size
542 REVB 00000101 .. 1001 00 100 ... ..... ..... @rd_pg_rn
543 REVH 00000101 .. 1001 01 100 ... ..... ..... @rd_pg_rn
544 REVW 00000101 .. 1001 10 100 ... ..... ..... @rd_pg_rn
545 RBIT 00000101 .. 1001 11 100 ... ..... ..... @rd_pg_rn
547 # SVE vector splice (predicated)
548 SPLICE 00000101 .. 101 100 100 ... ..... ..... @rdn_pg_rm
550 ### SVE Select Vectors Group
552 # SVE select vector elements (predicated)
553 SEL_zpzz 00000101 .. 1 ..... 11 .... ..... ..... @rd_pg4_rn_rm
555 ### SVE Integer Compare - Vectors Group
557 # SVE integer compare_vectors
558 CMPHS_ppzz 00100100 .. 0 ..... 000 ... ..... 0 .... @pd_pg_rn_rm
559 CMPHI_ppzz 00100100 .. 0 ..... 000 ... ..... 1 .... @pd_pg_rn_rm
560 CMPGE_ppzz 00100100 .. 0 ..... 100 ... ..... 0 .... @pd_pg_rn_rm
561 CMPGT_ppzz 00100100 .. 0 ..... 100 ... ..... 1 .... @pd_pg_rn_rm
562 CMPEQ_ppzz 00100100 .. 0 ..... 101 ... ..... 0 .... @pd_pg_rn_rm
563 CMPNE_ppzz 00100100 .. 0 ..... 101 ... ..... 1 .... @pd_pg_rn_rm
565 # SVE integer compare with wide elements
566 # Note these require esz != 3.
567 CMPEQ_ppzw 00100100 .. 0 ..... 001 ... ..... 0 .... @pd_pg_rn_rm
568 CMPNE_ppzw 00100100 .. 0 ..... 001 ... ..... 1 .... @pd_pg_rn_rm
569 CMPGE_ppzw 00100100 .. 0 ..... 010 ... ..... 0 .... @pd_pg_rn_rm
570 CMPGT_ppzw 00100100 .. 0 ..... 010 ... ..... 1 .... @pd_pg_rn_rm
571 CMPLT_ppzw 00100100 .. 0 ..... 011 ... ..... 0 .... @pd_pg_rn_rm
572 CMPLE_ppzw 00100100 .. 0 ..... 011 ... ..... 1 .... @pd_pg_rn_rm
573 CMPHS_ppzw 00100100 .. 0 ..... 110 ... ..... 0 .... @pd_pg_rn_rm
574 CMPHI_ppzw 00100100 .. 0 ..... 110 ... ..... 1 .... @pd_pg_rn_rm
575 CMPLO_ppzw 00100100 .. 0 ..... 111 ... ..... 0 .... @pd_pg_rn_rm
576 CMPLS_ppzw 00100100 .. 0 ..... 111 ... ..... 1 .... @pd_pg_rn_rm
578 ### SVE Integer Compare - Unsigned Immediate Group
580 # SVE integer compare with unsigned immediate
581 CMPHS_ppzi 00100100 .. 1 ....... 0 ... ..... 0 .... @pd_pg_rn_i7
582 CMPHI_ppzi 00100100 .. 1 ....... 0 ... ..... 1 .... @pd_pg_rn_i7
583 CMPLO_ppzi 00100100 .. 1 ....... 1 ... ..... 0 .... @pd_pg_rn_i7
584 CMPLS_ppzi 00100100 .. 1 ....... 1 ... ..... 1 .... @pd_pg_rn_i7
586 ### SVE Integer Compare - Signed Immediate Group
588 # SVE integer compare with signed immediate
589 CMPGE_ppzi 00100101 .. 0 ..... 000 ... ..... 0 .... @pd_pg_rn_i5
590 CMPGT_ppzi 00100101 .. 0 ..... 000 ... ..... 1 .... @pd_pg_rn_i5
591 CMPLT_ppzi 00100101 .. 0 ..... 001 ... ..... 0 .... @pd_pg_rn_i5
592 CMPLE_ppzi 00100101 .. 0 ..... 001 ... ..... 1 .... @pd_pg_rn_i5
593 CMPEQ_ppzi 00100101 .. 0 ..... 100 ... ..... 0 .... @pd_pg_rn_i5
594 CMPNE_ppzi 00100101 .. 0 ..... 100 ... ..... 1 .... @pd_pg_rn_i5
596 ### SVE Predicate Logical Operations Group
598 # SVE predicate logical operations
599 AND_pppp 00100101 0. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_pm_s
600 BIC_pppp 00100101 0. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_pm_s
601 EOR_pppp 00100101 0. 00 .... 01 .... 1 .... 0 .... @pd_pg_pn_pm_s
602 SEL_pppp 00100101 0. 00 .... 01 .... 1 .... 1 .... @pd_pg_pn_pm_s
603 ORR_pppp 00100101 1. 00 .... 01 .... 0 .... 0 .... @pd_pg_pn_pm_s
604 ORN_pppp 00100101 1. 00 .... 01 .... 0 .... 1 .... @pd_pg_pn_pm_s
605 NOR_pppp 00100101 1. 00 .... 01 .... 1 .... 0 .... @pd_pg_pn_pm_s
606 NAND_pppp 00100101 1. 00 .... 01 .... 1 .... 1 .... @pd_pg_pn_pm_s
608 ### SVE Predicate Misc Group
610 # SVE predicate test
611 PTEST 00100101 01 010000 11 pg:4 0 rn:4 0 0000
613 # SVE predicate initialize
614 PTRUE 00100101 esz:2 01100 s:1 111000 pat:5 0 rd:4
616 # SVE initialize FFR
617 SETFFR 00100101 0010 1100 1001 0000 0000 0000
619 # SVE zero predicate register
620 PFALSE 00100101 0001 1000 1110 0100 0000 rd:4
622 # SVE predicate read from FFR (predicated)
623 RDFFR_p 00100101 0 s:1 0110001111000 pg:4 0 rd:4
625 # SVE predicate read from FFR (unpredicated)
626 RDFFR 00100101 0001 1001 1111 0000 0000 rd:4
628 # SVE FFR write from predicate (WRFFR)
629 WRFFR 00100101 0010 1000 1001 000 rn:4 00000
631 # SVE predicate first active
632 PFIRST 00100101 01 011 000 11000 00 .... 0 .... @pd_pn_e0
634 # SVE predicate next active
635 PNEXT 00100101 .. 011 001 11000 10 .... 0 .... @pd_pn
637 ### SVE Partition Break Group
639 # SVE propagate break from previous partition
640 BRKPA 00100101 0. 00 .... 11 .... 0 .... 0 .... @pd_pg_pn_pm_s
641 BRKPB 00100101 0. 00 .... 11 .... 0 .... 1 .... @pd_pg_pn_pm_s
643 # SVE partition break condition
644 BRKA_z 00100101 0. 01000001 .... 0 .... 0 .... @pd_pg_pn_s
645 BRKB_z 00100101 1. 01000001 .... 0 .... 0 .... @pd_pg_pn_s
646 BRKA_m 00100101 0. 01000001 .... 0 .... 1 .... @pd_pg_pn_s
647 BRKB_m 00100101 1. 01000001 .... 0 .... 1 .... @pd_pg_pn_s
649 # SVE propagate break to next partition
650 BRKN 00100101 0. 01100001 .... 0 .... 0 .... @pd_pg_pn_s
652 ### SVE Predicate Count Group
654 # SVE predicate count
655 CNTP 00100101 .. 100 000 10 .... 0 .... ..... @rd_pg4_pn
657 # SVE inc/dec register by predicate count
658 INCDECP_r 00100101 .. 10110 d:1 10001 00 .... ..... @incdec_pred u=1
660 # SVE inc/dec vector by predicate count
661 INCDECP_z 00100101 .. 10110 d:1 10000 00 .... ..... @incdec2_pred u=1
663 # SVE saturating inc/dec register by predicate count
664 SINCDECP_r_32 00100101 .. 1010 d:1 u:1 10001 00 .... ..... @incdec_pred
665 SINCDECP_r_64 00100101 .. 1010 d:1 u:1 10001 10 .... ..... @incdec_pred
667 # SVE saturating inc/dec vector by predicate count
668 SINCDECP_z 00100101 .. 1010 d:1 u:1 10000 00 .... ..... @incdec2_pred
670 ### SVE Integer Compare - Scalars Group
672 # SVE conditionally terminate scalars
673 CTERM 00100101 1 sf:1 1 rm:5 001000 rn:5 ne:1 0000
675 # SVE integer compare scalar count and limit
676 WHILE 00100101 esz:2 1 rm:5 000 sf:1 u:1 1 rn:5 eq:1 rd:4
678 ### SVE Integer Wide Immediate - Unpredicated Group
680 # SVE broadcast floating-point immediate (unpredicated)
681 FDUP 00100101 esz:2 111 00 1110 imm:8 rd:5
683 # SVE broadcast integer immediate (unpredicated)
684 DUP_i 00100101 esz:2 111 00 011 . ........ rd:5 imm=%sh8_i8s
686 # SVE integer add/subtract immediate (unpredicated)
687 ADD_zzi 00100101 .. 100 000 11 . ........ ..... @rdn_sh_i8u
688 SUB_zzi 00100101 .. 100 001 11 . ........ ..... @rdn_sh_i8u
689 SUBR_zzi 00100101 .. 100 011 11 . ........ ..... @rdn_sh_i8u
690 SQADD_zzi 00100101 .. 100 100 11 . ........ ..... @rdn_sh_i8u
691 UQADD_zzi 00100101 .. 100 101 11 . ........ ..... @rdn_sh_i8u
692 SQSUB_zzi 00100101 .. 100 110 11 . ........ ..... @rdn_sh_i8u
693 UQSUB_zzi 00100101 .. 100 111 11 . ........ ..... @rdn_sh_i8u
695 # SVE integer min/max immediate (unpredicated)
696 SMAX_zzi 00100101 .. 101 000 110 ........ ..... @rdn_i8s
697 UMAX_zzi 00100101 .. 101 001 110 ........ ..... @rdn_i8u
698 SMIN_zzi 00100101 .. 101 010 110 ........ ..... @rdn_i8s
699 UMIN_zzi 00100101 .. 101 011 110 ........ ..... @rdn_i8u
701 # SVE integer multiply immediate (unpredicated)
702 MUL_zzi 00100101 .. 110 000 110 ........ ..... @rdn_i8s
704 ### SVE FP Accumulating Reduction Group
706 # SVE floating-point serial reduction (predicated)
707 FADDA 01100101 .. 011 000 001 ... ..... ..... @rdn_pg_rm
709 ### SVE Floating Point Arithmetic - Unpredicated Group
711 # SVE floating-point arithmetic (unpredicated)
712 FADD_zzz 01100101 .. 0 ..... 000 000 ..... ..... @rd_rn_rm
713 FSUB_zzz 01100101 .. 0 ..... 000 001 ..... ..... @rd_rn_rm
714 FMUL_zzz 01100101 .. 0 ..... 000 010 ..... ..... @rd_rn_rm
715 FTSMUL 01100101 .. 0 ..... 000 011 ..... ..... @rd_rn_rm
716 FRECPS 01100101 .. 0 ..... 000 110 ..... ..... @rd_rn_rm
717 FRSQRTS 01100101 .. 0 ..... 000 111 ..... ..... @rd_rn_rm
719 ### SVE FP Arithmetic Predicated Group
721 # SVE floating-point arithmetic (predicated)
722 FADD_zpzz 01100101 .. 00 0000 100 ... ..... ..... @rdn_pg_rm
723 FSUB_zpzz 01100101 .. 00 0001 100 ... ..... ..... @rdn_pg_rm
724 FMUL_zpzz 01100101 .. 00 0010 100 ... ..... ..... @rdn_pg_rm
725 FSUB_zpzz 01100101 .. 00 0011 100 ... ..... ..... @rdm_pg_rn # FSUBR
726 FMAXNM_zpzz 01100101 .. 00 0100 100 ... ..... ..... @rdn_pg_rm
727 FMINNM_zpzz 01100101 .. 00 0101 100 ... ..... ..... @rdn_pg_rm
728 FMAX_zpzz 01100101 .. 00 0110 100 ... ..... ..... @rdn_pg_rm
729 FMIN_zpzz 01100101 .. 00 0111 100 ... ..... ..... @rdn_pg_rm
730 FABD 01100101 .. 00 1000 100 ... ..... ..... @rdn_pg_rm
731 FSCALE 01100101 .. 00 1001 100 ... ..... ..... @rdn_pg_rm
732 FMULX 01100101 .. 00 1010 100 ... ..... ..... @rdn_pg_rm
733 FDIV 01100101 .. 00 1100 100 ... ..... ..... @rdm_pg_rn # FDIVR
734 FDIV 01100101 .. 00 1101 100 ... ..... ..... @rdn_pg_rm
736 ### SVE FP Multiply-Add Group
738 # SVE floating-point multiply-accumulate writing addend
739 FMLA_zpzzz 01100101 .. 1 ..... 000 ... ..... ..... @rda_pg_rn_rm
740 FMLS_zpzzz 01100101 .. 1 ..... 001 ... ..... ..... @rda_pg_rn_rm
741 FNMLA_zpzzz 01100101 .. 1 ..... 010 ... ..... ..... @rda_pg_rn_rm
742 FNMLS_zpzzz 01100101 .. 1 ..... 011 ... ..... ..... @rda_pg_rn_rm
744 # SVE floating-point multiply-accumulate writing multiplicand
745 # Alter the operand extraction order and reuse the helpers from above.
746 # FMAD, FMSB, FNMAD, FNMS
747 FMLA_zpzzz 01100101 .. 1 ..... 100 ... ..... ..... @rdn_pg_rm_ra
748 FMLS_zpzzz 01100101 .. 1 ..... 101 ... ..... ..... @rdn_pg_rm_ra
749 FNMLA_zpzzz 01100101 .. 1 ..... 110 ... ..... ..... @rdn_pg_rm_ra
750 FNMLS_zpzzz 01100101 .. 1 ..... 111 ... ..... ..... @rdn_pg_rm_ra
752 ### SVE FP Unary Operations Predicated Group
754 # SVE integer convert to floating-point
755 SCVTF_hh 01100101 01 010 01 0 101 ... ..... ..... @rd_pg_rn_e0
756 SCVTF_sh 01100101 01 010 10 0 101 ... ..... ..... @rd_pg_rn_e0
757 SCVTF_dh 01100101 01 010 11 0 101 ... ..... ..... @rd_pg_rn_e0
758 SCVTF_ss 01100101 10 010 10 0 101 ... ..... ..... @rd_pg_rn_e0
759 SCVTF_sd 01100101 11 010 00 0 101 ... ..... ..... @rd_pg_rn_e0
760 SCVTF_ds 01100101 11 010 10 0 101 ... ..... ..... @rd_pg_rn_e0
761 SCVTF_dd 01100101 11 010 11 0 101 ... ..... ..... @rd_pg_rn_e0
763 UCVTF_hh 01100101 01 010 01 1 101 ... ..... ..... @rd_pg_rn_e0
764 UCVTF_sh 01100101 01 010 10 1 101 ... ..... ..... @rd_pg_rn_e0
765 UCVTF_dh 01100101 01 010 11 1 101 ... ..... ..... @rd_pg_rn_e0
766 UCVTF_ss 01100101 10 010 10 1 101 ... ..... ..... @rd_pg_rn_e0
767 UCVTF_sd 01100101 11 010 00 1 101 ... ..... ..... @rd_pg_rn_e0
768 UCVTF_ds 01100101 11 010 10 1 101 ... ..... ..... @rd_pg_rn_e0
769 UCVTF_dd 01100101 11 010 11 1 101 ... ..... ..... @rd_pg_rn_e0
771 ### SVE Memory - 32-bit Gather and Unsized Contiguous Group
773 # SVE load predicate register
774 LDR_pri 10000101 10 ...... 000 ... ..... 0 .... @pd_rn_i9
776 # SVE load vector register
777 LDR_zri 10000101 10 ...... 010 ... ..... ..... @rd_rn_i9
779 # SVE load and broadcast element
780 LD1R_zpri 1000010 .. 1 imm:6 1.. pg:3 rn:5 rd:5 \
781 &rpri_load dtype=%dtype_23_13 nreg=0
783 # SVE 32-bit gather load (scalar plus 32-bit unscaled offsets)
784 # SVE 32-bit gather load (scalar plus 32-bit scaled offsets)
785 LD1_zprz 1000010 00 .0 ..... 0.. ... ..... ..... \
786 @rprr_g_load_xs_u esz=2 msz=0 scale=0
787 LD1_zprz 1000010 01 .. ..... 0.. ... ..... ..... \
788 @rprr_g_load_xs_u_sc esz=2 msz=1
789 LD1_zprz 1000010 10 .. ..... 01. ... ..... ..... \
790 @rprr_g_load_xs_sc esz=2 msz=2 u=1
792 # SVE 32-bit gather load (vector plus immediate)
793 LD1_zpiz 1000010 .. 01 ..... 1.. ... ..... ..... \
794 @rpri_g_load esz=2
796 ### SVE Memory Contiguous Load Group
798 # SVE contiguous load (scalar plus scalar)
799 LD_zprr 1010010 .... ..... 010 ... ..... ..... @rprr_load_dt nreg=0
801 # SVE contiguous first-fault load (scalar plus scalar)
802 LDFF1_zprr 1010010 .... ..... 011 ... ..... ..... @rprr_load_dt nreg=0
804 # SVE contiguous load (scalar plus immediate)
805 LD_zpri 1010010 .... 0.... 101 ... ..... ..... @rpri_load_dt nreg=0
807 # SVE contiguous non-fault load (scalar plus immediate)
808 LDNF1_zpri 1010010 .... 1.... 101 ... ..... ..... @rpri_load_dt nreg=0
810 # SVE contiguous non-temporal load (scalar plus scalar)
811 # LDNT1B, LDNT1H, LDNT1W, LDNT1D
812 # SVE load multiple structures (scalar plus scalar)
813 # LD2B, LD2H, LD2W, LD2D; etc.
814 LD_zprr 1010010 .. nreg:2 ..... 110 ... ..... ..... @rprr_load_msz
816 # SVE contiguous non-temporal load (scalar plus immediate)
817 # LDNT1B, LDNT1H, LDNT1W, LDNT1D
818 # SVE load multiple structures (scalar plus immediate)
819 # LD2B, LD2H, LD2W, LD2D; etc.
820 LD_zpri 1010010 .. nreg:2 0.... 111 ... ..... ..... @rpri_load_msz
822 # SVE load and broadcast quadword (scalar plus scalar)
823 LD1RQ_zprr 1010010 .. 00 ..... 000 ... ..... ..... \
824 @rprr_load_msz nreg=0
826 # SVE load and broadcast quadword (scalar plus immediate)
827 # LD1RQB, LD1RQH, LD1RQS, LD1RQD
828 LD1RQ_zpri 1010010 .. 00 0.... 001 ... ..... ..... \
829 @rpri_load_msz nreg=0
831 # SVE 32-bit gather prefetch (scalar plus 32-bit scaled offsets)
832 PRF 1000010 00 -1 ----- 0-- --- ----- 0 ----
834 # SVE 32-bit gather prefetch (vector plus immediate)
835 PRF 1000010 -- 00 ----- 111 --- ----- 0 ----
837 # SVE contiguous prefetch (scalar plus immediate)
838 PRF 1000010 11 1- ----- 0-- --- ----- 0 ----
840 # SVE contiguous prefetch (scalar plus scalar)
841 PRF_rr 1000010 -- 00 rm:5 110 --- ----- 0 ----
843 ### SVE Memory 64-bit Gather Group
845 # SVE 64-bit gather load (scalar plus 32-bit unpacked unscaled offsets)
846 # SVE 64-bit gather load (scalar plus 32-bit unpacked scaled offsets)
847 LD1_zprz 1100010 00 .0 ..... 0.. ... ..... ..... \
848 @rprr_g_load_xs_u esz=3 msz=0 scale=0
849 LD1_zprz 1100010 01 .. ..... 0.. ... ..... ..... \
850 @rprr_g_load_xs_u_sc esz=3 msz=1
851 LD1_zprz 1100010 10 .. ..... 0.. ... ..... ..... \
852 @rprr_g_load_xs_u_sc esz=3 msz=2
853 LD1_zprz 1100010 11 .. ..... 01. ... ..... ..... \
854 @rprr_g_load_xs_sc esz=3 msz=3 u=1
856 # SVE 64-bit gather load (scalar plus 64-bit unscaled offsets)
857 # SVE 64-bit gather load (scalar plus 64-bit scaled offsets)
858 LD1_zprz 1100010 00 10 ..... 1.. ... ..... ..... \
859 @rprr_g_load_u esz=3 msz=0 scale=0
860 LD1_zprz 1100010 01 1. ..... 1.. ... ..... ..... \
861 @rprr_g_load_u_sc esz=3 msz=1
862 LD1_zprz 1100010 10 1. ..... 1.. ... ..... ..... \
863 @rprr_g_load_u_sc esz=3 msz=2
864 LD1_zprz 1100010 11 1. ..... 11. ... ..... ..... \
865 @rprr_g_load_sc esz=3 msz=3 u=1
867 # SVE 64-bit gather load (vector plus immediate)
868 LD1_zpiz 1100010 .. 01 ..... 1.. ... ..... ..... \
869 @rpri_g_load esz=3
871 # SVE 64-bit gather prefetch (scalar plus 64-bit scaled offsets)
872 PRF 1100010 00 11 ----- 1-- --- ----- 0 ----
874 # SVE 64-bit gather prefetch (scalar plus unpacked 32-bit scaled offsets)
875 PRF 1100010 00 -1 ----- 0-- --- ----- 0 ----
877 # SVE 64-bit gather prefetch (vector plus immediate)
878 PRF 1100010 -- 00 ----- 111 --- ----- 0 ----
880 ### SVE Memory Store Group
882 # SVE store predicate register
883 STR_pri 1110010 11 0. ..... 000 ... ..... 0 .... @pd_rn_i9
885 # SVE store vector register
886 STR_zri 1110010 11 0. ..... 010 ... ..... ..... @rd_rn_i9
888 # SVE contiguous store (scalar plus immediate)
889 # ST1B, ST1H, ST1W, ST1D; require msz <= esz
890 ST_zpri 1110010 .. esz:2 0.... 111 ... ..... ..... \
891 @rpri_store_msz nreg=0
893 # SVE contiguous store (scalar plus scalar)
894 # ST1B, ST1H, ST1W, ST1D; require msz <= esz
895 # Enumerate msz lest we conflict with STR_zri.
896 ST_zprr 1110010 00 .. ..... 010 ... ..... ..... \
897 @rprr_store_esz_n0 msz=0
898 ST_zprr 1110010 01 .. ..... 010 ... ..... ..... \
899 @rprr_store_esz_n0 msz=1
900 ST_zprr 1110010 10 .. ..... 010 ... ..... ..... \
901 @rprr_store_esz_n0 msz=2
902 ST_zprr 1110010 11 11 ..... 010 ... ..... ..... \
903 @rprr_store msz=3 esz=3 nreg=0
905 # SVE contiguous non-temporal store (scalar plus immediate) (nreg == 0)
906 # SVE store multiple structures (scalar plus immediate) (nreg != 0)
907 ST_zpri 1110010 .. nreg:2 1.... 111 ... ..... ..... \
908 @rpri_store_msz esz=%size_23
910 # SVE contiguous non-temporal store (scalar plus scalar) (nreg == 0)
911 # SVE store multiple structures (scalar plus scalar) (nreg != 0)
912 ST_zprr 1110010 msz:2 nreg:2 ..... 011 ... ..... ..... \
913 @rprr_store esz=%size_23
915 # SVE 32-bit scatter store (scalar plus 32-bit scaled offsets)
916 # Require msz > 0 && msz <= esz.
917 ST1_zprz 1110010 .. 11 ..... 100 ... ..... ..... \
918 @rprr_scatter_store xs=0 esz=2 scale=1
919 ST1_zprz 1110010 .. 11 ..... 110 ... ..... ..... \
920 @rprr_scatter_store xs=1 esz=2 scale=1
922 # SVE 32-bit scatter store (scalar plus 32-bit unscaled offsets)
923 # Require msz <= esz.
924 ST1_zprz 1110010 .. 10 ..... 100 ... ..... ..... \
925 @rprr_scatter_store xs=0 esz=2 scale=0
926 ST1_zprz 1110010 .. 10 ..... 110 ... ..... ..... \
927 @rprr_scatter_store xs=1 esz=2 scale=0
929 # SVE 64-bit scatter store (scalar plus 64-bit scaled offset)
930 # Require msz > 0
931 ST1_zprz 1110010 .. 01 ..... 101 ... ..... ..... \
932 @rprr_scatter_store xs=2 esz=3 scale=1
934 # SVE 64-bit scatter store (scalar plus 64-bit unscaled offset)
935 ST1_zprz 1110010 .. 00 ..... 101 ... ..... ..... \
936 @rprr_scatter_store xs=2 esz=3 scale=0
938 # SVE 64-bit scatter store (vector plus immediate)
939 ST1_zpiz 1110010 .. 10 ..... 101 ... ..... ..... \
940 @rpri_scatter_store esz=3
942 # SVE 32-bit scatter store (vector plus immediate)
943 ST1_zpiz 1110010 .. 11 ..... 101 ... ..... ..... \
944 @rpri_scatter_store esz=2
946 # SVE 64-bit scatter store (scalar plus unpacked 32-bit scaled offset)
947 # Require msz > 0
948 ST1_zprz 1110010 .. 01 ..... 100 ... ..... ..... \
949 @rprr_scatter_store xs=0 esz=3 scale=1
950 ST1_zprz 1110010 .. 01 ..... 110 ... ..... ..... \
951 @rprr_scatter_store xs=1 esz=3 scale=1
953 # SVE 64-bit scatter store (scalar plus unpacked 32-bit unscaled offset)
954 ST1_zprz 1110010 .. 00 ..... 100 ... ..... ..... \
955 @rprr_scatter_store xs=0 esz=3 scale=0
956 ST1_zprz 1110010 .. 00 ..... 110 ... ..... ..... \
957 @rprr_scatter_store xs=1 esz=3 scale=0