4 * Copyright (c) 2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
32 # define PCI_DPRINTF(format, ...) printf(format, __VA_ARGS__)
34 # define PCI_DPRINTF(format, ...) do { } while (0)
41 pci_set_irq_fn set_irq
;
42 pci_map_irq_fn map_irq
;
43 pci_hotplug_fn hotplug
;
44 uint32_t config_reg
; /* XXX: suppress */
46 PCIDevice
*devices
[256];
47 PCIDevice
*parent_dev
;
49 /* The bus IRQ state is the logical OR of the connected devices.
50 Keep a count of the number of devices with raised IRQs. */
55 static void pcibus_dev_print(Monitor
*mon
, DeviceState
*dev
, int indent
);
57 static struct BusInfo pci_bus_info
= {
59 .size
= sizeof(PCIBus
),
60 .print_dev
= pcibus_dev_print
,
61 .props
= (Property
[]) {
62 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice
, devfn
, -1),
63 DEFINE_PROP_END_OF_LIST()
67 static void pci_update_mappings(PCIDevice
*d
);
68 static void pci_set_irq(void *opaque
, int irq_num
, int level
);
70 target_phys_addr_t pci_mem_base
;
71 static uint16_t pci_default_sub_vendor_id
= PCI_SUBVENDOR_ID_REDHAT_QUMRANET
;
72 static uint16_t pci_default_sub_device_id
= PCI_SUBDEVICE_ID_QEMU
;
73 static PCIBus
*first_bus
;
75 static const VMStateDescription vmstate_pcibus
= {
78 .minimum_version_id
= 1,
79 .minimum_version_id_old
= 1,
80 .fields
= (VMStateField
[]) {
81 VMSTATE_INT32_EQUAL(nirq
, PCIBus
),
82 VMSTATE_INT32_VARRAY(irq_count
, PCIBus
, nirq
),
87 static inline int pci_bar(int reg
)
89 return reg
== PCI_ROM_SLOT
? PCI_ROM_ADDRESS
: PCI_BASE_ADDRESS_0
+ reg
* 4;
92 static void pci_device_reset(PCIDevice
*dev
)
96 memset(dev
->irq_state
, 0, sizeof dev
->irq_state
);
97 dev
->config
[PCI_COMMAND
] &= ~(PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
|
99 dev
->config
[PCI_CACHE_LINE_SIZE
] = 0x0;
100 dev
->config
[PCI_INTERRUPT_LINE
] = 0x0;
101 for (r
= 0; r
< PCI_NUM_REGIONS
; ++r
) {
102 if (!dev
->io_regions
[r
].size
) {
105 pci_set_long(dev
->config
+ pci_bar(r
), dev
->io_regions
[r
].type
);
107 pci_update_mappings(dev
);
110 static void pci_bus_reset(void *opaque
)
112 PCIBus
*bus
= opaque
;
115 for (i
= 0; i
< bus
->nirq
; i
++) {
116 bus
->irq_count
[i
] = 0;
118 for (i
= 0; i
< ARRAY_SIZE(bus
->devices
); ++i
) {
119 if (bus
->devices
[i
]) {
120 pci_device_reset(bus
->devices
[i
]);
125 void pci_bus_new_inplace(PCIBus
*bus
, DeviceState
*parent
,
126 const char *name
, int devfn_min
)
130 qbus_create_inplace(&bus
->qbus
, &pci_bus_info
, parent
, name
);
131 bus
->devfn_min
= devfn_min
;
132 bus
->next
= first_bus
;
134 vmstate_register(nbus
++, &vmstate_pcibus
, bus
);
135 qemu_register_reset(pci_bus_reset
, bus
);
138 PCIBus
*pci_bus_new(DeviceState
*parent
, const char *name
, int devfn_min
)
142 bus
= qemu_mallocz(sizeof(*bus
));
143 bus
->qbus
.qdev_allocated
= 1;
144 pci_bus_new_inplace(bus
, parent
, name
, devfn_min
);
148 void pci_bus_irqs(PCIBus
*bus
, pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
149 void *irq_opaque
, int nirq
)
151 bus
->set_irq
= set_irq
;
152 bus
->map_irq
= map_irq
;
153 bus
->irq_opaque
= irq_opaque
;
155 bus
->irq_count
= qemu_mallocz(nirq
* sizeof(bus
->irq_count
[0]));
158 void pci_bus_hotplug(PCIBus
*bus
, pci_hotplug_fn hotplug
)
160 bus
->qbus
.allow_hotplug
= 1;
161 bus
->hotplug
= hotplug
;
164 PCIBus
*pci_register_bus(DeviceState
*parent
, const char *name
,
165 pci_set_irq_fn set_irq
, pci_map_irq_fn map_irq
,
166 void *irq_opaque
, int devfn_min
, int nirq
)
170 bus
= pci_bus_new(parent
, name
, devfn_min
);
171 pci_bus_irqs(bus
, set_irq
, map_irq
, irq_opaque
, nirq
);
175 static void pci_register_secondary_bus(PCIBus
*bus
,
177 pci_map_irq_fn map_irq
,
180 qbus_create_inplace(&bus
->qbus
, &pci_bus_info
, &dev
->qdev
, name
);
181 bus
->map_irq
= map_irq
;
182 bus
->parent_dev
= dev
;
183 bus
->next
= dev
->bus
->next
;
184 dev
->bus
->next
= bus
;
187 int pci_bus_num(PCIBus
*s
)
192 static int get_pci_config_device(QEMUFile
*f
, void *pv
, size_t size
)
194 PCIDevice
*s
= container_of(pv
, PCIDevice
, config
);
195 uint8_t config
[PCI_CONFIG_SPACE_SIZE
];
198 assert(size
== sizeof config
);
199 qemu_get_buffer(f
, config
, sizeof config
);
200 for (i
= 0; i
< sizeof config
; ++i
)
201 if ((config
[i
] ^ s
->config
[i
]) & s
->cmask
[i
] & ~s
->wmask
[i
])
203 memcpy(s
->config
, config
, sizeof config
);
205 pci_update_mappings(s
);
210 /* just put buffer */
211 static void put_pci_config_device(QEMUFile
*f
, void *pv
, size_t size
)
213 const uint8_t *v
= pv
;
214 qemu_put_buffer(f
, v
, size
);
217 static VMStateInfo vmstate_info_pci_config
= {
218 .name
= "pci config",
219 .get
= get_pci_config_device
,
220 .put
= put_pci_config_device
,
223 const VMStateDescription vmstate_pci_device
= {
226 .minimum_version_id
= 1,
227 .minimum_version_id_old
= 1,
228 .fields
= (VMStateField
[]) {
229 VMSTATE_INT32_LE(version_id
, PCIDevice
),
230 VMSTATE_SINGLE(config
, PCIDevice
, 0, vmstate_info_pci_config
,
231 typeof_field(PCIDevice
,config
)),
232 VMSTATE_INT32_ARRAY_V(irq_state
, PCIDevice
, 4, 2),
233 VMSTATE_END_OF_LIST()
237 void pci_device_save(PCIDevice
*s
, QEMUFile
*f
)
239 vmstate_save_state(f
, &vmstate_pci_device
, s
);
242 int pci_device_load(PCIDevice
*s
, QEMUFile
*f
)
244 return vmstate_load_state(f
, &vmstate_pci_device
, s
, s
->version_id
);
247 static int pci_set_default_subsystem_id(PCIDevice
*pci_dev
)
251 id
= (void*)(&pci_dev
->config
[PCI_SUBVENDOR_ID
]);
252 id
[0] = cpu_to_le16(pci_default_sub_vendor_id
);
253 id
[1] = cpu_to_le16(pci_default_sub_device_id
);
258 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error
260 static int pci_parse_devaddr(const char *addr
, int *domp
, int *busp
, unsigned *slotp
)
265 unsigned long dom
= 0, bus
= 0;
269 val
= strtoul(p
, &e
, 16);
275 val
= strtoul(p
, &e
, 16);
282 val
= strtoul(p
, &e
, 16);
288 if (dom
> 0xffff || bus
> 0xff || val
> 0x1f)
296 /* Note: QEMU doesn't implement domains other than 0 */
297 if (dom
!= 0 || pci_find_bus(bus
) == NULL
)
306 int pci_read_devaddr(Monitor
*mon
, const char *addr
, int *domp
, int *busp
,
309 /* strip legacy tag */
310 if (!strncmp(addr
, "pci_addr=", 9)) {
313 if (pci_parse_devaddr(addr
, domp
, busp
, slotp
)) {
314 monitor_printf(mon
, "Invalid pci address\n");
320 PCIBus
*pci_get_bus_devfn(int *devfnp
, const char *devaddr
)
327 return pci_find_bus(0);
330 if (pci_parse_devaddr(devaddr
, &dom
, &bus
, &slot
) < 0) {
335 return pci_find_bus(bus
);
338 static void pci_init_cmask(PCIDevice
*dev
)
340 pci_set_word(dev
->cmask
+ PCI_VENDOR_ID
, 0xffff);
341 pci_set_word(dev
->cmask
+ PCI_DEVICE_ID
, 0xffff);
342 dev
->cmask
[PCI_STATUS
] = PCI_STATUS_CAP_LIST
;
343 dev
->cmask
[PCI_REVISION_ID
] = 0xff;
344 dev
->cmask
[PCI_CLASS_PROG
] = 0xff;
345 pci_set_word(dev
->cmask
+ PCI_CLASS_DEVICE
, 0xffff);
346 dev
->cmask
[PCI_HEADER_TYPE
] = 0xff;
347 dev
->cmask
[PCI_CAPABILITY_LIST
] = 0xff;
350 static void pci_init_wmask(PCIDevice
*dev
)
353 dev
->wmask
[PCI_CACHE_LINE_SIZE
] = 0xff;
354 dev
->wmask
[PCI_INTERRUPT_LINE
] = 0xff;
355 dev
->wmask
[PCI_COMMAND
] = PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
356 | PCI_COMMAND_MASTER
;
357 for (i
= PCI_CONFIG_HEADER_SIZE
; i
< PCI_CONFIG_SPACE_SIZE
; ++i
)
358 dev
->wmask
[i
] = 0xff;
361 /* -1 for devfn means auto assign */
362 static PCIDevice
*do_pci_register_device(PCIDevice
*pci_dev
, PCIBus
*bus
,
363 const char *name
, int devfn
,
364 PCIConfigReadFunc
*config_read
,
365 PCIConfigWriteFunc
*config_write
)
368 for(devfn
= bus
->devfn_min
; devfn
< 256; devfn
+= 8) {
369 if (!bus
->devices
[devfn
])
374 } else if (bus
->devices
[devfn
]) {
378 pci_dev
->devfn
= devfn
;
379 pstrcpy(pci_dev
->name
, sizeof(pci_dev
->name
), name
);
380 memset(pci_dev
->irq_state
, 0, sizeof(pci_dev
->irq_state
));
381 pci_set_default_subsystem_id(pci_dev
);
382 pci_init_cmask(pci_dev
);
383 pci_init_wmask(pci_dev
);
386 config_read
= pci_default_read_config
;
388 config_write
= pci_default_write_config
;
389 pci_dev
->config_read
= config_read
;
390 pci_dev
->config_write
= config_write
;
391 bus
->devices
[devfn
] = pci_dev
;
392 pci_dev
->irq
= qemu_allocate_irqs(pci_set_irq
, pci_dev
, 4);
393 pci_dev
->version_id
= 2; /* Current pci device vmstate version */
397 PCIDevice
*pci_register_device(PCIBus
*bus
, const char *name
,
398 int instance_size
, int devfn
,
399 PCIConfigReadFunc
*config_read
,
400 PCIConfigWriteFunc
*config_write
)
404 pci_dev
= qemu_mallocz(instance_size
);
405 pci_dev
= do_pci_register_device(pci_dev
, bus
, name
, devfn
,
406 config_read
, config_write
);
409 static target_phys_addr_t
pci_to_cpu_addr(target_phys_addr_t addr
)
411 return addr
+ pci_mem_base
;
414 static void pci_unregister_io_regions(PCIDevice
*pci_dev
)
419 for(i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
420 r
= &pci_dev
->io_regions
[i
];
421 if (!r
->size
|| r
->addr
== -1)
423 if (r
->type
== PCI_ADDRESS_SPACE_IO
) {
424 isa_unassign_ioport(r
->addr
, r
->size
);
426 cpu_register_physical_memory(pci_to_cpu_addr(r
->addr
),
433 static int pci_unregister_device(DeviceState
*dev
)
435 PCIDevice
*pci_dev
= DO_UPCAST(PCIDevice
, qdev
, dev
);
436 PCIDeviceInfo
*info
= DO_UPCAST(PCIDeviceInfo
, qdev
, dev
->info
);
440 ret
= info
->exit(pci_dev
);
444 pci_unregister_io_regions(pci_dev
);
446 qemu_free_irqs(pci_dev
->irq
);
447 pci_dev
->bus
->devices
[pci_dev
->devfn
] = NULL
;
451 void pci_register_bar(PCIDevice
*pci_dev
, int region_num
,
452 uint32_t size
, int type
,
453 PCIMapIORegionFunc
*map_func
)
459 if ((unsigned int)region_num
>= PCI_NUM_REGIONS
)
462 if (size
& (size
-1)) {
463 fprintf(stderr
, "ERROR: PCI region size must be pow2 "
464 "type=0x%x, size=0x%x\n", type
, size
);
468 r
= &pci_dev
->io_regions
[region_num
];
472 r
->map_func
= map_func
;
475 addr
= pci_bar(region_num
);
476 if (region_num
== PCI_ROM_SLOT
) {
477 /* ROM enable bit is writeable */
478 wmask
|= PCI_ROM_ADDRESS_ENABLE
;
480 *(uint32_t *)(pci_dev
->config
+ addr
) = cpu_to_le32(type
);
481 *(uint32_t *)(pci_dev
->wmask
+ addr
) = cpu_to_le32(wmask
);
482 *(uint32_t *)(pci_dev
->cmask
+ addr
) = 0xffffffff;
485 static void pci_update_mappings(PCIDevice
*d
)
489 uint32_t last_addr
, new_addr
;
491 cmd
= le16_to_cpu(*(uint16_t *)(d
->config
+ PCI_COMMAND
));
492 for(i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
493 r
= &d
->io_regions
[i
];
495 if (r
->type
& PCI_ADDRESS_SPACE_IO
) {
496 if (cmd
& PCI_COMMAND_IO
) {
497 new_addr
= pci_get_long(d
->config
+ pci_bar(i
));
498 new_addr
= new_addr
& ~(r
->size
- 1);
499 last_addr
= new_addr
+ r
->size
- 1;
500 /* NOTE: we have only 64K ioports on PC */
501 if (last_addr
<= new_addr
|| new_addr
== 0 ||
502 last_addr
>= 0x10000) {
509 if (cmd
& PCI_COMMAND_MEMORY
) {
510 new_addr
= pci_get_long(d
->config
+ pci_bar(i
));
511 /* the ROM slot has a specific enable bit */
512 if (i
== PCI_ROM_SLOT
&& !(new_addr
& PCI_ROM_ADDRESS_ENABLE
))
514 new_addr
= new_addr
& ~(r
->size
- 1);
515 last_addr
= new_addr
+ r
->size
- 1;
516 /* NOTE: we do not support wrapping */
517 /* XXX: as we cannot support really dynamic
518 mappings, we handle specific values as invalid
520 if (last_addr
<= new_addr
|| new_addr
== 0 ||
529 /* now do the real mapping */
530 if (new_addr
!= r
->addr
) {
532 if (r
->type
& PCI_ADDRESS_SPACE_IO
) {
534 /* NOTE: specific hack for IDE in PC case:
535 only one byte must be mapped. */
536 class = pci_get_word(d
->config
+ PCI_CLASS_DEVICE
);
537 if (class == 0x0101 && r
->size
== 4) {
538 isa_unassign_ioport(r
->addr
+ 2, 1);
540 isa_unassign_ioport(r
->addr
, r
->size
);
543 cpu_register_physical_memory(pci_to_cpu_addr(r
->addr
),
546 qemu_unregister_coalesced_mmio(r
->addr
, r
->size
);
551 r
->map_func(d
, i
, r
->addr
, r
->size
, r
->type
);
558 uint32_t pci_default_read_config(PCIDevice
*d
,
559 uint32_t address
, int len
)
566 if (address
<= 0xfc) {
567 val
= le32_to_cpu(*(uint32_t *)(d
->config
+ address
));
572 if (address
<= 0xfe) {
573 val
= le16_to_cpu(*(uint16_t *)(d
->config
+ address
));
578 val
= d
->config
[address
];
584 void pci_default_write_config(PCIDevice
*d
, uint32_t addr
, uint32_t val
, int l
)
586 uint8_t orig
[PCI_CONFIG_SPACE_SIZE
];
589 /* not efficient, but simple */
590 memcpy(orig
, d
->config
, PCI_CONFIG_SPACE_SIZE
);
591 for(i
= 0; i
< l
&& addr
< PCI_CONFIG_SPACE_SIZE
; val
>>= 8, ++i
, ++addr
) {
592 uint8_t wmask
= d
->wmask
[addr
];
593 d
->config
[addr
] = (d
->config
[addr
] & ~wmask
) | (val
& wmask
);
595 if (memcmp(orig
+ PCI_BASE_ADDRESS_0
, d
->config
+ PCI_BASE_ADDRESS_0
, 24)
596 || ((orig
[PCI_COMMAND
] ^ d
->config
[PCI_COMMAND
])
597 & (PCI_COMMAND_MEMORY
| PCI_COMMAND_IO
)))
598 pci_update_mappings(d
);
601 void pci_data_write(void *opaque
, uint32_t addr
, uint32_t val
, int len
)
605 int config_addr
, bus_num
;
608 PCI_DPRINTF("pci_data_write: addr=%08x val=%08x len=%d\n",
611 bus_num
= (addr
>> 16) & 0xff;
612 while (s
&& s
->bus_num
!= bus_num
)
616 pci_dev
= s
->devices
[(addr
>> 8) & 0xff];
619 config_addr
= addr
& 0xff;
620 PCI_DPRINTF("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
621 pci_dev
->name
, config_addr
, val
, len
);
622 pci_dev
->config_write(pci_dev
, config_addr
, val
, len
);
625 uint32_t pci_data_read(void *opaque
, uint32_t addr
, int len
)
629 int config_addr
, bus_num
;
632 bus_num
= (addr
>> 16) & 0xff;
633 while (s
&& s
->bus_num
!= bus_num
)
637 pci_dev
= s
->devices
[(addr
>> 8) & 0xff];
654 config_addr
= addr
& 0xff;
655 val
= pci_dev
->config_read(pci_dev
, config_addr
, len
);
656 PCI_DPRINTF("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
657 pci_dev
->name
, config_addr
, val
, len
);
660 PCI_DPRINTF("pci_data_read: addr=%08x val=%08x len=%d\n",
666 /***********************************************************/
667 /* generic PCI irq support */
669 /* 0 <= irq_num <= 3. level must be 0 or 1 */
670 static void pci_set_irq(void *opaque
, int irq_num
, int level
)
672 PCIDevice
*pci_dev
= opaque
;
676 change
= level
- pci_dev
->irq_state
[irq_num
];
680 pci_dev
->irq_state
[irq_num
] = level
;
683 irq_num
= bus
->map_irq(pci_dev
, irq_num
);
686 pci_dev
= bus
->parent_dev
;
688 bus
->irq_count
[irq_num
] += change
;
689 bus
->set_irq(bus
->irq_opaque
, irq_num
, bus
->irq_count
[irq_num
] != 0);
692 /***********************************************************/
693 /* monitor info on PCI */
700 static const pci_class_desc pci_class_descriptions
[] =
702 { 0x0100, "SCSI controller"},
703 { 0x0101, "IDE controller"},
704 { 0x0102, "Floppy controller"},
705 { 0x0103, "IPI controller"},
706 { 0x0104, "RAID controller"},
707 { 0x0106, "SATA controller"},
708 { 0x0107, "SAS controller"},
709 { 0x0180, "Storage controller"},
710 { 0x0200, "Ethernet controller"},
711 { 0x0201, "Token Ring controller"},
712 { 0x0202, "FDDI controller"},
713 { 0x0203, "ATM controller"},
714 { 0x0280, "Network controller"},
715 { 0x0300, "VGA controller"},
716 { 0x0301, "XGA controller"},
717 { 0x0302, "3D controller"},
718 { 0x0380, "Display controller"},
719 { 0x0400, "Video controller"},
720 { 0x0401, "Audio controller"},
722 { 0x0480, "Multimedia controller"},
723 { 0x0500, "RAM controller"},
724 { 0x0501, "Flash controller"},
725 { 0x0580, "Memory controller"},
726 { 0x0600, "Host bridge"},
727 { 0x0601, "ISA bridge"},
728 { 0x0602, "EISA bridge"},
729 { 0x0603, "MC bridge"},
730 { 0x0604, "PCI bridge"},
731 { 0x0605, "PCMCIA bridge"},
732 { 0x0606, "NUBUS bridge"},
733 { 0x0607, "CARDBUS bridge"},
734 { 0x0608, "RACEWAY bridge"},
736 { 0x0c03, "USB controller"},
740 static void pci_info_device(PCIDevice
*d
)
742 Monitor
*mon
= cur_mon
;
745 const pci_class_desc
*desc
;
747 monitor_printf(mon
, " Bus %2d, device %3d, function %d:\n",
748 d
->bus
->bus_num
, d
->devfn
>> 3, d
->devfn
& 7);
749 class = le16_to_cpu(*((uint16_t *)(d
->config
+ PCI_CLASS_DEVICE
)));
750 monitor_printf(mon
, " ");
751 desc
= pci_class_descriptions
;
752 while (desc
->desc
&& class != desc
->class)
755 monitor_printf(mon
, "%s", desc
->desc
);
757 monitor_printf(mon
, "Class %04x", class);
759 monitor_printf(mon
, ": PCI device %04x:%04x\n",
760 le16_to_cpu(*((uint16_t *)(d
->config
+ PCI_VENDOR_ID
))),
761 le16_to_cpu(*((uint16_t *)(d
->config
+ PCI_DEVICE_ID
))));
763 if (d
->config
[PCI_INTERRUPT_PIN
] != 0) {
764 monitor_printf(mon
, " IRQ %d.\n",
765 d
->config
[PCI_INTERRUPT_LINE
]);
767 if (class == 0x0604) {
768 monitor_printf(mon
, " BUS %d.\n", d
->config
[0x19]);
770 for(i
= 0;i
< PCI_NUM_REGIONS
; i
++) {
771 r
= &d
->io_regions
[i
];
773 monitor_printf(mon
, " BAR%d: ", i
);
774 if (r
->type
& PCI_ADDRESS_SPACE_IO
) {
775 monitor_printf(mon
, "I/O at 0x%04x [0x%04x].\n",
776 r
->addr
, r
->addr
+ r
->size
- 1);
778 monitor_printf(mon
, "32 bit memory at 0x%08x [0x%08x].\n",
779 r
->addr
, r
->addr
+ r
->size
- 1);
783 monitor_printf(mon
, " id \"%s\"\n", d
->qdev
.id
? d
->qdev
.id
: "");
784 if (class == 0x0604 && d
->config
[0x19] != 0) {
785 pci_for_each_device(d
->config
[0x19], pci_info_device
);
789 void pci_for_each_device(int bus_num
, void (*fn
)(PCIDevice
*d
))
791 PCIBus
*bus
= first_bus
;
795 while (bus
&& bus
->bus_num
!= bus_num
)
798 for(devfn
= 0; devfn
< 256; devfn
++) {
799 d
= bus
->devices
[devfn
];
806 void pci_info(Monitor
*mon
)
808 pci_for_each_device(0, pci_info_device
);
811 static const char * const pci_nic_models
[] = {
823 static const char * const pci_nic_names
[] = {
835 /* Initialize a PCI NIC. */
836 /* FIXME callers should check for failure, but don't */
837 PCIDevice
*pci_nic_init(NICInfo
*nd
, const char *default_model
,
838 const char *default_devaddr
)
840 const char *devaddr
= nd
->devaddr
? nd
->devaddr
: default_devaddr
;
847 i
= qemu_find_nic_model(nd
, pci_nic_models
, default_model
);
851 bus
= pci_get_bus_devfn(&devfn
, devaddr
);
853 qemu_error("Invalid PCI device address %s for device %s\n",
854 devaddr
, pci_nic_names
[i
]);
858 pci_dev
= pci_create(bus
, devfn
, pci_nic_names
[i
]);
859 dev
= &pci_dev
->qdev
;
861 dev
->id
= qemu_strdup(nd
->name
);
862 qdev_set_nic_properties(dev
, nd
);
863 if (qdev_init(dev
) < 0)
868 PCIDevice
*pci_nic_init_nofail(NICInfo
*nd
, const char *default_model
,
869 const char *default_devaddr
)
873 if (qemu_show_nic_models(nd
->model
, pci_nic_models
))
876 res
= pci_nic_init(nd
, default_model
, default_devaddr
);
889 static void pci_bridge_write_config(PCIDevice
*d
,
890 uint32_t address
, uint32_t val
, int len
)
892 PCIBridge
*s
= (PCIBridge
*)d
;
894 pci_default_write_config(d
, address
, val
, len
);
895 s
->bus
.bus_num
= d
->config
[PCI_SECONDARY_BUS
];
898 PCIBus
*pci_find_bus(int bus_num
)
900 PCIBus
*bus
= first_bus
;
902 while (bus
&& bus
->bus_num
!= bus_num
)
908 PCIDevice
*pci_find_device(int bus_num
, int slot
, int function
)
910 PCIBus
*bus
= pci_find_bus(bus_num
);
915 return bus
->devices
[PCI_DEVFN(slot
, function
)];
918 static int pci_bridge_initfn(PCIDevice
*dev
)
920 PCIBridge
*s
= DO_UPCAST(PCIBridge
, dev
, dev
);
922 pci_config_set_vendor_id(s
->dev
.config
, s
->vid
);
923 pci_config_set_device_id(s
->dev
.config
, s
->did
);
925 s
->dev
.config
[0x04] = 0x06; // command = bus master, pci mem
926 s
->dev
.config
[0x05] = 0x00;
927 s
->dev
.config
[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
928 s
->dev
.config
[0x07] = 0x00; // status = fast devsel
929 s
->dev
.config
[0x08] = 0x00; // revision
930 s
->dev
.config
[0x09] = 0x00; // programming i/f
931 pci_config_set_class(s
->dev
.config
, PCI_CLASS_BRIDGE_PCI
);
932 s
->dev
.config
[0x0D] = 0x10; // latency_timer
933 s
->dev
.config
[PCI_HEADER_TYPE
] =
934 PCI_HEADER_TYPE_MULTI_FUNCTION
| PCI_HEADER_TYPE_BRIDGE
; // header_type
935 s
->dev
.config
[0x1E] = 0xa0; // secondary status
939 PCIBus
*pci_bridge_init(PCIBus
*bus
, int devfn
, uint16_t vid
, uint16_t did
,
940 pci_map_irq_fn map_irq
, const char *name
)
945 dev
= pci_create(bus
, devfn
, "pci-bridge");
946 qdev_prop_set_uint32(&dev
->qdev
, "vendorid", vid
);
947 qdev_prop_set_uint32(&dev
->qdev
, "deviceid", did
);
948 qdev_init_nofail(&dev
->qdev
);
950 s
= DO_UPCAST(PCIBridge
, dev
, dev
);
951 pci_register_secondary_bus(&s
->bus
, &s
->dev
, map_irq
, name
);
955 static int pci_qdev_init(DeviceState
*qdev
, DeviceInfo
*base
)
957 PCIDevice
*pci_dev
= (PCIDevice
*)qdev
;
958 PCIDeviceInfo
*info
= container_of(base
, PCIDeviceInfo
, qdev
);
962 bus
= FROM_QBUS(PCIBus
, qdev_get_parent_bus(qdev
));
963 devfn
= pci_dev
->devfn
;
964 pci_dev
= do_pci_register_device(pci_dev
, bus
, base
->name
, devfn
,
965 info
->config_read
, info
->config_write
);
967 rc
= info
->init(pci_dev
);
970 if (qdev
->hotplugged
)
971 bus
->hotplug(pci_dev
, 1);
975 static int pci_unplug_device(DeviceState
*qdev
)
977 PCIDevice
*dev
= DO_UPCAST(PCIDevice
, qdev
, qdev
);
979 dev
->bus
->hotplug(dev
, 0);
983 void pci_qdev_register(PCIDeviceInfo
*info
)
985 info
->qdev
.init
= pci_qdev_init
;
986 info
->qdev
.unplug
= pci_unplug_device
;
987 info
->qdev
.exit
= pci_unregister_device
;
988 info
->qdev
.bus_info
= &pci_bus_info
;
989 qdev_register(&info
->qdev
);
992 void pci_qdev_register_many(PCIDeviceInfo
*info
)
994 while (info
->qdev
.name
) {
995 pci_qdev_register(info
);
1000 PCIDevice
*pci_create(PCIBus
*bus
, int devfn
, const char *name
)
1004 dev
= qdev_create(&bus
->qbus
, name
);
1005 qdev_prop_set_uint32(dev
, "addr", devfn
);
1006 return DO_UPCAST(PCIDevice
, qdev
, dev
);
1009 PCIDevice
*pci_create_simple(PCIBus
*bus
, int devfn
, const char *name
)
1011 PCIDevice
*dev
= pci_create(bus
, devfn
, name
);
1012 qdev_init_nofail(&dev
->qdev
);
1016 static int pci_find_space(PCIDevice
*pdev
, uint8_t size
)
1018 int offset
= PCI_CONFIG_HEADER_SIZE
;
1020 for (i
= PCI_CONFIG_HEADER_SIZE
; i
< PCI_CONFIG_SPACE_SIZE
; ++i
)
1023 else if (i
- offset
+ 1 == size
)
1028 static uint8_t pci_find_capability_list(PCIDevice
*pdev
, uint8_t cap_id
,
1033 if (!(pdev
->config
[PCI_STATUS
] & PCI_STATUS_CAP_LIST
))
1036 for (prev
= PCI_CAPABILITY_LIST
; (next
= pdev
->config
[prev
]);
1037 prev
= next
+ PCI_CAP_LIST_NEXT
)
1038 if (pdev
->config
[next
+ PCI_CAP_LIST_ID
] == cap_id
)
1046 /* Reserve space and add capability to the linked list in pci config space */
1047 int pci_add_capability(PCIDevice
*pdev
, uint8_t cap_id
, uint8_t size
)
1049 uint8_t offset
= pci_find_space(pdev
, size
);
1050 uint8_t *config
= pdev
->config
+ offset
;
1053 config
[PCI_CAP_LIST_ID
] = cap_id
;
1054 config
[PCI_CAP_LIST_NEXT
] = pdev
->config
[PCI_CAPABILITY_LIST
];
1055 pdev
->config
[PCI_CAPABILITY_LIST
] = offset
;
1056 pdev
->config
[PCI_STATUS
] |= PCI_STATUS_CAP_LIST
;
1057 memset(pdev
->used
+ offset
, 0xFF, size
);
1058 /* Make capability read-only by default */
1059 memset(pdev
->wmask
+ offset
, 0, size
);
1060 /* Check capability by default */
1061 memset(pdev
->cmask
+ offset
, 0xFF, size
);
1065 /* Unlink capability from the pci config space. */
1066 void pci_del_capability(PCIDevice
*pdev
, uint8_t cap_id
, uint8_t size
)
1068 uint8_t prev
, offset
= pci_find_capability_list(pdev
, cap_id
, &prev
);
1071 pdev
->config
[prev
] = pdev
->config
[offset
+ PCI_CAP_LIST_NEXT
];
1072 /* Make capability writeable again */
1073 memset(pdev
->wmask
+ offset
, 0xff, size
);
1074 /* Clear cmask as device-specific registers can't be checked */
1075 memset(pdev
->cmask
+ offset
, 0, size
);
1076 memset(pdev
->used
+ offset
, 0, size
);
1078 if (!pdev
->config
[PCI_CAPABILITY_LIST
])
1079 pdev
->config
[PCI_STATUS
] &= ~PCI_STATUS_CAP_LIST
;
1082 /* Reserve space for capability at a known offset (to call after load). */
1083 void pci_reserve_capability(PCIDevice
*pdev
, uint8_t offset
, uint8_t size
)
1085 memset(pdev
->used
+ offset
, 0xff, size
);
1088 uint8_t pci_find_capability(PCIDevice
*pdev
, uint8_t cap_id
)
1090 return pci_find_capability_list(pdev
, cap_id
, NULL
);
1093 static void pcibus_dev_print(Monitor
*mon
, DeviceState
*dev
, int indent
)
1095 PCIDevice
*d
= (PCIDevice
*)dev
;
1096 const pci_class_desc
*desc
;
1101 class = le16_to_cpu(*((uint16_t *)(d
->config
+ PCI_CLASS_DEVICE
)));
1102 desc
= pci_class_descriptions
;
1103 while (desc
->desc
&& class != desc
->class)
1106 snprintf(ctxt
, sizeof(ctxt
), "%s", desc
->desc
);
1108 snprintf(ctxt
, sizeof(ctxt
), "Class %04x", class);
1111 monitor_printf(mon
, "%*sclass %s, addr %02x:%02x.%x, "
1112 "pci id %04x:%04x (sub %04x:%04x)\n",
1114 d
->bus
->bus_num
, d
->devfn
>> 3, d
->devfn
& 7,
1115 le16_to_cpu(*((uint16_t *)(d
->config
+ PCI_VENDOR_ID
))),
1116 le16_to_cpu(*((uint16_t *)(d
->config
+ PCI_DEVICE_ID
))),
1117 le16_to_cpu(*((uint16_t *)(d
->config
+ PCI_SUBSYSTEM_VENDOR_ID
))),
1118 le16_to_cpu(*((uint16_t *)(d
->config
+ PCI_SUBSYSTEM_ID
))));
1119 for (i
= 0; i
< PCI_NUM_REGIONS
; i
++) {
1120 r
= &d
->io_regions
[i
];
1123 monitor_printf(mon
, "%*sbar %d: %s at 0x%x [0x%x]\n", indent
, "",
1124 i
, r
->type
& PCI_ADDRESS_SPACE_IO
? "i/o" : "mem",
1125 r
->addr
, r
->addr
+ r
->size
- 1);
1129 static PCIDeviceInfo bridge_info
= {
1130 .qdev
.name
= "pci-bridge",
1131 .qdev
.size
= sizeof(PCIBridge
),
1132 .init
= pci_bridge_initfn
,
1133 .config_write
= pci_bridge_write_config
,
1134 .qdev
.props
= (Property
[]) {
1135 DEFINE_PROP_HEX32("vendorid", PCIBridge
, vid
, 0),
1136 DEFINE_PROP_HEX32("deviceid", PCIBridge
, did
, 0),
1137 DEFINE_PROP_END_OF_LIST(),
1141 static void pci_register_devices(void)
1143 pci_qdev_register(&bridge_info
);
1146 device_init(pci_register_devices
)