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trace: avoid "is" with a literal Python 3.8 warnings
[qemu.git] / memory.c
blob978da3d3df65aab2fb6b6f7f6d99beb9e7812cbf
1 /*
2 * Physical memory management
3 *
4 * Copyright 2011 Red Hat, Inc. and/or its affiliates
5 *
6 * Authors:
7 * Avi Kivity <avi@redhat.com>
8 *
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
11 *
12 * Contributions after 2012-01-13 are licensed under the terms of the
13 * GNU GPL, version 2 or (at your option) any later version.
14 */
15
16 #include "qemu/osdep.h"
17 #include "qapi/error.h"
18 #include "cpu.h"
19 #include "exec/memory.h"
20 #include "exec/address-spaces.h"
21 #include "qapi/visitor.h"
22 #include "qemu/bitops.h"
23 #include "qemu/error-report.h"
24 #include "qemu/main-loop.h"
25 #include "qemu/qemu-print.h"
26 #include "qom/object.h"
27 #include "trace-root.h"
28
29 #include "exec/memory-internal.h"
30 #include "exec/ram_addr.h"
31 #include "sysemu/kvm.h"
32 #include "sysemu/runstate.h"
33 #include "sysemu/tcg.h"
34 #include "sysemu/accel.h"
35 #include "hw/boards.h"
36 #include "migration/vmstate.h"
37
38 //#define DEBUG_UNASSIGNED
39
40 static unsigned memory_region_transaction_depth;
41 static bool memory_region_update_pending;
42 static bool ioeventfd_update_pending;
43 bool global_dirty_log;
44
45 static QTAILQ_HEAD(, MemoryListener) memory_listeners
46 = QTAILQ_HEAD_INITIALIZER(memory_listeners);
47
48 static QTAILQ_HEAD(, AddressSpace) address_spaces
49 = QTAILQ_HEAD_INITIALIZER(address_spaces);
50
51 static GHashTable *flat_views;
52
53 typedef struct AddrRange AddrRange;
54
55 /*
56 * Note that signed integers are needed for negative offsetting in aliases
57 * (large MemoryRegion::alias_offset).
58 */
59 struct AddrRange {
60 Int128 start;
61 Int128 size;
62 };
63
64 static AddrRange addrrange_make(Int128 start, Int128 size)
65 {
66 return (AddrRange) { start, size };
67 }
68
69 static bool addrrange_equal(AddrRange r1, AddrRange r2)
70 {
71 return int128_eq(r1.start, r2.start) && int128_eq(r1.size, r2.size);
72 }
73
74 static Int128 addrrange_end(AddrRange r)
75 {
76 return int128_add(r.start, r.size);
77 }
78
79 static AddrRange addrrange_shift(AddrRange range, Int128 delta)
80 {
81 int128_addto(&range.start, delta);
82 return range;
83 }
84
85 static bool addrrange_contains(AddrRange range, Int128 addr)
86 {
87 return int128_ge(addr, range.start)
88 && int128_lt(addr, addrrange_end(range));
89 }
90
91 static bool addrrange_intersects(AddrRange r1, AddrRange r2)
92 {
93 return addrrange_contains(r1, r2.start)
94 || addrrange_contains(r2, r1.start);
95 }
96
97 static AddrRange addrrange_intersection(AddrRange r1, AddrRange r2)
98 {
99 Int128 start = int128_max(r1.start, r2.start);
100 Int128 end = int128_min(addrrange_end(r1), addrrange_end(r2));
101 return addrrange_make(start, int128_sub(end, start));
102 }
103
104 enum ListenerDirection { Forward, Reverse };
105
106 #define MEMORY_LISTENER_CALL_GLOBAL(_callback, _direction, _args...) \
107 do { \
108 MemoryListener *_listener; \
109 \
110 switch (_direction) { \
111 case Forward: \
112 QTAILQ_FOREACH(_listener, &memory_listeners, link) { \
113 if (_listener->_callback) { \
114 _listener->_callback(_listener, ##_args); \
115 } \
116 } \
117 break; \
118 case Reverse: \
119 QTAILQ_FOREACH_REVERSE(_listener, &memory_listeners, link) { \
120 if (_listener->_callback) { \
121 _listener->_callback(_listener, ##_args); \
122 } \
123 } \
124 break; \
125 default: \
126 abort(); \
127 } \
128 } while (0)
129
130 #define MEMORY_LISTENER_CALL(_as, _callback, _direction, _section, _args...) \
131 do { \
132 MemoryListener *_listener; \
133 \
134 switch (_direction) { \
135 case Forward: \
136 QTAILQ_FOREACH(_listener, &(_as)->listeners, link_as) { \
137 if (_listener->_callback) { \
138 _listener->_callback(_listener, _section, ##_args); \
139 } \
140 } \
141 break; \
142 case Reverse: \
143 QTAILQ_FOREACH_REVERSE(_listener, &(_as)->listeners, link_as) { \
144 if (_listener->_callback) { \
145 _listener->_callback(_listener, _section, ##_args); \
146 } \
147 } \
148 break; \
149 default: \
150 abort(); \
151 } \
152 } while (0)
153
154 /* No need to ref/unref .mr, the FlatRange keeps it alive. */
155 #define MEMORY_LISTENER_UPDATE_REGION(fr, as, dir, callback, _args...) \
156 do { \
157 MemoryRegionSection mrs = section_from_flat_range(fr, \
158 address_space_to_flatview(as)); \
159 MEMORY_LISTENER_CALL(as, callback, dir, &mrs, ##_args); \
160 } while(0)
161
162 struct CoalescedMemoryRange {
163 AddrRange addr;
164 QTAILQ_ENTRY(CoalescedMemoryRange) link;
165 };
166
167 struct MemoryRegionIoeventfd {
168 AddrRange addr;
169 bool match_data;
170 uint64_t data;
171 EventNotifier *e;
172 };
173
174 static bool memory_region_ioeventfd_before(MemoryRegionIoeventfd *a,
175 MemoryRegionIoeventfd *b)
176 {
177 if (int128_lt(a->addr.start, b->addr.start)) {
178 return true;
179 } else if (int128_gt(a->addr.start, b->addr.start)) {
180 return false;
181 } else if (int128_lt(a->addr.size, b->addr.size)) {
182 return true;
183 } else if (int128_gt(a->addr.size, b->addr.size)) {
184 return false;
185 } else if (a->match_data < b->match_data) {
186 return true;
187 } else if (a->match_data > b->match_data) {
188 return false;
189 } else if (a->match_data) {
190 if (a->data < b->data) {
191 return true;
192 } else if (a->data > b->data) {
193 return false;
194 }
195 }
196 if (a->e < b->e) {
197 return true;
198 } else if (a->e > b->e) {
199 return false;
200 }
201 return false;
202 }
203
204 static bool memory_region_ioeventfd_equal(MemoryRegionIoeventfd *a,
205 MemoryRegionIoeventfd *b)
206 {
207 return !memory_region_ioeventfd_before(a, b)
208 && !memory_region_ioeventfd_before(b, a);
209 }
210
211 /* Range of memory in the global map. Addresses are absolute. */
212 struct FlatRange {
213 MemoryRegion *mr;
214 hwaddr offset_in_region;
215 AddrRange addr;
216 uint8_t dirty_log_mask;
217 bool romd_mode;
218 bool readonly;
219 bool nonvolatile;
220 };
221
222 #define FOR_EACH_FLAT_RANGE(var, view) \
223 for (var = (view)->ranges; var < (view)->ranges + (view)->nr; ++var)
224
225 static inline MemoryRegionSection
226 section_from_flat_range(FlatRange *fr, FlatView *fv)
227 {
228 return (MemoryRegionSection) {
229 .mr = fr->mr,
230 .fv = fv,
231 .offset_within_region = fr->offset_in_region,
232 .size = fr->addr.size,
233 .offset_within_address_space = int128_get64(fr->addr.start),
234 .readonly = fr->readonly,
235 .nonvolatile = fr->nonvolatile,
236 };
237 }
238
239 static bool flatrange_equal(FlatRange *a, FlatRange *b)
240 {
241 return a->mr == b->mr
242 && addrrange_equal(a->addr, b->addr)
243 && a->offset_in_region == b->offset_in_region
244 && a->romd_mode == b->romd_mode
245 && a->readonly == b->readonly
246 && a->nonvolatile == b->nonvolatile;
247 }
248
249 static FlatView *flatview_new(MemoryRegion *mr_root)
250 {
251 FlatView *view;
252
253 view = g_new0(FlatView, 1);
254 view->ref = 1;
255 view->root = mr_root;
256 memory_region_ref(mr_root);
257 trace_flatview_new(view, mr_root);
258
259 return view;
260 }
261
262 /* Insert a range into a given position. Caller is responsible for maintaining
263 * sorting order.
264 */
265 static void flatview_insert(FlatView *view, unsigned pos, FlatRange *range)
266 {
267 if (view->nr == view->nr_allocated) {
268 view->nr_allocated = MAX(2 * view->nr, 10);
269 view->ranges = g_realloc(view->ranges,
270 view->nr_allocated * sizeof(*view->ranges));
271 }
272 memmove(view->ranges + pos + 1, view->ranges + pos,
273 (view->nr - pos) * sizeof(FlatRange));
274 view->ranges[pos] = *range;
275 memory_region_ref(range->mr);
276 ++view->nr;
277 }
278
279 static void flatview_destroy(FlatView *view)
280 {
281 int i;
282
283 trace_flatview_destroy(view, view->root);
284 if (view->dispatch) {
285 address_space_dispatch_free(view->dispatch);
286 }
287 for (i = 0; i < view->nr; i++) {
288 memory_region_unref(view->ranges[i].mr);
289 }
290 g_free(view->ranges);
291 memory_region_unref(view->root);
292 g_free(view);
293 }
294
295 static bool flatview_ref(FlatView *view)
296 {
297 return atomic_fetch_inc_nonzero(&view->ref) > 0;
298 }
299
300 void flatview_unref(FlatView *view)
301 {
302 if (atomic_fetch_dec(&view->ref) == 1) {
303 trace_flatview_destroy_rcu(view, view->root);
304 assert(view->root);
305 call_rcu(view, flatview_destroy, rcu);
306 }
307 }
308
309 static bool can_merge(FlatRange *r1, FlatRange *r2)
310 {
311 return int128_eq(addrrange_end(r1->addr), r2->addr.start)
312 && r1->mr == r2->mr
313 && int128_eq(int128_add(int128_make64(r1->offset_in_region),
314 r1->addr.size),
315 int128_make64(r2->offset_in_region))
316 && r1->dirty_log_mask == r2->dirty_log_mask
317 && r1->romd_mode == r2->romd_mode
318 && r1->readonly == r2->readonly
319 && r1->nonvolatile == r2->nonvolatile;
320 }
321
322 /* Attempt to simplify a view by merging adjacent ranges */
323 static void flatview_simplify(FlatView *view)
324 {
325 unsigned i, j, k;
326
327 i = 0;
328 while (i < view->nr) {
329 j = i + 1;
330 while (j < view->nr
331 && can_merge(&view->ranges[j-1], &view->ranges[j])) {
332 int128_addto(&view->ranges[i].addr.size, view->ranges[j].addr.size);
333 ++j;
334 }
335 ++i;
336 for (k = i; k < j; k++) {
337 memory_region_unref(view->ranges[k].mr);
338 }
339 memmove(&view->ranges[i], &view->ranges[j],
340 (view->nr - j) * sizeof(view->ranges[j]));
341 view->nr -= j - i;
342 }
343 }
344
345 static bool memory_region_big_endian(MemoryRegion *mr)
346 {
347 #ifdef TARGET_WORDS_BIGENDIAN
348 return mr->ops->endianness != DEVICE_LITTLE_ENDIAN;
349 #else
350 return mr->ops->endianness == DEVICE_BIG_ENDIAN;
351 #endif
352 }
353
354 static void adjust_endianness(MemoryRegion *mr, uint64_t *data, MemOp op)
355 {
356 if ((op & MO_BSWAP) != devend_memop(mr->ops->endianness)) {
357 switch (op & MO_SIZE) {
358 case MO_8:
359 break;
360 case MO_16:
361 *data = bswap16(*data);
362 break;
363 case MO_32:
364 *data = bswap32(*data);
365 break;
366 case MO_64:
367 *data = bswap64(*data);
368 break;
369 default:
370 g_assert_not_reached();
371 }
372 }
373 }
374
375 static inline void memory_region_shift_read_access(uint64_t *value,
376 signed shift,
377 uint64_t mask,
378 uint64_t tmp)
379 {
380 if (shift >= 0) {
381 *value |= (tmp & mask) << shift;
382 } else {
383 *value |= (tmp & mask) >> -shift;
384 }
385 }
386
387 static inline uint64_t memory_region_shift_write_access(uint64_t *value,
388 signed shift,
389 uint64_t mask)
390 {
391 uint64_t tmp;
392
393 if (shift >= 0) {
394 tmp = (*value >> shift) & mask;
395 } else {
396 tmp = (*value << -shift) & mask;
397 }
398
399 return tmp;
400 }
401
402 static hwaddr memory_region_to_absolute_addr(MemoryRegion *mr, hwaddr offset)
403 {
404 MemoryRegion *root;
405 hwaddr abs_addr = offset;
406
407 abs_addr += mr->addr;
408 for (root = mr; root->container; ) {
409 root = root->container;
410 abs_addr += root->addr;
411 }
412
413 return abs_addr;
414 }
415
416 static int get_cpu_index(void)
417 {
418 if (current_cpu) {
419 return current_cpu->cpu_index;
420 }
421 return -1;
422 }
423
424 static MemTxResult memory_region_read_accessor(MemoryRegion *mr,
425 hwaddr addr,
426 uint64_t *value,
427 unsigned size,
428 signed shift,
429 uint64_t mask,
430 MemTxAttrs attrs)
431 {
432 uint64_t tmp;
433
434 tmp = mr->ops->read(mr->opaque, addr, size);
435 if (mr->subpage) {
436 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
437 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
438 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
439 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
440 }
441 memory_region_shift_read_access(value, shift, mask, tmp);
442 return MEMTX_OK;
443 }
444
445 static MemTxResult memory_region_read_with_attrs_accessor(MemoryRegion *mr,
446 hwaddr addr,
447 uint64_t *value,
448 unsigned size,
449 signed shift,
450 uint64_t mask,
451 MemTxAttrs attrs)
452 {
453 uint64_t tmp = 0;
454 MemTxResult r;
455
456 r = mr->ops->read_with_attrs(mr->opaque, addr, &tmp, size, attrs);
457 if (mr->subpage) {
458 trace_memory_region_subpage_read(get_cpu_index(), mr, addr, tmp, size);
459 } else if (TRACE_MEMORY_REGION_OPS_READ_ENABLED) {
460 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
461 trace_memory_region_ops_read(get_cpu_index(), mr, abs_addr, tmp, size);
462 }
463 memory_region_shift_read_access(value, shift, mask, tmp);
464 return r;
465 }
466
467 static MemTxResult memory_region_write_accessor(MemoryRegion *mr,
468 hwaddr addr,
469 uint64_t *value,
470 unsigned size,
471 signed shift,
472 uint64_t mask,
473 MemTxAttrs attrs)
474 {
475 uint64_t tmp = memory_region_shift_write_access(value, shift, mask);
476
477 if (mr->subpage) {
478 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
479 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
480 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
481 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
482 }
483 mr->ops->write(mr->opaque, addr, tmp, size);
484 return MEMTX_OK;
485 }
486
487 static MemTxResult memory_region_write_with_attrs_accessor(MemoryRegion *mr,
488 hwaddr addr,
489 uint64_t *value,
490 unsigned size,
491 signed shift,
492 uint64_t mask,
493 MemTxAttrs attrs)
494 {
495 uint64_t tmp = memory_region_shift_write_access(value, shift, mask);
496
497 if (mr->subpage) {
498 trace_memory_region_subpage_write(get_cpu_index(), mr, addr, tmp, size);
499 } else if (TRACE_MEMORY_REGION_OPS_WRITE_ENABLED) {
500 hwaddr abs_addr = memory_region_to_absolute_addr(mr, addr);
501 trace_memory_region_ops_write(get_cpu_index(), mr, abs_addr, tmp, size);
502 }
503 return mr->ops->write_with_attrs(mr->opaque, addr, tmp, size, attrs);
504 }
505
506 static MemTxResult access_with_adjusted_size(hwaddr addr,
507 uint64_t *value,
508 unsigned size,
509 unsigned access_size_min,
510 unsigned access_size_max,
511 MemTxResult (*access_fn)
512 (MemoryRegion *mr,
513 hwaddr addr,
514 uint64_t *value,
515 unsigned size,
516 signed shift,
517 uint64_t mask,
518 MemTxAttrs attrs),
519 MemoryRegion *mr,
520 MemTxAttrs attrs)
521 {
522 uint64_t access_mask;
523 unsigned access_size;
524 unsigned i;
525 MemTxResult r = MEMTX_OK;
526
527 if (!access_size_min) {
528 access_size_min = 1;
529 }
530 if (!access_size_max) {
531 access_size_max = 4;
532 }
533
534 /* FIXME: support unaligned access? */
535 access_size = MAX(MIN(size, access_size_max), access_size_min);
536 access_mask = MAKE_64BIT_MASK(0, access_size * 8);
537 if (memory_region_big_endian(mr)) {
538 for (i = 0; i < size; i += access_size) {
539 r |= access_fn(mr, addr + i, value, access_size,
540 (size - access_size - i) * 8, access_mask, attrs);
541 }
542 } else {
543 for (i = 0; i < size; i += access_size) {
544 r |= access_fn(mr, addr + i, value, access_size, i * 8,
545 access_mask, attrs);
546 }
547 }
548 return r;
549 }
550
551 static AddressSpace *memory_region_to_address_space(MemoryRegion *mr)
552 {
553 AddressSpace *as;
554
555 while (mr->container) {
556 mr = mr->container;
557 }
558 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
559 if (mr == as->root) {
560 return as;
561 }
562 }
563 return NULL;
564 }
565
566 /* Render a memory region into the global view. Ranges in @view obscure
567 * ranges in @mr.
568 */
569 static void render_memory_region(FlatView *view,
570 MemoryRegion *mr,
571 Int128 base,
572 AddrRange clip,
573 bool readonly,
574 bool nonvolatile)
575 {
576 MemoryRegion *subregion;
577 unsigned i;
578 hwaddr offset_in_region;
579 Int128 remain;
580 Int128 now;
581 FlatRange fr;
582 AddrRange tmp;
583
584 if (!mr->enabled) {
585 return;
586 }
587
588 int128_addto(&base, int128_make64(mr->addr));
589 readonly |= mr->readonly;
590 nonvolatile |= mr->nonvolatile;
591
592 tmp = addrrange_make(base, mr->size);
593
594 if (!addrrange_intersects(tmp, clip)) {
595 return;
596 }
597
598 clip = addrrange_intersection(tmp, clip);
599
600 if (mr->alias) {
601 int128_subfrom(&base, int128_make64(mr->alias->addr));
602 int128_subfrom(&base, int128_make64(mr->alias_offset));
603 render_memory_region(view, mr->alias, base, clip,
604 readonly, nonvolatile);
605 return;
606 }
607
608 /* Render subregions in priority order. */
609 QTAILQ_FOREACH(subregion, &mr->subregions, subregions_link) {
610 render_memory_region(view, subregion, base, clip,
611 readonly, nonvolatile);
612 }
613
614 if (!mr->terminates) {
615 return;
616 }
617
618 offset_in_region = int128_get64(int128_sub(clip.start, base));
619 base = clip.start;
620 remain = clip.size;
621
622 fr.mr = mr;
623 fr.dirty_log_mask = memory_region_get_dirty_log_mask(mr);
624 fr.romd_mode = mr->romd_mode;
625 fr.readonly = readonly;
626 fr.nonvolatile = nonvolatile;
627
628 /* Render the region itself into any gaps left by the current view. */
629 for (i = 0; i < view->nr && int128_nz(remain); ++i) {
630 if (int128_ge(base, addrrange_end(view->ranges[i].addr))) {
631 continue;
632 }
633 if (int128_lt(base, view->ranges[i].addr.start)) {
634 now = int128_min(remain,
635 int128_sub(view->ranges[i].addr.start, base));
636 fr.offset_in_region = offset_in_region;
637 fr.addr = addrrange_make(base, now);
638 flatview_insert(view, i, &fr);
639 ++i;
640 int128_addto(&base, now);
641 offset_in_region += int128_get64(now);
642 int128_subfrom(&remain, now);
643 }
644 now = int128_sub(int128_min(int128_add(base, remain),
645 addrrange_end(view->ranges[i].addr)),
646 base);
647 int128_addto(&base, now);
648 offset_in_region += int128_get64(now);
649 int128_subfrom(&remain, now);
650 }
651 if (int128_nz(remain)) {
652 fr.offset_in_region = offset_in_region;
653 fr.addr = addrrange_make(base, remain);
654 flatview_insert(view, i, &fr);
655 }
656 }
657
658 static MemoryRegion *memory_region_get_flatview_root(MemoryRegion *mr)
659 {
660 while (mr->enabled) {
661 if (mr->alias) {
662 if (!mr->alias_offset && int128_ge(mr->size, mr->alias->size)) {
663 /* The alias is included in its entirety. Use it as
664 * the "real" root, so that we can share more FlatViews.
665 */
666 mr = mr->alias;
667 continue;
668 }
669 } else if (!mr->terminates) {
670 unsigned int found = 0;
671 MemoryRegion *child, *next = NULL;
672 QTAILQ_FOREACH(child, &mr->subregions, subregions_link) {
673 if (child->enabled) {
674 if (++found > 1) {
675 next = NULL;
676 break;
677 }
678 if (!child->addr && int128_ge(mr->size, child->size)) {
679 /* A child is included in its entirety. If it's the only
680 * enabled one, use it in the hope of finding an alias down the
681 * way. This will also let us share FlatViews.
682 */
683 next = child;
684 }
685 }
686 }
687 if (found == 0) {
688 return NULL;
689 }
690 if (next) {
691 mr = next;
692 continue;
693 }
694 }
695
696 return mr;
697 }
698
699 return NULL;
700 }
701
702 /* Render a memory topology into a list of disjoint absolute ranges. */
703 static FlatView *generate_memory_topology(MemoryRegion *mr)
704 {
705 int i;
706 FlatView *view;
707
708 view = flatview_new(mr);
709
710 if (mr) {
711 render_memory_region(view, mr, int128_zero(),
712 addrrange_make(int128_zero(), int128_2_64()),
713 false, false);
714 }
715 flatview_simplify(view);
716
717 view->dispatch = address_space_dispatch_new(view);
718 for (i = 0; i < view->nr; i++) {
719 MemoryRegionSection mrs =
720 section_from_flat_range(&view->ranges[i], view);
721 flatview_add_to_dispatch(view, &mrs);
722 }
723 address_space_dispatch_compact(view->dispatch);
724 g_hash_table_replace(flat_views, mr, view);
725
726 return view;
727 }
728
729 static void address_space_add_del_ioeventfds(AddressSpace *as,
730 MemoryRegionIoeventfd *fds_new,
731 unsigned fds_new_nb,
732 MemoryRegionIoeventfd *fds_old,
733 unsigned fds_old_nb)
734 {
735 unsigned iold, inew;
736 MemoryRegionIoeventfd *fd;
737 MemoryRegionSection section;
738
739 /* Generate a symmetric difference of the old and new fd sets, adding
740 * and deleting as necessary.
741 */
742
743 iold = inew = 0;
744 while (iold < fds_old_nb || inew < fds_new_nb) {
745 if (iold < fds_old_nb
746 && (inew == fds_new_nb
747 || memory_region_ioeventfd_before(&fds_old[iold],
748 &fds_new[inew]))) {
749 fd = &fds_old[iold];
750 section = (MemoryRegionSection) {
751 .fv = address_space_to_flatview(as),
752 .offset_within_address_space = int128_get64(fd->addr.start),
753 .size = fd->addr.size,
754 };
755 MEMORY_LISTENER_CALL(as, eventfd_del, Forward, &section,
756 fd->match_data, fd->data, fd->e);
757 ++iold;
758 } else if (inew < fds_new_nb
759 && (iold == fds_old_nb
760 || memory_region_ioeventfd_before(&fds_new[inew],
761 &fds_old[iold]))) {
762 fd = &fds_new[inew];
763 section = (MemoryRegionSection) {
764 .fv = address_space_to_flatview(as),
765 .offset_within_address_space = int128_get64(fd->addr.start),
766 .size = fd->addr.size,
767 };
768 MEMORY_LISTENER_CALL(as, eventfd_add, Reverse, &section,
769 fd->match_data, fd->data, fd->e);
770 ++inew;
771 } else {
772 ++iold;
773 ++inew;
774 }
775 }
776 }
777
778 FlatView *address_space_get_flatview(AddressSpace *as)
779 {
780 FlatView *view;
781
782 rcu_read_lock();
783 do {
784 view = address_space_to_flatview(as);
785 /* If somebody has replaced as->current_map concurrently,
786 * flatview_ref returns false.
787 */
788 } while (!flatview_ref(view));
789 rcu_read_unlock();
790 return view;
791 }
792
793 static void address_space_update_ioeventfds(AddressSpace *as)
794 {
795 FlatView *view;
796 FlatRange *fr;
797 unsigned ioeventfd_nb = 0;
798 MemoryRegionIoeventfd *ioeventfds = NULL;
799 AddrRange tmp;
800 unsigned i;
801
802 view = address_space_get_flatview(as);
803 FOR_EACH_FLAT_RANGE(fr, view) {
804 for (i = 0; i < fr->mr->ioeventfd_nb; ++i) {
805 tmp = addrrange_shift(fr->mr->ioeventfds[i].addr,
806 int128_sub(fr->addr.start,
807 int128_make64(fr->offset_in_region)));
808 if (addrrange_intersects(fr->addr, tmp)) {
809 ++ioeventfd_nb;
810 ioeventfds = g_realloc(ioeventfds,
811 ioeventfd_nb * sizeof(*ioeventfds));
812 ioeventfds[ioeventfd_nb-1] = fr->mr->ioeventfds[i];
813 ioeventfds[ioeventfd_nb-1].addr = tmp;
814 }
815 }
816 }
817
818 address_space_add_del_ioeventfds(as, ioeventfds, ioeventfd_nb,
819 as->ioeventfds, as->ioeventfd_nb);
820
821 g_free(as->ioeventfds);
822 as->ioeventfds = ioeventfds;
823 as->ioeventfd_nb = ioeventfd_nb;
824 flatview_unref(view);
825 }
826
827 /*
828 * Notify the memory listeners about the coalesced IO change events of
829 * range `cmr'. Only the part that has intersection of the specified
830 * FlatRange will be sent.
831 */
832 static void flat_range_coalesced_io_notify(FlatRange *fr, AddressSpace *as,
833 CoalescedMemoryRange *cmr, bool add)
834 {
835 AddrRange tmp;
836
837 tmp = addrrange_shift(cmr->addr,
838 int128_sub(fr->addr.start,
839 int128_make64(fr->offset_in_region)));
840 if (!addrrange_intersects(tmp, fr->addr)) {
841 return;
842 }
843 tmp = addrrange_intersection(tmp, fr->addr);
844
845 if (add) {
846 MEMORY_LISTENER_UPDATE_REGION(fr, as, Forward, coalesced_io_add,
847 int128_get64(tmp.start),
848 int128_get64(tmp.size));
849 } else {
850 MEMORY_LISTENER_UPDATE_REGION(fr, as, Reverse, coalesced_io_del,
851 int128_get64(tmp.start),
852 int128_get64(tmp.size));
853 }
854 }
855
856 static void flat_range_coalesced_io_del(FlatRange *fr, AddressSpace *as)
857 {
858 CoalescedMemoryRange *cmr;
859
860 QTAILQ_FOREACH(cmr, &fr->mr->coalesced, link) {
861 flat_range_coalesced_io_notify(fr, as, cmr, false);
862 }
863 }
864
865 static void flat_range_coalesced_io_add(FlatRange *fr, AddressSpace *as)
866 {
867 MemoryRegion *mr = fr->mr;
868 CoalescedMemoryRange *cmr;
869
870 if (QTAILQ_EMPTY(&mr->coalesced)) {
871 return;
872 }
873
874 QTAILQ_FOREACH(cmr, &mr->coalesced, link) {
875 flat_range_coalesced_io_notify(fr, as, cmr, true);
876 }
877 }
878
879 static void address_space_update_topology_pass(AddressSpace *as,
880 const FlatView *old_view,
881 const FlatView *new_view,
882 bool adding)
883 {
884 unsigned iold, inew;
885 FlatRange *frold, *frnew;
886
887 /* Generate a symmetric difference of the old and new memory maps.
888 * Kill ranges in the old map, and instantiate ranges in the new map.
889 */
890 iold = inew = 0;
891 while (iold < old_view->nr || inew < new_view->nr) {
892 if (iold < old_view->nr) {
893 frold = &old_view->ranges[iold];
894 } else {
895 frold = NULL;
896 }
897 if (inew < new_view->nr) {
898 frnew = &new_view->ranges[inew];
899 } else {
900 frnew = NULL;
901 }
902
903 if (frold
904 && (!frnew
905 || int128_lt(frold->addr.start, frnew->addr.start)
906 || (int128_eq(frold->addr.start, frnew->addr.start)
907 && !flatrange_equal(frold, frnew)))) {
908 /* In old but not in new, or in both but attributes changed. */
909
910 if (!adding) {
911 flat_range_coalesced_io_del(frold, as);
912 MEMORY_LISTENER_UPDATE_REGION(frold, as, Reverse, region_del);
913 }
914
915 ++iold;
916 } else if (frold && frnew && flatrange_equal(frold, frnew)) {
917 /* In both and unchanged (except logging may have changed) */
918
919 if (adding) {
920 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_nop);
921 if (frnew->dirty_log_mask & ~frold->dirty_log_mask) {
922 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, log_start,
923 frold->dirty_log_mask,
924 frnew->dirty_log_mask);
925 }
926 if (frold->dirty_log_mask & ~frnew->dirty_log_mask) {
927 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Reverse, log_stop,
928 frold->dirty_log_mask,
929 frnew->dirty_log_mask);
930 }
931 }
932
933 ++iold;
934 ++inew;
935 } else {
936 /* In new */
937
938 if (adding) {
939 MEMORY_LISTENER_UPDATE_REGION(frnew, as, Forward, region_add);
940 flat_range_coalesced_io_add(frnew, as);
941 }
942
943 ++inew;
944 }
945 }
946 }
947
948 static void flatviews_init(void)
949 {
950 static FlatView *empty_view;
951
952 if (flat_views) {
953 return;
954 }
955
956 flat_views = g_hash_table_new_full(g_direct_hash, g_direct_equal, NULL,
957 (GDestroyNotify) flatview_unref);
958 if (!empty_view) {
959 empty_view = generate_memory_topology(NULL);
960 /* We keep it alive forever in the global variable. */
961 flatview_ref(empty_view);
962 } else {
963 g_hash_table_replace(flat_views, NULL, empty_view);
964 flatview_ref(empty_view);
965 }
966 }
967
968 static void flatviews_reset(void)
969 {
970 AddressSpace *as;
971
972 if (flat_views) {
973 g_hash_table_unref(flat_views);
974 flat_views = NULL;
975 }
976 flatviews_init();
977
978 /* Render unique FVs */
979 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
980 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
981
982 if (g_hash_table_lookup(flat_views, physmr)) {
983 continue;
984 }
985
986 generate_memory_topology(physmr);
987 }
988 }
989
990 static void address_space_set_flatview(AddressSpace *as)
991 {
992 FlatView *old_view = address_space_to_flatview(as);
993 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
994 FlatView *new_view = g_hash_table_lookup(flat_views, physmr);
995
996 assert(new_view);
997
998 if (old_view == new_view) {
999 return;
1000 }
1001
1002 if (old_view) {
1003 flatview_ref(old_view);
1004 }
1005
1006 flatview_ref(new_view);
1007
1008 if (!QTAILQ_EMPTY(&as->listeners)) {
1009 FlatView tmpview = { .nr = 0 }, *old_view2 = old_view;
1010
1011 if (!old_view2) {
1012 old_view2 = &tmpview;
1013 }
1014 address_space_update_topology_pass(as, old_view2, new_view, false);
1015 address_space_update_topology_pass(as, old_view2, new_view, true);
1016 }
1017
1018 /* Writes are protected by the BQL. */
1019 atomic_rcu_set(&as->current_map, new_view);
1020 if (old_view) {
1021 flatview_unref(old_view);
1022 }
1023
1024 /* Note that all the old MemoryRegions are still alive up to this
1025 * point. This relieves most MemoryListeners from the need to
1026 * ref/unref the MemoryRegions they get---unless they use them
1027 * outside the iothread mutex, in which case precise reference
1028 * counting is necessary.
1029 */
1030 if (old_view) {
1031 flatview_unref(old_view);
1032 }
1033 }
1034
1035 static void address_space_update_topology(AddressSpace *as)
1036 {
1037 MemoryRegion *physmr = memory_region_get_flatview_root(as->root);
1038
1039 flatviews_init();
1040 if (!g_hash_table_lookup(flat_views, physmr)) {
1041 generate_memory_topology(physmr);
1042 }
1043 address_space_set_flatview(as);
1044 }
1045
1046 void memory_region_transaction_begin(void)
1047 {
1048 qemu_flush_coalesced_mmio_buffer();
1049 ++memory_region_transaction_depth;
1050 }
1051
1052 void memory_region_transaction_commit(void)
1053 {
1054 AddressSpace *as;
1055
1056 assert(memory_region_transaction_depth);
1057 assert(qemu_mutex_iothread_locked());
1058
1059 --memory_region_transaction_depth;
1060 if (!memory_region_transaction_depth) {
1061 if (memory_region_update_pending) {
1062 flatviews_reset();
1063
1064 MEMORY_LISTENER_CALL_GLOBAL(begin, Forward);
1065
1066 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1067 address_space_set_flatview(as);
1068 address_space_update_ioeventfds(as);
1069 }
1070 memory_region_update_pending = false;
1071 ioeventfd_update_pending = false;
1072 MEMORY_LISTENER_CALL_GLOBAL(commit, Forward);
1073 } else if (ioeventfd_update_pending) {
1074 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
1075 address_space_update_ioeventfds(as);
1076 }
1077 ioeventfd_update_pending = false;
1078 }
1079 }
1080 }
1081
1082 static void memory_region_destructor_none(MemoryRegion *mr)
1083 {
1084 }
1085
1086 static void memory_region_destructor_ram(MemoryRegion *mr)
1087 {
1088 qemu_ram_free(mr->ram_block);
1089 }
1090
1091 static bool memory_region_need_escape(char c)
1092 {
1093 return c == '/' || c == '[' || c == '\\' || c == ']';
1094 }
1095
1096 static char *memory_region_escape_name(const char *name)
1097 {
1098 const char *p;
1099 char *escaped, *q;
1100 uint8_t c;
1101 size_t bytes = 0;
1102
1103 for (p = name; *p; p++) {
1104 bytes += memory_region_need_escape(*p) ? 4 : 1;
1105 }
1106 if (bytes == p - name) {
1107 return g_memdup(name, bytes + 1);
1108 }
1109
1110 escaped = g_malloc(bytes + 1);
1111 for (p = name, q = escaped; *p; p++) {
1112 c = *p;
1113 if (unlikely(memory_region_need_escape(c))) {
1114 *q++ = '\\';
1115 *q++ = 'x';
1116 *q++ = "0123456789abcdef"[c >> 4];
1117 c = "0123456789abcdef"[c & 15];
1118 }
1119 *q++ = c;
1120 }
1121 *q = 0;
1122 return escaped;
1123 }
1124
1125 static void memory_region_do_init(MemoryRegion *mr,
1126 Object *owner,
1127 const char *name,
1128 uint64_t size)
1129 {
1130 mr->size = int128_make64(size);
1131 if (size == UINT64_MAX) {
1132 mr->size = int128_2_64();
1133 }
1134 mr->name = g_strdup(name);
1135 mr->owner = owner;
1136 mr->ram_block = NULL;
1137
1138 if (name) {
1139 char *escaped_name = memory_region_escape_name(name);
1140 char *name_array = g_strdup_printf("%s[*]", escaped_name);
1141
1142 if (!owner) {
1143 owner = container_get(qdev_get_machine(), "/unattached");
1144 }
1145
1146 object_property_add_child(owner, name_array, OBJECT(mr), &error_abort);
1147 object_unref(OBJECT(mr));
1148 g_free(name_array);
1149 g_free(escaped_name);
1150 }
1151 }
1152
1153 void memory_region_init(MemoryRegion *mr,
1154 Object *owner,
1155 const char *name,
1156 uint64_t size)
1157 {
1158 object_initialize(mr, sizeof(*mr), TYPE_MEMORY_REGION);
1159 memory_region_do_init(mr, owner, name, size);
1160 }
1161
1162 static void memory_region_get_addr(Object *obj, Visitor *v, const char *name,
1163 void *opaque, Error **errp)
1164 {
1165 MemoryRegion *mr = MEMORY_REGION(obj);
1166 uint64_t value = mr->addr;
1167
1168 visit_type_uint64(v, name, &value, errp);
1169 }
1170
1171 static void memory_region_get_container(Object *obj, Visitor *v,
1172 const char *name, void *opaque,
1173 Error **errp)
1174 {
1175 MemoryRegion *mr = MEMORY_REGION(obj);
1176 gchar *path = (gchar *)"";
1177
1178 if (mr->container) {
1179 path = object_get_canonical_path(OBJECT(mr->container));
1180 }
1181 visit_type_str(v, name, &path, errp);
1182 if (mr->container) {
1183 g_free(path);
1184 }
1185 }
1186
1187 static Object *memory_region_resolve_container(Object *obj, void *opaque,
1188 const char *part)
1189 {
1190 MemoryRegion *mr = MEMORY_REGION(obj);
1191
1192 return OBJECT(mr->container);
1193 }
1194
1195 static void memory_region_get_priority(Object *obj, Visitor *v,
1196 const char *name, void *opaque,
1197 Error **errp)
1198 {
1199 MemoryRegion *mr = MEMORY_REGION(obj);
1200 int32_t value = mr->priority;
1201
1202 visit_type_int32(v, name, &value, errp);
1203 }
1204
1205 static void memory_region_get_size(Object *obj, Visitor *v, const char *name,
1206 void *opaque, Error **errp)
1207 {
1208 MemoryRegion *mr = MEMORY_REGION(obj);
1209 uint64_t value = memory_region_size(mr);
1210
1211 visit_type_uint64(v, name, &value, errp);
1212 }
1213
1214 static void memory_region_initfn(Object *obj)
1215 {
1216 MemoryRegion *mr = MEMORY_REGION(obj);
1217 ObjectProperty *op;
1218
1219 mr->ops = &unassigned_mem_ops;
1220 mr->enabled = true;
1221 mr->romd_mode = true;
1222 mr->global_locking = true;
1223 mr->destructor = memory_region_destructor_none;
1224 QTAILQ_INIT(&mr->subregions);
1225 QTAILQ_INIT(&mr->coalesced);
1226
1227 op = object_property_add(OBJECT(mr), "container",
1228 "link<" TYPE_MEMORY_REGION ">",
1229 memory_region_get_container,
1230 NULL, /* memory_region_set_container */
1231 NULL, NULL, &error_abort);
1232 op->resolve = memory_region_resolve_container;
1233
1234 object_property_add(OBJECT(mr), "addr", "uint64",
1235 memory_region_get_addr,
1236 NULL, /* memory_region_set_addr */
1237 NULL, NULL, &error_abort);
1238 object_property_add(OBJECT(mr), "priority", "uint32",
1239 memory_region_get_priority,
1240 NULL, /* memory_region_set_priority */
1241 NULL, NULL, &error_abort);
1242 object_property_add(OBJECT(mr), "size", "uint64",
1243 memory_region_get_size,
1244 NULL, /* memory_region_set_size, */
1245 NULL, NULL, &error_abort);
1246 }
1247
1248 static void iommu_memory_region_initfn(Object *obj)
1249 {
1250 MemoryRegion *mr = MEMORY_REGION(obj);
1251
1252 mr->is_iommu = true;
1253 }
1254
1255 static uint64_t unassigned_mem_read(void *opaque, hwaddr addr,
1256 unsigned size)
1257 {
1258 #ifdef DEBUG_UNASSIGNED
1259 printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
1260 #endif
1261 if (current_cpu != NULL) {
1262 bool is_exec = current_cpu->mem_io_access_type == MMU_INST_FETCH;
1263 cpu_unassigned_access(current_cpu, addr, false, is_exec, 0, size);
1264 }
1265 return 0;
1266 }
1267
1268 static void unassigned_mem_write(void *opaque, hwaddr addr,
1269 uint64_t val, unsigned size)
1270 {
1271 #ifdef DEBUG_UNASSIGNED
1272 printf("Unassigned mem write " TARGET_FMT_plx " = 0x%"PRIx64"\n", addr, val);
1273 #endif
1274 if (current_cpu != NULL) {
1275 cpu_unassigned_access(current_cpu, addr, true, false, 0, size);
1276 }
1277 }
1278
1279 static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
1280 unsigned size, bool is_write,
1281 MemTxAttrs attrs)
1282 {
1283 return false;
1284 }
1285
1286 const MemoryRegionOps unassigned_mem_ops = {
1287 .valid.accepts = unassigned_mem_accepts,
1288 .endianness = DEVICE_NATIVE_ENDIAN,
1289 };
1290
1291 static uint64_t memory_region_ram_device_read(void *opaque,
1292 hwaddr addr, unsigned size)
1293 {
1294 MemoryRegion *mr = opaque;
1295 uint64_t data = (uint64_t)~0;
1296
1297 switch (size) {
1298 case 1:
1299 data = *(uint8_t *)(mr->ram_block->host + addr);
1300 break;
1301 case 2:
1302 data = *(uint16_t *)(mr->ram_block->host + addr);
1303 break;
1304 case 4:
1305 data = *(uint32_t *)(mr->ram_block->host + addr);
1306 break;
1307 case 8:
1308 data = *(uint64_t *)(mr->ram_block->host + addr);
1309 break;
1310 }
1311
1312 trace_memory_region_ram_device_read(get_cpu_index(), mr, addr, data, size);
1313
1314 return data;
1315 }
1316
1317 static void memory_region_ram_device_write(void *opaque, hwaddr addr,
1318 uint64_t data, unsigned size)
1319 {
1320 MemoryRegion *mr = opaque;
1321
1322 trace_memory_region_ram_device_write(get_cpu_index(), mr, addr, data, size);
1323
1324 switch (size) {
1325 case 1:
1326 *(uint8_t *)(mr->ram_block->host + addr) = (uint8_t)data;
1327 break;
1328 case 2:
1329 *(uint16_t *)(mr->ram_block->host + addr) = (uint16_t)data;
1330 break;
1331 case 4:
1332 *(uint32_t *)(mr->ram_block->host + addr) = (uint32_t)data;
1333 break;
1334 case 8:
1335 *(uint64_t *)(mr->ram_block->host + addr) = data;
1336 break;
1337 }
1338 }
1339
1340 static const MemoryRegionOps ram_device_mem_ops = {
1341 .read = memory_region_ram_device_read,
1342 .write = memory_region_ram_device_write,
1343 .endianness = DEVICE_HOST_ENDIAN,
1344 .valid = {
1345 .min_access_size = 1,
1346 .max_access_size = 8,
1347 .unaligned = true,
1348 },
1349 .impl = {
1350 .min_access_size = 1,
1351 .max_access_size = 8,
1352 .unaligned = true,
1353 },
1354 };
1355
1356 bool memory_region_access_valid(MemoryRegion *mr,
1357 hwaddr addr,
1358 unsigned size,
1359 bool is_write,
1360 MemTxAttrs attrs)
1361 {
1362 int access_size_min, access_size_max;
1363 int access_size, i;
1364
1365 if (!mr->ops->valid.unaligned && (addr & (size - 1))) {
1366 return false;
1367 }
1368
1369 if (!mr->ops->valid.accepts) {
1370 return true;
1371 }
1372
1373 access_size_min = mr->ops->valid.min_access_size;
1374 if (!mr->ops->valid.min_access_size) {
1375 access_size_min = 1;
1376 }
1377
1378 access_size_max = mr->ops->valid.max_access_size;
1379 if (!mr->ops->valid.max_access_size) {
1380 access_size_max = 4;
1381 }
1382
1383 access_size = MAX(MIN(size, access_size_max), access_size_min);
1384 for (i = 0; i < size; i += access_size) {
1385 if (!mr->ops->valid.accepts(mr->opaque, addr + i, access_size,
1386 is_write, attrs)) {
1387 return false;
1388 }
1389 }
1390
1391 return true;
1392 }
1393
1394 static MemTxResult memory_region_dispatch_read1(MemoryRegion *mr,
1395 hwaddr addr,
1396 uint64_t *pval,
1397 unsigned size,
1398 MemTxAttrs attrs)
1399 {
1400 *pval = 0;
1401
1402 if (mr->ops->read) {
1403 return access_with_adjusted_size(addr, pval, size,
1404 mr->ops->impl.min_access_size,
1405 mr->ops->impl.max_access_size,
1406 memory_region_read_accessor,
1407 mr, attrs);
1408 } else {
1409 return access_with_adjusted_size(addr, pval, size,
1410 mr->ops->impl.min_access_size,
1411 mr->ops->impl.max_access_size,
1412 memory_region_read_with_attrs_accessor,
1413 mr, attrs);
1414 }
1415 }
1416
1417 MemTxResult memory_region_dispatch_read(MemoryRegion *mr,
1418 hwaddr addr,
1419 uint64_t *pval,
1420 MemOp op,
1421 MemTxAttrs attrs)
1422 {
1423 unsigned size = memop_size(op);
1424 MemTxResult r;
1425
1426 if (!memory_region_access_valid(mr, addr, size, false, attrs)) {
1427 *pval = unassigned_mem_read(mr, addr, size);
1428 return MEMTX_DECODE_ERROR;
1429 }
1430
1431 r = memory_region_dispatch_read1(mr, addr, pval, size, attrs);
1432 adjust_endianness(mr, pval, op);
1433 return r;
1434 }
1435
1436 /* Return true if an eventfd was signalled */
1437 static bool memory_region_dispatch_write_eventfds(MemoryRegion *mr,
1438 hwaddr addr,
1439 uint64_t data,
1440 unsigned size,
1441 MemTxAttrs attrs)
1442 {
1443 MemoryRegionIoeventfd ioeventfd = {
1444 .addr = addrrange_make(int128_make64(addr), int128_make64(size)),
1445 .data = data,
1446 };
1447 unsigned i;
1448
1449 for (i = 0; i < mr->ioeventfd_nb; i++) {
1450 ioeventfd.match_data = mr->ioeventfds[i].match_data;
1451 ioeventfd.e = mr->ioeventfds[i].e;
1452
1453 if (memory_region_ioeventfd_equal(&ioeventfd, &mr->ioeventfds[i])) {
1454 event_notifier_set(ioeventfd.e);
1455 return true;
1456 }
1457 }
1458
1459 return false;
1460 }
1461
1462 MemTxResult memory_region_dispatch_write(MemoryRegion *mr,
1463 hwaddr addr,
1464 uint64_t data,
1465 MemOp op,
1466 MemTxAttrs attrs)
1467 {
1468 unsigned size = memop_size(op);
1469
1470 if (!memory_region_access_valid(mr, addr, size, true, attrs)) {
1471 unassigned_mem_write(mr, addr, data, size);
1472 return MEMTX_DECODE_ERROR;
1473 }
1474
1475 adjust_endianness(mr, &data, op);
1476
1477 if ((!kvm_eventfds_enabled()) &&
1478 memory_region_dispatch_write_eventfds(mr, addr, data, size, attrs)) {
1479 return MEMTX_OK;
1480 }
1481
1482 if (mr->ops->write) {
1483 return access_with_adjusted_size(addr, &data, size,
1484 mr->ops->impl.min_access_size,
1485 mr->ops->impl.max_access_size,
1486 memory_region_write_accessor, mr,
1487 attrs);
1488 } else {
1489 return
1490 access_with_adjusted_size(addr, &data, size,
1491 mr->ops->impl.min_access_size,
1492 mr->ops->impl.max_access_size,
1493 memory_region_write_with_attrs_accessor,
1494 mr, attrs);
1495 }
1496 }
1497
1498 void memory_region_init_io(MemoryRegion *mr,
1499 Object *owner,
1500 const MemoryRegionOps *ops,
1501 void *opaque,
1502 const char *name,
1503 uint64_t size)
1504 {
1505 memory_region_init(mr, owner, name, size);
1506 mr->ops = ops ? ops : &unassigned_mem_ops;
1507 mr->opaque = opaque;
1508 mr->terminates = true;
1509 }
1510
1511 void memory_region_init_ram_nomigrate(MemoryRegion *mr,
1512 Object *owner,
1513 const char *name,
1514 uint64_t size,
1515 Error **errp)
1516 {
1517 memory_region_init_ram_shared_nomigrate(mr, owner, name, size, false, errp);
1518 }
1519
1520 void memory_region_init_ram_shared_nomigrate(MemoryRegion *mr,
1521 Object *owner,
1522 const char *name,
1523 uint64_t size,
1524 bool share,
1525 Error **errp)
1526 {
1527 Error *err = NULL;
1528 memory_region_init(mr, owner, name, size);
1529 mr->ram = true;
1530 mr->terminates = true;
1531 mr->destructor = memory_region_destructor_ram;
1532 mr->ram_block = qemu_ram_alloc(size, share, mr, &err);
1533 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1534 if (err) {
1535 mr->size = int128_zero();
1536 object_unparent(OBJECT(mr));
1537 error_propagate(errp, err);
1538 }
1539 }
1540
1541 void memory_region_init_resizeable_ram(MemoryRegion *mr,
1542 Object *owner,
1543 const char *name,
1544 uint64_t size,
1545 uint64_t max_size,
1546 void (*resized)(const char*,
1547 uint64_t length,
1548 void *host),
1549 Error **errp)
1550 {
1551 Error *err = NULL;
1552 memory_region_init(mr, owner, name, size);
1553 mr->ram = true;
1554 mr->terminates = true;
1555 mr->destructor = memory_region_destructor_ram;
1556 mr->ram_block = qemu_ram_alloc_resizeable(size, max_size, resized,
1557 mr, &err);
1558 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1559 if (err) {
1560 mr->size = int128_zero();
1561 object_unparent(OBJECT(mr));
1562 error_propagate(errp, err);
1563 }
1564 }
1565
1566 #ifdef CONFIG_POSIX
1567 void memory_region_init_ram_from_file(MemoryRegion *mr,
1568 struct Object *owner,
1569 const char *name,
1570 uint64_t size,
1571 uint64_t align,
1572 uint32_t ram_flags,
1573 const char *path,
1574 Error **errp)
1575 {
1576 Error *err = NULL;
1577 memory_region_init(mr, owner, name, size);
1578 mr->ram = true;
1579 mr->terminates = true;
1580 mr->destructor = memory_region_destructor_ram;
1581 mr->align = align;
1582 mr->ram_block = qemu_ram_alloc_from_file(size, mr, ram_flags, path, &err);
1583 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1584 if (err) {
1585 mr->size = int128_zero();
1586 object_unparent(OBJECT(mr));
1587 error_propagate(errp, err);
1588 }
1589 }
1590
1591 void memory_region_init_ram_from_fd(MemoryRegion *mr,
1592 struct Object *owner,
1593 const char *name,
1594 uint64_t size,
1595 bool share,
1596 int fd,
1597 Error **errp)
1598 {
1599 Error *err = NULL;
1600 memory_region_init(mr, owner, name, size);
1601 mr->ram = true;
1602 mr->terminates = true;
1603 mr->destructor = memory_region_destructor_ram;
1604 mr->ram_block = qemu_ram_alloc_from_fd(size, mr,
1605 share ? RAM_SHARED : 0,
1606 fd, &err);
1607 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1608 if (err) {
1609 mr->size = int128_zero();
1610 object_unparent(OBJECT(mr));
1611 error_propagate(errp, err);
1612 }
1613 }
1614 #endif
1615
1616 void memory_region_init_ram_ptr(MemoryRegion *mr,
1617 Object *owner,
1618 const char *name,
1619 uint64_t size,
1620 void *ptr)
1621 {
1622 memory_region_init(mr, owner, name, size);
1623 mr->ram = true;
1624 mr->terminates = true;
1625 mr->destructor = memory_region_destructor_ram;
1626 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1627
1628 /* qemu_ram_alloc_from_ptr cannot fail with ptr != NULL. */
1629 assert(ptr != NULL);
1630 mr->ram_block = qemu_ram_alloc_from_ptr(size, ptr, mr, &error_fatal);
1631 }
1632
1633 void memory_region_init_ram_device_ptr(MemoryRegion *mr,
1634 Object *owner,
1635 const char *name,
1636 uint64_t size,
1637 void *ptr)
1638 {
1639 memory_region_init(mr, owner, name, size);
1640 mr->ram = true;
1641 mr->terminates = true;
1642 mr->ram_device = true;
1643 mr->ops = &ram_device_mem_ops;
1644 mr->opaque = mr;
1645 mr->destructor = memory_region_destructor_ram;
1646 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1647 /* qemu_ram_alloc_from_ptr cannot fail with ptr != NULL. */
1648 assert(ptr != NULL);
1649 mr->ram_block = qemu_ram_alloc_from_ptr(size, ptr, mr, &error_fatal);
1650 }
1651
1652 void memory_region_init_alias(MemoryRegion *mr,
1653 Object *owner,
1654 const char *name,
1655 MemoryRegion *orig,
1656 hwaddr offset,
1657 uint64_t size)
1658 {
1659 memory_region_init(mr, owner, name, size);
1660 mr->alias = orig;
1661 mr->alias_offset = offset;
1662 }
1663
1664 void memory_region_init_rom_nomigrate(MemoryRegion *mr,
1665 struct Object *owner,
1666 const char *name,
1667 uint64_t size,
1668 Error **errp)
1669 {
1670 Error *err = NULL;
1671 memory_region_init(mr, owner, name, size);
1672 mr->ram = true;
1673 mr->readonly = true;
1674 mr->terminates = true;
1675 mr->destructor = memory_region_destructor_ram;
1676 mr->ram_block = qemu_ram_alloc(size, false, mr, &err);
1677 mr->dirty_log_mask = tcg_enabled() ? (1 << DIRTY_MEMORY_CODE) : 0;
1678 if (err) {
1679 mr->size = int128_zero();
1680 object_unparent(OBJECT(mr));
1681 error_propagate(errp, err);
1682 }
1683 }
1684
1685 void memory_region_init_rom_device_nomigrate(MemoryRegion *mr,
1686 Object *owner,
1687 const MemoryRegionOps *ops,
1688 void *opaque,
1689 const char *name,
1690 uint64_t size,
1691 Error **errp)
1692 {
1693 Error *err = NULL;
1694 assert(ops);
1695 memory_region_init(mr, owner, name, size);
1696 mr->ops = ops;
1697 mr->opaque = opaque;
1698 mr->terminates = true;
1699 mr->rom_device = true;
1700 mr->destructor = memory_region_destructor_ram;
1701 mr->ram_block = qemu_ram_alloc(size, false, mr, &err);
1702 if (err) {
1703 mr->size = int128_zero();
1704 object_unparent(OBJECT(mr));
1705 error_propagate(errp, err);
1706 }
1707 }
1708
1709 void memory_region_init_iommu(void *_iommu_mr,
1710 size_t instance_size,
1711 const char *mrtypename,
1712 Object *owner,
1713 const char *name,
1714 uint64_t size)
1715 {
1716 struct IOMMUMemoryRegion *iommu_mr;
1717 struct MemoryRegion *mr;
1718
1719 object_initialize(_iommu_mr, instance_size, mrtypename);
1720 mr = MEMORY_REGION(_iommu_mr);
1721 memory_region_do_init(mr, owner, name, size);
1722 iommu_mr = IOMMU_MEMORY_REGION(mr);
1723 mr->terminates = true; /* then re-forwards */
1724 QLIST_INIT(&iommu_mr->iommu_notify);
1725 iommu_mr->iommu_notify_flags = IOMMU_NOTIFIER_NONE;
1726 }
1727
1728 static void memory_region_finalize(Object *obj)
1729 {
1730 MemoryRegion *mr = MEMORY_REGION(obj);
1731
1732 assert(!mr->container);
1733
1734 /* We know the region is not visible in any address space (it
1735 * does not have a container and cannot be a root either because
1736 * it has no references, so we can blindly clear mr->enabled.
1737 * memory_region_set_enabled instead could trigger a transaction
1738 * and cause an infinite loop.
1739 */
1740 mr->enabled = false;
1741 memory_region_transaction_begin();
1742 while (!QTAILQ_EMPTY(&mr->subregions)) {
1743 MemoryRegion *subregion = QTAILQ_FIRST(&mr->subregions);
1744 memory_region_del_subregion(mr, subregion);
1745 }
1746 memory_region_transaction_commit();
1747
1748 mr->destructor(mr);
1749 memory_region_clear_coalescing(mr);
1750 g_free((char *)mr->name);
1751 g_free(mr->ioeventfds);
1752 }
1753
1754 Object *memory_region_owner(MemoryRegion *mr)
1755 {
1756 Object *obj = OBJECT(mr);
1757 return obj->parent;
1758 }
1759
1760 void memory_region_ref(MemoryRegion *mr)
1761 {
1762 /* MMIO callbacks most likely will access data that belongs
1763 * to the owner, hence the need to ref/unref the owner whenever
1764 * the memory region is in use.
1765 *
1766 * The memory region is a child of its owner. As long as the
1767 * owner doesn't call unparent itself on the memory region,
1768 * ref-ing the owner will also keep the memory region alive.
1769 * Memory regions without an owner are supposed to never go away;
1770 * we do not ref/unref them because it slows down DMA sensibly.
1771 */
1772 if (mr && mr->owner) {
1773 object_ref(mr->owner);
1774 }
1775 }
1776
1777 void memory_region_unref(MemoryRegion *mr)
1778 {
1779 if (mr && mr->owner) {
1780 object_unref(mr->owner);
1781 }
1782 }
1783
1784 uint64_t memory_region_size(MemoryRegion *mr)
1785 {
1786 if (int128_eq(mr->size, int128_2_64())) {
1787 return UINT64_MAX;
1788 }
1789 return int128_get64(mr->size);
1790 }
1791
1792 const char *memory_region_name(const MemoryRegion *mr)
1793 {
1794 if (!mr->name) {
1795 ((MemoryRegion *)mr)->name =
1796 object_get_canonical_path_component(OBJECT(mr));
1797 }
1798 return mr->name;
1799 }
1800
1801 bool memory_region_is_ram_device(MemoryRegion *mr)
1802 {
1803 return mr->ram_device;
1804 }
1805
1806 uint8_t memory_region_get_dirty_log_mask(MemoryRegion *mr)
1807 {
1808 uint8_t mask = mr->dirty_log_mask;
1809 if (global_dirty_log && mr->ram_block) {
1810 mask |= (1 << DIRTY_MEMORY_MIGRATION);
1811 }
1812 return mask;
1813 }
1814
1815 bool memory_region_is_logging(MemoryRegion *mr, uint8_t client)
1816 {
1817 return memory_region_get_dirty_log_mask(mr) & (1 << client);
1818 }
1819
1820 static int memory_region_update_iommu_notify_flags(IOMMUMemoryRegion *iommu_mr,
1821 Error **errp)
1822 {
1823 IOMMUNotifierFlag flags = IOMMU_NOTIFIER_NONE;
1824 IOMMUNotifier *iommu_notifier;
1825 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1826 int ret = 0;
1827
1828 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
1829 flags |= iommu_notifier->notifier_flags;
1830 }
1831
1832 if (flags != iommu_mr->iommu_notify_flags && imrc->notify_flag_changed) {
1833 ret = imrc->notify_flag_changed(iommu_mr,
1834 iommu_mr->iommu_notify_flags,
1835 flags, errp);
1836 }
1837
1838 if (!ret) {
1839 iommu_mr->iommu_notify_flags = flags;
1840 }
1841 return ret;
1842 }
1843
1844 int memory_region_register_iommu_notifier(MemoryRegion *mr,
1845 IOMMUNotifier *n, Error **errp)
1846 {
1847 IOMMUMemoryRegion *iommu_mr;
1848 int ret;
1849
1850 if (mr->alias) {
1851 return memory_region_register_iommu_notifier(mr->alias, n, errp);
1852 }
1853
1854 /* We need to register for at least one bitfield */
1855 iommu_mr = IOMMU_MEMORY_REGION(mr);
1856 assert(n->notifier_flags != IOMMU_NOTIFIER_NONE);
1857 assert(n->start <= n->end);
1858 assert(n->iommu_idx >= 0 &&
1859 n->iommu_idx < memory_region_iommu_num_indexes(iommu_mr));
1860
1861 QLIST_INSERT_HEAD(&iommu_mr->iommu_notify, n, node);
1862 ret = memory_region_update_iommu_notify_flags(iommu_mr, errp);
1863 if (ret) {
1864 QLIST_REMOVE(n, node);
1865 }
1866 return ret;
1867 }
1868
1869 uint64_t memory_region_iommu_get_min_page_size(IOMMUMemoryRegion *iommu_mr)
1870 {
1871 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1872
1873 if (imrc->get_min_page_size) {
1874 return imrc->get_min_page_size(iommu_mr);
1875 }
1876 return TARGET_PAGE_SIZE;
1877 }
1878
1879 void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n)
1880 {
1881 MemoryRegion *mr = MEMORY_REGION(iommu_mr);
1882 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1883 hwaddr addr, granularity;
1884 IOMMUTLBEntry iotlb;
1885
1886 /* If the IOMMU has its own replay callback, override */
1887 if (imrc->replay) {
1888 imrc->replay(iommu_mr, n);
1889 return;
1890 }
1891
1892 granularity = memory_region_iommu_get_min_page_size(iommu_mr);
1893
1894 for (addr = 0; addr < memory_region_size(mr); addr += granularity) {
1895 iotlb = imrc->translate(iommu_mr, addr, IOMMU_NONE, n->iommu_idx);
1896 if (iotlb.perm != IOMMU_NONE) {
1897 n->notify(n, &iotlb);
1898 }
1899
1900 /* if (2^64 - MR size) < granularity, it's possible to get an
1901 * infinite loop here. This should catch such a wraparound */
1902 if ((addr + granularity) < addr) {
1903 break;
1904 }
1905 }
1906 }
1907
1908 void memory_region_unregister_iommu_notifier(MemoryRegion *mr,
1909 IOMMUNotifier *n)
1910 {
1911 IOMMUMemoryRegion *iommu_mr;
1912
1913 if (mr->alias) {
1914 memory_region_unregister_iommu_notifier(mr->alias, n);
1915 return;
1916 }
1917 QLIST_REMOVE(n, node);
1918 iommu_mr = IOMMU_MEMORY_REGION(mr);
1919 memory_region_update_iommu_notify_flags(iommu_mr, NULL);
1920 }
1921
1922 void memory_region_notify_one(IOMMUNotifier *notifier,
1923 IOMMUTLBEntry *entry)
1924 {
1925 IOMMUNotifierFlag request_flags;
1926 hwaddr entry_end = entry->iova + entry->addr_mask;
1927
1928 /*
1929 * Skip the notification if the notification does not overlap
1930 * with registered range.
1931 */
1932 if (notifier->start > entry_end || notifier->end < entry->iova) {
1933 return;
1934 }
1935
1936 assert(entry->iova >= notifier->start && entry_end <= notifier->end);
1937
1938 if (entry->perm & IOMMU_RW) {
1939 request_flags = IOMMU_NOTIFIER_MAP;
1940 } else {
1941 request_flags = IOMMU_NOTIFIER_UNMAP;
1942 }
1943
1944 if (notifier->notifier_flags & request_flags) {
1945 notifier->notify(notifier, entry);
1946 }
1947 }
1948
1949 void memory_region_notify_iommu(IOMMUMemoryRegion *iommu_mr,
1950 int iommu_idx,
1951 IOMMUTLBEntry entry)
1952 {
1953 IOMMUNotifier *iommu_notifier;
1954
1955 assert(memory_region_is_iommu(MEMORY_REGION(iommu_mr)));
1956
1957 IOMMU_NOTIFIER_FOREACH(iommu_notifier, iommu_mr) {
1958 if (iommu_notifier->iommu_idx == iommu_idx) {
1959 memory_region_notify_one(iommu_notifier, &entry);
1960 }
1961 }
1962 }
1963
1964 int memory_region_iommu_get_attr(IOMMUMemoryRegion *iommu_mr,
1965 enum IOMMUMemoryRegionAttr attr,
1966 void *data)
1967 {
1968 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1969
1970 if (!imrc->get_attr) {
1971 return -EINVAL;
1972 }
1973
1974 return imrc->get_attr(iommu_mr, attr, data);
1975 }
1976
1977 int memory_region_iommu_attrs_to_index(IOMMUMemoryRegion *iommu_mr,
1978 MemTxAttrs attrs)
1979 {
1980 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1981
1982 if (!imrc->attrs_to_index) {
1983 return 0;
1984 }
1985
1986 return imrc->attrs_to_index(iommu_mr, attrs);
1987 }
1988
1989 int memory_region_iommu_num_indexes(IOMMUMemoryRegion *iommu_mr)
1990 {
1991 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_GET_CLASS(iommu_mr);
1992
1993 if (!imrc->num_indexes) {
1994 return 1;
1995 }
1996
1997 return imrc->num_indexes(iommu_mr);
1998 }
1999
2000 void memory_region_set_log(MemoryRegion *mr, bool log, unsigned client)
2001 {
2002 uint8_t mask = 1 << client;
2003 uint8_t old_logging;
2004
2005 assert(client == DIRTY_MEMORY_VGA);
2006 old_logging = mr->vga_logging_count;
2007 mr->vga_logging_count += log ? 1 : -1;
2008 if (!!old_logging == !!mr->vga_logging_count) {
2009 return;
2010 }
2011
2012 memory_region_transaction_begin();
2013 mr->dirty_log_mask = (mr->dirty_log_mask & ~mask) | (log * mask);
2014 memory_region_update_pending |= mr->enabled;
2015 memory_region_transaction_commit();
2016 }
2017
2018 void memory_region_set_dirty(MemoryRegion *mr, hwaddr addr,
2019 hwaddr size)
2020 {
2021 assert(mr->ram_block);
2022 cpu_physical_memory_set_dirty_range(memory_region_get_ram_addr(mr) + addr,
2023 size,
2024 memory_region_get_dirty_log_mask(mr));
2025 }
2026
2027 static void memory_region_sync_dirty_bitmap(MemoryRegion *mr)
2028 {
2029 MemoryListener *listener;
2030 AddressSpace *as;
2031 FlatView *view;
2032 FlatRange *fr;
2033
2034 /* If the same address space has multiple log_sync listeners, we
2035 * visit that address space's FlatView multiple times. But because
2036 * log_sync listeners are rare, it's still cheaper than walking each
2037 * address space once.
2038 */
2039 QTAILQ_FOREACH(listener, &memory_listeners, link) {
2040 if (!listener->log_sync) {
2041 continue;
2042 }
2043 as = listener->address_space;
2044 view = address_space_get_flatview(as);
2045 FOR_EACH_FLAT_RANGE(fr, view) {
2046 if (fr->dirty_log_mask && (!mr || fr->mr == mr)) {
2047 MemoryRegionSection mrs = section_from_flat_range(fr, view);
2048 listener->log_sync(listener, &mrs);
2049 }
2050 }
2051 flatview_unref(view);
2052 }
2053 }
2054
2055 void memory_region_clear_dirty_bitmap(MemoryRegion *mr, hwaddr start,
2056 hwaddr len)
2057 {
2058 MemoryRegionSection mrs;
2059 MemoryListener *listener;
2060 AddressSpace *as;
2061 FlatView *view;
2062 FlatRange *fr;
2063 hwaddr sec_start, sec_end, sec_size;
2064
2065 QTAILQ_FOREACH(listener, &memory_listeners, link) {
2066 if (!listener->log_clear) {
2067 continue;
2068 }
2069 as = listener->address_space;
2070 view = address_space_get_flatview(as);
2071 FOR_EACH_FLAT_RANGE(fr, view) {
2072 if (!fr->dirty_log_mask || fr->mr != mr) {
2073 /*
2074 * Clear dirty bitmap operation only applies to those
2075 * regions whose dirty logging is at least enabled
2076 */
2077 continue;
2078 }
2079
2080 mrs = section_from_flat_range(fr, view);
2081
2082 sec_start = MAX(mrs.offset_within_region, start);
2083 sec_end = mrs.offset_within_region + int128_get64(mrs.size);
2084 sec_end = MIN(sec_end, start + len);
2085
2086 if (sec_start >= sec_end) {
2087 /*
2088 * If this memory region section has no intersection
2089 * with the requested range, skip.
2090 */
2091 continue;
2092 }
2093
2094 /* Valid case; shrink the section if needed */
2095 mrs.offset_within_address_space +=
2096 sec_start - mrs.offset_within_region;
2097 mrs.offset_within_region = sec_start;
2098 sec_size = sec_end - sec_start;
2099 mrs.size = int128_make64(sec_size);
2100 listener->log_clear(listener, &mrs);
2101 }
2102 flatview_unref(view);
2103 }
2104 }
2105
2106 DirtyBitmapSnapshot *memory_region_snapshot_and_clear_dirty(MemoryRegion *mr,
2107 hwaddr addr,
2108 hwaddr size,
2109 unsigned client)
2110 {
2111 DirtyBitmapSnapshot *snapshot;
2112 assert(mr->ram_block);
2113 memory_region_sync_dirty_bitmap(mr);
2114 snapshot = cpu_physical_memory_snapshot_and_clear_dirty(mr, addr, size, client);
2115 memory_global_after_dirty_log_sync();
2116 return snapshot;
2117 }
2118
2119 bool memory_region_snapshot_get_dirty(MemoryRegion *mr, DirtyBitmapSnapshot *snap,
2120 hwaddr addr, hwaddr size)
2121 {
2122 assert(mr->ram_block);
2123 return cpu_physical_memory_snapshot_get_dirty(snap,
2124 memory_region_get_ram_addr(mr) + addr, size);
2125 }
2126
2127 void memory_region_set_readonly(MemoryRegion *mr, bool readonly)
2128 {
2129 if (mr->readonly != readonly) {
2130 memory_region_transaction_begin();
2131 mr->readonly = readonly;
2132 memory_region_update_pending |= mr->enabled;
2133 memory_region_transaction_commit();
2134 }
2135 }
2136
2137 void memory_region_set_nonvolatile(MemoryRegion *mr, bool nonvolatile)
2138 {
2139 if (mr->nonvolatile != nonvolatile) {
2140 memory_region_transaction_begin();
2141 mr->nonvolatile = nonvolatile;
2142 memory_region_update_pending |= mr->enabled;
2143 memory_region_transaction_commit();
2144 }
2145 }
2146
2147 void memory_region_rom_device_set_romd(MemoryRegion *mr, bool romd_mode)
2148 {
2149 if (mr->romd_mode != romd_mode) {
2150 memory_region_transaction_begin();
2151 mr->romd_mode = romd_mode;
2152 memory_region_update_pending |= mr->enabled;
2153 memory_region_transaction_commit();
2154 }
2155 }
2156
2157 void memory_region_reset_dirty(MemoryRegion *mr, hwaddr addr,
2158 hwaddr size, unsigned client)
2159 {
2160 assert(mr->ram_block);
2161 cpu_physical_memory_test_and_clear_dirty(
2162 memory_region_get_ram_addr(mr) + addr, size, client);
2163 }
2164
2165 int memory_region_get_fd(MemoryRegion *mr)
2166 {
2167 int fd;
2168
2169 rcu_read_lock();
2170 while (mr->alias) {
2171 mr = mr->alias;
2172 }
2173 fd = mr->ram_block->fd;
2174 rcu_read_unlock();
2175
2176 return fd;
2177 }
2178
2179 void *memory_region_get_ram_ptr(MemoryRegion *mr)
2180 {
2181 void *ptr;
2182 uint64_t offset = 0;
2183
2184 rcu_read_lock();
2185 while (mr->alias) {
2186 offset += mr->alias_offset;
2187 mr = mr->alias;
2188 }
2189 assert(mr->ram_block);
2190 ptr = qemu_map_ram_ptr(mr->ram_block, offset);
2191 rcu_read_unlock();
2192
2193 return ptr;
2194 }
2195
2196 MemoryRegion *memory_region_from_host(void *ptr, ram_addr_t *offset)
2197 {
2198 RAMBlock *block;
2199
2200 block = qemu_ram_block_from_host(ptr, false, offset);
2201 if (!block) {
2202 return NULL;
2203 }
2204
2205 return block->mr;
2206 }
2207
2208 ram_addr_t memory_region_get_ram_addr(MemoryRegion *mr)
2209 {
2210 return mr->ram_block ? mr->ram_block->offset : RAM_ADDR_INVALID;
2211 }
2212
2213 void memory_region_ram_resize(MemoryRegion *mr, ram_addr_t newsize, Error **errp)
2214 {
2215 assert(mr->ram_block);
2216
2217 qemu_ram_resize(mr->ram_block, newsize, errp);
2218 }
2219
2220 /*
2221 * Call proper memory listeners about the change on the newly
2222 * added/removed CoalescedMemoryRange.
2223 */
2224 static void memory_region_update_coalesced_range(MemoryRegion *mr,
2225 CoalescedMemoryRange *cmr,
2226 bool add)
2227 {
2228 AddressSpace *as;
2229 FlatView *view;
2230 FlatRange *fr;
2231
2232 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
2233 view = address_space_get_flatview(as);
2234 FOR_EACH_FLAT_RANGE(fr, view) {
2235 if (fr->mr == mr) {
2236 flat_range_coalesced_io_notify(fr, as, cmr, add);
2237 }
2238 }
2239 flatview_unref(view);
2240 }
2241 }
2242
2243 void memory_region_set_coalescing(MemoryRegion *mr)
2244 {
2245 memory_region_clear_coalescing(mr);
2246 memory_region_add_coalescing(mr, 0, int128_get64(mr->size));
2247 }
2248
2249 void memory_region_add_coalescing(MemoryRegion *mr,
2250 hwaddr offset,
2251 uint64_t size)
2252 {
2253 CoalescedMemoryRange *cmr = g_malloc(sizeof(*cmr));
2254
2255 cmr->addr = addrrange_make(int128_make64(offset), int128_make64(size));
2256 QTAILQ_INSERT_TAIL(&mr->coalesced, cmr, link);
2257 memory_region_update_coalesced_range(mr, cmr, true);
2258 memory_region_set_flush_coalesced(mr);
2259 }
2260
2261 void memory_region_clear_coalescing(MemoryRegion *mr)
2262 {
2263 CoalescedMemoryRange *cmr;
2264
2265 if (QTAILQ_EMPTY(&mr->coalesced)) {
2266 return;
2267 }
2268
2269 qemu_flush_coalesced_mmio_buffer();
2270 mr->flush_coalesced_mmio = false;
2271
2272 while (!QTAILQ_EMPTY(&mr->coalesced)) {
2273 cmr = QTAILQ_FIRST(&mr->coalesced);
2274 QTAILQ_REMOVE(&mr->coalesced, cmr, link);
2275 memory_region_update_coalesced_range(mr, cmr, false);
2276 g_free(cmr);
2277 }
2278 }
2279
2280 void memory_region_set_flush_coalesced(MemoryRegion *mr)
2281 {
2282 mr->flush_coalesced_mmio = true;
2283 }
2284
2285 void memory_region_clear_flush_coalesced(MemoryRegion *mr)
2286 {
2287 qemu_flush_coalesced_mmio_buffer();
2288 if (QTAILQ_EMPTY(&mr->coalesced)) {
2289 mr->flush_coalesced_mmio = false;
2290 }
2291 }
2292
2293 void memory_region_clear_global_locking(MemoryRegion *mr)
2294 {
2295 mr->global_locking = false;
2296 }
2297
2298 static bool userspace_eventfd_warning;
2299
2300 void memory_region_add_eventfd(MemoryRegion *mr,
2301 hwaddr addr,
2302 unsigned size,
2303 bool match_data,
2304 uint64_t data,
2305 EventNotifier *e)
2306 {
2307 MemoryRegionIoeventfd mrfd = {
2308 .addr.start = int128_make64(addr),
2309 .addr.size = int128_make64(size),
2310 .match_data = match_data,
2311 .data = data,
2312 .e = e,
2313 };
2314 unsigned i;
2315
2316 if (kvm_enabled() && (!(kvm_eventfds_enabled() ||
2317 userspace_eventfd_warning))) {
2318 userspace_eventfd_warning = true;
2319 error_report("Using eventfd without MMIO binding in KVM. "
2320 "Suboptimal performance expected");
2321 }
2322
2323 if (size) {
2324 adjust_endianness(mr, &mrfd.data, size_memop(size) | MO_TE);
2325 }
2326 memory_region_transaction_begin();
2327 for (i = 0; i < mr->ioeventfd_nb; ++i) {
2328 if (memory_region_ioeventfd_before(&mrfd, &mr->ioeventfds[i])) {
2329 break;
2330 }
2331 }
2332 ++mr->ioeventfd_nb;
2333 mr->ioeventfds = g_realloc(mr->ioeventfds,
2334 sizeof(*mr->ioeventfds) * mr->ioeventfd_nb);
2335 memmove(&mr->ioeventfds[i+1], &mr->ioeventfds[i],
2336 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb-1 - i));
2337 mr->ioeventfds[i] = mrfd;
2338 ioeventfd_update_pending |= mr->enabled;
2339 memory_region_transaction_commit();
2340 }
2341
2342 void memory_region_del_eventfd(MemoryRegion *mr,
2343 hwaddr addr,
2344 unsigned size,
2345 bool match_data,
2346 uint64_t data,
2347 EventNotifier *e)
2348 {
2349 MemoryRegionIoeventfd mrfd = {
2350 .addr.start = int128_make64(addr),
2351 .addr.size = int128_make64(size),
2352 .match_data = match_data,
2353 .data = data,
2354 .e = e,
2355 };
2356 unsigned i;
2357
2358 if (size) {
2359 adjust_endianness(mr, &mrfd.data, size_memop(size) | MO_TE);
2360 }
2361 memory_region_transaction_begin();
2362 for (i = 0; i < mr->ioeventfd_nb; ++i) {
2363 if (memory_region_ioeventfd_equal(&mrfd, &mr->ioeventfds[i])) {
2364 break;
2365 }
2366 }
2367 assert(i != mr->ioeventfd_nb);
2368 memmove(&mr->ioeventfds[i], &mr->ioeventfds[i+1],
2369 sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb - (i+1)));
2370 --mr->ioeventfd_nb;
2371 mr->ioeventfds = g_realloc(mr->ioeventfds,
2372 sizeof(*mr->ioeventfds)*mr->ioeventfd_nb + 1);
2373 ioeventfd_update_pending |= mr->enabled;
2374 memory_region_transaction_commit();
2375 }
2376
2377 static void memory_region_update_container_subregions(MemoryRegion *subregion)
2378 {
2379 MemoryRegion *mr = subregion->container;
2380 MemoryRegion *other;
2381
2382 memory_region_transaction_begin();
2383
2384 memory_region_ref(subregion);
2385 QTAILQ_FOREACH(other, &mr->subregions, subregions_link) {
2386 if (subregion->priority >= other->priority) {
2387 QTAILQ_INSERT_BEFORE(other, subregion, subregions_link);
2388 goto done;
2389 }
2390 }
2391 QTAILQ_INSERT_TAIL(&mr->subregions, subregion, subregions_link);
2392 done:
2393 memory_region_update_pending |= mr->enabled && subregion->enabled;
2394 memory_region_transaction_commit();
2395 }
2396
2397 static void memory_region_add_subregion_common(MemoryRegion *mr,
2398 hwaddr offset,
2399 MemoryRegion *subregion)
2400 {
2401 assert(!subregion->container);
2402 subregion->container = mr;
2403 subregion->addr = offset;
2404 memory_region_update_container_subregions(subregion);
2405 }
2406
2407 void memory_region_add_subregion(MemoryRegion *mr,
2408 hwaddr offset,
2409 MemoryRegion *subregion)
2410 {
2411 subregion->priority = 0;
2412 memory_region_add_subregion_common(mr, offset, subregion);
2413 }
2414
2415 void memory_region_add_subregion_overlap(MemoryRegion *mr,
2416 hwaddr offset,
2417 MemoryRegion *subregion,
2418 int priority)
2419 {
2420 subregion->priority = priority;
2421 memory_region_add_subregion_common(mr, offset, subregion);
2422 }
2423
2424 void memory_region_del_subregion(MemoryRegion *mr,
2425 MemoryRegion *subregion)
2426 {
2427 memory_region_transaction_begin();
2428 assert(subregion->container == mr);
2429 subregion->container = NULL;
2430 QTAILQ_REMOVE(&mr->subregions, subregion, subregions_link);
2431 memory_region_unref(subregion);
2432 memory_region_update_pending |= mr->enabled && subregion->enabled;
2433 memory_region_transaction_commit();
2434 }
2435
2436 void memory_region_set_enabled(MemoryRegion *mr, bool enabled)
2437 {
2438 if (enabled == mr->enabled) {
2439 return;
2440 }
2441 memory_region_transaction_begin();
2442 mr->enabled = enabled;
2443 memory_region_update_pending = true;
2444 memory_region_transaction_commit();
2445 }
2446
2447 void memory_region_set_size(MemoryRegion *mr, uint64_t size)
2448 {
2449 Int128 s = int128_make64(size);
2450
2451 if (size == UINT64_MAX) {
2452 s = int128_2_64();
2453 }
2454 if (int128_eq(s, mr->size)) {
2455 return;
2456 }
2457 memory_region_transaction_begin();
2458 mr->size = s;
2459 memory_region_update_pending = true;
2460 memory_region_transaction_commit();
2461 }
2462
2463 static void memory_region_readd_subregion(MemoryRegion *mr)
2464 {
2465 MemoryRegion *container = mr->container;
2466
2467 if (container) {
2468 memory_region_transaction_begin();
2469 memory_region_ref(mr);
2470 memory_region_del_subregion(container, mr);
2471 mr->container = container;
2472 memory_region_update_container_subregions(mr);
2473 memory_region_unref(mr);
2474 memory_region_transaction_commit();
2475 }
2476 }
2477
2478 void memory_region_set_address(MemoryRegion *mr, hwaddr addr)
2479 {
2480 if (addr != mr->addr) {
2481 mr->addr = addr;
2482 memory_region_readd_subregion(mr);
2483 }
2484 }
2485
2486 void memory_region_set_alias_offset(MemoryRegion *mr, hwaddr offset)
2487 {
2488 assert(mr->alias);
2489
2490 if (offset == mr->alias_offset) {
2491 return;
2492 }
2493
2494 memory_region_transaction_begin();
2495 mr->alias_offset = offset;
2496 memory_region_update_pending |= mr->enabled;
2497 memory_region_transaction_commit();
2498 }
2499
2500 uint64_t memory_region_get_alignment(const MemoryRegion *mr)
2501 {
2502 return mr->align;
2503 }
2504
2505 static int cmp_flatrange_addr(const void *addr_, const void *fr_)
2506 {
2507 const AddrRange *addr = addr_;
2508 const FlatRange *fr = fr_;
2509
2510 if (int128_le(addrrange_end(*addr), fr->addr.start)) {
2511 return -1;
2512 } else if (int128_ge(addr->start, addrrange_end(fr->addr))) {
2513 return 1;
2514 }
2515 return 0;
2516 }
2517
2518 static FlatRange *flatview_lookup(FlatView *view, AddrRange addr)
2519 {
2520 return bsearch(&addr, view->ranges, view->nr,
2521 sizeof(FlatRange), cmp_flatrange_addr);
2522 }
2523
2524 bool memory_region_is_mapped(MemoryRegion *mr)
2525 {
2526 return mr->container ? true : false;
2527 }
2528
2529 /* Same as memory_region_find, but it does not add a reference to the
2530 * returned region. It must be called from an RCU critical section.
2531 */
2532 static MemoryRegionSection memory_region_find_rcu(MemoryRegion *mr,
2533 hwaddr addr, uint64_t size)
2534 {
2535 MemoryRegionSection ret = { .mr = NULL };
2536 MemoryRegion *root;
2537 AddressSpace *as;
2538 AddrRange range;
2539 FlatView *view;
2540 FlatRange *fr;
2541
2542 addr += mr->addr;
2543 for (root = mr; root->container; ) {
2544 root = root->container;
2545 addr += root->addr;
2546 }
2547
2548 as = memory_region_to_address_space(root);
2549 if (!as) {
2550 return ret;
2551 }
2552 range = addrrange_make(int128_make64(addr), int128_make64(size));
2553
2554 view = address_space_to_flatview(as);
2555 fr = flatview_lookup(view, range);
2556 if (!fr) {
2557 return ret;
2558 }
2559
2560 while (fr > view->ranges && addrrange_intersects(fr[-1].addr, range)) {
2561 --fr;
2562 }
2563
2564 ret.mr = fr->mr;
2565 ret.fv = view;
2566 range = addrrange_intersection(range, fr->addr);
2567 ret.offset_within_region = fr->offset_in_region;
2568 ret.offset_within_region += int128_get64(int128_sub(range.start,
2569 fr->addr.start));
2570 ret.size = range.size;
2571 ret.offset_within_address_space = int128_get64(range.start);
2572 ret.readonly = fr->readonly;
2573 ret.nonvolatile = fr->nonvolatile;
2574 return ret;
2575 }
2576
2577 MemoryRegionSection memory_region_find(MemoryRegion *mr,
2578 hwaddr addr, uint64_t size)
2579 {
2580 MemoryRegionSection ret;
2581 rcu_read_lock();
2582 ret = memory_region_find_rcu(mr, addr, size);
2583 if (ret.mr) {
2584 memory_region_ref(ret.mr);
2585 }
2586 rcu_read_unlock();
2587 return ret;
2588 }
2589
2590 bool memory_region_present(MemoryRegion *container, hwaddr addr)
2591 {
2592 MemoryRegion *mr;
2593
2594 rcu_read_lock();
2595 mr = memory_region_find_rcu(container, addr, 1).mr;
2596 rcu_read_unlock();
2597 return mr && mr != container;
2598 }
2599
2600 void memory_global_dirty_log_sync(void)
2601 {
2602 memory_region_sync_dirty_bitmap(NULL);
2603 }
2604
2605 void memory_global_after_dirty_log_sync(void)
2606 {
2607 MEMORY_LISTENER_CALL_GLOBAL(log_global_after_sync, Forward);
2608 }
2609
2610 static VMChangeStateEntry *vmstate_change;
2611
2612 void memory_global_dirty_log_start(void)
2613 {
2614 if (vmstate_change) {
2615 qemu_del_vm_change_state_handler(vmstate_change);
2616 vmstate_change = NULL;
2617 }
2618
2619 global_dirty_log = true;
2620
2621 MEMORY_LISTENER_CALL_GLOBAL(log_global_start, Forward);
2622
2623 /* Refresh DIRTY_MEMORY_MIGRATION bit. */
2624 memory_region_transaction_begin();
2625 memory_region_update_pending = true;
2626 memory_region_transaction_commit();
2627 }
2628
2629 static void memory_global_dirty_log_do_stop(void)
2630 {
2631 global_dirty_log = false;
2632
2633 /* Refresh DIRTY_MEMORY_MIGRATION bit. */
2634 memory_region_transaction_begin();
2635 memory_region_update_pending = true;
2636 memory_region_transaction_commit();
2637
2638 MEMORY_LISTENER_CALL_GLOBAL(log_global_stop, Reverse);
2639 }
2640
2641 static void memory_vm_change_state_handler(void *opaque, int running,
2642 RunState state)
2643 {
2644 if (running) {
2645 memory_global_dirty_log_do_stop();
2646
2647 if (vmstate_change) {
2648 qemu_del_vm_change_state_handler(vmstate_change);
2649 vmstate_change = NULL;
2650 }
2651 }
2652 }
2653
2654 void memory_global_dirty_log_stop(void)
2655 {
2656 if (!runstate_is_running()) {
2657 if (vmstate_change) {
2658 return;
2659 }
2660 vmstate_change = qemu_add_vm_change_state_handler(
2661 memory_vm_change_state_handler, NULL);
2662 return;
2663 }
2664
2665 memory_global_dirty_log_do_stop();
2666 }
2667
2668 static void listener_add_address_space(MemoryListener *listener,
2669 AddressSpace *as)
2670 {
2671 FlatView *view;
2672 FlatRange *fr;
2673
2674 if (listener->begin) {
2675 listener->begin(listener);
2676 }
2677 if (global_dirty_log) {
2678 if (listener->log_global_start) {
2679 listener->log_global_start(listener);
2680 }
2681 }
2682
2683 view = address_space_get_flatview(as);
2684 FOR_EACH_FLAT_RANGE(fr, view) {
2685 MemoryRegionSection section = section_from_flat_range(fr, view);
2686
2687 if (listener->region_add) {
2688 listener->region_add(listener, &section);
2689 }
2690 if (fr->dirty_log_mask && listener->log_start) {
2691 listener->log_start(listener, &section, 0, fr->dirty_log_mask);
2692 }
2693 }
2694 if (listener->commit) {
2695 listener->commit(listener);
2696 }
2697 flatview_unref(view);
2698 }
2699
2700 static void listener_del_address_space(MemoryListener *listener,
2701 AddressSpace *as)
2702 {
2703 FlatView *view;
2704 FlatRange *fr;
2705
2706 if (listener->begin) {
2707 listener->begin(listener);
2708 }
2709 view = address_space_get_flatview(as);
2710 FOR_EACH_FLAT_RANGE(fr, view) {
2711 MemoryRegionSection section = section_from_flat_range(fr, view);
2712
2713 if (fr->dirty_log_mask && listener->log_stop) {
2714 listener->log_stop(listener, &section, fr->dirty_log_mask, 0);
2715 }
2716 if (listener->region_del) {
2717 listener->region_del(listener, &section);
2718 }
2719 }
2720 if (listener->commit) {
2721 listener->commit(listener);
2722 }
2723 flatview_unref(view);
2724 }
2725
2726 void memory_listener_register(MemoryListener *listener, AddressSpace *as)
2727 {
2728 MemoryListener *other = NULL;
2729
2730 listener->address_space = as;
2731 if (QTAILQ_EMPTY(&memory_listeners)
2732 || listener->priority >= QTAILQ_LAST(&memory_listeners)->priority) {
2733 QTAILQ_INSERT_TAIL(&memory_listeners, listener, link);
2734 } else {
2735 QTAILQ_FOREACH(other, &memory_listeners, link) {
2736 if (listener->priority < other->priority) {
2737 break;
2738 }
2739 }
2740 QTAILQ_INSERT_BEFORE(other, listener, link);
2741 }
2742
2743 if (QTAILQ_EMPTY(&as->listeners)
2744 || listener->priority >= QTAILQ_LAST(&as->listeners)->priority) {
2745 QTAILQ_INSERT_TAIL(&as->listeners, listener, link_as);
2746 } else {
2747 QTAILQ_FOREACH(other, &as->listeners, link_as) {
2748 if (listener->priority < other->priority) {
2749 break;
2750 }
2751 }
2752 QTAILQ_INSERT_BEFORE(other, listener, link_as);
2753 }
2754
2755 listener_add_address_space(listener, as);
2756 }
2757
2758 void memory_listener_unregister(MemoryListener *listener)
2759 {
2760 if (!listener->address_space) {
2761 return;
2762 }
2763
2764 listener_del_address_space(listener, listener->address_space);
2765 QTAILQ_REMOVE(&memory_listeners, listener, link);
2766 QTAILQ_REMOVE(&listener->address_space->listeners, listener, link_as);
2767 listener->address_space = NULL;
2768 }
2769
2770 void address_space_remove_listeners(AddressSpace *as)
2771 {
2772 while (!QTAILQ_EMPTY(&as->listeners)) {
2773 memory_listener_unregister(QTAILQ_FIRST(&as->listeners));
2774 }
2775 }
2776
2777 void address_space_init(AddressSpace *as, MemoryRegion *root, const char *name)
2778 {
2779 memory_region_ref(root);
2780 as->root = root;
2781 as->current_map = NULL;
2782 as->ioeventfd_nb = 0;
2783 as->ioeventfds = NULL;
2784 QTAILQ_INIT(&as->listeners);
2785 QTAILQ_INSERT_TAIL(&address_spaces, as, address_spaces_link);
2786 as->name = g_strdup(name ? name : "anonymous");
2787 address_space_update_topology(as);
2788 address_space_update_ioeventfds(as);
2789 }
2790
2791 static void do_address_space_destroy(AddressSpace *as)
2792 {
2793 assert(QTAILQ_EMPTY(&as->listeners));
2794
2795 flatview_unref(as->current_map);
2796 g_free(as->name);
2797 g_free(as->ioeventfds);
2798 memory_region_unref(as->root);
2799 }
2800
2801 void address_space_destroy(AddressSpace *as)
2802 {
2803 MemoryRegion *root = as->root;
2804
2805 /* Flush out anything from MemoryListeners listening in on this */
2806 memory_region_transaction_begin();
2807 as->root = NULL;
2808 memory_region_transaction_commit();
2809 QTAILQ_REMOVE(&address_spaces, as, address_spaces_link);
2810
2811 /* At this point, as->dispatch and as->current_map are dummy
2812 * entries that the guest should never use. Wait for the old
2813 * values to expire before freeing the data.
2814 */
2815 as->root = root;
2816 call_rcu(as, do_address_space_destroy, rcu);
2817 }
2818
2819 static const char *memory_region_type(MemoryRegion *mr)
2820 {
2821 if (memory_region_is_ram_device(mr)) {
2822 return "ramd";
2823 } else if (memory_region_is_romd(mr)) {
2824 return "romd";
2825 } else if (memory_region_is_rom(mr)) {
2826 return "rom";
2827 } else if (memory_region_is_ram(mr)) {
2828 return "ram";
2829 } else {
2830 return "i/o";
2831 }
2832 }
2833
2834 typedef struct MemoryRegionList MemoryRegionList;
2835
2836 struct MemoryRegionList {
2837 const MemoryRegion *mr;
2838 QTAILQ_ENTRY(MemoryRegionList) mrqueue;
2839 };
2840
2841 typedef QTAILQ_HEAD(, MemoryRegionList) MemoryRegionListHead;
2842
2843 #define MR_SIZE(size) (int128_nz(size) ? (hwaddr)int128_get64( \
2844 int128_sub((size), int128_one())) : 0)
2845 #define MTREE_INDENT " "
2846
2847 static void mtree_expand_owner(const char *label, Object *obj)
2848 {
2849 DeviceState *dev = (DeviceState *) object_dynamic_cast(obj, TYPE_DEVICE);
2850
2851 qemu_printf(" %s:{%s", label, dev ? "dev" : "obj");
2852 if (dev && dev->id) {
2853 qemu_printf(" id=%s", dev->id);
2854 } else {
2855 gchar *canonical_path = object_get_canonical_path(obj);
2856 if (canonical_path) {
2857 qemu_printf(" path=%s", canonical_path);
2858 g_free(canonical_path);
2859 } else {
2860 qemu_printf(" type=%s", object_get_typename(obj));
2861 }
2862 }
2863 qemu_printf("}");
2864 }
2865
2866 static void mtree_print_mr_owner(const MemoryRegion *mr)
2867 {
2868 Object *owner = mr->owner;
2869 Object *parent = memory_region_owner((MemoryRegion *)mr);
2870
2871 if (!owner && !parent) {
2872 qemu_printf(" orphan");
2873 return;
2874 }
2875 if (owner) {
2876 mtree_expand_owner("owner", owner);
2877 }
2878 if (parent && parent != owner) {
2879 mtree_expand_owner("parent", parent);
2880 }
2881 }
2882
2883 static void mtree_print_mr(const MemoryRegion *mr, unsigned int level,
2884 hwaddr base,
2885 MemoryRegionListHead *alias_print_queue,
2886 bool owner)
2887 {
2888 MemoryRegionList *new_ml, *ml, *next_ml;
2889 MemoryRegionListHead submr_print_queue;
2890 const MemoryRegion *submr;
2891 unsigned int i;
2892 hwaddr cur_start, cur_end;
2893
2894 if (!mr) {
2895 return;
2896 }
2897
2898 for (i = 0; i < level; i++) {
2899 qemu_printf(MTREE_INDENT);
2900 }
2901
2902 cur_start = base + mr->addr;
2903 cur_end = cur_start + MR_SIZE(mr->size);
2904
2905 /*
2906 * Try to detect overflow of memory region. This should never
2907 * happen normally. When it happens, we dump something to warn the
2908 * user who is observing this.
2909 */
2910 if (cur_start < base || cur_end < cur_start) {
2911 qemu_printf("[DETECTED OVERFLOW!] ");
2912 }
2913
2914 if (mr->alias) {
2915 MemoryRegionList *ml;
2916 bool found = false;
2917
2918 /* check if the alias is already in the queue */
2919 QTAILQ_FOREACH(ml, alias_print_queue, mrqueue) {
2920 if (ml->mr == mr->alias) {
2921 found = true;
2922 }
2923 }
2924
2925 if (!found) {
2926 ml = g_new(MemoryRegionList, 1);
2927 ml->mr = mr->alias;
2928 QTAILQ_INSERT_TAIL(alias_print_queue, ml, mrqueue);
2929 }
2930 qemu_printf(TARGET_FMT_plx "-" TARGET_FMT_plx
2931 " (prio %d, %s%s): alias %s @%s " TARGET_FMT_plx
2932 "-" TARGET_FMT_plx "%s",
2933 cur_start, cur_end,
2934 mr->priority,
2935 mr->nonvolatile ? "nv-" : "",
2936 memory_region_type((MemoryRegion *)mr),
2937 memory_region_name(mr),
2938 memory_region_name(mr->alias),
2939 mr->alias_offset,
2940 mr->alias_offset + MR_SIZE(mr->size),
2941 mr->enabled ? "" : " [disabled]");
2942 if (owner) {
2943 mtree_print_mr_owner(mr);
2944 }
2945 } else {
2946 qemu_printf(TARGET_FMT_plx "-" TARGET_FMT_plx
2947 " (prio %d, %s%s): %s%s",
2948 cur_start, cur_end,
2949 mr->priority,
2950 mr->nonvolatile ? "nv-" : "",
2951 memory_region_type((MemoryRegion *)mr),
2952 memory_region_name(mr),
2953 mr->enabled ? "" : " [disabled]");
2954 if (owner) {
2955 mtree_print_mr_owner(mr);
2956 }
2957 }
2958 qemu_printf("\n");
2959
2960 QTAILQ_INIT(&submr_print_queue);
2961
2962 QTAILQ_FOREACH(submr, &mr->subregions, subregions_link) {
2963 new_ml = g_new(MemoryRegionList, 1);
2964 new_ml->mr = submr;
2965 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
2966 if (new_ml->mr->addr < ml->mr->addr ||
2967 (new_ml->mr->addr == ml->mr->addr &&
2968 new_ml->mr->priority > ml->mr->priority)) {
2969 QTAILQ_INSERT_BEFORE(ml, new_ml, mrqueue);
2970 new_ml = NULL;
2971 break;
2972 }
2973 }
2974 if (new_ml) {
2975 QTAILQ_INSERT_TAIL(&submr_print_queue, new_ml, mrqueue);
2976 }
2977 }
2978
2979 QTAILQ_FOREACH(ml, &submr_print_queue, mrqueue) {
2980 mtree_print_mr(ml->mr, level + 1, cur_start,
2981 alias_print_queue, owner);
2982 }
2983
2984 QTAILQ_FOREACH_SAFE(ml, &submr_print_queue, mrqueue, next_ml) {
2985 g_free(ml);
2986 }
2987 }
2988
2989 struct FlatViewInfo {
2990 int counter;
2991 bool dispatch_tree;
2992 bool owner;
2993 AccelClass *ac;
2994 const char *ac_name;
2995 };
2996
2997 static void mtree_print_flatview(gpointer key, gpointer value,
2998 gpointer user_data)
2999 {
3000 FlatView *view = key;
3001 GArray *fv_address_spaces = value;
3002 struct FlatViewInfo *fvi = user_data;
3003 FlatRange *range = &view->ranges[0];
3004 MemoryRegion *mr;
3005 int n = view->nr;
3006 int i;
3007 AddressSpace *as;
3008
3009 qemu_printf("FlatView #%d\n", fvi->counter);
3010 ++fvi->counter;
3011
3012 for (i = 0; i < fv_address_spaces->len; ++i) {
3013 as = g_array_index(fv_address_spaces, AddressSpace*, i);
3014 qemu_printf(" AS \"%s\", root: %s",
3015 as->name, memory_region_name(as->root));
3016 if (as->root->alias) {
3017 qemu_printf(", alias %s", memory_region_name(as->root->alias));
3018 }
3019 qemu_printf("\n");
3020 }
3021
3022 qemu_printf(" Root memory region: %s\n",
3023 view->root ? memory_region_name(view->root) : "(none)");
3024
3025 if (n <= 0) {
3026 qemu_printf(MTREE_INDENT "No rendered FlatView\n\n");
3027 return;
3028 }
3029
3030 while (n--) {
3031 mr = range->mr;
3032 if (range->offset_in_region) {
3033 qemu_printf(MTREE_INDENT TARGET_FMT_plx "-" TARGET_FMT_plx
3034 " (prio %d, %s%s): %s @" TARGET_FMT_plx,
3035 int128_get64(range->addr.start),
3036 int128_get64(range->addr.start)
3037 + MR_SIZE(range->addr.size),
3038 mr->priority,
3039 range->nonvolatile ? "nv-" : "",
3040 range->readonly ? "rom" : memory_region_type(mr),
3041 memory_region_name(mr),
3042 range->offset_in_region);
3043 } else {
3044 qemu_printf(MTREE_INDENT TARGET_FMT_plx "-" TARGET_FMT_plx
3045 " (prio %d, %s%s): %s",
3046 int128_get64(range->addr.start),
3047 int128_get64(range->addr.start)
3048 + MR_SIZE(range->addr.size),
3049 mr->priority,
3050 range->nonvolatile ? "nv-" : "",
3051 range->readonly ? "rom" : memory_region_type(mr),
3052 memory_region_name(mr));
3053 }
3054 if (fvi->owner) {
3055 mtree_print_mr_owner(mr);
3056 }
3057
3058 if (fvi->ac) {
3059 for (i = 0; i < fv_address_spaces->len; ++i) {
3060 as = g_array_index(fv_address_spaces, AddressSpace*, i);
3061 if (fvi->ac->has_memory(current_machine, as,
3062 int128_get64(range->addr.start),
3063 MR_SIZE(range->addr.size) + 1)) {
3064 qemu_printf(" %s", fvi->ac_name);
3065 }
3066 }
3067 }
3068 qemu_printf("\n");
3069 range++;
3070 }
3071
3072 #if !defined(CONFIG_USER_ONLY)
3073 if (fvi->dispatch_tree && view->root) {
3074 mtree_print_dispatch(view->dispatch, view->root);
3075 }
3076 #endif
3077
3078 qemu_printf("\n");
3079 }
3080
3081 static gboolean mtree_info_flatview_free(gpointer key, gpointer value,
3082 gpointer user_data)
3083 {
3084 FlatView *view = key;
3085 GArray *fv_address_spaces = value;
3086
3087 g_array_unref(fv_address_spaces);
3088 flatview_unref(view);
3089
3090 return true;
3091 }
3092
3093 void mtree_info(bool flatview, bool dispatch_tree, bool owner)
3094 {
3095 MemoryRegionListHead ml_head;
3096 MemoryRegionList *ml, *ml2;
3097 AddressSpace *as;
3098
3099 if (flatview) {
3100 FlatView *view;
3101 struct FlatViewInfo fvi = {
3102 .counter = 0,
3103 .dispatch_tree = dispatch_tree,
3104 .owner = owner,
3105 };
3106 GArray *fv_address_spaces;
3107 GHashTable *views = g_hash_table_new(g_direct_hash, g_direct_equal);
3108 AccelClass *ac = ACCEL_GET_CLASS(current_machine->accelerator);
3109
3110 if (ac->has_memory) {
3111 fvi.ac = ac;
3112 fvi.ac_name = current_machine->accel ? current_machine->accel :
3113 object_class_get_name(OBJECT_CLASS(ac));
3114 }
3115
3116 /* Gather all FVs in one table */
3117 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
3118 view = address_space_get_flatview(as);
3119
3120 fv_address_spaces = g_hash_table_lookup(views, view);
3121 if (!fv_address_spaces) {
3122 fv_address_spaces = g_array_new(false, false, sizeof(as));
3123 g_hash_table_insert(views, view, fv_address_spaces);
3124 }
3125
3126 g_array_append_val(fv_address_spaces, as);
3127 }
3128
3129 /* Print */
3130 g_hash_table_foreach(views, mtree_print_flatview, &fvi);
3131
3132 /* Free */
3133 g_hash_table_foreach_remove(views, mtree_info_flatview_free, 0);
3134 g_hash_table_unref(views);
3135
3136 return;
3137 }
3138
3139 QTAILQ_INIT(&ml_head);
3140
3141 QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
3142 qemu_printf("address-space: %s\n", as->name);
3143 mtree_print_mr(as->root, 1, 0, &ml_head, owner);
3144 qemu_printf("\n");
3145 }
3146
3147 /* print aliased regions */
3148 QTAILQ_FOREACH(ml, &ml_head, mrqueue) {
3149 qemu_printf("memory-region: %s\n", memory_region_name(ml->mr));
3150 mtree_print_mr(ml->mr, 1, 0, &ml_head, owner);
3151 qemu_printf("\n");
3152 }
3153
3154 QTAILQ_FOREACH_SAFE(ml, &ml_head, mrqueue, ml2) {
3155 g_free(ml);
3156 }
3157 }
3158
3159 void memory_region_init_ram(MemoryRegion *mr,
3160 struct Object *owner,
3161 const char *name,
3162 uint64_t size,
3163 Error **errp)
3164 {
3165 DeviceState *owner_dev;
3166 Error *err = NULL;
3167
3168 memory_region_init_ram_nomigrate(mr, owner, name, size, &err);
3169 if (err) {
3170 error_propagate(errp, err);
3171 return;
3172 }
3173 /* This will assert if owner is neither NULL nor a DeviceState.
3174 * We only want the owner here for the purposes of defining a
3175 * unique name for migration. TODO: Ideally we should implement
3176 * a naming scheme for Objects which are not DeviceStates, in
3177 * which case we can relax this restriction.
3178 */
3179 owner_dev = DEVICE(owner);
3180 vmstate_register_ram(mr, owner_dev);
3181 }
3182
3183 void memory_region_init_rom(MemoryRegion *mr,
3184 struct Object *owner,
3185 const char *name,
3186 uint64_t size,
3187 Error **errp)
3188 {
3189 DeviceState *owner_dev;
3190 Error *err = NULL;
3191
3192 memory_region_init_rom_nomigrate(mr, owner, name, size, &err);
3193 if (err) {
3194 error_propagate(errp, err);
3195 return;
3196 }
3197 /* This will assert if owner is neither NULL nor a DeviceState.
3198 * We only want the owner here for the purposes of defining a
3199 * unique name for migration. TODO: Ideally we should implement
3200 * a naming scheme for Objects which are not DeviceStates, in
3201 * which case we can relax this restriction.
3202 */
3203 owner_dev = DEVICE(owner);
3204 vmstate_register_ram(mr, owner_dev);
3205 }
3206
3207 void memory_region_init_rom_device(MemoryRegion *mr,
3208 struct Object *owner,
3209 const MemoryRegionOps *ops,
3210 void *opaque,
3211 const char *name,
3212 uint64_t size,
3213 Error **errp)
3214 {
3215 DeviceState *owner_dev;
3216 Error *err = NULL;
3217
3218 memory_region_init_rom_device_nomigrate(mr, owner, ops, opaque,
3219 name, size, &err);
3220 if (err) {
3221 error_propagate(errp, err);
3222 return;
3223 }
3224 /* This will assert if owner is neither NULL nor a DeviceState.
3225 * We only want the owner here for the purposes of defining a
3226 * unique name for migration. TODO: Ideally we should implement
3227 * a naming scheme for Objects which are not DeviceStates, in
3228 * which case we can relax this restriction.
3229 */
3230 owner_dev = DEVICE(owner);
3231 vmstate_register_ram(mr, owner_dev);
3232 }
3233
3234 static const TypeInfo memory_region_info = {
3235 .parent = TYPE_OBJECT,
3236 .name = TYPE_MEMORY_REGION,
3237 .class_size = sizeof(MemoryRegionClass),
3238 .instance_size = sizeof(MemoryRegion),
3239 .instance_init = memory_region_initfn,
3240 .instance_finalize = memory_region_finalize,
3241 };
3242
3243 static const TypeInfo iommu_memory_region_info = {
3244 .parent = TYPE_MEMORY_REGION,
3245 .name = TYPE_IOMMU_MEMORY_REGION,
3246 .class_size = sizeof(IOMMUMemoryRegionClass),
3247 .instance_size = sizeof(IOMMUMemoryRegion),
3248 .instance_init = iommu_memory_region_initfn,
3249 .abstract = true,
3250 };
3251
3252 static void memory_register_types(void)
3253 {
3254 type_register_static(&memory_region_info);
3255 type_register_static(&iommu_memory_region_info);
3256 }
3257
3258 type_init(memory_register_types)
QEmu