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graph-lock: TSA annotations for lock/unlock functions
[qemu.git] / hw / usb / hcd-ohci.c
blob9d68036d233cb79a4b9e4d1808e267ce589edc6c
1 /*
2 * QEMU USB OHCI Emulation
3 * Copyright (c) 2004 Gianni Tedesco
4 * Copyright (c) 2006 CodeSourcery
5 * Copyright (c) 2006 Openedhand Ltd.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 *
20 * TODO:
21 * o Isochronous transfers
22 * o Allocate bandwidth in frames properly
23 * o Disable timers when nothing needs to be done, or remove timer usage
24 * all together.
25 * o BIOS work to boot from USB storage
26 */
27
28 #include "qemu/osdep.h"
29 #include "hw/irq.h"
30 #include "qapi/error.h"
31 #include "qemu/module.h"
32 #include "qemu/timer.h"
33 #include "hw/usb.h"
34 #include "migration/vmstate.h"
35 #include "hw/sysbus.h"
36 #include "hw/qdev-dma.h"
37 #include "hw/qdev-properties.h"
38 #include "trace.h"
39 #include "hcd-ohci.h"
40
41 /* This causes frames to occur 1000x slower */
42 //#define OHCI_TIME_WARP 1
43
44 #define ED_LINK_LIMIT 32
45
46 static int64_t usb_frame_time;
47 static int64_t usb_bit_time;
48
49 /* Host Controller Communications Area */
50 struct ohci_hcca {
51 uint32_t intr[32];
52 uint16_t frame, pad;
53 uint32_t done;
54 };
55 #define HCCA_WRITEBACK_OFFSET offsetof(struct ohci_hcca, frame)
56 #define HCCA_WRITEBACK_SIZE 8 /* frame, pad, done */
57
58 #define ED_WBACK_OFFSET offsetof(struct ohci_ed, head)
59 #define ED_WBACK_SIZE 4
60
61 /* Bitfields for the first word of an Endpoint Desciptor. */
62 #define OHCI_ED_FA_SHIFT 0
63 #define OHCI_ED_FA_MASK (0x7f<<OHCI_ED_FA_SHIFT)
64 #define OHCI_ED_EN_SHIFT 7
65 #define OHCI_ED_EN_MASK (0xf<<OHCI_ED_EN_SHIFT)
66 #define OHCI_ED_D_SHIFT 11
67 #define OHCI_ED_D_MASK (3<<OHCI_ED_D_SHIFT)
68 #define OHCI_ED_S (1<<13)
69 #define OHCI_ED_K (1<<14)
70 #define OHCI_ED_F (1<<15)
71 #define OHCI_ED_MPS_SHIFT 16
72 #define OHCI_ED_MPS_MASK (0x7ff<<OHCI_ED_MPS_SHIFT)
73
74 /* Flags in the head field of an Endpoint Desciptor. */
75 #define OHCI_ED_H 1
76 #define OHCI_ED_C 2
77
78 /* Bitfields for the first word of a Transfer Desciptor. */
79 #define OHCI_TD_R (1<<18)
80 #define OHCI_TD_DP_SHIFT 19
81 #define OHCI_TD_DP_MASK (3<<OHCI_TD_DP_SHIFT)
82 #define OHCI_TD_DI_SHIFT 21
83 #define OHCI_TD_DI_MASK (7<<OHCI_TD_DI_SHIFT)
84 #define OHCI_TD_T0 (1<<24)
85 #define OHCI_TD_T1 (1<<25)
86 #define OHCI_TD_EC_SHIFT 26
87 #define OHCI_TD_EC_MASK (3<<OHCI_TD_EC_SHIFT)
88 #define OHCI_TD_CC_SHIFT 28
89 #define OHCI_TD_CC_MASK (0xf<<OHCI_TD_CC_SHIFT)
90
91 /* Bitfields for the first word of an Isochronous Transfer Desciptor. */
92 /* CC & DI - same as in the General Transfer Desciptor */
93 #define OHCI_TD_SF_SHIFT 0
94 #define OHCI_TD_SF_MASK (0xffff<<OHCI_TD_SF_SHIFT)
95 #define OHCI_TD_FC_SHIFT 24
96 #define OHCI_TD_FC_MASK (7<<OHCI_TD_FC_SHIFT)
97
98 /* Isochronous Transfer Desciptor - Offset / PacketStatusWord */
99 #define OHCI_TD_PSW_CC_SHIFT 12
100 #define OHCI_TD_PSW_CC_MASK (0xf<<OHCI_TD_PSW_CC_SHIFT)
101 #define OHCI_TD_PSW_SIZE_SHIFT 0
102 #define OHCI_TD_PSW_SIZE_MASK (0xfff<<OHCI_TD_PSW_SIZE_SHIFT)
103
104 #define OHCI_PAGE_MASK 0xfffff000
105 #define OHCI_OFFSET_MASK 0xfff
106
107 #define OHCI_DPTR_MASK 0xfffffff0
108
109 #define OHCI_BM(val, field) \
110 (((val) & OHCI_##field##_MASK) >> OHCI_##field##_SHIFT)
111
112 #define OHCI_SET_BM(val, field, newval) do { \
113 val &= ~OHCI_##field##_MASK; \
114 val |= ((newval) << OHCI_##field##_SHIFT) & OHCI_##field##_MASK; \
115 } while(0)
116
117 /* endpoint descriptor */
118 struct ohci_ed {
119 uint32_t flags;
120 uint32_t tail;
121 uint32_t head;
122 uint32_t next;
123 };
124
125 /* General transfer descriptor */
126 struct ohci_td {
127 uint32_t flags;
128 uint32_t cbp;
129 uint32_t next;
130 uint32_t be;
131 };
132
133 /* Isochronous transfer descriptor */
134 struct ohci_iso_td {
135 uint32_t flags;
136 uint32_t bp;
137 uint32_t next;
138 uint32_t be;
139 uint16_t offset[8];
140 };
141
142 #define USB_HZ 12000000
143
144 /* OHCI Local stuff */
145 #define OHCI_CTL_CBSR ((1<<0)|(1<<1))
146 #define OHCI_CTL_PLE (1<<2)
147 #define OHCI_CTL_IE (1<<3)
148 #define OHCI_CTL_CLE (1<<4)
149 #define OHCI_CTL_BLE (1<<5)
150 #define OHCI_CTL_HCFS ((1<<6)|(1<<7))
151 #define OHCI_USB_RESET 0x00
152 #define OHCI_USB_RESUME 0x40
153 #define OHCI_USB_OPERATIONAL 0x80
154 #define OHCI_USB_SUSPEND 0xc0
155 #define OHCI_CTL_IR (1<<8)
156 #define OHCI_CTL_RWC (1<<9)
157 #define OHCI_CTL_RWE (1<<10)
158
159 #define OHCI_STATUS_HCR (1<<0)
160 #define OHCI_STATUS_CLF (1<<1)
161 #define OHCI_STATUS_BLF (1<<2)
162 #define OHCI_STATUS_OCR (1<<3)
163 #define OHCI_STATUS_SOC ((1<<6)|(1<<7))
164
165 #define OHCI_INTR_SO (1U<<0) /* Scheduling overrun */
166 #define OHCI_INTR_WD (1U<<1) /* HcDoneHead writeback */
167 #define OHCI_INTR_SF (1U<<2) /* Start of frame */
168 #define OHCI_INTR_RD (1U<<3) /* Resume detect */
169 #define OHCI_INTR_UE (1U<<4) /* Unrecoverable error */
170 #define OHCI_INTR_FNO (1U<<5) /* Frame number overflow */
171 #define OHCI_INTR_RHSC (1U<<6) /* Root hub status change */
172 #define OHCI_INTR_OC (1U<<30) /* Ownership change */
173 #define OHCI_INTR_MIE (1U<<31) /* Master Interrupt Enable */
174
175 #define OHCI_HCCA_SIZE 0x100
176 #define OHCI_HCCA_MASK 0xffffff00
177
178 #define OHCI_EDPTR_MASK 0xfffffff0
179
180 #define OHCI_FMI_FI 0x00003fff
181 #define OHCI_FMI_FSMPS 0xffff0000
182 #define OHCI_FMI_FIT 0x80000000
183
184 #define OHCI_FR_RT (1U<<31)
185
186 #define OHCI_LS_THRESH 0x628
187
188 #define OHCI_RHA_RW_MASK 0x00000000 /* Mask of supported features. */
189 #define OHCI_RHA_PSM (1<<8)
190 #define OHCI_RHA_NPS (1<<9)
191 #define OHCI_RHA_DT (1<<10)
192 #define OHCI_RHA_OCPM (1<<11)
193 #define OHCI_RHA_NOCP (1<<12)
194 #define OHCI_RHA_POTPGT_MASK 0xff000000
195
196 #define OHCI_RHS_LPS (1U<<0)
197 #define OHCI_RHS_OCI (1U<<1)
198 #define OHCI_RHS_DRWE (1U<<15)
199 #define OHCI_RHS_LPSC (1U<<16)
200 #define OHCI_RHS_OCIC (1U<<17)
201 #define OHCI_RHS_CRWE (1U<<31)
202
203 #define OHCI_PORT_CCS (1<<0)
204 #define OHCI_PORT_PES (1<<1)
205 #define OHCI_PORT_PSS (1<<2)
206 #define OHCI_PORT_POCI (1<<3)
207 #define OHCI_PORT_PRS (1<<4)
208 #define OHCI_PORT_PPS (1<<8)
209 #define OHCI_PORT_LSDA (1<<9)
210 #define OHCI_PORT_CSC (1<<16)
211 #define OHCI_PORT_PESC (1<<17)
212 #define OHCI_PORT_PSSC (1<<18)
213 #define OHCI_PORT_OCIC (1<<19)
214 #define OHCI_PORT_PRSC (1<<20)
215 #define OHCI_PORT_WTC (OHCI_PORT_CSC|OHCI_PORT_PESC|OHCI_PORT_PSSC \
216 |OHCI_PORT_OCIC|OHCI_PORT_PRSC)
217
218 #define OHCI_TD_DIR_SETUP 0x0
219 #define OHCI_TD_DIR_OUT 0x1
220 #define OHCI_TD_DIR_IN 0x2
221 #define OHCI_TD_DIR_RESERVED 0x3
222
223 #define OHCI_CC_NOERROR 0x0
224 #define OHCI_CC_CRC 0x1
225 #define OHCI_CC_BITSTUFFING 0x2
226 #define OHCI_CC_DATATOGGLEMISMATCH 0x3
227 #define OHCI_CC_STALL 0x4
228 #define OHCI_CC_DEVICENOTRESPONDING 0x5
229 #define OHCI_CC_PIDCHECKFAILURE 0x6
230 #define OHCI_CC_UNDEXPETEDPID 0x7
231 #define OHCI_CC_DATAOVERRUN 0x8
232 #define OHCI_CC_DATAUNDERRUN 0x9
233 #define OHCI_CC_BUFFEROVERRUN 0xc
234 #define OHCI_CC_BUFFERUNDERRUN 0xd
235
236 #define OHCI_HRESET_FSBIR (1 << 0)
237
238 static void ohci_die(OHCIState *ohci)
239 {
240 ohci->ohci_die(ohci);
241 }
242
243 /* Update IRQ levels */
244 static inline void ohci_intr_update(OHCIState *ohci)
245 {
246 int level = 0;
247
248 if ((ohci->intr & OHCI_INTR_MIE) &&
249 (ohci->intr_status & ohci->intr))
250 level = 1;
251
252 qemu_set_irq(ohci->irq, level);
253 }
254
255 /* Set an interrupt */
256 static inline void ohci_set_interrupt(OHCIState *ohci, uint32_t intr)
257 {
258 ohci->intr_status |= intr;
259 ohci_intr_update(ohci);
260 }
261
262 static USBDevice *ohci_find_device(OHCIState *ohci, uint8_t addr)
263 {
264 USBDevice *dev;
265 int i;
266
267 for (i = 0; i < ohci->num_ports; i++) {
268 if ((ohci->rhport[i].ctrl & OHCI_PORT_PES) == 0) {
269 continue;
270 }
271 dev = usb_find_device(&ohci->rhport[i].port, addr);
272 if (dev != NULL) {
273 return dev;
274 }
275 }
276 return NULL;
277 }
278
279 void ohci_stop_endpoints(OHCIState *ohci)
280 {
281 USBDevice *dev;
282 int i, j;
283
284 if (ohci->async_td) {
285 usb_cancel_packet(&ohci->usb_packet);
286 ohci->async_td = 0;
287 }
288 for (i = 0; i < ohci->num_ports; i++) {
289 dev = ohci->rhport[i].port.dev;
290 if (dev && dev->attached) {
291 usb_device_ep_stopped(dev, &dev->ep_ctl);
292 for (j = 0; j < USB_MAX_ENDPOINTS; j++) {
293 usb_device_ep_stopped(dev, &dev->ep_in[j]);
294 usb_device_ep_stopped(dev, &dev->ep_out[j]);
295 }
296 }
297 }
298 }
299
300 static void ohci_roothub_reset(OHCIState *ohci)
301 {
302 OHCIPort *port;
303 int i;
304
305 ohci_bus_stop(ohci);
306 ohci->rhdesc_a = OHCI_RHA_NPS | ohci->num_ports;
307 ohci->rhdesc_b = 0x0; /* Impl. specific */
308 ohci->rhstatus = 0;
309
310 for (i = 0; i < ohci->num_ports; i++) {
311 port = &ohci->rhport[i];
312 port->ctrl = 0;
313 if (port->port.dev && port->port.dev->attached) {
314 usb_port_reset(&port->port);
315 }
316 }
317 ohci_stop_endpoints(ohci);
318 }
319
320 /* Reset the controller */
321 static void ohci_soft_reset(OHCIState *ohci)
322 {
323 trace_usb_ohci_reset(ohci->name);
324
325 ohci_bus_stop(ohci);
326 ohci->ctl = (ohci->ctl & OHCI_CTL_IR) | OHCI_USB_SUSPEND;
327 ohci->old_ctl = 0;
328 ohci->status = 0;
329 ohci->intr_status = 0;
330 ohci->intr = OHCI_INTR_MIE;
331
332 ohci->hcca = 0;
333 ohci->ctrl_head = ohci->ctrl_cur = 0;
334 ohci->bulk_head = ohci->bulk_cur = 0;
335 ohci->per_cur = 0;
336 ohci->done = 0;
337 ohci->done_count = 7;
338
339 /* FSMPS is marked TBD in OCHI 1.0, what gives ffs?
340 * I took the value linux sets ...
341 */
342 ohci->fsmps = 0x2778;
343 ohci->fi = 0x2edf;
344 ohci->fit = 0;
345 ohci->frt = 0;
346 ohci->frame_number = 0;
347 ohci->pstart = 0;
348 ohci->lst = OHCI_LS_THRESH;
349 }
350
351 void ohci_hard_reset(OHCIState *ohci)
352 {
353 ohci_soft_reset(ohci);
354 ohci->ctl = 0;
355 ohci_roothub_reset(ohci);
356 }
357
358 /* Get an array of dwords from main memory */
359 static inline int get_dwords(OHCIState *ohci,
360 dma_addr_t addr, uint32_t *buf, int num)
361 {
362 int i;
363
364 addr += ohci->localmem_base;
365
366 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
367 if (dma_memory_read(ohci->as, addr,
368 buf, sizeof(*buf), MEMTXATTRS_UNSPECIFIED)) {
369 return -1;
370 }
371 *buf = le32_to_cpu(*buf);
372 }
373
374 return 0;
375 }
376
377 /* Put an array of dwords in to main memory */
378 static inline int put_dwords(OHCIState *ohci,
379 dma_addr_t addr, uint32_t *buf, int num)
380 {
381 int i;
382
383 addr += ohci->localmem_base;
384
385 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
386 uint32_t tmp = cpu_to_le32(*buf);
387 if (dma_memory_write(ohci->as, addr,
388 &tmp, sizeof(tmp), MEMTXATTRS_UNSPECIFIED)) {
389 return -1;
390 }
391 }
392
393 return 0;
394 }
395
396 /* Get an array of words from main memory */
397 static inline int get_words(OHCIState *ohci,
398 dma_addr_t addr, uint16_t *buf, int num)
399 {
400 int i;
401
402 addr += ohci->localmem_base;
403
404 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
405 if (dma_memory_read(ohci->as, addr,
406 buf, sizeof(*buf), MEMTXATTRS_UNSPECIFIED)) {
407 return -1;
408 }
409 *buf = le16_to_cpu(*buf);
410 }
411
412 return 0;
413 }
414
415 /* Put an array of words in to main memory */
416 static inline int put_words(OHCIState *ohci,
417 dma_addr_t addr, uint16_t *buf, int num)
418 {
419 int i;
420
421 addr += ohci->localmem_base;
422
423 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
424 uint16_t tmp = cpu_to_le16(*buf);
425 if (dma_memory_write(ohci->as, addr,
426 &tmp, sizeof(tmp), MEMTXATTRS_UNSPECIFIED)) {
427 return -1;
428 }
429 }
430
431 return 0;
432 }
433
434 static inline int ohci_read_ed(OHCIState *ohci,
435 dma_addr_t addr, struct ohci_ed *ed)
436 {
437 return get_dwords(ohci, addr, (uint32_t *)ed, sizeof(*ed) >> 2);
438 }
439
440 static inline int ohci_read_td(OHCIState *ohci,
441 dma_addr_t addr, struct ohci_td *td)
442 {
443 return get_dwords(ohci, addr, (uint32_t *)td, sizeof(*td) >> 2);
444 }
445
446 static inline int ohci_read_iso_td(OHCIState *ohci,
447 dma_addr_t addr, struct ohci_iso_td *td)
448 {
449 return get_dwords(ohci, addr, (uint32_t *)td, 4) ||
450 get_words(ohci, addr + 16, td->offset, 8);
451 }
452
453 static inline int ohci_read_hcca(OHCIState *ohci,
454 dma_addr_t addr, struct ohci_hcca *hcca)
455 {
456 return dma_memory_read(ohci->as, addr + ohci->localmem_base, hcca,
457 sizeof(*hcca), MEMTXATTRS_UNSPECIFIED);
458 }
459
460 static inline int ohci_put_ed(OHCIState *ohci,
461 dma_addr_t addr, struct ohci_ed *ed)
462 {
463 /* ed->tail is under control of the HCD.
464 * Since just ed->head is changed by HC, just write back this
465 */
466
467 return put_dwords(ohci, addr + ED_WBACK_OFFSET,
468 (uint32_t *)((char *)ed + ED_WBACK_OFFSET),
469 ED_WBACK_SIZE >> 2);
470 }
471
472 static inline int ohci_put_td(OHCIState *ohci,
473 dma_addr_t addr, struct ohci_td *td)
474 {
475 return put_dwords(ohci, addr, (uint32_t *)td, sizeof(*td) >> 2);
476 }
477
478 static inline int ohci_put_iso_td(OHCIState *ohci,
479 dma_addr_t addr, struct ohci_iso_td *td)
480 {
481 return put_dwords(ohci, addr, (uint32_t *)td, 4) ||
482 put_words(ohci, addr + 16, td->offset, 8);
483 }
484
485 static inline int ohci_put_hcca(OHCIState *ohci,
486 dma_addr_t addr, struct ohci_hcca *hcca)
487 {
488 return dma_memory_write(ohci->as,
489 addr + ohci->localmem_base + HCCA_WRITEBACK_OFFSET,
490 (char *)hcca + HCCA_WRITEBACK_OFFSET,
491 HCCA_WRITEBACK_SIZE, MEMTXATTRS_UNSPECIFIED);
492 }
493
494 /* Read/Write the contents of a TD from/to main memory. */
495 static int ohci_copy_td(OHCIState *ohci, struct ohci_td *td,
496 uint8_t *buf, int len, DMADirection dir)
497 {
498 dma_addr_t ptr, n;
499
500 ptr = td->cbp;
501 n = 0x1000 - (ptr & 0xfff);
502 if (n > len)
503 n = len;
504
505 if (dma_memory_rw(ohci->as, ptr + ohci->localmem_base, buf,
506 n, dir, MEMTXATTRS_UNSPECIFIED)) {
507 return -1;
508 }
509 if (n == len) {
510 return 0;
511 }
512 ptr = td->be & ~0xfffu;
513 buf += n;
514 if (dma_memory_rw(ohci->as, ptr + ohci->localmem_base, buf,
515 len - n, dir, MEMTXATTRS_UNSPECIFIED)) {
516 return -1;
517 }
518 return 0;
519 }
520
521 /* Read/Write the contents of an ISO TD from/to main memory. */
522 static int ohci_copy_iso_td(OHCIState *ohci,
523 uint32_t start_addr, uint32_t end_addr,
524 uint8_t *buf, int len, DMADirection dir)
525 {
526 dma_addr_t ptr, n;
527
528 ptr = start_addr;
529 n = 0x1000 - (ptr & 0xfff);
530 if (n > len)
531 n = len;
532
533 if (dma_memory_rw(ohci->as, ptr + ohci->localmem_base, buf,
534 n, dir, MEMTXATTRS_UNSPECIFIED)) {
535 return -1;
536 }
537 if (n == len) {
538 return 0;
539 }
540 ptr = end_addr & ~0xfffu;
541 buf += n;
542 if (dma_memory_rw(ohci->as, ptr + ohci->localmem_base, buf,
543 len - n, dir, MEMTXATTRS_UNSPECIFIED)) {
544 return -1;
545 }
546 return 0;
547 }
548
549 #define USUB(a, b) ((int16_t)((uint16_t)(a) - (uint16_t)(b)))
550
551 static int ohci_service_iso_td(OHCIState *ohci, struct ohci_ed *ed)
552 {
553 int dir;
554 size_t len = 0;
555 const char *str = NULL;
556 int pid;
557 int ret;
558 int i;
559 USBDevice *dev;
560 USBEndpoint *ep;
561 USBPacket *pkt;
562 uint8_t buf[8192];
563 bool int_req;
564 struct ohci_iso_td iso_td;
565 uint32_t addr;
566 uint16_t starting_frame;
567 int16_t relative_frame_number;
568 int frame_count;
569 uint32_t start_offset, next_offset, end_offset = 0;
570 uint32_t start_addr, end_addr;
571
572 addr = ed->head & OHCI_DPTR_MASK;
573
574 if (addr == 0) {
575 ohci_die(ohci);
576 return 1;
577 }
578
579 if (ohci_read_iso_td(ohci, addr, &iso_td)) {
580 trace_usb_ohci_iso_td_read_failed(addr);
581 ohci_die(ohci);
582 return 1;
583 }
584
585 starting_frame = OHCI_BM(iso_td.flags, TD_SF);
586 frame_count = OHCI_BM(iso_td.flags, TD_FC);
587 relative_frame_number = USUB(ohci->frame_number, starting_frame);
588
589 trace_usb_ohci_iso_td_head(
590 ed->head & OHCI_DPTR_MASK, ed->tail & OHCI_DPTR_MASK,
591 iso_td.flags, iso_td.bp, iso_td.next, iso_td.be,
592 ohci->frame_number, starting_frame,
593 frame_count, relative_frame_number);
594 trace_usb_ohci_iso_td_head_offset(
595 iso_td.offset[0], iso_td.offset[1],
596 iso_td.offset[2], iso_td.offset[3],
597 iso_td.offset[4], iso_td.offset[5],
598 iso_td.offset[6], iso_td.offset[7]);
599
600 if (relative_frame_number < 0) {
601 trace_usb_ohci_iso_td_relative_frame_number_neg(relative_frame_number);
602 return 1;
603 } else if (relative_frame_number > frame_count) {
604 /* ISO TD expired - retire the TD to the Done Queue and continue with
605 the next ISO TD of the same ED */
606 trace_usb_ohci_iso_td_relative_frame_number_big(relative_frame_number,
607 frame_count);
608 if (OHCI_CC_DATAOVERRUN == OHCI_BM(iso_td.flags, TD_CC)) {
609 /* avoid infinite loop */
610 return 1;
611 }
612 OHCI_SET_BM(iso_td.flags, TD_CC, OHCI_CC_DATAOVERRUN);
613 ed->head &= ~OHCI_DPTR_MASK;
614 ed->head |= (iso_td.next & OHCI_DPTR_MASK);
615 iso_td.next = ohci->done;
616 ohci->done = addr;
617 i = OHCI_BM(iso_td.flags, TD_DI);
618 if (i < ohci->done_count)
619 ohci->done_count = i;
620 if (ohci_put_iso_td(ohci, addr, &iso_td)) {
621 ohci_die(ohci);
622 return 1;
623 }
624 return 0;
625 }
626
627 dir = OHCI_BM(ed->flags, ED_D);
628 switch (dir) {
629 case OHCI_TD_DIR_IN:
630 str = "in";
631 pid = USB_TOKEN_IN;
632 break;
633 case OHCI_TD_DIR_OUT:
634 str = "out";
635 pid = USB_TOKEN_OUT;
636 break;
637 case OHCI_TD_DIR_SETUP:
638 str = "setup";
639 pid = USB_TOKEN_SETUP;
640 break;
641 default:
642 trace_usb_ohci_iso_td_bad_direction(dir);
643 return 1;
644 }
645
646 if (!iso_td.bp || !iso_td.be) {
647 trace_usb_ohci_iso_td_bad_bp_be(iso_td.bp, iso_td.be);
648 return 1;
649 }
650
651 start_offset = iso_td.offset[relative_frame_number];
652 if (relative_frame_number < frame_count) {
653 next_offset = iso_td.offset[relative_frame_number + 1];
654 } else {
655 next_offset = iso_td.be;
656 }
657
658 if (!(OHCI_BM(start_offset, TD_PSW_CC) & 0xe) ||
659 ((relative_frame_number < frame_count) &&
660 !(OHCI_BM(next_offset, TD_PSW_CC) & 0xe))) {
661 trace_usb_ohci_iso_td_bad_cc_not_accessed(start_offset, next_offset);
662 return 1;
663 }
664
665 if ((relative_frame_number < frame_count) && (start_offset > next_offset)) {
666 trace_usb_ohci_iso_td_bad_cc_overrun(start_offset, next_offset);
667 return 1;
668 }
669
670 if ((start_offset & 0x1000) == 0) {
671 start_addr = (iso_td.bp & OHCI_PAGE_MASK) |
672 (start_offset & OHCI_OFFSET_MASK);
673 } else {
674 start_addr = (iso_td.be & OHCI_PAGE_MASK) |
675 (start_offset & OHCI_OFFSET_MASK);
676 }
677
678 if (relative_frame_number < frame_count) {
679 end_offset = next_offset - 1;
680 if ((end_offset & 0x1000) == 0) {
681 end_addr = (iso_td.bp & OHCI_PAGE_MASK) |
682 (end_offset & OHCI_OFFSET_MASK);
683 } else {
684 end_addr = (iso_td.be & OHCI_PAGE_MASK) |
685 (end_offset & OHCI_OFFSET_MASK);
686 }
687 } else {
688 /* Last packet in the ISO TD */
689 end_addr = next_offset;
690 }
691
692 if (start_addr > end_addr) {
693 trace_usb_ohci_iso_td_bad_cc_overrun(start_addr, end_addr);
694 return 1;
695 }
696
697 if ((start_addr & OHCI_PAGE_MASK) != (end_addr & OHCI_PAGE_MASK)) {
698 len = (end_addr & OHCI_OFFSET_MASK) + 0x1001
699 - (start_addr & OHCI_OFFSET_MASK);
700 } else {
701 len = end_addr - start_addr + 1;
702 }
703 if (len > sizeof(buf)) {
704 len = sizeof(buf);
705 }
706
707 if (len && dir != OHCI_TD_DIR_IN) {
708 if (ohci_copy_iso_td(ohci, start_addr, end_addr, buf, len,
709 DMA_DIRECTION_TO_DEVICE)) {
710 ohci_die(ohci);
711 return 1;
712 }
713 }
714
715 dev = ohci_find_device(ohci, OHCI_BM(ed->flags, ED_FA));
716 if (dev == NULL) {
717 trace_usb_ohci_td_dev_error();
718 return 1;
719 }
720 ep = usb_ep_get(dev, pid, OHCI_BM(ed->flags, ED_EN));
721 pkt = g_new0(USBPacket, 1);
722 usb_packet_init(pkt);
723 int_req = relative_frame_number == frame_count &&
724 OHCI_BM(iso_td.flags, TD_DI) == 0;
725 usb_packet_setup(pkt, pid, ep, 0, addr, false, int_req);
726 usb_packet_addbuf(pkt, buf, len);
727 usb_handle_packet(dev, pkt);
728 if (pkt->status == USB_RET_ASYNC) {
729 usb_device_flush_ep_queue(dev, ep);
730 g_free(pkt);
731 return 1;
732 }
733 if (pkt->status == USB_RET_SUCCESS) {
734 ret = pkt->actual_length;
735 } else {
736 ret = pkt->status;
737 }
738 g_free(pkt);
739
740 trace_usb_ohci_iso_td_so(start_offset, end_offset, start_addr, end_addr,
741 str, len, ret);
742
743 /* Writeback */
744 if (dir == OHCI_TD_DIR_IN && ret >= 0 && ret <= len) {
745 /* IN transfer succeeded */
746 if (ohci_copy_iso_td(ohci, start_addr, end_addr, buf, ret,
747 DMA_DIRECTION_FROM_DEVICE)) {
748 ohci_die(ohci);
749 return 1;
750 }
751 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
752 OHCI_CC_NOERROR);
753 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, ret);
754 } else if (dir == OHCI_TD_DIR_OUT && ret == len) {
755 /* OUT transfer succeeded */
756 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
757 OHCI_CC_NOERROR);
758 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, 0);
759 } else {
760 if (ret > (ssize_t) len) {
761 trace_usb_ohci_iso_td_data_overrun(ret, len);
762 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
763 OHCI_CC_DATAOVERRUN);
764 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE,
765 len);
766 } else if (ret >= 0) {
767 trace_usb_ohci_iso_td_data_underrun(ret);
768 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
769 OHCI_CC_DATAUNDERRUN);
770 } else {
771 switch (ret) {
772 case USB_RET_IOERROR:
773 case USB_RET_NODEV:
774 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
775 OHCI_CC_DEVICENOTRESPONDING);
776 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE,
777 0);
778 break;
779 case USB_RET_NAK:
780 case USB_RET_STALL:
781 trace_usb_ohci_iso_td_nak(ret);
782 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
783 OHCI_CC_STALL);
784 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE,
785 0);
786 break;
787 default:
788 trace_usb_ohci_iso_td_bad_response(ret);
789 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC,
790 OHCI_CC_UNDEXPETEDPID);
791 break;
792 }
793 }
794 }
795
796 if (relative_frame_number == frame_count) {
797 /* Last data packet of ISO TD - retire the TD to the Done Queue */
798 OHCI_SET_BM(iso_td.flags, TD_CC, OHCI_CC_NOERROR);
799 ed->head &= ~OHCI_DPTR_MASK;
800 ed->head |= (iso_td.next & OHCI_DPTR_MASK);
801 iso_td.next = ohci->done;
802 ohci->done = addr;
803 i = OHCI_BM(iso_td.flags, TD_DI);
804 if (i < ohci->done_count)
805 ohci->done_count = i;
806 }
807 if (ohci_put_iso_td(ohci, addr, &iso_td)) {
808 ohci_die(ohci);
809 }
810 return 1;
811 }
812
813 #define HEX_CHAR_PER_LINE 16
814
815 static void ohci_td_pkt(const char *msg, const uint8_t *buf, size_t len)
816 {
817 bool print16;
818 bool printall;
819 int i;
820 char tmp[3 * HEX_CHAR_PER_LINE + 1];
821 char *p = tmp;
822
823 print16 = !!trace_event_get_state_backends(TRACE_USB_OHCI_TD_PKT_SHORT);
824 printall = !!trace_event_get_state_backends(TRACE_USB_OHCI_TD_PKT_FULL);
825
826 if (!printall && !print16) {
827 return;
828 }
829
830 for (i = 0; ; i++) {
831 if (i && (!(i % HEX_CHAR_PER_LINE) || (i == len))) {
832 if (!printall) {
833 trace_usb_ohci_td_pkt_short(msg, tmp);
834 break;
835 }
836 trace_usb_ohci_td_pkt_full(msg, tmp);
837 p = tmp;
838 *p = 0;
839 }
840 if (i == len) {
841 break;
842 }
843
844 p += sprintf(p, " %.2x", buf[i]);
845 }
846 }
847
848 /* Service a transport descriptor.
849 Returns nonzero to terminate processing of this endpoint. */
850
851 static int ohci_service_td(OHCIState *ohci, struct ohci_ed *ed)
852 {
853 int dir;
854 size_t len = 0, pktlen = 0;
855 const char *str = NULL;
856 int pid;
857 int ret;
858 int i;
859 USBDevice *dev;
860 USBEndpoint *ep;
861 struct ohci_td td;
862 uint32_t addr;
863 int flag_r;
864 int completion;
865
866 addr = ed->head & OHCI_DPTR_MASK;
867 if (addr == 0) {
868 ohci_die(ohci);
869 return 1;
870 }
871
872 /* See if this TD has already been submitted to the device. */
873 completion = (addr == ohci->async_td);
874 if (completion && !ohci->async_complete) {
875 trace_usb_ohci_td_skip_async();
876 return 1;
877 }
878 if (ohci_read_td(ohci, addr, &td)) {
879 trace_usb_ohci_td_read_error(addr);
880 ohci_die(ohci);
881 return 1;
882 }
883
884 dir = OHCI_BM(ed->flags, ED_D);
885 switch (dir) {
886 case OHCI_TD_DIR_OUT:
887 case OHCI_TD_DIR_IN:
888 /* Same value. */
889 break;
890 default:
891 dir = OHCI_BM(td.flags, TD_DP);
892 break;
893 }
894
895 switch (dir) {
896 case OHCI_TD_DIR_IN:
897 str = "in";
898 pid = USB_TOKEN_IN;
899 break;
900 case OHCI_TD_DIR_OUT:
901 str = "out";
902 pid = USB_TOKEN_OUT;
903 break;
904 case OHCI_TD_DIR_SETUP:
905 str = "setup";
906 pid = USB_TOKEN_SETUP;
907 break;
908 default:
909 trace_usb_ohci_td_bad_direction(dir);
910 return 1;
911 }
912 if (td.cbp && td.be) {
913 if ((td.cbp & 0xfffff000) != (td.be & 0xfffff000)) {
914 len = (td.be & 0xfff) + 0x1001 - (td.cbp & 0xfff);
915 } else {
916 if (td.cbp > td.be) {
917 trace_usb_ohci_iso_td_bad_cc_overrun(td.cbp, td.be);
918 ohci_die(ohci);
919 return 1;
920 }
921 len = (td.be - td.cbp) + 1;
922 }
923 if (len > sizeof(ohci->usb_buf)) {
924 len = sizeof(ohci->usb_buf);
925 }
926
927 pktlen = len;
928 if (len && dir != OHCI_TD_DIR_IN) {
929 /* The endpoint may not allow us to transfer it all now */
930 pktlen = (ed->flags & OHCI_ED_MPS_MASK) >> OHCI_ED_MPS_SHIFT;
931 if (pktlen > len) {
932 pktlen = len;
933 }
934 if (!completion) {
935 if (ohci_copy_td(ohci, &td, ohci->usb_buf, pktlen,
936 DMA_DIRECTION_TO_DEVICE)) {
937 ohci_die(ohci);
938 }
939 }
940 }
941 }
942
943 flag_r = (td.flags & OHCI_TD_R) != 0;
944 trace_usb_ohci_td_pkt_hdr(addr, (int64_t)pktlen, (int64_t)len, str,
945 flag_r, td.cbp, td.be);
946 ohci_td_pkt("OUT", ohci->usb_buf, pktlen);
947
948 if (completion) {
949 ohci->async_td = 0;
950 ohci->async_complete = false;
951 } else {
952 dev = ohci_find_device(ohci, OHCI_BM(ed->flags, ED_FA));
953 if (dev == NULL) {
954 trace_usb_ohci_td_dev_error();
955 return 1;
956 }
957 ep = usb_ep_get(dev, pid, OHCI_BM(ed->flags, ED_EN));
958 if (ohci->async_td) {
959 /* ??? The hardware should allow one active packet per
960 endpoint. We only allow one active packet per controller.
961 This should be sufficient as long as devices respond in a
962 timely manner.
963 */
964 trace_usb_ohci_td_too_many_pending(ep->nr);
965 return 1;
966 }
967 usb_packet_setup(&ohci->usb_packet, pid, ep, 0, addr, !flag_r,
968 OHCI_BM(td.flags, TD_DI) == 0);
969 usb_packet_addbuf(&ohci->usb_packet, ohci->usb_buf, pktlen);
970 usb_handle_packet(dev, &ohci->usb_packet);
971 trace_usb_ohci_td_packet_status(ohci->usb_packet.status);
972
973 if (ohci->usb_packet.status == USB_RET_ASYNC) {
974 usb_device_flush_ep_queue(dev, ep);
975 ohci->async_td = addr;
976 return 1;
977 }
978 }
979 if (ohci->usb_packet.status == USB_RET_SUCCESS) {
980 ret = ohci->usb_packet.actual_length;
981 } else {
982 ret = ohci->usb_packet.status;
983 }
984
985 if (ret >= 0) {
986 if (dir == OHCI_TD_DIR_IN) {
987 if (ohci_copy_td(ohci, &td, ohci->usb_buf, ret,
988 DMA_DIRECTION_FROM_DEVICE)) {
989 ohci_die(ohci);
990 }
991 ohci_td_pkt("IN", ohci->usb_buf, pktlen);
992 } else {
993 ret = pktlen;
994 }
995 }
996
997 /* Writeback */
998 if (ret == pktlen || (dir == OHCI_TD_DIR_IN && ret >= 0 && flag_r)) {
999 /* Transmission succeeded. */
1000 if (ret == len) {
1001 td.cbp = 0;
1002 } else {
1003 if ((td.cbp & 0xfff) + ret > 0xfff) {
1004 td.cbp = (td.be & ~0xfff) + ((td.cbp + ret) & 0xfff);
1005 } else {
1006 td.cbp += ret;
1007 }
1008 }
1009 td.flags |= OHCI_TD_T1;
1010 td.flags ^= OHCI_TD_T0;
1011 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_NOERROR);
1012 OHCI_SET_BM(td.flags, TD_EC, 0);
1013
1014 if ((dir != OHCI_TD_DIR_IN) && (ret != len)) {
1015 /* Partial packet transfer: TD not ready to retire yet */
1016 goto exit_no_retire;
1017 }
1018
1019 /* Setting ED_C is part of the TD retirement process */
1020 ed->head &= ~OHCI_ED_C;
1021 if (td.flags & OHCI_TD_T0)
1022 ed->head |= OHCI_ED_C;
1023 } else {
1024 if (ret >= 0) {
1025 trace_usb_ohci_td_underrun();
1026 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAUNDERRUN);
1027 } else {
1028 switch (ret) {
1029 case USB_RET_IOERROR:
1030 case USB_RET_NODEV:
1031 trace_usb_ohci_td_dev_error();
1032 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DEVICENOTRESPONDING);
1033 break;
1034 case USB_RET_NAK:
1035 trace_usb_ohci_td_nak();
1036 return 1;
1037 case USB_RET_STALL:
1038 trace_usb_ohci_td_stall();
1039 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_STALL);
1040 break;
1041 case USB_RET_BABBLE:
1042 trace_usb_ohci_td_babble();
1043 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAOVERRUN);
1044 break;
1045 default:
1046 trace_usb_ohci_td_bad_device_response(ret);
1047 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_UNDEXPETEDPID);
1048 OHCI_SET_BM(td.flags, TD_EC, 3);
1049 break;
1050 }
1051 /* An error occurred so we have to clear the interrupt counter. See
1052 * spec at 6.4.4 on page 104 */
1053 ohci->done_count = 0;
1054 }
1055 ed->head |= OHCI_ED_H;
1056 }
1057
1058 /* Retire this TD */
1059 ed->head &= ~OHCI_DPTR_MASK;
1060 ed->head |= td.next & OHCI_DPTR_MASK;
1061 td.next = ohci->done;
1062 ohci->done = addr;
1063 i = OHCI_BM(td.flags, TD_DI);
1064 if (i < ohci->done_count)
1065 ohci->done_count = i;
1066 exit_no_retire:
1067 if (ohci_put_td(ohci, addr, &td)) {
1068 ohci_die(ohci);
1069 return 1;
1070 }
1071 return OHCI_BM(td.flags, TD_CC) != OHCI_CC_NOERROR;
1072 }
1073
1074 /* Service an endpoint list. Returns nonzero if active TD were found. */
1075 static int ohci_service_ed_list(OHCIState *ohci, uint32_t head)
1076 {
1077 struct ohci_ed ed;
1078 uint32_t next_ed;
1079 uint32_t cur;
1080 int active;
1081 uint32_t link_cnt = 0;
1082 active = 0;
1083
1084 if (head == 0)
1085 return 0;
1086
1087 for (cur = head; cur && link_cnt++ < ED_LINK_LIMIT; cur = next_ed) {
1088 if (ohci_read_ed(ohci, cur, &ed)) {
1089 trace_usb_ohci_ed_read_error(cur);
1090 ohci_die(ohci);
1091 return 0;
1092 }
1093
1094 next_ed = ed.next & OHCI_DPTR_MASK;
1095
1096 if ((ed.head & OHCI_ED_H) || (ed.flags & OHCI_ED_K)) {
1097 uint32_t addr;
1098 /* Cancel pending packets for ED that have been paused. */
1099 addr = ed.head & OHCI_DPTR_MASK;
1100 if (ohci->async_td && addr == ohci->async_td) {
1101 usb_cancel_packet(&ohci->usb_packet);
1102 ohci->async_td = 0;
1103 usb_device_ep_stopped(ohci->usb_packet.ep->dev,
1104 ohci->usb_packet.ep);
1105 }
1106 continue;
1107 }
1108
1109 while ((ed.head & OHCI_DPTR_MASK) != ed.tail) {
1110 trace_usb_ohci_ed_pkt(cur, (ed.head & OHCI_ED_H) != 0,
1111 (ed.head & OHCI_ED_C) != 0, ed.head & OHCI_DPTR_MASK,
1112 ed.tail & OHCI_DPTR_MASK, ed.next & OHCI_DPTR_MASK);
1113 trace_usb_ohci_ed_pkt_flags(
1114 OHCI_BM(ed.flags, ED_FA), OHCI_BM(ed.flags, ED_EN),
1115 OHCI_BM(ed.flags, ED_D), (ed.flags & OHCI_ED_S)!= 0,
1116 (ed.flags & OHCI_ED_K) != 0, (ed.flags & OHCI_ED_F) != 0,
1117 OHCI_BM(ed.flags, ED_MPS));
1118
1119 active = 1;
1120
1121 if ((ed.flags & OHCI_ED_F) == 0) {
1122 if (ohci_service_td(ohci, &ed))
1123 break;
1124 } else {
1125 /* Handle isochronous endpoints */
1126 if (ohci_service_iso_td(ohci, &ed)) {
1127 break;
1128 }
1129 }
1130 }
1131
1132 if (ohci_put_ed(ohci, cur, &ed)) {
1133 ohci_die(ohci);
1134 return 0;
1135 }
1136 }
1137
1138 return active;
1139 }
1140
1141 /* set a timer for EOF */
1142 static void ohci_eof_timer(OHCIState *ohci)
1143 {
1144 timer_mod(ohci->eof_timer, ohci->sof_time + usb_frame_time);
1145 }
1146 /* Set a timer for EOF and generate a SOF event */
1147 static void ohci_sof(OHCIState *ohci)
1148 {
1149 ohci->sof_time += usb_frame_time;
1150 ohci_eof_timer(ohci);
1151 ohci_set_interrupt(ohci, OHCI_INTR_SF);
1152 }
1153
1154 /* Process Control and Bulk lists. */
1155 static void ohci_process_lists(OHCIState *ohci)
1156 {
1157 if ((ohci->ctl & OHCI_CTL_CLE) && (ohci->status & OHCI_STATUS_CLF)) {
1158 if (ohci->ctrl_cur && ohci->ctrl_cur != ohci->ctrl_head) {
1159 trace_usb_ohci_process_lists(ohci->ctrl_head, ohci->ctrl_cur);
1160 }
1161 if (!ohci_service_ed_list(ohci, ohci->ctrl_head)) {
1162 ohci->ctrl_cur = 0;
1163 ohci->status &= ~OHCI_STATUS_CLF;
1164 }
1165 }
1166
1167 if ((ohci->ctl & OHCI_CTL_BLE) && (ohci->status & OHCI_STATUS_BLF)) {
1168 if (!ohci_service_ed_list(ohci, ohci->bulk_head)) {
1169 ohci->bulk_cur = 0;
1170 ohci->status &= ~OHCI_STATUS_BLF;
1171 }
1172 }
1173 }
1174
1175 /* Do frame processing on frame boundary */
1176 static void ohci_frame_boundary(void *opaque)
1177 {
1178 OHCIState *ohci = opaque;
1179 struct ohci_hcca hcca;
1180
1181 if (ohci_read_hcca(ohci, ohci->hcca, &hcca)) {
1182 trace_usb_ohci_hcca_read_error(ohci->hcca);
1183 ohci_die(ohci);
1184 return;
1185 }
1186
1187 /* Process all the lists at the end of the frame */
1188 if (ohci->ctl & OHCI_CTL_PLE) {
1189 int n;
1190
1191 n = ohci->frame_number & 0x1f;
1192 ohci_service_ed_list(ohci, le32_to_cpu(hcca.intr[n]));
1193 }
1194
1195 /* Cancel all pending packets if either of the lists has been disabled. */
1196 if (ohci->old_ctl & (~ohci->ctl) & (OHCI_CTL_BLE | OHCI_CTL_CLE)) {
1197 ohci_stop_endpoints(ohci);
1198 }
1199 ohci->old_ctl = ohci->ctl;
1200 ohci_process_lists(ohci);
1201
1202 /* Stop if UnrecoverableError happened or ohci_sof will crash */
1203 if (ohci->intr_status & OHCI_INTR_UE) {
1204 return;
1205 }
1206
1207 /* Frame boundary, so do EOF stuf here */
1208 ohci->frt = ohci->fit;
1209
1210 /* Increment frame number and take care of endianness. */
1211 ohci->frame_number = (ohci->frame_number + 1) & 0xffff;
1212 hcca.frame = cpu_to_le16(ohci->frame_number);
1213
1214 if (ohci->done_count == 0 && !(ohci->intr_status & OHCI_INTR_WD)) {
1215 if (!ohci->done)
1216 abort();
1217 if (ohci->intr & ohci->intr_status)
1218 ohci->done |= 1;
1219 hcca.done = cpu_to_le32(ohci->done);
1220 ohci->done = 0;
1221 ohci->done_count = 7;
1222 ohci_set_interrupt(ohci, OHCI_INTR_WD);
1223 }
1224
1225 if (ohci->done_count != 7 && ohci->done_count != 0)
1226 ohci->done_count--;
1227
1228 /* Do SOF stuff here */
1229 ohci_sof(ohci);
1230
1231 /* Writeback HCCA */
1232 if (ohci_put_hcca(ohci, ohci->hcca, &hcca)) {
1233 ohci_die(ohci);
1234 }
1235 }
1236
1237 /* Start sending SOF tokens across the USB bus, lists are processed in
1238 * next frame
1239 */
1240 static int ohci_bus_start(OHCIState *ohci)
1241 {
1242 trace_usb_ohci_start(ohci->name);
1243
1244 /* Delay the first SOF event by one frame time as
1245 * linux driver is not ready to receive it and
1246 * can meet some race conditions
1247 */
1248
1249 ohci->sof_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1250 ohci_eof_timer(ohci);
1251
1252 return 1;
1253 }
1254
1255 /* Stop sending SOF tokens on the bus */
1256 void ohci_bus_stop(OHCIState *ohci)
1257 {
1258 trace_usb_ohci_stop(ohci->name);
1259 timer_del(ohci->eof_timer);
1260 }
1261
1262 /* Sets a flag in a port status register but only set it if the port is
1263 * connected, if not set ConnectStatusChange flag. If flag is enabled
1264 * return 1.
1265 */
1266 static int ohci_port_set_if_connected(OHCIState *ohci, int i, uint32_t val)
1267 {
1268 int ret = 1;
1269
1270 /* writing a 0 has no effect */
1271 if (val == 0)
1272 return 0;
1273
1274 /* If CurrentConnectStatus is cleared we set
1275 * ConnectStatusChange
1276 */
1277 if (!(ohci->rhport[i].ctrl & OHCI_PORT_CCS)) {
1278 ohci->rhport[i].ctrl |= OHCI_PORT_CSC;
1279 if (ohci->rhstatus & OHCI_RHS_DRWE) {
1280 /* TODO: CSC is a wakeup event */
1281 }
1282 return 0;
1283 }
1284
1285 if (ohci->rhport[i].ctrl & val)
1286 ret = 0;
1287
1288 /* set the bit */
1289 ohci->rhport[i].ctrl |= val;
1290
1291 return ret;
1292 }
1293
1294 /* Set the frame interval - frame interval toggle is manipulated by the hcd only */
1295 static void ohci_set_frame_interval(OHCIState *ohci, uint16_t val)
1296 {
1297 val &= OHCI_FMI_FI;
1298
1299 if (val != ohci->fi) {
1300 trace_usb_ohci_set_frame_interval(ohci->name, ohci->fi, ohci->fi);
1301 }
1302
1303 ohci->fi = val;
1304 }
1305
1306 static void ohci_port_power(OHCIState *ohci, int i, int p)
1307 {
1308 if (p) {
1309 ohci->rhport[i].ctrl |= OHCI_PORT_PPS;
1310 } else {
1311 ohci->rhport[i].ctrl &= ~(OHCI_PORT_PPS|
1312 OHCI_PORT_CCS|
1313 OHCI_PORT_PSS|
1314 OHCI_PORT_PRS);
1315 }
1316 }
1317
1318 /* Set HcControlRegister */
1319 static void ohci_set_ctl(OHCIState *ohci, uint32_t val)
1320 {
1321 uint32_t old_state;
1322 uint32_t new_state;
1323
1324 old_state = ohci->ctl & OHCI_CTL_HCFS;
1325 ohci->ctl = val;
1326 new_state = ohci->ctl & OHCI_CTL_HCFS;
1327
1328 /* no state change */
1329 if (old_state == new_state)
1330 return;
1331
1332 trace_usb_ohci_set_ctl(ohci->name, new_state);
1333 switch (new_state) {
1334 case OHCI_USB_OPERATIONAL:
1335 ohci_bus_start(ohci);
1336 break;
1337 case OHCI_USB_SUSPEND:
1338 ohci_bus_stop(ohci);
1339 /* clear pending SF otherwise linux driver loops in ohci_irq() */
1340 ohci->intr_status &= ~OHCI_INTR_SF;
1341 ohci_intr_update(ohci);
1342 break;
1343 case OHCI_USB_RESUME:
1344 trace_usb_ohci_resume(ohci->name);
1345 break;
1346 case OHCI_USB_RESET:
1347 ohci_roothub_reset(ohci);
1348 break;
1349 }
1350 }
1351
1352 static uint32_t ohci_get_frame_remaining(OHCIState *ohci)
1353 {
1354 uint16_t fr;
1355 int64_t tks;
1356
1357 if ((ohci->ctl & OHCI_CTL_HCFS) != OHCI_USB_OPERATIONAL)
1358 return (ohci->frt << 31);
1359
1360 /* Being in USB operational state guarnatees sof_time was
1361 * set already.
1362 */
1363 tks = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - ohci->sof_time;
1364 if (tks < 0) {
1365 tks = 0;
1366 }
1367
1368 /* avoid muldiv if possible */
1369 if (tks >= usb_frame_time)
1370 return (ohci->frt << 31);
1371
1372 tks = tks / usb_bit_time;
1373 fr = (uint16_t)(ohci->fi - tks);
1374
1375 return (ohci->frt << 31) | fr;
1376 }
1377
1378
1379 /* Set root hub status */
1380 static void ohci_set_hub_status(OHCIState *ohci, uint32_t val)
1381 {
1382 uint32_t old_state;
1383
1384 old_state = ohci->rhstatus;
1385
1386 /* write 1 to clear OCIC */
1387 if (val & OHCI_RHS_OCIC)
1388 ohci->rhstatus &= ~OHCI_RHS_OCIC;
1389
1390 if (val & OHCI_RHS_LPS) {
1391 int i;
1392
1393 for (i = 0; i < ohci->num_ports; i++)
1394 ohci_port_power(ohci, i, 0);
1395 trace_usb_ohci_hub_power_down();
1396 }
1397
1398 if (val & OHCI_RHS_LPSC) {
1399 int i;
1400
1401 for (i = 0; i < ohci->num_ports; i++)
1402 ohci_port_power(ohci, i, 1);
1403 trace_usb_ohci_hub_power_up();
1404 }
1405
1406 if (val & OHCI_RHS_DRWE)
1407 ohci->rhstatus |= OHCI_RHS_DRWE;
1408
1409 if (val & OHCI_RHS_CRWE)
1410 ohci->rhstatus &= ~OHCI_RHS_DRWE;
1411
1412 if (old_state != ohci->rhstatus)
1413 ohci_set_interrupt(ohci, OHCI_INTR_RHSC);
1414 }
1415
1416 /* Set root hub port status */
1417 static void ohci_port_set_status(OHCIState *ohci, int portnum, uint32_t val)
1418 {
1419 uint32_t old_state;
1420 OHCIPort *port;
1421
1422 port = &ohci->rhport[portnum];
1423 old_state = port->ctrl;
1424
1425 /* Write to clear CSC, PESC, PSSC, OCIC, PRSC */
1426 if (val & OHCI_PORT_WTC)
1427 port->ctrl &= ~(val & OHCI_PORT_WTC);
1428
1429 if (val & OHCI_PORT_CCS)
1430 port->ctrl &= ~OHCI_PORT_PES;
1431
1432 ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PES);
1433
1434 if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PSS)) {
1435 trace_usb_ohci_port_suspend(portnum);
1436 }
1437
1438 if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PRS)) {
1439 trace_usb_ohci_port_reset(portnum);
1440 usb_device_reset(port->port.dev);
1441 port->ctrl &= ~OHCI_PORT_PRS;
1442 /* ??? Should this also set OHCI_PORT_PESC. */
1443 port->ctrl |= OHCI_PORT_PES | OHCI_PORT_PRSC;
1444 }
1445
1446 /* Invert order here to ensure in ambiguous case, device is
1447 * powered up...
1448 */
1449 if (val & OHCI_PORT_LSDA)
1450 ohci_port_power(ohci, portnum, 0);
1451 if (val & OHCI_PORT_PPS)
1452 ohci_port_power(ohci, portnum, 1);
1453
1454 if (old_state != port->ctrl)
1455 ohci_set_interrupt(ohci, OHCI_INTR_RHSC);
1456 }
1457
1458 static uint64_t ohci_mem_read(void *opaque,
1459 hwaddr addr,
1460 unsigned size)
1461 {
1462 OHCIState *ohci = opaque;
1463 uint32_t retval;
1464
1465 /* Only aligned reads are allowed on OHCI */
1466 if (addr & 3) {
1467 trace_usb_ohci_mem_read_unaligned(addr);
1468 return 0xffffffff;
1469 } else if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) {
1470 /* HcRhPortStatus */
1471 retval = ohci->rhport[(addr - 0x54) >> 2].ctrl | OHCI_PORT_PPS;
1472 } else {
1473 switch (addr >> 2) {
1474 case 0: /* HcRevision */
1475 retval = 0x10;
1476 break;
1477
1478 case 1: /* HcControl */
1479 retval = ohci->ctl;
1480 break;
1481
1482 case 2: /* HcCommandStatus */
1483 retval = ohci->status;
1484 break;
1485
1486 case 3: /* HcInterruptStatus */
1487 retval = ohci->intr_status;
1488 break;
1489
1490 case 4: /* HcInterruptEnable */
1491 case 5: /* HcInterruptDisable */
1492 retval = ohci->intr;
1493 break;
1494
1495 case 6: /* HcHCCA */
1496 retval = ohci->hcca;
1497 break;
1498
1499 case 7: /* HcPeriodCurrentED */
1500 retval = ohci->per_cur;
1501 break;
1502
1503 case 8: /* HcControlHeadED */
1504 retval = ohci->ctrl_head;
1505 break;
1506
1507 case 9: /* HcControlCurrentED */
1508 retval = ohci->ctrl_cur;
1509 break;
1510
1511 case 10: /* HcBulkHeadED */
1512 retval = ohci->bulk_head;
1513 break;
1514
1515 case 11: /* HcBulkCurrentED */
1516 retval = ohci->bulk_cur;
1517 break;
1518
1519 case 12: /* HcDoneHead */
1520 retval = ohci->done;
1521 break;
1522
1523 case 13: /* HcFmInterretval */
1524 retval = (ohci->fit << 31) | (ohci->fsmps << 16) | (ohci->fi);
1525 break;
1526
1527 case 14: /* HcFmRemaining */
1528 retval = ohci_get_frame_remaining(ohci);
1529 break;
1530
1531 case 15: /* HcFmNumber */
1532 retval = ohci->frame_number;
1533 break;
1534
1535 case 16: /* HcPeriodicStart */
1536 retval = ohci->pstart;
1537 break;
1538
1539 case 17: /* HcLSThreshold */
1540 retval = ohci->lst;
1541 break;
1542
1543 case 18: /* HcRhDescriptorA */
1544 retval = ohci->rhdesc_a;
1545 break;
1546
1547 case 19: /* HcRhDescriptorB */
1548 retval = ohci->rhdesc_b;
1549 break;
1550
1551 case 20: /* HcRhStatus */
1552 retval = ohci->rhstatus;
1553 break;
1554
1555 /* PXA27x specific registers */
1556 case 24: /* HcStatus */
1557 retval = ohci->hstatus & ohci->hmask;
1558 break;
1559
1560 case 25: /* HcHReset */
1561 retval = ohci->hreset;
1562 break;
1563
1564 case 26: /* HcHInterruptEnable */
1565 retval = ohci->hmask;
1566 break;
1567
1568 case 27: /* HcHInterruptTest */
1569 retval = ohci->htest;
1570 break;
1571
1572 default:
1573 trace_usb_ohci_mem_read_bad_offset(addr);
1574 retval = 0xffffffff;
1575 }
1576 }
1577
1578 return retval;
1579 }
1580
1581 static void ohci_mem_write(void *opaque,
1582 hwaddr addr,
1583 uint64_t val,
1584 unsigned size)
1585 {
1586 OHCIState *ohci = opaque;
1587
1588 /* Only aligned reads are allowed on OHCI */
1589 if (addr & 3) {
1590 trace_usb_ohci_mem_write_unaligned(addr);
1591 return;
1592 }
1593
1594 if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) {
1595 /* HcRhPortStatus */
1596 ohci_port_set_status(ohci, (addr - 0x54) >> 2, val);
1597 return;
1598 }
1599
1600 switch (addr >> 2) {
1601 case 1: /* HcControl */
1602 ohci_set_ctl(ohci, val);
1603 break;
1604
1605 case 2: /* HcCommandStatus */
1606 /* SOC is read-only */
1607 val = (val & ~OHCI_STATUS_SOC);
1608
1609 /* Bits written as '0' remain unchanged in the register */
1610 ohci->status |= val;
1611
1612 if (ohci->status & OHCI_STATUS_HCR)
1613 ohci_soft_reset(ohci);
1614 break;
1615
1616 case 3: /* HcInterruptStatus */
1617 ohci->intr_status &= ~val;
1618 ohci_intr_update(ohci);
1619 break;
1620
1621 case 4: /* HcInterruptEnable */
1622 ohci->intr |= val;
1623 ohci_intr_update(ohci);
1624 break;
1625
1626 case 5: /* HcInterruptDisable */
1627 ohci->intr &= ~val;
1628 ohci_intr_update(ohci);
1629 break;
1630
1631 case 6: /* HcHCCA */
1632 ohci->hcca = val & OHCI_HCCA_MASK;
1633 break;
1634
1635 case 7: /* HcPeriodCurrentED */
1636 /* Ignore writes to this read-only register, Linux does them */
1637 break;
1638
1639 case 8: /* HcControlHeadED */
1640 ohci->ctrl_head = val & OHCI_EDPTR_MASK;
1641 break;
1642
1643 case 9: /* HcControlCurrentED */
1644 ohci->ctrl_cur = val & OHCI_EDPTR_MASK;
1645 break;
1646
1647 case 10: /* HcBulkHeadED */
1648 ohci->bulk_head = val & OHCI_EDPTR_MASK;
1649 break;
1650
1651 case 11: /* HcBulkCurrentED */
1652 ohci->bulk_cur = val & OHCI_EDPTR_MASK;
1653 break;
1654
1655 case 13: /* HcFmInterval */
1656 ohci->fsmps = (val & OHCI_FMI_FSMPS) >> 16;
1657 ohci->fit = (val & OHCI_FMI_FIT) >> 31;
1658 ohci_set_frame_interval(ohci, val);
1659 break;
1660
1661 case 15: /* HcFmNumber */
1662 break;
1663
1664 case 16: /* HcPeriodicStart */
1665 ohci->pstart = val & 0xffff;
1666 break;
1667
1668 case 17: /* HcLSThreshold */
1669 ohci->lst = val & 0xffff;
1670 break;
1671
1672 case 18: /* HcRhDescriptorA */
1673 ohci->rhdesc_a &= ~OHCI_RHA_RW_MASK;
1674 ohci->rhdesc_a |= val & OHCI_RHA_RW_MASK;
1675 break;
1676
1677 case 19: /* HcRhDescriptorB */
1678 break;
1679
1680 case 20: /* HcRhStatus */
1681 ohci_set_hub_status(ohci, val);
1682 break;
1683
1684 /* PXA27x specific registers */
1685 case 24: /* HcStatus */
1686 ohci->hstatus &= ~(val & ohci->hmask);
1687 break;
1688
1689 case 25: /* HcHReset */
1690 ohci->hreset = val & ~OHCI_HRESET_FSBIR;
1691 if (val & OHCI_HRESET_FSBIR)
1692 ohci_hard_reset(ohci);
1693 break;
1694
1695 case 26: /* HcHInterruptEnable */
1696 ohci->hmask = val;
1697 break;
1698
1699 case 27: /* HcHInterruptTest */
1700 ohci->htest = val;
1701 break;
1702
1703 default:
1704 trace_usb_ohci_mem_write_bad_offset(addr);
1705 break;
1706 }
1707 }
1708
1709 static const MemoryRegionOps ohci_mem_ops = {
1710 .read = ohci_mem_read,
1711 .write = ohci_mem_write,
1712 .endianness = DEVICE_LITTLE_ENDIAN,
1713 };
1714
1715 /* USBPortOps */
1716 static void ohci_attach(USBPort *port1)
1717 {
1718 OHCIState *s = port1->opaque;
1719 OHCIPort *port = &s->rhport[port1->index];
1720 uint32_t old_state = port->ctrl;
1721
1722 /* set connect status */
1723 port->ctrl |= OHCI_PORT_CCS | OHCI_PORT_CSC;
1724
1725 /* update speed */
1726 if (port->port.dev->speed == USB_SPEED_LOW) {
1727 port->ctrl |= OHCI_PORT_LSDA;
1728 } else {
1729 port->ctrl &= ~OHCI_PORT_LSDA;
1730 }
1731
1732 /* notify of remote-wakeup */
1733 if ((s->ctl & OHCI_CTL_HCFS) == OHCI_USB_SUSPEND) {
1734 ohci_set_interrupt(s, OHCI_INTR_RD);
1735 }
1736
1737 trace_usb_ohci_port_attach(port1->index);
1738
1739 if (old_state != port->ctrl) {
1740 ohci_set_interrupt(s, OHCI_INTR_RHSC);
1741 }
1742 }
1743
1744 static void ohci_child_detach(USBPort *port1, USBDevice *dev)
1745 {
1746 OHCIState *ohci = port1->opaque;
1747
1748 if (ohci->async_td &&
1749 usb_packet_is_inflight(&ohci->usb_packet) &&
1750 ohci->usb_packet.ep->dev == dev) {
1751 usb_cancel_packet(&ohci->usb_packet);
1752 ohci->async_td = 0;
1753 }
1754 }
1755
1756 static void ohci_detach(USBPort *port1)
1757 {
1758 OHCIState *s = port1->opaque;
1759 OHCIPort *port = &s->rhport[port1->index];
1760 uint32_t old_state = port->ctrl;
1761
1762 ohci_child_detach(port1, port1->dev);
1763
1764 /* set connect status */
1765 if (port->ctrl & OHCI_PORT_CCS) {
1766 port->ctrl &= ~OHCI_PORT_CCS;
1767 port->ctrl |= OHCI_PORT_CSC;
1768 }
1769 /* disable port */
1770 if (port->ctrl & OHCI_PORT_PES) {
1771 port->ctrl &= ~OHCI_PORT_PES;
1772 port->ctrl |= OHCI_PORT_PESC;
1773 }
1774 trace_usb_ohci_port_detach(port1->index);
1775
1776 if (old_state != port->ctrl) {
1777 ohci_set_interrupt(s, OHCI_INTR_RHSC);
1778 }
1779 }
1780
1781 static void ohci_wakeup(USBPort *port1)
1782 {
1783 OHCIState *s = port1->opaque;
1784 OHCIPort *port = &s->rhport[port1->index];
1785 uint32_t intr = 0;
1786 if (port->ctrl & OHCI_PORT_PSS) {
1787 trace_usb_ohci_port_wakeup(port1->index);
1788 port->ctrl |= OHCI_PORT_PSSC;
1789 port->ctrl &= ~OHCI_PORT_PSS;
1790 intr = OHCI_INTR_RHSC;
1791 }
1792 /* Note that the controller can be suspended even if this port is not */
1793 if ((s->ctl & OHCI_CTL_HCFS) == OHCI_USB_SUSPEND) {
1794 trace_usb_ohci_remote_wakeup(s->name);
1795 /* This is the one state transition the controller can do by itself */
1796 s->ctl &= ~OHCI_CTL_HCFS;
1797 s->ctl |= OHCI_USB_RESUME;
1798 /*
1799 * In suspend mode only ResumeDetected is possible, not RHSC:
1800 * see the OHCI spec 5.1.2.3.
1801 */
1802 intr = OHCI_INTR_RD;
1803 }
1804 ohci_set_interrupt(s, intr);
1805 }
1806
1807 static void ohci_async_complete_packet(USBPort *port, USBPacket *packet)
1808 {
1809 OHCIState *ohci = container_of(packet, OHCIState, usb_packet);
1810
1811 trace_usb_ohci_async_complete();
1812 ohci->async_complete = true;
1813 ohci_process_lists(ohci);
1814 }
1815
1816 static USBPortOps ohci_port_ops = {
1817 .attach = ohci_attach,
1818 .detach = ohci_detach,
1819 .child_detach = ohci_child_detach,
1820 .wakeup = ohci_wakeup,
1821 .complete = ohci_async_complete_packet,
1822 };
1823
1824 static USBBusOps ohci_bus_ops = {
1825 };
1826
1827 void usb_ohci_init(OHCIState *ohci, DeviceState *dev, uint32_t num_ports,
1828 dma_addr_t localmem_base, char *masterbus,
1829 uint32_t firstport, AddressSpace *as,
1830 void (*ohci_die_fn)(struct OHCIState *), Error **errp)
1831 {
1832 Error *err = NULL;
1833 int i;
1834
1835 ohci->as = as;
1836 ohci->ohci_die = ohci_die_fn;
1837
1838 if (num_ports > OHCI_MAX_PORTS) {
1839 error_setg(errp, "OHCI num-ports=%u is too big (limit is %u ports)",
1840 num_ports, OHCI_MAX_PORTS);
1841 return;
1842 }
1843
1844 if (usb_frame_time == 0) {
1845 #ifdef OHCI_TIME_WARP
1846 usb_frame_time = NANOSECONDS_PER_SECOND;
1847 usb_bit_time = NANOSECONDS_PER_SECOND / (USB_HZ / 1000);
1848 #else
1849 usb_frame_time = NANOSECONDS_PER_SECOND / 1000;
1850 if (NANOSECONDS_PER_SECOND >= USB_HZ) {
1851 usb_bit_time = NANOSECONDS_PER_SECOND / USB_HZ;
1852 } else {
1853 usb_bit_time = 1;
1854 }
1855 #endif
1856 trace_usb_ohci_init_time(usb_frame_time, usb_bit_time);
1857 }
1858
1859 ohci->num_ports = num_ports;
1860 if (masterbus) {
1861 USBPort *ports[OHCI_MAX_PORTS];
1862 for(i = 0; i < num_ports; i++) {
1863 ports[i] = &ohci->rhport[i].port;
1864 }
1865 usb_register_companion(masterbus, ports, num_ports,
1866 firstport, ohci, &ohci_port_ops,
1867 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL,
1868 &err);
1869 if (err) {
1870 error_propagate(errp, err);
1871 return;
1872 }
1873 } else {
1874 usb_bus_new(&ohci->bus, sizeof(ohci->bus), &ohci_bus_ops, dev);
1875 for (i = 0; i < num_ports; i++) {
1876 usb_register_port(&ohci->bus, &ohci->rhport[i].port,
1877 ohci, i, &ohci_port_ops,
1878 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL);
1879 }
1880 }
1881
1882 memory_region_init_io(&ohci->mem, OBJECT(dev), &ohci_mem_ops,
1883 ohci, "ohci", 256);
1884 ohci->localmem_base = localmem_base;
1885
1886 ohci->name = object_get_typename(OBJECT(dev));
1887 usb_packet_init(&ohci->usb_packet);
1888
1889 ohci->async_td = 0;
1890
1891 ohci->eof_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
1892 ohci_frame_boundary, ohci);
1893 }
1894
1895 /**
1896 * A typical OHCI will stop operating and set itself into error state
1897 * (which can be queried by MMIO) to signal that it got an error.
1898 */
1899 void ohci_sysbus_die(struct OHCIState *ohci)
1900 {
1901 trace_usb_ohci_die();
1902
1903 ohci_set_interrupt(ohci, OHCI_INTR_UE);
1904 ohci_bus_stop(ohci);
1905 }
1906
1907 static void ohci_realize_pxa(DeviceState *dev, Error **errp)
1908 {
1909 OHCISysBusState *s = SYSBUS_OHCI(dev);
1910 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1911 Error *err = NULL;
1912
1913 usb_ohci_init(&s->ohci, dev, s->num_ports, s->dma_offset,
1914 s->masterbus, s->firstport,
1915 &address_space_memory, ohci_sysbus_die, &err);
1916 if (err) {
1917 error_propagate(errp, err);
1918 return;
1919 }
1920 sysbus_init_irq(sbd, &s->ohci.irq);
1921 sysbus_init_mmio(sbd, &s->ohci.mem);
1922 }
1923
1924 static void usb_ohci_reset_sysbus(DeviceState *dev)
1925 {
1926 OHCISysBusState *s = SYSBUS_OHCI(dev);
1927 OHCIState *ohci = &s->ohci;
1928
1929 ohci_hard_reset(ohci);
1930 }
1931
1932 static const VMStateDescription vmstate_ohci_state_port = {
1933 .name = "ohci-core/port",
1934 .version_id = 1,
1935 .minimum_version_id = 1,
1936 .fields = (VMStateField[]) {
1937 VMSTATE_UINT32(ctrl, OHCIPort),
1938 VMSTATE_END_OF_LIST()
1939 },
1940 };
1941
1942 static bool ohci_eof_timer_needed(void *opaque)
1943 {
1944 OHCIState *ohci = opaque;
1945
1946 return timer_pending(ohci->eof_timer);
1947 }
1948
1949 static const VMStateDescription vmstate_ohci_eof_timer = {
1950 .name = "ohci-core/eof-timer",
1951 .version_id = 1,
1952 .minimum_version_id = 1,
1953 .needed = ohci_eof_timer_needed,
1954 .fields = (VMStateField[]) {
1955 VMSTATE_TIMER_PTR(eof_timer, OHCIState),
1956 VMSTATE_END_OF_LIST()
1957 },
1958 };
1959
1960 const VMStateDescription vmstate_ohci_state = {
1961 .name = "ohci-core",
1962 .version_id = 1,
1963 .minimum_version_id = 1,
1964 .fields = (VMStateField[]) {
1965 VMSTATE_INT64(sof_time, OHCIState),
1966 VMSTATE_UINT32(ctl, OHCIState),
1967 VMSTATE_UINT32(status, OHCIState),
1968 VMSTATE_UINT32(intr_status, OHCIState),
1969 VMSTATE_UINT32(intr, OHCIState),
1970 VMSTATE_UINT32(hcca, OHCIState),
1971 VMSTATE_UINT32(ctrl_head, OHCIState),
1972 VMSTATE_UINT32(ctrl_cur, OHCIState),
1973 VMSTATE_UINT32(bulk_head, OHCIState),
1974 VMSTATE_UINT32(bulk_cur, OHCIState),
1975 VMSTATE_UINT32(per_cur, OHCIState),
1976 VMSTATE_UINT32(done, OHCIState),
1977 VMSTATE_INT32(done_count, OHCIState),
1978 VMSTATE_UINT16(fsmps, OHCIState),
1979 VMSTATE_UINT8(fit, OHCIState),
1980 VMSTATE_UINT16(fi, OHCIState),
1981 VMSTATE_UINT8(frt, OHCIState),
1982 VMSTATE_UINT16(frame_number, OHCIState),
1983 VMSTATE_UINT16(padding, OHCIState),
1984 VMSTATE_UINT32(pstart, OHCIState),
1985 VMSTATE_UINT32(lst, OHCIState),
1986 VMSTATE_UINT32(rhdesc_a, OHCIState),
1987 VMSTATE_UINT32(rhdesc_b, OHCIState),
1988 VMSTATE_UINT32(rhstatus, OHCIState),
1989 VMSTATE_STRUCT_ARRAY(rhport, OHCIState, OHCI_MAX_PORTS, 0,
1990 vmstate_ohci_state_port, OHCIPort),
1991 VMSTATE_UINT32(hstatus, OHCIState),
1992 VMSTATE_UINT32(hmask, OHCIState),
1993 VMSTATE_UINT32(hreset, OHCIState),
1994 VMSTATE_UINT32(htest, OHCIState),
1995 VMSTATE_UINT32(old_ctl, OHCIState),
1996 VMSTATE_UINT8_ARRAY(usb_buf, OHCIState, 8192),
1997 VMSTATE_UINT32(async_td, OHCIState),
1998 VMSTATE_BOOL(async_complete, OHCIState),
1999 VMSTATE_END_OF_LIST()
2000 },
2001 .subsections = (const VMStateDescription*[]) {
2002 &vmstate_ohci_eof_timer,
2003 NULL
2004 }
2005 };
2006
2007 static Property ohci_sysbus_properties[] = {
2008 DEFINE_PROP_STRING("masterbus", OHCISysBusState, masterbus),
2009 DEFINE_PROP_UINT32("num-ports", OHCISysBusState, num_ports, 3),
2010 DEFINE_PROP_UINT32("firstport", OHCISysBusState, firstport, 0),
2011 DEFINE_PROP_DMAADDR("dma-offset", OHCISysBusState, dma_offset, 0),
2012 DEFINE_PROP_END_OF_LIST(),
2013 };
2014
2015 static void ohci_sysbus_class_init(ObjectClass *klass, void *data)
2016 {
2017 DeviceClass *dc = DEVICE_CLASS(klass);
2018
2019 dc->realize = ohci_realize_pxa;
2020 set_bit(DEVICE_CATEGORY_USB, dc->categories);
2021 dc->desc = "OHCI USB Controller";
2022 device_class_set_props(dc, ohci_sysbus_properties);
2023 dc->reset = usb_ohci_reset_sysbus;
2024 }
2025
2026 static const TypeInfo ohci_sysbus_info = {
2027 .name = TYPE_SYSBUS_OHCI,
2028 .parent = TYPE_SYS_BUS_DEVICE,
2029 .instance_size = sizeof(OHCISysBusState),
2030 .class_init = ohci_sysbus_class_init,
2031 };
2032
2033 static void ohci_register_types(void)
2034 {
2035 type_register_static(&ohci_sysbus_info);
2036 }
2037
2038 type_init(ohci_register_types)
QEmu