hw/cxl/cxl-host.c

   1 /*
   2  * CXL host parameter parsing routines
   3  *
   4  * Copyright (c) 2022 Huawei
   5  * Modeled loosely on the NUMA options handling in hw/core/numa.c
   6  */
   7
   8 #include "qemu/osdep.h"
   9 #include "qemu/units.h"
  10 #include "qemu/bitmap.h"
  11 #include "qemu/error-report.h"
  12 #include "qapi/error.h"
  13 #include "sysemu/qtest.h"
  14 #include "hw/boards.h"
  15
  16 #include "qapi/qapi-visit-machine.h"
  17 #include "hw/cxl/cxl.h"
  18 #include "hw/cxl/cxl_host.h"
  19 #include "hw/pci/pci_bus.h"
  20 #include "hw/pci/pci_bridge.h"
  21 #include "hw/pci/pci_host.h"
  22 #include "hw/pci/pcie_port.h"
  23 #include "hw/pci-bridge/pci_expander_bridge.h"
  24
  25 static void cxl_fixed_memory_window_config(CXLState *cxl_state,
  26                                            CXLFixedMemoryWindowOptions *object,
  27                                            Error **errp)
  28 {
  29     g_autofree CXLFixedWindow *fw = g_malloc0(sizeof(*fw));
  30     strList *target;
  31     int i;
  32
  33     for (target = object->targets; target; target = target->next) {
  34         fw->num_targets++;
  35     }
  36
  37     fw->enc_int_ways = cxl_interleave_ways_enc(fw->num_targets, errp);
  38     if (*errp) {
  39         return;
  40     }
  41
  42     fw->targets = g_malloc0_n(fw->num_targets, sizeof(*fw->targets));
  43     for (i = 0, target = object->targets; target; i++, target = target->next) {
  44         /* This link cannot be resolved yet, so stash the name for now */
  45         fw->targets[i] = g_strdup(target->value);
  46     }
  47
  48     if (object->size % (256 * MiB)) {
  49         error_setg(errp,
  50                    "Size of a CXL fixed memory window must my a multiple of 256MiB");
  51         return;
  52     }
  53     fw->size = object->size;
  54
  55     if (object->has_interleave_granularity) {
  56         fw->enc_int_gran =
  57             cxl_interleave_granularity_enc(object->interleave_granularity,
  58                                            errp);
  59         if (*errp) {
  60             return;
  61         }
  62     } else {
  63         /* Default to 256 byte interleave */
  64         fw->enc_int_gran = 0;
  65     }
  66
  67     cxl_state->fixed_windows = g_list_append(cxl_state->fixed_windows,
  68                                              g_steal_pointer(&fw));
  69
  70     return;
  71 }
  72
  73 void cxl_fmws_link_targets(CXLState *cxl_state, Error **errp)
  74 {
  75     if (cxl_state && cxl_state->fixed_windows) {
  76         GList *it;
  77
  78         for (it = cxl_state->fixed_windows; it; it = it->next) {
  79             CXLFixedWindow *fw = it->data;
  80             int i;
  81
  82             for (i = 0; i < fw->num_targets; i++) {
  83                 Object *o;
  84                 bool ambig;
  85
  86                 o = object_resolve_path_type(fw->targets[i],
  87                                              TYPE_PXB_CXL_DEVICE,
  88                                              &ambig);
  89                 if (!o) {
  90                     error_setg(errp, "Could not resolve CXLFM target %s",
  91                                fw->targets[i]);
  92                     return;
  93                 }
  94                 fw->target_hbs[i] = PXB_CXL_DEV(o);
  95             }
  96         }
  97     }
  98 }
  99
 100 /* TODO: support, multiple hdm decoders */
 101 static bool cxl_hdm_find_target(uint32_t *cache_mem, hwaddr addr,
 102                                 uint8_t *target)
 103 {
 104     uint32_t ctrl;
 105     uint32_t ig_enc;
 106     uint32_t iw_enc;
 107     uint32_t target_idx;
 108
 109     ctrl = cache_mem[R_CXL_HDM_DECODER0_CTRL];
 110     if (!FIELD_EX32(ctrl, CXL_HDM_DECODER0_CTRL, COMMITTED)) {
 111         return false;
 112     }
 113
 114     ig_enc = FIELD_EX32(ctrl, CXL_HDM_DECODER0_CTRL, IG);
 115     iw_enc = FIELD_EX32(ctrl, CXL_HDM_DECODER0_CTRL, IW);
 116     target_idx = (addr / cxl_decode_ig(ig_enc)) % (1 << iw_enc);
 117
 118     if (target_idx < 4) {
 119         *target = extract32(cache_mem[R_CXL_HDM_DECODER0_TARGET_LIST_LO],
 120                             target_idx * 8, 8);
 121     } else {
 122         *target = extract32(cache_mem[R_CXL_HDM_DECODER0_TARGET_LIST_HI],
 123                             (target_idx - 4) * 8, 8);
 124     }
 125
 126     return true;
 127 }
 128
 129 static PCIDevice *cxl_cfmws_find_device(CXLFixedWindow *fw, hwaddr addr)
 130 {
 131     CXLComponentState *hb_cstate, *usp_cstate;
 132     PCIHostState *hb;
 133     CXLUpstreamPort *usp;
 134     int rb_index;
 135     uint32_t *cache_mem;
 136     uint8_t target;
 137     bool target_found;
 138     PCIDevice *rp, *d;
 139
 140     /* Address is relative to memory region. Convert to HPA */
 141     addr += fw->base;
 142
 143     rb_index = (addr / cxl_decode_ig(fw->enc_int_gran)) % fw->num_targets;
 144     hb = PCI_HOST_BRIDGE(fw->target_hbs[rb_index]->cxl.cxl_host_bridge);
 145     if (!hb || !hb->bus || !pci_bus_is_cxl(hb->bus)) {
 146         return NULL;
 147     }
 148
 149     hb_cstate = cxl_get_hb_cstate(hb);
 150     if (!hb_cstate) {
 151         return NULL;
 152     }
 153
 154     cache_mem = hb_cstate->crb.cache_mem_registers;
 155
 156     target_found = cxl_hdm_find_target(cache_mem, addr, &target);
 157     if (!target_found) {
 158         return NULL;
 159     }
 160
 161     rp = pcie_find_port_by_pn(hb->bus, target);
 162     if (!rp) {
 163         return NULL;
 164     }
 165
 166     d = pci_bridge_get_sec_bus(PCI_BRIDGE(rp))->devices[0];
 167     if (!d) {
 168         return NULL;
 169     }
 170
 171     if (object_dynamic_cast(OBJECT(d), TYPE_CXL_TYPE3)) {
 172         return d;
 173     }
 174
 175     /*
 176      * Could also be a switch.  Note only one level of switching currently
 177      * supported.
 178      */
 179     if (!object_dynamic_cast(OBJECT(d), TYPE_CXL_USP)) {
 180         return NULL;
 181     }
 182     usp = CXL_USP(d);
 183
 184     usp_cstate = cxl_usp_to_cstate(usp);
 185     if (!usp_cstate) {
 186         return NULL;
 187     }
 188
 189     cache_mem = usp_cstate->crb.cache_mem_registers;
 190
 191     target_found = cxl_hdm_find_target(cache_mem, addr, &target);
 192     if (!target_found) {
 193         return NULL;
 194     }
 195
 196     d = pcie_find_port_by_pn(&PCI_BRIDGE(d)->sec_bus, target);
 197     if (!d) {
 198         return NULL;
 199     }
 200
 201     d = pci_bridge_get_sec_bus(PCI_BRIDGE(d))->devices[0];
 202     if (!d) {
 203         return NULL;
 204     }
 205
 206     if (!object_dynamic_cast(OBJECT(d), TYPE_CXL_TYPE3)) {
 207         return NULL;
 208     }
 209
 210     return d;
 211 }
 212
 213 static MemTxResult cxl_read_cfmws(void *opaque, hwaddr addr, uint64_t *data,
 214                                   unsigned size, MemTxAttrs attrs)
 215 {
 216     CXLFixedWindow *fw = opaque;
 217     PCIDevice *d;
 218
 219     d = cxl_cfmws_find_device(fw, addr);
 220     if (d == NULL) {
 221         *data = 0;
 222         /* Reads to invalid address return poison */
 223         return MEMTX_ERROR;
 224     }
 225
 226     return cxl_type3_read(d, addr + fw->base, data, size, attrs);
 227 }
 228
 229 static MemTxResult cxl_write_cfmws(void *opaque, hwaddr addr,
 230                                    uint64_t data, unsigned size,
 231                                    MemTxAttrs attrs)
 232 {
 233     CXLFixedWindow *fw = opaque;
 234     PCIDevice *d;
 235
 236     d = cxl_cfmws_find_device(fw, addr);
 237     if (d == NULL) {
 238         /* Writes to invalid address are silent */
 239         return MEMTX_OK;
 240     }
 241
 242     return cxl_type3_write(d, addr + fw->base, data, size, attrs);
 243 }
 244
 245 const MemoryRegionOps cfmws_ops = {
 246     .read_with_attrs = cxl_read_cfmws,
 247     .write_with_attrs = cxl_write_cfmws,
 248     .endianness = DEVICE_LITTLE_ENDIAN,
 249     .valid = {
 250         .min_access_size = 1,
 251         .max_access_size = 8,
 252         .unaligned = true,
 253     },
 254     .impl = {
 255         .min_access_size = 1,
 256         .max_access_size = 8,
 257         .unaligned = true,
 258     },
 259 };
 260
 261 static void machine_get_cxl(Object *obj, Visitor *v, const char *name,
 262                             void *opaque, Error **errp)
 263 {
 264     CXLState *cxl_state = opaque;
 265     bool value = cxl_state->is_enabled;
 266
 267     visit_type_bool(v, name, &value, errp);
 268 }
 269
 270 static void machine_set_cxl(Object *obj, Visitor *v, const char *name,
 271                             void *opaque, Error **errp)
 272 {
 273     CXLState *cxl_state = opaque;
 274     bool value;
 275
 276     if (!visit_type_bool(v, name, &value, errp)) {
 277         return;
 278     }
 279     cxl_state->is_enabled = value;
 280 }
 281
 282 static void machine_get_cfmw(Object *obj, Visitor *v, const char *name,
 283                              void *opaque, Error **errp)
 284 {
 285     CXLFixedMemoryWindowOptionsList **list = opaque;
 286
 287     visit_type_CXLFixedMemoryWindowOptionsList(v, name, list, errp);
 288 }
 289
 290 static void machine_set_cfmw(Object *obj, Visitor *v, const char *name,
 291                              void *opaque, Error **errp)
 292 {
 293     CXLState *state = opaque;
 294     CXLFixedMemoryWindowOptionsList *cfmw_list = NULL;
 295     CXLFixedMemoryWindowOptionsList *it;
 296
 297     visit_type_CXLFixedMemoryWindowOptionsList(v, name, &cfmw_list, errp);
 298     if (!cfmw_list) {
 299         return;
 300     }
 301
 302     for (it = cfmw_list; it; it = it->next) {
 303         cxl_fixed_memory_window_config(state, it->value, errp);
 304     }
 305     state->cfmw_list = cfmw_list;
 306 }
 307
 308 void cxl_machine_init(Object *obj, CXLState *state)
 309 {
 310     object_property_add(obj, "cxl", "bool", machine_get_cxl,
 311                         machine_set_cxl, NULL, state);
 312     object_property_set_description(obj, "cxl",
 313                                     "Set on/off to enable/disable "
 314                                     "CXL instantiation");
 315
 316     object_property_add(obj, "cxl-fmw", "CXLFixedMemoryWindow",
 317                         machine_get_cfmw, machine_set_cfmw,
 318                         NULL, state);
 319     object_property_set_description(obj, "cxl-fmw",
 320                                     "CXL Fixed Memory Windows (array)");
 321 }
 322
 323 void cxl_hook_up_pxb_registers(PCIBus *bus, CXLState *state, Error **errp)
 324 {
 325     /* Walk the pci busses looking for pxb busses to hook up */
 326     if (bus) {
 327         QLIST_FOREACH(bus, &bus->child, sibling) {
 328             if (!pci_bus_is_root(bus)) {
 329                 continue;
 330             }
 331             if (pci_bus_is_cxl(bus)) {
 332                 if (!state->is_enabled) {
 333                     error_setg(errp, "CXL host bridges present, but cxl=off");
 334                     return;
 335                 }
 336                 pxb_cxl_hook_up_registers(state, bus, errp);
 337             }
 338         }
 339     }
 340 }