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acpi: allow using object as offset for OperationRegion
[qemu.git] / hw / i386 / acpi-build.c
blobf32223088556ec0b717f79dc9c0dd0ca24ca852a
1 /* Support for generating ACPI tables and passing them to Guests
2 *
3 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 * Copyright (C) 2006 Fabrice Bellard
5 * Copyright (C) 2013 Red Hat Inc
6 *
7 * Author: Michael S. Tsirkin <mst@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #include "qemu/osdep.h"
24 #include "acpi-build.h"
25 #include <glib.h>
26 #include "qemu-common.h"
27 #include "qemu/bitmap.h"
28 #include "qemu/error-report.h"
29 #include "hw/pci/pci.h"
30 #include "qom/cpu.h"
31 #include "hw/i386/pc.h"
32 #include "target-i386/cpu.h"
33 #include "hw/timer/hpet.h"
34 #include "hw/acpi/acpi-defs.h"
35 #include "hw/acpi/acpi.h"
36 #include "hw/nvram/fw_cfg.h"
37 #include "hw/acpi/bios-linker-loader.h"
38 #include "hw/loader.h"
39 #include "hw/isa/isa.h"
40 #include "hw/acpi/memory_hotplug.h"
41 #include "hw/mem/nvdimm.h"
42 #include "sysemu/tpm.h"
43 #include "hw/acpi/tpm.h"
44 #include "sysemu/tpm_backend.h"
45 #include "hw/timer/mc146818rtc_regs.h"
46
47 /* Supported chipsets: */
48 #include "hw/acpi/piix4.h"
49 #include "hw/acpi/pcihp.h"
50 #include "hw/i386/ich9.h"
51 #include "hw/pci/pci_bus.h"
52 #include "hw/pci-host/q35.h"
53 #include "hw/i386/intel_iommu.h"
54 #include "hw/timer/hpet.h"
55
56 #include "hw/acpi/aml-build.h"
57
58 #include "qapi/qmp/qint.h"
59 #include "qom/qom-qobject.h"
60
61 /* These are used to size the ACPI tables for -M pc-i440fx-1.7 and
62 * -M pc-i440fx-2.0. Even if the actual amount of AML generated grows
63 * a little bit, there should be plenty of free space since the DSDT
64 * shrunk by ~1.5k between QEMU 2.0 and QEMU 2.1.
65 */
66 #define ACPI_BUILD_LEGACY_CPU_AML_SIZE 97
67 #define ACPI_BUILD_ALIGN_SIZE 0x1000
68
69 #define ACPI_BUILD_TABLE_SIZE 0x20000
70
71 /* #define DEBUG_ACPI_BUILD */
72 #ifdef DEBUG_ACPI_BUILD
73 #define ACPI_BUILD_DPRINTF(fmt, ...) \
74 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0)
75 #else
76 #define ACPI_BUILD_DPRINTF(fmt, ...)
77 #endif
78
79 typedef struct AcpiCpuInfo {
80 DECLARE_BITMAP(found_cpus, ACPI_CPU_HOTPLUG_ID_LIMIT);
81 } AcpiCpuInfo;
82
83 typedef struct AcpiMcfgInfo {
84 uint64_t mcfg_base;
85 uint32_t mcfg_size;
86 } AcpiMcfgInfo;
87
88 typedef struct AcpiPmInfo {
89 bool s3_disabled;
90 bool s4_disabled;
91 bool pcihp_bridge_en;
92 uint8_t s4_val;
93 uint16_t sci_int;
94 uint8_t acpi_enable_cmd;
95 uint8_t acpi_disable_cmd;
96 uint32_t gpe0_blk;
97 uint32_t gpe0_blk_len;
98 uint32_t io_base;
99 uint16_t cpu_hp_io_base;
100 uint16_t cpu_hp_io_len;
101 uint16_t mem_hp_io_base;
102 uint16_t mem_hp_io_len;
103 uint16_t pcihp_io_base;
104 uint16_t pcihp_io_len;
105 } AcpiPmInfo;
106
107 typedef struct AcpiMiscInfo {
108 bool is_piix4;
109 bool has_hpet;
110 TPMVersion tpm_version;
111 const unsigned char *dsdt_code;
112 unsigned dsdt_size;
113 uint16_t pvpanic_port;
114 uint16_t applesmc_io_base;
115 } AcpiMiscInfo;
116
117 typedef struct AcpiBuildPciBusHotplugState {
118 GArray *device_table;
119 GArray *notify_table;
120 struct AcpiBuildPciBusHotplugState *parent;
121 bool pcihp_bridge_en;
122 } AcpiBuildPciBusHotplugState;
123
124 static
125 int acpi_add_cpu_info(Object *o, void *opaque)
126 {
127 AcpiCpuInfo *cpu = opaque;
128 uint64_t apic_id;
129
130 if (object_dynamic_cast(o, TYPE_CPU)) {
131 apic_id = object_property_get_int(o, "apic-id", NULL);
132 assert(apic_id < ACPI_CPU_HOTPLUG_ID_LIMIT);
133
134 set_bit(apic_id, cpu->found_cpus);
135 }
136
137 object_child_foreach(o, acpi_add_cpu_info, opaque);
138 return 0;
139 }
140
141 static void acpi_get_cpu_info(AcpiCpuInfo *cpu)
142 {
143 Object *root = object_get_root();
144
145 memset(cpu->found_cpus, 0, sizeof cpu->found_cpus);
146 object_child_foreach(root, acpi_add_cpu_info, cpu);
147 }
148
149 static void acpi_get_pm_info(AcpiPmInfo *pm)
150 {
151 Object *piix = piix4_pm_find();
152 Object *lpc = ich9_lpc_find();
153 Object *obj = NULL;
154 QObject *o;
155
156 pm->cpu_hp_io_base = 0;
157 pm->pcihp_io_base = 0;
158 pm->pcihp_io_len = 0;
159 if (piix) {
160 obj = piix;
161 pm->cpu_hp_io_base = PIIX4_CPU_HOTPLUG_IO_BASE;
162 pm->pcihp_io_base =
163 object_property_get_int(obj, ACPI_PCIHP_IO_BASE_PROP, NULL);
164 pm->pcihp_io_len =
165 object_property_get_int(obj, ACPI_PCIHP_IO_LEN_PROP, NULL);
166 }
167 if (lpc) {
168 obj = lpc;
169 pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE;
170 }
171 assert(obj);
172
173 pm->cpu_hp_io_len = ACPI_GPE_PROC_LEN;
174 pm->mem_hp_io_base = ACPI_MEMORY_HOTPLUG_BASE;
175 pm->mem_hp_io_len = ACPI_MEMORY_HOTPLUG_IO_LEN;
176
177 /* Fill in optional s3/s4 related properties */
178 o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
179 if (o) {
180 pm->s3_disabled = qint_get_int(qobject_to_qint(o));
181 } else {
182 pm->s3_disabled = false;
183 }
184 qobject_decref(o);
185 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL);
186 if (o) {
187 pm->s4_disabled = qint_get_int(qobject_to_qint(o));
188 } else {
189 pm->s4_disabled = false;
190 }
191 qobject_decref(o);
192 o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL);
193 if (o) {
194 pm->s4_val = qint_get_int(qobject_to_qint(o));
195 } else {
196 pm->s4_val = false;
197 }
198 qobject_decref(o);
199
200 /* Fill in mandatory properties */
201 pm->sci_int = object_property_get_int(obj, ACPI_PM_PROP_SCI_INT, NULL);
202
203 pm->acpi_enable_cmd = object_property_get_int(obj,
204 ACPI_PM_PROP_ACPI_ENABLE_CMD,
205 NULL);
206 pm->acpi_disable_cmd = object_property_get_int(obj,
207 ACPI_PM_PROP_ACPI_DISABLE_CMD,
208 NULL);
209 pm->io_base = object_property_get_int(obj, ACPI_PM_PROP_PM_IO_BASE,
210 NULL);
211 pm->gpe0_blk = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK,
212 NULL);
213 pm->gpe0_blk_len = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK_LEN,
214 NULL);
215 pm->pcihp_bridge_en =
216 object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support",
217 NULL);
218 }
219
220 static void acpi_get_misc_info(AcpiMiscInfo *info)
221 {
222 Object *piix = piix4_pm_find();
223 Object *lpc = ich9_lpc_find();
224 assert(!!piix != !!lpc);
225
226 if (piix) {
227 info->is_piix4 = true;
228 }
229 if (lpc) {
230 info->is_piix4 = false;
231 }
232
233 info->has_hpet = hpet_find();
234 info->tpm_version = tpm_get_version();
235 info->pvpanic_port = pvpanic_port();
236 info->applesmc_io_base = applesmc_port();
237 }
238
239 /*
240 * Because of the PXB hosts we cannot simply query TYPE_PCI_HOST_BRIDGE.
241 * On i386 arch we only have two pci hosts, so we can look only for them.
242 */
243 static Object *acpi_get_i386_pci_host(void)
244 {
245 PCIHostState *host;
246
247 host = OBJECT_CHECK(PCIHostState,
248 object_resolve_path("/machine/i440fx", NULL),
249 TYPE_PCI_HOST_BRIDGE);
250 if (!host) {
251 host = OBJECT_CHECK(PCIHostState,
252 object_resolve_path("/machine/q35", NULL),
253 TYPE_PCI_HOST_BRIDGE);
254 }
255
256 return OBJECT(host);
257 }
258
259 static void acpi_get_pci_info(PcPciInfo *info)
260 {
261 Object *pci_host;
262
263
264 pci_host = acpi_get_i386_pci_host();
265 g_assert(pci_host);
266
267 info->w32.begin = object_property_get_int(pci_host,
268 PCI_HOST_PROP_PCI_HOLE_START,
269 NULL);
270 info->w32.end = object_property_get_int(pci_host,
271 PCI_HOST_PROP_PCI_HOLE_END,
272 NULL);
273 info->w64.begin = object_property_get_int(pci_host,
274 PCI_HOST_PROP_PCI_HOLE64_START,
275 NULL);
276 info->w64.end = object_property_get_int(pci_host,
277 PCI_HOST_PROP_PCI_HOLE64_END,
278 NULL);
279 }
280
281 #define ACPI_PORT_SMI_CMD 0x00b2 /* TODO: this is APM_CNT_IOPORT */
282
283 static void acpi_align_size(GArray *blob, unsigned align)
284 {
285 /* Align size to multiple of given size. This reduces the chance
286 * we need to change size in the future (breaking cross version migration).
287 */
288 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
289 }
290
291 /* FACS */
292 static void
293 build_facs(GArray *table_data, GArray *linker)
294 {
295 AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs);
296 memcpy(&facs->signature, "FACS", 4);
297 facs->length = cpu_to_le32(sizeof(*facs));
298 }
299
300 /* Load chipset information in FADT */
301 static void fadt_setup(AcpiFadtDescriptorRev1 *fadt, AcpiPmInfo *pm)
302 {
303 fadt->model = 1;
304 fadt->reserved1 = 0;
305 fadt->sci_int = cpu_to_le16(pm->sci_int);
306 fadt->smi_cmd = cpu_to_le32(ACPI_PORT_SMI_CMD);
307 fadt->acpi_enable = pm->acpi_enable_cmd;
308 fadt->acpi_disable = pm->acpi_disable_cmd;
309 /* EVT, CNT, TMR offset matches hw/acpi/core.c */
310 fadt->pm1a_evt_blk = cpu_to_le32(pm->io_base);
311 fadt->pm1a_cnt_blk = cpu_to_le32(pm->io_base + 0x04);
312 fadt->pm_tmr_blk = cpu_to_le32(pm->io_base + 0x08);
313 fadt->gpe0_blk = cpu_to_le32(pm->gpe0_blk);
314 /* EVT, CNT, TMR length matches hw/acpi/core.c */
315 fadt->pm1_evt_len = 4;
316 fadt->pm1_cnt_len = 2;
317 fadt->pm_tmr_len = 4;
318 fadt->gpe0_blk_len = pm->gpe0_blk_len;
319 fadt->plvl2_lat = cpu_to_le16(0xfff); /* C2 state not supported */
320 fadt->plvl3_lat = cpu_to_le16(0xfff); /* C3 state not supported */
321 fadt->flags = cpu_to_le32((1 << ACPI_FADT_F_WBINVD) |
322 (1 << ACPI_FADT_F_PROC_C1) |
323 (1 << ACPI_FADT_F_SLP_BUTTON) |
324 (1 << ACPI_FADT_F_RTC_S4));
325 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK);
326 /* APIC destination mode ("Flat Logical") has an upper limit of 8 CPUs
327 * For more than 8 CPUs, "Clustered Logical" mode has to be used
328 */
329 if (max_cpus > 8) {
330 fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL);
331 }
332 fadt->century = RTC_CENTURY;
333 }
334
335
336 /* FADT */
337 static void
338 build_fadt(GArray *table_data, GArray *linker, AcpiPmInfo *pm,
339 unsigned facs, unsigned dsdt,
340 const char *oem_id, const char *oem_table_id)
341 {
342 AcpiFadtDescriptorRev1 *fadt = acpi_data_push(table_data, sizeof(*fadt));
343
344 fadt->firmware_ctrl = cpu_to_le32(facs);
345 /* FACS address to be filled by Guest linker */
346 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
347 ACPI_BUILD_TABLE_FILE,
348 table_data, &fadt->firmware_ctrl,
349 sizeof fadt->firmware_ctrl);
350
351 fadt->dsdt = cpu_to_le32(dsdt);
352 /* DSDT address to be filled by Guest linker */
353 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
354 ACPI_BUILD_TABLE_FILE,
355 table_data, &fadt->dsdt,
356 sizeof fadt->dsdt);
357
358 fadt_setup(fadt, pm);
359
360 build_header(linker, table_data,
361 (void *)fadt, "FACP", sizeof(*fadt), 1, oem_id, oem_table_id);
362 }
363
364 static void
365 build_madt(GArray *table_data, GArray *linker, AcpiCpuInfo *cpu)
366 {
367 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
368 int madt_start = table_data->len;
369
370 AcpiMultipleApicTable *madt;
371 AcpiMadtIoApic *io_apic;
372 AcpiMadtIntsrcovr *intsrcovr;
373 AcpiMadtLocalNmi *local_nmi;
374 int i;
375
376 madt = acpi_data_push(table_data, sizeof *madt);
377 madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS);
378 madt->flags = cpu_to_le32(1);
379
380 for (i = 0; i < pcms->apic_id_limit; i++) {
381 AcpiMadtProcessorApic *apic = acpi_data_push(table_data, sizeof *apic);
382 apic->type = ACPI_APIC_PROCESSOR;
383 apic->length = sizeof(*apic);
384 apic->processor_id = i;
385 apic->local_apic_id = i;
386 if (test_bit(i, cpu->found_cpus)) {
387 apic->flags = cpu_to_le32(1);
388 } else {
389 apic->flags = cpu_to_le32(0);
390 }
391 }
392 io_apic = acpi_data_push(table_data, sizeof *io_apic);
393 io_apic->type = ACPI_APIC_IO;
394 io_apic->length = sizeof(*io_apic);
395 #define ACPI_BUILD_IOAPIC_ID 0x0
396 io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID;
397 io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS);
398 io_apic->interrupt = cpu_to_le32(0);
399
400 if (pcms->apic_xrupt_override) {
401 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
402 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
403 intsrcovr->length = sizeof(*intsrcovr);
404 intsrcovr->source = 0;
405 intsrcovr->gsi = cpu_to_le32(2);
406 intsrcovr->flags = cpu_to_le16(0); /* conforms to bus specifications */
407 }
408 for (i = 1; i < 16; i++) {
409 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
410 if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) {
411 /* No need for a INT source override structure. */
412 continue;
413 }
414 intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
415 intsrcovr->type = ACPI_APIC_XRUPT_OVERRIDE;
416 intsrcovr->length = sizeof(*intsrcovr);
417 intsrcovr->source = i;
418 intsrcovr->gsi = cpu_to_le32(i);
419 intsrcovr->flags = cpu_to_le16(0xd); /* active high, level triggered */
420 }
421
422 local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
423 local_nmi->type = ACPI_APIC_LOCAL_NMI;
424 local_nmi->length = sizeof(*local_nmi);
425 local_nmi->processor_id = 0xff; /* all processors */
426 local_nmi->flags = cpu_to_le16(0);
427 local_nmi->lint = 1; /* ACPI_LINT1 */
428
429 build_header(linker, table_data,
430 (void *)(table_data->data + madt_start), "APIC",
431 table_data->len - madt_start, 1, NULL, NULL);
432 }
433
434 /* Assign BSEL property to all buses. In the future, this can be changed
435 * to only assign to buses that support hotplug.
436 */
437 static void *acpi_set_bsel(PCIBus *bus, void *opaque)
438 {
439 unsigned *bsel_alloc = opaque;
440 unsigned *bus_bsel;
441
442 if (qbus_is_hotpluggable(BUS(bus))) {
443 bus_bsel = g_malloc(sizeof *bus_bsel);
444
445 *bus_bsel = (*bsel_alloc)++;
446 object_property_add_uint32_ptr(OBJECT(bus), ACPI_PCIHP_PROP_BSEL,
447 bus_bsel, NULL);
448 }
449
450 return bsel_alloc;
451 }
452
453 static void acpi_set_pci_info(void)
454 {
455 PCIBus *bus = find_i440fx(); /* TODO: Q35 support */
456 unsigned bsel_alloc = 0;
457
458 if (bus) {
459 /* Scan all PCI buses. Set property to enable acpi based hotplug. */
460 pci_for_each_bus_depth_first(bus, acpi_set_bsel, NULL, &bsel_alloc);
461 }
462 }
463
464 static void build_append_pcihp_notify_entry(Aml *method, int slot)
465 {
466 Aml *if_ctx;
467 int32_t devfn = PCI_DEVFN(slot, 0);
468
469 if_ctx = aml_if(aml_and(aml_arg(0), aml_int(0x1U << slot), NULL));
470 aml_append(if_ctx, aml_notify(aml_name("S%.02X", devfn), aml_arg(1)));
471 aml_append(method, if_ctx);
472 }
473
474 static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus,
475 bool pcihp_bridge_en)
476 {
477 Aml *dev, *notify_method, *method;
478 QObject *bsel;
479 PCIBus *sec;
480 int i;
481
482 bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
483 if (bsel) {
484 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel));
485
486 aml_append(parent_scope, aml_name_decl("BSEL", aml_int(bsel_val)));
487 notify_method = aml_method("DVNT", 2, AML_NOTSERIALIZED);
488 }
489
490 for (i = 0; i < ARRAY_SIZE(bus->devices); i += PCI_FUNC_MAX) {
491 DeviceClass *dc;
492 PCIDeviceClass *pc;
493 PCIDevice *pdev = bus->devices[i];
494 int slot = PCI_SLOT(i);
495 bool hotplug_enabled_dev;
496 bool bridge_in_acpi;
497
498 if (!pdev) {
499 if (bsel) { /* add hotplug slots for non present devices */
500 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
501 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
502 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
503 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
504 aml_append(method,
505 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
506 );
507 aml_append(dev, method);
508 aml_append(parent_scope, dev);
509
510 build_append_pcihp_notify_entry(notify_method, slot);
511 }
512 continue;
513 }
514
515 pc = PCI_DEVICE_GET_CLASS(pdev);
516 dc = DEVICE_GET_CLASS(pdev);
517
518 /* When hotplug for bridges is enabled, bridges are
519 * described in ACPI separately (see build_pci_bus_end).
520 * In this case they aren't themselves hot-pluggable.
521 * Hotplugged bridges *are* hot-pluggable.
522 */
523 bridge_in_acpi = pc->is_bridge && pcihp_bridge_en &&
524 !DEVICE(pdev)->hotplugged;
525
526 hotplug_enabled_dev = bsel && dc->hotpluggable && !bridge_in_acpi;
527
528 if (pc->class_id == PCI_CLASS_BRIDGE_ISA) {
529 continue;
530 }
531
532 /* start to compose PCI slot descriptor */
533 dev = aml_device("S%.02X", PCI_DEVFN(slot, 0));
534 aml_append(dev, aml_name_decl("_ADR", aml_int(slot << 16)));
535
536 if (pc->class_id == PCI_CLASS_DISPLAY_VGA) {
537 /* add VGA specific AML methods */
538 int s3d;
539
540 if (object_dynamic_cast(OBJECT(pdev), "qxl-vga")) {
541 s3d = 3;
542 } else {
543 s3d = 0;
544 }
545
546 method = aml_method("_S1D", 0, AML_NOTSERIALIZED);
547 aml_append(method, aml_return(aml_int(0)));
548 aml_append(dev, method);
549
550 method = aml_method("_S2D", 0, AML_NOTSERIALIZED);
551 aml_append(method, aml_return(aml_int(0)));
552 aml_append(dev, method);
553
554 method = aml_method("_S3D", 0, AML_NOTSERIALIZED);
555 aml_append(method, aml_return(aml_int(s3d)));
556 aml_append(dev, method);
557 } else if (hotplug_enabled_dev) {
558 /* add _SUN/_EJ0 to make slot hotpluggable */
559 aml_append(dev, aml_name_decl("_SUN", aml_int(slot)));
560
561 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
562 aml_append(method,
563 aml_call2("PCEJ", aml_name("BSEL"), aml_name("_SUN"))
564 );
565 aml_append(dev, method);
566
567 if (bsel) {
568 build_append_pcihp_notify_entry(notify_method, slot);
569 }
570 } else if (bridge_in_acpi) {
571 /*
572 * device is coldplugged bridge,
573 * add child device descriptions into its scope
574 */
575 PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(pdev));
576
577 build_append_pci_bus_devices(dev, sec_bus, pcihp_bridge_en);
578 }
579 /* slot descriptor has been composed, add it into parent context */
580 aml_append(parent_scope, dev);
581 }
582
583 if (bsel) {
584 aml_append(parent_scope, notify_method);
585 }
586
587 /* Append PCNT method to notify about events on local and child buses.
588 * Add unconditionally for root since DSDT expects it.
589 */
590 method = aml_method("PCNT", 0, AML_NOTSERIALIZED);
591
592 /* If bus supports hotplug select it and notify about local events */
593 if (bsel) {
594 int64_t bsel_val = qint_get_int(qobject_to_qint(bsel));
595 aml_append(method, aml_store(aml_int(bsel_val), aml_name("BNUM")));
596 aml_append(method,
597 aml_call2("DVNT", aml_name("PCIU"), aml_int(1) /* Device Check */)
598 );
599 aml_append(method,
600 aml_call2("DVNT", aml_name("PCID"), aml_int(3)/* Eject Request */)
601 );
602 }
603
604 /* Notify about child bus events in any case */
605 if (pcihp_bridge_en) {
606 QLIST_FOREACH(sec, &bus->child, sibling) {
607 int32_t devfn = sec->parent_dev->devfn;
608
609 aml_append(method, aml_name("^S%.02X.PCNT", devfn));
610 }
611 }
612 aml_append(parent_scope, method);
613 qobject_decref(bsel);
614 }
615
616 /**
617 * build_prt_entry:
618 * @link_name: link name for PCI route entry
619 *
620 * build AML package containing a PCI route entry for @link_name
621 */
622 static Aml *build_prt_entry(const char *link_name)
623 {
624 Aml *a_zero = aml_int(0);
625 Aml *pkg = aml_package(4);
626 aml_append(pkg, a_zero);
627 aml_append(pkg, a_zero);
628 aml_append(pkg, aml_name("%s", link_name));
629 aml_append(pkg, a_zero);
630 return pkg;
631 }
632
633 /*
634 * initialize_route - Initialize the interrupt routing rule
635 * through a specific LINK:
636 * if (lnk_idx == idx)
637 * route using link 'link_name'
638 */
639 static Aml *initialize_route(Aml *route, const char *link_name,
640 Aml *lnk_idx, int idx)
641 {
642 Aml *if_ctx = aml_if(aml_equal(lnk_idx, aml_int(idx)));
643 Aml *pkg = build_prt_entry(link_name);
644
645 aml_append(if_ctx, aml_store(pkg, route));
646
647 return if_ctx;
648 }
649
650 /*
651 * build_prt - Define interrupt rounting rules
652 *
653 * Returns an array of 128 routes, one for each device,
654 * based on device location.
655 * The main goal is to equaly distribute the interrupts
656 * over the 4 existing ACPI links (works only for i440fx).
657 * The hash function is (slot + pin) & 3 -> "LNK[D|A|B|C]".
658 *
659 */
660 static Aml *build_prt(bool is_pci0_prt)
661 {
662 Aml *method, *while_ctx, *pin, *res;
663
664 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
665 res = aml_local(0);
666 pin = aml_local(1);
667 aml_append(method, aml_store(aml_package(128), res));
668 aml_append(method, aml_store(aml_int(0), pin));
669
670 /* while (pin < 128) */
671 while_ctx = aml_while(aml_lless(pin, aml_int(128)));
672 {
673 Aml *slot = aml_local(2);
674 Aml *lnk_idx = aml_local(3);
675 Aml *route = aml_local(4);
676
677 /* slot = pin >> 2 */
678 aml_append(while_ctx,
679 aml_store(aml_shiftright(pin, aml_int(2), NULL), slot));
680 /* lnk_idx = (slot + pin) & 3 */
681 aml_append(while_ctx,
682 aml_store(aml_and(aml_add(pin, slot, NULL), aml_int(3), NULL),
683 lnk_idx));
684
685 /* route[2] = "LNK[D|A|B|C]", selection based on pin % 3 */
686 aml_append(while_ctx, initialize_route(route, "LNKD", lnk_idx, 0));
687 if (is_pci0_prt) {
688 Aml *if_device_1, *if_pin_4, *else_pin_4;
689
690 /* device 1 is the power-management device, needs SCI */
691 if_device_1 = aml_if(aml_equal(lnk_idx, aml_int(1)));
692 {
693 if_pin_4 = aml_if(aml_equal(pin, aml_int(4)));
694 {
695 aml_append(if_pin_4,
696 aml_store(build_prt_entry("LNKS"), route));
697 }
698 aml_append(if_device_1, if_pin_4);
699 else_pin_4 = aml_else();
700 {
701 aml_append(else_pin_4,
702 aml_store(build_prt_entry("LNKA"), route));
703 }
704 aml_append(if_device_1, else_pin_4);
705 }
706 aml_append(while_ctx, if_device_1);
707 } else {
708 aml_append(while_ctx, initialize_route(route, "LNKA", lnk_idx, 1));
709 }
710 aml_append(while_ctx, initialize_route(route, "LNKB", lnk_idx, 2));
711 aml_append(while_ctx, initialize_route(route, "LNKC", lnk_idx, 3));
712
713 /* route[0] = 0x[slot]FFFF */
714 aml_append(while_ctx,
715 aml_store(aml_or(aml_shiftleft(slot, aml_int(16)), aml_int(0xFFFF),
716 NULL),
717 aml_index(route, aml_int(0))));
718 /* route[1] = pin & 3 */
719 aml_append(while_ctx,
720 aml_store(aml_and(pin, aml_int(3), NULL),
721 aml_index(route, aml_int(1))));
722 /* res[pin] = route */
723 aml_append(while_ctx, aml_store(route, aml_index(res, pin)));
724 /* pin++ */
725 aml_append(while_ctx, aml_increment(pin));
726 }
727 aml_append(method, while_ctx);
728 /* return res*/
729 aml_append(method, aml_return(res));
730
731 return method;
732 }
733
734 typedef struct CrsRangeEntry {
735 uint64_t base;
736 uint64_t limit;
737 } CrsRangeEntry;
738
739 static void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit)
740 {
741 CrsRangeEntry *entry;
742
743 entry = g_malloc(sizeof(*entry));
744 entry->base = base;
745 entry->limit = limit;
746
747 g_ptr_array_add(ranges, entry);
748 }
749
750 static void crs_range_free(gpointer data)
751 {
752 CrsRangeEntry *entry = (CrsRangeEntry *)data;
753 g_free(entry);
754 }
755
756 static gint crs_range_compare(gconstpointer a, gconstpointer b)
757 {
758 CrsRangeEntry *entry_a = *(CrsRangeEntry **)a;
759 CrsRangeEntry *entry_b = *(CrsRangeEntry **)b;
760
761 return (int64_t)entry_a->base - (int64_t)entry_b->base;
762 }
763
764 /*
765 * crs_replace_with_free_ranges - given the 'used' ranges within [start - end]
766 * interval, computes the 'free' ranges from the same interval.
767 * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function
768 * will return { [base - a1], [a2 - b1], [b2 - limit] }.
769 */
770 static void crs_replace_with_free_ranges(GPtrArray *ranges,
771 uint64_t start, uint64_t end)
772 {
773 GPtrArray *free_ranges = g_ptr_array_new_with_free_func(crs_range_free);
774 uint64_t free_base = start;
775 int i;
776
777 g_ptr_array_sort(ranges, crs_range_compare);
778 for (i = 0; i < ranges->len; i++) {
779 CrsRangeEntry *used = g_ptr_array_index(ranges, i);
780
781 if (free_base < used->base) {
782 crs_range_insert(free_ranges, free_base, used->base - 1);
783 }
784
785 free_base = used->limit + 1;
786 }
787
788 if (free_base < end) {
789 crs_range_insert(free_ranges, free_base, end);
790 }
791
792 g_ptr_array_set_size(ranges, 0);
793 for (i = 0; i < free_ranges->len; i++) {
794 g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i));
795 }
796
797 g_ptr_array_free(free_ranges, false);
798 }
799
800 /*
801 * crs_range_merge - merges adjacent ranges in the given array.
802 * Array elements are deleted and replaced with the merged ranges.
803 */
804 static void crs_range_merge(GPtrArray *range)
805 {
806 GPtrArray *tmp = g_ptr_array_new_with_free_func(crs_range_free);
807 CrsRangeEntry *entry;
808 uint64_t range_base, range_limit;
809 int i;
810
811 if (!range->len) {
812 return;
813 }
814
815 g_ptr_array_sort(range, crs_range_compare);
816
817 entry = g_ptr_array_index(range, 0);
818 range_base = entry->base;
819 range_limit = entry->limit;
820 for (i = 1; i < range->len; i++) {
821 entry = g_ptr_array_index(range, i);
822 if (entry->base - 1 == range_limit) {
823 range_limit = entry->limit;
824 } else {
825 crs_range_insert(tmp, range_base, range_limit);
826 range_base = entry->base;
827 range_limit = entry->limit;
828 }
829 }
830 crs_range_insert(tmp, range_base, range_limit);
831
832 g_ptr_array_set_size(range, 0);
833 for (i = 0; i < tmp->len; i++) {
834 entry = g_ptr_array_index(tmp, i);
835 crs_range_insert(range, entry->base, entry->limit);
836 }
837 g_ptr_array_free(tmp, true);
838 }
839
840 static Aml *build_crs(PCIHostState *host,
841 GPtrArray *io_ranges, GPtrArray *mem_ranges)
842 {
843 Aml *crs = aml_resource_template();
844 GPtrArray *host_io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
845 GPtrArray *host_mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
846 CrsRangeEntry *entry;
847 uint8_t max_bus = pci_bus_num(host->bus);
848 uint8_t type;
849 int devfn;
850 int i;
851
852 for (devfn = 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) {
853 uint64_t range_base, range_limit;
854 PCIDevice *dev = host->bus->devices[devfn];
855
856 if (!dev) {
857 continue;
858 }
859
860 for (i = 0; i < PCI_NUM_REGIONS; i++) {
861 PCIIORegion *r = &dev->io_regions[i];
862
863 range_base = r->addr;
864 range_limit = r->addr + r->size - 1;
865
866 /*
867 * Work-around for old bioses
868 * that do not support multiple root buses
869 */
870 if (!range_base || range_base > range_limit) {
871 continue;
872 }
873
874 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
875 crs_range_insert(host_io_ranges, range_base, range_limit);
876 } else { /* "memory" */
877 crs_range_insert(host_mem_ranges, range_base, range_limit);
878 }
879 }
880
881 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
882 if (type == PCI_HEADER_TYPE_BRIDGE) {
883 uint8_t subordinate = dev->config[PCI_SUBORDINATE_BUS];
884 if (subordinate > max_bus) {
885 max_bus = subordinate;
886 }
887
888 range_base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
889 range_limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
890
891 /*
892 * Work-around for old bioses
893 * that do not support multiple root buses
894 */
895 if (range_base && range_base <= range_limit) {
896 crs_range_insert(host_io_ranges, range_base, range_limit);
897 }
898
899 range_base =
900 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
901 range_limit =
902 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
903
904 /*
905 * Work-around for old bioses
906 * that do not support multiple root buses
907 */
908 if (range_base && range_base <= range_limit) {
909 crs_range_insert(host_mem_ranges, range_base, range_limit);
910 }
911
912 range_base =
913 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
914 range_limit =
915 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
916
917 /*
918 * Work-around for old bioses
919 * that do not support multiple root buses
920 */
921 if (range_base && range_base <= range_limit) {
922 crs_range_insert(host_mem_ranges, range_base, range_limit);
923 }
924 }
925 }
926
927 crs_range_merge(host_io_ranges);
928 for (i = 0; i < host_io_ranges->len; i++) {
929 entry = g_ptr_array_index(host_io_ranges, i);
930 aml_append(crs,
931 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
932 AML_POS_DECODE, AML_ENTIRE_RANGE,
933 0, entry->base, entry->limit, 0,
934 entry->limit - entry->base + 1));
935 crs_range_insert(io_ranges, entry->base, entry->limit);
936 }
937 g_ptr_array_free(host_io_ranges, true);
938
939 crs_range_merge(host_mem_ranges);
940 for (i = 0; i < host_mem_ranges->len; i++) {
941 entry = g_ptr_array_index(host_mem_ranges, i);
942 aml_append(crs,
943 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED,
944 AML_MAX_FIXED, AML_NON_CACHEABLE,
945 AML_READ_WRITE,
946 0, entry->base, entry->limit, 0,
947 entry->limit - entry->base + 1));
948 crs_range_insert(mem_ranges, entry->base, entry->limit);
949 }
950 g_ptr_array_free(host_mem_ranges, true);
951
952 aml_append(crs,
953 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
954 0,
955 pci_bus_num(host->bus),
956 max_bus,
957 0,
958 max_bus - pci_bus_num(host->bus) + 1));
959
960 return crs;
961 }
962
963 static void build_processor_devices(Aml *sb_scope, unsigned acpi_cpus,
964 AcpiCpuInfo *cpu, AcpiPmInfo *pm)
965 {
966 int i;
967 Aml *dev;
968 Aml *crs;
969 Aml *pkg;
970 Aml *field;
971 Aml *ifctx;
972 Aml *method;
973
974 /* The current AML generator can cover the APIC ID range [0..255],
975 * inclusive, for VCPU hotplug. */
976 QEMU_BUILD_BUG_ON(ACPI_CPU_HOTPLUG_ID_LIMIT > 256);
977 g_assert(acpi_cpus <= ACPI_CPU_HOTPLUG_ID_LIMIT);
978
979 /* create PCI0.PRES device and its _CRS to reserve CPU hotplug MMIO */
980 dev = aml_device("PCI0." stringify(CPU_HOTPLUG_RESOURCE_DEVICE));
981 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06")));
982 aml_append(dev,
983 aml_name_decl("_UID", aml_string("CPU Hotplug resources"))
984 );
985 /* device present, functioning, decoding, not shown in UI */
986 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
987 crs = aml_resource_template();
988 aml_append(crs,
989 aml_io(AML_DECODE16, pm->cpu_hp_io_base, pm->cpu_hp_io_base, 1,
990 pm->cpu_hp_io_len)
991 );
992 aml_append(dev, aml_name_decl("_CRS", crs));
993 aml_append(sb_scope, dev);
994 /* declare CPU hotplug MMIO region and PRS field to access it */
995 aml_append(sb_scope, aml_operation_region(
996 "PRST", AML_SYSTEM_IO, aml_int(pm->cpu_hp_io_base), pm->cpu_hp_io_len));
997 field = aml_field("PRST", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
998 aml_append(field, aml_named_field("PRS", 256));
999 aml_append(sb_scope, field);
1000
1001 /* build Processor object for each processor */
1002 for (i = 0; i < acpi_cpus; i++) {
1003 dev = aml_processor(i, 0, 0, "CP%.02X", i);
1004
1005 method = aml_method("_MAT", 0, AML_NOTSERIALIZED);
1006 aml_append(method,
1007 aml_return(aml_call1(CPU_MAT_METHOD, aml_int(i))));
1008 aml_append(dev, method);
1009
1010 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1011 aml_append(method,
1012 aml_return(aml_call1(CPU_STATUS_METHOD, aml_int(i))));
1013 aml_append(dev, method);
1014
1015 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
1016 aml_append(method,
1017 aml_return(aml_call2(CPU_EJECT_METHOD, aml_int(i), aml_arg(0)))
1018 );
1019 aml_append(dev, method);
1020
1021 aml_append(sb_scope, dev);
1022 }
1023
1024 /* build this code:
1025 * Method(NTFY, 2) {If (LEqual(Arg0, 0x00)) {Notify(CP00, Arg1)} ...}
1026 */
1027 /* Arg0 = Processor ID = APIC ID */
1028 method = aml_method(AML_NOTIFY_METHOD, 2, AML_NOTSERIALIZED);
1029 for (i = 0; i < acpi_cpus; i++) {
1030 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i)));
1031 aml_append(ifctx,
1032 aml_notify(aml_name("CP%.02X", i), aml_arg(1))
1033 );
1034 aml_append(method, ifctx);
1035 }
1036 aml_append(sb_scope, method);
1037
1038 /* build "Name(CPON, Package() { One, One, ..., Zero, Zero, ... })"
1039 *
1040 * Note: The ability to create variable-sized packages was first
1041 * introduced in ACPI 2.0. ACPI 1.0 only allowed fixed-size packages
1042 * ith up to 255 elements. Windows guests up to win2k8 fail when
1043 * VarPackageOp is used.
1044 */
1045 pkg = acpi_cpus <= 255 ? aml_package(acpi_cpus) :
1046 aml_varpackage(acpi_cpus);
1047
1048 for (i = 0; i < acpi_cpus; i++) {
1049 uint8_t b = test_bit(i, cpu->found_cpus) ? 0x01 : 0x00;
1050 aml_append(pkg, aml_int(b));
1051 }
1052 aml_append(sb_scope, aml_name_decl(CPU_ON_BITMAP, pkg));
1053 }
1054
1055 static void build_memory_devices(Aml *sb_scope, int nr_mem,
1056 uint16_t io_base, uint16_t io_len)
1057 {
1058 int i;
1059 Aml *scope;
1060 Aml *crs;
1061 Aml *field;
1062 Aml *dev;
1063 Aml *method;
1064 Aml *ifctx;
1065
1066 /* build memory devices */
1067 assert(nr_mem <= ACPI_MAX_RAM_SLOTS);
1068 scope = aml_scope("\\_SB.PCI0." MEMORY_HOTPLUG_DEVICE);
1069 aml_append(scope,
1070 aml_name_decl(MEMORY_SLOTS_NUMBER, aml_int(nr_mem))
1071 );
1072
1073 crs = aml_resource_template();
1074 aml_append(crs,
1075 aml_io(AML_DECODE16, io_base, io_base, 0, io_len)
1076 );
1077 aml_append(scope, aml_name_decl("_CRS", crs));
1078
1079 aml_append(scope, aml_operation_region(
1080 MEMORY_HOTPLUG_IO_REGION, AML_SYSTEM_IO,
1081 aml_int(io_base), io_len)
1082 );
1083
1084 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_DWORD_ACC,
1085 AML_NOLOCK, AML_PRESERVE);
1086 aml_append(field, /* read only */
1087 aml_named_field(MEMORY_SLOT_ADDR_LOW, 32));
1088 aml_append(field, /* read only */
1089 aml_named_field(MEMORY_SLOT_ADDR_HIGH, 32));
1090 aml_append(field, /* read only */
1091 aml_named_field(MEMORY_SLOT_SIZE_LOW, 32));
1092 aml_append(field, /* read only */
1093 aml_named_field(MEMORY_SLOT_SIZE_HIGH, 32));
1094 aml_append(field, /* read only */
1095 aml_named_field(MEMORY_SLOT_PROXIMITY, 32));
1096 aml_append(scope, field);
1097
1098 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_BYTE_ACC,
1099 AML_NOLOCK, AML_WRITE_AS_ZEROS);
1100 aml_append(field, aml_reserved_field(160 /* bits, Offset(20) */));
1101 aml_append(field, /* 1 if enabled, read only */
1102 aml_named_field(MEMORY_SLOT_ENABLED, 1));
1103 aml_append(field,
1104 /*(read) 1 if has a insert event. (write) 1 to clear event */
1105 aml_named_field(MEMORY_SLOT_INSERT_EVENT, 1));
1106 aml_append(field,
1107 /* (read) 1 if has a remove event. (write) 1 to clear event */
1108 aml_named_field(MEMORY_SLOT_REMOVE_EVENT, 1));
1109 aml_append(field,
1110 /* initiates device eject, write only */
1111 aml_named_field(MEMORY_SLOT_EJECT, 1));
1112 aml_append(scope, field);
1113
1114 field = aml_field(MEMORY_HOTPLUG_IO_REGION, AML_DWORD_ACC,
1115 AML_NOLOCK, AML_PRESERVE);
1116 aml_append(field, /* DIMM selector, write only */
1117 aml_named_field(MEMORY_SLOT_SLECTOR, 32));
1118 aml_append(field, /* _OST event code, write only */
1119 aml_named_field(MEMORY_SLOT_OST_EVENT, 32));
1120 aml_append(field, /* _OST status code, write only */
1121 aml_named_field(MEMORY_SLOT_OST_STATUS, 32));
1122 aml_append(scope, field);
1123 aml_append(sb_scope, scope);
1124
1125 for (i = 0; i < nr_mem; i++) {
1126 #define BASEPATH "\\_SB.PCI0." MEMORY_HOTPLUG_DEVICE "."
1127 const char *s;
1128
1129 dev = aml_device("MP%02X", i);
1130 aml_append(dev, aml_name_decl("_UID", aml_string("0x%02X", i)));
1131 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C80")));
1132
1133 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1134 s = BASEPATH MEMORY_SLOT_CRS_METHOD;
1135 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1136 aml_append(dev, method);
1137
1138 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1139 s = BASEPATH MEMORY_SLOT_STATUS_METHOD;
1140 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1141 aml_append(dev, method);
1142
1143 method = aml_method("_PXM", 0, AML_NOTSERIALIZED);
1144 s = BASEPATH MEMORY_SLOT_PROXIMITY_METHOD;
1145 aml_append(method, aml_return(aml_call1(s, aml_name("_UID"))));
1146 aml_append(dev, method);
1147
1148 method = aml_method("_OST", 3, AML_NOTSERIALIZED);
1149 s = BASEPATH MEMORY_SLOT_OST_METHOD;
1150
1151 aml_append(method, aml_return(aml_call4(
1152 s, aml_name("_UID"), aml_arg(0), aml_arg(1), aml_arg(2)
1153 )));
1154 aml_append(dev, method);
1155
1156 method = aml_method("_EJ0", 1, AML_NOTSERIALIZED);
1157 s = BASEPATH MEMORY_SLOT_EJECT_METHOD;
1158 aml_append(method, aml_return(aml_call2(
1159 s, aml_name("_UID"), aml_arg(0))));
1160 aml_append(dev, method);
1161
1162 aml_append(sb_scope, dev);
1163 }
1164
1165 /* build Method(MEMORY_SLOT_NOTIFY_METHOD, 2) {
1166 * If (LEqual(Arg0, 0x00)) {Notify(MP00, Arg1)} ... }
1167 */
1168 method = aml_method(MEMORY_SLOT_NOTIFY_METHOD, 2, AML_NOTSERIALIZED);
1169 for (i = 0; i < nr_mem; i++) {
1170 ifctx = aml_if(aml_equal(aml_arg(0), aml_int(i)));
1171 aml_append(ifctx,
1172 aml_notify(aml_name("MP%.02X", i), aml_arg(1))
1173 );
1174 aml_append(method, ifctx);
1175 }
1176 aml_append(sb_scope, method);
1177 }
1178
1179 static void build_hpet_aml(Aml *table)
1180 {
1181 Aml *crs;
1182 Aml *field;
1183 Aml *method;
1184 Aml *if_ctx;
1185 Aml *scope = aml_scope("_SB");
1186 Aml *dev = aml_device("HPET");
1187 Aml *zero = aml_int(0);
1188 Aml *id = aml_local(0);
1189 Aml *period = aml_local(1);
1190
1191 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0103")));
1192 aml_append(dev, aml_name_decl("_UID", zero));
1193
1194 aml_append(dev,
1195 aml_operation_region("HPTM", AML_SYSTEM_MEMORY, aml_int(HPET_BASE),
1196 HPET_LEN));
1197 field = aml_field("HPTM", AML_DWORD_ACC, AML_LOCK, AML_PRESERVE);
1198 aml_append(field, aml_named_field("VEND", 32));
1199 aml_append(field, aml_named_field("PRD", 32));
1200 aml_append(dev, field);
1201
1202 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1203 aml_append(method, aml_store(aml_name("VEND"), id));
1204 aml_append(method, aml_store(aml_name("PRD"), period));
1205 aml_append(method, aml_shiftright(id, aml_int(16), id));
1206 if_ctx = aml_if(aml_lor(aml_equal(id, zero),
1207 aml_equal(id, aml_int(0xffff))));
1208 {
1209 aml_append(if_ctx, aml_return(zero));
1210 }
1211 aml_append(method, if_ctx);
1212
1213 if_ctx = aml_if(aml_lor(aml_equal(period, zero),
1214 aml_lgreater(period, aml_int(100000000))));
1215 {
1216 aml_append(if_ctx, aml_return(zero));
1217 }
1218 aml_append(method, if_ctx);
1219
1220 aml_append(method, aml_return(aml_int(0x0F)));
1221 aml_append(dev, method);
1222
1223 crs = aml_resource_template();
1224 aml_append(crs, aml_memory32_fixed(HPET_BASE, HPET_LEN, AML_READ_ONLY));
1225 aml_append(dev, aml_name_decl("_CRS", crs));
1226
1227 aml_append(scope, dev);
1228 aml_append(table, scope);
1229 }
1230
1231 static Aml *build_fdc_device_aml(void)
1232 {
1233 Aml *dev;
1234 Aml *crs;
1235 Aml *method;
1236 Aml *if_ctx;
1237 Aml *else_ctx;
1238 Aml *zero = aml_int(0);
1239 Aml *is_present = aml_local(0);
1240
1241 dev = aml_device("FDC0");
1242 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0700")));
1243
1244 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1245 aml_append(method, aml_store(aml_name("FDEN"), is_present));
1246 if_ctx = aml_if(aml_equal(is_present, zero));
1247 {
1248 aml_append(if_ctx, aml_return(aml_int(0x00)));
1249 }
1250 aml_append(method, if_ctx);
1251 else_ctx = aml_else();
1252 {
1253 aml_append(else_ctx, aml_return(aml_int(0x0f)));
1254 }
1255 aml_append(method, else_ctx);
1256 aml_append(dev, method);
1257
1258 crs = aml_resource_template();
1259 aml_append(crs, aml_io(AML_DECODE16, 0x03F2, 0x03F2, 0x00, 0x04));
1260 aml_append(crs, aml_io(AML_DECODE16, 0x03F7, 0x03F7, 0x00, 0x01));
1261 aml_append(crs, aml_irq_no_flags(6));
1262 aml_append(crs,
1263 aml_dma(AML_COMPATIBILITY, AML_NOTBUSMASTER, AML_TRANSFER8, 2));
1264 aml_append(dev, aml_name_decl("_CRS", crs));
1265
1266 return dev;
1267 }
1268
1269 static Aml *build_rtc_device_aml(void)
1270 {
1271 Aml *dev;
1272 Aml *crs;
1273
1274 dev = aml_device("RTC");
1275 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0B00")));
1276 crs = aml_resource_template();
1277 aml_append(crs, aml_io(AML_DECODE16, 0x0070, 0x0070, 0x10, 0x02));
1278 aml_append(crs, aml_irq_no_flags(8));
1279 aml_append(crs, aml_io(AML_DECODE16, 0x0072, 0x0072, 0x02, 0x06));
1280 aml_append(dev, aml_name_decl("_CRS", crs));
1281
1282 return dev;
1283 }
1284
1285 static Aml *build_kbd_device_aml(void)
1286 {
1287 Aml *dev;
1288 Aml *crs;
1289 Aml *method;
1290
1291 dev = aml_device("KBD");
1292 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0303")));
1293
1294 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1295 aml_append(method, aml_return(aml_int(0x0f)));
1296 aml_append(dev, method);
1297
1298 crs = aml_resource_template();
1299 aml_append(crs, aml_io(AML_DECODE16, 0x0060, 0x0060, 0x01, 0x01));
1300 aml_append(crs, aml_io(AML_DECODE16, 0x0064, 0x0064, 0x01, 0x01));
1301 aml_append(crs, aml_irq_no_flags(1));
1302 aml_append(dev, aml_name_decl("_CRS", crs));
1303
1304 return dev;
1305 }
1306
1307 static Aml *build_mouse_device_aml(void)
1308 {
1309 Aml *dev;
1310 Aml *crs;
1311 Aml *method;
1312
1313 dev = aml_device("MOU");
1314 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0F13")));
1315
1316 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1317 aml_append(method, aml_return(aml_int(0x0f)));
1318 aml_append(dev, method);
1319
1320 crs = aml_resource_template();
1321 aml_append(crs, aml_irq_no_flags(12));
1322 aml_append(dev, aml_name_decl("_CRS", crs));
1323
1324 return dev;
1325 }
1326
1327 static Aml *build_lpt_device_aml(void)
1328 {
1329 Aml *dev;
1330 Aml *crs;
1331 Aml *method;
1332 Aml *if_ctx;
1333 Aml *else_ctx;
1334 Aml *zero = aml_int(0);
1335 Aml *is_present = aml_local(0);
1336
1337 dev = aml_device("LPT");
1338 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0400")));
1339
1340 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1341 aml_append(method, aml_store(aml_name("LPEN"), is_present));
1342 if_ctx = aml_if(aml_equal(is_present, zero));
1343 {
1344 aml_append(if_ctx, aml_return(aml_int(0x00)));
1345 }
1346 aml_append(method, if_ctx);
1347 else_ctx = aml_else();
1348 {
1349 aml_append(else_ctx, aml_return(aml_int(0x0f)));
1350 }
1351 aml_append(method, else_ctx);
1352 aml_append(dev, method);
1353
1354 crs = aml_resource_template();
1355 aml_append(crs, aml_io(AML_DECODE16, 0x0378, 0x0378, 0x08, 0x08));
1356 aml_append(crs, aml_irq_no_flags(7));
1357 aml_append(dev, aml_name_decl("_CRS", crs));
1358
1359 return dev;
1360 }
1361
1362 static Aml *build_com_device_aml(uint8_t uid)
1363 {
1364 Aml *dev;
1365 Aml *crs;
1366 Aml *method;
1367 Aml *if_ctx;
1368 Aml *else_ctx;
1369 Aml *zero = aml_int(0);
1370 Aml *is_present = aml_local(0);
1371 const char *enabled_field = "CAEN";
1372 uint8_t irq = 4;
1373 uint16_t io_port = 0x03F8;
1374
1375 assert(uid == 1 || uid == 2);
1376 if (uid == 2) {
1377 enabled_field = "CBEN";
1378 irq = 3;
1379 io_port = 0x02F8;
1380 }
1381
1382 dev = aml_device("COM%d", uid);
1383 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0501")));
1384 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1385
1386 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1387 aml_append(method, aml_store(aml_name("%s", enabled_field), is_present));
1388 if_ctx = aml_if(aml_equal(is_present, zero));
1389 {
1390 aml_append(if_ctx, aml_return(aml_int(0x00)));
1391 }
1392 aml_append(method, if_ctx);
1393 else_ctx = aml_else();
1394 {
1395 aml_append(else_ctx, aml_return(aml_int(0x0f)));
1396 }
1397 aml_append(method, else_ctx);
1398 aml_append(dev, method);
1399
1400 crs = aml_resource_template();
1401 aml_append(crs, aml_io(AML_DECODE16, io_port, io_port, 0x00, 0x08));
1402 aml_append(crs, aml_irq_no_flags(irq));
1403 aml_append(dev, aml_name_decl("_CRS", crs));
1404
1405 return dev;
1406 }
1407
1408 static void build_isa_devices_aml(Aml *table)
1409 {
1410 Aml *scope = aml_scope("_SB.PCI0.ISA");
1411
1412 aml_append(scope, build_rtc_device_aml());
1413 aml_append(scope, build_kbd_device_aml());
1414 aml_append(scope, build_mouse_device_aml());
1415 aml_append(scope, build_fdc_device_aml());
1416 aml_append(scope, build_lpt_device_aml());
1417 aml_append(scope, build_com_device_aml(1));
1418 aml_append(scope, build_com_device_aml(2));
1419
1420 aml_append(table, scope);
1421 }
1422
1423 static void build_dbg_aml(Aml *table)
1424 {
1425 Aml *field;
1426 Aml *method;
1427 Aml *while_ctx;
1428 Aml *scope = aml_scope("\\");
1429 Aml *buf = aml_local(0);
1430 Aml *len = aml_local(1);
1431 Aml *idx = aml_local(2);
1432
1433 aml_append(scope,
1434 aml_operation_region("DBG", AML_SYSTEM_IO, aml_int(0x0402), 0x01));
1435 field = aml_field("DBG", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1436 aml_append(field, aml_named_field("DBGB", 8));
1437 aml_append(scope, field);
1438
1439 method = aml_method("DBUG", 1, AML_NOTSERIALIZED);
1440
1441 aml_append(method, aml_to_hexstring(aml_arg(0), buf));
1442 aml_append(method, aml_to_buffer(buf, buf));
1443 aml_append(method, aml_subtract(aml_sizeof(buf), aml_int(1), len));
1444 aml_append(method, aml_store(aml_int(0), idx));
1445
1446 while_ctx = aml_while(aml_lless(idx, len));
1447 aml_append(while_ctx,
1448 aml_store(aml_derefof(aml_index(buf, idx)), aml_name("DBGB")));
1449 aml_append(while_ctx, aml_increment(idx));
1450 aml_append(method, while_ctx);
1451
1452 aml_append(method, aml_store(aml_int(0x0A), aml_name("DBGB")));
1453 aml_append(scope, method);
1454
1455 aml_append(table, scope);
1456 }
1457
1458 static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg)
1459 {
1460 Aml *dev;
1461 Aml *crs;
1462 Aml *method;
1463 uint32_t irqs[] = {5, 10, 11};
1464
1465 dev = aml_device("%s", name);
1466 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1467 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1468
1469 crs = aml_resource_template();
1470 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1471 AML_SHARED, irqs, ARRAY_SIZE(irqs)));
1472 aml_append(dev, aml_name_decl("_PRS", crs));
1473
1474 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1475 aml_append(method, aml_return(aml_call1("IQST", reg)));
1476 aml_append(dev, method);
1477
1478 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1479 aml_append(method, aml_or(reg, aml_int(0x80), reg));
1480 aml_append(dev, method);
1481
1482 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1483 aml_append(method, aml_return(aml_call1("IQCR", reg)));
1484 aml_append(dev, method);
1485
1486 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1487 aml_append(method, aml_create_dword_field(aml_arg(0), aml_int(5), "PRRI"));
1488 aml_append(method, aml_store(aml_name("PRRI"), reg));
1489 aml_append(dev, method);
1490
1491 return dev;
1492 }
1493
1494 static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi)
1495 {
1496 Aml *dev;
1497 Aml *crs;
1498 Aml *method;
1499 uint32_t irqs;
1500
1501 dev = aml_device("%s", name);
1502 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1503 aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
1504
1505 crs = aml_resource_template();
1506 irqs = gsi;
1507 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
1508 AML_SHARED, &irqs, 1));
1509 aml_append(dev, aml_name_decl("_PRS", crs));
1510
1511 aml_append(dev, aml_name_decl("_CRS", crs));
1512
1513 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1514 aml_append(dev, method);
1515
1516 return dev;
1517 }
1518
1519 /* _CRS method - get current settings */
1520 static Aml *build_iqcr_method(bool is_piix4)
1521 {
1522 Aml *if_ctx;
1523 uint32_t irqs;
1524 Aml *method = aml_method("IQCR", 1, AML_SERIALIZED);
1525 Aml *crs = aml_resource_template();
1526
1527 irqs = 0;
1528 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1529 AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1));
1530 aml_append(method, aml_name_decl("PRR0", crs));
1531
1532 aml_append(method,
1533 aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
1534
1535 if (is_piix4) {
1536 if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
1537 aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI")));
1538 aml_append(method, if_ctx);
1539 } else {
1540 aml_append(method,
1541 aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL),
1542 aml_name("PRRI")));
1543 }
1544
1545 aml_append(method, aml_return(aml_name("PRR0")));
1546 return method;
1547 }
1548
1549 /* _STA method - get status */
1550 static Aml *build_irq_status_method(void)
1551 {
1552 Aml *if_ctx;
1553 Aml *method = aml_method("IQST", 1, AML_NOTSERIALIZED);
1554
1555 if_ctx = aml_if(aml_and(aml_int(0x80), aml_arg(0), NULL));
1556 aml_append(if_ctx, aml_return(aml_int(0x09)));
1557 aml_append(method, if_ctx);
1558 aml_append(method, aml_return(aml_int(0x0B)));
1559 return method;
1560 }
1561
1562 static void build_piix4_pci0_int(Aml *table)
1563 {
1564 Aml *dev;
1565 Aml *crs;
1566 Aml *field;
1567 Aml *method;
1568 uint32_t irqs;
1569 Aml *sb_scope = aml_scope("_SB");
1570 Aml *pci0_scope = aml_scope("PCI0");
1571
1572 aml_append(pci0_scope, build_prt(true));
1573 aml_append(sb_scope, pci0_scope);
1574
1575 field = aml_field("PCI0.ISA.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1576 aml_append(field, aml_named_field("PRQ0", 8));
1577 aml_append(field, aml_named_field("PRQ1", 8));
1578 aml_append(field, aml_named_field("PRQ2", 8));
1579 aml_append(field, aml_named_field("PRQ3", 8));
1580 aml_append(sb_scope, field);
1581
1582 aml_append(sb_scope, build_irq_status_method());
1583 aml_append(sb_scope, build_iqcr_method(true));
1584
1585 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0")));
1586 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1")));
1587 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2")));
1588 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3")));
1589
1590 dev = aml_device("LNKS");
1591 {
1592 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C0F")));
1593 aml_append(dev, aml_name_decl("_UID", aml_int(4)));
1594
1595 crs = aml_resource_template();
1596 irqs = 9;
1597 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
1598 AML_ACTIVE_HIGH, AML_SHARED,
1599 &irqs, 1));
1600 aml_append(dev, aml_name_decl("_PRS", crs));
1601
1602 /* The SCI cannot be disabled and is always attached to GSI 9,
1603 * so these are no-ops. We only need this link to override the
1604 * polarity to active high and match the content of the MADT.
1605 */
1606 method = aml_method("_STA", 0, AML_NOTSERIALIZED);
1607 aml_append(method, aml_return(aml_int(0x0b)));
1608 aml_append(dev, method);
1609
1610 method = aml_method("_DIS", 0, AML_NOTSERIALIZED);
1611 aml_append(dev, method);
1612
1613 method = aml_method("_CRS", 0, AML_NOTSERIALIZED);
1614 aml_append(method, aml_return(aml_name("_PRS")));
1615 aml_append(dev, method);
1616
1617 method = aml_method("_SRS", 1, AML_NOTSERIALIZED);
1618 aml_append(dev, method);
1619 }
1620 aml_append(sb_scope, dev);
1621
1622 aml_append(table, sb_scope);
1623 }
1624
1625 static void append_q35_prt_entry(Aml *ctx, uint32_t nr, const char *name)
1626 {
1627 int i;
1628 int head;
1629 Aml *pkg;
1630 char base = name[3] < 'E' ? 'A' : 'E';
1631 char *s = g_strdup(name);
1632 Aml *a_nr = aml_int((nr << 16) | 0xffff);
1633
1634 assert(strlen(s) == 4);
1635
1636 head = name[3] - base;
1637 for (i = 0; i < 4; i++) {
1638 if (head + i > 3) {
1639 head = i * -1;
1640 }
1641 s[3] = base + head + i;
1642 pkg = aml_package(4);
1643 aml_append(pkg, a_nr);
1644 aml_append(pkg, aml_int(i));
1645 aml_append(pkg, aml_name("%s", s));
1646 aml_append(pkg, aml_int(0));
1647 aml_append(ctx, pkg);
1648 }
1649 g_free(s);
1650 }
1651
1652 static Aml *build_q35_routing_table(const char *str)
1653 {
1654 int i;
1655 Aml *pkg;
1656 char *name = g_strdup_printf("%s ", str);
1657
1658 pkg = aml_package(128);
1659 for (i = 0; i < 0x18; i++) {
1660 name[3] = 'E' + (i & 0x3);
1661 append_q35_prt_entry(pkg, i, name);
1662 }
1663
1664 name[3] = 'E';
1665 append_q35_prt_entry(pkg, 0x18, name);
1666
1667 /* INTA -> PIRQA for slot 25 - 31, see the default value of D<N>IR */
1668 for (i = 0x0019; i < 0x1e; i++) {
1669 name[3] = 'A';
1670 append_q35_prt_entry(pkg, i, name);
1671 }
1672
1673 /* PCIe->PCI bridge. use PIRQ[E-H] */
1674 name[3] = 'E';
1675 append_q35_prt_entry(pkg, 0x1e, name);
1676 name[3] = 'A';
1677 append_q35_prt_entry(pkg, 0x1f, name);
1678
1679 g_free(name);
1680 return pkg;
1681 }
1682
1683 static void build_q35_pci0_int(Aml *table)
1684 {
1685 Aml *field;
1686 Aml *method;
1687 Aml *sb_scope = aml_scope("_SB");
1688 Aml *pci0_scope = aml_scope("PCI0");
1689
1690 /* Zero => PIC mode, One => APIC Mode */
1691 aml_append(table, aml_name_decl("PICF", aml_int(0)));
1692 method = aml_method("_PIC", 1, AML_NOTSERIALIZED);
1693 {
1694 aml_append(method, aml_store(aml_arg(0), aml_name("PICF")));
1695 }
1696 aml_append(table, method);
1697
1698 aml_append(pci0_scope,
1699 aml_name_decl("PRTP", build_q35_routing_table("LNK")));
1700 aml_append(pci0_scope,
1701 aml_name_decl("PRTA", build_q35_routing_table("GSI")));
1702
1703 method = aml_method("_PRT", 0, AML_NOTSERIALIZED);
1704 {
1705 Aml *if_ctx;
1706 Aml *else_ctx;
1707
1708 /* PCI IRQ routing table, example from ACPI 2.0a specification,
1709 section 6.2.8.1 */
1710 /* Note: we provide the same info as the PCI routing
1711 table of the Bochs BIOS */
1712 if_ctx = aml_if(aml_equal(aml_name("PICF"), aml_int(0)));
1713 aml_append(if_ctx, aml_return(aml_name("PRTP")));
1714 aml_append(method, if_ctx);
1715 else_ctx = aml_else();
1716 aml_append(else_ctx, aml_return(aml_name("PRTA")));
1717 aml_append(method, else_ctx);
1718 }
1719 aml_append(pci0_scope, method);
1720 aml_append(sb_scope, pci0_scope);
1721
1722 field = aml_field("PCI0.ISA.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
1723 aml_append(field, aml_named_field("PRQA", 8));
1724 aml_append(field, aml_named_field("PRQB", 8));
1725 aml_append(field, aml_named_field("PRQC", 8));
1726 aml_append(field, aml_named_field("PRQD", 8));
1727 aml_append(field, aml_reserved_field(0x20));
1728 aml_append(field, aml_named_field("PRQE", 8));
1729 aml_append(field, aml_named_field("PRQF", 8));
1730 aml_append(field, aml_named_field("PRQG", 8));
1731 aml_append(field, aml_named_field("PRQH", 8));
1732 aml_append(sb_scope, field);
1733
1734 aml_append(sb_scope, build_irq_status_method());
1735 aml_append(sb_scope, build_iqcr_method(false));
1736
1737 aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA")));
1738 aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB")));
1739 aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC")));
1740 aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD")));
1741 aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE")));
1742 aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF")));
1743 aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG")));
1744 aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH")));
1745
1746 /*
1747 * TODO: UID probably shouldn't be the same for GSIx devices
1748 * but that's how it was in original ASL so keep it for now
1749 */
1750 aml_append(sb_scope, build_gsi_link_dev("GSIA", 0, 0x10));
1751 aml_append(sb_scope, build_gsi_link_dev("GSIB", 0, 0x11));
1752 aml_append(sb_scope, build_gsi_link_dev("GSIC", 0, 0x12));
1753 aml_append(sb_scope, build_gsi_link_dev("GSID", 0, 0x13));
1754 aml_append(sb_scope, build_gsi_link_dev("GSIE", 0, 0x14));
1755 aml_append(sb_scope, build_gsi_link_dev("GSIF", 0, 0x15));
1756 aml_append(sb_scope, build_gsi_link_dev("GSIG", 0, 0x16));
1757 aml_append(sb_scope, build_gsi_link_dev("GSIH", 0, 0x17));
1758
1759 aml_append(table, sb_scope);
1760 }
1761
1762 static void build_q35_isa_bridge(Aml *table)
1763 {
1764 Aml *dev;
1765 Aml *scope;
1766 Aml *field;
1767
1768 scope = aml_scope("_SB.PCI0");
1769 dev = aml_device("ISA");
1770 aml_append(dev, aml_name_decl("_ADR", aml_int(0x001F0000)));
1771
1772 /* ICH9 PCI to ISA irq remapping */
1773 aml_append(dev, aml_operation_region("PIRQ", AML_PCI_CONFIG,
1774 aml_int(0x60), 0x0C));
1775
1776 aml_append(dev, aml_operation_region("LPCD", AML_PCI_CONFIG,
1777 aml_int(0x80), 0x02));
1778 field = aml_field("LPCD", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1779 aml_append(field, aml_named_field("COMA", 3));
1780 aml_append(field, aml_reserved_field(1));
1781 aml_append(field, aml_named_field("COMB", 3));
1782 aml_append(field, aml_reserved_field(1));
1783 aml_append(field, aml_named_field("LPTD", 2));
1784 aml_append(field, aml_reserved_field(2));
1785 aml_append(field, aml_named_field("FDCD", 2));
1786 aml_append(dev, field);
1787
1788 aml_append(dev, aml_operation_region("LPCE", AML_PCI_CONFIG,
1789 aml_int(0x82), 0x02));
1790 /* enable bits */
1791 field = aml_field("LPCE", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1792 aml_append(field, aml_named_field("CAEN", 1));
1793 aml_append(field, aml_named_field("CBEN", 1));
1794 aml_append(field, aml_named_field("LPEN", 1));
1795 aml_append(field, aml_named_field("FDEN", 1));
1796 aml_append(dev, field);
1797
1798 aml_append(scope, dev);
1799 aml_append(table, scope);
1800 }
1801
1802 static void build_piix4_pm(Aml *table)
1803 {
1804 Aml *dev;
1805 Aml *scope;
1806
1807 scope = aml_scope("_SB.PCI0");
1808 dev = aml_device("PX13");
1809 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010003)));
1810
1811 aml_append(dev, aml_operation_region("P13C", AML_PCI_CONFIG,
1812 aml_int(0x00), 0xff));
1813 aml_append(scope, dev);
1814 aml_append(table, scope);
1815 }
1816
1817 static void build_piix4_isa_bridge(Aml *table)
1818 {
1819 Aml *dev;
1820 Aml *scope;
1821 Aml *field;
1822
1823 scope = aml_scope("_SB.PCI0");
1824 dev = aml_device("ISA");
1825 aml_append(dev, aml_name_decl("_ADR", aml_int(0x00010000)));
1826
1827 /* PIIX PCI to ISA irq remapping */
1828 aml_append(dev, aml_operation_region("P40C", AML_PCI_CONFIG,
1829 aml_int(0x60), 0x04));
1830 /* enable bits */
1831 field = aml_field("^PX13.P13C", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);
1832 /* Offset(0x5f),, 7, */
1833 aml_append(field, aml_reserved_field(0x2f8));
1834 aml_append(field, aml_reserved_field(7));
1835 aml_append(field, aml_named_field("LPEN", 1));
1836 /* Offset(0x67),, 3, */
1837 aml_append(field, aml_reserved_field(0x38));
1838 aml_append(field, aml_reserved_field(3));
1839 aml_append(field, aml_named_field("CAEN", 1));
1840 aml_append(field, aml_reserved_field(3));
1841 aml_append(field, aml_named_field("CBEN", 1));
1842 aml_append(dev, field);
1843 aml_append(dev, aml_name_decl("FDEN", aml_int(1)));
1844
1845 aml_append(scope, dev);
1846 aml_append(table, scope);
1847 }
1848
1849 static void build_piix4_pci_hotplug(Aml *table)
1850 {
1851 Aml *scope;
1852 Aml *field;
1853 Aml *method;
1854
1855 scope = aml_scope("_SB.PCI0");
1856
1857 aml_append(scope,
1858 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x08));
1859 field = aml_field("PCST", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1860 aml_append(field, aml_named_field("PCIU", 32));
1861 aml_append(field, aml_named_field("PCID", 32));
1862 aml_append(scope, field);
1863
1864 aml_append(scope,
1865 aml_operation_region("SEJ", AML_SYSTEM_IO, aml_int(0xae08), 0x04));
1866 field = aml_field("SEJ", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1867 aml_append(field, aml_named_field("B0EJ", 32));
1868 aml_append(scope, field);
1869
1870 aml_append(scope,
1871 aml_operation_region("BNMR", AML_SYSTEM_IO, aml_int(0xae10), 0x04));
1872 field = aml_field("BNMR", AML_DWORD_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1873 aml_append(field, aml_named_field("BNUM", 32));
1874 aml_append(scope, field);
1875
1876 aml_append(scope, aml_mutex("BLCK", 0));
1877
1878 method = aml_method("PCEJ", 2, AML_NOTSERIALIZED);
1879 aml_append(method, aml_acquire(aml_name("BLCK"), 0xFFFF));
1880 aml_append(method, aml_store(aml_arg(0), aml_name("BNUM")));
1881 aml_append(method,
1882 aml_store(aml_shiftleft(aml_int(1), aml_arg(1)), aml_name("B0EJ")));
1883 aml_append(method, aml_release(aml_name("BLCK")));
1884 aml_append(method, aml_return(aml_int(0)));
1885 aml_append(scope, method);
1886
1887 aml_append(table, scope);
1888 }
1889
1890 static Aml *build_q35_osc_method(void)
1891 {
1892 Aml *if_ctx;
1893 Aml *if_ctx2;
1894 Aml *else_ctx;
1895 Aml *method;
1896 Aml *a_cwd1 = aml_name("CDW1");
1897 Aml *a_ctrl = aml_name("CTRL");
1898
1899 method = aml_method("_OSC", 4, AML_NOTSERIALIZED);
1900 aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1"));
1901
1902 if_ctx = aml_if(aml_equal(
1903 aml_arg(0), aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766")));
1904 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2"));
1905 aml_append(if_ctx, aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3"));
1906
1907 aml_append(if_ctx, aml_store(aml_name("CDW2"), aml_name("SUPP")));
1908 aml_append(if_ctx, aml_store(aml_name("CDW3"), a_ctrl));
1909
1910 /*
1911 * Always allow native PME, AER (no dependencies)
1912 * Never allow SHPC (no SHPC controller in this system)
1913 */
1914 aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1D), a_ctrl));
1915
1916 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1))));
1917 /* Unknown revision */
1918 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x08), a_cwd1));
1919 aml_append(if_ctx, if_ctx2);
1920
1921 if_ctx2 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), a_ctrl)));
1922 /* Capabilities bits were masked */
1923 aml_append(if_ctx2, aml_or(a_cwd1, aml_int(0x10), a_cwd1));
1924 aml_append(if_ctx, if_ctx2);
1925
1926 /* Update DWORD3 in the buffer */
1927 aml_append(if_ctx, aml_store(a_ctrl, aml_name("CDW3")));
1928 aml_append(method, if_ctx);
1929
1930 else_ctx = aml_else();
1931 /* Unrecognized UUID */
1932 aml_append(else_ctx, aml_or(a_cwd1, aml_int(4), a_cwd1));
1933 aml_append(method, else_ctx);
1934
1935 aml_append(method, aml_return(aml_arg(3)));
1936 return method;
1937 }
1938
1939 static void
1940 build_dsdt(GArray *table_data, GArray *linker,
1941 AcpiCpuInfo *cpu, AcpiPmInfo *pm, AcpiMiscInfo *misc,
1942 PcPciInfo *pci)
1943 {
1944 CrsRangeEntry *entry;
1945 Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs;
1946 GPtrArray *mem_ranges = g_ptr_array_new_with_free_func(crs_range_free);
1947 GPtrArray *io_ranges = g_ptr_array_new_with_free_func(crs_range_free);
1948 MachineState *machine = MACHINE(qdev_get_machine());
1949 PCMachineState *pcms = PC_MACHINE(machine);
1950 uint32_t nr_mem = machine->ram_slots;
1951 int root_bus_limit = 0xFF;
1952 PCIBus *bus = NULL;
1953 int i;
1954
1955 dsdt = init_aml_allocator();
1956
1957 /* Reserve space for header */
1958 acpi_data_push(dsdt->buf, sizeof(AcpiTableHeader));
1959
1960 build_dbg_aml(dsdt);
1961 if (misc->is_piix4) {
1962 sb_scope = aml_scope("_SB");
1963 dev = aml_device("PCI0");
1964 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
1965 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1966 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
1967 aml_append(sb_scope, dev);
1968 aml_append(dsdt, sb_scope);
1969
1970 build_hpet_aml(dsdt);
1971 build_piix4_pm(dsdt);
1972 build_piix4_isa_bridge(dsdt);
1973 build_isa_devices_aml(dsdt);
1974 build_piix4_pci_hotplug(dsdt);
1975 build_piix4_pci0_int(dsdt);
1976 } else {
1977 sb_scope = aml_scope("_SB");
1978 aml_append(sb_scope,
1979 aml_operation_region("PCST", AML_SYSTEM_IO, aml_int(0xae00), 0x0c));
1980 aml_append(sb_scope,
1981 aml_operation_region("PCSB", AML_SYSTEM_IO, aml_int(0xae0c), 0x01));
1982 field = aml_field("PCSB", AML_ANY_ACC, AML_NOLOCK, AML_WRITE_AS_ZEROS);
1983 aml_append(field, aml_named_field("PCIB", 8));
1984 aml_append(sb_scope, field);
1985 aml_append(dsdt, sb_scope);
1986
1987 sb_scope = aml_scope("_SB");
1988 dev = aml_device("PCI0");
1989 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08")));
1990 aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03")));
1991 aml_append(dev, aml_name_decl("_ADR", aml_int(0)));
1992 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
1993 aml_append(dev, aml_name_decl("SUPP", aml_int(0)));
1994 aml_append(dev, aml_name_decl("CTRL", aml_int(0)));
1995 aml_append(dev, build_q35_osc_method());
1996 aml_append(sb_scope, dev);
1997 aml_append(dsdt, sb_scope);
1998
1999 build_hpet_aml(dsdt);
2000 build_q35_isa_bridge(dsdt);
2001 build_isa_devices_aml(dsdt);
2002 build_q35_pci0_int(dsdt);
2003 }
2004
2005 build_cpu_hotplug_aml(dsdt);
2006 build_memory_hotplug_aml(dsdt, nr_mem, pm->mem_hp_io_base,
2007 pm->mem_hp_io_len);
2008
2009 scope = aml_scope("_GPE");
2010 {
2011 aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006")));
2012
2013 aml_append(scope, aml_method("_L00", 0, AML_NOTSERIALIZED));
2014
2015 if (misc->is_piix4) {
2016 method = aml_method("_E01", 0, AML_NOTSERIALIZED);
2017 aml_append(method,
2018 aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF));
2019 aml_append(method, aml_call0("\\_SB.PCI0.PCNT"));
2020 aml_append(method, aml_release(aml_name("\\_SB.PCI0.BLCK")));
2021 aml_append(scope, method);
2022 } else {
2023 aml_append(scope, aml_method("_L01", 0, AML_NOTSERIALIZED));
2024 }
2025
2026 method = aml_method("_E02", 0, AML_NOTSERIALIZED);
2027 aml_append(method, aml_call0("\\_SB." CPU_SCAN_METHOD));
2028 aml_append(scope, method);
2029
2030 method = aml_method("_E03", 0, AML_NOTSERIALIZED);
2031 aml_append(method, aml_call0(MEMORY_HOTPLUG_HANDLER_PATH));
2032 aml_append(scope, method);
2033
2034 aml_append(scope, aml_method("_L04", 0, AML_NOTSERIALIZED));
2035 aml_append(scope, aml_method("_L05", 0, AML_NOTSERIALIZED));
2036 aml_append(scope, aml_method("_L06", 0, AML_NOTSERIALIZED));
2037 aml_append(scope, aml_method("_L07", 0, AML_NOTSERIALIZED));
2038 aml_append(scope, aml_method("_L08", 0, AML_NOTSERIALIZED));
2039 aml_append(scope, aml_method("_L09", 0, AML_NOTSERIALIZED));
2040 aml_append(scope, aml_method("_L0A", 0, AML_NOTSERIALIZED));
2041 aml_append(scope, aml_method("_L0B", 0, AML_NOTSERIALIZED));
2042 aml_append(scope, aml_method("_L0C", 0, AML_NOTSERIALIZED));
2043 aml_append(scope, aml_method("_L0D", 0, AML_NOTSERIALIZED));
2044 aml_append(scope, aml_method("_L0E", 0, AML_NOTSERIALIZED));
2045 aml_append(scope, aml_method("_L0F", 0, AML_NOTSERIALIZED));
2046 }
2047 aml_append(dsdt, scope);
2048
2049 bus = PC_MACHINE(machine)->bus;
2050 if (bus) {
2051 QLIST_FOREACH(bus, &bus->child, sibling) {
2052 uint8_t bus_num = pci_bus_num(bus);
2053 uint8_t numa_node = pci_bus_numa_node(bus);
2054
2055 /* look only for expander root buses */
2056 if (!pci_bus_is_root(bus)) {
2057 continue;
2058 }
2059
2060 if (bus_num < root_bus_limit) {
2061 root_bus_limit = bus_num - 1;
2062 }
2063
2064 scope = aml_scope("\\_SB");
2065 dev = aml_device("PC%.02X", bus_num);
2066 aml_append(dev, aml_name_decl("_UID", aml_int(bus_num)));
2067 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03")));
2068 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num)));
2069
2070 if (numa_node != NUMA_NODE_UNASSIGNED) {
2071 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node)));
2072 }
2073
2074 aml_append(dev, build_prt(false));
2075 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent),
2076 io_ranges, mem_ranges);
2077 aml_append(dev, aml_name_decl("_CRS", crs));
2078 aml_append(scope, dev);
2079 aml_append(dsdt, scope);
2080 }
2081 }
2082
2083 scope = aml_scope("\\_SB.PCI0");
2084 /* build PCI0._CRS */
2085 crs = aml_resource_template();
2086 aml_append(crs,
2087 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE,
2088 0x0000, 0x0, root_bus_limit,
2089 0x0000, root_bus_limit + 1));
2090 aml_append(crs, aml_io(AML_DECODE16, 0x0CF8, 0x0CF8, 0x01, 0x08));
2091
2092 aml_append(crs,
2093 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
2094 AML_POS_DECODE, AML_ENTIRE_RANGE,
2095 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8));
2096
2097 crs_replace_with_free_ranges(io_ranges, 0x0D00, 0xFFFF);
2098 for (i = 0; i < io_ranges->len; i++) {
2099 entry = g_ptr_array_index(io_ranges, i);
2100 aml_append(crs,
2101 aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED,
2102 AML_POS_DECODE, AML_ENTIRE_RANGE,
2103 0x0000, entry->base, entry->limit,
2104 0x0000, entry->limit - entry->base + 1));
2105 }
2106
2107 aml_append(crs,
2108 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
2109 AML_CACHEABLE, AML_READ_WRITE,
2110 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000));
2111
2112 crs_replace_with_free_ranges(mem_ranges, pci->w32.begin, pci->w32.end - 1);
2113 for (i = 0; i < mem_ranges->len; i++) {
2114 entry = g_ptr_array_index(mem_ranges, i);
2115 aml_append(crs,
2116 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
2117 AML_NON_CACHEABLE, AML_READ_WRITE,
2118 0, entry->base, entry->limit,
2119 0, entry->limit - entry->base + 1));
2120 }
2121
2122 if (pci->w64.begin) {
2123 aml_append(crs,
2124 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
2125 AML_CACHEABLE, AML_READ_WRITE,
2126 0, pci->w64.begin, pci->w64.end - 1, 0,
2127 pci->w64.end - pci->w64.begin));
2128 }
2129 aml_append(scope, aml_name_decl("_CRS", crs));
2130
2131 /* reserve GPE0 block resources */
2132 dev = aml_device("GPE0");
2133 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
2134 aml_append(dev, aml_name_decl("_UID", aml_string("GPE0 resources")));
2135 /* device present, functioning, decoding, not shown in UI */
2136 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2137 crs = aml_resource_template();
2138 aml_append(crs,
2139 aml_io(AML_DECODE16, pm->gpe0_blk, pm->gpe0_blk, 1, pm->gpe0_blk_len)
2140 );
2141 aml_append(dev, aml_name_decl("_CRS", crs));
2142 aml_append(scope, dev);
2143
2144 g_ptr_array_free(io_ranges, true);
2145 g_ptr_array_free(mem_ranges, true);
2146
2147 /* reserve PCIHP resources */
2148 if (pm->pcihp_io_len) {
2149 dev = aml_device("PHPR");
2150 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06")));
2151 aml_append(dev,
2152 aml_name_decl("_UID", aml_string("PCI Hotplug resources")));
2153 /* device present, functioning, decoding, not shown in UI */
2154 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2155 crs = aml_resource_template();
2156 aml_append(crs,
2157 aml_io(AML_DECODE16, pm->pcihp_io_base, pm->pcihp_io_base, 1,
2158 pm->pcihp_io_len)
2159 );
2160 aml_append(dev, aml_name_decl("_CRS", crs));
2161 aml_append(scope, dev);
2162 }
2163 aml_append(dsdt, scope);
2164
2165 /* create S3_ / S4_ / S5_ packages if necessary */
2166 scope = aml_scope("\\");
2167 if (!pm->s3_disabled) {
2168 pkg = aml_package(4);
2169 aml_append(pkg, aml_int(1)); /* PM1a_CNT.SLP_TYP */
2170 aml_append(pkg, aml_int(1)); /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2171 aml_append(pkg, aml_int(0)); /* reserved */
2172 aml_append(pkg, aml_int(0)); /* reserved */
2173 aml_append(scope, aml_name_decl("_S3", pkg));
2174 }
2175
2176 if (!pm->s4_disabled) {
2177 pkg = aml_package(4);
2178 aml_append(pkg, aml_int(pm->s4_val)); /* PM1a_CNT.SLP_TYP */
2179 /* PM1b_CNT.SLP_TYP, FIXME: not impl. */
2180 aml_append(pkg, aml_int(pm->s4_val));
2181 aml_append(pkg, aml_int(0)); /* reserved */
2182 aml_append(pkg, aml_int(0)); /* reserved */
2183 aml_append(scope, aml_name_decl("_S4", pkg));
2184 }
2185
2186 pkg = aml_package(4);
2187 aml_append(pkg, aml_int(0)); /* PM1a_CNT.SLP_TYP */
2188 aml_append(pkg, aml_int(0)); /* PM1b_CNT.SLP_TYP not impl. */
2189 aml_append(pkg, aml_int(0)); /* reserved */
2190 aml_append(pkg, aml_int(0)); /* reserved */
2191 aml_append(scope, aml_name_decl("_S5", pkg));
2192 aml_append(dsdt, scope);
2193
2194 /* create fw_cfg node, unconditionally */
2195 {
2196 /* when using port i/o, the 8-bit data register *always* overlaps
2197 * with half of the 16-bit control register. Hence, the total size
2198 * of the i/o region used is FW_CFG_CTL_SIZE; when using DMA, the
2199 * DMA control register is located at FW_CFG_DMA_IO_BASE + 4 */
2200 uint8_t io_size = object_property_get_bool(OBJECT(pcms->fw_cfg),
2201 "dma_enabled", NULL) ?
2202 ROUND_UP(FW_CFG_CTL_SIZE, 4) + sizeof(dma_addr_t) :
2203 FW_CFG_CTL_SIZE;
2204
2205 scope = aml_scope("\\_SB.PCI0");
2206 dev = aml_device("FWCF");
2207
2208 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
2209
2210 /* device present, functioning, decoding, not shown in UI */
2211 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2212
2213 crs = aml_resource_template();
2214 aml_append(crs,
2215 aml_io(AML_DECODE16, FW_CFG_IO_BASE, FW_CFG_IO_BASE, 0x01, io_size)
2216 );
2217 aml_append(dev, aml_name_decl("_CRS", crs));
2218
2219 aml_append(scope, dev);
2220 aml_append(dsdt, scope);
2221 }
2222
2223 if (misc->applesmc_io_base) {
2224 scope = aml_scope("\\_SB.PCI0.ISA");
2225 dev = aml_device("SMC");
2226
2227 aml_append(dev, aml_name_decl("_HID", aml_eisaid("APP0001")));
2228 /* device present, functioning, decoding, not shown in UI */
2229 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
2230
2231 crs = aml_resource_template();
2232 aml_append(crs,
2233 aml_io(AML_DECODE16, misc->applesmc_io_base, misc->applesmc_io_base,
2234 0x01, APPLESMC_MAX_DATA_LENGTH)
2235 );
2236 aml_append(crs, aml_irq_no_flags(6));
2237 aml_append(dev, aml_name_decl("_CRS", crs));
2238
2239 aml_append(scope, dev);
2240 aml_append(dsdt, scope);
2241 }
2242
2243 if (misc->pvpanic_port) {
2244 scope = aml_scope("\\_SB.PCI0.ISA");
2245
2246 dev = aml_device("PEVT");
2247 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0001")));
2248
2249 crs = aml_resource_template();
2250 aml_append(crs,
2251 aml_io(AML_DECODE16, misc->pvpanic_port, misc->pvpanic_port, 1, 1)
2252 );
2253 aml_append(dev, aml_name_decl("_CRS", crs));
2254
2255 aml_append(dev, aml_operation_region("PEOR", AML_SYSTEM_IO,
2256 aml_int(misc->pvpanic_port), 1));
2257 field = aml_field("PEOR", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
2258 aml_append(field, aml_named_field("PEPT", 8));
2259 aml_append(dev, field);
2260
2261 /* device present, functioning, decoding, shown in UI */
2262 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
2263
2264 method = aml_method("RDPT", 0, AML_NOTSERIALIZED);
2265 aml_append(method, aml_store(aml_name("PEPT"), aml_local(0)));
2266 aml_append(method, aml_return(aml_local(0)));
2267 aml_append(dev, method);
2268
2269 method = aml_method("WRPT", 1, AML_NOTSERIALIZED);
2270 aml_append(method, aml_store(aml_arg(0), aml_name("PEPT")));
2271 aml_append(dev, method);
2272
2273 aml_append(scope, dev);
2274 aml_append(dsdt, scope);
2275 }
2276
2277 sb_scope = aml_scope("\\_SB");
2278 {
2279 build_processor_devices(sb_scope, pcms->apic_id_limit, cpu, pm);
2280
2281 build_memory_devices(sb_scope, nr_mem, pm->mem_hp_io_base,
2282 pm->mem_hp_io_len);
2283
2284 {
2285 Object *pci_host;
2286 PCIBus *bus = NULL;
2287
2288 pci_host = acpi_get_i386_pci_host();
2289 if (pci_host) {
2290 bus = PCI_HOST_BRIDGE(pci_host)->bus;
2291 }
2292
2293 if (bus) {
2294 Aml *scope = aml_scope("PCI0");
2295 /* Scan all PCI buses. Generate tables to support hotplug. */
2296 build_append_pci_bus_devices(scope, bus, pm->pcihp_bridge_en);
2297
2298 if (misc->tpm_version != TPM_VERSION_UNSPEC) {
2299 dev = aml_device("ISA.TPM");
2300 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0C31")));
2301 aml_append(dev, aml_name_decl("_STA", aml_int(0xF)));
2302 crs = aml_resource_template();
2303 aml_append(crs, aml_memory32_fixed(TPM_TIS_ADDR_BASE,
2304 TPM_TIS_ADDR_SIZE, AML_READ_WRITE));
2305 aml_append(crs, aml_irq_no_flags(TPM_TIS_IRQ));
2306 aml_append(dev, aml_name_decl("_CRS", crs));
2307 aml_append(scope, dev);
2308 }
2309
2310 aml_append(sb_scope, scope);
2311 }
2312 }
2313 aml_append(dsdt, sb_scope);
2314 }
2315
2316 /* copy AML table into ACPI tables blob and patch header there */
2317 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
2318 build_header(linker, table_data,
2319 (void *)(table_data->data + table_data->len - dsdt->buf->len),
2320 "DSDT", dsdt->buf->len, 1, NULL, NULL);
2321 free_aml_allocator();
2322 }
2323
2324 static void
2325 build_hpet(GArray *table_data, GArray *linker)
2326 {
2327 Acpi20Hpet *hpet;
2328
2329 hpet = acpi_data_push(table_data, sizeof(*hpet));
2330 /* Note timer_block_id value must be kept in sync with value advertised by
2331 * emulated hpet
2332 */
2333 hpet->timer_block_id = cpu_to_le32(0x8086a201);
2334 hpet->addr.address = cpu_to_le64(HPET_BASE);
2335 build_header(linker, table_data,
2336 (void *)hpet, "HPET", sizeof(*hpet), 1, NULL, NULL);
2337 }
2338
2339 static void
2340 build_tpm_tcpa(GArray *table_data, GArray *linker, GArray *tcpalog)
2341 {
2342 Acpi20Tcpa *tcpa = acpi_data_push(table_data, sizeof *tcpa);
2343 uint64_t log_area_start_address = acpi_data_len(tcpalog);
2344
2345 tcpa->platform_class = cpu_to_le16(TPM_TCPA_ACPI_CLASS_CLIENT);
2346 tcpa->log_area_minimum_length = cpu_to_le32(TPM_LOG_AREA_MINIMUM_SIZE);
2347 tcpa->log_area_start_address = cpu_to_le64(log_area_start_address);
2348
2349 bios_linker_loader_alloc(linker, ACPI_BUILD_TPMLOG_FILE, 1,
2350 false /* high memory */);
2351
2352 /* log area start address to be filled by Guest linker */
2353 bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
2354 ACPI_BUILD_TPMLOG_FILE,
2355 table_data, &tcpa->log_area_start_address,
2356 sizeof(tcpa->log_area_start_address));
2357
2358 build_header(linker, table_data,
2359 (void *)tcpa, "TCPA", sizeof(*tcpa), 2, NULL, NULL);
2360
2361 acpi_data_push(tcpalog, TPM_LOG_AREA_MINIMUM_SIZE);
2362 }
2363
2364 static void
2365 build_tpm2(GArray *table_data, GArray *linker)
2366 {
2367 Acpi20TPM2 *tpm2_ptr;
2368
2369 tpm2_ptr = acpi_data_push(table_data, sizeof *tpm2_ptr);
2370
2371 tpm2_ptr->platform_class = cpu_to_le16(TPM2_ACPI_CLASS_CLIENT);
2372 tpm2_ptr->control_area_address = cpu_to_le64(0);
2373 tpm2_ptr->start_method = cpu_to_le32(TPM2_START_METHOD_MMIO);
2374
2375 build_header(linker, table_data,
2376 (void *)tpm2_ptr, "TPM2", sizeof(*tpm2_ptr), 4, NULL, NULL);
2377 }
2378
2379 typedef enum {
2380 MEM_AFFINITY_NOFLAGS = 0,
2381 MEM_AFFINITY_ENABLED = (1 << 0),
2382 MEM_AFFINITY_HOTPLUGGABLE = (1 << 1),
2383 MEM_AFFINITY_NON_VOLATILE = (1 << 2),
2384 } MemoryAffinityFlags;
2385
2386 static void
2387 acpi_build_srat_memory(AcpiSratMemoryAffinity *numamem, uint64_t base,
2388 uint64_t len, int node, MemoryAffinityFlags flags)
2389 {
2390 numamem->type = ACPI_SRAT_MEMORY;
2391 numamem->length = sizeof(*numamem);
2392 memset(numamem->proximity, 0, 4);
2393 numamem->proximity[0] = node;
2394 numamem->flags = cpu_to_le32(flags);
2395 numamem->base_addr = cpu_to_le64(base);
2396 numamem->range_length = cpu_to_le64(len);
2397 }
2398
2399 static void
2400 build_srat(GArray *table_data, GArray *linker)
2401 {
2402 AcpiSystemResourceAffinityTable *srat;
2403 AcpiSratProcessorAffinity *core;
2404 AcpiSratMemoryAffinity *numamem;
2405
2406 int i;
2407 uint64_t curnode;
2408 int srat_start, numa_start, slots;
2409 uint64_t mem_len, mem_base, next_base;
2410 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
2411 ram_addr_t hotplugabble_address_space_size =
2412 object_property_get_int(OBJECT(pcms), PC_MACHINE_MEMHP_REGION_SIZE,
2413 NULL);
2414
2415 srat_start = table_data->len;
2416
2417 srat = acpi_data_push(table_data, sizeof *srat);
2418 srat->reserved1 = cpu_to_le32(1);
2419 core = (void *)(srat + 1);
2420
2421 for (i = 0; i < pcms->apic_id_limit; ++i) {
2422 core = acpi_data_push(table_data, sizeof *core);
2423 core->type = ACPI_SRAT_PROCESSOR;
2424 core->length = sizeof(*core);
2425 core->local_apic_id = i;
2426 curnode = pcms->node_cpu[i];
2427 core->proximity_lo = curnode;
2428 memset(core->proximity_hi, 0, 3);
2429 core->local_sapic_eid = 0;
2430 core->flags = cpu_to_le32(1);
2431 }
2432
2433
2434 /* the memory map is a bit tricky, it contains at least one hole
2435 * from 640k-1M and possibly another one from 3.5G-4G.
2436 */
2437 next_base = 0;
2438 numa_start = table_data->len;
2439
2440 numamem = acpi_data_push(table_data, sizeof *numamem);
2441 acpi_build_srat_memory(numamem, 0, 640*1024, 0, MEM_AFFINITY_ENABLED);
2442 next_base = 1024 * 1024;
2443 for (i = 1; i < pcms->numa_nodes + 1; ++i) {
2444 mem_base = next_base;
2445 mem_len = pcms->node_mem[i - 1];
2446 if (i == 1) {
2447 mem_len -= 1024 * 1024;
2448 }
2449 next_base = mem_base + mem_len;
2450
2451 /* Cut out the ACPI_PCI hole */
2452 if (mem_base <= pcms->below_4g_mem_size &&
2453 next_base > pcms->below_4g_mem_size) {
2454 mem_len -= next_base - pcms->below_4g_mem_size;
2455 if (mem_len > 0) {
2456 numamem = acpi_data_push(table_data, sizeof *numamem);
2457 acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1,
2458 MEM_AFFINITY_ENABLED);
2459 }
2460 mem_base = 1ULL << 32;
2461 mem_len = next_base - pcms->below_4g_mem_size;
2462 next_base += (1ULL << 32) - pcms->below_4g_mem_size;
2463 }
2464 numamem = acpi_data_push(table_data, sizeof *numamem);
2465 acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1,
2466 MEM_AFFINITY_ENABLED);
2467 }
2468 slots = (table_data->len - numa_start) / sizeof *numamem;
2469 for (; slots < pcms->numa_nodes + 2; slots++) {
2470 numamem = acpi_data_push(table_data, sizeof *numamem);
2471 acpi_build_srat_memory(numamem, 0, 0, 0, MEM_AFFINITY_NOFLAGS);
2472 }
2473
2474 /*
2475 * Entry is required for Windows to enable memory hotplug in OS.
2476 * Memory devices may override proximity set by this entry,
2477 * providing _PXM method if necessary.
2478 */
2479 if (hotplugabble_address_space_size) {
2480 numamem = acpi_data_push(table_data, sizeof *numamem);
2481 acpi_build_srat_memory(numamem, pcms->hotplug_memory.base,
2482 hotplugabble_address_space_size, 0,
2483 MEM_AFFINITY_HOTPLUGGABLE |
2484 MEM_AFFINITY_ENABLED);
2485 }
2486
2487 build_header(linker, table_data,
2488 (void *)(table_data->data + srat_start),
2489 "SRAT",
2490 table_data->len - srat_start, 1, NULL, NULL);
2491 }
2492
2493 static void
2494 build_mcfg_q35(GArray *table_data, GArray *linker, AcpiMcfgInfo *info)
2495 {
2496 AcpiTableMcfg *mcfg;
2497 const char *sig;
2498 int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]);
2499
2500 mcfg = acpi_data_push(table_data, len);
2501 mcfg->allocation[0].address = cpu_to_le64(info->mcfg_base);
2502 /* Only a single allocation so no need to play with segments */
2503 mcfg->allocation[0].pci_segment = cpu_to_le16(0);
2504 mcfg->allocation[0].start_bus_number = 0;
2505 mcfg->allocation[0].end_bus_number = PCIE_MMCFG_BUS(info->mcfg_size - 1);
2506
2507 /* MCFG is used for ECAM which can be enabled or disabled by guest.
2508 * To avoid table size changes (which create migration issues),
2509 * always create the table even if there are no allocations,
2510 * but set the signature to a reserved value in this case.
2511 * ACPI spec requires OSPMs to ignore such tables.
2512 */
2513 if (info->mcfg_base == PCIE_BASE_ADDR_UNMAPPED) {
2514 /* Reserved signature: ignored by OSPM */
2515 sig = "QEMU";
2516 } else {
2517 sig = "MCFG";
2518 }
2519 build_header(linker, table_data, (void *)mcfg, sig, len, 1, NULL, NULL);
2520 }
2521
2522 static void
2523 build_dmar_q35(GArray *table_data, GArray *linker)
2524 {
2525 int dmar_start = table_data->len;
2526
2527 AcpiTableDmar *dmar;
2528 AcpiDmarHardwareUnit *drhd;
2529
2530 dmar = acpi_data_push(table_data, sizeof(*dmar));
2531 dmar->host_address_width = VTD_HOST_ADDRESS_WIDTH - 1;
2532 dmar->flags = 0; /* No intr_remap for now */
2533
2534 /* DMAR Remapping Hardware Unit Definition structure */
2535 drhd = acpi_data_push(table_data, sizeof(*drhd));
2536 drhd->type = cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT);
2537 drhd->length = cpu_to_le16(sizeof(*drhd)); /* No device scope now */
2538 drhd->flags = ACPI_DMAR_INCLUDE_PCI_ALL;
2539 drhd->pci_segment = cpu_to_le16(0);
2540 drhd->address = cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR);
2541
2542 build_header(linker, table_data, (void *)(table_data->data + dmar_start),
2543 "DMAR", table_data->len - dmar_start, 1, NULL, NULL);
2544 }
2545
2546 static GArray *
2547 build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt)
2548 {
2549 AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp);
2550
2551 bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, 16,
2552 true /* fseg memory */);
2553
2554 memcpy(&rsdp->signature, "RSD PTR ", 8);
2555 memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, 6);
2556 rsdp->rsdt_physical_address = cpu_to_le32(rsdt);
2557 /* Address to be filled by Guest linker */
2558 bios_linker_loader_add_pointer(linker, ACPI_BUILD_RSDP_FILE,
2559 ACPI_BUILD_TABLE_FILE,
2560 rsdp_table, &rsdp->rsdt_physical_address,
2561 sizeof rsdp->rsdt_physical_address);
2562 rsdp->checksum = 0;
2563 /* Checksum to be filled by Guest linker */
2564 bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE,
2565 rsdp_table, rsdp, sizeof *rsdp,
2566 &rsdp->checksum);
2567
2568 return rsdp_table;
2569 }
2570
2571 typedef
2572 struct AcpiBuildState {
2573 /* Copy of table in RAM (for patching). */
2574 MemoryRegion *table_mr;
2575 /* Is table patched? */
2576 uint8_t patched;
2577 void *rsdp;
2578 MemoryRegion *rsdp_mr;
2579 MemoryRegion *linker_mr;
2580 } AcpiBuildState;
2581
2582 static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg)
2583 {
2584 Object *pci_host;
2585 QObject *o;
2586
2587 pci_host = acpi_get_i386_pci_host();
2588 g_assert(pci_host);
2589
2590 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL);
2591 if (!o) {
2592 return false;
2593 }
2594 mcfg->mcfg_base = qint_get_int(qobject_to_qint(o));
2595 qobject_decref(o);
2596
2597 o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
2598 assert(o);
2599 mcfg->mcfg_size = qint_get_int(qobject_to_qint(o));
2600 qobject_decref(o);
2601 return true;
2602 }
2603
2604 static bool acpi_has_iommu(void)
2605 {
2606 bool ambiguous;
2607 Object *intel_iommu;
2608
2609 intel_iommu = object_resolve_path_type("", TYPE_INTEL_IOMMU_DEVICE,
2610 &ambiguous);
2611 return intel_iommu && !ambiguous;
2612 }
2613
2614 static bool acpi_has_nvdimm(void)
2615 {
2616 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
2617
2618 return pcms->nvdimm;
2619 }
2620
2621 static
2622 void acpi_build(AcpiBuildTables *tables)
2623 {
2624 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
2625 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2626 GArray *table_offsets;
2627 unsigned facs, dsdt, rsdt, fadt;
2628 AcpiCpuInfo cpu;
2629 AcpiPmInfo pm;
2630 AcpiMiscInfo misc;
2631 AcpiMcfgInfo mcfg;
2632 PcPciInfo pci;
2633 uint8_t *u;
2634 size_t aml_len = 0;
2635 GArray *tables_blob = tables->table_data;
2636 AcpiSlicOem slic_oem = { .id = NULL, .table_id = NULL };
2637
2638 acpi_get_cpu_info(&cpu);
2639 acpi_get_pm_info(&pm);
2640 acpi_get_misc_info(&misc);
2641 acpi_get_pci_info(&pci);
2642 acpi_get_slic_oem(&slic_oem);
2643
2644 table_offsets = g_array_new(false, true /* clear */,
2645 sizeof(uint32_t));
2646 ACPI_BUILD_DPRINTF("init ACPI tables\n");
2647
2648 bios_linker_loader_alloc(tables->linker, ACPI_BUILD_TABLE_FILE,
2649 64 /* Ensure FACS is aligned */,
2650 false /* high memory */);
2651
2652 /*
2653 * FACS is pointed to by FADT.
2654 * We place it first since it's the only table that has alignment
2655 * requirements.
2656 */
2657 facs = tables_blob->len;
2658 build_facs(tables_blob, tables->linker);
2659
2660 /* DSDT is pointed to by FADT */
2661 dsdt = tables_blob->len;
2662 build_dsdt(tables_blob, tables->linker, &cpu, &pm, &misc, &pci);
2663
2664 /* Count the size of the DSDT and SSDT, we will need it for legacy
2665 * sizing of ACPI tables.
2666 */
2667 aml_len += tables_blob->len - dsdt;
2668
2669 /* ACPI tables pointed to by RSDT */
2670 fadt = tables_blob->len;
2671 acpi_add_table(table_offsets, tables_blob);
2672 build_fadt(tables_blob, tables->linker, &pm, facs, dsdt,
2673 slic_oem.id, slic_oem.table_id);
2674 aml_len += tables_blob->len - fadt;
2675
2676 acpi_add_table(table_offsets, tables_blob);
2677 build_madt(tables_blob, tables->linker, &cpu);
2678
2679 if (misc.has_hpet) {
2680 acpi_add_table(table_offsets, tables_blob);
2681 build_hpet(tables_blob, tables->linker);
2682 }
2683 if (misc.tpm_version != TPM_VERSION_UNSPEC) {
2684 acpi_add_table(table_offsets, tables_blob);
2685 build_tpm_tcpa(tables_blob, tables->linker, tables->tcpalog);
2686
2687 if (misc.tpm_version == TPM_VERSION_2_0) {
2688 acpi_add_table(table_offsets, tables_blob);
2689 build_tpm2(tables_blob, tables->linker);
2690 }
2691 }
2692 if (pcms->numa_nodes) {
2693 acpi_add_table(table_offsets, tables_blob);
2694 build_srat(tables_blob, tables->linker);
2695 }
2696 if (acpi_get_mcfg(&mcfg)) {
2697 acpi_add_table(table_offsets, tables_blob);
2698 build_mcfg_q35(tables_blob, tables->linker, &mcfg);
2699 }
2700 if (acpi_has_iommu()) {
2701 acpi_add_table(table_offsets, tables_blob);
2702 build_dmar_q35(tables_blob, tables->linker);
2703 }
2704
2705 if (acpi_has_nvdimm()) {
2706 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker);
2707 }
2708
2709 /* Add tables supplied by user (if any) */
2710 for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
2711 unsigned len = acpi_table_len(u);
2712
2713 acpi_add_table(table_offsets, tables_blob);
2714 g_array_append_vals(tables_blob, u, len);
2715 }
2716
2717 /* RSDT is pointed to by RSDP */
2718 rsdt = tables_blob->len;
2719 build_rsdt(tables_blob, tables->linker, table_offsets,
2720 slic_oem.id, slic_oem.table_id);
2721
2722 /* RSDP is in FSEG memory, so allocate it separately */
2723 build_rsdp(tables->rsdp, tables->linker, rsdt);
2724
2725 /* We'll expose it all to Guest so we want to reduce
2726 * chance of size changes.
2727 *
2728 * We used to align the tables to 4k, but of course this would
2729 * too simple to be enough. 4k turned out to be too small an
2730 * alignment very soon, and in fact it is almost impossible to
2731 * keep the table size stable for all (max_cpus, max_memory_slots)
2732 * combinations. So the table size is always 64k for pc-i440fx-2.1
2733 * and we give an error if the table grows beyond that limit.
2734 *
2735 * We still have the problem of migrating from "-M pc-i440fx-2.0". For
2736 * that, we exploit the fact that QEMU 2.1 generates _smaller_ tables
2737 * than 2.0 and we can always pad the smaller tables with zeros. We can
2738 * then use the exact size of the 2.0 tables.
2739 *
2740 * All this is for PIIX4, since QEMU 2.0 didn't support Q35 migration.
2741 */
2742 if (pcmc->legacy_acpi_table_size) {
2743 /* Subtracting aml_len gives the size of fixed tables. Then add the
2744 * size of the PIIX4 DSDT/SSDT in QEMU 2.0.
2745 */
2746 int legacy_aml_len =
2747 pcmc->legacy_acpi_table_size +
2748 ACPI_BUILD_LEGACY_CPU_AML_SIZE * max_cpus;
2749 int legacy_table_size =
2750 ROUND_UP(tables_blob->len - aml_len + legacy_aml_len,
2751 ACPI_BUILD_ALIGN_SIZE);
2752 if (tables_blob->len > legacy_table_size) {
2753 /* Should happen only with PCI bridges and -M pc-i440fx-2.0. */
2754 error_report("Warning: migration may not work.");
2755 }
2756 g_array_set_size(tables_blob, legacy_table_size);
2757 } else {
2758 /* Make sure we have a buffer in case we need to resize the tables. */
2759 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
2760 /* As of QEMU 2.1, this fires with 160 VCPUs and 255 memory slots. */
2761 error_report("Warning: ACPI tables are larger than 64k.");
2762 error_report("Warning: migration may not work.");
2763 error_report("Warning: please remove CPUs, NUMA nodes, "
2764 "memory slots or PCI bridges.");
2765 }
2766 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
2767 }
2768
2769 acpi_align_size(tables->linker, ACPI_BUILD_ALIGN_SIZE);
2770
2771 /* Cleanup memory that's no longer used. */
2772 g_array_free(table_offsets, true);
2773 }
2774
2775 static void acpi_ram_update(MemoryRegion *mr, GArray *data)
2776 {
2777 uint32_t size = acpi_data_len(data);
2778
2779 /* Make sure RAM size is correct - in case it got changed e.g. by migration */
2780 memory_region_ram_resize(mr, size, &error_abort);
2781
2782 memcpy(memory_region_get_ram_ptr(mr), data->data, size);
2783 memory_region_set_dirty(mr, 0, size);
2784 }
2785
2786 static void acpi_build_update(void *build_opaque)
2787 {
2788 AcpiBuildState *build_state = build_opaque;
2789 AcpiBuildTables tables;
2790
2791 /* No state to update or already patched? Nothing to do. */
2792 if (!build_state || build_state->patched) {
2793 return;
2794 }
2795 build_state->patched = 1;
2796
2797 acpi_build_tables_init(&tables);
2798
2799 acpi_build(&tables);
2800
2801 acpi_ram_update(build_state->table_mr, tables.table_data);
2802
2803 if (build_state->rsdp) {
2804 memcpy(build_state->rsdp, tables.rsdp->data, acpi_data_len(tables.rsdp));
2805 } else {
2806 acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
2807 }
2808
2809 acpi_ram_update(build_state->linker_mr, tables.linker);
2810 acpi_build_tables_cleanup(&tables, true);
2811 }
2812
2813 static void acpi_build_reset(void *build_opaque)
2814 {
2815 AcpiBuildState *build_state = build_opaque;
2816 build_state->patched = 0;
2817 }
2818
2819 static MemoryRegion *acpi_add_rom_blob(AcpiBuildState *build_state,
2820 GArray *blob, const char *name,
2821 uint64_t max_size)
2822 {
2823 return rom_add_blob(name, blob->data, acpi_data_len(blob), max_size, -1,
2824 name, acpi_build_update, build_state);
2825 }
2826
2827 static const VMStateDescription vmstate_acpi_build = {
2828 .name = "acpi_build",
2829 .version_id = 1,
2830 .minimum_version_id = 1,
2831 .fields = (VMStateField[]) {
2832 VMSTATE_UINT8(patched, AcpiBuildState),
2833 VMSTATE_END_OF_LIST()
2834 },
2835 };
2836
2837 void acpi_setup(void)
2838 {
2839 PCMachineState *pcms = PC_MACHINE(qdev_get_machine());
2840 PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
2841 AcpiBuildTables tables;
2842 AcpiBuildState *build_state;
2843
2844 if (!pcms->fw_cfg) {
2845 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n");
2846 return;
2847 }
2848
2849 if (!pcmc->has_acpi_build) {
2850 ACPI_BUILD_DPRINTF("ACPI build disabled. Bailing out.\n");
2851 return;
2852 }
2853
2854 if (!acpi_enabled) {
2855 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n");
2856 return;
2857 }
2858
2859 build_state = g_malloc0(sizeof *build_state);
2860
2861 acpi_set_pci_info();
2862
2863 acpi_build_tables_init(&tables);
2864 acpi_build(&tables);
2865
2866 /* Now expose it all to Guest */
2867 build_state->table_mr = acpi_add_rom_blob(build_state, tables.table_data,
2868 ACPI_BUILD_TABLE_FILE,
2869 ACPI_BUILD_TABLE_MAX_SIZE);
2870 assert(build_state->table_mr != NULL);
2871
2872 build_state->linker_mr =
2873 acpi_add_rom_blob(build_state, tables.linker, "etc/table-loader", 0);
2874
2875 fw_cfg_add_file(pcms->fw_cfg, ACPI_BUILD_TPMLOG_FILE,
2876 tables.tcpalog->data, acpi_data_len(tables.tcpalog));
2877
2878 if (!pcmc->rsdp_in_ram) {
2879 /*
2880 * Keep for compatibility with old machine types.
2881 * Though RSDP is small, its contents isn't immutable, so
2882 * we'll update it along with the rest of tables on guest access.
2883 */
2884 uint32_t rsdp_size = acpi_data_len(tables.rsdp);
2885
2886 build_state->rsdp = g_memdup(tables.rsdp->data, rsdp_size);
2887 fw_cfg_add_file_callback(pcms->fw_cfg, ACPI_BUILD_RSDP_FILE,
2888 acpi_build_update, build_state,
2889 build_state->rsdp, rsdp_size);
2890 build_state->rsdp_mr = NULL;
2891 } else {
2892 build_state->rsdp = NULL;
2893 build_state->rsdp_mr = acpi_add_rom_blob(build_state, tables.rsdp,
2894 ACPI_BUILD_RSDP_FILE, 0);
2895 }
2896
2897 qemu_register_reset(acpi_build_reset, build_state);
2898 acpi_build_reset(build_state);
2899 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state);
2900
2901 /* Cleanup tables but don't free the memory: we track it
2902 * in build_state.
2903 */
2904 acpi_build_tables_cleanup(&tables, false);
2905 }
QEmu