hw/intc/xics.c

   1 /*
   2  * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
   3  *
   4  * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
   5  *
   6  * Copyright (c) 2010,2011 David Gibson, IBM Corporation.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a copy
   9  * of this software and associated documentation files (the "Software"), to deal
  10  * in the Software without restriction, including without limitation the rights
  11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12  * copies of the Software, and to permit persons to whom the Software is
  13  * furnished to do so, subject to the following conditions:
  14  *
  15  * The above copyright notice and this permission notice shall be included in
  16  * all copies or substantial portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24  * THE SOFTWARE.
  25  *
  26  */
  27
  28 #include "hw/hw.h"
  29 #include "trace.h"
  30 #include "qemu/timer.h"
  31 #include "hw/ppc/spapr.h"
  32 #include "hw/ppc/xics.h"
  33 #include "qemu/error-report.h"
  34 #include "qapi/visitor.h"
  35
  36 static int get_cpu_index_by_dt_id(int cpu_dt_id)
  37 {
  38     PowerPCCPU *cpu = ppc_get_vcpu_by_dt_id(cpu_dt_id);
  39
  40     if (cpu) {
  41         return cpu->parent_obj.cpu_index;
  42     }
  43
  44     return -1;
  45 }
  46
  47 void xics_cpu_setup(XICSState *icp, PowerPCCPU *cpu)
  48 {
  49     CPUState *cs = CPU(cpu);
  50     CPUPPCState *env = &cpu->env;
  51     ICPState *ss = &icp->ss[cs->cpu_index];
  52     XICSStateClass *info = XICS_COMMON_GET_CLASS(icp);
  53
  54     assert(cs->cpu_index < icp->nr_servers);
  55
  56     if (info->cpu_setup) {
  57         info->cpu_setup(icp, cpu);
  58     }
  59
  60     switch (PPC_INPUT(env)) {
  61     case PPC_FLAGS_INPUT_POWER7:
  62         ss->output = env->irq_inputs[POWER7_INPUT_INT];
  63         break;
  64
  65     case PPC_FLAGS_INPUT_970:
  66         ss->output = env->irq_inputs[PPC970_INPUT_INT];
  67         break;
  68
  69     default:
  70         error_report("XICS interrupt controller does not support this CPU "
  71                      "bus model");
  72         abort();
  73     }
  74 }
  75
  76 /*
  77  * XICS Common class - parent for emulated XICS and KVM-XICS
  78  */
  79 static void xics_common_reset(DeviceState *d)
  80 {
  81     XICSState *icp = XICS_COMMON(d);
  82     int i;
  83
  84     for (i = 0; i < icp->nr_servers; i++) {
  85         device_reset(DEVICE(&icp->ss[i]));
  86     }
  87
  88     device_reset(DEVICE(icp->ics));
  89 }
  90
  91 static void xics_prop_get_nr_irqs(Object *obj, Visitor *v,
  92                                   void *opaque, const char *name, Error **errp)
  93 {
  94     XICSState *icp = XICS_COMMON(obj);
  95     int64_t value = icp->nr_irqs;
  96
  97     visit_type_int(v, &value, name, errp);
  98 }
  99
 100 static void xics_prop_set_nr_irqs(Object *obj, Visitor *v,
 101                                   void *opaque, const char *name, Error **errp)
 102 {
 103     XICSState *icp = XICS_COMMON(obj);
 104     XICSStateClass *info = XICS_COMMON_GET_CLASS(icp);
 105     Error *error = NULL;
 106     int64_t value;
 107
 108     visit_type_int(v, &value, name, &error);
 109     if (error) {
 110         error_propagate(errp, error);
 111         return;
 112     }
 113     if (icp->nr_irqs) {
 114         error_setg(errp, "Number of interrupts is already set to %u",
 115                    icp->nr_irqs);
 116         return;
 117     }
 118
 119     assert(info->set_nr_irqs);
 120     assert(icp->ics);
 121     info->set_nr_irqs(icp, value, errp);
 122 }
 123
 124 static void xics_prop_get_nr_servers(Object *obj, Visitor *v,
 125                                      void *opaque, const char *name,
 126                                      Error **errp)
 127 {
 128     XICSState *icp = XICS_COMMON(obj);
 129     int64_t value = icp->nr_servers;
 130
 131     visit_type_int(v, &value, name, errp);
 132 }
 133
 134 static void xics_prop_set_nr_servers(Object *obj, Visitor *v,
 135                                      void *opaque, const char *name,
 136                                      Error **errp)
 137 {
 138     XICSState *icp = XICS_COMMON(obj);
 139     XICSStateClass *info = XICS_COMMON_GET_CLASS(icp);
 140     Error *error = NULL;
 141     int64_t value;
 142
 143     visit_type_int(v, &value, name, &error);
 144     if (error) {
 145         error_propagate(errp, error);
 146         return;
 147     }
 148     if (icp->nr_servers) {
 149         error_setg(errp, "Number of servers is already set to %u",
 150                    icp->nr_servers);
 151         return;
 152     }
 153
 154     assert(info->set_nr_servers);
 155     info->set_nr_servers(icp, value, errp);
 156 }
 157
 158 static void xics_common_initfn(Object *obj)
 159 {
 160     object_property_add(obj, "nr_irqs", "int",
 161                         xics_prop_get_nr_irqs, xics_prop_set_nr_irqs,
 162                         NULL, NULL, NULL);
 163     object_property_add(obj, "nr_servers", "int",
 164                         xics_prop_get_nr_servers, xics_prop_set_nr_servers,
 165                         NULL, NULL, NULL);
 166 }
 167
 168 static void xics_common_class_init(ObjectClass *oc, void *data)
 169 {
 170     DeviceClass *dc = DEVICE_CLASS(oc);
 171
 172     dc->reset = xics_common_reset;
 173 }
 174
 175 static const TypeInfo xics_common_info = {
 176     .name          = TYPE_XICS_COMMON,
 177     .parent        = TYPE_SYS_BUS_DEVICE,
 178     .instance_size = sizeof(XICSState),
 179     .class_size    = sizeof(XICSStateClass),
 180     .instance_init = xics_common_initfn,
 181     .class_init    = xics_common_class_init,
 182 };
 183
 184 /*
 185  * ICP: Presentation layer
 186  */
 187
 188 #define XISR_MASK  0x00ffffff
 189 #define CPPR_MASK  0xff000000
 190
 191 #define XISR(ss)   (((ss)->xirr) & XISR_MASK)
 192 #define CPPR(ss)   (((ss)->xirr) >> 24)
 193
 194 static void ics_reject(ICSState *ics, int nr);
 195 static void ics_resend(ICSState *ics);
 196 static void ics_eoi(ICSState *ics, int nr);
 197
 198 static void icp_check_ipi(XICSState *icp, int server)
 199 {
 200     ICPState *ss = icp->ss + server;
 201
 202     if (XISR(ss) && (ss->pending_priority <= ss->mfrr)) {
 203         return;
 204     }
 205
 206     trace_xics_icp_check_ipi(server, ss->mfrr);
 207
 208     if (XISR(ss)) {
 209         ics_reject(icp->ics, XISR(ss));
 210     }
 211
 212     ss->xirr = (ss->xirr & ~XISR_MASK) | XICS_IPI;
 213     ss->pending_priority = ss->mfrr;
 214     qemu_irq_raise(ss->output);
 215 }
 216
 217 static void icp_resend(XICSState *icp, int server)
 218 {
 219     ICPState *ss = icp->ss + server;
 220
 221     if (ss->mfrr < CPPR(ss)) {
 222         icp_check_ipi(icp, server);
 223     }
 224     ics_resend(icp->ics);
 225 }
 226
 227 static void icp_set_cppr(XICSState *icp, int server, uint8_t cppr)
 228 {
 229     ICPState *ss = icp->ss + server;
 230     uint8_t old_cppr;
 231     uint32_t old_xisr;
 232
 233     old_cppr = CPPR(ss);
 234     ss->xirr = (ss->xirr & ~CPPR_MASK) | (cppr << 24);
 235
 236     if (cppr < old_cppr) {
 237         if (XISR(ss) && (cppr <= ss->pending_priority)) {
 238             old_xisr = XISR(ss);
 239             ss->xirr &= ~XISR_MASK; /* Clear XISR */
 240             ss->pending_priority = 0xff;
 241             qemu_irq_lower(ss->output);
 242             ics_reject(icp->ics, old_xisr);
 243         }
 244     } else {
 245         if (!XISR(ss)) {
 246             icp_resend(icp, server);
 247         }
 248     }
 249 }
 250
 251 static void icp_set_mfrr(XICSState *icp, int server, uint8_t mfrr)
 252 {
 253     ICPState *ss = icp->ss + server;
 254
 255     ss->mfrr = mfrr;
 256     if (mfrr < CPPR(ss)) {
 257         icp_check_ipi(icp, server);
 258     }
 259 }
 260
 261 static uint32_t icp_accept(ICPState *ss)
 262 {
 263     uint32_t xirr = ss->xirr;
 264
 265     qemu_irq_lower(ss->output);
 266     ss->xirr = ss->pending_priority << 24;
 267     ss->pending_priority = 0xff;
 268
 269     trace_xics_icp_accept(xirr, ss->xirr);
 270
 271     return xirr;
 272 }
 273
 274 static void icp_eoi(XICSState *icp, int server, uint32_t xirr)
 275 {
 276     ICPState *ss = icp->ss + server;
 277
 278     /* Send EOI -> ICS */
 279     ss->xirr = (ss->xirr & ~CPPR_MASK) | (xirr & CPPR_MASK);
 280     trace_xics_icp_eoi(server, xirr, ss->xirr);
 281     ics_eoi(icp->ics, xirr & XISR_MASK);
 282     if (!XISR(ss)) {
 283         icp_resend(icp, server);
 284     }
 285 }
 286
 287 static void icp_irq(XICSState *icp, int server, int nr, uint8_t priority)
 288 {
 289     ICPState *ss = icp->ss + server;
 290
 291     trace_xics_icp_irq(server, nr, priority);
 292
 293     if ((priority >= CPPR(ss))
 294         || (XISR(ss) && (ss->pending_priority <= priority))) {
 295         ics_reject(icp->ics, nr);
 296     } else {
 297         if (XISR(ss)) {
 298             ics_reject(icp->ics, XISR(ss));
 299         }
 300         ss->xirr = (ss->xirr & ~XISR_MASK) | (nr & XISR_MASK);
 301         ss->pending_priority = priority;
 302         trace_xics_icp_raise(ss->xirr, ss->pending_priority);
 303         qemu_irq_raise(ss->output);
 304     }
 305 }
 306
 307 static void icp_dispatch_pre_save(void *opaque)
 308 {
 309     ICPState *ss = opaque;
 310     ICPStateClass *info = ICP_GET_CLASS(ss);
 311
 312     if (info->pre_save) {
 313         info->pre_save(ss);
 314     }
 315 }
 316
 317 static int icp_dispatch_post_load(void *opaque, int version_id)
 318 {
 319     ICPState *ss = opaque;
 320     ICPStateClass *info = ICP_GET_CLASS(ss);
 321
 322     if (info->post_load) {
 323         return info->post_load(ss, version_id);
 324     }
 325
 326     return 0;
 327 }
 328
 329 static const VMStateDescription vmstate_icp_server = {
 330     .name = "icp/server",
 331     .version_id = 1,
 332     .minimum_version_id = 1,
 333     .minimum_version_id_old = 1,
 334     .pre_save = icp_dispatch_pre_save,
 335     .post_load = icp_dispatch_post_load,
 336     .fields      = (VMStateField []) {
 337         /* Sanity check */
 338         VMSTATE_UINT32(xirr, ICPState),
 339         VMSTATE_UINT8(pending_priority, ICPState),
 340         VMSTATE_UINT8(mfrr, ICPState),
 341         VMSTATE_END_OF_LIST()
 342     },
 343 };
 344
 345 static void icp_reset(DeviceState *dev)
 346 {
 347     ICPState *icp = ICP(dev);
 348
 349     icp->xirr = 0;
 350     icp->pending_priority = 0xff;
 351     icp->mfrr = 0xff;
 352
 353     /* Make all outputs are deasserted */
 354     qemu_set_irq(icp->output, 0);
 355 }
 356
 357 static void icp_class_init(ObjectClass *klass, void *data)
 358 {
 359     DeviceClass *dc = DEVICE_CLASS(klass);
 360
 361     dc->reset = icp_reset;
 362     dc->vmsd = &vmstate_icp_server;
 363 }
 364
 365 static const TypeInfo icp_info = {
 366     .name = TYPE_ICP,
 367     .parent = TYPE_DEVICE,
 368     .instance_size = sizeof(ICPState),
 369     .class_init = icp_class_init,
 370     .class_size = sizeof(ICPStateClass),
 371 };
 372
 373 /*
 374  * ICS: Source layer
 375  */
 376 static int ics_valid_irq(ICSState *ics, uint32_t nr)
 377 {
 378     return (nr >= ics->offset)
 379         && (nr < (ics->offset + ics->nr_irqs));
 380 }
 381
 382 static void resend_msi(ICSState *ics, int srcno)
 383 {
 384     ICSIRQState *irq = ics->irqs + srcno;
 385
 386     /* FIXME: filter by server#? */
 387     if (irq->status & XICS_STATUS_REJECTED) {
 388         irq->status &= ~XICS_STATUS_REJECTED;
 389         if (irq->priority != 0xff) {
 390             icp_irq(ics->icp, irq->server, srcno + ics->offset,
 391                     irq->priority);
 392         }
 393     }
 394 }
 395
 396 static void resend_lsi(ICSState *ics, int srcno)
 397 {
 398     ICSIRQState *irq = ics->irqs + srcno;
 399
 400     if ((irq->priority != 0xff)
 401         && (irq->status & XICS_STATUS_ASSERTED)
 402         && !(irq->status & XICS_STATUS_SENT)) {
 403         irq->status |= XICS_STATUS_SENT;
 404         icp_irq(ics->icp, irq->server, srcno + ics->offset, irq->priority);
 405     }
 406 }
 407
 408 static void set_irq_msi(ICSState *ics, int srcno, int val)
 409 {
 410     ICSIRQState *irq = ics->irqs + srcno;
 411
 412     trace_xics_set_irq_msi(srcno, srcno + ics->offset);
 413
 414     if (val) {
 415         if (irq->priority == 0xff) {
 416             irq->status |= XICS_STATUS_MASKED_PENDING;
 417             trace_xics_masked_pending();
 418         } else  {
 419             icp_irq(ics->icp, irq->server, srcno + ics->offset, irq->priority);
 420         }
 421     }
 422 }
 423
 424 static void set_irq_lsi(ICSState *ics, int srcno, int val)
 425 {
 426     ICSIRQState *irq = ics->irqs + srcno;
 427
 428     trace_xics_set_irq_lsi(srcno, srcno + ics->offset);
 429     if (val) {
 430         irq->status |= XICS_STATUS_ASSERTED;
 431     } else {
 432         irq->status &= ~XICS_STATUS_ASSERTED;
 433     }
 434     resend_lsi(ics, srcno);
 435 }
 436
 437 static void ics_set_irq(void *opaque, int srcno, int val)
 438 {
 439     ICSState *ics = (ICSState *)opaque;
 440
 441     if (ics->islsi[srcno]) {
 442         set_irq_lsi(ics, srcno, val);
 443     } else {
 444         set_irq_msi(ics, srcno, val);
 445     }
 446 }
 447
 448 static void write_xive_msi(ICSState *ics, int srcno)
 449 {
 450     ICSIRQState *irq = ics->irqs + srcno;
 451
 452     if (!(irq->status & XICS_STATUS_MASKED_PENDING)
 453         || (irq->priority == 0xff)) {
 454         return;
 455     }
 456
 457     irq->status &= ~XICS_STATUS_MASKED_PENDING;
 458     icp_irq(ics->icp, irq->server, srcno + ics->offset, irq->priority);
 459 }
 460
 461 static void write_xive_lsi(ICSState *ics, int srcno)
 462 {
 463     resend_lsi(ics, srcno);
 464 }
 465
 466 static void ics_write_xive(ICSState *ics, int nr, int server,
 467                            uint8_t priority, uint8_t saved_priority)
 468 {
 469     int srcno = nr - ics->offset;
 470     ICSIRQState *irq = ics->irqs + srcno;
 471
 472     irq->server = server;
 473     irq->priority = priority;
 474     irq->saved_priority = saved_priority;
 475
 476     trace_xics_ics_write_xive(nr, srcno, server, priority);
 477
 478     if (ics->islsi[srcno]) {
 479         write_xive_lsi(ics, srcno);
 480     } else {
 481         write_xive_msi(ics, srcno);
 482     }
 483 }
 484
 485 static void ics_reject(ICSState *ics, int nr)
 486 {
 487     ICSIRQState *irq = ics->irqs + nr - ics->offset;
 488
 489     trace_xics_ics_reject(nr, nr - ics->offset);
 490     irq->status |= XICS_STATUS_REJECTED; /* Irrelevant but harmless for LSI */
 491     irq->status &= ~XICS_STATUS_SENT; /* Irrelevant but harmless for MSI */
 492 }
 493
 494 static void ics_resend(ICSState *ics)
 495 {
 496     int i;
 497
 498     for (i = 0; i < ics->nr_irqs; i++) {
 499         /* FIXME: filter by server#? */
 500         if (ics->islsi[i]) {
 501             resend_lsi(ics, i);
 502         } else {
 503             resend_msi(ics, i);
 504         }
 505     }
 506 }
 507
 508 static void ics_eoi(ICSState *ics, int nr)
 509 {
 510     int srcno = nr - ics->offset;
 511     ICSIRQState *irq = ics->irqs + srcno;
 512
 513     trace_xics_ics_eoi(nr);
 514
 515     if (ics->islsi[srcno]) {
 516         irq->status &= ~XICS_STATUS_SENT;
 517     }
 518 }
 519
 520 static void ics_reset(DeviceState *dev)
 521 {
 522     ICSState *ics = ICS(dev);
 523     int i;
 524
 525     memset(ics->irqs, 0, sizeof(ICSIRQState) * ics->nr_irqs);
 526     for (i = 0; i < ics->nr_irqs; i++) {
 527         ics->irqs[i].priority = 0xff;
 528         ics->irqs[i].saved_priority = 0xff;
 529     }
 530 }
 531
 532 static int ics_post_load(ICSState *ics, int version_id)
 533 {
 534     int i;
 535
 536     for (i = 0; i < ics->icp->nr_servers; i++) {
 537         icp_resend(ics->icp, i);
 538     }
 539
 540     return 0;
 541 }
 542
 543 static void ics_dispatch_pre_save(void *opaque)
 544 {
 545     ICSState *ics = opaque;
 546     ICSStateClass *info = ICS_GET_CLASS(ics);
 547
 548     if (info->pre_save) {
 549         info->pre_save(ics);
 550     }
 551 }
 552
 553 static int ics_dispatch_post_load(void *opaque, int version_id)
 554 {
 555     ICSState *ics = opaque;
 556     ICSStateClass *info = ICS_GET_CLASS(ics);
 557
 558     if (info->post_load) {
 559         return info->post_load(ics, version_id);
 560     }
 561
 562     return 0;
 563 }
 564
 565 static const VMStateDescription vmstate_ics_irq = {
 566     .name = "ics/irq",
 567     .version_id = 1,
 568     .minimum_version_id = 1,
 569     .minimum_version_id_old = 1,
 570     .fields      = (VMStateField []) {
 571         VMSTATE_UINT32(server, ICSIRQState),
 572         VMSTATE_UINT8(priority, ICSIRQState),
 573         VMSTATE_UINT8(saved_priority, ICSIRQState),
 574         VMSTATE_UINT8(status, ICSIRQState),
 575         VMSTATE_END_OF_LIST()
 576     },
 577 };
 578
 579 static const VMStateDescription vmstate_ics = {
 580     .name = "ics",
 581     .version_id = 1,
 582     .minimum_version_id = 1,
 583     .minimum_version_id_old = 1,
 584     .pre_save = ics_dispatch_pre_save,
 585     .post_load = ics_dispatch_post_load,
 586     .fields      = (VMStateField []) {
 587         /* Sanity check */
 588         VMSTATE_UINT32_EQUAL(nr_irqs, ICSState),
 589
 590         VMSTATE_STRUCT_VARRAY_POINTER_UINT32(irqs, ICSState, nr_irqs,
 591                                              vmstate_ics_irq, ICSIRQState),
 592         VMSTATE_END_OF_LIST()
 593     },
 594 };
 595
 596 static void ics_initfn(Object *obj)
 597 {
 598     ICSState *ics = ICS(obj);
 599
 600     ics->offset = XICS_IRQ_BASE;
 601 }
 602
 603 static void ics_realize(DeviceState *dev, Error **errp)
 604 {
 605     ICSState *ics = ICS(dev);
 606
 607     if (!ics->nr_irqs) {
 608         error_setg(errp, "Number of interrupts needs to be greater 0");
 609         return;
 610     }
 611     ics->irqs = g_malloc0(ics->nr_irqs * sizeof(ICSIRQState));
 612     ics->islsi = g_malloc0(ics->nr_irqs * sizeof(bool));
 613     ics->qirqs = qemu_allocate_irqs(ics_set_irq, ics, ics->nr_irqs);
 614 }
 615
 616 static void ics_class_init(ObjectClass *klass, void *data)
 617 {
 618     DeviceClass *dc = DEVICE_CLASS(klass);
 619     ICSStateClass *isc = ICS_CLASS(klass);
 620
 621     dc->realize = ics_realize;
 622     dc->vmsd = &vmstate_ics;
 623     dc->reset = ics_reset;
 624     isc->post_load = ics_post_load;
 625 }
 626
 627 static const TypeInfo ics_info = {
 628     .name = TYPE_ICS,
 629     .parent = TYPE_DEVICE,
 630     .instance_size = sizeof(ICSState),
 631     .class_init = ics_class_init,
 632     .class_size = sizeof(ICSStateClass),
 633     .instance_init = ics_initfn,
 634 };
 635
 636 /*
 637  * Exported functions
 638  */
 639
 640 qemu_irq xics_get_qirq(XICSState *icp, int irq)
 641 {
 642     if (!ics_valid_irq(icp->ics, irq)) {
 643         return NULL;
 644     }
 645
 646     return icp->ics->qirqs[irq - icp->ics->offset];
 647 }
 648
 649 void xics_set_irq_type(XICSState *icp, int irq, bool lsi)
 650 {
 651     assert(ics_valid_irq(icp->ics, irq));
 652
 653     icp->ics->islsi[irq - icp->ics->offset] = lsi;
 654 }
 655
 656 /*
 657  * Guest interfaces
 658  */
 659
 660 static target_ulong h_cppr(PowerPCCPU *cpu, sPAPREnvironment *spapr,
 661                            target_ulong opcode, target_ulong *args)
 662 {
 663     CPUState *cs = CPU(cpu);
 664     target_ulong cppr = args[0];
 665
 666     icp_set_cppr(spapr->icp, cs->cpu_index, cppr);
 667     return H_SUCCESS;
 668 }
 669
 670 static target_ulong h_ipi(PowerPCCPU *cpu, sPAPREnvironment *spapr,
 671                           target_ulong opcode, target_ulong *args)
 672 {
 673     target_ulong server = get_cpu_index_by_dt_id(args[0]);
 674     target_ulong mfrr = args[1];
 675
 676     if (server >= spapr->icp->nr_servers) {
 677         return H_PARAMETER;
 678     }
 679
 680     icp_set_mfrr(spapr->icp, server, mfrr);
 681     return H_SUCCESS;
 682 }
 683
 684 static target_ulong h_xirr(PowerPCCPU *cpu, sPAPREnvironment *spapr,
 685                            target_ulong opcode, target_ulong *args)
 686 {
 687     CPUState *cs = CPU(cpu);
 688     uint32_t xirr = icp_accept(spapr->icp->ss + cs->cpu_index);
 689
 690     args[0] = xirr;
 691     return H_SUCCESS;
 692 }
 693
 694 static target_ulong h_xirr_x(PowerPCCPU *cpu, sPAPREnvironment *spapr,
 695                              target_ulong opcode, target_ulong *args)
 696 {
 697     CPUState *cs = CPU(cpu);
 698     ICPState *ss = &spapr->icp->ss[cs->cpu_index];
 699     uint32_t xirr = icp_accept(ss);
 700
 701     args[0] = xirr;
 702     args[1] = cpu_get_real_ticks();
 703     return H_SUCCESS;
 704 }
 705
 706 static target_ulong h_eoi(PowerPCCPU *cpu, sPAPREnvironment *spapr,
 707                           target_ulong opcode, target_ulong *args)
 708 {
 709     CPUState *cs = CPU(cpu);
 710     target_ulong xirr = args[0];
 711
 712     icp_eoi(spapr->icp, cs->cpu_index, xirr);
 713     return H_SUCCESS;
 714 }
 715
 716 static target_ulong h_ipoll(PowerPCCPU *cpu, sPAPREnvironment *spapr,
 717                             target_ulong opcode, target_ulong *args)
 718 {
 719     CPUState *cs = CPU(cpu);
 720     ICPState *ss = &spapr->icp->ss[cs->cpu_index];
 721
 722     args[0] = ss->xirr;
 723     args[1] = ss->mfrr;
 724
 725     return H_SUCCESS;
 726 }
 727
 728 static void rtas_set_xive(PowerPCCPU *cpu, sPAPREnvironment *spapr,
 729                           uint32_t token,
 730                           uint32_t nargs, target_ulong args,
 731                           uint32_t nret, target_ulong rets)
 732 {
 733     ICSState *ics = spapr->icp->ics;
 734     uint32_t nr, server, priority;
 735
 736     if ((nargs != 3) || (nret != 1)) {
 737         rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
 738         return;
 739     }
 740
 741     nr = rtas_ld(args, 0);
 742     server = get_cpu_index_by_dt_id(rtas_ld(args, 1));
 743     priority = rtas_ld(args, 2);
 744
 745     if (!ics_valid_irq(ics, nr) || (server >= ics->icp->nr_servers)
 746         || (priority > 0xff)) {
 747         rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
 748         return;
 749     }
 750
 751     ics_write_xive(ics, nr, server, priority, priority);
 752
 753     rtas_st(rets, 0, RTAS_OUT_SUCCESS);
 754 }
 755
 756 static void rtas_get_xive(PowerPCCPU *cpu, sPAPREnvironment *spapr,
 757                           uint32_t token,
 758                           uint32_t nargs, target_ulong args,
 759                           uint32_t nret, target_ulong rets)
 760 {
 761     ICSState *ics = spapr->icp->ics;
 762     uint32_t nr;
 763
 764     if ((nargs != 1) || (nret != 3)) {
 765         rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
 766         return;
 767     }
 768
 769     nr = rtas_ld(args, 0);
 770
 771     if (!ics_valid_irq(ics, nr)) {
 772         rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
 773         return;
 774     }
 775
 776     rtas_st(rets, 0, RTAS_OUT_SUCCESS);
 777     rtas_st(rets, 1, ics->irqs[nr - ics->offset].server);
 778     rtas_st(rets, 2, ics->irqs[nr - ics->offset].priority);
 779 }
 780
 781 static void rtas_int_off(PowerPCCPU *cpu, sPAPREnvironment *spapr,
 782                          uint32_t token,
 783                          uint32_t nargs, target_ulong args,
 784                          uint32_t nret, target_ulong rets)
 785 {
 786     ICSState *ics = spapr->icp->ics;
 787     uint32_t nr;
 788
 789     if ((nargs != 1) || (nret != 1)) {
 790         rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
 791         return;
 792     }
 793
 794     nr = rtas_ld(args, 0);
 795
 796     if (!ics_valid_irq(ics, nr)) {
 797         rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
 798         return;
 799     }
 800
 801     ics_write_xive(ics, nr, ics->irqs[nr - ics->offset].server, 0xff,
 802                    ics->irqs[nr - ics->offset].priority);
 803
 804     rtas_st(rets, 0, RTAS_OUT_SUCCESS);
 805 }
 806
 807 static void rtas_int_on(PowerPCCPU *cpu, sPAPREnvironment *spapr,
 808                         uint32_t token,
 809                         uint32_t nargs, target_ulong args,
 810                         uint32_t nret, target_ulong rets)
 811 {
 812     ICSState *ics = spapr->icp->ics;
 813     uint32_t nr;
 814
 815     if ((nargs != 1) || (nret != 1)) {
 816         rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
 817         return;
 818     }
 819
 820     nr = rtas_ld(args, 0);
 821
 822     if (!ics_valid_irq(ics, nr)) {
 823         rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
 824         return;
 825     }
 826
 827     ics_write_xive(ics, nr, ics->irqs[nr - ics->offset].server,
 828                    ics->irqs[nr - ics->offset].saved_priority,
 829                    ics->irqs[nr - ics->offset].saved_priority);
 830
 831     rtas_st(rets, 0, RTAS_OUT_SUCCESS);
 832 }
 833
 834 /*
 835  * XICS
 836  */
 837
 838 static void xics_set_nr_irqs(XICSState *icp, uint32_t nr_irqs, Error **errp)
 839 {
 840     icp->nr_irqs = icp->ics->nr_irqs = nr_irqs;
 841 }
 842
 843 static void xics_set_nr_servers(XICSState *icp, uint32_t nr_servers,
 844                                 Error **errp)
 845 {
 846     int i;
 847
 848     icp->nr_servers = nr_servers;
 849
 850     icp->ss = g_malloc0(icp->nr_servers*sizeof(ICPState));
 851     for (i = 0; i < icp->nr_servers; i++) {
 852         char buffer[32];
 853         object_initialize(&icp->ss[i], sizeof(icp->ss[i]), TYPE_ICP);
 854         snprintf(buffer, sizeof(buffer), "icp[%d]", i);
 855         object_property_add_child(OBJECT(icp), buffer, OBJECT(&icp->ss[i]),
 856                                   errp);
 857     }
 858 }
 859
 860 static void xics_realize(DeviceState *dev, Error **errp)
 861 {
 862     XICSState *icp = XICS(dev);
 863     Error *error = NULL;
 864     int i;
 865
 866     if (!icp->nr_servers) {
 867         error_setg(errp, "Number of servers needs to be greater 0");
 868         return;
 869     }
 870
 871     /* Registration of global state belongs into realize */
 872     spapr_rtas_register("ibm,set-xive", rtas_set_xive);
 873     spapr_rtas_register("ibm,get-xive", rtas_get_xive);
 874     spapr_rtas_register("ibm,int-off", rtas_int_off);
 875     spapr_rtas_register("ibm,int-on", rtas_int_on);
 876
 877     spapr_register_hypercall(H_CPPR, h_cppr);
 878     spapr_register_hypercall(H_IPI, h_ipi);
 879     spapr_register_hypercall(H_XIRR, h_xirr);
 880     spapr_register_hypercall(H_XIRR_X, h_xirr_x);
 881     spapr_register_hypercall(H_EOI, h_eoi);
 882     spapr_register_hypercall(H_IPOLL, h_ipoll);
 883
 884     object_property_set_bool(OBJECT(icp->ics), true, "realized", &error);
 885     if (error) {
 886         error_propagate(errp, error);
 887         return;
 888     }
 889
 890     for (i = 0; i < icp->nr_servers; i++) {
 891         object_property_set_bool(OBJECT(&icp->ss[i]), true, "realized", &error);
 892         if (error) {
 893             error_propagate(errp, error);
 894             return;
 895         }
 896     }
 897 }
 898
 899 static void xics_initfn(Object *obj)
 900 {
 901     XICSState *xics = XICS(obj);
 902
 903     xics->ics = ICS(object_new(TYPE_ICS));
 904     object_property_add_child(obj, "ics", OBJECT(xics->ics), NULL);
 905     xics->ics->icp = xics;
 906 }
 907
 908 static void xics_class_init(ObjectClass *oc, void *data)
 909 {
 910     DeviceClass *dc = DEVICE_CLASS(oc);
 911     XICSStateClass *xsc = XICS_CLASS(oc);
 912
 913     dc->realize = xics_realize;
 914     xsc->set_nr_irqs = xics_set_nr_irqs;
 915     xsc->set_nr_servers = xics_set_nr_servers;
 916 }
 917
 918 static const TypeInfo xics_info = {
 919     .name          = TYPE_XICS,
 920     .parent        = TYPE_XICS_COMMON,
 921     .instance_size = sizeof(XICSState),
 922     .class_size = sizeof(XICSStateClass),
 923     .class_init    = xics_class_init,
 924     .instance_init = xics_initfn,
 925 };
 926
 927 static void xics_register_types(void)
 928 {
 929     type_register_static(&xics_common_info);
 930     type_register_static(&xics_info);
 931     type_register_static(&ics_info);
 932     type_register_static(&icp_info);
 933 }
 934
 935 type_init(xics_register_types)