hw/opencores_eth.c

   1 /*
   2  * OpenCores Ethernet MAC 10/100 + subset of
   3  * National Semiconductors DP83848C 10/100 PHY
   4  *
   5  * http://opencores.org/svnget,ethmac?file=%2Ftrunk%2F%2Fdoc%2Feth_speci.pdf
   6  * http://cache.national.com/ds/DP/DP83848C.pdf
   7  *
   8  * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
   9  * All rights reserved.
  10  *
  11  * Redistribution and use in source and binary forms, with or without
  12  * modification, are permitted provided that the following conditions are met:
  13  *     * Redistributions of source code must retain the above copyright
  14  *       notice, this list of conditions and the following disclaimer.
  15  *     * Redistributions in binary form must reproduce the above copyright
  16  *       notice, this list of conditions and the following disclaimer in the
  17  *       documentation and/or other materials provided with the distribution.
  18  *     * Neither the name of the Open Source and Linux Lab nor the
  19  *       names of its contributors may be used to endorse or promote products
  20  *       derived from this software without specific prior written permission.
  21  *
  22  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  23  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  26  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  27  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  28  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  29  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  31  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include "hw.h"
  35 #include "sysbus.h"
  36 #include "net.h"
  37 #include "sysemu.h"
  38 #include "trace.h"
  39
  40 /* RECSMALL is not used because it breaks tap networking in linux:
  41  * incoming ARP responses are too short
  42  */
  43 #undef USE_RECSMALL
  44
  45 #define GET_FIELD(v, field) (((v) & (field)) >> (field ## _LBN))
  46 #define GET_REGBIT(s, reg, field) ((s)->regs[reg] & (reg ## _ ## field))
  47 #define GET_REGFIELD(s, reg, field) \
  48     GET_FIELD((s)->regs[reg], reg ## _ ## field)
  49
  50 #define SET_FIELD(v, field, data) \
  51     ((v) = (((v) & ~(field)) | (((data) << (field ## _LBN)) & (field))))
  52 #define SET_REGFIELD(s, reg, field, data) \
  53     SET_FIELD((s)->regs[reg], reg ## _ ## field, data)
  54
  55 /* PHY MII registers */
  56 enum {
  57     MII_BMCR,
  58     MII_BMSR,
  59     MII_PHYIDR1,
  60     MII_PHYIDR2,
  61     MII_ANAR,
  62     MII_ANLPAR,
  63     MII_REG_MAX = 16,
  64 };
  65
  66 typedef struct Mii {
  67     uint16_t regs[MII_REG_MAX];
  68     bool link_ok;
  69 } Mii;
  70
  71 static void mii_set_link(Mii *s, bool link_ok)
  72 {
  73     if (link_ok) {
  74         s->regs[MII_BMSR] |= 0x4;
  75         s->regs[MII_ANLPAR] |= 0x01e1;
  76     } else {
  77         s->regs[MII_BMSR] &= ~0x4;
  78         s->regs[MII_ANLPAR] &= 0x01ff;
  79     }
  80     s->link_ok = link_ok;
  81 }
  82
  83 static void mii_reset(Mii *s)
  84 {
  85     memset(s->regs, 0, sizeof(s->regs));
  86     s->regs[MII_BMCR] = 0x1000;
  87     s->regs[MII_BMSR] = 0x7848; /* no ext regs */
  88     s->regs[MII_PHYIDR1] = 0x2000;
  89     s->regs[MII_PHYIDR2] = 0x5c90;
  90     s->regs[MII_ANAR] = 0x01e1;
  91     mii_set_link(s, s->link_ok);
  92 }
  93
  94 static void mii_ro(Mii *s, uint16_t v)
  95 {
  96 }
  97
  98 static void mii_write_bmcr(Mii *s, uint16_t v)
  99 {
 100     if (v & 0x8000) {
 101         mii_reset(s);
 102     } else {
 103         s->regs[MII_BMCR] = v;
 104     }
 105 }
 106
 107 static void mii_write_host(Mii *s, unsigned idx, uint16_t v)
 108 {
 109     static void (*reg_write[MII_REG_MAX])(Mii *s, uint16_t v) = {
 110         [MII_BMCR] = mii_write_bmcr,
 111         [MII_BMSR] = mii_ro,
 112         [MII_PHYIDR1] = mii_ro,
 113         [MII_PHYIDR2] = mii_ro,
 114     };
 115
 116     if (idx < MII_REG_MAX) {
 117         trace_open_eth_mii_write(idx, v);
 118         if (reg_write[idx]) {
 119             reg_write[idx](s, v);
 120         } else {
 121             s->regs[idx] = v;
 122         }
 123     }
 124 }
 125
 126 static uint16_t mii_read_host(Mii *s, unsigned idx)
 127 {
 128     trace_open_eth_mii_read(idx, s->regs[idx]);
 129     return s->regs[idx];
 130 }
 131
 132 /* OpenCores Ethernet registers */
 133 enum {
 134     MODER,
 135     INT_SOURCE,
 136     INT_MASK,
 137     IPGT,
 138     IPGR1,
 139     IPGR2,
 140     PACKETLEN,
 141     COLLCONF,
 142     TX_BD_NUM,
 143     CTRLMODER,
 144     MIIMODER,
 145     MIICOMMAND,
 146     MIIADDRESS,
 147     MIITX_DATA,
 148     MIIRX_DATA,
 149     MIISTATUS,
 150     MAC_ADDR0,
 151     MAC_ADDR1,
 152     HASH0,
 153     HASH1,
 154     TXCTRL,
 155     REG_MAX,
 156 };
 157
 158 enum {
 159     MODER_RECSMALL = 0x10000,
 160     MODER_PAD = 0x8000,
 161     MODER_HUGEN = 0x4000,
 162     MODER_RST = 0x800,
 163     MODER_LOOPBCK = 0x80,
 164     MODER_PRO = 0x20,
 165     MODER_IAM = 0x10,
 166     MODER_BRO = 0x8,
 167     MODER_TXEN = 0x2,
 168     MODER_RXEN = 0x1,
 169 };
 170
 171 enum {
 172     INT_SOURCE_RXB = 0x4,
 173     INT_SOURCE_TXB = 0x1,
 174 };
 175
 176 enum {
 177     PACKETLEN_MINFL = 0xffff0000,
 178     PACKETLEN_MINFL_LBN = 16,
 179     PACKETLEN_MAXFL = 0xffff,
 180     PACKETLEN_MAXFL_LBN = 0,
 181 };
 182
 183 enum {
 184     MIICOMMAND_WCTRLDATA = 0x4,
 185     MIICOMMAND_RSTAT = 0x2,
 186     MIICOMMAND_SCANSTAT = 0x1,
 187 };
 188
 189 enum {
 190     MIIADDRESS_RGAD = 0x1f00,
 191     MIIADDRESS_RGAD_LBN = 8,
 192     MIIADDRESS_FIAD = 0x1f,
 193     MIIADDRESS_FIAD_LBN = 0,
 194 };
 195
 196 enum {
 197     MIITX_DATA_CTRLDATA = 0xffff,
 198     MIITX_DATA_CTRLDATA_LBN = 0,
 199 };
 200
 201 enum {
 202     MIIRX_DATA_PRSD = 0xffff,
 203     MIIRX_DATA_PRSD_LBN = 0,
 204 };
 205
 206 enum {
 207     MIISTATUS_LINKFAIL = 0x1,
 208     MIISTATUS_LINKFAIL_LBN = 0,
 209 };
 210
 211 enum {
 212     MAC_ADDR0_BYTE2 = 0xff000000,
 213     MAC_ADDR0_BYTE2_LBN = 24,
 214     MAC_ADDR0_BYTE3 = 0xff0000,
 215     MAC_ADDR0_BYTE3_LBN = 16,
 216     MAC_ADDR0_BYTE4 = 0xff00,
 217     MAC_ADDR0_BYTE4_LBN = 8,
 218     MAC_ADDR0_BYTE5 = 0xff,
 219     MAC_ADDR0_BYTE5_LBN = 0,
 220 };
 221
 222 enum {
 223     MAC_ADDR1_BYTE0 = 0xff00,
 224     MAC_ADDR1_BYTE0_LBN = 8,
 225     MAC_ADDR1_BYTE1 = 0xff,
 226     MAC_ADDR1_BYTE1_LBN = 0,
 227 };
 228
 229 enum {
 230     TXD_LEN = 0xffff0000,
 231     TXD_LEN_LBN = 16,
 232     TXD_RD = 0x8000,
 233     TXD_IRQ = 0x4000,
 234     TXD_WR = 0x2000,
 235     TXD_PAD = 0x1000,
 236     TXD_CRC = 0x800,
 237     TXD_UR = 0x100,
 238     TXD_RTRY = 0xf0,
 239     TXD_RTRY_LBN = 4,
 240     TXD_RL = 0x8,
 241     TXD_LC = 0x4,
 242     TXD_DF = 0x2,
 243     TXD_CS = 0x1,
 244 };
 245
 246 enum {
 247     RXD_LEN = 0xffff0000,
 248     RXD_LEN_LBN = 16,
 249     RXD_E = 0x8000,
 250     RXD_IRQ = 0x4000,
 251     RXD_WRAP = 0x2000,
 252     RXD_CF = 0x100,
 253     RXD_M = 0x80,
 254     RXD_OR = 0x40,
 255     RXD_IS = 0x20,
 256     RXD_DN = 0x10,
 257     RXD_TL = 0x8,
 258     RXD_SF = 0x4,
 259     RXD_CRC = 0x2,
 260     RXD_LC = 0x1,
 261 };
 262
 263 typedef struct desc {
 264     uint32_t len_flags;
 265     uint32_t buf_ptr;
 266 } desc;
 267
 268 #define DEFAULT_PHY 1
 269
 270 typedef struct OpenEthState {
 271     SysBusDevice dev;
 272     NICState *nic;
 273     NICConf conf;
 274     MemoryRegion reg_io;
 275     MemoryRegion desc_io;
 276     qemu_irq irq;
 277
 278     Mii mii;
 279     uint32_t regs[REG_MAX];
 280     unsigned tx_desc;
 281     unsigned rx_desc;
 282     desc desc[128];
 283 } OpenEthState;
 284
 285 static desc *rx_desc(OpenEthState *s)
 286 {
 287     return s->desc + s->rx_desc;
 288 }
 289
 290 static desc *tx_desc(OpenEthState *s)
 291 {
 292     return s->desc + s->tx_desc;
 293 }
 294
 295 static void open_eth_update_irq(OpenEthState *s,
 296         uint32_t old, uint32_t new)
 297 {
 298     if (!old != !new) {
 299         trace_open_eth_update_irq(new);
 300         qemu_set_irq(s->irq, new);
 301     }
 302 }
 303
 304 static void open_eth_int_source_write(OpenEthState *s,
 305         uint32_t val)
 306 {
 307     uint32_t old_val = s->regs[INT_SOURCE];
 308
 309     s->regs[INT_SOURCE] = val;
 310     open_eth_update_irq(s, old_val & s->regs[INT_MASK],
 311             s->regs[INT_SOURCE] & s->regs[INT_MASK]);
 312 }
 313
 314 static void open_eth_set_link_status(VLANClientState *nc)
 315 {
 316     OpenEthState *s = DO_UPCAST(NICState, nc, nc)->opaque;
 317
 318     if (GET_REGBIT(s, MIICOMMAND, SCANSTAT)) {
 319         SET_REGFIELD(s, MIISTATUS, LINKFAIL, nc->link_down);
 320     }
 321     mii_set_link(&s->mii, !nc->link_down);
 322 }
 323
 324 static void open_eth_reset(void *opaque)
 325 {
 326     OpenEthState *s = opaque;
 327
 328     memset(s->regs, 0, sizeof(s->regs));
 329     s->regs[MODER] = 0xa000;
 330     s->regs[IPGT] = 0x12;
 331     s->regs[IPGR1] = 0xc;
 332     s->regs[IPGR2] = 0x12;
 333     s->regs[PACKETLEN] = 0x400600;
 334     s->regs[COLLCONF] = 0xf003f;
 335     s->regs[TX_BD_NUM] = 0x40;
 336     s->regs[MIIMODER] = 0x64;
 337
 338     s->tx_desc = 0;
 339     s->rx_desc = 0x40;
 340
 341     mii_reset(&s->mii);
 342     open_eth_set_link_status(&s->nic->nc);
 343 }
 344
 345 static int open_eth_can_receive(VLANClientState *nc)
 346 {
 347     OpenEthState *s = DO_UPCAST(NICState, nc, nc)->opaque;
 348
 349     return GET_REGBIT(s, MODER, RXEN) &&
 350         (s->regs[TX_BD_NUM] < 0x80) &&
 351         (rx_desc(s)->len_flags & RXD_E);
 352 }
 353
 354 #define POLYNOMIAL 0x04c11db6
 355
 356 /* From FreeBSD */
 357 /* XXX: optimize */
 358 static unsigned compute_mcast_idx(const uint8_t *ep)
 359 {
 360     uint32_t crc;
 361     int carry, i, j;
 362     uint8_t b;
 363
 364     crc = 0xffffffff;
 365     for (i = 0; i < 6; i++) {
 366         b = *ep++;
 367         for (j = 0; j < 8; j++) {
 368             carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
 369             crc <<= 1;
 370             b >>= 1;
 371             if (carry) {
 372                 crc = ((crc ^ POLYNOMIAL) | carry);
 373             }
 374         }
 375     }
 376     return crc >> 26;
 377 }
 378
 379 static ssize_t open_eth_receive(VLANClientState *nc,
 380         const uint8_t *buf, size_t size)
 381 {
 382     OpenEthState *s = DO_UPCAST(NICState, nc, nc)->opaque;
 383     size_t maxfl = GET_REGFIELD(s, PACKETLEN, MAXFL);
 384     size_t minfl = GET_REGFIELD(s, PACKETLEN, MINFL);
 385     bool miss = true;
 386
 387     trace_open_eth_receive((unsigned)size);
 388
 389     if (size >= 6) {
 390         static const uint8_t bcast_addr[] = {
 391             0xff, 0xff, 0xff, 0xff, 0xff, 0xff
 392         };
 393         if (memcmp(buf, bcast_addr, sizeof(bcast_addr)) == 0) {
 394             miss = GET_REGBIT(s, MODER, BRO);
 395         } else if ((buf[0] & 0x1) || GET_REGBIT(s, MODER, IAM)) {
 396             unsigned mcast_idx = compute_mcast_idx(buf);
 397             miss = !(s->regs[HASH0 + mcast_idx / 32] &
 398                     (1 << (mcast_idx % 32)));
 399             trace_open_eth_receive_mcast(
 400                     mcast_idx, s->regs[HASH0], s->regs[HASH1]);
 401         } else {
 402             miss = GET_REGFIELD(s, MAC_ADDR1, BYTE0) != buf[0] ||
 403                 GET_REGFIELD(s, MAC_ADDR1, BYTE1) != buf[1] ||
 404                 GET_REGFIELD(s, MAC_ADDR0, BYTE2) != buf[2] ||
 405                 GET_REGFIELD(s, MAC_ADDR0, BYTE3) != buf[3] ||
 406                 GET_REGFIELD(s, MAC_ADDR0, BYTE4) != buf[4] ||
 407                 GET_REGFIELD(s, MAC_ADDR0, BYTE5) != buf[5];
 408         }
 409     }
 410
 411     if (miss && !GET_REGBIT(s, MODER, PRO)) {
 412         trace_open_eth_receive_reject();
 413         return size;
 414     }
 415
 416 #ifdef USE_RECSMALL
 417     if (GET_REGBIT(s, MODER, RECSMALL) || size >= minfl) {
 418 #else
 419     {
 420 #endif
 421         desc *desc = rx_desc(s);
 422         size_t copy_size = GET_REGBIT(s, MODER, HUGEN) ? 65536 : maxfl;
 423
 424         desc->len_flags &= ~(RXD_CF | RXD_M | RXD_OR |
 425                 RXD_IS | RXD_DN | RXD_TL | RXD_SF | RXD_CRC | RXD_LC);
 426
 427         if (copy_size > size) {
 428             copy_size = size;
 429         }
 430         if (miss) {
 431             desc->len_flags |= RXD_M;
 432         }
 433         if (size > maxfl) {
 434             desc->len_flags |= RXD_TL;
 435         }
 436 #ifdef USE_RECSMALL
 437         if (size < minfl) {
 438             desc->len_flags |= RXD_SF;
 439         }
 440 #endif
 441
 442         cpu_physical_memory_write(desc->buf_ptr, buf, copy_size);
 443
 444         if (GET_REGBIT(s, MODER, PAD) && copy_size < minfl) {
 445             static const uint8_t zero[65536] = {0};
 446
 447             cpu_physical_memory_write(desc->buf_ptr + copy_size,
 448                     zero, minfl - copy_size);
 449             copy_size = minfl;
 450         }
 451
 452         SET_FIELD(desc->len_flags, RXD_LEN, copy_size);
 453
 454         if ((desc->len_flags & RXD_WRAP) || s->rx_desc == 0x7f) {
 455             s->rx_desc = s->regs[TX_BD_NUM];
 456         } else {
 457             ++s->rx_desc;
 458         }
 459         desc->len_flags &= ~RXD_E;
 460
 461         trace_open_eth_receive_desc(desc->buf_ptr, desc->len_flags);
 462
 463         if (desc->len_flags & RXD_IRQ) {
 464             open_eth_int_source_write(s,
 465                     s->regs[INT_SOURCE] | INT_SOURCE_RXB);
 466         }
 467     }
 468     return size;
 469 }
 470
 471 static void open_eth_cleanup(VLANClientState *nc)
 472 {
 473 }
 474
 475 static NetClientInfo net_open_eth_info = {
 476     .type = NET_CLIENT_TYPE_NIC,
 477     .size = sizeof(NICState),
 478     .can_receive = open_eth_can_receive,
 479     .receive = open_eth_receive,
 480     .cleanup = open_eth_cleanup,
 481     .link_status_changed = open_eth_set_link_status,
 482 };
 483
 484 static void open_eth_start_xmit(OpenEthState *s, desc *tx)
 485 {
 486     uint8_t buf[65536];
 487     unsigned len = GET_FIELD(tx->len_flags, TXD_LEN);
 488     unsigned tx_len = len;
 489
 490     if ((tx->len_flags & TXD_PAD) &&
 491             tx_len < GET_REGFIELD(s, PACKETLEN, MINFL)) {
 492         tx_len = GET_REGFIELD(s, PACKETLEN, MINFL);
 493     }
 494     if (!GET_REGBIT(s, MODER, HUGEN) &&
 495             tx_len > GET_REGFIELD(s, PACKETLEN, MAXFL)) {
 496         tx_len = GET_REGFIELD(s, PACKETLEN, MAXFL);
 497     }
 498
 499     trace_open_eth_start_xmit(tx->buf_ptr, len, tx_len);
 500
 501     if (len > tx_len) {
 502         len = tx_len;
 503     }
 504     cpu_physical_memory_read(tx->buf_ptr, buf, len);
 505     if (tx_len > len) {
 506         memset(buf + len, 0, tx_len - len);
 507     }
 508     qemu_send_packet(&s->nic->nc, buf, tx_len);
 509
 510     if (tx->len_flags & TXD_WR) {
 511         s->tx_desc = 0;
 512     } else {
 513         ++s->tx_desc;
 514         if (s->tx_desc >= s->regs[TX_BD_NUM]) {
 515             s->tx_desc = 0;
 516         }
 517     }
 518     tx->len_flags &= ~(TXD_RD | TXD_UR |
 519             TXD_RTRY | TXD_RL | TXD_LC | TXD_DF | TXD_CS);
 520     if (tx->len_flags & TXD_IRQ) {
 521         open_eth_int_source_write(s, s->regs[INT_SOURCE] | INT_SOURCE_TXB);
 522     }
 523
 524 }
 525
 526 static void open_eth_check_start_xmit(OpenEthState *s)
 527 {
 528     desc *tx = tx_desc(s);
 529     if (GET_REGBIT(s, MODER, TXEN) && s->regs[TX_BD_NUM] > 0 &&
 530             (tx->len_flags & TXD_RD) &&
 531             GET_FIELD(tx->len_flags, TXD_LEN) > 4) {
 532         open_eth_start_xmit(s, tx);
 533     }
 534 }
 535
 536 static uint64_t open_eth_reg_read(void *opaque,
 537         target_phys_addr_t addr, unsigned int size)
 538 {
 539     static uint32_t (*reg_read[REG_MAX])(OpenEthState *s) = {
 540     };
 541     OpenEthState *s = opaque;
 542     unsigned idx = addr / 4;
 543     uint64_t v = 0;
 544
 545     if (idx < REG_MAX) {
 546         if (reg_read[idx]) {
 547             v = reg_read[idx](s);
 548         } else {
 549             v = s->regs[idx];
 550         }
 551     }
 552     trace_open_eth_reg_read((uint32_t)addr, (uint32_t)v);
 553     return v;
 554 }
 555
 556 static void open_eth_ro(OpenEthState *s, uint32_t val)
 557 {
 558 }
 559
 560 static void open_eth_moder_host_write(OpenEthState *s, uint32_t val)
 561 {
 562     uint32_t set = val & ~s->regs[MODER];
 563
 564     if (set & MODER_RST) {
 565         open_eth_reset(s);
 566     }
 567
 568     s->regs[MODER] = val;
 569
 570     if (set & MODER_RXEN) {
 571         s->rx_desc = s->regs[TX_BD_NUM];
 572     }
 573     if (set & MODER_TXEN) {
 574         s->tx_desc = 0;
 575         open_eth_check_start_xmit(s);
 576     }
 577 }
 578
 579 static void open_eth_int_source_host_write(OpenEthState *s, uint32_t val)
 580 {
 581     uint32_t old = s->regs[INT_SOURCE];
 582
 583     s->regs[INT_SOURCE] &= ~val;
 584     open_eth_update_irq(s, old & s->regs[INT_MASK],
 585             s->regs[INT_SOURCE] & s->regs[INT_MASK]);
 586 }
 587
 588 static void open_eth_int_mask_host_write(OpenEthState *s, uint32_t val)
 589 {
 590     uint32_t old = s->regs[INT_MASK];
 591
 592     s->regs[INT_MASK] = val;
 593     open_eth_update_irq(s, s->regs[INT_SOURCE] & old,
 594             s->regs[INT_SOURCE] & s->regs[INT_MASK]);
 595 }
 596
 597 static void open_eth_mii_command_host_write(OpenEthState *s, uint32_t val)
 598 {
 599     unsigned fiad = GET_REGFIELD(s, MIIADDRESS, FIAD);
 600     unsigned rgad = GET_REGFIELD(s, MIIADDRESS, RGAD);
 601
 602     if (val & MIICOMMAND_WCTRLDATA) {
 603         if (fiad == DEFAULT_PHY) {
 604             mii_write_host(&s->mii, rgad,
 605                     GET_REGFIELD(s, MIITX_DATA, CTRLDATA));
 606         }
 607     }
 608     if (val & MIICOMMAND_RSTAT) {
 609         if (fiad == DEFAULT_PHY) {
 610             SET_REGFIELD(s, MIIRX_DATA, PRSD,
 611                     mii_read_host(&s->mii, rgad));
 612         } else {
 613             s->regs[MIIRX_DATA] = 0xffff;
 614         }
 615         SET_REGFIELD(s, MIISTATUS, LINKFAIL, s->nic->nc.link_down);
 616     }
 617 }
 618
 619 static void open_eth_mii_tx_host_write(OpenEthState *s, uint32_t val)
 620 {
 621     SET_REGFIELD(s, MIITX_DATA, CTRLDATA, val);
 622     if (GET_REGFIELD(s, MIIADDRESS, FIAD) == DEFAULT_PHY) {
 623         mii_write_host(&s->mii, GET_REGFIELD(s, MIIADDRESS, RGAD),
 624                 GET_REGFIELD(s, MIITX_DATA, CTRLDATA));
 625     }
 626 }
 627
 628 static void open_eth_reg_write(void *opaque,
 629         target_phys_addr_t addr, uint64_t val, unsigned int size)
 630 {
 631     static void (*reg_write[REG_MAX])(OpenEthState *s, uint32_t val) = {
 632         [MODER] = open_eth_moder_host_write,
 633         [INT_SOURCE] = open_eth_int_source_host_write,
 634         [INT_MASK] = open_eth_int_mask_host_write,
 635         [MIICOMMAND] = open_eth_mii_command_host_write,
 636         [MIITX_DATA] = open_eth_mii_tx_host_write,
 637         [MIISTATUS] = open_eth_ro,
 638     };
 639     OpenEthState *s = opaque;
 640     unsigned idx = addr / 4;
 641
 642     if (idx < REG_MAX) {
 643         trace_open_eth_reg_write((uint32_t)addr, (uint32_t)val);
 644         if (reg_write[idx]) {
 645             reg_write[idx](s, val);
 646         } else {
 647             s->regs[idx] = val;
 648         }
 649     }
 650 }
 651
 652 static uint64_t open_eth_desc_read(void *opaque,
 653         target_phys_addr_t addr, unsigned int size)
 654 {
 655     OpenEthState *s = opaque;
 656     uint64_t v = 0;
 657
 658     addr &= 0x3ff;
 659     memcpy(&v, (uint8_t *)s->desc + addr, size);
 660     trace_open_eth_desc_read((uint32_t)addr, (uint32_t)v);
 661     return v;
 662 }
 663
 664 static void open_eth_desc_write(void *opaque,
 665         target_phys_addr_t addr, uint64_t val, unsigned int size)
 666 {
 667     OpenEthState *s = opaque;
 668
 669     addr &= 0x3ff;
 670     trace_open_eth_desc_write((uint32_t)addr, (uint32_t)val);
 671     memcpy((uint8_t *)s->desc + addr, &val, size);
 672     open_eth_check_start_xmit(s);
 673 }
 674
 675
 676 static MemoryRegionOps open_eth_reg_ops = {
 677     .read = open_eth_reg_read,
 678     .write = open_eth_reg_write,
 679 };
 680
 681 static MemoryRegionOps open_eth_desc_ops = {
 682     .read = open_eth_desc_read,
 683     .write = open_eth_desc_write,
 684 };
 685
 686 static int sysbus_open_eth_init(SysBusDevice *dev)
 687 {
 688     OpenEthState *s = DO_UPCAST(OpenEthState, dev, dev);
 689
 690     memory_region_init_io(&s->reg_io, &open_eth_reg_ops, s,
 691             "open_eth.regs", 0x54);
 692     sysbus_init_mmio_region(dev, &s->reg_io);
 693
 694     memory_region_init_io(&s->desc_io, &open_eth_desc_ops, s,
 695             "open_eth.desc", 0x400);
 696     sysbus_init_mmio_region(dev, &s->desc_io);
 697
 698     sysbus_init_irq(dev, &s->irq);
 699
 700     s->nic = qemu_new_nic(&net_open_eth_info, &s->conf,
 701                           s->dev.qdev.info->name, s->dev.qdev.id, s);
 702     return 0;
 703 }
 704
 705 static void qdev_open_eth_reset(DeviceState *dev)
 706 {
 707     OpenEthState *d = DO_UPCAST(OpenEthState, dev.qdev, dev);
 708     open_eth_reset(d);
 709 }
 710
 711 static SysBusDeviceInfo open_eth_info = {
 712     .qdev.name  = "open_eth",
 713     .qdev.desc  = "Opencores 10/100 Mbit Ethernet",
 714     .qdev.size  = sizeof(OpenEthState),
 715     .qdev.reset = qdev_open_eth_reset,
 716     .init       = sysbus_open_eth_init,
 717     .qdev.props = (Property[]) {
 718         DEFINE_NIC_PROPERTIES(OpenEthState, conf),
 719         DEFINE_PROP_END_OF_LIST(),
 720     }
 721 };
 722
 723 static void open_eth_register_devices(void)
 724 {
 725     sysbus_register_withprop(&open_eth_info);
 726 }
 727
 728 device_init(open_eth_register_devices)