target-arm/cpu.c

   1 /*
   2  * QEMU ARM CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20
  21 #include "cpu.h"
  22 #include "internals.h"
  23 #include "qemu-common.h"
  24 #include "hw/qdev-properties.h"
  25 #include "qapi/qmp/qerror.h"
  26 #if !defined(CONFIG_USER_ONLY)
  27 #include "hw/loader.h"
  28 #endif
  29 #include "hw/arm/arm.h"
  30 #include "sysemu/sysemu.h"
  31 #include "sysemu/kvm.h"
  32 #include "kvm_arm.h"
  33
  34 static void arm_cpu_set_pc(CPUState *cs, vaddr value)
  35 {
  36     ARMCPU *cpu = ARM_CPU(cs);
  37
  38     cpu->env.regs[15] = value;
  39 }
  40
  41 static bool arm_cpu_has_work(CPUState *cs)
  42 {
  43     ARMCPU *cpu = ARM_CPU(cs);
  44
  45     return !cpu->powered_off
  46         && cs->interrupt_request &
  47         (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD
  48          | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ
  49          | CPU_INTERRUPT_EXITTB);
  50 }
  51
  52 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
  53 {
  54     /* Reset a single ARMCPRegInfo register */
  55     ARMCPRegInfo *ri = value;
  56     ARMCPU *cpu = opaque;
  57
  58     if (ri->type & ARM_CP_SPECIAL) {
  59         return;
  60     }
  61
  62     if (ri->resetfn) {
  63         ri->resetfn(&cpu->env, ri);
  64         return;
  65     }
  66
  67     /* A zero offset is never possible as it would be regs[0]
  68      * so we use it to indicate that reset is being handled elsewhere.
  69      * This is basically only used for fields in non-core coprocessors
  70      * (like the pxa2xx ones).
  71      */
  72     if (!ri->fieldoffset) {
  73         return;
  74     }
  75
  76     if (cpreg_field_is_64bit(ri)) {
  77         CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
  78     } else {
  79         CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
  80     }
  81 }
  82
  83 /* CPUClass::reset() */
  84 static void arm_cpu_reset(CPUState *s)
  85 {
  86     ARMCPU *cpu = ARM_CPU(s);
  87     ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
  88     CPUARMState *env = &cpu->env;
  89
  90     acc->parent_reset(s);
  91
  92     memset(env, 0, offsetof(CPUARMState, features));
  93     g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
  94     env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
  95     env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
  96     env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
  97     env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2;
  98
  99     cpu->powered_off = cpu->start_powered_off;
 100     s->halted = cpu->start_powered_off;
 101
 102     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 103         env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
 104     }
 105
 106     if (arm_feature(env, ARM_FEATURE_AARCH64)) {
 107         /* 64 bit CPUs always start in 64 bit mode */
 108         env->aarch64 = 1;
 109 #if defined(CONFIG_USER_ONLY)
 110         env->pstate = PSTATE_MODE_EL0t;
 111         /* Userspace expects access to CTL_EL0 and the cache ops */
 112         env->cp15.c1_sys |= SCTLR_UCT | SCTLR_UCI;
 113         /* and to the FP/Neon instructions */
 114         env->cp15.c1_coproc = deposit64(env->cp15.c1_coproc, 20, 2, 3);
 115 #else
 116         env->pstate = PSTATE_MODE_EL1h;
 117         env->pc = cpu->rvbar;
 118 #endif
 119     } else {
 120 #if defined(CONFIG_USER_ONLY)
 121         /* Userspace expects access to cp10 and cp11 for FP/Neon */
 122         env->cp15.c1_coproc = deposit64(env->cp15.c1_coproc, 20, 4, 0xf);
 123 #endif
 124     }
 125
 126 #if defined(CONFIG_USER_ONLY)
 127     env->uncached_cpsr = ARM_CPU_MODE_USR;
 128     /* For user mode we must enable access to coprocessors */
 129     env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
 130     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 131         env->cp15.c15_cpar = 3;
 132     } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
 133         env->cp15.c15_cpar = 1;
 134     }
 135 #else
 136     /* SVC mode with interrupts disabled.  */
 137     env->uncached_cpsr = ARM_CPU_MODE_SVC;
 138     env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
 139     /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
 140      * clear at reset. Initial SP and PC are loaded from ROM.
 141      */
 142     if (IS_M(env)) {
 143         uint32_t initial_msp; /* Loaded from 0x0 */
 144         uint32_t initial_pc; /* Loaded from 0x4 */
 145         uint8_t *rom;
 146
 147         env->daif &= ~PSTATE_I;
 148         rom = rom_ptr(0);
 149         if (rom) {
 150             /* Address zero is covered by ROM which hasn't yet been
 151              * copied into physical memory.
 152              */
 153             initial_msp = ldl_p(rom);
 154             initial_pc = ldl_p(rom + 4);
 155         } else {
 156             /* Address zero not covered by a ROM blob, or the ROM blob
 157              * is in non-modifiable memory and this is a second reset after
 158              * it got copied into memory. In the latter case, rom_ptr
 159              * will return a NULL pointer and we should use ldl_phys instead.
 160              */
 161             initial_msp = ldl_phys(s->as, 0);
 162             initial_pc = ldl_phys(s->as, 4);
 163         }
 164
 165         env->regs[13] = initial_msp & 0xFFFFFFFC;
 166         env->regs[15] = initial_pc & ~1;
 167         env->thumb = initial_pc & 1;
 168     }
 169
 170     if (env->cp15.c1_sys & SCTLR_V) {
 171         env->regs[15] = 0xFFFF0000;
 172     }
 173
 174     env->vfp.xregs[ARM_VFP_FPEXC] = 0;
 175 #endif
 176     set_flush_to_zero(1, &env->vfp.standard_fp_status);
 177     set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
 178     set_default_nan_mode(1, &env->vfp.standard_fp_status);
 179     set_float_detect_tininess(float_tininess_before_rounding,
 180                               &env->vfp.fp_status);
 181     set_float_detect_tininess(float_tininess_before_rounding,
 182                               &env->vfp.standard_fp_status);
 183     tlb_flush(s, 1);
 184
 185 #ifndef CONFIG_USER_ONLY
 186     if (kvm_enabled()) {
 187         kvm_arm_reset_vcpu(cpu);
 188     }
 189 #endif
 190
 191     hw_breakpoint_update_all(cpu);
 192     hw_watchpoint_update_all(cpu);
 193 }
 194
 195 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 196 {
 197     CPUClass *cc = CPU_GET_CLASS(cs);
 198     bool ret = false;
 199
 200     if (interrupt_request & CPU_INTERRUPT_FIQ
 201         && arm_excp_unmasked(cs, EXCP_FIQ)) {
 202         cs->exception_index = EXCP_FIQ;
 203         cc->do_interrupt(cs);
 204         ret = true;
 205     }
 206     /* ARMv7-M interrupt return works by loading a magic value
 207        into the PC.  On real hardware the load causes the
 208        return to occur.  The qemu implementation performs the
 209        jump normally, then does the exception return when the
 210        CPU tries to execute code at the magic address.
 211        This will cause the magic PC value to be pushed to
 212        the stack if an interrupt occurred at the wrong time.
 213        We avoid this by disabling interrupts when
 214        pc contains a magic address.  */
 215     if (interrupt_request & CPU_INTERRUPT_HARD
 216         && arm_excp_unmasked(cs, EXCP_IRQ)) {
 217         cs->exception_index = EXCP_IRQ;
 218         cc->do_interrupt(cs);
 219         ret = true;
 220     }
 221     if (interrupt_request & CPU_INTERRUPT_VIRQ
 222         && arm_excp_unmasked(cs, EXCP_VIRQ)) {
 223         cs->exception_index = EXCP_VIRQ;
 224         cc->do_interrupt(cs);
 225         ret = true;
 226     }
 227     if (interrupt_request & CPU_INTERRUPT_VFIQ
 228         && arm_excp_unmasked(cs, EXCP_VFIQ)) {
 229         cs->exception_index = EXCP_VFIQ;
 230         cc->do_interrupt(cs);
 231         ret = true;
 232     }
 233
 234     return ret;
 235 }
 236
 237 #ifndef CONFIG_USER_ONLY
 238 static void arm_cpu_set_irq(void *opaque, int irq, int level)
 239 {
 240     ARMCPU *cpu = opaque;
 241     CPUARMState *env = &cpu->env;
 242     CPUState *cs = CPU(cpu);
 243     static const int mask[] = {
 244         [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD,
 245         [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ,
 246         [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ,
 247         [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ
 248     };
 249
 250     switch (irq) {
 251     case ARM_CPU_VIRQ:
 252     case ARM_CPU_VFIQ:
 253         if (!arm_feature(env, ARM_FEATURE_EL2)) {
 254             hw_error("%s: Virtual interrupt line %d with no EL2 support\n",
 255                      __func__, irq);
 256         }
 257         /* fall through */
 258     case ARM_CPU_IRQ:
 259     case ARM_CPU_FIQ:
 260         if (level) {
 261             cpu_interrupt(cs, mask[irq]);
 262         } else {
 263             cpu_reset_interrupt(cs, mask[irq]);
 264         }
 265         break;
 266     default:
 267         hw_error("arm_cpu_set_irq: Bad interrupt line %d\n", irq);
 268     }
 269 }
 270
 271 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
 272 {
 273 #ifdef CONFIG_KVM
 274     ARMCPU *cpu = opaque;
 275     CPUState *cs = CPU(cpu);
 276     int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT;
 277
 278     switch (irq) {
 279     case ARM_CPU_IRQ:
 280         kvm_irq |= KVM_ARM_IRQ_CPU_IRQ;
 281         break;
 282     case ARM_CPU_FIQ:
 283         kvm_irq |= KVM_ARM_IRQ_CPU_FIQ;
 284         break;
 285     default:
 286         hw_error("arm_cpu_kvm_set_irq: Bad interrupt line %d\n", irq);
 287     }
 288     kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT;
 289     kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0);
 290 #endif
 291 }
 292 #endif
 293
 294 static inline void set_feature(CPUARMState *env, int feature)
 295 {
 296     env->features |= 1ULL << feature;
 297 }
 298
 299 static void arm_cpu_initfn(Object *obj)
 300 {
 301     CPUState *cs = CPU(obj);
 302     ARMCPU *cpu = ARM_CPU(obj);
 303     static bool inited;
 304
 305     cs->env_ptr = &cpu->env;
 306     cpu_exec_init(&cpu->env);
 307     cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
 308                                          g_free, g_free);
 309
 310 #ifndef CONFIG_USER_ONLY
 311     /* Our inbound IRQ and FIQ lines */
 312     if (kvm_enabled()) {
 313         /* VIRQ and VFIQ are unused with KVM but we add them to maintain
 314          * the same interface as non-KVM CPUs.
 315          */
 316         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4);
 317     } else {
 318         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4);
 319     }
 320
 321     cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 322                                                 arm_gt_ptimer_cb, cpu);
 323     cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 324                                                 arm_gt_vtimer_cb, cpu);
 325     qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
 326                        ARRAY_SIZE(cpu->gt_timer_outputs));
 327 #endif
 328
 329     /* DTB consumers generally don't in fact care what the 'compatible'
 330      * string is, so always provide some string and trust that a hypothetical
 331      * picky DTB consumer will also provide a helpful error message.
 332      */
 333     cpu->dtb_compatible = "qemu,unknown";
 334     cpu->psci_version = 1; /* By default assume PSCI v0.1 */
 335     cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
 336
 337     if (tcg_enabled() && !inited) {
 338         inited = true;
 339         arm_translate_init();
 340     }
 341 }
 342
 343 static Property arm_cpu_reset_cbar_property =
 344             DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0);
 345
 346 static Property arm_cpu_reset_hivecs_property =
 347             DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
 348
 349 static Property arm_cpu_rvbar_property =
 350             DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0);
 351
 352 static void arm_cpu_post_init(Object *obj)
 353 {
 354     ARMCPU *cpu = ARM_CPU(obj);
 355
 356     if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
 357         arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
 358         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property,
 359                                  &error_abort);
 360     }
 361
 362     if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
 363         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property,
 364                                  &error_abort);
 365     }
 366
 367     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
 368         qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property,
 369                                  &error_abort);
 370     }
 371 }
 372
 373 static void arm_cpu_finalizefn(Object *obj)
 374 {
 375     ARMCPU *cpu = ARM_CPU(obj);
 376     g_hash_table_destroy(cpu->cp_regs);
 377 }
 378
 379 static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
 380 {
 381     CPUState *cs = CPU(dev);
 382     ARMCPU *cpu = ARM_CPU(dev);
 383     ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
 384     CPUARMState *env = &cpu->env;
 385
 386     /* Some features automatically imply others: */
 387     if (arm_feature(env, ARM_FEATURE_V8)) {
 388         set_feature(env, ARM_FEATURE_V7);
 389         set_feature(env, ARM_FEATURE_ARM_DIV);
 390         set_feature(env, ARM_FEATURE_LPAE);
 391     }
 392     if (arm_feature(env, ARM_FEATURE_V7)) {
 393         set_feature(env, ARM_FEATURE_VAPA);
 394         set_feature(env, ARM_FEATURE_THUMB2);
 395         set_feature(env, ARM_FEATURE_MPIDR);
 396         if (!arm_feature(env, ARM_FEATURE_M)) {
 397             set_feature(env, ARM_FEATURE_V6K);
 398         } else {
 399             set_feature(env, ARM_FEATURE_V6);
 400         }
 401     }
 402     if (arm_feature(env, ARM_FEATURE_V6K)) {
 403         set_feature(env, ARM_FEATURE_V6);
 404         set_feature(env, ARM_FEATURE_MVFR);
 405     }
 406     if (arm_feature(env, ARM_FEATURE_V6)) {
 407         set_feature(env, ARM_FEATURE_V5);
 408         if (!arm_feature(env, ARM_FEATURE_M)) {
 409             set_feature(env, ARM_FEATURE_AUXCR);
 410         }
 411     }
 412     if (arm_feature(env, ARM_FEATURE_V5)) {
 413         set_feature(env, ARM_FEATURE_V4T);
 414     }
 415     if (arm_feature(env, ARM_FEATURE_M)) {
 416         set_feature(env, ARM_FEATURE_THUMB_DIV);
 417     }
 418     if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
 419         set_feature(env, ARM_FEATURE_THUMB_DIV);
 420     }
 421     if (arm_feature(env, ARM_FEATURE_VFP4)) {
 422         set_feature(env, ARM_FEATURE_VFP3);
 423         set_feature(env, ARM_FEATURE_VFP_FP16);
 424     }
 425     if (arm_feature(env, ARM_FEATURE_VFP3)) {
 426         set_feature(env, ARM_FEATURE_VFP);
 427     }
 428     if (arm_feature(env, ARM_FEATURE_LPAE)) {
 429         set_feature(env, ARM_FEATURE_V7MP);
 430         set_feature(env, ARM_FEATURE_PXN);
 431     }
 432     if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
 433         set_feature(env, ARM_FEATURE_CBAR);
 434     }
 435
 436     if (cpu->reset_hivecs) {
 437             cpu->reset_sctlr |= (1 << 13);
 438     }
 439
 440     register_cp_regs_for_features(cpu);
 441     arm_cpu_register_gdb_regs_for_features(cpu);
 442
 443     init_cpreg_list(cpu);
 444
 445     qemu_init_vcpu(cs);
 446     cpu_reset(cs);
 447
 448     acc->parent_realize(dev, errp);
 449 }
 450
 451 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
 452 {
 453     ObjectClass *oc;
 454     char *typename;
 455
 456     if (!cpu_model) {
 457         return NULL;
 458     }
 459
 460     typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpu_model);
 461     oc = object_class_by_name(typename);
 462     g_free(typename);
 463     if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
 464         object_class_is_abstract(oc)) {
 465         return NULL;
 466     }
 467     return oc;
 468 }
 469
 470 /* CPU models. These are not needed for the AArch64 linux-user build. */
 471 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 472
 473 static void arm926_initfn(Object *obj)
 474 {
 475     ARMCPU *cpu = ARM_CPU(obj);
 476
 477     cpu->dtb_compatible = "arm,arm926";
 478     set_feature(&cpu->env, ARM_FEATURE_V5);
 479     set_feature(&cpu->env, ARM_FEATURE_VFP);
 480     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 481     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 482     cpu->midr = 0x41069265;
 483     cpu->reset_fpsid = 0x41011090;
 484     cpu->ctr = 0x1dd20d2;
 485     cpu->reset_sctlr = 0x00090078;
 486 }
 487
 488 static void arm946_initfn(Object *obj)
 489 {
 490     ARMCPU *cpu = ARM_CPU(obj);
 491
 492     cpu->dtb_compatible = "arm,arm946";
 493     set_feature(&cpu->env, ARM_FEATURE_V5);
 494     set_feature(&cpu->env, ARM_FEATURE_MPU);
 495     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 496     cpu->midr = 0x41059461;
 497     cpu->ctr = 0x0f004006;
 498     cpu->reset_sctlr = 0x00000078;
 499 }
 500
 501 static void arm1026_initfn(Object *obj)
 502 {
 503     ARMCPU *cpu = ARM_CPU(obj);
 504
 505     cpu->dtb_compatible = "arm,arm1026";
 506     set_feature(&cpu->env, ARM_FEATURE_V5);
 507     set_feature(&cpu->env, ARM_FEATURE_VFP);
 508     set_feature(&cpu->env, ARM_FEATURE_AUXCR);
 509     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 510     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 511     cpu->midr = 0x4106a262;
 512     cpu->reset_fpsid = 0x410110a0;
 513     cpu->ctr = 0x1dd20d2;
 514     cpu->reset_sctlr = 0x00090078;
 515     cpu->reset_auxcr = 1;
 516     {
 517         /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
 518         ARMCPRegInfo ifar = {
 519             .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 520             .access = PL1_RW,
 521             .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el[1]),
 522             .resetvalue = 0
 523         };
 524         define_one_arm_cp_reg(cpu, &ifar);
 525     }
 526 }
 527
 528 static void arm1136_r2_initfn(Object *obj)
 529 {
 530     ARMCPU *cpu = ARM_CPU(obj);
 531     /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
 532      * older core than plain "arm1136". In particular this does not
 533      * have the v6K features.
 534      * These ID register values are correct for 1136 but may be wrong
 535      * for 1136_r2 (in particular r0p2 does not actually implement most
 536      * of the ID registers).
 537      */
 538
 539     cpu->dtb_compatible = "arm,arm1136";
 540     set_feature(&cpu->env, ARM_FEATURE_V6);
 541     set_feature(&cpu->env, ARM_FEATURE_VFP);
 542     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 543     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 544     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 545     cpu->midr = 0x4107b362;
 546     cpu->reset_fpsid = 0x410120b4;
 547     cpu->mvfr0 = 0x11111111;
 548     cpu->mvfr1 = 0x00000000;
 549     cpu->ctr = 0x1dd20d2;
 550     cpu->reset_sctlr = 0x00050078;
 551     cpu->id_pfr0 = 0x111;
 552     cpu->id_pfr1 = 0x1;
 553     cpu->id_dfr0 = 0x2;
 554     cpu->id_afr0 = 0x3;
 555     cpu->id_mmfr0 = 0x01130003;
 556     cpu->id_mmfr1 = 0x10030302;
 557     cpu->id_mmfr2 = 0x01222110;
 558     cpu->id_isar0 = 0x00140011;
 559     cpu->id_isar1 = 0x12002111;
 560     cpu->id_isar2 = 0x11231111;
 561     cpu->id_isar3 = 0x01102131;
 562     cpu->id_isar4 = 0x141;
 563     cpu->reset_auxcr = 7;
 564 }
 565
 566 static void arm1136_initfn(Object *obj)
 567 {
 568     ARMCPU *cpu = ARM_CPU(obj);
 569
 570     cpu->dtb_compatible = "arm,arm1136";
 571     set_feature(&cpu->env, ARM_FEATURE_V6K);
 572     set_feature(&cpu->env, ARM_FEATURE_V6);
 573     set_feature(&cpu->env, ARM_FEATURE_VFP);
 574     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 575     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 576     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 577     cpu->midr = 0x4117b363;
 578     cpu->reset_fpsid = 0x410120b4;
 579     cpu->mvfr0 = 0x11111111;
 580     cpu->mvfr1 = 0x00000000;
 581     cpu->ctr = 0x1dd20d2;
 582     cpu->reset_sctlr = 0x00050078;
 583     cpu->id_pfr0 = 0x111;
 584     cpu->id_pfr1 = 0x1;
 585     cpu->id_dfr0 = 0x2;
 586     cpu->id_afr0 = 0x3;
 587     cpu->id_mmfr0 = 0x01130003;
 588     cpu->id_mmfr1 = 0x10030302;
 589     cpu->id_mmfr2 = 0x01222110;
 590     cpu->id_isar0 = 0x00140011;
 591     cpu->id_isar1 = 0x12002111;
 592     cpu->id_isar2 = 0x11231111;
 593     cpu->id_isar3 = 0x01102131;
 594     cpu->id_isar4 = 0x141;
 595     cpu->reset_auxcr = 7;
 596 }
 597
 598 static void arm1176_initfn(Object *obj)
 599 {
 600     ARMCPU *cpu = ARM_CPU(obj);
 601
 602     cpu->dtb_compatible = "arm,arm1176";
 603     set_feature(&cpu->env, ARM_FEATURE_V6K);
 604     set_feature(&cpu->env, ARM_FEATURE_VFP);
 605     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 606     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 607     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 608     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 609     cpu->midr = 0x410fb767;
 610     cpu->reset_fpsid = 0x410120b5;
 611     cpu->mvfr0 = 0x11111111;
 612     cpu->mvfr1 = 0x00000000;
 613     cpu->ctr = 0x1dd20d2;
 614     cpu->reset_sctlr = 0x00050078;
 615     cpu->id_pfr0 = 0x111;
 616     cpu->id_pfr1 = 0x11;
 617     cpu->id_dfr0 = 0x33;
 618     cpu->id_afr0 = 0;
 619     cpu->id_mmfr0 = 0x01130003;
 620     cpu->id_mmfr1 = 0x10030302;
 621     cpu->id_mmfr2 = 0x01222100;
 622     cpu->id_isar0 = 0x0140011;
 623     cpu->id_isar1 = 0x12002111;
 624     cpu->id_isar2 = 0x11231121;
 625     cpu->id_isar3 = 0x01102131;
 626     cpu->id_isar4 = 0x01141;
 627     cpu->reset_auxcr = 7;
 628 }
 629
 630 static void arm11mpcore_initfn(Object *obj)
 631 {
 632     ARMCPU *cpu = ARM_CPU(obj);
 633
 634     cpu->dtb_compatible = "arm,arm11mpcore";
 635     set_feature(&cpu->env, ARM_FEATURE_V6K);
 636     set_feature(&cpu->env, ARM_FEATURE_VFP);
 637     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 638     set_feature(&cpu->env, ARM_FEATURE_MPIDR);
 639     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 640     cpu->midr = 0x410fb022;
 641     cpu->reset_fpsid = 0x410120b4;
 642     cpu->mvfr0 = 0x11111111;
 643     cpu->mvfr1 = 0x00000000;
 644     cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
 645     cpu->id_pfr0 = 0x111;
 646     cpu->id_pfr1 = 0x1;
 647     cpu->id_dfr0 = 0;
 648     cpu->id_afr0 = 0x2;
 649     cpu->id_mmfr0 = 0x01100103;
 650     cpu->id_mmfr1 = 0x10020302;
 651     cpu->id_mmfr2 = 0x01222000;
 652     cpu->id_isar0 = 0x00100011;
 653     cpu->id_isar1 = 0x12002111;
 654     cpu->id_isar2 = 0x11221011;
 655     cpu->id_isar3 = 0x01102131;
 656     cpu->id_isar4 = 0x141;
 657     cpu->reset_auxcr = 1;
 658 }
 659
 660 static void cortex_m3_initfn(Object *obj)
 661 {
 662     ARMCPU *cpu = ARM_CPU(obj);
 663     set_feature(&cpu->env, ARM_FEATURE_V7);
 664     set_feature(&cpu->env, ARM_FEATURE_M);
 665     cpu->midr = 0x410fc231;
 666 }
 667
 668 static void arm_v7m_class_init(ObjectClass *oc, void *data)
 669 {
 670 #ifndef CONFIG_USER_ONLY
 671     CPUClass *cc = CPU_CLASS(oc);
 672
 673     cc->do_interrupt = arm_v7m_cpu_do_interrupt;
 674 #endif
 675 }
 676
 677 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
 678     { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
 679       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 680     { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 681       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 682     REGINFO_SENTINEL
 683 };
 684
 685 static void cortex_a8_initfn(Object *obj)
 686 {
 687     ARMCPU *cpu = ARM_CPU(obj);
 688
 689     cpu->dtb_compatible = "arm,cortex-a8";
 690     set_feature(&cpu->env, ARM_FEATURE_V7);
 691     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 692     set_feature(&cpu->env, ARM_FEATURE_NEON);
 693     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 694     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 695     cpu->midr = 0x410fc080;
 696     cpu->reset_fpsid = 0x410330c0;
 697     cpu->mvfr0 = 0x11110222;
 698     cpu->mvfr1 = 0x00011100;
 699     cpu->ctr = 0x82048004;
 700     cpu->reset_sctlr = 0x00c50078;
 701     cpu->id_pfr0 = 0x1031;
 702     cpu->id_pfr1 = 0x11;
 703     cpu->id_dfr0 = 0x400;
 704     cpu->id_afr0 = 0;
 705     cpu->id_mmfr0 = 0x31100003;
 706     cpu->id_mmfr1 = 0x20000000;
 707     cpu->id_mmfr2 = 0x01202000;
 708     cpu->id_mmfr3 = 0x11;
 709     cpu->id_isar0 = 0x00101111;
 710     cpu->id_isar1 = 0x12112111;
 711     cpu->id_isar2 = 0x21232031;
 712     cpu->id_isar3 = 0x11112131;
 713     cpu->id_isar4 = 0x00111142;
 714     cpu->dbgdidr = 0x15141000;
 715     cpu->clidr = (1 << 27) | (2 << 24) | 3;
 716     cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
 717     cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
 718     cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
 719     cpu->reset_auxcr = 2;
 720     define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
 721 }
 722
 723 static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
 724     /* power_control should be set to maximum latency. Again,
 725      * default to 0 and set by private hook
 726      */
 727     { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
 728       .access = PL1_RW, .resetvalue = 0,
 729       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
 730     { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
 731       .access = PL1_RW, .resetvalue = 0,
 732       .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
 733     { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
 734       .access = PL1_RW, .resetvalue = 0,
 735       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
 736     { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
 737       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 738     /* TLB lockdown control */
 739     { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
 740       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 741     { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
 742       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 743     { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
 744       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 745     { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
 746       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 747     { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
 748       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 749     REGINFO_SENTINEL
 750 };
 751
 752 static void cortex_a9_initfn(Object *obj)
 753 {
 754     ARMCPU *cpu = ARM_CPU(obj);
 755
 756     cpu->dtb_compatible = "arm,cortex-a9";
 757     set_feature(&cpu->env, ARM_FEATURE_V7);
 758     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 759     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
 760     set_feature(&cpu->env, ARM_FEATURE_NEON);
 761     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 762     /* Note that A9 supports the MP extensions even for
 763      * A9UP and single-core A9MP (which are both different
 764      * and valid configurations; we don't model A9UP).
 765      */
 766     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 767     set_feature(&cpu->env, ARM_FEATURE_CBAR);
 768     cpu->midr = 0x410fc090;
 769     cpu->reset_fpsid = 0x41033090;
 770     cpu->mvfr0 = 0x11110222;
 771     cpu->mvfr1 = 0x01111111;
 772     cpu->ctr = 0x80038003;
 773     cpu->reset_sctlr = 0x00c50078;
 774     cpu->id_pfr0 = 0x1031;
 775     cpu->id_pfr1 = 0x11;
 776     cpu->id_dfr0 = 0x000;
 777     cpu->id_afr0 = 0;
 778     cpu->id_mmfr0 = 0x00100103;
 779     cpu->id_mmfr1 = 0x20000000;
 780     cpu->id_mmfr2 = 0x01230000;
 781     cpu->id_mmfr3 = 0x00002111;
 782     cpu->id_isar0 = 0x00101111;
 783     cpu->id_isar1 = 0x13112111;
 784     cpu->id_isar2 = 0x21232041;
 785     cpu->id_isar3 = 0x11112131;
 786     cpu->id_isar4 = 0x00111142;
 787     cpu->dbgdidr = 0x35141000;
 788     cpu->clidr = (1 << 27) | (1 << 24) | 3;
 789     cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
 790     cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
 791     define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
 792 }
 793
 794 #ifndef CONFIG_USER_ONLY
 795 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 796 {
 797     /* Linux wants the number of processors from here.
 798      * Might as well set the interrupt-controller bit too.
 799      */
 800     return ((smp_cpus - 1) << 24) | (1 << 23);
 801 }
 802 #endif
 803
 804 static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
 805 #ifndef CONFIG_USER_ONLY
 806     { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 807       .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
 808       .writefn = arm_cp_write_ignore, },
 809 #endif
 810     { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
 811       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 812     REGINFO_SENTINEL
 813 };
 814
 815 static void cortex_a15_initfn(Object *obj)
 816 {
 817     ARMCPU *cpu = ARM_CPU(obj);
 818
 819     cpu->dtb_compatible = "arm,cortex-a15";
 820     set_feature(&cpu->env, ARM_FEATURE_V7);
 821     set_feature(&cpu->env, ARM_FEATURE_VFP4);
 822     set_feature(&cpu->env, ARM_FEATURE_NEON);
 823     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 824     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
 825     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
 826     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 827     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
 828     set_feature(&cpu->env, ARM_FEATURE_LPAE);
 829     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
 830     cpu->midr = 0x412fc0f1;
 831     cpu->reset_fpsid = 0x410430f0;
 832     cpu->mvfr0 = 0x10110222;
 833     cpu->mvfr1 = 0x11111111;
 834     cpu->ctr = 0x8444c004;
 835     cpu->reset_sctlr = 0x00c50078;
 836     cpu->id_pfr0 = 0x00001131;
 837     cpu->id_pfr1 = 0x00011011;
 838     cpu->id_dfr0 = 0x02010555;
 839     cpu->id_afr0 = 0x00000000;
 840     cpu->id_mmfr0 = 0x10201105;
 841     cpu->id_mmfr1 = 0x20000000;
 842     cpu->id_mmfr2 = 0x01240000;
 843     cpu->id_mmfr3 = 0x02102211;
 844     cpu->id_isar0 = 0x02101110;
 845     cpu->id_isar1 = 0x13112111;
 846     cpu->id_isar2 = 0x21232041;
 847     cpu->id_isar3 = 0x11112131;
 848     cpu->id_isar4 = 0x10011142;
 849     cpu->dbgdidr = 0x3515f021;
 850     cpu->clidr = 0x0a200023;
 851     cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
 852     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
 853     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
 854     define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
 855 }
 856
 857 static void ti925t_initfn(Object *obj)
 858 {
 859     ARMCPU *cpu = ARM_CPU(obj);
 860     set_feature(&cpu->env, ARM_FEATURE_V4T);
 861     set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
 862     cpu->midr = ARM_CPUID_TI925T;
 863     cpu->ctr = 0x5109149;
 864     cpu->reset_sctlr = 0x00000070;
 865 }
 866
 867 static void sa1100_initfn(Object *obj)
 868 {
 869     ARMCPU *cpu = ARM_CPU(obj);
 870
 871     cpu->dtb_compatible = "intel,sa1100";
 872     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 873     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 874     cpu->midr = 0x4401A11B;
 875     cpu->reset_sctlr = 0x00000070;
 876 }
 877
 878 static void sa1110_initfn(Object *obj)
 879 {
 880     ARMCPU *cpu = ARM_CPU(obj);
 881     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
 882     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 883     cpu->midr = 0x6901B119;
 884     cpu->reset_sctlr = 0x00000070;
 885 }
 886
 887 static void pxa250_initfn(Object *obj)
 888 {
 889     ARMCPU *cpu = ARM_CPU(obj);
 890
 891     cpu->dtb_compatible = "marvell,xscale";
 892     set_feature(&cpu->env, ARM_FEATURE_V5);
 893     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 894     cpu->midr = 0x69052100;
 895     cpu->ctr = 0xd172172;
 896     cpu->reset_sctlr = 0x00000078;
 897 }
 898
 899 static void pxa255_initfn(Object *obj)
 900 {
 901     ARMCPU *cpu = ARM_CPU(obj);
 902
 903     cpu->dtb_compatible = "marvell,xscale";
 904     set_feature(&cpu->env, ARM_FEATURE_V5);
 905     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 906     cpu->midr = 0x69052d00;
 907     cpu->ctr = 0xd172172;
 908     cpu->reset_sctlr = 0x00000078;
 909 }
 910
 911 static void pxa260_initfn(Object *obj)
 912 {
 913     ARMCPU *cpu = ARM_CPU(obj);
 914
 915     cpu->dtb_compatible = "marvell,xscale";
 916     set_feature(&cpu->env, ARM_FEATURE_V5);
 917     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 918     cpu->midr = 0x69052903;
 919     cpu->ctr = 0xd172172;
 920     cpu->reset_sctlr = 0x00000078;
 921 }
 922
 923 static void pxa261_initfn(Object *obj)
 924 {
 925     ARMCPU *cpu = ARM_CPU(obj);
 926
 927     cpu->dtb_compatible = "marvell,xscale";
 928     set_feature(&cpu->env, ARM_FEATURE_V5);
 929     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 930     cpu->midr = 0x69052d05;
 931     cpu->ctr = 0xd172172;
 932     cpu->reset_sctlr = 0x00000078;
 933 }
 934
 935 static void pxa262_initfn(Object *obj)
 936 {
 937     ARMCPU *cpu = ARM_CPU(obj);
 938
 939     cpu->dtb_compatible = "marvell,xscale";
 940     set_feature(&cpu->env, ARM_FEATURE_V5);
 941     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 942     cpu->midr = 0x69052d06;
 943     cpu->ctr = 0xd172172;
 944     cpu->reset_sctlr = 0x00000078;
 945 }
 946
 947 static void pxa270a0_initfn(Object *obj)
 948 {
 949     ARMCPU *cpu = ARM_CPU(obj);
 950
 951     cpu->dtb_compatible = "marvell,xscale";
 952     set_feature(&cpu->env, ARM_FEATURE_V5);
 953     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 954     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 955     cpu->midr = 0x69054110;
 956     cpu->ctr = 0xd172172;
 957     cpu->reset_sctlr = 0x00000078;
 958 }
 959
 960 static void pxa270a1_initfn(Object *obj)
 961 {
 962     ARMCPU *cpu = ARM_CPU(obj);
 963
 964     cpu->dtb_compatible = "marvell,xscale";
 965     set_feature(&cpu->env, ARM_FEATURE_V5);
 966     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 967     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 968     cpu->midr = 0x69054111;
 969     cpu->ctr = 0xd172172;
 970     cpu->reset_sctlr = 0x00000078;
 971 }
 972
 973 static void pxa270b0_initfn(Object *obj)
 974 {
 975     ARMCPU *cpu = ARM_CPU(obj);
 976
 977     cpu->dtb_compatible = "marvell,xscale";
 978     set_feature(&cpu->env, ARM_FEATURE_V5);
 979     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 980     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 981     cpu->midr = 0x69054112;
 982     cpu->ctr = 0xd172172;
 983     cpu->reset_sctlr = 0x00000078;
 984 }
 985
 986 static void pxa270b1_initfn(Object *obj)
 987 {
 988     ARMCPU *cpu = ARM_CPU(obj);
 989
 990     cpu->dtb_compatible = "marvell,xscale";
 991     set_feature(&cpu->env, ARM_FEATURE_V5);
 992     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
 993     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
 994     cpu->midr = 0x69054113;
 995     cpu->ctr = 0xd172172;
 996     cpu->reset_sctlr = 0x00000078;
 997 }
 998
 999 static void pxa270c0_initfn(Object *obj)
1000 {
1001     ARMCPU *cpu = ARM_CPU(obj);
1002
1003     cpu->dtb_compatible = "marvell,xscale";
1004     set_feature(&cpu->env, ARM_FEATURE_V5);
1005     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1006     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1007     cpu->midr = 0x69054114;
1008     cpu->ctr = 0xd172172;
1009     cpu->reset_sctlr = 0x00000078;
1010 }
1011
1012 static void pxa270c5_initfn(Object *obj)
1013 {
1014     ARMCPU *cpu = ARM_CPU(obj);
1015
1016     cpu->dtb_compatible = "marvell,xscale";
1017     set_feature(&cpu->env, ARM_FEATURE_V5);
1018     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1019     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1020     cpu->midr = 0x69054117;
1021     cpu->ctr = 0xd172172;
1022     cpu->reset_sctlr = 0x00000078;
1023 }
1024
1025 #ifdef CONFIG_USER_ONLY
1026 static void arm_any_initfn(Object *obj)
1027 {
1028     ARMCPU *cpu = ARM_CPU(obj);
1029     set_feature(&cpu->env, ARM_FEATURE_V8);
1030     set_feature(&cpu->env, ARM_FEATURE_VFP4);
1031     set_feature(&cpu->env, ARM_FEATURE_NEON);
1032     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1033     set_feature(&cpu->env, ARM_FEATURE_V8_AES);
1034     set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
1035     set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
1036     set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
1037     set_feature(&cpu->env, ARM_FEATURE_CRC);
1038     cpu->midr = 0xffffffff;
1039 }
1040 #endif
1041
1042 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
1043
1044 typedef struct ARMCPUInfo {
1045     const char *name;
1046     void (*initfn)(Object *obj);
1047     void (*class_init)(ObjectClass *oc, void *data);
1048 } ARMCPUInfo;
1049
1050 static const ARMCPUInfo arm_cpus[] = {
1051 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1052     { .name = "arm926",      .initfn = arm926_initfn },
1053     { .name = "arm946",      .initfn = arm946_initfn },
1054     { .name = "arm1026",     .initfn = arm1026_initfn },
1055     /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
1056      * older core than plain "arm1136". In particular this does not
1057      * have the v6K features.
1058      */
1059     { .name = "arm1136-r2",  .initfn = arm1136_r2_initfn },
1060     { .name = "arm1136",     .initfn = arm1136_initfn },
1061     { .name = "arm1176",     .initfn = arm1176_initfn },
1062     { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
1063     { .name = "cortex-m3",   .initfn = cortex_m3_initfn,
1064                              .class_init = arm_v7m_class_init },
1065     { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
1066     { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
1067     { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
1068     { .name = "ti925t",      .initfn = ti925t_initfn },
1069     { .name = "sa1100",      .initfn = sa1100_initfn },
1070     { .name = "sa1110",      .initfn = sa1110_initfn },
1071     { .name = "pxa250",      .initfn = pxa250_initfn },
1072     { .name = "pxa255",      .initfn = pxa255_initfn },
1073     { .name = "pxa260",      .initfn = pxa260_initfn },
1074     { .name = "pxa261",      .initfn = pxa261_initfn },
1075     { .name = "pxa262",      .initfn = pxa262_initfn },
1076     /* "pxa270" is an alias for "pxa270-a0" */
1077     { .name = "pxa270",      .initfn = pxa270a0_initfn },
1078     { .name = "pxa270-a0",   .initfn = pxa270a0_initfn },
1079     { .name = "pxa270-a1",   .initfn = pxa270a1_initfn },
1080     { .name = "pxa270-b0",   .initfn = pxa270b0_initfn },
1081     { .name = "pxa270-b1",   .initfn = pxa270b1_initfn },
1082     { .name = "pxa270-c0",   .initfn = pxa270c0_initfn },
1083     { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
1084 #ifdef CONFIG_USER_ONLY
1085     { .name = "any",         .initfn = arm_any_initfn },
1086 #endif
1087 #endif
1088     { .name = NULL }
1089 };
1090
1091 static Property arm_cpu_properties[] = {
1092     DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),
1093     DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0),
1094     DEFINE_PROP_END_OF_LIST()
1095 };
1096
1097 static void arm_cpu_class_init(ObjectClass *oc, void *data)
1098 {
1099     ARMCPUClass *acc = ARM_CPU_CLASS(oc);
1100     CPUClass *cc = CPU_CLASS(acc);
1101     DeviceClass *dc = DEVICE_CLASS(oc);
1102
1103     acc->parent_realize = dc->realize;
1104     dc->realize = arm_cpu_realizefn;
1105     dc->props = arm_cpu_properties;
1106
1107     acc->parent_reset = cc->reset;
1108     cc->reset = arm_cpu_reset;
1109
1110     cc->class_by_name = arm_cpu_class_by_name;
1111     cc->has_work = arm_cpu_has_work;
1112     cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
1113     cc->dump_state = arm_cpu_dump_state;
1114     cc->set_pc = arm_cpu_set_pc;
1115     cc->gdb_read_register = arm_cpu_gdb_read_register;
1116     cc->gdb_write_register = arm_cpu_gdb_write_register;
1117 #ifdef CONFIG_USER_ONLY
1118     cc->handle_mmu_fault = arm_cpu_handle_mmu_fault;
1119 #else
1120     cc->do_interrupt = arm_cpu_do_interrupt;
1121     cc->get_phys_page_debug = arm_cpu_get_phys_page_debug;
1122     cc->vmsd = &vmstate_arm_cpu;
1123 #endif
1124     cc->gdb_num_core_regs = 26;
1125     cc->gdb_core_xml_file = "arm-core.xml";
1126     cc->gdb_stop_before_watchpoint = true;
1127     cc->debug_excp_handler = arm_debug_excp_handler;
1128 }
1129
1130 static void cpu_register(const ARMCPUInfo *info)
1131 {
1132     TypeInfo type_info = {
1133         .parent = TYPE_ARM_CPU,
1134         .instance_size = sizeof(ARMCPU),
1135         .instance_init = info->initfn,
1136         .class_size = sizeof(ARMCPUClass),
1137         .class_init = info->class_init,
1138     };
1139
1140     type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
1141     type_register(&type_info);
1142     g_free((void *)type_info.name);
1143 }
1144
1145 static const TypeInfo arm_cpu_type_info = {
1146     .name = TYPE_ARM_CPU,
1147     .parent = TYPE_CPU,
1148     .instance_size = sizeof(ARMCPU),
1149     .instance_init = arm_cpu_initfn,
1150     .instance_post_init = arm_cpu_post_init,
1151     .instance_finalize = arm_cpu_finalizefn,
1152     .abstract = true,
1153     .class_size = sizeof(ARMCPUClass),
1154     .class_init = arm_cpu_class_init,
1155 };
1156
1157 static void arm_cpu_register_types(void)
1158 {
1159     const ARMCPUInfo *info = arm_cpus;
1160
1161     type_register_static(&arm_cpu_type_info);
1162
1163     while (info->name) {
1164         cpu_register(info);
1165         info++;
1166     }
1167 }
1168
1169 type_init(arm_cpu_register_types)